Activity

From 04/14/2013 to 05/13/2013

05/13/2013

11:32 pm Add PlanAhead image for ambpex5_sx50t_wishbone
http://ds-dev.ru/projects/ds-dma/wiki/AMBPEX5_SX50T_WISHBONE_PlanAhead_image
Dmitry Smekhov

05/12/2013

10:11 pm Language of issue tracker
Language of issue tracker is changed to English Dmitry Smekhov
09:46 pm Revision 22: correct wishbone_test_en.htm
Dmitry Smekhov
09:44 pm Bug #50 (Resolved): Changed DMA_REQUEST between TEST_CHECK and TEST_GENERATE
In the document:
TEST_CHECK - dmar0
TEST_GENERATE - dmar1
In the FPGA incorrect:
TEST_CHECK - dmar1
TEST_GEN...
Dmitry Smekhov
09:39 pm Development #46: Program WB_TEST
Change pexdrv, wb_test, pex_board Dmitry Smekhov
09:38 pm Bug #49 (Resolved): Computer crashes after the DMA stop
Program: ./wb_test test_gen.cfg
Stream: 0
Buffers: 8
Size of one block: 1 Mbyte
Cycle: No
Revision r20
Dmitry Smekhov
09:34 pm Development #47 (Resolved): ShowWishboneInfo - Read ID for TEST_CHECK, TEST_GEN
Dmitry Smekhov
09:22 pm Revision 21: debug ambpex5_sx50t_wishbone
Dmitry Smekhov
09:01 pm Revision 20: debug wb_test
Dmitry Smekhov
08:45 pm Revision 19
Dmitry Smekhov
04:06 am Development #48: AMBPEX5_SX50T_WISHBONE
Correct core64_pb_disp; Add signals *timeout_cnt*, *slave_timeout*
Dmitry Smekhov
04:04 am Development #47 (Confirmed): ShowWishboneInfo - Read ID for TEST_CHECK, TEST_GEN
Correct CL_WBPEX::wb_block_read()
Read BLOCK_ID from TEST_CHECK and TEST_GEN is ok.
Dmitry Smekhov
04:03 am Revision 18: read block_id - ok
Dmitry Smekhov

04/21/2013

01:27 am Revision 17: ambpex5_sx50t_wishbone - simulation is ok
Dmitry Smekhov
01:26 am Development #48: AMBPEX5_SX50T_WISHBONE
Simulation is ok. Revision r17
Dmitry Smekhov

04/20/2013

11:59 pm Added FAQ page on English
Added FAQ page on English: http://ds-dev.ru/projects/ds-dma/wiki/FAQ_en Dmitry Smekhov
03:18 am Revision 16: ambpex5_sx50t_wishbone - add files, don't work
Dmitry Smekhov
01:42 am Revision 15: Add ambpex5_sx50t_wishbone\src
Dmitry Smekhov
01:41 am Revision 14: Add project ambpex5_sx50t_wishbone
Dmitry Smekhov
01:35 am Development #48 (Confirmed): AMBPEX5_SX50T_WISHBONE
PCI Express controller for WISHBONE bus;
Virtex5 SX50T
PCI Express v1.1 x8
Dmitry Smekhov

04/17/2013

07:47 pm Development #47 (Resolved): ShowWishboneInfo - Read ID for TEST_CHECK, TEST_GEN
ShowWishboneInfo function should read the IDs of blocks TEST_CHECK, TEST_GEN Dmitry Smekhov
07:44 pm Development #46 (New): Program WB_TEST
Development of programs for design verification WISHBONE Dmitry Smekhov

04/14/2013

11:51 pm Support #45 (Resolved): Translate WISHBONE register description to English
Description is available here: http://src.ds-dev.ru/doc_en/wishbone/wishbone_test_en.htm
Revision: r13
Dmitry Smekhov
11:44 pm Revision 13: correct wishbone_test_en.htm
Dmitry Smekhov
11:42 pm Revision 12: Add description of project wishbone
Dmitry Smekhov
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