library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

	-- Add your library and packages declaration here ...

entity core64_interrupt_tb is
end core64_interrupt_tb;

architecture TB_ARCHITECTURE of core64_interrupt_tb is
	-- Component declaration of the tested unit
	component core64_interrupt
	port(
		rstp : in STD_LOGIC;
		clk : in STD_LOGIC;
		irq : in STD_LOGIC;
		cfg_command10 : in STD_LOGIC;
		cfg_interrupt : out STD_LOGIC;
		cfg_interrupt_assert : out STD_LOGIC;
		cfg_interrupt_rdy : in STD_LOGIC );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal rstp : STD_LOGIC;
	signal clk : STD_LOGIC:='0';
	signal irq : STD_LOGIC;
	signal cfg_command10 : STD_LOGIC;
	signal cfg_interrupt_rdy : STD_LOGIC;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal cfg_interrupt : STD_LOGIC;
	signal cfg_interrupt_assert : STD_LOGIC;

	-- Add your code here ...

begin						   
	
clk <= not clk	after 2 ns;
rstp <= '1', '0' after 100 ns;

	-- Unit Under Test port map
	UUT : core64_interrupt
		port map (
			rstp => rstp,
			clk => clk,
			irq => irq,
			cfg_command10 => cfg_command10,
			cfg_interrupt => cfg_interrupt,
			cfg_interrupt_assert => cfg_interrupt_assert,
			cfg_interrupt_rdy => cfg_interrupt_rdy
		);

irq <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 500 ns, '0' after 600 ns;	

cfg_command10 <= '0';
pr_interrupt_rdy: process begin

	cfg_interrupt_rdy <= '1';
	wait until rising_edge( clk ) and  cfg_interrupt='0';
	
	wait until rising_edge( clk );
	wait until rising_edge( clk );
	wait until rising_edge( clk );
	wait until rising_edge( clk );
	wait until rising_edge( clk );
	
	cfg_interrupt_rdy <= '0' after 1 ns;
	
	wait until rising_edge( clk );
	
	cfg_interrupt_rdy <= '1' after 1 ns;

	wait until rising_edge( clk );
	wait until rising_edge( clk );
	
end process;
	
end TB_ARCHITECTURE;


