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--
-- Title      : List of local and global libraries visible in Library Manager
-- Active-HDL : 8.3.2120.sp1.14.01.3884 
-- Workspace  : fmcpex6
-- Design     : ambpex5_v20_sx50t_core
-- Author     : Dmitry
-- Company    : NNS
-- Date       : 22.09.2011, 09:38:10
--
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Library                               | Mode  | Vendor   | Version                                          | Comment
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aldec                                 | RO    | ALDEC    | PROCEDURES FOR CALLING ASDB                      | FSDB, MATLAB, SIGNAL AGENT TASKS FROM THE VHDL CODE, RANDOM PACKAGE
exemplar                              | RO    | MENTOR   | MENTOR GRAPHICS PRECISION RTL SYNTHESIS 2009a.76 | EXEMPLAR VHDL LIBRARY.
sp605_lx45t_core                      | RW    | No Data  | No Data                                          | No Data
ieee_proposed                         | RO    | No Data  | No Data                                          | VHDL '93 compatible version of the proposed packages for the IEEE 1076-2008 standard
ml605_lx240t_core                     | RW    | No Data  | No Data                                          | No Data
pcie_v5_sim                           | RW    | No Data  | No Data                                          | No Data
pcie_v5_sim2                          | RW    | No Data  | No Data                                          | No Data
synopsys                              | RO    | No Data  | No Data                                          | Library containing packages with useful functions for std_logic types objects
std                                   | RO    | No Data  | No Data                                          | Standard VHDL library
vtl                                   | RO    | No Data  | No Data                                          | No Data
fmc103e_pcie_core                     | RW    | No Data  | No Data                                          | No Data
vital2000                             | RO    | No Data  | No Data                                          | Standard IEEE packages library
fmcpex6_sim                           | RW    | No Data  | No Data                                          | No Data
vl                                    | RO    | No Data  | No Data                                          | Standard Verilog library
cl_pcie_m2                            | RW    | No Data  | No Data                                          | No Data
assertions                            | RO    | No Data  | No Data                                          | No Data
vtl_dbg                               | RO    | No Data  | No Data                                          | No Data
ieee                                  | RO    | No Data  | No Data                                          | Standard IEEE packages library
ambpex5_v20_sx50t_core                | RW    | No Data  | No Data                                          | No Data
ambpex5_v20_sx50t_core_post_synthesis | RW    | No Data  | No Data                                          | No Data
synplify                              | RO    | SYNOPSYS | SYNOPSYS FPGA PRODUCTS E-2010.09                 | SYNPLIFY VHDL LIBRARY
ovi_simprim                           | RO    | XILINX   | XILINX ISE 13.1                                  | SIMPRIM VERILOG LIBRARY
simprim                               | RO    | XILINX   | XILINX ISE 13.1                                  | SIMPRIM VHDL LIBRARY
ovi_unimacro                          | RO    | XILINX   | XILINX ISE 13.1                                  | UNIMACRO VERILOG LIBRARY
ovi_cpld                              | RO    | XILINX   | XILINX ISE 13.1                                  | CPLD VERILOG LIBRARY
ovi_uni9000                           | RO    | XILINX   | XILINX ISE 13.1                                  | UNISIM VERILOG LIBRARY FOR XC9000 FAMILY
ovi_unisim                            | RW    | XILINX   | XILINX ISE 13.1                                  | UNISIM VERILOG LIBRARY
uni9000_ver                           | RO    | XILINX   | XILINX ISE 13.1                                  | UNISIM VERILOG LIBRARY FOR XC9000 FAMILY
secureip                              | RO    | XILINX   | XILINX ISE 13.1                                  | SECUREIP LIBRARY
simprims_ver                          | RO    | XILINX   | XILINX ISE 13.1                                  | SIMPRIM VERILOG LIBRARY
unimacro_ver                          | RO    | XILINX   | XILINX ISE 13.1                                  | UNIMACRO VERILOG LIBRARY
unisims_ver                           | RW    | XILINX   | XILINX ISE 13.1                                  | UNISIM VERILOG LIBRARY
unimacro                              | RO    | XILINX   | XILINX ISE 13.1                                  | UNIMACRO VHDL LIBRARY
unisim                                | RO    | XILINX   | XILINX ISE 13.1                                  | UNISIM VHDL LIBRARY
xilinxcorelib                         | RO    | XILINX   | XILINX ISE 13.1                                  | XILINXCORELIB VHDL LIBRARY
xilinxcorelib_ver                     | RO    | XILINX   | XILINX ISE 13.1                                  | XILINXCORELIB VERILOG LIBRARY
cpld                                  | RO    | XILINX   | XILINX ISE 13.1                                  | CPLD VHDL LIBRARY
ovi_xilinxcorelib                     | RO    | XILINX   | XILINX ISE 13.1                                  | XILINXCORELIB VERILOG LIBRARY
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