# //  ModelSim SE 10.0c Jul 21 2011 
# //
# //  Copyright 1991-2011 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# do setup_sim.do 
# Cre WORK lib (and del OLD, if exists) 
# Compile SRC: 
# ** Warning: ../src/pcie_src/pcie_core64_m1/source/pcie_blk_ll_arb.v(67): (vlog-2275) 'pcie_blk_ll_arb' already exists and will be overwritten.
# ** Warning: [4] ../src/pcie_src/pcie_core64_m1/pcie_fifo_ext/ctrl_ram_cmd_pb.vhd(179): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# Compile TEST ENV: 
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(30): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(31): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(34): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(86): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(87): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/sim/root_memory_pkg.vhd(88): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(99): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(100): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(101): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(102): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(103): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(104): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(105): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(106): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(107): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(108): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(109): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(110): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(111): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/test_interface.vhd(112): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(179): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(180): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/pcie_src/pcie_sim/dsport/pci_exp_usrapp_rx_m2.vhd(181): (vcom-1236) Shared variables must be of a protected type.
# ** Warning: ../src/testbench/test_pkg.vhd(86): (vcom-1236) Shared variables must be of a protected type.
# Start SIM: 
# vsim -L secureip -L unisims_ver -t ps -novopt work.stend_ambpex5_core_m2 glbl 
# Loading std.standard
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.stend_ambpex5_core_m2(stend_ambpex5_core_m2)
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_textio(body)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmd_sim_pkg(body)
# Loading ieee.std_logic_arith(body)
# Loading work.cmd_sim_pkg(body)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.block_pkg(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.block_pkg(body)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ambpex5_v20_sx50t_core_pkg
# Loading work.ambpex5_v20_sx50t_core_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.xilinx_pcie_rport_m2_pkg
# Loading work.xilinx_pcie_rport_m2_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.test_pkg(body)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_pkg(body)
# Loading work.trd_pkg(body)
# Loading work.test_pkg(body)
# Loading work.stend_ambpex5_core_m2(stend_ambpex5_core_m2)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.glbl
# Loading work.glbl
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ambpex5_v20_sx50t_core(ambpex5_v20_sx50t_core)
# Loading unisim.vcomponents
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.adm2_pkg
# Loading work.adm2_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_ambpex5_m5_pkg
# Loading work.cl_ambpex5_m5_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_main_v8_pkg
# Loading work.trd_main_v8_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_pio_std_v4_pkg
# Loading work.trd_pio_std_v4_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_admdio64_out_v4_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_chn_v3_pkg
# Loading work.cl_chn_v3_pkg
# Loading work.trd_admdio64_out_v4_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_admdio64_in_v6_pkg
# Loading work.trd_admdio64_in_v6_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_test_ctrl_m1_pkg
# Loading work.trd_test_ctrl_m1_pkg
# Loading work.ambpex5_v20_sx50t_core(ambpex5_v20_sx50t_core)
# Loading unisim.obuf_s_16(obuf_s_16_v)
# Loading unisim.obuf_f_16(obuf_f_16_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_ambpex5_m5(cl_ambpex5_m5)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pb_adm_ctrl_m2_pkg
# Loading work.pb_adm_ctrl_m2_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_blink_pkg
# Loading work.ctrl_blink_pkg
# Loading work.cl_ambpex5_m5(cl_ambpex5_m5)
# Loading unisim.bufg(bufg_v)
# Loading unisim.ibufds(ibufds_v)
# Loading ieee.vital_timing(body)
# Loading unisim.ibuf(ibuf_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_core64_m2(pcie_core64_m2)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_type_pkg
# Loading work.core64_type_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_core64_m1_pkg
# Loading work.pcie_core64_m1_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_pb_transaction_pkg
# Loading work.core64_pb_transaction_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.block_pe_main_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.host_pkg
# Loading work.host_pkg
# Loading work.block_pe_main_pkg
# Loading work.pcie_core64_m2(pcie_core64_m2)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_core64_m1(pcie_core64_m1)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_rx_engine_pkg
# Loading work.core64_rx_engine_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_tx_engine_pkg
# Loading work.core64_tx_engine_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_reg_access_pkg
# Loading work.core64_reg_access_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_pb_disp_pkg
# Loading work.core64_pb_disp_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.block_pe_fifo_ext_pkg
# Loading work.block_pe_fifo_ext_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_interrupt_pkg
# Loading work.core64_interrupt_pkg
# Loading work.pcie_core64_m1(pcie_core64_m1)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_pcie_x8
# Loading work.ctrl_pcie_x8
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_ep_top
# Loading work.pcie_ep_top
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_top_wrapper
# Loading work.pcie_top_wrapper
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_clocking
# Loading work.pcie_clocking
# Loading unisims_ver.PLL_ADV
# Loading unisims_ver.BUFG
# Loading unisims_ver.PCIE_EP
# Loading unisims_ver.PCIE_INTERNAL_1_1
# Loading secureip.PCIE_INTERNAL_1_1_SWIFT
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.prod_fixes
# Loading work.prod_fixes
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_mim_wrapper
# Loading work.pcie_mim_wrapper
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.bram_common
# Loading work.bram_common
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_gt_wrapper_top
# Loading work.pcie_gt_wrapper_top
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_if
# Loading work.pcie_blk_if
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll
# Loading work.pcie_blk_ll
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_plus_ll_tx
# Loading work.pcie_blk_plus_ll_tx
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll_tx_arb
# Loading work.pcie_blk_ll_tx_arb
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll_tx
# Loading work.pcie_blk_ll_tx
# Loading unisims_ver.LUT6
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_plus_ll_rx
# Loading work.pcie_blk_plus_ll_rx
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.tlm_rx_data_snk
# Loading work.tlm_rx_data_snk
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.tlm_rx_data_snk_mal
# Loading work.tlm_rx_data_snk_mal
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.tlm_rx_data_snk_pwr_mgmt
# Loading work.tlm_rx_data_snk_pwr_mgmt
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.tlm_rx_data_snk_bar
# Loading work.tlm_rx_data_snk_bar
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_decoder
# Loading work.cmm_decoder
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll_oqbqfifo
# Loading work.pcie_blk_ll_oqbqfifo
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.sync_fifo
# Loading work.sync_fifo
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll_arb
# Loading work.pcie_blk_ll_arb
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_ll_credit
# Loading work.pcie_blk_ll_credit
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.my_SRL16E
# Loading work.my_SRL16E
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_cf
# Loading work.pcie_blk_cf
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_cf_mgmt
# Loading work.pcie_blk_cf_mgmt
# Loading unisims_ver.LUT5
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_cf_err
# Loading work.pcie_blk_cf_err
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_cor
# Loading work.cmm_errman_cor
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_cnt_en
# Loading work.cmm_errman_cnt_en
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_ftl
# Loading work.cmm_errman_ftl
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_cpl
# Loading work.cmm_errman_cpl
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_ram4x26
# Loading work.cmm_errman_ram4x26
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_errman_ram8x26
# Loading work.cmm_errman_ram8x26
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_cf_arb
# Loading work.pcie_blk_cf_arb
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_blk_cf_pwr
# Loading work.pcie_blk_cf_pwr
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_soft_cf_int
# Loading work.pcie_soft_cf_int
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cmm_intr
# Loading work.cmm_intr
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.extend_clk
# Loading work.extend_clk
# Loading unisims_ver.RAMB36SDP
# Loading unisims_ver.ARAMB36_INTERNAL
# Loading unisims_ver.RAMB36
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_gt_wrapper
# Loading work.pcie_gt_wrapper
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.TX_SYNC_GTP
# Loading work.TX_SYNC_GTP
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.reset_logic
# Loading work.reset_logic
# Loading unisims_ver.SRL16E
# Loading unisims_ver.FD
# Loading unisims_ver.FDCP
# Loading unisims_ver.GTP_DUAL
# Loading secureip.GTP_DUAL_FAST
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_rx_engine(core64_rx_engine)
# Loading work.core64_rx_engine(core64_rx_engine)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_fifo64x70st(ctrl_fifo64x70st_a)
# Loading work.ctrl_fifo64x70st(ctrl_fifo64x70st_a)
# Loading xilinxcorelib.fifo_generator_v8_1(behavioral)
# Loading xilinxcorelib.fifo_generator_v8_1_conv(behavioral)
# Loading xilinxcorelib.fifo_generator_v8_1_bhv_ss(behavioral)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_tx_engine(core64_tx_engine)
# Loading work.core64_tx_engine(core64_tx_engine)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_fifo64x67fw(ctrl_fifo64x67fw_a)
# Loading work.ctrl_fifo64x67fw(ctrl_fifo64x67fw_a)
# Loading xilinxcorelib.fifo_generator_v8_1_bhv_preload0(behavioral)
# Loading ieee.numeric_std(body)
# Loading unisim.srlc32e(srlc32e_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_reg_access(core64_reg_access)
# Loading work.core64_reg_access(core64_reg_access)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_pb_disp(core64_pb_disp)
# Loading work.core64_pb_disp(core64_pb_disp)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.block_pe_fifo_ext(block_pe_fifo_ext)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_dma_ext_cmd_pkg
# Loading work.ctrl_dma_ext_cmd_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ext_descriptor_pkg
# Loading work.ctrl_ext_descriptor_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ext_ram_pkg
# Loading work.ctrl_ext_ram_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_main_pkg
# Loading work.ctrl_main_pkg
# Loading work.block_pe_fifo_ext(block_pe_fifo_ext)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# Loading unisim.ramb16_s36_s36(ramb16_s36_s36_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_main(ctrl_main)
# Loading work.ctrl_main(ctrl_main)
# Loading unisim.srl16(srl16_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_dma_ext_cmd(ctrl_dma_ext_cmd)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_dma_adr_pkg
# Loading work.ctrl_dma_adr_pkg
# Loading work.ctrl_dma_ext_cmd(ctrl_dma_ext_cmd)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_dma_adr(ctrl_dma_adr)
# Loading work.ctrl_dma_adr(ctrl_dma_adr)
# Loading ieee.std_logic_signed(body)
# Loading unisim.dsp48(dsp48_v)
# Loading unisim.ram16x1d(ram16x1d_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ext_descriptor(ctrl_ext_descriptor)
# Loading work.ctrl_ext_descriptor(ctrl_ext_descriptor)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ext_ram(ctrl_ext_ram)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram_cmd_pkg
# Loading work.ctrl_ram_cmd_pkg
# Loading work.ctrl_ext_ram(ctrl_ext_ram)
# Loading unisim.ramb16_s9_s9(ramb16_s9_s9_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram_cmd(ctrl_ram_cmd)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram_cmd_pb_pkg
# Loading work.ctrl_ram_cmd_pb_pkg
# Loading work.ctrl_ram_cmd(ctrl_ram_cmd)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram_cmd_pb(ctrl_ram_cmd_pb)
# Loading work.ctrl_ram_cmd_pb(ctrl_ram_cmd_pb)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_interrupt(core64_interrupt)
# Loading work.core64_interrupt(core64_interrupt)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.core64_pb_transaction(core64_pb_transaction)
# Loading work.core64_pb_transaction(core64_pb_transaction)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.block_pe_main(block_pe_main)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram16_v1_pkg
# Loading work.ctrl_ram16_v1_pkg
# Loading work.block_pe_main(block_pe_main)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_ram16_v1(ctrl_ram16_v1)
# Loading work.ctrl_ram16_v1(ctrl_ram16_v1)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_blink(ctrl_blink)
# Loading work.ctrl_blink(ctrl_blink)
# Loading unisim.fd(fd_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pb_adm_ctrl_m2(pb_adm_ctrl_m2)
# Loading work.pb_adm_ctrl_m2(pb_adm_ctrl_m2)
# Loading unisim.ramb16_s18(ramb16_s18_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_adsp_v2_decode_data_cs(ctrl_adsp_v2_decode_data_cs)
# Loading work.ctrl_adsp_v2_decode_data_cs(ctrl_adsp_v2_decode_data_cs)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_adsp_v2_decode_data_we(ctrl_adsp_v2_decode_data_we)
# Loading work.ctrl_adsp_v2_decode_data_we(ctrl_adsp_v2_decode_data_we)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_adsp_v2_decode_ram_cs(ctrl_adsp_v2_decode_ram_cs)
# Loading work.ctrl_adsp_v2_decode_ram_cs(ctrl_adsp_v2_decode_ram_cs)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_adsp_v2_decode_cmd_adr_cs(ctrl_adsp_v2_decode_cmd_adr_cs)
# Loading work.ctrl_adsp_v2_decode_cmd_adr_cs(ctrl_adsp_v2_decode_cmd_adr_cs)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_mux8x48(ctrl_mux8x48_a)
# Loading xilinxcorelib.prims_constants_v6_0
# Loading xilinxcorelib.prims_utils_v6_0(body)
# Loading xilinxcorelib.c_reg_fd_v6_0_comp
# Loading work.ctrl_mux8x48(ctrl_mux8x48_a)
# Loading xilinxcorelib.c_mux_bus_v6_0(behavioral)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_mux16x16(ctrl_mux16x16_a)
# Loading work.ctrl_mux16x16(ctrl_mux16x16_a)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_mux8x16r(ctrl_mux8x16r_a)
# Loading work.ctrl_mux8x16r(ctrl_mux8x16r_a)
# Loading xilinxcorelib.c_reg_fd_v6_0(behavioral)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_main_v8(trd_main_v8)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_start_v2_pkg
# Loading work.ctrl_start_v2_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test0_v4_pkg
# Loading work.cl_test0_v4_pkg
# Loading work.trd_main_v8(trd_main_v8)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test0_v4(cl_test0_v4)
# Loading work.cl_test0_v4(cl_test0_v4)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_start_v2(ctrl_start_v2)
# Loading work.ctrl_start_v2(ctrl_start_v2)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_thdac(ctrl_thdac)
# Loading work.ctrl_thdac(ctrl_thdac)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_admdio64_in_v6(trd_admdio64_in_v6)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_fifo1024x65_v5_pkg
# Loading work.cl_fifo1024x65_v5_pkg
# Loading work.trd_admdio64_in_v6(trd_admdio64_in_v6)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_buft16(ctrl_buft16)
# Loading work.ctrl_buft16(ctrl_buft16)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_buft64(ctrl_buft64)
# Loading work.ctrl_buft64(ctrl_buft64)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_chn_v3(cl_chn_v3)
# Loading work.cl_chn_v3(cl_chn_v3)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_fifo1024x65_v5(cl_fifo1024x65_v5)
# Loading work.cl_fifo1024x65_v5(cl_fifo1024x65_v5)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_fifo1024x65_v5(ctrl_fifo1024x65_v5_a)
# Loading xilinxcorelib.iputils_std_logic_arith(body)
# Loading xilinxcorelib.iputils_std_logic_unsigned(body)
# Loading xilinxcorelib.iputils_conv(body)
# Loading xilinxcorelib.iputils_misc(body)
# Loading work.ctrl_fifo1024x65_v5(ctrl_fifo1024x65_v5_a)
# Loading xilinxcorelib.fifo_generator_v3_3(behavioral)
# Loading xilinxcorelib.fifo_generator_v3_3_bhv_as(behavioral)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_fifo_control_v2(cl_fifo_control_v2)
# Loading work.cl_fifo_control_v2(cl_fifo_control_v2)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_admdio64_out_v4(trd_admdio64_out_v4)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_chn_v4_pkg
# Loading work.cl_chn_v4_pkg
# Loading work.trd_admdio64_out_v4(trd_admdio64_out_v4)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_chn_v4(cl_chn_v4)
# Loading work.cl_chn_v4(cl_chn_v4)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.trd_test_ctrl_m1(trd_test_ctrl_m1)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test_generate_pkg
# Loading work.cl_test_generate_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test_check_pkg
# Loading work.cl_test_check_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_freq_pkg
# Loading work.ctrl_freq_pkg
# Loading work.trd_test_ctrl_m1(trd_test_ctrl_m1)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test_generate(cl_test_generate)
# Loading work.cl_test_generate(cl_test_generate)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.cl_test_check(cl_test_check)
# Loading work.cl_test_check(cl_test_check)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_freq(ctrl_freq)
# Loading work.ctrl_freq(ctrl_freq)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.ctrl_multiplier_v1_0(ctrl_multiplier_v1_0_a)
# Loading xilinxcorelib.prims_constants_v9_0
# Loading xilinxcorelib.prims_utils_v9_0(body)
# Loading xilinxcorelib.pkg_baseblox_v9_0(body)
# Loading xilinxcorelib.pkg_mult_gen_v9_0(body)
# Loading work.ctrl_multiplier_v1_0(ctrl_multiplier_v1_0_a)
# Loading xilinxcorelib.mult_gen_v9_0(behavioral)
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr0/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr1/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# ** Note: returned a simple delay of 1
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/test_ctrl/fr2/x_mult/U0 File: C:/Xilinx/13.2/ISE_DS/ISE/vhdl/src/XilinxCoreLib/mult_gen_v9_0.vhd
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.xilinx_pcie_rport_m2(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_tx_m2_pkg
# Loading work.pci_exp_usrapp_tx_m2_pkg
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_rx_m2_pkg
# Loading work.pci_exp_usrapp_rx_m2_pkg
# Loading work.xilinx_pcie_rport_m2(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_2_0_rport_v6(v6_pcie)
# Loading work.pcie_2_0_rport_v6(v6_pcie)
# Loading unisim.fdcp(fdcp_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_reset_delay_v6(v6_pcie)
# Loading work.pcie_reset_delay_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_clocking_v6(v6_pcie)
# Loading work.pcie_clocking_v6(v6_pcie)
# Loading unisim.mmcm_adv(mmcm_adv_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_2_0_v6_rp(v6_pcie)
# Loading work.pcie_2_0_v6_rp(v6_pcie)
# Loading unisim.pcie_2_0(pcie_2_0_v)
# Loading secureip.PCIE_2_0_WRAP
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_pipe_v6(v6_pcie)
# Loading work.pcie_pipe_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_pipe_misc_v6(v6_pcie)
# Loading work.pcie_pipe_misc_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_pipe_lane_v6(v6_pcie)
# Loading work.pcie_pipe_lane_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_gtx_v6(v6_pcie)
# Loading work.pcie_gtx_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.gtx_wrapper_v6(v6_pcie)
# Loading work.gtx_wrapper_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.gtx_drp_chanalign_fix_3752_v6(v6_pcie)
# Loading work.gtx_drp_chanalign_fix_3752_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.gtx_rx_valid_filter_v6(v6_pcie)
# Loading work.gtx_rx_valid_filter_v6(v6_pcie)
# Loading unisim.srl16e(srl16e_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.gtx_tx_sync_rate_v6(v6_pcie)
# Loading work.gtx_tx_sync_rate_v6(v6_pcie)
# Loading unisim.gtxe1(gtxe1_v)
# Loading secureip.GTXE1_WRAP
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_bram_top_v6(v6_pcie)
# Loading work.pcie_bram_top_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_brams_v6(v6_pcie)
# Loading work.pcie_brams_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_bram_v6(v6_pcie)
# Loading work.pcie_bram_v6(v6_pcie)
# Loading unisim.ramb36(ramb36_v)
# Loading unisim.aramb36_internal(aramb36_internal_v)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pcie_upconfig_fix_3451_v6(v6_pcie)
# Loading work.pcie_upconfig_fix_3451_v6(v6_pcie)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_cfg(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.test_interface(body)
# Loading work.test_interface(body)
# Loading work.pci_exp_usrapp_cfg(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_rx_m2(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.root_memory_pkg(body)
# Loading work.root_memory_pkg(body)
# Loading work.pci_exp_usrapp_rx_m2(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_tx_m2(rtl)
# Loading work.pci_exp_usrapp_tx_m2(rtl)
# Refreshing D:\TMP\08\Help\ambpex5_v20_sx50t_core\modelsim\work.pci_exp_usrapp_pl(rtl)
# Loading work.pci_exp_usrapp_pl(rtl)
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [TFMPC] - Too few port connections. Expected 90, found 88.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [PCDPC] - Port size (56 or 56) does not match connection size (32) for port 'gt_daddr'. The port definition is at: ../src/pcie_src/pcie_core64_m1/source/pcie_ep.v(340).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'gt_den'. The port definition is at: ../src/pcie_src/pcie_core64_m1/source/pcie_ep.v(341).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'gt_dwen'. The port definition is at: ../src/pcie_src/pcie_core64_m1/source/pcie_ep.v(342).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [PCDPC] - Port size (128 or 128) does not match connection size (32) for port 'gt_di'. The port definition is at: ../src/pcie_src/pcie_core64_m1/source/pcie_ep.v(343).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [TFMPC] - Missing connection for port 'trn_rfc_cplh_av'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/ctrl_pcie_x8.v(480): [TFMPC] - Missing connection for port 'trn_rfc_cpld_av'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Too few port connections. Expected 28, found 10.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/clocking_i/use_pll/pll_adv_i
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKFBDCM'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUT4'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUT5'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM0'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM1'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM2'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM3'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM4'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKOUTDCM5'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DO'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DRDY'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'CLKIN2'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DADDR'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DCLK'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DEN'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DI'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'DWE'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_clocking.v(160): [TFMPC] - Missing connection for port 'REL'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/pcie_top.v(1998): [TFMPC] - Too few port connections. Expected 278, found 277.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_ep
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/pcie_top.v(1998): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'L0CFGDISABLESCRAMBLE'. The port definition is at: C:/Xilinx/13.2/ISE_DS/ISE/verilog/src/unisims/PCIE_EP.v(204).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_ep
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_top.v(1998): [TFMPC] - Missing connection for port 'LLKTXCONFIGREADYN'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Too few port connections. Expected 28, found 16.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/genblk1/generate_tdp2[0]/ram_tdp2_inst
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPB'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Too few port connections. Expected 28, found 16.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/genblk1/generate_tdp2[1]/ram_tdp2_inst
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPB'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Too few port connections. Expected 28, found 16.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/genblk1/generate_tdp2[0]/ram_tdp2_inst
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPB'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Too few port connections. Expected 28, found 16.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/genblk1/generate_tdp2[1]/ram_tdp2_inst
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEOUTREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DOPB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINLATB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'CASCADEINREGB'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPA'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/bram_common.v(170): [TFMPC] - Missing connection for port 'DIPB'.
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Too few port connections. Expected 104, found 98.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk_if/ll_bridge
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_nph_cl'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_npd_cl'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_ph_cl'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_pd_cl'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_cplh_cl'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_if.v(482): [TFMPC] - Missing connection for port 'trn_pfc_cpld_cl'.
# ** Warning: (vsim-3015) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_plus_ll_rx.v(339): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'td_ecrc_trim_i'. The port definition is at: ../src/pcie_src/pcie_core64_m1/source/tlm_rx_data_snk.v(212).
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst
# ** Warning: (vsim-3017) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_ll_oqbqfifo.v(265): [TFMPC] - Too few port connections. Expected 14, found 11.
#         Region: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/ep/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bq_fifo
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_ll_oqbqfifo.v(265): [TFMPC] - Missing connection for port 'mark_addr'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_ll_oqbqfifo.v(265): [TFMPC] - Missing connection for port 'clear_addr'.
# ** Warning: (vsim-3722) ../src/pcie_src/pcie_core64_m1/source/pcie_blk_ll_oqbqfifo.v(265): [TFMPC] - Missing connection for port 'rewind'.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(5 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo0_reg/U0/DATA_COUNT(5 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo1_cmpl/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(5 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/rx/fifo1_cmpl/U0/DATA_COUNT(5 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/gen_ss/fgss/VALID, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/valid_fifo_out.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/gen_ss/fgss/UNDERFLOW, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/underflow_fifo_out.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/gconvfifo/inst_conv_fifo/DATA_COUNT(6 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/tx/fifo0_reg/U0/DATA_COUNT(6 downto 0).
# ** Warning: (vsim-8683) Uninitialized out port /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/main/pb_reset has no driver.
# This port will contribute value (U) to the signal network.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(15).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(15).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(14).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(14).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(13).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(13).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(12).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(12).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(11).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(11).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(10).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(10).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(9).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(9).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/gen_syn/ad/trd_host_cmd(8).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/amb/trdi_host_cmd(8).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_adr(15 downto 7), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_adr(15 downto 7).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(15)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(15)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(14)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(14)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(13)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(13)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(12)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(12)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(11)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(11)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(10)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(10)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(9)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(9)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_data(8)(63 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_data(8)(63 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(15)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(15)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(14)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(14)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(13)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(13)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(12)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(12)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(11)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(11)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(10)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(10)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(9)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(9)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd_data(8)(15 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd_data(8)(15 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(15).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(15).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(14).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(14).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(13).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(13).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(12).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(12).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(11).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(11).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(10).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(10).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(9).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(9).adr(9 downto 0).
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_data_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_data_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).status_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).status_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_data_cs, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_data_cs.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).cmd_adr_we, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).cmd_adr_we.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).data_oe, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).data_oe.
# ** Warning: (vsim-8684) No drivers exist on out port /stend_ambpex5_core_m2/amb/amb/trd_host_cmd(8).adr(9 downto 0), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /stend_ambpex5_core_m2/amb/trd_host_cmd(8).adr(9 downto 0).
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/dio_out/x_fifo/ctrl_fifo/U0
# ** Note: Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.
#    Time: 0 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2/amb/dio_in/x_fifo/ctrl_fifo/U0
# ===== Number of BRAMS for RETRYRAM =           1  =====
# ===== Number of BRAMS for TL_TXRAM =           2  =====
# ===== Number of BRAMS for TL_RXRAM =           2  =====
# [ 1000 ns ] : Init start
# ** Warning: OPMODE Input Warning : The OPMODE 0UU00UU with CARRYINSEL  00 to DSP48 instance is invalid.
#    Time: 5030100 ps  Iteration: 5  Instance: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/fifo/cmd/dma_adr/gen_dsp48/dsp0
# ** Warning: OPMODE Input Warning : The OPMODE 0UU00UU with CARRYINSEL  00 to DSP48 instance is invalid.
#    Time: 5030100 ps  Iteration: 5  Instance: /stend_ambpex5_core_m2/amb/amb/gen_syn/pcie/core/fifo/cmd/dma_adr/gen_dsp48/dsp1
# [ 15923.246 ns ] : Transaction Reset is De-asserted
#             23794000: Bad trailing TS characters (note)
# [ 85187.246 ns ] : Transaction Link is Up
# [ 85187.246 ns ] : PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN..
#             BAR 0 = 0x10000000 RANGE = 0xFFE00000 MEM32 MAPPED
#             BAR 1 = 0x20000000 RANGE = 0xFFE00000 MEM32 MAPPED
#             BAR 2 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 3 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 4 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 5 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 6 = 0x00000000 RANGE = 0x00000000 DISABLED
# [ 85187.246 ns ] : Setting Core Configuration Space...
# [ 133235.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 134883.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 135379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 136531.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 137043.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 138179.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 138675.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 139827.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 140339.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 141475.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 142035.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 143123.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 143667.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 144771.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 145331.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 146419.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 146963.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 148627.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 167219.146 ns ] : BUS Master Enable 
# [ 167219.146 ns ] : Reading Config space
#   Addr: [0x001]
#   Cfg Addr [0x001] -> Data [0x00100000]
# [ 167379.146 ns ] : Writing Config space
#   Addr: [0x001] -> Data [0x00000007]
# [ 167539.146 ns ] : Reading Config space
#   Addr: [0x001]
#   Cfg Addr [0x001] -> Data [0x00100007]
# [ 172667.146 ns ] : Init complete
# [ 186003.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186067.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186131.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186195.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186259.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186323.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186387.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 186451.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 198355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 198467.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 198531.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 198595.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 202643.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 202755.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 202819.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 202883.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 202947.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 206771.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 206867.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 206931.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 207027.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 208467.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 208691.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 208867.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 208915.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 209091.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 209267.146 ns ] : PROC_PARSE_FRAME on Transmit
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# [ 209491.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 209667.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 209715.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214131.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 214355.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214531.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214579.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214643.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 214707.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 219155.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 219267.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 226643.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 227251.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 227827.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 228435.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 229011.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 229619.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 230195.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 230803.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 231379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 231987.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 232563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 233171.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 233747.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 234355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 234963.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 235571.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 236147.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 236755.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 237331.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 237939.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 238515.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 239123.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 239331.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 239731.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 240339.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 240915.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 241523.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 242131.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 242771.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 243347.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 243955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 244531.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 245139.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 245811.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 246419.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 246995.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 247603.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 248179.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 248211.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 248323.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 248883.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 249491.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 250099.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 250675.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 251347.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 251987.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 252595.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 253171.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 253811.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 254387.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 254995.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 255571.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 256179.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 256755.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 257363.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 257939.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 257971.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 258083.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 258675.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 259251.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 259859.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 260435.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 261107.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 261683.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 262291.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 262867.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 263475.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264051.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264659.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264691.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264723.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264755.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264787.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 264819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 265043.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 265219.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 265267.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 265443.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 265619.146 ns ] : PROC_PARSE_FRAME on Transmit
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# [ 265971.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 266019.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 269523.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 269747.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 269923.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 269971.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 272659.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 272771.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 273331.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 275891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 276563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 277139.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 277779.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 278355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 278963.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 279539.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 279571.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 279683.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 280243.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 280819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 281427.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 282003.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 282707.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 283283.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 283891.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 284467.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 285139.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 285715.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 286323.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 286899.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 287507.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 288083.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 288115.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 288723.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 288787.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 289363.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 289971.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 290547.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 291155.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 291795.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 292435.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 293011.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 293619.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 294195.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 294899.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 295475.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296083.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 296659.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 297299.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 297875.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 297907.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 298019.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 298579.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 299155.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 299763.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 300339.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 301011.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 301587.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 302195.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 302771.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 303379.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 303955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 304563.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 305139.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 305747.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 306323.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 306963.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 307539.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 308147.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 308179.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 308291.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 308819.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 308851.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 309427.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 310003.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 310611.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 311251.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 311955.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 312531.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 313139.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 313715.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 314323.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 314355.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 314467.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 316723.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 316835.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 316899.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 319219.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 319331.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 319395.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 321651.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 322259.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 324595.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 325203.146 ns ] : PROC_PARSE_FRAME on Transmit
# [ 327411.146 ns ] : PROC_PARSE_FRAME on Receive
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# [ 330259.146 ns ] : PROC_PARSE_FRAME on Receive
# [ 330867.146 ns ] : PROC_PARSE_FRAME on Transmit
# ** Warning: Init END OF TEST
#    Time: 332286146 ps  Iteration: 0  Instance: /stend_ambpex5_core_m2
# ** Failure: End of TEST; Ending simulation (not a Failure)
#    Time: 332286146 ps  Iteration: 0  Process: /stend_ambpex5_core_m2/pr_main File: ../src/testbench/stend_ambpex5_core_m2.vhd
# Break in Process pr_main at ../src/testbench/stend_ambpex5_core_m2.vhd line 200
# Simulation Breakpoint: Break in Process pr_main at ../src/testbench/stend_ambpex5_core_m2.vhd line 200
# MACRO ./setup_sim.do PAUSED at line 45
