--------------------------------------------------------------------------------
Release 13.1 Trace  (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -e 32 -s 1 -n 3 -fastpaths
ambpex5_v20_sx50t_core_merge_chipscope.ncd
ambpex5_v20_sx50t_core_merge_chipscope.pcf -o
ambpex5_v20_sx50t_core_merge_chipscope_postpar.twr

Design file:              ambpex5_v20_sx50t_core_merge_chipscope.ncd
Physical constraint file: ambpex5_v20_sx50t_core_merge_chipscope.pcf
Device,package,speed:     xc5vsx50t,ff1136,-1 (PRODUCTION 1.72 2011-02-03, STEPPING level 0)
Report level:             error report, limited to 32 items per endpoint, 3 endpoints per constraint

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 
15 ns;

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   0.873ns.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 250 MHz HIGH 50%;

 157713 paths analyzed, 33664 endpoints analyzed, 2405 failing endpoints
 2405 timing errors detected. (2405 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.445ns.
--------------------------------------------------------------------------------

Paths for end point amb/gen_syn.pcie/core/reg/bar0_data_2 (SLICE_X39Y46.B6), 7 paths
--------------------------------------------------------------------------------
Slack (setup path):     -1.445ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/fifo/ram (RAM)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.940ns (Levels of Logic = 2)
  Clock Path Skew:      -0.440ns (1.123 - 1.563)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/fifo/ram to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X2Y3.DOBDOL1  Trcko_DOWB            2.180   amb/gen_syn.pcie/core/fifo/ram
                                                       amb/gen_syn.pcie/core/fifo/ram
    SLICE_X34Y34.A5      net (fanout=1)        1.457   amb/gen_syn.pcie/core/fifo/ram_do_b<2>
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.940ns (2.301ns logic, 2.639ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.657ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_6 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.423ns (Levels of Logic = 3)
  Clock Path Skew:      -0.169ns (1.123 - 1.292)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_6 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y21.DQ      Tcko                  0.450   amb/gen_syn.pcie/bp_adr<3>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_6
    SLICE_X34Y34.C2      net (fanout=27)       1.923   amb/gen_syn.pcie/bp_adr<3>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.423ns (0.665ns logic, 3.758ns route)
                                                       (15.0% logic, 85.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.536ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_3 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.279ns (Levels of Logic = 3)
  Clock Path Skew:      -0.192ns (1.123 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_3 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.AQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_3
    SLICE_X34Y34.C4      net (fanout=26)       1.758   amb/gen_syn.pcie/bp_adr<0>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.279ns (0.686ns logic, 3.593ns route)
                                                       (16.0% logic, 84.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.529ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_9 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.298ns (Levels of Logic = 3)
  Clock Path Skew:      -0.166ns (1.123 - 1.289)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_9 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y22.AQ      Tcko                  0.450   amb/gen_syn.pcie/core/bp_adr<8>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_9
    SLICE_X34Y34.C1      net (fanout=24)       1.798   amb/gen_syn.pcie/bp_sel<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.298ns (0.665ns logic, 3.633ns route)
                                                       (15.5% logic, 84.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.454ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_7 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.216ns (Levels of Logic = 3)
  Clock Path Skew:      -0.173ns (1.123 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_7 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.BQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_7
    SLICE_X34Y34.C6      net (fanout=24)       1.716   amb/gen_syn.pcie/bp_adr<4>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.216ns (0.665ns logic, 3.551ns route)
                                                       (15.8% logic, 84.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.365ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_5 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.127ns (Levels of Logic = 3)
  Clock Path Skew:      -0.173ns (1.123 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_5 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.AQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_5
    SLICE_X34Y34.C3      net (fanout=26)       1.627   amb/gen_syn.pcie/bp_adr<2>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.127ns (0.665ns logic, 3.462ns route)
                                                       (16.1% logic, 83.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.317ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_4 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_2 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.060ns (Levels of Logic = 3)
  Clock Path Skew:      -0.192ns (1.123 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_4 to amb/gen_syn.pcie/core/reg/bar0_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.BQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_4
    SLICE_X34Y34.C5      net (fanout=26)       1.539   amb/gen_syn.pcie/bp_adr<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A3      net (fanout=13)       0.653   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y34.A       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut68_12725
    SLICE_X39Y46.B6      net (fanout=1)        1.182   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<2>
    SLICE_X39Y46.CLK     Tas                   0.027   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][167_9484
                                                       amb/gen_syn.pcie/core/reg/bar0_data_2
    -------------------------------------------------  ---------------------------
    Total                                      4.060ns (0.686ns logic, 3.374ns route)
                                                       (16.9% logic, 83.1% route)

--------------------------------------------------------------------------------

Paths for end point amb/gen_syn.pcie/core/reg/bar0_data_12 (SLICE_X37Y46.D6), 7 paths
--------------------------------------------------------------------------------
Slack (setup path):     -1.407ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/fifo/ram (RAM)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.889ns (Levels of Logic = 2)
  Clock Path Skew:      -0.453ns (1.110 - 1.563)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/fifo/ram to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X2Y3.DOBDOL6  Trcko_DOWB            2.180   amb/gen_syn.pcie/core/fifo/ram
                                                       amb/gen_syn.pcie/core/fifo/ram
    SLICE_X35Y36.C4      net (fanout=1)        1.598   amb/gen_syn.pcie/core/fifo/ram_do_b<12>
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.889ns (2.302ns logic, 2.587ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.626ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_6 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.379ns (Levels of Logic = 3)
  Clock Path Skew:      -0.182ns (1.110 - 1.292)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_6 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y21.DQ      Tcko                  0.450   amb/gen_syn.pcie/bp_adr<3>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_6
    SLICE_X34Y34.C2      net (fanout=27)       1.923   amb/gen_syn.pcie/bp_adr<3>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.379ns (0.666ns logic, 3.713ns route)
                                                       (15.2% logic, 84.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.505ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_3 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.235ns (Levels of Logic = 3)
  Clock Path Skew:      -0.205ns (1.110 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_3 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.AQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_3
    SLICE_X34Y34.C4      net (fanout=26)       1.758   amb/gen_syn.pcie/bp_adr<0>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.235ns (0.687ns logic, 3.548ns route)
                                                       (16.2% logic, 83.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.498ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_9 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.254ns (Levels of Logic = 3)
  Clock Path Skew:      -0.179ns (1.110 - 1.289)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_9 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y22.AQ      Tcko                  0.450   amb/gen_syn.pcie/core/bp_adr<8>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_9
    SLICE_X34Y34.C1      net (fanout=24)       1.798   amb/gen_syn.pcie/bp_sel<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.254ns (0.666ns logic, 3.588ns route)
                                                       (15.7% logic, 84.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.423ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_7 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.172ns (Levels of Logic = 3)
  Clock Path Skew:      -0.186ns (1.110 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_7 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.BQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_7
    SLICE_X34Y34.C6      net (fanout=24)       1.716   amb/gen_syn.pcie/bp_adr<4>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.172ns (0.666ns logic, 3.506ns route)
                                                       (16.0% logic, 84.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.334ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_5 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.083ns (Levels of Logic = 3)
  Clock Path Skew:      -0.186ns (1.110 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_5 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.AQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_5
    SLICE_X34Y34.C3      net (fanout=26)       1.627   amb/gen_syn.pcie/bp_adr<2>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.083ns (0.666ns logic, 3.417ns route)
                                                       (16.3% logic, 83.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.286ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_4 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_12 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.016ns (Levels of Logic = 3)
  Clock Path Skew:      -0.205ns (1.110 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_4 to amb/gen_syn.pcie/core/reg/bar0_data_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.BQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_4
    SLICE_X34Y34.C5      net (fanout=26)       1.539   amb/gen_syn.pcie/bp_adr<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C2      net (fanout=13)       0.801   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X35Y36.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<6>
                                                       amb/gen_syn.pcie/core/fifo/lut88_12735
    SLICE_X37Y46.D6      net (fanout=1)        0.989   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<12>
    SLICE_X37Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<12>
                                                       amb/gen_syn.pcie/core/reg/][207_9524
                                                       amb/gen_syn.pcie/core/reg/bar0_data_12
    -------------------------------------------------  ---------------------------
    Total                                      4.016ns (0.687ns logic, 3.329ns route)
                                                       (17.1% logic, 82.9% route)

--------------------------------------------------------------------------------

Paths for end point amb/gen_syn.pcie/core/reg/bar0_data_7 (SLICE_X39Y46.D5), 10 paths
--------------------------------------------------------------------------------
Slack (setup path):     -1.401ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/fifo/ram (RAM)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.892ns (Levels of Logic = 2)
  Clock Path Skew:      -0.444ns (1.123 - 1.567)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/fifo/ram to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X2Y3.DOBDOU3  Trcko_DOWB            2.180   amb/gen_syn.pcie/core/fifo/ram
                                                       amb/gen_syn.pcie/core/fifo/ram
    SLICE_X34Y38.C6      net (fanout=1)        1.451   amb/gen_syn.pcie/core/fifo/ram_do_b<7>
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.892ns (2.302ns logic, 2.590ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.797ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_6 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.563ns (Levels of Logic = 3)
  Clock Path Skew:      -0.169ns (1.123 - 1.292)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_6 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y21.DQ      Tcko                  0.450   amb/gen_syn.pcie/bp_adr<3>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_6
    SLICE_X34Y34.C2      net (fanout=27)       1.923   amb/gen_syn.pcie/bp_adr<3>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.563ns (0.666ns logic, 3.897ns route)
                                                       (14.6% logic, 85.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.676ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_3 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.419ns (Levels of Logic = 3)
  Clock Path Skew:      -0.192ns (1.123 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_3 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.AQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_3
    SLICE_X34Y34.C4      net (fanout=26)       1.758   amb/gen_syn.pcie/bp_adr<0>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.419ns (0.687ns logic, 3.732ns route)
                                                       (15.5% logic, 84.5% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.669ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_9 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.438ns (Levels of Logic = 3)
  Clock Path Skew:      -0.166ns (1.123 - 1.289)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_9 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X37Y22.AQ      Tcko                  0.450   amb/gen_syn.pcie/core/bp_adr<8>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_9
    SLICE_X34Y34.C1      net (fanout=24)       1.798   amb/gen_syn.pcie/bp_sel<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.438ns (0.666ns logic, 3.772ns route)
                                                       (15.0% logic, 85.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.594ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_7 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.356ns (Levels of Logic = 3)
  Clock Path Skew:      -0.173ns (1.123 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_7 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.BQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_7
    SLICE_X34Y34.C6      net (fanout=24)       1.716   amb/gen_syn.pcie/bp_adr<4>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.356ns (0.666ns logic, 3.690ns route)
                                                       (15.3% logic, 84.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.505ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_5 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.267ns (Levels of Logic = 3)
  Clock Path Skew:      -0.173ns (1.123 - 1.296)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_5 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y21.AQ      Tcko                  0.450   amb/gen_syn.pcie/bp_host_data<14>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_5
    SLICE_X34Y34.C3      net (fanout=26)       1.627   amb/gen_syn.pcie/bp_adr<2>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.267ns (0.666ns logic, 3.601ns route)
                                                       (15.6% logic, 84.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.457ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_4 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      4.200ns (Levels of Logic = 3)
  Clock Path Skew:      -0.192ns (1.123 - 1.315)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_4 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y23.BQ      Tcko                  0.471   amb/gen_syn.pcie/core/bp_adr<7>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_4
    SLICE_X34Y34.C5      net (fanout=26)       1.539   amb/gen_syn.pcie/bp_adr<1>
    SLICE_X34Y34.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<15>
                                                       amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C4      net (fanout=13)       0.835   amb/gen_syn.pcie/core/fifo/lut63_12722
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      4.200ns (0.687ns logic, 3.513ns route)
                                                       (16.4% logic, 83.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     -0.014ns (requirement - (data path - clock path skew + uncertainty))
  Source:               amb/gen_syn.pcie/core/rx/tlp_dw2_8 (FF)
  Destination:          amb/gen_syn.pcie/core/reg/bar0_data_7 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.787ns (Levels of Logic = 2)
  Clock Path Skew:      -0.162ns (1.123 - 1.285)
  Source Clock:         clk rising at 0.000ns
  Destination Clock:    clk rising at 4.000ns
  Clock Uncertainty:    0.065ns

  Clock Uncertainty:          0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.110ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: amb/gen_syn.pcie/core/rx/tlp_dw2_8 to amb/gen_syn.pcie/core/reg/bar0_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y24.AQ      Tcko                  0.450   amb/gen_syn.pcie/core/bp_adr<17>
                                                       amb/gen_syn.pcie/core/rx/tlp_dw2_8
    SLICE_X34Y38.C3      net (fanout=32)       2.076   amb/gen_syn.pcie/bp_sel<0>
    SLICE_X34Y38.C       Tilo                  0.094   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<4>
                                                       amb/gen_syn.pcie/core/fifo/lut78_12730
    SLICE_X39Y46.D5      net (fanout=1)        1.139   amb/gen_syn.pcie/core/reg_ext_fifo_back_data<7>
    SLICE_X39Y46.CLK     Tas                   0.028   amb/gen_syn.pcie/core/reg/bar0_data<7>
                                                       amb/gen_syn.pcie/core/reg/][187_9504
                                                       amb/gen_syn.pcie/core/reg/bar0_data_7
    -------------------------------------------------  ---------------------------
    Total                                      3.787ns (0.572ns logic, 3.215ns route)
                                                       (15.1% logic, 84.9% route)

--------------------------------------------------------------------------------


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock mgt251_n
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
mgt251_n       |    5.445|         |         |         |
mgt251_p       |    5.445|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock mgt251_p
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
mgt251_n       |    5.445|         |         |         |
mgt251_p       |    5.445|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 2405  Score: 1044412  (Setup/Max: 1044412, Hold: 0)

Constraints cover 157714 paths, 0 nets, and 36166 connections

Design statistics:
   Minimum period:   5.445ns   (Maximum frequency: 183.655MHz)
   Maximum path delay from/to any node:   0.873ns


Analysis completed Thu Sep 22 08:29:29 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 375 MB



