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//-----------------------------------------------------------------------------
// Project    : V5-Block Plus for PCI Express
// File       : pcie_clocking.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor      : Xilinx
// \   \   \/     Version     : 1.1
//  \   \         Application : Generated by Xilinx PCI Express Wizard
//  /   /         Filename    : pcie_clocking.v
// /___/   /\     Module      : pcie_clocking
// \   \  /  \
//  \___\/\___\
//
//------------------------------------------------------------------------------

module pcie_clocking #
( parameter    G_DIVIDE_VAL = 2,  // use 2 or 4
  parameter    REF_CLK_FREQ = 1  // use 0 or 1
)

(
  input  clkin_pll,
  input  clkin_dcm,
  input  rst,
  
  output coreclk,
  output userclk,
  output gtx_usrclk,
  output txsync_clk,
  output locked,
  input  fast_train_simulation_only
 );
 

  wire clkfbout;
  wire clkfbin;
  wire clkout0;
  wire clkout1;
  wire clkout2;
  wire txsync_clkout;

  
  wire clk0;
  wire clkfb;
  wire clkdv;
  wire [15:0] not_connected;
  
  reg  [7:0]  lock_wait_cntr_7_0;
  reg  [7:0]  lock_wait_cntr_15_8;
  reg         pll_locked_out_r;
  reg         pll_locked_out_r_d;
  reg         pll_locked_out_r_2d;
  reg         time_elapsed;


  parameter G_DVIDED_VAL_PLL = G_DIVIDE_VAL*2;
  
   generate
       begin : use_pll

        // CALCULATED WAY (easier): must use bitgen -g plladv_xNyM_use_calc:Yes to enable this attribute
       // synthesis attribute CLKOUT1_DIVIDE pll1 "4";
       // synthesis attribute CLKOUT1_PHASE pll1 "0";
       // synthesis attribute CLKOUT1_DUTY_CYCLE pll1 "0.5";

       // synthesis attribute PLL_OPT_INV pll1 "001001";
       // synthesis attribute PLL_CP pll1 "2";
       // synthesis attribute PLL_RES pll1 "8";

          PLL_ADV #
          (
            // 5 for 100 MHz, 2 for 250 MHz
            .CLKFBOUT_MULT (5-(REF_CLK_FREQ*3)),
            .CLKFBOUT_PHASE(0),
            
            // 10 for 100 MHz, 4 for 250 MHz
            .CLKIN1_PERIOD (10-(REF_CLK_FREQ*6)),
            .CLKIN2_PERIOD (10-(REF_CLK_FREQ*6)),
            
            .CLKOUT0_DIVIDE(2),
            .CLKOUT0_PHASE (0),
            
            .CLKOUT1_DIVIDE(G_DVIDED_VAL_PLL),
            .CLKOUT1_PHASE (0),

            .CLKOUT2_DIVIDE (4), // always 125 MHz for gtx_usrclk
            .CLKOUT2_PHASE (0),

            .CLKOUT3_DIVIDE (4), // always 125 MHz for tx_sync
            .CLKOUT3_PHASE (0)
            
            // .PLL_OPT_INV   (6'b001000),
         
          )
          pll_adv_i
          (
            .CLKIN1(clkin_pll),
            .CLKINSEL(1'b1),
            .CLKFBIN(clkfbin),
            .RST(rst),
            .CLKOUT0(clkout0),
            .CLKOUT1(clkout1),
            .CLKOUT2(clkout2),
            .CLKOUT3(txsync_clkout),
            .CLKFBOUT(clkfbout),
            //.LOCKED(locked)
            .LOCKED(pll_lk_out)
          );
          // PLL w/ internal feedback loop per UG190 Fig 3-11
          assign clkfbin = clkfbout;

          BUFG coreclk_pll_bufg  (.O(coreclk),    .I(clkout0)); // 250 MHz
          BUFG gtxclk_pll_bufg   (.O(gtx_usrclk), .I(clkout2));  // 125 MHz
          BUFG txsync_clk_pll_bufg   (.O(txsync_clk), .I(txsync_clkout));  // txsync_clk

      if (REF_CLK_FREQ == 1) // 250Mhz
      begin
          // lock not valid until 100us after PLL is released from reset
          always @(posedge clkin_pll or posedge rst)
          begin
             if(rst) 
             begin
                lock_wait_cntr_7_0  <= 8'h0;
                lock_wait_cntr_15_8 <= 8'h0;
                pll_locked_out_r  <= 1'b0;
                time_elapsed      <= 1'b0;
             end else begin
                if ((lock_wait_cntr_15_8 == 8'h80) | time_elapsed)
                begin
                   pll_locked_out_r <= pll_lk_out;
                   time_elapsed     <= 1'b1;
                end else begin
                   lock_wait_cntr_7_0  <= lock_wait_cntr_7_0 + 1'b1;
                   lock_wait_cntr_15_8 <= (lock_wait_cntr_7_0 == 8'hff) ?
                       (lock_wait_cntr_15_8 + 1'b1) : lock_wait_cntr_15_8;
                end
             end
          end
      end
      else  // 100Mhz
      begin
          // lock not valid until 100us after PLL is released from reset
          always @(posedge clkin_pll or posedge rst)
          begin
             if(rst) 
             begin
                lock_wait_cntr_7_0  <= 8'h0;
                lock_wait_cntr_15_8 <= 8'h0;
                pll_locked_out_r  <= 1'b0;
                time_elapsed      <= 1'b0;
             end else begin
                if ((lock_wait_cntr_15_8 == 8'h33) | time_elapsed)
                begin
                   pll_locked_out_r <= pll_lk_out;
                   time_elapsed     <= 1'b1;
                end else begin
                   lock_wait_cntr_7_0  <= lock_wait_cntr_7_0 + 1'b1;
                   lock_wait_cntr_15_8 <= (lock_wait_cntr_7_0 == 8'hff) ?
                       (lock_wait_cntr_15_8 + 1'b1) : lock_wait_cntr_15_8;
                end
             end
          end
      end
          // bring locked into PLL output domain
          always @(posedge coreclk or posedge rst)
          begin
             if (rst)
             begin
                pll_locked_out_r_d  <= 0;
                pll_locked_out_r_2d <= 0;
             end
             else
             begin
                pll_locked_out_r_d  <= pll_locked_out_r;
                pll_locked_out_r_2d <= pll_locked_out_r_d;
             end
          end

            assign locked = fast_train_simulation_only ?
                                     pll_lk_out : pll_locked_out_r_2d;

       end   


   endgenerate      






   generate
     if (G_DIVIDE_VAL == 1)
      begin : sameclk
        assign userclk = coreclk;
      end
     else
      begin : notsame
        BUFG usrclk_pll_bufg (.O(userclk), .I(clkout1)); // 125 MHz or 62.5 MHz
      end
   endgenerate

endmodule

