[AHDL]
Type=Implementation
Handle=132884
Project=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\ambpex5_v20_sx50t_core.adf
[Xilinx]
Path=C:\Xilinx\13.1\ISE_DS\ISE\bin\nt
[GUI]
AutoClose=0
[ChipScope]
InserterEnable=1
InserterGuiEnable=1
NetlistMergingEnable=1
InserterProjectPath=e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/synthesis/ambpex5_v20_sx50t_core.cdc
UseInserterBat=0
BinariesFolder=C:\Xilinx\13.1\ISE_DS\ISE\bin\nt
[Design.PartSelector]
Family=VIRTEX5
Device=5vsx50tff1136
Speed=-1
Part=5vsx50tff1136-1
[Design.Input]
Netlist=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core.ngc
UCF=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\src\top\ambpex5_v20_sx50t_core.ucf
OutputPath=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\implement
OutputRelativePath=implement
StdOutputFile=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\log\implementation.htm
Version=ver1
Revision=rev1
Format=None
EffortLevel=2
InputTristateTermMode=Keeper
UnusedIOPadTermMode=Keeper
Mode=batch
SDF_path=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\implement
Corelate=1
ExeName=ise.exe
ImplToolName=MV_ISE122
SynthToolName=MV_XST122
DirectoryList={e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis} {e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\compile} {e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\src}
DestinationPath=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\implement
SynthesisPath=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis
ClbPackingStrategy=100
PackClbRegisters=0
UseBufg=0
IgnoreRlocConstr=1
DetailedReport=0
Place_And_Route_Mode=Route Only
dont_run_translate=1
dont_run_map=1
dont_run_place=0
dont_run_trace=0
dont_run_post_map_trace=1
dont_run_simulation=1
dont_run_fit=0
dont_run_bitgen=0
use_ngdbuild_file=0
use_par_file=0
use_map_file=0
use_post_map_file=0
use_trace_file=0
use_netgen_file=0
use_cpld_ndg2vhdl_file=0
use_cgsm_ndg2vhdl_file=0
use_bitgen_file=1
use_use_cpldfit_file=0
use_hprep6_file=0
use_tsim_file=0
bitgen_file_str=e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\implement\ver1\rev1\bitgen.bat
Generate_Asynchronous_Delay_Report=0
Generate_Clock_Region_Report=0
DoCopyGlblFile=0
[Engine.Command]
Command=Implement
[Ngdbuild]
Switches=  -aul  -sd "e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\src\pcie_src\components\coregen" -sd "e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\src\adm\coregen"  
[Map]
Switches=  -pr b  -ol high  -cm speed  -ir off    -detail  -t 1  -global_opt speed  -retiming on  -equivalent_register_removal on  -lc auto  -mt off 
[PostMap]
Switches=  -v 3  -s 2  -n 3  -fastpaths 
[Par]
Switches=  -ol high  -p  -mt off 
[PostPar]
Switches=  -e 32  -s  1  -n 3  -fastpaths 
[FPGANetgenGeneral]
Switches= 
[FPGANetgenVhdl]
Switches=  -tpw 0  -rpw 100  -s  2  -ar  Structure  -insert_pp_buffers true 
[FPGABitgen]
Switches=  -g Binary:No  -g IEEE1532:No  -g Compress  -g CRC:Enable  -g Security:None  -g Encrypt:No  -g JTAG_SysMon:Enable  -g StartupClk:Cclk  -g DonePipe:No  -g DONE_cycle:4  -g GTS_cycle:5  -g GWE_cycle:6  -g LCK_cycle:NoWait  -g Match_cycle:Auto  -g DriveDone:Yes  -g ConfigRate:2  -g CclkPin:Pullup  -g M0Pin:Pullup  -g M1Pin:Pullup  -g M2Pin:Pullup  -g ProgPin:Pullup  -g DonePin:Pullup  -g HswapenPin:Pullup  -g InitPin:Pullup  -g CsPin:Pullup  -g DinPin:Pullup  -g BusyPin:Pullup  -g RdWrPin:Pullup  -g TckPin:Pullup  -g TdiPin:Pullup  -g TdoPin:Pullup  -g TmsPin:Pullup  -g UnusedPin:Pullup  -g UserID:0xFFFFFFFF  -g DCIUpdateMode:AsRequired  -g ConfigFallback:Enable  -g SelectMAPAbort:Enable  -g BPI_page_size:1  -g OverTempPowerDown:Disable 
[Engine.Implement.Output]
Changed=1
Stage=Configure
State=OK
Abort=NO
Errors=0
Warnings=58
Status=Warning
[Engine.Reports.Output]
Path=implement/ver1/rev1
Files=netlist_merging.log chipscope.log map.mrp implementation.htm
Names={Netlist Merging} Insertion Map {Implement Log}
