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//-----------------------------------------------------------------------------
// Project    : V5-Block Plus for PCI Express
// File       : pcie_blk_cf_pwr.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//--
//-- Description: PCIe Block Power Management Interface
//--
//--             
//--
//--------------------------------------------------------------------------------

`timescale 1ns/1ns
`ifndef TCQ
 `define TCQ 1
`endif

module pcie_blk_cf_pwr
(
       // Clock and reset

       input              clk,
       input              rst_n,

       // User Interface Power Management Ports
       
       input              cfg_turnoff_ok_n,
       output reg         cfg_to_turnoff_n,

       input              cfg_pm_wake_n,


       // PCIe Block Power Management Ports

       input              l0_pwr_turn_off_req,

       output reg         l0_pme_req_in,
       input              l0_pme_ack,

       // Interface to arbiter
       output reg         send_pmeack,
       input              cs_is_pm,
       input              grant
); 

always @(posedge clk)
begin
  if (~rst_n) begin
    cfg_to_turnoff_n    <= #`TCQ 1;
    send_pmeack         <= #`TCQ 0;
    l0_pme_req_in       <= #`TCQ 0;
  end else begin
    //PME Turn Off message rec'd; inform user
    if (l0_pwr_turn_off_req)
      cfg_to_turnoff_n    <= #`TCQ 0;
    else if (~cfg_turnoff_ok_n)
      cfg_to_turnoff_n    <= #`TCQ 1;
    //User issues PME To ACK
    if (~cfg_turnoff_ok_n && ~cfg_to_turnoff_n)
      send_pmeack         <= #`TCQ 1;
    else if (cs_is_pm && grant)
      send_pmeack         <= #`TCQ 0;
    //Send a PM PME message
    if (~cfg_pm_wake_n)
      l0_pme_req_in       <= #`TCQ 1;
    else if (l0_pme_ack)
      l0_pme_req_in       <= #`TCQ 0;
  end
end

endmodule // pcie_blk_cf_pwr

