<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="impact" timeStamp="Thu Sep 22 09:32:28 2011">
<section name="Project Information" visible="false">
<property name="ProjectID" value="778406d560954ad3b306b1a2b51c26e9"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
<property name="Use Project File" value="Yes"/>
<property name="Project Entry" value="Stand Alone"/>
<property name="OS Name" value="Microsoft Windows 7"/>
<property name="User Lic. Info" value="_"/>
</section>
<section name="iMPACT One Step SVF File Mode" visible="true">
<item name="Chain Summary">
<property name="Number of device" value="2"/>
<property name="Number of Xilinx device" value="2"/>
<property name="Number of Non-Xilinx device" value="0"/>
</item>
<item name="Chain Description">
<property name="Device1" value="xcfp"/>
<property name="Part1" value="xcf32p"/>
<property name="Use XCF00P as" value="Regular PROM"/>
<property name="Device2" value="virtex5"/>
<property name="Part2" value="xc5vsx50t"/>
</item>
<item name="Boundary Scan Operations Statistics">
<property name="BSCAN Operation" value="Verify -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0 -e -v -loadfpga -parallel -master -internalClk -clkFreq 40 -defaultVersion 0
"/>
</item>
<item name="Cable Summary">
<property name="Cable Type" value="Platform Cable USB"/>
<property name="Cable Speed" value="6 MHz"/>
<property name="Port" value="usb-hs"/>
<property name="Local_Server_Mode" value="Local"/>
</item>
</section>
</application>
</document>
