--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: O.40d
--  \   \         Application: netgen
--  /   /         Filename: ambpex5_v20_sx50t_core.vhd
-- /___/   /\     Timestamp: Thu Sep 22 07:33:28 2011
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -ofmt vhdl -intstyle silent -w ambpex5_v20_sx50t_core.ngc ambpex5_v20_sx50t_core.vhd 
-- Device	: xc5vsx50tff1136-1
-- Input file	: ambpex5_v20_sx50t_core.ngc
-- Output file	: ambpex5_v20_sx50t_core.vhd
-- # of Entities	: 156
-- Design Name	: ambpex5_v20_sx50t_core
-- Xilinx	: C:\Xilinx\13.1\ISE_DS\ISE\
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_soft_cf_int is
  port (
    clk : in STD_LOGIC := 'X'; 
    signaledint : out STD_LOGIC; 
    rst_n : in STD_LOGIC := 'X'; 
    intr_req_valid : out STD_LOGIC; 
    legacy_int_request : out STD_LOGIC; 
    msi_8bit_en : in STD_LOGIC := 'X'; 
    cfg_interrupt_msienable : out STD_LOGIC; 
    cfg_interrupt_n : in STD_LOGIC := 'X'; 
    cs_is_intr : in STD_LOGIC := 'X'; 
    msi_enable : in STD_LOGIC := 'X'; 
    cfg_interrupt_rdy_n : out STD_LOGIC; 
    grant : in STD_LOGIC := 'X'; 
    cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    intr_vector : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    msi_request : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    intr_req_type : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    cfg_msguaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    msi_laddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    msi_haddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_msgctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_msgdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end pcie_soft_cf_int;

architecture STRUCTURE of pcie_soft_cf_int is
  signal Q_and0000 : STD_LOGIC; 
  signal NlwRenamedSignal_cfg_interrupt_msienable : STD_LOGIC; 
  signal intr_rdy : STD_LOGIC; 
  signal u_cmm_intr_not0000 : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd4_In : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd4_20586 : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd3_In : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd2_In : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd2_20582 : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd1_In : STD_LOGIC; 
  signal u_cmm_intr_state_FSM_FFd1_20580 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_73_20578 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_62_20577 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_40_20576 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_29_20575 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_11_20574 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_100_20573 : STD_LOGIC; 
  signal u_cmm_intr_q_intr_req_type_0_0_20572 : STD_LOGIC; 
  signal u_cmm_intr_intr_req_q_20511 : STD_LOGIC; 
  signal u_cmm_intr_intr_req : STD_LOGIC; 
  signal u_cmm_intr_intr_rdyx_and0000 : STD_LOGIC; 
  signal u_cmm_intr_intr_rdy_q_20507 : STD_LOGIC; 
  signal u_cmm_intr_cfg_interrupt_assert_n_q_20498 : STD_LOGIC; 
  signal u_cmm_intr_allow_int_or0000 : STD_LOGIC; 
  signal u_cmm_intr_allow_int_20495 : STD_LOGIC; 
  signal u_cmm_intr_N3 : STD_LOGIC; 
  signal NlwRenamedSignal_cfg_interrupt_do : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSignal_cfg_interrupt_mmenable : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal NlwRenamedSig_OI_intr_req_type : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal NlwRenamedSignal_msi_request : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal u_cmm_intr_intr_vector_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  legacy_int_request <= NlwRenamedSignal_msi_request(0);
  cfg_interrupt_msienable <= NlwRenamedSignal_cfg_interrupt_msienable;
  cfg_interrupt_do(7) <= NlwRenamedSignal_cfg_interrupt_do(7);
  cfg_interrupt_do(6) <= NlwRenamedSignal_cfg_interrupt_do(6);
  cfg_interrupt_do(5) <= NlwRenamedSignal_cfg_interrupt_do(5);
  cfg_interrupt_do(4) <= NlwRenamedSignal_cfg_interrupt_do(4);
  cfg_interrupt_do(3) <= NlwRenamedSignal_cfg_interrupt_do(3);
  cfg_interrupt_do(2) <= NlwRenamedSignal_cfg_interrupt_do(2);
  cfg_interrupt_do(1) <= NlwRenamedSignal_cfg_interrupt_do(1);
  cfg_interrupt_do(0) <= NlwRenamedSignal_cfg_interrupt_do(0);
  cfg_interrupt_mmenable(2) <= NlwRenamedSignal_cfg_interrupt_mmenable(2);
  cfg_interrupt_mmenable(1) <= NlwRenamedSignal_cfg_interrupt_mmenable(1);
  cfg_interrupt_mmenable(0) <= NlwRenamedSignal_cfg_interrupt_mmenable(0);
  msi_request(3) <= NlwRenamedSignal_msi_request(0);
  msi_request(2) <= NlwRenamedSignal_msi_request(0);
  msi_request(1) <= NlwRenamedSignal_msi_request(0);
  msi_request(0) <= NlwRenamedSignal_msi_request(0);
  intr_req_type(1) <= NlwRenamedSig_OI_intr_req_type(1);
  NlwRenamedSignal_cfg_interrupt_mmenable(2) <= cfg_msgctrl(6);
  NlwRenamedSignal_cfg_interrupt_mmenable(1) <= cfg_msgctrl(5);
  NlwRenamedSignal_cfg_interrupt_mmenable(0) <= cfg_msgctrl(4);
  NlwRenamedSignal_cfg_interrupt_msienable <= cfg_msgctrl(0);
  NlwRenamedSignal_cfg_interrupt_do(7) <= cfg_msgdata(7);
  NlwRenamedSignal_cfg_interrupt_do(6) <= cfg_msgdata(6);
  NlwRenamedSignal_cfg_interrupt_do(5) <= cfg_msgdata(5);
  NlwRenamedSignal_cfg_interrupt_do(4) <= cfg_msgdata(4);
  NlwRenamedSignal_cfg_interrupt_do(3) <= cfg_msgdata(3);
  NlwRenamedSignal_cfg_interrupt_do(2) <= cfg_msgdata(2);
  NlwRenamedSignal_cfg_interrupt_do(1) <= cfg_msgdata(1);
  NlwRenamedSignal_cfg_interrupt_do(0) <= cfg_msgdata(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSignal_msi_request(0)
    );
  Q_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => grant,
      I1 => cs_is_intr,
      O => Q_and0000
    );
  cfg_interrupt_rdy_n1_INV_0 : INV
    port map (
      I => intr_rdy,
      O => cfg_interrupt_rdy_n
    );
  u_cmm_intr_not00001_INV_0 : INV
    port map (
      I => rst_n,
      O => u_cmm_intr_not0000
    );
  u_cmm_intr_q_intr_req_type_0_120 : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => u_cmm_intr_q_intr_req_type_0_100_20573,
      I1 => cfg_msgctrl(7),
      I2 => NlwRenamedSig_OI_intr_req_type(1),
      I3 => u_cmm_intr_state_FSM_FFd1_20580,
      O => intr_req_type(0)
    );
  u_cmm_intr_q_intr_req_type_0_100 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => u_cmm_intr_q_intr_req_type_0_0_20572,
      I1 => u_cmm_intr_q_intr_req_type_0_11_20574,
      I2 => u_cmm_intr_q_intr_req_type_0_29_20575,
      I3 => u_cmm_intr_q_intr_req_type_0_40_20576,
      I4 => u_cmm_intr_q_intr_req_type_0_62_20577,
      I5 => u_cmm_intr_q_intr_req_type_0_73_20578,
      O => u_cmm_intr_q_intr_req_type_0_100_20573
    );
  u_cmm_intr_q_intr_req_type_0_73 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msi_haddr(24),
      I1 => msi_haddr(25),
      I2 => msi_haddr(26),
      I3 => msi_haddr(27),
      I4 => msi_haddr(4),
      I5 => msi_haddr(5),
      O => u_cmm_intr_q_intr_req_type_0_73_20578
    );
  u_cmm_intr_q_intr_req_type_0_62 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msi_haddr(6),
      I1 => msi_haddr(7),
      I2 => msi_haddr(8),
      I3 => msi_haddr(9),
      I4 => msi_haddr(0),
      I5 => msi_haddr(10),
      O => u_cmm_intr_q_intr_req_type_0_62_20577
    );
  u_cmm_intr_q_intr_req_type_0_40 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msi_haddr(13),
      I1 => msi_haddr(14),
      I2 => msi_haddr(15),
      I3 => msi_haddr(16),
      I4 => msi_haddr(28),
      I5 => msi_haddr(29),
      O => u_cmm_intr_q_intr_req_type_0_40_20576
    );
  u_cmm_intr_q_intr_req_type_0_29 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msi_haddr(2),
      I1 => msi_haddr(30),
      I2 => msi_haddr(31),
      I3 => msi_haddr(3),
      I4 => msi_haddr(22),
      I5 => msi_haddr(23),
      O => u_cmm_intr_q_intr_req_type_0_29_20575
    );
  u_cmm_intr_q_intr_req_type_0_11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msi_haddr(19),
      I1 => msi_haddr(1),
      I2 => msi_haddr(20),
      I3 => msi_haddr(21),
      I4 => msi_haddr(11),
      I5 => msi_haddr(12),
      O => u_cmm_intr_q_intr_req_type_0_11_20574
    );
  u_cmm_intr_q_intr_req_type_0_0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => msi_haddr(17),
      I1 => msi_haddr(18),
      O => u_cmm_intr_q_intr_req_type_0_0_20572
    );
  u_cmm_intr_q_intr_req_valid1 : LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      I0 => Q_and0000,
      I1 => NlwRenamedSig_OI_intr_req_type(1),
      I2 => u_cmm_intr_state_FSM_FFd2_20582,
      I3 => u_cmm_intr_state_FSM_FFd1_20580,
      O => intr_req_valid
    );
  u_cmm_intr_state_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"FDFFA8AA"
    )
    port map (
      I0 => u_cmm_intr_state_FSM_FFd4_20586,
      I1 => u_cmm_intr_intr_rdy_q_20507,
      I2 => intr_rdy,
      I3 => u_cmm_intr_intr_req_q_20511,
      I4 => Q_and0000,
      O => u_cmm_intr_state_FSM_FFd4_In
    );
  u_cmm_intr_state_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"4444F444"
    )
    port map (
      I0 => Q_and0000,
      I1 => u_cmm_intr_state_FSM_FFd1_20580,
      I2 => u_cmm_intr_N3,
      I3 => u_cmm_intr_cfg_interrupt_assert_n_q_20498,
      I4 => NlwRenamedSignal_cfg_interrupt_msienable,
      O => u_cmm_intr_state_FSM_FFd1_In
    );
  u_cmm_intr_state_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"02FF0202"
    )
    port map (
      I0 => u_cmm_intr_N3,
      I1 => NlwRenamedSignal_cfg_interrupt_msienable,
      I2 => u_cmm_intr_cfg_interrupt_assert_n_q_20498,
      I3 => Q_and0000,
      I4 => u_cmm_intr_state_FSM_FFd2_20582,
      O => u_cmm_intr_state_FSM_FFd2_In
    );
  u_cmm_intr_intr_rdyx_and00001 : LUT4
    generic map(
      INIT => X"CCC8"
    )
    port map (
      I0 => NlwRenamedSig_OI_intr_req_type(1),
      I1 => Q_and0000,
      I2 => u_cmm_intr_state_FSM_FFd2_20582,
      I3 => u_cmm_intr_state_FSM_FFd1_20580,
      O => u_cmm_intr_intr_rdyx_and0000
    );
  u_cmm_intr_state_FSM_FFd1_In11 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => u_cmm_intr_intr_req_q_20511,
      I1 => intr_rdy,
      I2 => u_cmm_intr_intr_rdy_q_20507,
      I3 => u_cmm_intr_state_FSM_FFd4_20586,
      O => u_cmm_intr_N3
    );
  u_cmm_intr_state_FSM_FFd3_In1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_msienable,
      I1 => u_cmm_intr_N3,
      I2 => Q_and0000,
      I3 => NlwRenamedSig_OI_intr_req_type(1),
      O => u_cmm_intr_state_FSM_FFd3_In
    );
  u_cmm_intr_intr_vector_mux0000_0_1 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_msienable,
      I1 => NlwRenamedSignal_cfg_interrupt_do(0),
      I2 => NlwRenamedSignal_cfg_interrupt_mmenable(0),
      I3 => NlwRenamedSignal_cfg_interrupt_mmenable(1),
      I4 => NlwRenamedSignal_cfg_interrupt_mmenable(2),
      O => u_cmm_intr_intr_vector_mux0000(0)
    );
  u_cmm_intr_intr_vector_mux0000_2_1 : LUT5
    generic map(
      INIT => X"00404040"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_mmenable(2),
      I1 => NlwRenamedSignal_cfg_interrupt_msienable,
      I2 => NlwRenamedSignal_cfg_interrupt_do(2),
      I3 => NlwRenamedSignal_cfg_interrupt_mmenable(0),
      I4 => NlwRenamedSignal_cfg_interrupt_mmenable(1),
      O => u_cmm_intr_intr_vector_mux0000(2)
    );
  u_cmm_intr_intr_vector_mux0000_4_1 : LUT5
    generic map(
      INIT => X"00088888"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_msienable,
      I1 => NlwRenamedSignal_cfg_interrupt_do(4),
      I2 => NlwRenamedSignal_cfg_interrupt_mmenable(1),
      I3 => NlwRenamedSignal_cfg_interrupt_mmenable(0),
      I4 => NlwRenamedSignal_cfg_interrupt_mmenable(2),
      O => u_cmm_intr_intr_vector_mux0000(4)
    );
  u_cmm_intr_intr_vector_mux0000_1_1 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_do(1),
      I1 => NlwRenamedSignal_cfg_interrupt_mmenable(1),
      I2 => NlwRenamedSignal_cfg_interrupt_mmenable(2),
      I3 => NlwRenamedSignal_cfg_interrupt_msienable,
      O => u_cmm_intr_intr_vector_mux0000(1)
    );
  u_cmm_intr_allow_int_or00001 : LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_msienable,
      I1 => cfg_command(10),
      I2 => cfg_command(2),
      O => u_cmm_intr_allow_int_or0000
    );
  u_cmm_intr_intr_vector_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_msienable,
      I1 => NlwRenamedSignal_cfg_interrupt_do(3),
      I2 => NlwRenamedSignal_cfg_interrupt_mmenable(2),
      O => u_cmm_intr_intr_vector_mux0000(3)
    );
  u_cmm_intr_intr_req1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cfg_interrupt_n,
      I1 => u_cmm_intr_allow_int_20495,
      O => u_cmm_intr_intr_req
    );
  u_cmm_intr_intr_vector_mux0000_5_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_do(5),
      I1 => NlwRenamedSignal_cfg_interrupt_msienable,
      O => u_cmm_intr_intr_vector_mux0000(5)
    );
  u_cmm_intr_intr_vector_mux0000_6_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_do(6),
      I1 => NlwRenamedSignal_cfg_interrupt_msienable,
      O => u_cmm_intr_intr_vector_mux0000(6)
    );
  u_cmm_intr_intr_vector_mux0000_7_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSignal_cfg_interrupt_do(7),
      I1 => NlwRenamedSignal_cfg_interrupt_msienable,
      O => u_cmm_intr_intr_vector_mux0000(7)
    );
  u_cmm_intr_state_FSM_FFd4 : FDS
    port map (
      C => clk,
      D => u_cmm_intr_state_FSM_FFd4_In,
      S => u_cmm_intr_not0000,
      Q => u_cmm_intr_state_FSM_FFd4_20586
    );
  u_cmm_intr_state_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => u_cmm_intr_state_FSM_FFd3_In,
      R => u_cmm_intr_not0000,
      Q => NlwRenamedSig_OI_intr_req_type(1)
    );
  u_cmm_intr_state_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => u_cmm_intr_state_FSM_FFd2_In,
      R => u_cmm_intr_not0000,
      Q => u_cmm_intr_state_FSM_FFd2_20582
    );
  u_cmm_intr_state_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => u_cmm_intr_state_FSM_FFd1_In,
      R => u_cmm_intr_not0000,
      Q => u_cmm_intr_state_FSM_FFd1_20580
    );
  u_cmm_intr_intr_rdy_q : FDR
    port map (
      C => clk,
      D => intr_rdy,
      R => u_cmm_intr_not0000,
      Q => u_cmm_intr_intr_rdy_q_20507
    );
  u_cmm_intr_intr_vector_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(7),
      Q => intr_vector(7)
    );
  u_cmm_intr_intr_vector_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(6),
      Q => intr_vector(6)
    );
  u_cmm_intr_intr_vector_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(5),
      Q => intr_vector(5)
    );
  u_cmm_intr_intr_vector_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(4),
      Q => intr_vector(4)
    );
  u_cmm_intr_intr_vector_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(3),
      Q => intr_vector(3)
    );
  u_cmm_intr_intr_vector_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(2),
      Q => intr_vector(2)
    );
  u_cmm_intr_intr_vector_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(1),
      Q => intr_vector(1)
    );
  u_cmm_intr_intr_vector_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => u_cmm_intr_intr_req_q_20511,
      D => u_cmm_intr_intr_vector_mux0000(0),
      Q => intr_vector(0)
    );
  u_cmm_intr_cfg_interrupt_assert_n_q : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_interrupt_assert_n,
      PRE => u_cmm_intr_not0000,
      Q => u_cmm_intr_cfg_interrupt_assert_n_q_20498
    );
  u_cmm_intr_intr_rdyx : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => u_cmm_intr_not0000,
      D => u_cmm_intr_intr_rdyx_and0000,
      Q => intr_rdy
    );
  u_cmm_intr_allow_int : FDC
    port map (
      C => clk,
      CLR => u_cmm_intr_not0000,
      D => u_cmm_intr_allow_int_or0000,
      Q => u_cmm_intr_allow_int_20495
    );
  u_cmm_intr_intr_req_q : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => u_cmm_intr_not0000,
      D => u_cmm_intr_intr_req,
      Q => u_cmm_intr_intr_req_q_20511
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_ram8x26 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    we : in STD_LOGIC := 'X'; 
    rddata : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
    wrdata : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
    rd_ptr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    wr_ptr : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_ram8x26;

architecture STRUCTURE of cmm_errman_ram8x26 is
  signal N0_0 : STD_LOGIC; 
  signal \Q_varindex0000_12)\ : STD_LOGIC; 
  signal \Q_varindex0000_13)\ : STD_LOGIC; 
  signal \Q_varindex0000_14)\ : STD_LOGIC; 
  signal \Q_varindex0000_15)\ : STD_LOGIC; 
  signal \Q_varindex0000_16)\ : STD_LOGIC; 
  signal \Q_varindex0000_17)\ : STD_LOGIC; 
  signal \Q_varindex0000_48)\ : STD_LOGIC; 
  signal NLW_Mram_lutram_data3_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data3_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data91_SPO_UNCONNECTED : STD_LOGIC; 
  signal reg_rdata : STD_LOGIC_VECTOR ( 49 downto 0 ); 
begin
  rddata(49) <= reg_rdata(49);
  rddata(48) <= reg_rdata(48);
  rddata(47) <= reg_rdata(47);
  rddata(46) <= reg_rdata(46);
  rddata(45) <= reg_rdata(45);
  rddata(44) <= reg_rdata(44);
  rddata(43) <= reg_rdata(43);
  rddata(42) <= reg_rdata(42);
  rddata(41) <= reg_rdata(41);
  rddata(40) <= reg_rdata(40);
  rddata(39) <= reg_rdata(39);
  rddata(38) <= reg_rdata(38);
  rddata(37) <= reg_rdata(37);
  rddata(36) <= reg_rdata(36);
  rddata(35) <= reg_rdata(35);
  rddata(34) <= reg_rdata(34);
  rddata(33) <= reg_rdata(33);
  rddata(32) <= reg_rdata(32);
  rddata(31) <= reg_rdata(31);
  rddata(30) <= reg_rdata(30);
  rddata(29) <= reg_rdata(29);
  rddata(28) <= reg_rdata(28);
  rddata(27) <= reg_rdata(27);
  rddata(26) <= reg_rdata(26);
  rddata(25) <= reg_rdata(25);
  rddata(24) <= reg_rdata(24);
  rddata(23) <= reg_rdata(23);
  rddata(22) <= reg_rdata(22);
  rddata(21) <= reg_rdata(21);
  rddata(20) <= reg_rdata(20);
  rddata(19) <= reg_rdata(19);
  rddata(18) <= reg_rdata(18);
  rddata(17) <= reg_rdata(17);
  rddata(16) <= reg_rdata(16);
  rddata(15) <= reg_rdata(15);
  rddata(14) <= reg_rdata(14);
  rddata(13) <= reg_rdata(13);
  rddata(12) <= reg_rdata(12);
  rddata(11) <= reg_rdata(11);
  rddata(10) <= reg_rdata(10);
  rddata(9) <= reg_rdata(9);
  rddata(8) <= reg_rdata(8);
  rddata(7) <= reg_rdata(7);
  rddata(6) <= reg_rdata(6);
  rddata(5) <= reg_rdata(5);
  rddata(4) <= reg_rdata(4);
  rddata(3) <= reg_rdata(3);
  rddata(2) <= reg_rdata(2);
  rddata(1) <= reg_rdata(1);
  rddata(0) <= reg_rdata(0);
  XST_GND : GND
    port map (
      G => N0_0
    );
  reg_rdata_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(0)
    );
  reg_rdata_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(1)
    );
  reg_rdata_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(2)
    );
  reg_rdata_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(3)
    );
  reg_rdata_4 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(4)
    );
  reg_rdata_5 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(5)
    );
  reg_rdata_6 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(6)
    );
  reg_rdata_7 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(7)
    );
  reg_rdata_8 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(8)
    );
  reg_rdata_9 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(9)
    );
  reg_rdata_10 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(10)
    );
  reg_rdata_11 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(11)
    );
  reg_rdata_12 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(12)
    );
  reg_rdata_13 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(13)
    );
  reg_rdata_14 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(14)
    );
  reg_rdata_15 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(15)
    );
  reg_rdata_16 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(16)
    );
  reg_rdata_17 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(17)
    );
  reg_rdata_18 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(18)
    );
  reg_rdata_19 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(19)
    );
  reg_rdata_20 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(20)
    );
  reg_rdata_21 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(21)
    );
  reg_rdata_22 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(22)
    );
  reg_rdata_23 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(23)
    );
  reg_rdata_24 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(24)
    );
  reg_rdata_25 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(25)
    );
  reg_rdata_26 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(26)
    );
  reg_rdata_27 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(27)
    );
  reg_rdata_28 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(28)
    );
  reg_rdata_29 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(29)
    );
  reg_rdata_30 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(30)
    );
  reg_rdata_31 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(31)
    );
  reg_rdata_32 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(32)
    );
  reg_rdata_33 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(33)
    );
  reg_rdata_34 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(34)
    );
  reg_rdata_35 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(35)
    );
  reg_rdata_36 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(36)
    );
  reg_rdata_37 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(37)
    );
  reg_rdata_38 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(38)
    );
  reg_rdata_39 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(39)
    );
  reg_rdata_40 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(40)
    );
  reg_rdata_41 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(41)
    );
  reg_rdata_42 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_12)\,
      Q => reg_rdata(42)
    );
  reg_rdata_43 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_13)\,
      Q => reg_rdata(43)
    );
  reg_rdata_44 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_14)\,
      Q => reg_rdata(44)
    );
  reg_rdata_45 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_15)\,
      Q => reg_rdata(45)
    );
  reg_rdata_46 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_16)\,
      Q => reg_rdata(46)
    );
  reg_rdata_47 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_17)\,
      Q => reg_rdata(47)
    );
  reg_rdata_48 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_48)\,
      Q => reg_rdata(48)
    );
  reg_rdata_49 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => \Q_varindex0000_48)\,
      Q => reg_rdata(49)
    );
  Mram_lutram_data3 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => N0_0,
      DIA(1) => N0_0,
      DIA(0) => N0_0,
      DIB(1) => N0_0,
      DIB(0) => N0_0,
      DIC(1) => N0_0,
      DIC(0) => N0_0,
      DID(1) => N0_0,
      DID(0) => N0_0,
      ADDRA(4) => N0_0,
      ADDRA(3) => N0_0,
      ADDRA(2) => rd_ptr(2),
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0_0,
      ADDRB(3) => N0_0,
      ADDRB(2) => rd_ptr(2),
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0_0,
      ADDRC(3) => N0_0,
      ADDRC(2) => rd_ptr(2),
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0_0,
      ADDRD(3) => N0_0,
      ADDRD(2) => wr_ptr(2),
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => \Q_varindex0000_13)\,
      DOA(0) => \Q_varindex0000_12)\,
      DOB(1) => \Q_varindex0000_15)\,
      DOB(0) => \Q_varindex0000_14)\,
      DOC(1) => \Q_varindex0000_17)\,
      DOC(0) => \Q_varindex0000_16)\,
      DOD(1) => NLW_Mram_lutram_data3_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data3_DOD_0_UNCONNECTED
    );
  Mram_lutram_data91 : RAM32X1D
    port map (
      A0 => wr_ptr(0),
      A1 => wr_ptr(1),
      A2 => wr_ptr(2),
      A3 => N0_0,
      A4 => N0_0,
      D => N0_0,
      DPRA0 => rd_ptr(0),
      DPRA1 => rd_ptr(1),
      DPRA2 => rd_ptr(2),
      DPRA3 => N0_0,
      DPRA4 => N0_0,
      WCLK => clk,
      WE => N0_0,
      SPO => NLW_Mram_lutram_data91_SPO_UNCONNECTED,
      DPO => \Q_varindex0000_48)\
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_ram4x26 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    we : in STD_LOGIC := 'X'; 
    rddata : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
    wrdata : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
    rd_ptr : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    wr_ptr : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end cmm_errman_ram4x26;

architecture STRUCTURE of cmm_errman_ram4x26 is
  signal N0 : STD_LOGIC; 
  signal NLW_Mram_lutram_data3_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data3_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data1_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data1_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data2_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data2_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data4_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data4_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data5_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data5_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data6_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data6_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data7_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data7_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data8_DOD_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data8_DOD_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data91_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_lutram_data92_SPO_UNCONNECTED : STD_LOGIC; 
  signal Q_varindex0000 : STD_LOGIC_VECTOR ( 49 downto 0 ); 
  signal reg_rdata : STD_LOGIC_VECTOR ( 49 downto 0 ); 
begin
  rddata(49) <= reg_rdata(49);
  rddata(48) <= reg_rdata(48);
  rddata(47) <= reg_rdata(47);
  rddata(46) <= reg_rdata(46);
  rddata(45) <= reg_rdata(45);
  rddata(44) <= reg_rdata(44);
  rddata(43) <= reg_rdata(43);
  rddata(42) <= reg_rdata(42);
  rddata(41) <= reg_rdata(41);
  rddata(40) <= reg_rdata(40);
  rddata(39) <= reg_rdata(39);
  rddata(38) <= reg_rdata(38);
  rddata(37) <= reg_rdata(37);
  rddata(36) <= reg_rdata(36);
  rddata(35) <= reg_rdata(35);
  rddata(34) <= reg_rdata(34);
  rddata(33) <= reg_rdata(33);
  rddata(32) <= reg_rdata(32);
  rddata(31) <= reg_rdata(31);
  rddata(30) <= reg_rdata(30);
  rddata(29) <= reg_rdata(29);
  rddata(28) <= reg_rdata(28);
  rddata(27) <= reg_rdata(27);
  rddata(26) <= reg_rdata(26);
  rddata(25) <= reg_rdata(25);
  rddata(24) <= reg_rdata(24);
  rddata(23) <= reg_rdata(23);
  rddata(22) <= reg_rdata(22);
  rddata(21) <= reg_rdata(21);
  rddata(20) <= reg_rdata(20);
  rddata(19) <= reg_rdata(19);
  rddata(18) <= reg_rdata(18);
  rddata(17) <= reg_rdata(17);
  rddata(16) <= reg_rdata(16);
  rddata(15) <= reg_rdata(15);
  rddata(14) <= reg_rdata(14);
  rddata(13) <= reg_rdata(13);
  rddata(12) <= reg_rdata(12);
  rddata(11) <= reg_rdata(11);
  rddata(10) <= reg_rdata(10);
  rddata(9) <= reg_rdata(9);
  rddata(8) <= reg_rdata(8);
  rddata(7) <= reg_rdata(7);
  rddata(6) <= reg_rdata(6);
  rddata(5) <= reg_rdata(5);
  rddata(4) <= reg_rdata(4);
  rddata(3) <= reg_rdata(3);
  rddata(2) <= reg_rdata(2);
  rddata(1) <= reg_rdata(1);
  rddata(0) <= reg_rdata(0);
  XST_GND : GND
    port map (
      G => N0
    );
  reg_rdata_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(0),
      Q => reg_rdata(0)
    );
  reg_rdata_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(1),
      Q => reg_rdata(1)
    );
  reg_rdata_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(2),
      Q => reg_rdata(2)
    );
  reg_rdata_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(3),
      Q => reg_rdata(3)
    );
  reg_rdata_4 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(4),
      Q => reg_rdata(4)
    );
  reg_rdata_5 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(5),
      Q => reg_rdata(5)
    );
  reg_rdata_6 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(6),
      Q => reg_rdata(6)
    );
  reg_rdata_7 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(7),
      Q => reg_rdata(7)
    );
  reg_rdata_8 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(8),
      Q => reg_rdata(8)
    );
  reg_rdata_9 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(9),
      Q => reg_rdata(9)
    );
  reg_rdata_10 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(10),
      Q => reg_rdata(10)
    );
  reg_rdata_11 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(11),
      Q => reg_rdata(11)
    );
  reg_rdata_12 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(12),
      Q => reg_rdata(12)
    );
  reg_rdata_13 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(13),
      Q => reg_rdata(13)
    );
  reg_rdata_14 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(14),
      Q => reg_rdata(14)
    );
  reg_rdata_15 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(15),
      Q => reg_rdata(15)
    );
  reg_rdata_16 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(16),
      Q => reg_rdata(16)
    );
  reg_rdata_17 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(17),
      Q => reg_rdata(17)
    );
  reg_rdata_18 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(18),
      Q => reg_rdata(18)
    );
  reg_rdata_19 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(19),
      Q => reg_rdata(19)
    );
  reg_rdata_20 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(20),
      Q => reg_rdata(20)
    );
  reg_rdata_21 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(21),
      Q => reg_rdata(21)
    );
  reg_rdata_22 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(22),
      Q => reg_rdata(22)
    );
  reg_rdata_23 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(23),
      Q => reg_rdata(23)
    );
  reg_rdata_24 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(24),
      Q => reg_rdata(24)
    );
  reg_rdata_25 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(25),
      Q => reg_rdata(25)
    );
  reg_rdata_26 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(26),
      Q => reg_rdata(26)
    );
  reg_rdata_27 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(27),
      Q => reg_rdata(27)
    );
  reg_rdata_28 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(28),
      Q => reg_rdata(28)
    );
  reg_rdata_29 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(29),
      Q => reg_rdata(29)
    );
  reg_rdata_30 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(30),
      Q => reg_rdata(30)
    );
  reg_rdata_31 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(31),
      Q => reg_rdata(31)
    );
  reg_rdata_32 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(32),
      Q => reg_rdata(32)
    );
  reg_rdata_33 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(33),
      Q => reg_rdata(33)
    );
  reg_rdata_34 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(34),
      Q => reg_rdata(34)
    );
  reg_rdata_35 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(35),
      Q => reg_rdata(35)
    );
  reg_rdata_36 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(36),
      Q => reg_rdata(36)
    );
  reg_rdata_37 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(37),
      Q => reg_rdata(37)
    );
  reg_rdata_38 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(38),
      Q => reg_rdata(38)
    );
  reg_rdata_39 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(39),
      Q => reg_rdata(39)
    );
  reg_rdata_40 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(40),
      Q => reg_rdata(40)
    );
  reg_rdata_41 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(41),
      Q => reg_rdata(41)
    );
  reg_rdata_42 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(42),
      Q => reg_rdata(42)
    );
  reg_rdata_43 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(43),
      Q => reg_rdata(43)
    );
  reg_rdata_44 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(44),
      Q => reg_rdata(44)
    );
  reg_rdata_45 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(45),
      Q => reg_rdata(45)
    );
  reg_rdata_46 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(46),
      Q => reg_rdata(46)
    );
  reg_rdata_47 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(47),
      Q => reg_rdata(47)
    );
  reg_rdata_48 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(48),
      Q => reg_rdata(48)
    );
  reg_rdata_49 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Q_varindex0000(49),
      Q => reg_rdata(49)
    );
  Mram_lutram_data3 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(13),
      DIA(0) => wrdata(12),
      DIB(1) => wrdata(15),
      DIB(0) => wrdata(14),
      DIC(1) => wrdata(17),
      DIC(0) => wrdata(16),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(13),
      DOA(0) => Q_varindex0000(12),
      DOB(1) => Q_varindex0000(15),
      DOB(0) => Q_varindex0000(14),
      DOC(1) => Q_varindex0000(17),
      DOC(0) => Q_varindex0000(16),
      DOD(1) => NLW_Mram_lutram_data3_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data3_DOD_0_UNCONNECTED
    );
  Mram_lutram_data1 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(1),
      DIA(0) => wrdata(0),
      DIB(1) => wrdata(3),
      DIB(0) => wrdata(2),
      DIC(1) => wrdata(5),
      DIC(0) => wrdata(4),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(1),
      DOA(0) => Q_varindex0000(0),
      DOB(1) => Q_varindex0000(3),
      DOB(0) => Q_varindex0000(2),
      DOC(1) => Q_varindex0000(5),
      DOC(0) => Q_varindex0000(4),
      DOD(1) => NLW_Mram_lutram_data1_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data1_DOD_0_UNCONNECTED
    );
  Mram_lutram_data2 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(7),
      DIA(0) => wrdata(6),
      DIB(1) => wrdata(9),
      DIB(0) => wrdata(8),
      DIC(1) => wrdata(11),
      DIC(0) => wrdata(10),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(7),
      DOA(0) => Q_varindex0000(6),
      DOB(1) => Q_varindex0000(9),
      DOB(0) => Q_varindex0000(8),
      DOC(1) => Q_varindex0000(11),
      DOC(0) => Q_varindex0000(10),
      DOD(1) => NLW_Mram_lutram_data2_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data2_DOD_0_UNCONNECTED
    );
  Mram_lutram_data4 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(19),
      DIA(0) => wrdata(18),
      DIB(1) => wrdata(21),
      DIB(0) => wrdata(20),
      DIC(1) => wrdata(23),
      DIC(0) => wrdata(22),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(19),
      DOA(0) => Q_varindex0000(18),
      DOB(1) => Q_varindex0000(21),
      DOB(0) => Q_varindex0000(20),
      DOC(1) => Q_varindex0000(23),
      DOC(0) => Q_varindex0000(22),
      DOD(1) => NLW_Mram_lutram_data4_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data4_DOD_0_UNCONNECTED
    );
  Mram_lutram_data5 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(25),
      DIA(0) => wrdata(24),
      DIB(1) => wrdata(27),
      DIB(0) => wrdata(26),
      DIC(1) => wrdata(29),
      DIC(0) => wrdata(28),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(25),
      DOA(0) => Q_varindex0000(24),
      DOB(1) => Q_varindex0000(27),
      DOB(0) => Q_varindex0000(26),
      DOC(1) => Q_varindex0000(29),
      DOC(0) => Q_varindex0000(28),
      DOD(1) => NLW_Mram_lutram_data5_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data5_DOD_0_UNCONNECTED
    );
  Mram_lutram_data6 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(31),
      DIA(0) => wrdata(30),
      DIB(1) => wrdata(33),
      DIB(0) => wrdata(32),
      DIC(1) => wrdata(35),
      DIC(0) => wrdata(34),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(31),
      DOA(0) => Q_varindex0000(30),
      DOB(1) => Q_varindex0000(33),
      DOB(0) => Q_varindex0000(32),
      DOC(1) => Q_varindex0000(35),
      DOC(0) => Q_varindex0000(34),
      DOD(1) => NLW_Mram_lutram_data6_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data6_DOD_0_UNCONNECTED
    );
  Mram_lutram_data7 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(37),
      DIA(0) => wrdata(36),
      DIB(1) => wrdata(39),
      DIB(0) => wrdata(38),
      DIC(1) => wrdata(41),
      DIC(0) => wrdata(40),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(37),
      DOA(0) => Q_varindex0000(36),
      DOB(1) => Q_varindex0000(39),
      DOB(0) => Q_varindex0000(38),
      DOC(1) => Q_varindex0000(41),
      DOC(0) => Q_varindex0000(40),
      DOD(1) => NLW_Mram_lutram_data7_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data7_DOD_0_UNCONNECTED
    );
  Mram_lutram_data8 : RAM32M
    generic map(
      INIT_C => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_D => X"0000000000000000",
      INIT_A => X"0000000000000000"
    )
    port map (
      WCLK => clk,
      WE => we,
      DIA(1) => wrdata(43),
      DIA(0) => wrdata(42),
      DIB(1) => wrdata(45),
      DIB(0) => wrdata(44),
      DIC(1) => wrdata(47),
      DIC(0) => wrdata(46),
      DID(1) => N0,
      DID(0) => N0,
      ADDRA(4) => N0,
      ADDRA(3) => N0,
      ADDRA(2) => N0,
      ADDRA(1) => rd_ptr(1),
      ADDRA(0) => rd_ptr(0),
      ADDRB(4) => N0,
      ADDRB(3) => N0,
      ADDRB(2) => N0,
      ADDRB(1) => rd_ptr(1),
      ADDRB(0) => rd_ptr(0),
      ADDRC(4) => N0,
      ADDRC(3) => N0,
      ADDRC(2) => N0,
      ADDRC(1) => rd_ptr(1),
      ADDRC(0) => rd_ptr(0),
      ADDRD(4) => N0,
      ADDRD(3) => N0,
      ADDRD(2) => N0,
      ADDRD(1) => wr_ptr(1),
      ADDRD(0) => wr_ptr(0),
      DOA(1) => Q_varindex0000(43),
      DOA(0) => Q_varindex0000(42),
      DOB(1) => Q_varindex0000(45),
      DOB(0) => Q_varindex0000(44),
      DOC(1) => Q_varindex0000(47),
      DOC(0) => Q_varindex0000(46),
      DOD(1) => NLW_Mram_lutram_data8_DOD_1_UNCONNECTED,
      DOD(0) => NLW_Mram_lutram_data8_DOD_0_UNCONNECTED
    );
  Mram_lutram_data91 : RAM32X1D
    port map (
      A0 => wr_ptr(0),
      A1 => wr_ptr(1),
      A2 => N0,
      A3 => N0,
      A4 => N0,
      D => wrdata(48),
      DPRA0 => rd_ptr(0),
      DPRA1 => rd_ptr(1),
      DPRA2 => N0,
      DPRA3 => N0,
      DPRA4 => N0,
      WCLK => clk,
      WE => we,
      SPO => NLW_Mram_lutram_data91_SPO_UNCONNECTED,
      DPO => Q_varindex0000(48)
    );
  Mram_lutram_data92 : RAM32X1D
    port map (
      A0 => wr_ptr(0),
      A1 => wr_ptr(1),
      A2 => N0,
      A3 => N0,
      A4 => N0,
      D => wrdata(49),
      DPRA0 => rd_ptr(0),
      DPRA1 => rd_ptr(1),
      DPRA2 => N0,
      DPRA3 => N0,
      DPRA4 => N0,
      WCLK => clk,
      WE => we,
      SPO => NLW_Mram_lutram_data92_SPO_UNCONNECTED,
      DPO => Q_varindex0000(49)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cpl_INST_1 is
  port (
    inc_dec_b : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    decr_cpl : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    cmm_err_tlp_posted : in STD_LOGIC := 'X'; 
    cpl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cpl_INST_1;

architecture STRUCTURE of cmm_errman_cpl_INST_1 is
  signal Mrom_COND_127_rom0000 : STD_LOGIC; 
  signal Mrom_COND_127_rom00001 : STD_LOGIC; 
  signal reg_inc_dec_b_19953 : STD_LOGIC; 
  signal reg_cpl_num : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  inc_dec_b <= reg_inc_dec_b_19953;
  cpl_num(0) <= reg_cpl_num(0);
  reg_cpl_num_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Mrom_COND_127_rom00001,
      Q => reg_cpl_num(0)
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Mrom_COND_127_rom0000,
      Q => reg_inc_dec_b_19953
    );
  Mrom_COND_127_rom000012 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => decr_cpl,
      I1 => cmm_err_tlp_posted,
      O => Mrom_COND_127_rom0000
    );
  Mrom_COND_127_rom0000111 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => decr_cpl,
      I1 => cmm_err_tlp_posted,
      O => Mrom_COND_127_rom00001
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cpl is
  port (
    inc_dec_b : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    decr_cpl : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    cmm_err_tlp_posted : in STD_LOGIC := 'X'; 
    cpl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cpl;

architecture STRUCTURE of cmm_errman_cpl is
  signal Mrom_COND_127_rom0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19945 : STD_LOGIC; 
  signal reg_cpl_num : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  inc_dec_b <= reg_inc_dec_b_19945;
  cpl_num(0) <= reg_cpl_num(0);
  reg_cpl_num_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => decr_cpl,
      Q => reg_cpl_num(0)
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Mrom_COND_127_rom0000,
      Q => reg_inc_dec_b_19945
    );
  Mrom_COND_127_rom000011_INV_0 : INV
    port map (
      I => decr_cpl,
      O => Mrom_COND_127_rom0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_ftl is
  port (
    inc_dec_b : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    cmmt_err_tlp_malformed : in STD_LOGIC := 'X'; 
    cmmt_err_fc : in STD_LOGIC := 'X'; 
    cmmt_err_rbuf_overflow : in STD_LOGIC := 'X'; 
    cmmp_training_err : in STD_LOGIC := 'X'; 
    decr_ftl : in STD_LOGIC := 'X'; 
    cmml_protocol_err_n : in STD_LOGIC := 'X'; 
    ftl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_ftl;

architecture STRUCTURE of cmm_errman_ftl is
  signal add_sub_b : STD_LOGIC; 
  signal reg_inc_dec_b_19939 : STD_LOGIC; 
  signal reg_ftl_num : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  inc_dec_b <= reg_inc_dec_b_19939;
  ftl_num(0) <= reg_ftl_num(0);
  reg_ftl_num_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => decr_ftl,
      Q => reg_ftl_num(0)
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => add_sub_b,
      Q => reg_inc_dec_b_19939
    );
  Mrom_COND_126_rom000011_INV_0 : INV
    port map (
      I => decr_ftl,
      O => add_sub_b
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cnt_en_INST_4 is
  port (
    inc_dec_b : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    enable : in STD_LOGIC := 'X'; 
    count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cnt_en_INST_4;

architecture STRUCTURE of cmm_errman_cnt_en_INST_4 is
  signal Madd_AUX_123_addsub0000_cy_0_Q : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy_2_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_0_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_Q : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal reg_extra_19929 : STD_LOGIC; 
  signal reg_extra_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19931 : STD_LOGIC; 
  signal reg_uflow_19932 : STD_LOGIC; 
  signal reg_uflow_and0000_19933 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_lut : STD_LOGIC_VECTOR ( 3 downto 2 ); 
  signal Msub_AUX_124_lut : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cnt : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal reg_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_cnt_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_reg_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_count_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  count(3) <= NlwRenamedSig_OI_reg_count(3);
  count(2) <= NlwRenamedSig_OI_reg_count(2);
  count(1) <= NlwRenamedSig_OI_reg_count(1);
  count(0) <= NlwRenamedSig_OI_reg_count(0);
  reg_cnt_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(3),
      Q => reg_cnt(0)
    );
  reg_cnt_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(2),
      Q => reg_cnt(1)
    );
  reg_cnt_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(1),
      Q => reg_cnt(2)
    );
  reg_cnt_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(0),
      Q => reg_cnt(3)
    );
  reg_extra : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_extra_mux0000,
      Q => reg_extra_19929
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => inc_dec_b,
      Q => reg_inc_dec_b_19931
    );
  reg_uflow : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_uflow_and0000_19933,
      Q => reg_uflow_19932
    );
  reg_count_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(3),
      Q => NlwRenamedSig_OI_reg_count(0)
    );
  reg_count_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(2),
      Q => NlwRenamedSig_OI_reg_count(1)
    );
  reg_count_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(1),
      Q => NlwRenamedSig_OI_reg_count(2)
    );
  reg_count_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(0),
      Q => NlwRenamedSig_OI_reg_count(3)
    );
  cnt_3_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19929,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_uflow_19932,
      I3 => reg_cnt(3),
      O => Madd_AUX_123_addsub0000_lut(3)
    );
  reg_uflow_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_count(1),
      I1 => NlwRenamedSig_OI_reg_count(0),
      I2 => inc_dec_b,
      O => N01
    );
  reg_uflow_and0000 : LUT6
    generic map(
      INIT => X"0101010101010100"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_count(3),
      I1 => NlwRenamedSig_OI_reg_count(2),
      I2 => N01,
      I3 => index(2),
      I4 => index(1),
      I5 => index(0),
      O => reg_uflow_and0000_19933
    );
  reg_extra_mux00001 : LUT5
    generic map(
      INIT => X"80820002"
    )
    port map (
      I0 => enable,
      I1 => inc_dec_b,
      I2 => Madd_AUX_123_addsub0000_lut(3),
      I3 => Msub_AUX_124_cy_2_Q,
      I4 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_extra_mux0000
    );
  reg_cnt_mux0000_0_1 : LUT5
    generic map(
      INIT => X"22828882"
    )
    port map (
      I0 => enable,
      I1 => Madd_AUX_123_addsub0000_lut(3),
      I2 => Msub_AUX_124_cy_2_Q,
      I3 => inc_dec_b,
      I4 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_cnt_mux0000(0)
    );
  cnt_2_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19929,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_uflow_19932,
      I3 => reg_cnt(2),
      O => cnt(2)
    );
  cnt_1_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19929,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_uflow_19932,
      I3 => reg_cnt(1),
      O => cnt(1)
    );
  reg_count_mux0000_3_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_extra_19929,
      I3 => reg_cnt(0),
      I4 => reg_uflow_19932,
      O => reg_count_mux0000(3)
    );
  reg_count_mux0000_2_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_extra_19929,
      I3 => reg_cnt(1),
      I4 => reg_uflow_19932,
      O => reg_count_mux0000(2)
    );
  reg_count_mux0000_1_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_extra_19929,
      I3 => reg_cnt(2),
      I4 => reg_uflow_19932,
      O => reg_count_mux0000(1)
    );
  reg_count_mux0000_0_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_extra_19929,
      I3 => reg_cnt(3),
      I4 => reg_uflow_19932,
      O => reg_count_mux0000(0)
    );
  reg_cnt_mux0000_3_1 : LUT6
    generic map(
      INIT => X"00AA8A208A208A20"
    )
    port map (
      I0 => enable,
      I1 => reg_uflow_19932,
      I2 => reg_cnt(0),
      I3 => index(0),
      I4 => reg_inc_dec_b_19931,
      I5 => reg_extra_19929,
      O => reg_cnt_mux0000(3)
    );
  Msub_AUX_124_cy_0_11 : LUT5
    generic map(
      INIT => X"8F88FFFF"
    )
    port map (
      I0 => reg_extra_19929,
      I1 => reg_inc_dec_b_19931,
      I2 => reg_uflow_19932,
      I3 => reg_cnt(0),
      I4 => index(0),
      O => Msub_AUX_124_cy_0_Q
    );
  Madd_AUX_123_addsub0000_cy_0_11 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => index(0),
      I1 => reg_inc_dec_b_19931,
      I2 => reg_extra_19929,
      I3 => reg_cnt(0),
      I4 => reg_uflow_19932,
      O => Madd_AUX_123_addsub0000_cy_0_Q
    );
  Msub_AUX_124_cy_2_11 : LUT5
    generic map(
      INIT => X"8A08EFAE"
    )
    port map (
      I0 => cnt(2),
      I1 => Msub_AUX_124_cy_0_Q,
      I2 => index(1),
      I3 => cnt(1),
      I4 => index(2),
      O => Msub_AUX_124_cy_2_Q
    );
  Madd_AUX_123_addsub0000_cy_2_11 : LUT5
    generic map(
      INIT => X"FEA8EA80"
    )
    port map (
      I0 => cnt(2),
      I1 => index(1),
      I2 => cnt(1),
      I3 => index(2),
      I4 => Madd_AUX_123_addsub0000_cy_0_Q,
      O => Madd_AUX_123_addsub0000_cy_2_Q
    );
  Msub_AUX_124_lut_2_1 : LUT5
    generic map(
      INIT => X"A50FE1C3"
    )
    port map (
      I0 => reg_inc_dec_b_19931,
      I1 => reg_cnt(2),
      I2 => index(2),
      I3 => reg_extra_19929,
      I4 => reg_uflow_19932,
      O => Msub_AUX_124_lut(2)
    );
  Madd_AUX_123_addsub0000_lut_2_1 : LUT5
    generic map(
      INIT => X"0FB4B4B4"
    )
    port map (
      I0 => reg_uflow_19932,
      I1 => reg_cnt(2),
      I2 => index(2),
      I3 => reg_inc_dec_b_19931,
      I4 => reg_extra_19929,
      O => Madd_AUX_123_addsub0000_lut(2)
    );
  reg_cnt_mux0000_2_1_SW0 : LUT4
    generic map(
      INIT => X"3F15"
    )
    port map (
      I0 => reg_cnt(1),
      I1 => reg_extra_19929,
      I2 => reg_inc_dec_b_19931,
      I3 => reg_uflow_19932,
      O => N5
    );
  reg_cnt_mux0000_2_1 : LUT6
    generic map(
      INIT => X"4888844444848848"
    )
    port map (
      I0 => index(1),
      I1 => enable,
      I2 => inc_dec_b,
      I3 => Madd_AUX_123_addsub0000_cy_0_Q,
      I4 => N5,
      I5 => Msub_AUX_124_cy_0_Q,
      O => reg_cnt_mux0000(2)
    );
  reg_cnt_mux0000_1_Q : MUXF7
    port map (
      I0 => N7,
      I1 => N8,
      S => inc_dec_b,
      O => reg_cnt_mux0000(1)
    );
  reg_cnt_mux0000_1_F : LUT5
    generic map(
      INIT => X"48884448"
    )
    port map (
      I0 => Msub_AUX_124_lut(2),
      I1 => enable,
      I2 => Msub_AUX_124_cy_0_Q,
      I3 => cnt(1),
      I4 => index(1),
      O => N7
    );
  reg_cnt_mux0000_1_G : LUT5
    generic map(
      INIT => X"1E007800"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_cy_0_Q,
      I1 => index(1),
      I2 => Madd_AUX_123_addsub0000_lut(2),
      I3 => enable,
      I4 => cnt(1),
      O => N8
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cnt_en_INST_3 is
  port (
    inc_dec_b : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    enable : in STD_LOGIC := 'X'; 
    count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cnt_en_INST_3;

architecture STRUCTURE of cmm_errman_cnt_en_INST_3 is
  signal Madd_AUX_123_addsub0000_cy_0_Q : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy_2_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_0_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_Q : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal reg_extra_19888 : STD_LOGIC; 
  signal reg_extra_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19890 : STD_LOGIC; 
  signal reg_uflow_19891 : STD_LOGIC; 
  signal reg_uflow_and0000_19892 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_lut : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal Msub_AUX_124_lut : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal reg_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_cnt_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_reg_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  count(3) <= NlwRenamedSig_OI_reg_count(3);
  count(2) <= NlwRenamedSig_OI_reg_count(2);
  count(1) <= NlwRenamedSig_OI_reg_count(1);
  count(0) <= NlwRenamedSig_OI_reg_count(0);
  reg_cnt_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(3),
      Q => reg_cnt(0)
    );
  reg_cnt_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(2),
      Q => reg_cnt(1)
    );
  reg_cnt_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(1),
      Q => reg_cnt(2)
    );
  reg_cnt_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(0),
      Q => reg_cnt(3)
    );
  reg_extra : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_extra_mux0000,
      Q => reg_extra_19888
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => inc_dec_b,
      Q => reg_inc_dec_b_19890
    );
  reg_uflow : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_uflow_and0000_19892,
      Q => reg_uflow_19891
    );
  reg_count_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => cnt(0),
      Q => NlwRenamedSig_OI_reg_count(0)
    );
  reg_count_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => cnt(1),
      Q => NlwRenamedSig_OI_reg_count(1)
    );
  reg_count_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => cnt(2),
      Q => NlwRenamedSig_OI_reg_count(2)
    );
  reg_count_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(3),
      Q => NlwRenamedSig_OI_reg_count(3)
    );
  cnt_3_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19888,
      I1 => reg_inc_dec_b_19890,
      I2 => reg_uflow_19891,
      I3 => reg_cnt(3),
      O => Madd_AUX_123_addsub0000_lut(3)
    );
  reg_uflow_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_count(1),
      I1 => NlwRenamedSig_OI_reg_count(0),
      I2 => inc_dec_b,
      O => N01
    );
  reg_uflow_and0000 : LUT6
    generic map(
      INIT => X"0101010101010100"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_count(3),
      I1 => NlwRenamedSig_OI_reg_count(2),
      I2 => N01,
      I3 => index(2),
      I4 => index(1),
      I5 => index(0),
      O => reg_uflow_and0000_19892
    );
  cnt_2_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19888,
      I1 => reg_inc_dec_b_19890,
      I2 => reg_uflow_19891,
      I3 => reg_cnt(2),
      O => cnt(2)
    );
  reg_extra_mux00001 : LUT4
    generic map(
      INIT => X"8901"
    )
    port map (
      I0 => inc_dec_b,
      I1 => Madd_AUX_123_addsub0000_lut(3),
      I2 => Msub_AUX_124_cy_2_Q,
      I3 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_extra_mux0000
    );
  reg_cnt_mux0000_0_1 : LUT4
    generic map(
      INIT => X"59A9"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_lut(3),
      I1 => Msub_AUX_124_cy_2_Q,
      I2 => inc_dec_b,
      I3 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_cnt_mux0000(0)
    );
  cnt_1_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19888,
      I1 => reg_inc_dec_b_19890,
      I2 => reg_uflow_19891,
      I3 => reg_cnt(1),
      O => cnt(1)
    );
  cnt_0_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19888,
      I1 => reg_inc_dec_b_19890,
      I2 => reg_uflow_19891,
      I3 => reg_cnt(0),
      O => cnt(0)
    );
  reg_cnt_mux0000_1_Q : LUT6
    generic map(
      INIT => X"0078001EFF78FF1E"
    )
    port map (
      I0 => cnt(1),
      I1 => Msub_AUX_124_cy_0_Q,
      I2 => Msub_AUX_124_lut(2),
      I3 => inc_dec_b,
      I4 => index(1),
      I5 => N2,
      O => reg_cnt_mux0000(1)
    );
  reg_cnt_mux0000_3_1 : LUT5
    generic map(
      INIT => X"0FB4B4B4"
    )
    port map (
      I0 => reg_uflow_19891,
      I1 => reg_cnt(0),
      I2 => index(0),
      I3 => reg_inc_dec_b_19890,
      I4 => reg_extra_19888,
      O => reg_cnt_mux0000(3)
    );
  Msub_AUX_124_cy_0_11 : LUT5
    generic map(
      INIT => X"8F88FFFF"
    )
    port map (
      I0 => reg_extra_19888,
      I1 => reg_inc_dec_b_19890,
      I2 => reg_uflow_19891,
      I3 => reg_cnt(0),
      I4 => index(0),
      O => Msub_AUX_124_cy_0_Q
    );
  Madd_AUX_123_addsub0000_cy_0_11 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => index(0),
      I1 => reg_inc_dec_b_19890,
      I2 => reg_extra_19888,
      I3 => reg_cnt(0),
      I4 => reg_uflow_19891,
      O => Madd_AUX_123_addsub0000_cy_0_Q
    );
  Msub_AUX_124_cy_2_11 : LUT5
    generic map(
      INIT => X"8A08EFAE"
    )
    port map (
      I0 => cnt(2),
      I1 => Msub_AUX_124_cy_0_Q,
      I2 => index(1),
      I3 => cnt(1),
      I4 => index(2),
      O => Msub_AUX_124_cy_2_Q
    );
  reg_cnt_mux0000_1_SW0 : LUT5
    generic map(
      INIT => X"1EE17887"
    )
    port map (
      I0 => cnt(1),
      I1 => index(1),
      I2 => cnt(2),
      I3 => index(2),
      I4 => Madd_AUX_123_addsub0000_cy_0_Q,
      O => N2
    );
  reg_cnt_mux0000_2_1 : LUT5
    generic map(
      INIT => X"99696669"
    )
    port map (
      I0 => cnt(1),
      I1 => index(1),
      I2 => Msub_AUX_124_cy_0_Q,
      I3 => inc_dec_b,
      I4 => Madd_AUX_123_addsub0000_cy_0_Q,
      O => reg_cnt_mux0000(2)
    );
  Madd_AUX_123_addsub0000_cy_2_11 : LUT5
    generic map(
      INIT => X"FEA8EA80"
    )
    port map (
      I0 => cnt(2),
      I1 => index(1),
      I2 => cnt(1),
      I3 => index(2),
      I4 => Madd_AUX_123_addsub0000_cy_0_Q,
      O => Madd_AUX_123_addsub0000_cy_2_Q
    );
  Msub_AUX_124_lut_2_1 : LUT5
    generic map(
      INIT => X"A50FE1C3"
    )
    port map (
      I0 => reg_inc_dec_b_19890,
      I1 => reg_cnt(2),
      I2 => index(2),
      I3 => reg_extra_19888,
      I4 => reg_uflow_19891,
      O => Msub_AUX_124_lut(2)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cnt_en_INST_2 is
  port (
    inc_dec_b : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    enable : in STD_LOGIC := 'X'; 
    count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cnt_en_INST_2;

architecture STRUCTURE of cmm_errman_cnt_en_INST_2 is
  signal Madd_AUX_123_addsub0000_cy_0_Q : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy_2_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_0_Q : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_Q : STD_LOGIC; 
  signal reg_extra_19854 : STD_LOGIC; 
  signal reg_extra_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19856 : STD_LOGIC; 
  signal reg_uflow_19857 : STD_LOGIC; 
  signal reg_uflow_and0000 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_lut : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal cnt : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal reg_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_cnt_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_reg_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_count_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  count(3) <= NlwRenamedSig_OI_reg_count(3);
  count(2) <= NlwRenamedSig_OI_reg_count(2);
  count(1) <= NlwRenamedSig_OI_reg_count(1);
  count(0) <= NlwRenamedSig_OI_reg_count(0);
  reg_cnt_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(3),
      Q => reg_cnt(0)
    );
  reg_cnt_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(2),
      Q => reg_cnt(1)
    );
  reg_cnt_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(1),
      Q => reg_cnt(2)
    );
  reg_cnt_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(0),
      Q => reg_cnt(3)
    );
  reg_extra : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_extra_mux0000,
      Q => reg_extra_19854
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => inc_dec_b,
      Q => reg_inc_dec_b_19856
    );
  reg_uflow : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_uflow_and0000,
      Q => reg_uflow_19857
    );
  reg_count_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(3),
      Q => NlwRenamedSig_OI_reg_count(0)
    );
  reg_count_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(2),
      Q => NlwRenamedSig_OI_reg_count(1)
    );
  reg_count_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(1),
      Q => NlwRenamedSig_OI_reg_count(2)
    );
  reg_count_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_count_mux0000(0),
      Q => NlwRenamedSig_OI_reg_count(3)
    );
  reg_uflow_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => index(0),
      I1 => inc_dec_b,
      I2 => NlwRenamedSig_OI_reg_count(0),
      I3 => NlwRenamedSig_OI_reg_count(1),
      I4 => NlwRenamedSig_OI_reg_count(2),
      I5 => NlwRenamedSig_OI_reg_count(3),
      O => reg_uflow_and0000
    );
  cnt_3_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19854,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_uflow_19857,
      I3 => reg_cnt(3),
      O => Madd_AUX_123_addsub0000_lut(3)
    );
  cnt_2_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19854,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_uflow_19857,
      I3 => reg_cnt(2),
      O => Madd_AUX_123_addsub0000_lut(2)
    );
  cnt_1_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19854,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_uflow_19857,
      I3 => reg_cnt(1),
      O => Madd_AUX_123_addsub0000_lut(1)
    );
  reg_cnt_mux0000_1_1 : LUT6
    generic map(
      INIT => X"28A0A0A02882A082"
    )
    port map (
      I0 => enable,
      I1 => inc_dec_b,
      I2 => Madd_AUX_123_addsub0000_lut(2),
      I3 => Madd_AUX_123_addsub0000_lut(1),
      I4 => Madd_AUX_123_addsub0000_cy_0_Q,
      I5 => Msub_AUX_124_cy_0_Q,
      O => reg_cnt_mux0000(1)
    );
  cnt_0_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19854,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_uflow_19857,
      I3 => reg_cnt(0),
      O => cnt(0)
    );
  reg_extra_mux00001 : LUT5
    generic map(
      INIT => X"80820002"
    )
    port map (
      I0 => enable,
      I1 => inc_dec_b,
      I2 => Madd_AUX_123_addsub0000_lut(3),
      I3 => Msub_AUX_124_cy_2_Q,
      I4 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_extra_mux0000
    );
  reg_cnt_mux0000_0_1 : LUT5
    generic map(
      INIT => X"22828882"
    )
    port map (
      I0 => enable,
      I1 => Madd_AUX_123_addsub0000_lut(3),
      I2 => Msub_AUX_124_cy_2_Q,
      I3 => inc_dec_b,
      I4 => Madd_AUX_123_addsub0000_cy_2_Q,
      O => reg_cnt_mux0000(0)
    );
  reg_count_mux0000_3_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_extra_19854,
      I3 => reg_cnt(0),
      I4 => reg_uflow_19857,
      O => reg_count_mux0000(3)
    );
  reg_count_mux0000_2_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_extra_19854,
      I3 => reg_cnt(1),
      I4 => reg_uflow_19857,
      O => reg_count_mux0000(2)
    );
  reg_count_mux0000_1_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_extra_19854,
      I3 => reg_cnt(2),
      I4 => reg_uflow_19857,
      O => reg_count_mux0000(1)
    );
  reg_count_mux0000_0_1 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => enable,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_extra_19854,
      I3 => reg_cnt(3),
      I4 => reg_uflow_19857,
      O => reg_count_mux0000(0)
    );
  reg_cnt_mux0000_3_1 : LUT6
    generic map(
      INIT => X"00AA8A208A208A20"
    )
    port map (
      I0 => enable,
      I1 => reg_uflow_19857,
      I2 => reg_cnt(0),
      I3 => index(0),
      I4 => reg_inc_dec_b_19856,
      I5 => reg_extra_19854,
      O => reg_cnt_mux0000(3)
    );
  reg_cnt_mux0000_2_1 : LUT6
    generic map(
      INIT => X"2888288822822888"
    )
    port map (
      I0 => enable,
      I1 => Madd_AUX_123_addsub0000_lut(1),
      I2 => inc_dec_b,
      I3 => Madd_AUX_123_addsub0000_cy_0_Q,
      I4 => index(0),
      I5 => cnt(0),
      O => reg_cnt_mux0000(2)
    );
  Madd_AUX_123_addsub0000_cy_0_11 : LUT5
    generic map(
      INIT => X"8080AA80"
    )
    port map (
      I0 => index(0),
      I1 => reg_inc_dec_b_19856,
      I2 => reg_extra_19854,
      I3 => reg_cnt(0),
      I4 => reg_uflow_19857,
      O => Madd_AUX_123_addsub0000_cy_0_Q
    );
  Madd_AUX_123_addsub0000_cy_2_11 : LUT6
    generic map(
      INIT => X"F0F0400040004000"
    )
    port map (
      I0 => reg_uflow_19857,
      I1 => reg_cnt(2),
      I2 => Madd_AUX_123_addsub0000_cy_0_Q,
      I3 => reg_cnt(1),
      I4 => reg_inc_dec_b_19856,
      I5 => reg_extra_19854,
      O => Madd_AUX_123_addsub0000_cy_2_Q
    );
  Msub_AUX_124_cy_2_11 : LUT6
    generic map(
      INIT => X"FFFFFFFF88FF88F8"
    )
    port map (
      I0 => reg_inc_dec_b_19856,
      I1 => reg_extra_19854,
      I2 => reg_cnt(1),
      I3 => reg_uflow_19857,
      I4 => reg_cnt(2),
      I5 => Msub_AUX_124_cy_0_Q,
      O => Msub_AUX_124_cy_2_Q
    );
  Msub_AUX_124_cy_0_11 : LUT5
    generic map(
      INIT => X"8F88FFFF"
    )
    port map (
      I0 => reg_extra_19854,
      I1 => reg_inc_dec_b_19856,
      I2 => reg_uflow_19857,
      I3 => reg_cnt(0),
      I4 => index(0),
      O => Msub_AUX_124_cy_0_Q
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cnt_en_INST_1 is
  port (
    inc_dec_b : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    enable : in STD_LOGIC := 'X'; 
    count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cnt_en_INST_1;

architecture STRUCTURE of cmm_errman_cnt_en_INST_1 is
  signal Madd_AUX_123_addsub0000_cy_2_11 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy_2_111_19797 : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_11 : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_111_19803 : STD_LOGIC; 
  signal reg_extra_19820 : STD_LOGIC; 
  signal reg_extra_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19822 : STD_LOGIC; 
  signal reg_uflow_19823 : STD_LOGIC; 
  signal reg_uflow_and0000 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Madd_AUX_123_addsub0000_lut : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal Msub_AUX_124_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cnt : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal reg_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_cnt_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_reg_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  count(3) <= NlwRenamedSig_OI_reg_count(3);
  count(2) <= NlwRenamedSig_OI_reg_count(2);
  count(1) <= NlwRenamedSig_OI_reg_count(1);
  count(0) <= NlwRenamedSig_OI_reg_count(0);
  reg_cnt_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(3),
      Q => reg_cnt(0)
    );
  reg_cnt_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(2),
      Q => reg_cnt(1)
    );
  reg_cnt_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(1),
      Q => reg_cnt(2)
    );
  reg_cnt_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(0),
      Q => reg_cnt(3)
    );
  reg_extra : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_extra_mux0000,
      Q => reg_extra_19820
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => inc_dec_b,
      Q => reg_inc_dec_b_19822
    );
  reg_uflow : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_uflow_and0000,
      Q => reg_uflow_19823
    );
  reg_count_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => cnt(0),
      Q => NlwRenamedSig_OI_reg_count(0)
    );
  reg_count_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(1),
      Q => NlwRenamedSig_OI_reg_count(1)
    );
  reg_count_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(2),
      Q => NlwRenamedSig_OI_reg_count(2)
    );
  reg_count_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(3),
      Q => NlwRenamedSig_OI_reg_count(3)
    );
  reg_uflow_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => index(0),
      I1 => inc_dec_b,
      I2 => NlwRenamedSig_OI_reg_count(0),
      I3 => NlwRenamedSig_OI_reg_count(1),
      I4 => NlwRenamedSig_OI_reg_count(2),
      I5 => NlwRenamedSig_OI_reg_count(3),
      O => reg_uflow_and0000
    );
  cnt_3_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19820,
      I1 => reg_inc_dec_b_19822,
      I2 => reg_uflow_19823,
      I3 => reg_cnt(3),
      O => Madd_AUX_123_addsub0000_lut(3)
    );
  cnt_2_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19820,
      I1 => reg_inc_dec_b_19822,
      I2 => reg_uflow_19823,
      I3 => reg_cnt(2),
      O => Madd_AUX_123_addsub0000_lut(2)
    );
  cnt_1_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19820,
      I1 => reg_inc_dec_b_19822,
      I2 => reg_uflow_19823,
      I3 => reg_cnt(1),
      O => Madd_AUX_123_addsub0000_lut(1)
    );
  cnt_0_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19820,
      I1 => reg_inc_dec_b_19822,
      I2 => reg_uflow_19823,
      I3 => reg_cnt(0),
      O => cnt(0)
    );
  reg_extra_mux00001 : LUT4
    generic map(
      INIT => X"8901"
    )
    port map (
      I0 => inc_dec_b,
      I1 => Madd_AUX_123_addsub0000_lut(3),
      I2 => Msub_AUX_124_cy(2),
      I3 => Madd_AUX_123_addsub0000_cy(2),
      O => reg_extra_mux0000
    );
  reg_cnt_mux0000_0_1 : LUT4
    generic map(
      INIT => X"59A9"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_lut(3),
      I1 => Msub_AUX_124_cy(2),
      I2 => inc_dec_b,
      I3 => Madd_AUX_123_addsub0000_cy(2),
      O => reg_cnt_mux0000(0)
    );
  reg_cnt_mux0000_3_1 : LUT5
    generic map(
      INIT => X"0FB4B4B4"
    )
    port map (
      I0 => reg_uflow_19823,
      I1 => reg_cnt(0),
      I2 => index(0),
      I3 => reg_inc_dec_b_19822,
      I4 => reg_extra_19820,
      O => reg_cnt_mux0000(3)
    );
  reg_cnt_mux0000_2_1 : LUT4
    generic map(
      INIT => X"6AA6"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_lut(1),
      I1 => index(0),
      I2 => cnt(0),
      I3 => inc_dec_b,
      O => reg_cnt_mux0000(2)
    );
  reg_cnt_mux0000_1_1 : LUT5
    generic map(
      INIT => X"6CC9CCCC"
    )
    port map (
      I0 => inc_dec_b,
      I1 => Madd_AUX_123_addsub0000_lut(2),
      I2 => Madd_AUX_123_addsub0000_lut(1),
      I3 => cnt(0),
      I4 => index(0),
      O => reg_cnt_mux0000(1)
    );
  Madd_AUX_123_addsub0000_cy_2_111 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => index(0),
      I1 => reg_inc_dec_b_19822,
      I2 => reg_extra_19820,
      O => Madd_AUX_123_addsub0000_cy_2_11
    );
  Madd_AUX_123_addsub0000_cy_2_112 : LUT6
    generic map(
      INIT => X"CCCC800080008000"
    )
    port map (
      I0 => reg_cnt(2),
      I1 => index(0),
      I2 => reg_cnt(0),
      I3 => reg_cnt(1),
      I4 => reg_inc_dec_b_19822,
      I5 => reg_extra_19820,
      O => Madd_AUX_123_addsub0000_cy_2_111_19797
    );
  Madd_AUX_123_addsub0000_cy_2_11_f7 : MUXF7
    port map (
      I0 => Madd_AUX_123_addsub0000_cy_2_111_19797,
      I1 => Madd_AUX_123_addsub0000_cy_2_11,
      S => reg_uflow_19823,
      O => Madd_AUX_123_addsub0000_cy(2)
    );
  Msub_AUX_124_cy_2_111 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => index(0),
      I1 => reg_extra_19820,
      I2 => reg_inc_dec_b_19822,
      O => Msub_AUX_124_cy_2_11
    );
  Msub_AUX_124_cy_2_112 : LUT6
    generic map(
      INIT => X"FFFFFEFFFEFFFEFF"
    )
    port map (
      I0 => reg_cnt(2),
      I1 => reg_cnt(0),
      I2 => reg_cnt(1),
      I3 => index(0),
      I4 => reg_extra_19820,
      I5 => reg_inc_dec_b_19822,
      O => Msub_AUX_124_cy_2_111_19803
    );
  Msub_AUX_124_cy_2_11_f7 : MUXF7
    port map (
      I0 => Msub_AUX_124_cy_2_111_19803,
      I1 => Msub_AUX_124_cy_2_11,
      S => reg_uflow_19823,
      O => Msub_AUX_124_cy(2)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cnt_en is
  port (
    inc_dec_b : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    enable : in STD_LOGIC := 'X'; 
    count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cnt_en;

architecture STRUCTURE of cmm_errman_cnt_en is
  signal Madd_AUX_123_addsub0000_cy_2_11 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy_2_111_19766 : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_11 : STD_LOGIC; 
  signal Msub_AUX_124_cy_2_111_19772 : STD_LOGIC; 
  signal reg_extra_19789 : STD_LOGIC; 
  signal reg_extra_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19791 : STD_LOGIC; 
  signal reg_uflow_19792 : STD_LOGIC; 
  signal reg_uflow_and0000 : STD_LOGIC; 
  signal Madd_AUX_123_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Madd_AUX_123_addsub0000_lut : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal Msub_AUX_124_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal cnt : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal reg_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_cnt_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_reg_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  count(3) <= NlwRenamedSig_OI_reg_count(3);
  count(2) <= NlwRenamedSig_OI_reg_count(2);
  count(1) <= NlwRenamedSig_OI_reg_count(1);
  count(0) <= NlwRenamedSig_OI_reg_count(0);
  reg_cnt_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(3),
      Q => reg_cnt(0)
    );
  reg_cnt_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(2),
      Q => reg_cnt(1)
    );
  reg_cnt_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(1),
      Q => reg_cnt(2)
    );
  reg_cnt_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_cnt_mux0000(0),
      Q => reg_cnt(3)
    );
  reg_extra : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_extra_mux0000,
      Q => reg_extra_19789
    );
  reg_inc_dec_b : FDC
    port map (
      C => clk,
      CLR => rst,
      D => inc_dec_b,
      Q => reg_inc_dec_b_19791
    );
  reg_uflow : FDC
    port map (
      C => clk,
      CLR => rst,
      D => reg_uflow_and0000,
      Q => reg_uflow_19792
    );
  reg_count_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => cnt(0),
      Q => NlwRenamedSig_OI_reg_count(0)
    );
  reg_count_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(1),
      Q => NlwRenamedSig_OI_reg_count(1)
    );
  reg_count_2 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(2),
      Q => NlwRenamedSig_OI_reg_count(2)
    );
  reg_count_3 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => Madd_AUX_123_addsub0000_lut(3),
      Q => NlwRenamedSig_OI_reg_count(3)
    );
  reg_uflow_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => index(0),
      I1 => inc_dec_b,
      I2 => NlwRenamedSig_OI_reg_count(0),
      I3 => NlwRenamedSig_OI_reg_count(1),
      I4 => NlwRenamedSig_OI_reg_count(2),
      I5 => NlwRenamedSig_OI_reg_count(3),
      O => reg_uflow_and0000
    );
  cnt_3_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19789,
      I1 => reg_inc_dec_b_19791,
      I2 => reg_uflow_19792,
      I3 => reg_cnt(3),
      O => Madd_AUX_123_addsub0000_lut(3)
    );
  cnt_2_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19789,
      I1 => reg_inc_dec_b_19791,
      I2 => reg_uflow_19792,
      I3 => reg_cnt(2),
      O => Madd_AUX_123_addsub0000_lut(2)
    );
  cnt_1_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19789,
      I1 => reg_inc_dec_b_19791,
      I2 => reg_uflow_19792,
      I3 => reg_cnt(1),
      O => Madd_AUX_123_addsub0000_lut(1)
    );
  cnt_0_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => reg_extra_19789,
      I1 => reg_inc_dec_b_19791,
      I2 => reg_uflow_19792,
      I3 => reg_cnt(0),
      O => cnt(0)
    );
  reg_extra_mux00001 : LUT4
    generic map(
      INIT => X"8901"
    )
    port map (
      I0 => inc_dec_b,
      I1 => Madd_AUX_123_addsub0000_lut(3),
      I2 => Msub_AUX_124_cy(2),
      I3 => Madd_AUX_123_addsub0000_cy(2),
      O => reg_extra_mux0000
    );
  reg_cnt_mux0000_0_1 : LUT4
    generic map(
      INIT => X"59A9"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_lut(3),
      I1 => Msub_AUX_124_cy(2),
      I2 => inc_dec_b,
      I3 => Madd_AUX_123_addsub0000_cy(2),
      O => reg_cnt_mux0000(0)
    );
  reg_cnt_mux0000_3_1 : LUT5
    generic map(
      INIT => X"0FB4B4B4"
    )
    port map (
      I0 => reg_uflow_19792,
      I1 => reg_cnt(0),
      I2 => index(0),
      I3 => reg_inc_dec_b_19791,
      I4 => reg_extra_19789,
      O => reg_cnt_mux0000(3)
    );
  reg_cnt_mux0000_2_1 : LUT4
    generic map(
      INIT => X"6AA6"
    )
    port map (
      I0 => Madd_AUX_123_addsub0000_lut(1),
      I1 => index(0),
      I2 => cnt(0),
      I3 => inc_dec_b,
      O => reg_cnt_mux0000(2)
    );
  reg_cnt_mux0000_1_1 : LUT5
    generic map(
      INIT => X"6CC9CCCC"
    )
    port map (
      I0 => inc_dec_b,
      I1 => Madd_AUX_123_addsub0000_lut(2),
      I2 => Madd_AUX_123_addsub0000_lut(1),
      I3 => cnt(0),
      I4 => index(0),
      O => reg_cnt_mux0000(1)
    );
  Madd_AUX_123_addsub0000_cy_2_111 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => index(0),
      I1 => reg_inc_dec_b_19791,
      I2 => reg_extra_19789,
      O => Madd_AUX_123_addsub0000_cy_2_11
    );
  Madd_AUX_123_addsub0000_cy_2_112 : LUT6
    generic map(
      INIT => X"CCCC800080008000"
    )
    port map (
      I0 => reg_cnt(2),
      I1 => index(0),
      I2 => reg_cnt(0),
      I3 => reg_cnt(1),
      I4 => reg_inc_dec_b_19791,
      I5 => reg_extra_19789,
      O => Madd_AUX_123_addsub0000_cy_2_111_19766
    );
  Madd_AUX_123_addsub0000_cy_2_11_f7 : MUXF7
    port map (
      I0 => Madd_AUX_123_addsub0000_cy_2_111_19766,
      I1 => Madd_AUX_123_addsub0000_cy_2_11,
      S => reg_uflow_19792,
      O => Madd_AUX_123_addsub0000_cy(2)
    );
  Msub_AUX_124_cy_2_111 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => index(0),
      I1 => reg_extra_19789,
      I2 => reg_inc_dec_b_19791,
      O => Msub_AUX_124_cy_2_11
    );
  Msub_AUX_124_cy_2_112 : LUT6
    generic map(
      INIT => X"FFFFFEFFFEFFFEFF"
    )
    port map (
      I0 => reg_cnt(2),
      I1 => reg_cnt(0),
      I2 => reg_cnt(1),
      I3 => index(0),
      I4 => reg_extra_19789,
      I5 => reg_inc_dec_b_19791,
      O => Msub_AUX_124_cy_2_111_19772
    );
  Msub_AUX_124_cy_2_11_f7 : MUXF7
    port map (
      I0 => Msub_AUX_124_cy_2_111_19772,
      I1 => Msub_AUX_124_cy_2_11,
      S => reg_uflow_19792,
      O => Msub_AUX_124_cy(2)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cor_INST_1 is
  port (
    inc_dec_b : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    add_input_three_n : in STD_LOGIC := 'X'; 
    decr_cor : in STD_LOGIC := 'X'; 
    add_input_five_n : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    add_input_one : in STD_LOGIC := 'X'; 
    add_input_four_n : in STD_LOGIC := 'X'; 
    add_input_six_n : in STD_LOGIC := 'X'; 
    add_input_two_n : in STD_LOGIC := 'X'; 
    reg_decr_cor : out STD_LOGIC; 
    cor_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cor_INST_1;

architecture STRUCTURE of cmm_errman_cor_INST_1 is
  signal reg_decr_cor_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19760 : STD_LOGIC; 
  signal reg_inc_dec_b_not0001 : STD_LOGIC; 
  signal reg_cor_num : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal to_incr : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  inc_dec_b <= reg_inc_dec_b_19760;
  cor_num(0) <= reg_cor_num(0);
  XST_VCC : VCC
    port map (
      P => to_incr(0)
    );
  reg_cor_num_0 : FDR
    port map (
      C => clk,
      D => to_incr(0),
      R => rst,
      Q => reg_cor_num(0)
    );
  reg_inc_dec_b : FDR
    port map (
      C => clk,
      D => reg_inc_dec_b_not0001,
      R => rst,
      Q => reg_inc_dec_b_19760
    );
  reg_decr_cor_11092 : FDR
    port map (
      C => clk,
      D => reg_decr_cor_mux0000,
      R => rst,
      Q => reg_decr_cor
    );
  reg_inc_dec_b_not00011_INV_0 : INV
    port map (
      I => decr_cor,
      O => reg_inc_dec_b_not0001
    );
  reg_decr_cor_mux000011_INV_0 : INV
    port map (
      I => decr_cor,
      O => reg_decr_cor_mux0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_errman_cor is
  port (
    inc_dec_b : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    add_input_three_n : in STD_LOGIC := 'X'; 
    decr_cor : in STD_LOGIC := 'X'; 
    add_input_five_n : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    add_input_one : in STD_LOGIC := 'X'; 
    add_input_four_n : in STD_LOGIC := 'X'; 
    add_input_six_n : in STD_LOGIC := 'X'; 
    add_input_two_n : in STD_LOGIC := 'X'; 
    reg_decr_cor : out STD_LOGIC; 
    cor_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_errman_cor;

architecture STRUCTURE of cmm_errman_cor is
  signal reg_decr_cor_mux0000 : STD_LOGIC; 
  signal reg_inc_dec_b_19751 : STD_LOGIC; 
  signal reg_inc_dec_b_not0001 : STD_LOGIC; 
  signal reg_cor_num : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal to_incr : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  inc_dec_b <= reg_inc_dec_b_19751;
  cor_num(0) <= reg_cor_num(0);
  XST_VCC : VCC
    port map (
      P => to_incr(0)
    );
  reg_cor_num_0 : FDR
    port map (
      C => clk,
      D => to_incr(0),
      R => rst,
      Q => reg_cor_num(0)
    );
  reg_inc_dec_b : FDR
    port map (
      C => clk,
      D => reg_inc_dec_b_not0001,
      R => rst,
      Q => reg_inc_dec_b_19751
    );
  reg_decr_cor_11085 : FDR
    port map (
      C => clk,
      D => reg_decr_cor_mux0000,
      R => rst,
      Q => reg_decr_cor
    );
  reg_inc_dec_b_not00011_INV_0 : INV
    port map (
      I => decr_cor,
      O => reg_inc_dec_b_not0001
    );
  reg_decr_cor_mux000011_INV_0 : INV
    port map (
      I => decr_cor,
      O => reg_decr_cor_mux0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_cf_err is
  port (
    rx_err_cpl_ur_n : in STD_LOGIC := 'X'; 
    l0_set_user_system_error : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    cs_is_nfl : in STD_LOGIC := 'X'; 
    rx_err_tlp_ur_lock_n : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    l0_set_user_received_master_abort : out STD_LOGIC; 
    l0_set_detected_nonfatal_error : out STD_LOGIC; 
    cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
    l0_set_detected_corr_error : out STD_LOGIC; 
    send_ftl : out STD_LOGIC; 
    cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
    send_cplt : out STD_LOGIC; 
    send_cplu : out STD_LOGIC; 
    cs_is_ftl : in STD_LOGIC := 'X'; 
    rx_err_cpl_ep_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_ur_n : in STD_LOGIC := 'X'; 
    l0_set_user_master_data_parity : out STD_LOGIC; 
    cfg_err_locked_n : in STD_LOGIC := 'X'; 
    l0_mac_link_up : in STD_LOGIC := 'X'; 
    l0_set_user_detected_parity_error : out STD_LOGIC; 
    l0_set_user_signaled_target_abort : out STD_LOGIC; 
    l0_set_detected_fatal_error : out STD_LOGIC; 
    tx_err_wr_ep_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_malformed_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_p_cpl_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
    cfg_err_ur_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    send_cor : out STD_LOGIC; 
    cfg_err_posted_n : in STD_LOGIC := 'X'; 
    rx_err_ep_n : in STD_LOGIC := 'X'; 
    l0_set_unsupported_request_other_error : out STD_LOGIC; 
    cs_is_cplt : in STD_LOGIC := 'X'; 
    cs_is_cplu : in STD_LOGIC := 'X'; 
    cs_is_cor : in STD_LOGIC := 'X'; 
    cfg_err_cpl_rdy_n : out STD_LOGIC; 
    l0_set_user_received_target_abort : out STD_LOGIC; 
    grant : in STD_LOGIC := 'X'; 
    rx_err_tlp_poisoned_n : in STD_LOGIC := 'X'; 
    send_nfl : out STD_LOGIC; 
    serr_en : in STD_LOGIC := 'X'; 
    cfg_err_cor_n : in STD_LOGIC := 'X'; 
    cfg_rd_hdr : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
    cmt_rd_hdr : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
    rx_err_tlp_hdr : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    request_data : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
    l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    cfg_command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end pcie_blk_cf_err;

architecture STRUCTURE of pcie_blk_cf_err is
  component cmm_errman_cor
    port (
      inc_dec_b : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      add_input_three_n : in STD_LOGIC := 'X'; 
      decr_cor : in STD_LOGIC := 'X'; 
      add_input_five_n : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      add_input_one : in STD_LOGIC := 'X'; 
      add_input_four_n : in STD_LOGIC := 'X'; 
      add_input_six_n : in STD_LOGIC := 'X'; 
      add_input_two_n : in STD_LOGIC := 'X'; 
      reg_decr_cor : out STD_LOGIC; 
      cor_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cor_INST_1
    port (
      inc_dec_b : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      add_input_three_n : in STD_LOGIC := 'X'; 
      decr_cor : in STD_LOGIC := 'X'; 
      add_input_five_n : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      add_input_one : in STD_LOGIC := 'X'; 
      add_input_four_n : in STD_LOGIC := 'X'; 
      add_input_six_n : in STD_LOGIC := 'X'; 
      add_input_two_n : in STD_LOGIC := 'X'; 
      reg_decr_cor : out STD_LOGIC; 
      cor_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cnt_en
    port (
      inc_dec_b : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      enable : in STD_LOGIC := 'X'; 
      count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cnt_en_INST_1
    port (
      inc_dec_b : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      enable : in STD_LOGIC := 'X'; 
      count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cnt_en_INST_2
    port (
      inc_dec_b : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      enable : in STD_LOGIC := 'X'; 
      count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cnt_en_INST_3
    port (
      inc_dec_b : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      enable : in STD_LOGIC := 'X'; 
      count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cnt_en_INST_4
    port (
      inc_dec_b : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      enable : in STD_LOGIC := 'X'; 
      count : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      index : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_ftl
    port (
      inc_dec_b : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      cmmt_err_tlp_malformed : in STD_LOGIC := 'X'; 
      cmmt_err_fc : in STD_LOGIC := 'X'; 
      cmmt_err_rbuf_overflow : in STD_LOGIC := 'X'; 
      cmmp_training_err : in STD_LOGIC := 'X'; 
      decr_ftl : in STD_LOGIC := 'X'; 
      cmml_protocol_err_n : in STD_LOGIC := 'X'; 
      ftl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cpl
    port (
      inc_dec_b : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      decr_cpl : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      cmm_err_tlp_posted : in STD_LOGIC := 'X'; 
      cpl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_cpl_INST_1
    port (
      inc_dec_b : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      decr_cpl : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      cmm_err_tlp_posted : in STD_LOGIC := 'X'; 
      cpl_num : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component cmm_errman_ram4x26
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      we : in STD_LOGIC := 'X'; 
      rddata : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
      wrdata : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
      rd_ptr : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      wr_ptr : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  component cmm_errman_ram8x26
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      we : in STD_LOGIC := 'X'; 
      rddata : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
      wrdata : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
      rd_ptr : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      wr_ptr : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  signal cor_add_sub_b : STD_LOGIC; 
  signal cplt_add_sub_b : STD_LOGIC; 
  signal cplu_add_sub_b : STD_LOGIC; 
  signal decr_cor : STD_LOGIC; 
  signal decr_cplt : STD_LOGIC; 
  signal decr_cplu : STD_LOGIC; 
  signal decr_ftl : STD_LOGIC; 
  signal decr_nfl : STD_LOGIC; 
  signal err_ftl_en : STD_LOGIC; 
  signal ftl_add_sub_b : STD_LOGIC; 
  signal NlwRenamedSig_OI_l0_set_user_signaled_target_abort : STD_LOGIC; 
  signal nfl_add_sub_b : STD_LOGIC; 
  signal reg_cmt_wr_hdr_0_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_1_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_10_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_11_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_12_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_13_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_14_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_15_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_16_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_17_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_18_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_19_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_2_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_20_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_21_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_22_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_23_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_24_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_25_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_26_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_27_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_28_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_29_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_3_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_30_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_31_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_32_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_33_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_34_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_35_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_36_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_37_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_38_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_39_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_4_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_40_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_41_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_42_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_43_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_44_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_45_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_46_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_47_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_49_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_5_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_6_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_7_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_8_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_9_Q : STD_LOGIC; 
  signal reg_cmt_wr_hdr_not0001_inv : STD_LOGIC; 
  signal reg_decr_cor : STD_LOGIC; 
  signal reg_decr_nfl : STD_LOGIC; 
  signal reg_detectedfatal_20406 : STD_LOGIC; 
  signal reg_detectedfatal_not0001 : STD_LOGIC; 
  signal reg_detectedparityerror_20408 : STD_LOGIC; 
  signal reg_detectedparityerror_not0001 : STD_LOGIC; 
  signal reg_incr_cplt_20410 : STD_LOGIC; 
  signal reg_masterdataparityerror_20411 : STD_LOGIC; 
  signal reg_masterdataparityerror_not0001_inv : STD_LOGIC; 
  signal reg_masterdataparityerror_or0000 : STD_LOGIC; 
  signal reg_receivedmasterabort_20414 : STD_LOGIC; 
  signal reg_receivedmasterabort_not0001 : STD_LOGIC; 
  signal reg_receivedtargetabort_20416 : STD_LOGIC; 
  signal reg_receivedtargetabort_not0001 : STD_LOGIC; 
  signal reg_signaledsystemerror_20418 : STD_LOGIC; 
  signal reg_signaledsystemerror_not0001_inv : STD_LOGIC; 
  signal reg_signaledsystemerror_or0000 : STD_LOGIC; 
  signal reg_unsupportedreq_20421 : STD_LOGIC; 
  signal reg_unsupportedreq_and0000 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal send_cor_or0000 : STD_LOGIC; 
  signal send_cplt_or0000 : STD_LOGIC; 
  signal send_cplu_or0000 : STD_LOGIC; 
  signal send_ftl_or0000 : STD_LOGIC; 
  signal send_nfl_or0000 : STD_LOGIC; 
  signal tlp_is_np_and_ur : STD_LOGIC; 
  signal NLW_wtd_ftl_cmml_protocol_err_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_nfl_cntr_enable_UNCONNECTED : STD_LOGIC; 
  signal NLW_cplt_cntr_enable_UNCONNECTED : STD_LOGIC; 
  signal NLW_cplu_cntr_enable_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_add_input_three_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_add_input_five_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_add_input_four_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_add_input_six_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_add_input_two_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_cor_num_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_cor_cor_num_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_add_input_three_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_add_input_five_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_add_input_four_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_add_input_six_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_add_input_two_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_cor_num_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_wtd_nfl_cor_num_1_UNCONNECTED : STD_LOGIC; 
  signal cnt_cor : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cnt_cplt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cnt_cplu : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cnt_ftl : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cnt_nfl : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cor_num : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cor_num_int : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal cplt_num : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cplu_num : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal ftl_num : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal nfl_num : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal nfl_num_int : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal reg_cfg_rp : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal reg_cfg_rp_add0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal reg_cmt_rp : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal reg_cmt_rp_add0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal reg_cmt_wp : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal reg_cmt_wp_add0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  l0_set_user_system_error <= reg_signaledsystemerror_20418;
  l0_set_user_received_master_abort <= reg_receivedmasterabort_20414;
  l0_set_detected_nonfatal_error <= NlwRenamedSig_OI_l0_set_user_signaled_target_abort;
  l0_set_detected_corr_error <= NlwRenamedSig_OI_l0_set_user_signaled_target_abort;
  l0_set_user_master_data_parity <= reg_masterdataparityerror_20411;
  l0_set_user_detected_parity_error <= reg_detectedparityerror_20408;
  l0_set_user_signaled_target_abort <= NlwRenamedSig_OI_l0_set_user_signaled_target_abort;
  l0_set_detected_fatal_error <= reg_detectedfatal_20406;
  l0_set_unsupported_request_other_error <= reg_unsupportedreq_20421;
  l0_set_user_received_target_abort <= reg_receivedtargetabort_20416;
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_l0_set_user_signaled_target_abort
    );
  reg_signaledsystemerror : FDRS
    port map (
      C => clk,
      D => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      R => reg_signaledsystemerror_not0001_inv,
      S => reg_signaledsystemerror_or0000,
      Q => reg_signaledsystemerror_20418
    );
  reg_masterdataparityerror : FDR
    port map (
      C => clk,
      D => reg_masterdataparityerror_or0000,
      R => reg_masterdataparityerror_not0001_inv,
      Q => reg_masterdataparityerror_20411
    );
  reg_receivedtargetabort : FDR
    port map (
      C => clk,
      D => reg_receivedtargetabort_not0001,
      R => rst_n_inv,
      Q => reg_receivedtargetabort_20416
    );
  reg_receivedmasterabort : FDR
    port map (
      C => clk,
      D => reg_receivedmasterabort_not0001,
      R => rst_n_inv,
      Q => reg_receivedmasterabort_20414
    );
  reg_detectedparityerror : FDR
    port map (
      C => clk,
      D => reg_detectedparityerror_not0001,
      R => rst_n_inv,
      Q => reg_detectedparityerror_20408
    );
  send_cor_11017 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => send_cor_or0000,
      R => rst_n_inv,
      Q => send_cor
    );
  reg_detectedfatal : FDR
    port map (
      C => clk,
      D => reg_detectedfatal_not0001,
      R => rst_n_inv,
      Q => reg_detectedfatal_20406
    );
  reg_unsupportedreq : FDR
    port map (
      C => clk,
      D => reg_unsupportedreq_and0000,
      R => rst_n_inv,
      Q => reg_unsupportedreq_20421
    );
  send_nfl_11020 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => send_nfl_or0000,
      R => rst_n_inv,
      Q => send_nfl
    );
  send_ftl_11021 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => send_ftl_or0000,
      R => rst_n_inv,
      Q => send_ftl
    );
  send_cplt_11022 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => send_cplt_or0000,
      R => rst_n_inv,
      Q => send_cplt
    );
  send_cplu_11023 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => send_cplu_or0000,
      R => rst_n_inv,
      Q => send_cplu
    );
  reg_cmt_wr_hdr_0 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(0),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_0_Q
    );
  reg_cmt_wr_hdr_1 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(1),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_1_Q
    );
  reg_cmt_wr_hdr_2 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(2),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_2_Q
    );
  reg_cmt_wr_hdr_3 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(3),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_3_Q
    );
  reg_cmt_wr_hdr_4 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(4),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_4_Q
    );
  reg_cmt_wr_hdr_5 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(5),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_5_Q
    );
  reg_cmt_wr_hdr_6 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(6),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_6_Q
    );
  reg_cmt_wr_hdr_7 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(7),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_7_Q
    );
  reg_cmt_wr_hdr_8 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(8),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_8_Q
    );
  reg_cmt_wr_hdr_9 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(9),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_9_Q
    );
  reg_cmt_wr_hdr_10 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(10),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_10_Q
    );
  reg_cmt_wr_hdr_11 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(11),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_11_Q
    );
  reg_cmt_wr_hdr_12 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(12),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_12_Q
    );
  reg_cmt_wr_hdr_13 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(13),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_13_Q
    );
  reg_cmt_wr_hdr_14 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(14),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_14_Q
    );
  reg_cmt_wr_hdr_15 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(15),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_15_Q
    );
  reg_cmt_wr_hdr_16 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(16),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_16_Q
    );
  reg_cmt_wr_hdr_17 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(17),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_17_Q
    );
  reg_cmt_wr_hdr_18 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(18),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_18_Q
    );
  reg_cmt_wr_hdr_19 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(19),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_19_Q
    );
  reg_cmt_wr_hdr_20 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(20),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_20_Q
    );
  reg_cmt_wr_hdr_21 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(21),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_21_Q
    );
  reg_cmt_wr_hdr_22 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(22),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_22_Q
    );
  reg_cmt_wr_hdr_23 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(23),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_23_Q
    );
  reg_cmt_wr_hdr_24 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(24),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_24_Q
    );
  reg_cmt_wr_hdr_25 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(25),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_25_Q
    );
  reg_cmt_wr_hdr_26 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(26),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_26_Q
    );
  reg_cmt_wr_hdr_27 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(27),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_27_Q
    );
  reg_cmt_wr_hdr_28 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(28),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_28_Q
    );
  reg_cmt_wr_hdr_29 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(29),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_29_Q
    );
  reg_cmt_wr_hdr_30 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(30),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_30_Q
    );
  reg_cmt_wr_hdr_31 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(31),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_31_Q
    );
  reg_cmt_wr_hdr_32 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(32),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_32_Q
    );
  reg_cmt_wr_hdr_33 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(33),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_33_Q
    );
  reg_cmt_wr_hdr_34 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(34),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_34_Q
    );
  reg_cmt_wr_hdr_35 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(35),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_35_Q
    );
  reg_cmt_wr_hdr_36 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(36),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_36_Q
    );
  reg_cmt_wr_hdr_37 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(37),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_37_Q
    );
  reg_cmt_wr_hdr_38 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(38),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_38_Q
    );
  reg_cmt_wr_hdr_39 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(39),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_39_Q
    );
  reg_cmt_wr_hdr_40 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(40),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_40_Q
    );
  reg_cmt_wr_hdr_41 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(41),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_41_Q
    );
  reg_cmt_wr_hdr_42 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(42),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_42_Q
    );
  reg_cmt_wr_hdr_43 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(43),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_43_Q
    );
  reg_cmt_wr_hdr_44 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(44),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_44_Q
    );
  reg_cmt_wr_hdr_45 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(45),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_45_Q
    );
  reg_cmt_wr_hdr_46 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(46),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_46_Q
    );
  reg_cmt_wr_hdr_47 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_hdr(47),
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_47_Q
    );
  reg_cmt_wr_hdr_49 : FDR
    port map (
      C => clk,
      D => rx_err_tlp_ur_lock_n,
      R => reg_cmt_wr_hdr_not0001_inv,
      Q => reg_cmt_wr_hdr_49_Q
    );
  reg_incr_cplt : FDR
    port map (
      C => clk,
      D => tlp_is_np_and_ur,
      R => rst_n_inv,
      Q => reg_incr_cplt_20410
    );
  reg_cmt_wp_0 : FDRE
    port map (
      C => clk,
      CE => reg_incr_cplt_20410,
      D => reg_cmt_wp_add0000(0),
      R => rst_n_inv,
      Q => reg_cmt_wp(0)
    );
  reg_cmt_wp_1 : FDRE
    port map (
      C => clk,
      CE => reg_incr_cplt_20410,
      D => reg_cmt_wp_add0000(1),
      R => rst_n_inv,
      Q => reg_cmt_wp(1)
    );
  reg_cmt_rp_0 : FDRE
    port map (
      C => clk,
      CE => decr_cplt,
      D => reg_cmt_rp_add0000(0),
      R => rst_n_inv,
      Q => reg_cmt_rp(0)
    );
  reg_cmt_rp_1 : FDRE
    port map (
      C => clk,
      CE => decr_cplt,
      D => reg_cmt_rp_add0000(1),
      R => rst_n_inv,
      Q => reg_cmt_rp(1)
    );
  reg_cfg_rp_0 : FDRE
    port map (
      C => clk,
      CE => decr_cplu,
      D => reg_cfg_rp_add0000(0),
      R => rst_n_inv,
      Q => reg_cfg_rp(0)
    );
  reg_cfg_rp_1 : FDRE
    port map (
      C => clk,
      CE => decr_cplu,
      D => reg_cfg_rp_add0000(1),
      R => rst_n_inv,
      Q => reg_cfg_rp(1)
    );
  reg_cfg_rp_2 : FDRE
    port map (
      C => clk,
      CE => decr_cplu,
      D => reg_cfg_rp_add0000(2),
      R => rst_n_inv,
      Q => reg_cfg_rp(2)
    );
  wtd_nfl : cmm_errman_cor
    port map (
      inc_dec_b => nfl_add_sub_b,
      clk => clk,
      add_input_three_n => NLW_wtd_nfl_add_input_three_n_UNCONNECTED,
      decr_cor => decr_nfl,
      add_input_five_n => NLW_wtd_nfl_add_input_five_n_UNCONNECTED,
      rst => rst_n_inv,
      add_input_one => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      add_input_four_n => NLW_wtd_nfl_add_input_four_n_UNCONNECTED,
      add_input_six_n => NLW_wtd_nfl_add_input_six_n_UNCONNECTED,
      add_input_two_n => NLW_wtd_nfl_add_input_two_n_UNCONNECTED,
      reg_decr_cor => reg_decr_nfl,
      cor_num(2) => NLW_wtd_nfl_cor_num_2_UNCONNECTED,
      cor_num(1) => NLW_wtd_nfl_cor_num_1_UNCONNECTED,
      cor_num(0) => nfl_num_int(0)
    );
  wtd_cor : cmm_errman_cor_INST_1
    port map (
      inc_dec_b => cor_add_sub_b,
      clk => clk,
      add_input_three_n => NLW_wtd_cor_add_input_three_n_UNCONNECTED,
      decr_cor => decr_cor,
      add_input_five_n => NLW_wtd_cor_add_input_five_n_UNCONNECTED,
      rst => rst_n_inv,
      add_input_one => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      add_input_four_n => NLW_wtd_cor_add_input_four_n_UNCONNECTED,
      add_input_six_n => NLW_wtd_cor_add_input_six_n_UNCONNECTED,
      add_input_two_n => NLW_wtd_cor_add_input_two_n_UNCONNECTED,
      reg_decr_cor => reg_decr_cor,
      cor_num(2) => NLW_wtd_cor_cor_num_2_UNCONNECTED,
      cor_num(1) => NLW_wtd_cor_cor_num_1_UNCONNECTED,
      cor_num(0) => cor_num_int(0)
    );
  cplu_cntr : cmm_errman_cnt_en
    port map (
      inc_dec_b => cplu_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      enable => NLW_cplu_cntr_enable_UNCONNECTED,
      count(3) => cnt_cplu(3),
      count(2) => cnt_cplu(2),
      count(1) => cnt_cplu(1),
      count(0) => cnt_cplu(0),
      index(2) => cplu_num(2),
      index(1) => cplu_num(1),
      index(0) => cplu_num(0)
    );
  cplt_cntr : cmm_errman_cnt_en_INST_1
    port map (
      inc_dec_b => cplt_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      enable => NLW_cplt_cntr_enable_UNCONNECTED,
      count(3) => cnt_cplt(3),
      count(2) => cnt_cplt(2),
      count(1) => cnt_cplt(1),
      count(0) => cnt_cplt(0),
      index(2) => cplt_num(2),
      index(1) => cplt_num(1),
      index(0) => cplt_num(0)
    );
  ftl_cntr : cmm_errman_cnt_en_INST_2
    port map (
      inc_dec_b => ftl_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      enable => err_ftl_en,
      count(3) => cnt_ftl(3),
      count(2) => cnt_ftl(2),
      count(1) => cnt_ftl(1),
      count(0) => cnt_ftl(0),
      index(2) => ftl_num(2),
      index(1) => ftl_num(1),
      index(0) => ftl_num(0)
    );
  nfl_cntr : cmm_errman_cnt_en_INST_3
    port map (
      inc_dec_b => nfl_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      enable => NLW_nfl_cntr_enable_UNCONNECTED,
      count(3) => cnt_nfl(3),
      count(2) => cnt_nfl(2),
      count(1) => cnt_nfl(1),
      count(0) => cnt_nfl(0),
      index(2) => nfl_num(2),
      index(1) => nfl_num(1),
      index(0) => nfl_num(0)
    );
  cor_cntr : cmm_errman_cnt_en_INST_4
    port map (
      inc_dec_b => cor_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      enable => cfg_dcommand(0),
      count(3) => cnt_cor(3),
      count(2) => cnt_cor(2),
      count(1) => cnt_cor(1),
      count(0) => cnt_cor(0),
      index(2) => cor_num(2),
      index(1) => cor_num(1),
      index(0) => cor_num(0)
    );
  wtd_ftl : cmm_errman_ftl
    port map (
      inc_dec_b => ftl_add_sub_b,
      clk => clk,
      rst => rst_n_inv,
      cmmt_err_tlp_malformed => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      cmmt_err_fc => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      cmmt_err_rbuf_overflow => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      cmmp_training_err => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      decr_ftl => decr_ftl,
      cmml_protocol_err_n => NLW_wtd_ftl_cmml_protocol_err_n_UNCONNECTED,
      ftl_num(2) => ftl_num(2),
      ftl_num(1) => ftl_num(1),
      ftl_num(0) => ftl_num(0)
    );
  wtd_cplu : cmm_errman_cpl
    port map (
      inc_dec_b => cplu_add_sub_b,
      clk => clk,
      decr_cpl => decr_cplu,
      rst => rst_n_inv,
      cmm_err_tlp_posted => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      cpl_num(2) => cplu_num(2),
      cpl_num(1) => cplu_num(1),
      cpl_num(0) => cplu_num(0)
    );
  wtd_cplt : cmm_errman_cpl_INST_1
    port map (
      inc_dec_b => cplt_add_sub_b,
      clk => clk,
      decr_cpl => decr_cplt,
      rst => rst_n_inv,
      cmm_err_tlp_posted => tlp_is_np_and_ur,
      cpl_num(2) => cplt_num(2),
      cpl_num(1) => cplt_num(1),
      cpl_num(0) => cplt_num(0)
    );
  cmt_hdr_buf : cmm_errman_ram4x26
    port map (
      clk => clk,
      rst => rst_n_inv,
      we => reg_incr_cplt_20410,
      rddata(49) => cmt_rd_hdr(49),
      rddata(48) => cmt_rd_hdr(48),
      rddata(47) => cmt_rd_hdr(47),
      rddata(46) => cmt_rd_hdr(46),
      rddata(45) => cmt_rd_hdr(45),
      rddata(44) => cmt_rd_hdr(44),
      rddata(43) => cmt_rd_hdr(43),
      rddata(42) => cmt_rd_hdr(42),
      rddata(41) => cmt_rd_hdr(41),
      rddata(40) => cmt_rd_hdr(40),
      rddata(39) => cmt_rd_hdr(39),
      rddata(38) => cmt_rd_hdr(38),
      rddata(37) => cmt_rd_hdr(37),
      rddata(36) => cmt_rd_hdr(36),
      rddata(35) => cmt_rd_hdr(35),
      rddata(34) => cmt_rd_hdr(34),
      rddata(33) => cmt_rd_hdr(33),
      rddata(32) => cmt_rd_hdr(32),
      rddata(31) => cmt_rd_hdr(31),
      rddata(30) => cmt_rd_hdr(30),
      rddata(29) => cmt_rd_hdr(29),
      rddata(28) => cmt_rd_hdr(28),
      rddata(27) => cmt_rd_hdr(27),
      rddata(26) => cmt_rd_hdr(26),
      rddata(25) => cmt_rd_hdr(25),
      rddata(24) => cmt_rd_hdr(24),
      rddata(23) => cmt_rd_hdr(23),
      rddata(22) => cmt_rd_hdr(22),
      rddata(21) => cmt_rd_hdr(21),
      rddata(20) => cmt_rd_hdr(20),
      rddata(19) => cmt_rd_hdr(19),
      rddata(18) => cmt_rd_hdr(18),
      rddata(17) => cmt_rd_hdr(17),
      rddata(16) => cmt_rd_hdr(16),
      rddata(15) => cmt_rd_hdr(15),
      rddata(14) => cmt_rd_hdr(14),
      rddata(13) => cmt_rd_hdr(13),
      rddata(12) => cmt_rd_hdr(12),
      rddata(11) => cmt_rd_hdr(11),
      rddata(10) => cmt_rd_hdr(10),
      rddata(9) => cmt_rd_hdr(9),
      rddata(8) => cmt_rd_hdr(8),
      rddata(7) => cmt_rd_hdr(7),
      rddata(6) => cmt_rd_hdr(6),
      rddata(5) => cmt_rd_hdr(5),
      rddata(4) => cmt_rd_hdr(4),
      rddata(3) => cmt_rd_hdr(3),
      rddata(2) => cmt_rd_hdr(2),
      rddata(1) => cmt_rd_hdr(1),
      rddata(0) => cmt_rd_hdr(0),
      wrdata(49) => reg_cmt_wr_hdr_49_Q,
      wrdata(48) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(47) => reg_cmt_wr_hdr_47_Q,
      wrdata(46) => reg_cmt_wr_hdr_46_Q,
      wrdata(45) => reg_cmt_wr_hdr_45_Q,
      wrdata(44) => reg_cmt_wr_hdr_44_Q,
      wrdata(43) => reg_cmt_wr_hdr_43_Q,
      wrdata(42) => reg_cmt_wr_hdr_42_Q,
      wrdata(41) => reg_cmt_wr_hdr_41_Q,
      wrdata(40) => reg_cmt_wr_hdr_40_Q,
      wrdata(39) => reg_cmt_wr_hdr_39_Q,
      wrdata(38) => reg_cmt_wr_hdr_38_Q,
      wrdata(37) => reg_cmt_wr_hdr_37_Q,
      wrdata(36) => reg_cmt_wr_hdr_36_Q,
      wrdata(35) => reg_cmt_wr_hdr_35_Q,
      wrdata(34) => reg_cmt_wr_hdr_34_Q,
      wrdata(33) => reg_cmt_wr_hdr_33_Q,
      wrdata(32) => reg_cmt_wr_hdr_32_Q,
      wrdata(31) => reg_cmt_wr_hdr_31_Q,
      wrdata(30) => reg_cmt_wr_hdr_30_Q,
      wrdata(29) => reg_cmt_wr_hdr_29_Q,
      wrdata(28) => reg_cmt_wr_hdr_28_Q,
      wrdata(27) => reg_cmt_wr_hdr_27_Q,
      wrdata(26) => reg_cmt_wr_hdr_26_Q,
      wrdata(25) => reg_cmt_wr_hdr_25_Q,
      wrdata(24) => reg_cmt_wr_hdr_24_Q,
      wrdata(23) => reg_cmt_wr_hdr_23_Q,
      wrdata(22) => reg_cmt_wr_hdr_22_Q,
      wrdata(21) => reg_cmt_wr_hdr_21_Q,
      wrdata(20) => reg_cmt_wr_hdr_20_Q,
      wrdata(19) => reg_cmt_wr_hdr_19_Q,
      wrdata(18) => reg_cmt_wr_hdr_18_Q,
      wrdata(17) => reg_cmt_wr_hdr_17_Q,
      wrdata(16) => reg_cmt_wr_hdr_16_Q,
      wrdata(15) => reg_cmt_wr_hdr_15_Q,
      wrdata(14) => reg_cmt_wr_hdr_14_Q,
      wrdata(13) => reg_cmt_wr_hdr_13_Q,
      wrdata(12) => reg_cmt_wr_hdr_12_Q,
      wrdata(11) => reg_cmt_wr_hdr_11_Q,
      wrdata(10) => reg_cmt_wr_hdr_10_Q,
      wrdata(9) => reg_cmt_wr_hdr_9_Q,
      wrdata(8) => reg_cmt_wr_hdr_8_Q,
      wrdata(7) => reg_cmt_wr_hdr_7_Q,
      wrdata(6) => reg_cmt_wr_hdr_6_Q,
      wrdata(5) => reg_cmt_wr_hdr_5_Q,
      wrdata(4) => reg_cmt_wr_hdr_4_Q,
      wrdata(3) => reg_cmt_wr_hdr_3_Q,
      wrdata(2) => reg_cmt_wr_hdr_2_Q,
      wrdata(1) => reg_cmt_wr_hdr_1_Q,
      wrdata(0) => reg_cmt_wr_hdr_0_Q,
      rd_ptr(1) => reg_cmt_rp(1),
      rd_ptr(0) => reg_cmt_rp(0),
      wr_ptr(1) => reg_cmt_wp(1),
      wr_ptr(0) => reg_cmt_wp(0)
    );
  cfg_hdr_buf : cmm_errman_ram8x26
    port map (
      clk => clk,
      rst => rst_n_inv,
      we => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      rddata(49) => cfg_rd_hdr(49),
      rddata(48) => cfg_rd_hdr(48),
      rddata(47) => cfg_rd_hdr(47),
      rddata(46) => cfg_rd_hdr(46),
      rddata(45) => cfg_rd_hdr(45),
      rddata(44) => cfg_rd_hdr(44),
      rddata(43) => cfg_rd_hdr(43),
      rddata(42) => cfg_rd_hdr(42),
      rddata(41) => cfg_rd_hdr(41),
      rddata(40) => cfg_rd_hdr(40),
      rddata(39) => cfg_rd_hdr(39),
      rddata(38) => cfg_rd_hdr(38),
      rddata(37) => cfg_rd_hdr(37),
      rddata(36) => cfg_rd_hdr(36),
      rddata(35) => cfg_rd_hdr(35),
      rddata(34) => cfg_rd_hdr(34),
      rddata(33) => cfg_rd_hdr(33),
      rddata(32) => cfg_rd_hdr(32),
      rddata(31) => cfg_rd_hdr(31),
      rddata(30) => cfg_rd_hdr(30),
      rddata(29) => cfg_rd_hdr(29),
      rddata(28) => cfg_rd_hdr(28),
      rddata(27) => cfg_rd_hdr(27),
      rddata(26) => cfg_rd_hdr(26),
      rddata(25) => cfg_rd_hdr(25),
      rddata(24) => cfg_rd_hdr(24),
      rddata(23) => cfg_rd_hdr(23),
      rddata(22) => cfg_rd_hdr(22),
      rddata(21) => cfg_rd_hdr(21),
      rddata(20) => cfg_rd_hdr(20),
      rddata(19) => cfg_rd_hdr(19),
      rddata(18) => cfg_rd_hdr(18),
      rddata(17) => cfg_rd_hdr(17),
      rddata(16) => cfg_rd_hdr(16),
      rddata(15) => cfg_rd_hdr(15),
      rddata(14) => cfg_rd_hdr(14),
      rddata(13) => cfg_rd_hdr(13),
      rddata(12) => cfg_rd_hdr(12),
      rddata(11) => cfg_rd_hdr(11),
      rddata(10) => cfg_rd_hdr(10),
      rddata(9) => cfg_rd_hdr(9),
      rddata(8) => cfg_rd_hdr(8),
      rddata(7) => cfg_rd_hdr(7),
      rddata(6) => cfg_rd_hdr(6),
      rddata(5) => cfg_rd_hdr(5),
      rddata(4) => cfg_rd_hdr(4),
      rddata(3) => cfg_rd_hdr(3),
      rddata(2) => cfg_rd_hdr(2),
      rddata(1) => cfg_rd_hdr(1),
      rddata(0) => cfg_rd_hdr(0),
      wrdata(49) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(48) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(47) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(46) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(45) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(44) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(43) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(42) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(41) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(40) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(39) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(38) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(37) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(36) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(35) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(34) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(33) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(32) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(31) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(30) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(29) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(28) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(27) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(26) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(25) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(24) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(23) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(22) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(21) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(20) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(19) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(18) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(17) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(16) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(15) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(14) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(13) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(12) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(11) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(10) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(9) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(8) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(7) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(6) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(5) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(4) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(3) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(2) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(1) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wrdata(0) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      rd_ptr(2) => reg_cfg_rp(2),
      rd_ptr(1) => reg_cfg_rp(1),
      rd_ptr(0) => reg_cfg_rp(0),
      wr_ptr(2) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wr_ptr(1) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort,
      wr_ptr(0) => NlwRenamedSig_OI_l0_set_user_signaled_target_abort
    );
  Madd_reg_cmt_wp_add0000_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_cmt_wp(1),
      I1 => reg_cmt_wp(0),
      O => reg_cmt_wp_add0000(1)
    );
  Madd_reg_cmt_rp_add0000_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_cmt_rp(1),
      I1 => reg_cmt_rp(0),
      O => reg_cmt_rp_add0000(1)
    );
  Madd_reg_cfg_rp_add0000_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_cfg_rp(1),
      I1 => reg_cfg_rp(0),
      O => reg_cfg_rp_add0000(1)
    );
  Madd_reg_cfg_rp_add0000_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => reg_cfg_rp(1),
      I1 => reg_cfg_rp(2),
      I2 => reg_cfg_rp(0),
      O => reg_cfg_rp_add0000(2)
    );
  send_nfl_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cnt_nfl(1),
      I1 => cnt_nfl(0),
      I2 => cnt_nfl(3),
      I3 => cnt_nfl(2),
      O => send_nfl_or0000
    );
  send_ftl_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cnt_ftl(1),
      I1 => cnt_ftl(0),
      I2 => cnt_ftl(3),
      I3 => cnt_ftl(2),
      O => send_ftl_or0000
    );
  send_cplu_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cnt_cplu(1),
      I1 => cnt_cplu(0),
      I2 => cnt_cplu(3),
      I3 => cnt_cplu(2),
      O => send_cplu_or0000
    );
  send_cplt_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cnt_cplt(1),
      I1 => cnt_cplt(0),
      I2 => cnt_cplt(3),
      I3 => cnt_cplt(2),
      O => send_cplt_or0000
    );
  send_cor_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cnt_cor(1),
      I1 => cnt_cor(0),
      I2 => cnt_cor(3),
      I3 => cnt_cor(2),
      O => send_cor_or0000
    );
  reg_unsupportedreq_and00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => rx_err_tlp_ur_n,
      I1 => rx_err_tlp_p_cpl_n,
      O => reg_unsupportedreq_and0000
    );
  reg_masterdataparityerror_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => rx_err_cpl_ep_n,
      I1 => tx_err_wr_ep_n,
      O => reg_masterdataparityerror_or0000
    );
  err_ftl_en1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => cfg_dcommand(2),
      I1 => cfg_command(8),
      O => err_ftl_en
    );
  decr_nfl1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cs_is_nfl,
      I1 => grant,
      O => decr_nfl
    );
  decr_ftl1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cs_is_ftl,
      I1 => grant,
      O => decr_ftl
    );
  decr_cplu1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cs_is_cplu,
      I1 => grant,
      O => decr_cplu
    );
  decr_cplt1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cs_is_cplt,
      I1 => grant,
      O => decr_cplt
    );
  decr_cor1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cs_is_cor,
      I1 => grant,
      O => decr_cor
    );
  reg_masterdataparityerror_or00011 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => rst_n,
      I1 => cfg_command(6),
      O => reg_masterdataparityerror_not0001_inv
    );
  reg_signaledsystemerror_or00011 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => grant,
      I1 => rst_n,
      I2 => cfg_command(8),
      O => reg_signaledsystemerror_not0001_inv
    );
  reg_signaledsystemerror_or00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF08"
    )
    port map (
      I0 => cfg_dcommand(3),
      I1 => cs_is_cplt,
      I2 => request_data(48),
      I3 => cs_is_ftl,
      I4 => cs_is_nfl,
      I5 => cs_is_cplu,
      O => reg_signaledsystemerror_or0000
    );
  nfl_num_2_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => nfl_num_int(0),
      I1 => reg_decr_nfl,
      O => nfl_num(2)
    );
  tlp_is_np_and_ur1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => rx_err_tlp_ur_n,
      I1 => rx_err_tlp_p_cpl_n,
      O => tlp_is_np_and_ur
    );
  cor_num_2_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cor_num_int(0),
      I1 => reg_decr_cor,
      O => cor_num(2)
    );
  nfl_num_1_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => nfl_num_int(0),
      I1 => reg_decr_nfl,
      O => nfl_num(1)
    );
  Msub_nfl_num_xor_0_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => nfl_num_int(0),
      I1 => reg_decr_nfl,
      O => nfl_num(0)
    );
  cor_num_1_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cor_num_int(0),
      I1 => reg_decr_cor,
      O => cor_num(1)
    );
  Msub_cor_num_xor_0_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => cor_num_int(0),
      I1 => reg_decr_cor,
      O => cor_num(0)
    );
  reg_cmt_wr_hdr_or00001 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => rst_n,
      I1 => rx_err_tlp_p_cpl_n,
      I2 => rx_err_tlp_ur_n,
      O => reg_cmt_wr_hdr_not0001_inv
    );
  Madd_reg_cmt_wp_add0000_xor_0_11_INV_0 : INV
    port map (
      I => reg_cmt_wp(0),
      O => reg_cmt_wp_add0000(0)
    );
  Madd_reg_cmt_rp_add0000_xor_0_11_INV_0 : INV
    port map (
      I => reg_cmt_rp(0),
      O => reg_cmt_rp_add0000(0)
    );
  Madd_reg_cfg_rp_add0000_xor_0_11_INV_0 : INV
    port map (
      I => reg_cfg_rp(0),
      O => reg_cfg_rp_add0000(0)
    );
  reg_receivedtargetabort_not00011_INV_0 : INV
    port map (
      I => rx_err_cpl_abort_n,
      O => reg_receivedtargetabort_not0001
    );
  reg_receivedmasterabort_not00011_INV_0 : INV
    port map (
      I => rx_err_cpl_ur_n,
      O => reg_receivedmasterabort_not0001
    );
  reg_detectedparityerror_not00011_INV_0 : INV
    port map (
      I => rx_err_ep_n,
      O => reg_detectedparityerror_not0001
    );
  reg_detectedfatal_not00011_INV_0 : INV
    port map (
      I => rx_err_tlp_malformed_n,
      O => reg_detectedfatal_not0001
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_cf_mgmt is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
    mgmt_rden : out STD_LOGIC; 
    l0_set_detected_corr_error : in STD_LOGIC := 'X'; 
    mgmt_wren : out STD_LOGIC; 
    cfg_rd_en_n : in STD_LOGIC := 'X'; 
    cfg_rd_wr_done_n : out STD_LOGIC; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    l0_stats_cfg_received : in STD_LOGIC := 'X'; 
    l0_set_unsupported_request_other_error : in STD_LOGIC := 'X'; 
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_msguaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mgmt_bwren : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    mgmt_addr : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_dcap : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_xrom : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_pmcsr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_msgctrl : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_msgladdr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_msgdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_rx_bar0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    mgmt_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar4 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar5 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    mgmt_pso : in STD_LOGIC_VECTOR ( 16 downto 0 ); 
    l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    completer_id : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_dwaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_rx_data_d : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mgmt_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end pcie_blk_cf_mgmt;

architecture STRUCTURE of pcie_blk_cf_mgmt is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal cfg_dcap_not0001 : STD_LOGIC; 
  signal cfg_dstatus_not0001 : STD_LOGIC; 
  signal cfg_lstatus_not0001 : STD_LOGIC; 
  signal cfg_msgctrl_not0001 : STD_LOGIC; 
  signal cfg_msgdata_not0001 : STD_LOGIC; 
  signal cfg_msgladdr_not0001 : STD_LOGIC; 
  signal cfg_msguaddr_not0001 : STD_LOGIC; 
  signal cfg_pmcsr_not0001 : STD_LOGIC; 
  signal cfg_rx_bar0_not0001 : STD_LOGIC; 
  signal cfg_rx_bar1_not0001 : STD_LOGIC; 
  signal cfg_rx_bar2_not0001 : STD_LOGIC; 
  signal cfg_rx_xrom_not0001 : STD_LOGIC; 
  signal cfg_status_not0001 : STD_LOGIC; 
  signal detected_cfg_read1cycle_19530 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq0000 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq00001201_19532 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq0000135_19533 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq00001561 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq0000171_19535 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq000028_19536 : STD_LOGIC; 
  signal detected_cfg_read1cycle_cmp_eq000064_19537 : STD_LOGIC; 
  signal detected_cfg_read1cycle_or0000_inv : STD_LOGIC; 
  signal detected_h48read_19539 : STD_LOGIC; 
  signal detected_h48read_and0000 : STD_LOGIC; 
  signal detected_h48read_d_19541 : STD_LOGIC; 
  signal detected_h68read_19542 : STD_LOGIC; 
  signal detected_h68read_and0000 : STD_LOGIC; 
  signal detected_h68read_d_19544 : STD_LOGIC; 
  signal fabric_co_error_detect : STD_LOGIC; 
  signal fabric_co_error_detected_19546 : STD_LOGIC; 
  signal fabric_co_error_detected_or0000 : STD_LOGIC; 
  signal fabric_ur_error_detected_19548 : STD_LOGIC; 
  signal fabric_ur_error_detected_or0000 : STD_LOGIC; 
  signal falseur_cfg_access_wr_reg_19550 : STD_LOGIC; 
  signal falseur_cfg_access_wr_reg_and0000 : STD_LOGIC; 
  signal falseur_cfg_access_wr_reg_inv : STD_LOGIC; 
  signal falseur_cfg_access_wr_reg_or0000 : STD_LOGIC; 
  signal mgmt_addr_or0000 : STD_LOGIC; 
  signal mgmt_pso_co_d_19624 : STD_LOGIC; 
  signal mgmt_pso_co_fell_d_19625 : STD_LOGIC; 
  signal mgmt_pso_co_fell_d_and0000 : STD_LOGIC; 
  signal mgmt_pso_ur_d_19627 : STD_LOGIC; 
  signal mgmt_pso_ur_fell_d_19628 : STD_LOGIC; 
  signal mgmt_pso_ur_fell_d_and0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_rden : STD_LOGIC; 
  signal mgmt_rden_or0000 : STD_LOGIC; 
  signal mgmt_wdata_and0000 : STD_LOGIC; 
  signal mgmt_wdata_mux0000_16_Q : STD_LOGIC; 
  signal mgmt_wdata_mux0000_17_Q : STD_LOGIC; 
  signal mgmt_wdata_mux0000_18_Q : STD_LOGIC; 
  signal mgmt_wdata_mux0000_19_Q : STD_LOGIC; 
  signal mgmt_wdata_mux0000_21_Q : STD_LOGIC; 
  signal mgmt_wdata_not0001 : STD_LOGIC; 
  signal mgmt_wren_not0001_inv : STD_LOGIC; 
  signal mgmt_wren_or0000 : STD_LOGIC; 
  signal msi_ctrl_cfg_access_wr_reg_19712 : STD_LOGIC; 
  signal msi_ctrl_cfg_access_wr_reg_and0000 : STD_LOGIC; 
  signal msi_ctrl_cfg_access_wr_reg_inv : STD_LOGIC; 
  signal poll_data_en : STD_LOGIC; 
  signal poll_data_en_d_19716 : STD_LOGIC; 
  signal poll_dwaddr_cntr_not0001 : STD_LOGIC; 
  signal poll_dwrw : STD_LOGIC; 
  signal poll_en_19741 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal wait_stg1_19744 : STD_LOGIC; 
  signal wait_stg2_19745 : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom6_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom5_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom4_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom3_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom2_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom1_O_UNCONNECTED : STD_LOGIC; 
  signal NLW_lut_cfgdw_rom0_O_UNCONNECTED : STD_LOGIC; 
  signal Result : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal NlwRenamedSignal_cfg_bus_number : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSignal_cfg_device_number : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal l0_dll_error_vector_d : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal l0_rx_mac_link_error_d : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal mgmt_addr_mux0000 : STD_LOGIC_VECTOR ( 10 downto 4 ); 
  signal mgmt_bwren_mux0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal mgmt_rdata_d1 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSig_OI_mgmt_wdata : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal poll_dwaddr_cntr : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal poll_dwaddr_cntr_d1 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal poll_dwaddr_cntr_d2 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal poll_dwaddrx : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  mgmt_rden <= NlwRenamedSig_OI_mgmt_rden;
  cfg_device_number(4) <= NlwRenamedSignal_cfg_device_number(4);
  cfg_device_number(3) <= NlwRenamedSignal_cfg_device_number(3);
  cfg_device_number(2) <= NlwRenamedSignal_cfg_device_number(2);
  cfg_device_number(1) <= NlwRenamedSignal_cfg_device_number(1);
  cfg_device_number(0) <= NlwRenamedSignal_cfg_device_number(0);
  mgmt_addr(10) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_addr(9) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_addr(8) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_addr(7) <= NlwRenamedSig_OI_mgmt_wdata(0);
  cfg_bus_number(7) <= NlwRenamedSignal_cfg_bus_number(7);
  cfg_bus_number(6) <= NlwRenamedSignal_cfg_bus_number(6);
  cfg_bus_number(5) <= NlwRenamedSignal_cfg_bus_number(5);
  cfg_bus_number(4) <= NlwRenamedSignal_cfg_bus_number(4);
  cfg_bus_number(3) <= NlwRenamedSignal_cfg_bus_number(3);
  cfg_bus_number(2) <= NlwRenamedSignal_cfg_bus_number(2);
  cfg_bus_number(1) <= NlwRenamedSignal_cfg_bus_number(1);
  cfg_bus_number(0) <= NlwRenamedSignal_cfg_bus_number(0);
  cfg_function_number(2) <= NlwRenamedSig_OI_mgmt_wdata(0);
  cfg_function_number(1) <= NlwRenamedSig_OI_mgmt_wdata(0);
  cfg_function_number(0) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(31) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(30) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(29) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(28) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(27) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(26) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(25) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(24) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(23) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(22) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(20) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(15) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(14) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(13) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(12) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(11) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(10) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(9) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(8) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(7) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(6) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(5) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(4) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(3) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(2) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(1) <= NlwRenamedSig_OI_mgmt_wdata(0);
  mgmt_wdata(0) <= NlwRenamedSig_OI_mgmt_wdata(0);
  NlwRenamedSignal_cfg_bus_number(7) <= completer_id(12);
  NlwRenamedSignal_cfg_bus_number(6) <= completer_id(11);
  NlwRenamedSignal_cfg_bus_number(5) <= completer_id(10);
  NlwRenamedSignal_cfg_bus_number(4) <= completer_id(9);
  NlwRenamedSignal_cfg_bus_number(3) <= completer_id(8);
  NlwRenamedSignal_cfg_bus_number(2) <= completer_id(7);
  NlwRenamedSignal_cfg_bus_number(1) <= completer_id(6);
  NlwRenamedSignal_cfg_bus_number(0) <= completer_id(5);
  NlwRenamedSignal_cfg_device_number(4) <= completer_id(4);
  NlwRenamedSignal_cfg_device_number(3) <= completer_id(3);
  NlwRenamedSignal_cfg_device_number(2) <= completer_id(2);
  NlwRenamedSignal_cfg_device_number(1) <= completer_id(1);
  NlwRenamedSignal_cfg_device_number(0) <= completer_id(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_mgmt_wdata(0)
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  mgmt_addr_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(10),
      S => rst_n_inv,
      Q => mgmt_addr(0)
    );
  mgmt_addr_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(9),
      S => rst_n_inv,
      Q => mgmt_addr(1)
    );
  mgmt_addr_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(8),
      S => rst_n_inv,
      Q => mgmt_addr(2)
    );
  mgmt_addr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(7),
      R => rst_n_inv,
      Q => mgmt_addr(3)
    );
  mgmt_addr_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(6),
      R => rst_n_inv,
      Q => mgmt_addr(4)
    );
  mgmt_addr_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(5),
      R => rst_n_inv,
      Q => mgmt_addr(5)
    );
  mgmt_addr_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_addr_mux0000(4),
      S => rst_n_inv,
      Q => mgmt_addr(6)
    );
  mgmt_wdata_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_wdata_not0001,
      D => mgmt_wdata_mux0000_16_Q,
      R => rst_n_inv,
      Q => mgmt_wdata(16)
    );
  mgmt_wdata_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_wdata_not0001,
      D => mgmt_wdata_mux0000_17_Q,
      R => rst_n_inv,
      Q => mgmt_wdata(17)
    );
  mgmt_wdata_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_wdata_not0001,
      D => mgmt_wdata_mux0000_18_Q,
      R => rst_n_inv,
      Q => mgmt_wdata(18)
    );
  mgmt_wdata_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_wdata_not0001,
      D => mgmt_wdata_mux0000_19_Q,
      R => rst_n_inv,
      Q => mgmt_wdata(19)
    );
  mgmt_wdata_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_wdata_not0001,
      D => mgmt_wdata_mux0000_21_Q,
      R => rst_n_inv,
      Q => mgmt_wdata(21)
    );
  poll_en : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => mgmt_addr_or0000,
      D => mgmt_wdata_and0000,
      R => rst_n_inv,
      Q => poll_en_19741
    );
  mgmt_rden_10641 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => N1,
      R => mgmt_rden_or0000,
      Q => NlwRenamedSig_OI_mgmt_rden
    );
  mgmt_wren_10642 : FDRS
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_wdata(0),
      R => mgmt_wren_not0001_inv,
      S => mgmt_wren_or0000,
      Q => mgmt_wren
    );
  mgmt_bwren_0 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => N4,
      Q => mgmt_bwren(0)
    );
  mgmt_bwren_1 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => N4,
      Q => mgmt_bwren(1)
    );
  mgmt_bwren_2 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => mgmt_bwren_mux0000(1),
      Q => mgmt_bwren(2)
    );
  mgmt_bwren_3 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => falseur_cfg_access_wr_reg_inv,
      Q => mgmt_bwren(3)
    );
  poll_data_en_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_data_en,
      R => rst_n_inv,
      Q => poll_data_en_d_19716
    );
  mgmt_rdata_d1_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(0),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(0)
    );
  mgmt_rdata_d1_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(1),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(1)
    );
  mgmt_rdata_d1_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(2),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(2)
    );
  mgmt_rdata_d1_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(3),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(3)
    );
  mgmt_rdata_d1_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(4),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(4)
    );
  mgmt_rdata_d1_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(5),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(5)
    );
  mgmt_rdata_d1_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(6),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(6)
    );
  mgmt_rdata_d1_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(7),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(7)
    );
  mgmt_rdata_d1_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(8),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(8)
    );
  mgmt_rdata_d1_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(9),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(9)
    );
  mgmt_rdata_d1_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(10),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(10)
    );
  mgmt_rdata_d1_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(11),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(11)
    );
  mgmt_rdata_d1_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(12),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(12)
    );
  mgmt_rdata_d1_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(13),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(13)
    );
  mgmt_rdata_d1_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(14),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(14)
    );
  mgmt_rdata_d1_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(15),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(15)
    );
  mgmt_rdata_d1_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(16),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(16)
    );
  mgmt_rdata_d1_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(17),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(17)
    );
  mgmt_rdata_d1_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(18),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(18)
    );
  mgmt_rdata_d1_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(19),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(19)
    );
  mgmt_rdata_d1_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(20),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(20)
    );
  mgmt_rdata_d1_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(21),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(21)
    );
  mgmt_rdata_d1_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(22),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(22)
    );
  mgmt_rdata_d1_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(23),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(23)
    );
  mgmt_rdata_d1_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(24),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(24)
    );
  mgmt_rdata_d1_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(25),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(25)
    );
  mgmt_rdata_d1_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(26),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(26)
    );
  mgmt_rdata_d1_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(27),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(27)
    );
  mgmt_rdata_d1_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(28),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(28)
    );
  mgmt_rdata_d1_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(29),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(29)
    );
  mgmt_rdata_d1_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(30),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(30)
    );
  mgmt_rdata_d1_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_stg2_19745,
      D => mgmt_rdata(31),
      R => rst_n_inv,
      Q => mgmt_rdata_d1(31)
    );
  mgmt_pso_ur_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_pso(7),
      R => rst_n_inv,
      Q => mgmt_pso_ur_d_19627
    );
  mgmt_pso_co_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_pso(10),
      R => rst_n_inv,
      Q => mgmt_pso_co_d_19624
    );
  l0_dll_error_vector_d_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => l0_dll_error_vector(0),
      R => rst_n_inv,
      Q => l0_dll_error_vector_d(0)
    );
  l0_dll_error_vector_d_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => l0_dll_error_vector(1),
      R => rst_n_inv,
      Q => l0_dll_error_vector_d(1)
    );
  l0_dll_error_vector_d_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => l0_dll_error_vector(2),
      R => rst_n_inv,
      Q => l0_dll_error_vector_d(2)
    );
  l0_dll_error_vector_d_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => l0_dll_error_vector(3),
      R => rst_n_inv,
      Q => l0_dll_error_vector_d(3)
    );
  mgmt_pso_co_fell_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_pso_co_fell_d_and0000,
      R => rst_n_inv,
      Q => mgmt_pso_co_fell_d_19625
    );
  mgmt_pso_ur_fell_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_pso_ur_fell_d_and0000,
      R => rst_n_inv,
      Q => mgmt_pso_ur_fell_d_19628
    );
  fabric_co_error_detected : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fabric_co_error_detect,
      D => N1,
      R => fabric_co_error_detected_or0000,
      Q => fabric_co_error_detected_19546
    );
  l0_rx_mac_link_error_d_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => l0_rx_mac_link_error(1),
      R => rst_n_inv,
      Q => l0_rx_mac_link_error_d(1)
    );
  detected_h68read : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => detected_h68read_and0000,
      R => rst_n_inv,
      Q => detected_h68read_19542
    );
  fabric_ur_error_detected : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => l0_set_unsupported_request_other_error,
      D => N1,
      R => fabric_ur_error_detected_or0000,
      Q => fabric_ur_error_detected_19548
    );
  detected_cfg_read1cycle : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => detected_cfg_read1cycle_or0000_inv,
      D => NlwRenamedSig_OI_mgmt_wdata(0),
      R => rst_n_inv,
      S => detected_cfg_read1cycle_cmp_eq0000,
      Q => detected_cfg_read1cycle_19530
    );
  detected_h48read : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => detected_h48read_and0000,
      R => rst_n_inv,
      Q => detected_h48read_19539
    );
  falseur_cfg_access_wr_reg : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => falseur_cfg_access_wr_reg_inv,
      D => falseur_cfg_access_wr_reg_and0000,
      R => falseur_cfg_access_wr_reg_or0000,
      Q => falseur_cfg_access_wr_reg_19550
    );
  msi_ctrl_cfg_access_wr_reg : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => msi_ctrl_cfg_access_wr_reg_inv,
      D => msi_ctrl_cfg_access_wr_reg_and0000,
      R => falseur_cfg_access_wr_reg_or0000,
      Q => msi_ctrl_cfg_access_wr_reg_19712
    );
  poll_dwaddr_cntr_d1_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => poll_dwaddr_cntr(0),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d1(0)
    );
  poll_dwaddr_cntr_d1_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => poll_dwaddr_cntr(1),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d1(1)
    );
  poll_dwaddr_cntr_d1_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => poll_dwaddr_cntr(2),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d1(2)
    );
  poll_dwaddr_cntr_d1_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => poll_dwaddr_cntr(3),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d1(3)
    );
  poll_dwaddr_cntr_d1_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => poll_dwaddr_cntr(4),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d1(4)
    );
  wait_stg1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_rden,
      R => rst_n_inv,
      Q => wait_stg1_19744
    );
  cfg_command_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_status_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_command(1)
    );
  cfg_command_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_status_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_command(2)
    );
  cfg_command_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_status_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_command(6)
    );
  cfg_command_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_status_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_command(8)
    );
  cfg_command_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_status_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_command(10)
    );
  cfg_lstatus_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_lstatus_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_lstatus(4)
    );
  cfg_lstatus_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_lstatus_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_lstatus(5)
    );
  cfg_lstatus_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_lstatus_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_lstatus(6)
    );
  cfg_dcommand_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dstatus_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_dcommand(0)
    );
  cfg_dcommand_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dstatus_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_dcommand(2)
    );
  cfg_dcommand_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dstatus_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_dcommand(3)
    );
  cfg_dcommand_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dstatus_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_dcommand(5)
    );
  cfg_dcommand_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dstatus_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_dcommand(9)
    );
  cfg_dcap_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dcap_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_dcap(0)
    );
  cfg_dcap_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dcap_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_dcap(1)
    );
  cfg_dcap_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_dcap_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_dcap(2)
    );
  cfg_pmcsr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_pmcsr_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_pmcsr(0)
    );
  cfg_pmcsr_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_pmcsr_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_pmcsr(1)
    );
  cfg_msguaddr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_msguaddr(0)
    );
  cfg_msguaddr_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_msguaddr(1)
    );
  cfg_msguaddr_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_msguaddr(2)
    );
  cfg_msguaddr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_msguaddr(3)
    );
  cfg_msguaddr_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_msguaddr(4)
    );
  cfg_msguaddr_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_msguaddr(5)
    );
  cfg_msguaddr_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_msguaddr(6)
    );
  cfg_msguaddr_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_msguaddr(7)
    );
  cfg_msguaddr_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_msguaddr(8)
    );
  cfg_msguaddr_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_msguaddr(9)
    );
  cfg_msguaddr_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_msguaddr(10)
    );
  cfg_msguaddr_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_msguaddr(11)
    );
  cfg_msguaddr_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_msguaddr(12)
    );
  cfg_msguaddr_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_msguaddr(13)
    );
  cfg_msguaddr_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_msguaddr(14)
    );
  cfg_msguaddr_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_msguaddr(15)
    );
  cfg_msguaddr_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_msguaddr(16)
    );
  cfg_msguaddr_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_msguaddr(17)
    );
  cfg_msguaddr_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_msguaddr(18)
    );
  cfg_msguaddr_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_msguaddr(19)
    );
  cfg_msguaddr_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_msguaddr(20)
    );
  cfg_msguaddr_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_msguaddr(21)
    );
  cfg_msguaddr_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_msguaddr(22)
    );
  cfg_msguaddr_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_msguaddr(23)
    );
  cfg_msguaddr_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_msguaddr(24)
    );
  cfg_msguaddr_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_msguaddr(25)
    );
  cfg_msguaddr_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_msguaddr(26)
    );
  cfg_msguaddr_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_msguaddr(27)
    );
  cfg_msguaddr_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_msguaddr(28)
    );
  cfg_msguaddr_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_msguaddr(29)
    );
  cfg_msguaddr_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_msguaddr(30)
    );
  cfg_msguaddr_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msguaddr_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_msguaddr(31)
    );
  cfg_msgctrl_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgctrl_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_msgctrl(0)
    );
  cfg_msgctrl_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgctrl_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_msgctrl(4)
    );
  cfg_msgctrl_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgctrl_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_msgctrl(5)
    );
  cfg_msgctrl_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgctrl_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_msgctrl(6)
    );
  cfg_msgctrl_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgctrl_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_msgctrl(7)
    );
  cfg_msgladdr_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_msgladdr(2)
    );
  cfg_msgladdr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_msgladdr(3)
    );
  cfg_msgladdr_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_msgladdr(4)
    );
  cfg_msgladdr_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_msgladdr(5)
    );
  cfg_msgladdr_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_msgladdr(6)
    );
  cfg_msgladdr_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_msgladdr(7)
    );
  cfg_msgladdr_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_msgladdr(8)
    );
  cfg_msgladdr_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_msgladdr(9)
    );
  cfg_msgladdr_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_msgladdr(10)
    );
  cfg_msgladdr_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_msgladdr(11)
    );
  cfg_msgladdr_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_msgladdr(12)
    );
  cfg_msgladdr_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_msgladdr(13)
    );
  cfg_msgladdr_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_msgladdr(14)
    );
  cfg_msgladdr_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_msgladdr(15)
    );
  cfg_msgladdr_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_msgladdr(16)
    );
  cfg_msgladdr_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_msgladdr(17)
    );
  cfg_msgladdr_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_msgladdr(18)
    );
  cfg_msgladdr_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_msgladdr(19)
    );
  cfg_msgladdr_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_msgladdr(20)
    );
  cfg_msgladdr_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_msgladdr(21)
    );
  cfg_msgladdr_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_msgladdr(22)
    );
  cfg_msgladdr_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_msgladdr(23)
    );
  cfg_msgladdr_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_msgladdr(24)
    );
  cfg_msgladdr_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_msgladdr(25)
    );
  cfg_msgladdr_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_msgladdr(26)
    );
  cfg_msgladdr_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_msgladdr(27)
    );
  cfg_msgladdr_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_msgladdr(28)
    );
  cfg_msgladdr_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_msgladdr(29)
    );
  cfg_msgladdr_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_msgladdr(30)
    );
  cfg_msgladdr_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgladdr_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_msgladdr(31)
    );
  cfg_msgdata_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_msgdata(0)
    );
  cfg_msgdata_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_msgdata(1)
    );
  cfg_msgdata_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_msgdata(2)
    );
  cfg_msgdata_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_msgdata(3)
    );
  cfg_msgdata_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_msgdata(4)
    );
  cfg_msgdata_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_msgdata(5)
    );
  cfg_msgdata_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_msgdata(6)
    );
  cfg_msgdata_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_msgdata(7)
    );
  cfg_msgdata_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_msgdata(8)
    );
  cfg_msgdata_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_msgdata(9)
    );
  cfg_msgdata_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_msgdata(10)
    );
  cfg_msgdata_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_msgdata(11)
    );
  cfg_msgdata_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_msgdata(12)
    );
  cfg_msgdata_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_msgdata(13)
    );
  cfg_msgdata_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_msgdata(14)
    );
  cfg_msgdata_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_msgdata_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_msgdata(15)
    );
  cfg_rx_bar0_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_rx_bar0(0)
    );
  cfg_rx_bar0_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_rx_bar0(1)
    );
  cfg_rx_bar0_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_rx_bar0(2)
    );
  cfg_rx_bar0_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_rx_bar0(4)
    );
  cfg_rx_bar0_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_rx_bar0(5)
    );
  cfg_rx_bar0_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_rx_bar0(6)
    );
  cfg_rx_bar0_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_rx_bar0(7)
    );
  cfg_rx_bar0_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_rx_bar0(8)
    );
  cfg_rx_bar0_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_rx_bar0(9)
    );
  cfg_rx_bar0_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_rx_bar0(10)
    );
  cfg_rx_bar0_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_rx_bar0(11)
    );
  cfg_rx_bar0_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_rx_bar0(12)
    );
  cfg_rx_bar0_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_rx_bar0(13)
    );
  cfg_rx_bar0_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_rx_bar0(14)
    );
  cfg_rx_bar0_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_rx_bar0(15)
    );
  cfg_rx_bar0_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_rx_bar0(16)
    );
  cfg_rx_bar0_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_rx_bar0(17)
    );
  cfg_rx_bar0_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_rx_bar0(18)
    );
  cfg_rx_bar0_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_rx_bar0(19)
    );
  cfg_rx_bar0_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_rx_bar0(20)
    );
  cfg_rx_bar0_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_rx_bar0(21)
    );
  cfg_rx_bar0_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_rx_bar0(22)
    );
  cfg_rx_bar0_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_rx_bar0(23)
    );
  cfg_rx_bar0_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_rx_bar0(24)
    );
  cfg_rx_bar0_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_rx_bar0(25)
    );
  cfg_rx_bar0_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_rx_bar0(26)
    );
  cfg_rx_bar0_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_rx_bar0(27)
    );
  cfg_rx_bar0_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_rx_bar0(28)
    );
  cfg_rx_bar0_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_rx_bar0(29)
    );
  cfg_rx_bar0_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_rx_bar0(30)
    );
  cfg_rx_bar0_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar0_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_rx_bar0(31)
    );
  cfg_rx_bar1_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_rx_bar1(0)
    );
  cfg_rx_bar1_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_rx_bar1(1)
    );
  cfg_rx_bar1_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_rx_bar1(2)
    );
  cfg_rx_bar1_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_rx_bar1(3)
    );
  cfg_rx_bar1_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_rx_bar1(4)
    );
  cfg_rx_bar1_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_rx_bar1(5)
    );
  cfg_rx_bar1_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_rx_bar1(6)
    );
  cfg_rx_bar1_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_rx_bar1(7)
    );
  cfg_rx_bar1_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_rx_bar1(8)
    );
  cfg_rx_bar1_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_rx_bar1(9)
    );
  cfg_rx_bar1_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_rx_bar1(10)
    );
  cfg_rx_bar1_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_rx_bar1(11)
    );
  cfg_rx_bar1_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_rx_bar1(12)
    );
  cfg_rx_bar1_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_rx_bar1(13)
    );
  cfg_rx_bar1_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_rx_bar1(14)
    );
  cfg_rx_bar1_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_rx_bar1(15)
    );
  cfg_rx_bar1_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_rx_bar1(16)
    );
  cfg_rx_bar1_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_rx_bar1(17)
    );
  cfg_rx_bar1_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_rx_bar1(18)
    );
  cfg_rx_bar1_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_rx_bar1(19)
    );
  cfg_rx_bar1_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_rx_bar1(20)
    );
  cfg_rx_bar1_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_rx_bar1(21)
    );
  cfg_rx_bar1_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_rx_bar1(22)
    );
  cfg_rx_bar1_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_rx_bar1(23)
    );
  cfg_rx_bar1_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_rx_bar1(24)
    );
  cfg_rx_bar1_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_rx_bar1(25)
    );
  cfg_rx_bar1_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_rx_bar1(26)
    );
  cfg_rx_bar1_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_rx_bar1(27)
    );
  cfg_rx_bar1_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_rx_bar1(28)
    );
  cfg_rx_bar1_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_rx_bar1(29)
    );
  cfg_rx_bar1_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_rx_bar1(30)
    );
  cfg_rx_bar1_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar1_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_rx_bar1(31)
    );
  cfg_rx_bar2_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_rx_bar2(0)
    );
  cfg_rx_bar2_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(1),
      R => rst_n_inv,
      Q => cfg_rx_bar2(1)
    );
  cfg_rx_bar2_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(2),
      R => rst_n_inv,
      Q => cfg_rx_bar2(2)
    );
  cfg_rx_bar2_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(3),
      R => rst_n_inv,
      Q => cfg_rx_bar2(3)
    );
  cfg_rx_bar2_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(4),
      R => rst_n_inv,
      Q => cfg_rx_bar2(4)
    );
  cfg_rx_bar2_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(5),
      R => rst_n_inv,
      Q => cfg_rx_bar2(5)
    );
  cfg_rx_bar2_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(6),
      R => rst_n_inv,
      Q => cfg_rx_bar2(6)
    );
  cfg_rx_bar2_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(7),
      R => rst_n_inv,
      Q => cfg_rx_bar2(7)
    );
  cfg_rx_bar2_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(8),
      R => rst_n_inv,
      Q => cfg_rx_bar2(8)
    );
  cfg_rx_bar2_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(9),
      R => rst_n_inv,
      Q => cfg_rx_bar2(9)
    );
  cfg_rx_bar2_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(10),
      R => rst_n_inv,
      Q => cfg_rx_bar2(10)
    );
  cfg_rx_bar2_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_rx_bar2(11)
    );
  cfg_rx_bar2_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_rx_bar2(12)
    );
  cfg_rx_bar2_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_rx_bar2(13)
    );
  cfg_rx_bar2_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_rx_bar2(14)
    );
  cfg_rx_bar2_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_rx_bar2(15)
    );
  cfg_rx_bar2_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_rx_bar2(16)
    );
  cfg_rx_bar2_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_rx_bar2(17)
    );
  cfg_rx_bar2_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_rx_bar2(18)
    );
  cfg_rx_bar2_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_rx_bar2(19)
    );
  cfg_rx_bar2_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_rx_bar2(20)
    );
  cfg_rx_bar2_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_rx_bar2(21)
    );
  cfg_rx_bar2_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_rx_bar2(22)
    );
  cfg_rx_bar2_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_rx_bar2(23)
    );
  cfg_rx_bar2_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_rx_bar2(24)
    );
  cfg_rx_bar2_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_rx_bar2(25)
    );
  cfg_rx_bar2_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_rx_bar2(26)
    );
  cfg_rx_bar2_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_rx_bar2(27)
    );
  cfg_rx_bar2_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_rx_bar2(28)
    );
  cfg_rx_bar2_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_rx_bar2(29)
    );
  cfg_rx_bar2_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_rx_bar2(30)
    );
  cfg_rx_bar2_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_bar2_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_rx_bar2(31)
    );
  cfg_rx_xrom_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(0),
      R => rst_n_inv,
      Q => cfg_rx_xrom(0)
    );
  cfg_rx_xrom_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(11),
      R => rst_n_inv,
      Q => cfg_rx_xrom(11)
    );
  cfg_rx_xrom_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(12),
      R => rst_n_inv,
      Q => cfg_rx_xrom(12)
    );
  cfg_rx_xrom_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(13),
      R => rst_n_inv,
      Q => cfg_rx_xrom(13)
    );
  cfg_rx_xrom_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(14),
      R => rst_n_inv,
      Q => cfg_rx_xrom(14)
    );
  cfg_rx_xrom_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(15),
      R => rst_n_inv,
      Q => cfg_rx_xrom(15)
    );
  cfg_rx_xrom_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(16),
      R => rst_n_inv,
      Q => cfg_rx_xrom(16)
    );
  cfg_rx_xrom_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(17),
      R => rst_n_inv,
      Q => cfg_rx_xrom(17)
    );
  cfg_rx_xrom_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(18),
      R => rst_n_inv,
      Q => cfg_rx_xrom(18)
    );
  cfg_rx_xrom_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(19),
      R => rst_n_inv,
      Q => cfg_rx_xrom(19)
    );
  cfg_rx_xrom_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(20),
      R => rst_n_inv,
      Q => cfg_rx_xrom(20)
    );
  cfg_rx_xrom_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(21),
      R => rst_n_inv,
      Q => cfg_rx_xrom(21)
    );
  cfg_rx_xrom_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(22),
      R => rst_n_inv,
      Q => cfg_rx_xrom(22)
    );
  cfg_rx_xrom_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(23),
      R => rst_n_inv,
      Q => cfg_rx_xrom(23)
    );
  cfg_rx_xrom_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(24),
      R => rst_n_inv,
      Q => cfg_rx_xrom(24)
    );
  cfg_rx_xrom_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(25),
      R => rst_n_inv,
      Q => cfg_rx_xrom(25)
    );
  cfg_rx_xrom_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(26),
      R => rst_n_inv,
      Q => cfg_rx_xrom(26)
    );
  cfg_rx_xrom_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(27),
      R => rst_n_inv,
      Q => cfg_rx_xrom(27)
    );
  cfg_rx_xrom_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(28),
      R => rst_n_inv,
      Q => cfg_rx_xrom(28)
    );
  cfg_rx_xrom_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(29),
      R => rst_n_inv,
      Q => cfg_rx_xrom(29)
    );
  cfg_rx_xrom_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(30),
      R => rst_n_inv,
      Q => cfg_rx_xrom(30)
    );
  cfg_rx_xrom_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_rx_xrom_not0001,
      D => mgmt_rdata_d1(31),
      R => rst_n_inv,
      Q => cfg_rx_xrom(31)
    );
  detected_h68read_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => detected_h68read_19542,
      R => rst_n_inv,
      Q => detected_h68read_d_19544
    );
  detected_h48read_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => detected_h48read_19539,
      R => rst_n_inv,
      Q => detected_h48read_d_19541
    );
  wait_stg2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => wait_stg1_19744,
      R => rst_n_inv,
      Q => wait_stg2_19745
    );
  poll_dwaddr_cntr_d2_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_dwaddr_cntr_d1(0),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d2(0)
    );
  poll_dwaddr_cntr_d2_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_dwaddr_cntr_d1(1),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d2(1)
    );
  poll_dwaddr_cntr_d2_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_dwaddr_cntr_d1(2),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d2(2)
    );
  poll_dwaddr_cntr_d2_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_dwaddr_cntr_d1(3),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d2(3)
    );
  poll_dwaddr_cntr_d2_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => poll_dwaddr_cntr_d1(4),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr_d2(4)
    );
  poll_dwaddr_cntr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => Result(0),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr(0)
    );
  poll_dwaddr_cntr_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => Result(1),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr(1)
    );
  poll_dwaddr_cntr_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => Result(2),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr(2)
    );
  poll_dwaddr_cntr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => Result(3),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr(3)
    );
  poll_dwaddr_cntr_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poll_dwaddr_cntr_not0001,
      D => Result(4),
      R => rst_n_inv,
      Q => poll_dwaddr_cntr(4)
    );
  lut_dwaddr_rom6 : LUT5
    generic map(
      INIT => X"0000C003"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(6)
    );
  lut_dwaddr_rom5 : LUT5
    generic map(
      INIT => X"000F2C00"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(5)
    );
  lut_dwaddr_rom4 : LUT5
    generic map(
      INIT => X"00001000"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(4)
    );
  lut_dwaddr_rom3 : LUT5
    generic map(
      INIT => X"0000BF82"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(3)
    );
  lut_dwaddr_rom2 : LUT5
    generic map(
      INIT => X"000C5A79"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(2)
    );
  lut_dwaddr_rom1 : LUT5
    generic map(
      INIT => X"00035461"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(1)
    );
  lut_dwaddr_rom0 : LUT5
    generic map(
      INIT => X"000A6155"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwaddrx(0)
    );
  lut_dwrw_rom : LUT5
    generic map(
      INIT => X"0000C000"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(1),
      I2 => poll_dwaddr_cntr(2),
      I3 => poll_dwaddr_cntr(3),
      I4 => poll_dwaddr_cntr(4),
      O => poll_dwrw
    );
  lut_cfgdw_rom6 : LUT5
    generic map(
      INIT => X"E0000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom6_O_UNCONNECTED
    );
  lut_cfgdw_rom5 : LUT5
    generic map(
      INIT => X"1FFC0000"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom5_O_UNCONNECTED
    );
  lut_cfgdw_rom4 : LUT5
    generic map(
      INIT => X"00030000"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom4_O_UNCONNECTED
    );
  lut_cfgdw_rom3 : LUT5
    generic map(
      INIT => X"3F03FF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom3_O_UNCONNECTED
    );
  lut_cfgdw_rom2 : LUT5
    generic map(
      INIT => X"D0F3F0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom2_O_UNCONNECTED
    );
  lut_cfgdw_rom1 : LUT5
    generic map(
      INIT => X"CCCE0CCC"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom1_O_UNCONNECTED
    );
  lut_cfgdw_rom0 : LUT5
    generic map(
      INIT => X"4AA9EAAA"
    )
    port map (
      I0 => NlwRenamedSig_OI_mgmt_wdata(0),
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      I2 => NlwRenamedSig_OI_mgmt_wdata(0),
      I3 => NlwRenamedSig_OI_mgmt_wdata(0),
      I4 => NlwRenamedSig_OI_mgmt_wdata(0),
      O => NLW_lut_cfgdw_rom0_O_UNCONNECTED
    );
  poll_data_en1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => wait_stg2_19745,
      I1 => poll_en_19741,
      O => poll_data_en
    );
  mgmt_wdata_mux0000_19_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => fabric_ur_error_detected_19548,
      O => mgmt_wdata_mux0000_19_Q
    );
  mgmt_wdata_mux0000_16_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => fabric_co_error_detected_19546,
      O => mgmt_wdata_mux0000_16_Q
    );
  mgmt_bwren_mux0000_1_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => msi_ctrl_cfg_access_wr_reg_19712,
      I1 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_bwren_mux0000(1)
    );
  Mcount_poll_dwaddr_cntr_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => poll_dwaddr_cntr(1),
      I1 => poll_dwaddr_cntr(0),
      O => Result(1)
    );
  Mcount_poll_dwaddr_cntr_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(2),
      I2 => poll_dwaddr_cntr(1),
      O => Result(2)
    );
  Mcount_poll_dwaddr_cntr_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(3),
      I2 => poll_dwaddr_cntr(1),
      I3 => poll_dwaddr_cntr(2),
      O => Result(3)
    );
  Mcount_poll_dwaddr_cntr_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => poll_dwaddr_cntr(0),
      I1 => poll_dwaddr_cntr(4),
      I2 => poll_dwaddr_cntr(1),
      I3 => poll_dwaddr_cntr(2),
      I4 => poll_dwaddr_cntr(3),
      O => Result(4)
    );
  mgmt_addr_or00001 : LUT4
    generic map(
      INIT => X"FFAB"
    )
    port map (
      I0 => msi_ctrl_cfg_access_wr_reg_19712,
      I1 => NlwRenamedSig_OI_mgmt_rden,
      I2 => wait_stg1_19744,
      I3 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_addr_or0000
    );
  fabric_co_error_detect1 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => l0_rx_mac_link_error_d(1),
      I1 => l0_dll_error_vector_d(3),
      I2 => l0_dll_error_vector_d(2),
      I3 => l0_dll_error_vector_d(1),
      I4 => l0_dll_error_vector_d(0),
      O => fabric_co_error_detect
    );
  cfg_status_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(1),
      I1 => poll_data_en_d_19716,
      I2 => poll_dwaddr_cntr_d2(0),
      I3 => poll_dwaddr_cntr_d2(3),
      I4 => poll_dwaddr_cntr_d2(4),
      I5 => poll_dwaddr_cntr_d2(2),
      O => cfg_status_not0001
    );
  cfg_rx_xrom_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(3),
      I1 => poll_dwaddr_cntr_d2(0),
      I2 => poll_dwaddr_cntr_d2(1),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(4),
      I5 => poll_dwaddr_cntr_d2(2),
      O => cfg_rx_xrom_not0001
    );
  cfg_rx_bar2_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(2),
      I1 => poll_dwaddr_cntr_d2(0),
      I2 => poll_dwaddr_cntr_d2(1),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(3),
      I5 => poll_dwaddr_cntr_d2(4),
      O => cfg_rx_bar2_not0001
    );
  cfg_rx_bar1_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => poll_data_en_d_19716,
      I1 => poll_dwaddr_cntr_d2(2),
      I2 => poll_dwaddr_cntr_d2(0),
      I3 => poll_dwaddr_cntr_d2(1),
      I4 => poll_dwaddr_cntr_d2(3),
      I5 => poll_dwaddr_cntr_d2(4),
      O => cfg_rx_bar1_not0001
    );
  cfg_rx_bar0_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(1),
      I1 => poll_dwaddr_cntr_d2(0),
      I2 => poll_dwaddr_cntr_d2(3),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(4),
      I5 => poll_dwaddr_cntr_d2(2),
      O => cfg_rx_bar0_not0001
    );
  cfg_pmcsr_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(2),
      I1 => poll_dwaddr_cntr_d2(3),
      I2 => poll_dwaddr_cntr_d2(1),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(0),
      I5 => poll_dwaddr_cntr_d2(4),
      O => cfg_pmcsr_not0001
    );
  cfg_msguaddr_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_data_en_d_19716,
      I1 => poll_dwaddr_cntr_d2(1),
      I2 => poll_dwaddr_cntr_d2(0),
      I3 => poll_dwaddr_cntr_d2(4),
      I4 => poll_dwaddr_cntr_d2(2),
      I5 => poll_dwaddr_cntr_d2(3),
      O => cfg_msguaddr_not0001
    );
  cfg_msgladdr_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_data_en_d_19716,
      I1 => poll_dwaddr_cntr_d2(0),
      I2 => poll_dwaddr_cntr_d2(1),
      I3 => poll_dwaddr_cntr_d2(4),
      I4 => poll_dwaddr_cntr_d2(2),
      I5 => poll_dwaddr_cntr_d2(3),
      O => cfg_msgladdr_not0001
    );
  cfg_msgdata_not00011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(0),
      I1 => poll_dwaddr_cntr_d2(1),
      I2 => poll_data_en_d_19716,
      I3 => poll_dwaddr_cntr_d2(4),
      I4 => poll_dwaddr_cntr_d2(2),
      I5 => poll_dwaddr_cntr_d2(3),
      O => cfg_msgdata_not0001
    );
  cfg_msgctrl_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => poll_data_en_d_19716,
      I1 => poll_dwaddr_cntr_d2(4),
      I2 => poll_dwaddr_cntr_d2(0),
      I3 => poll_dwaddr_cntr_d2(1),
      I4 => poll_dwaddr_cntr_d2(2),
      I5 => poll_dwaddr_cntr_d2(3),
      O => cfg_msgctrl_not0001
    );
  cfg_lstatus_not00011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(0),
      I1 => poll_dwaddr_cntr_d2(1),
      I2 => poll_dwaddr_cntr_d2(3),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(4),
      I5 => poll_dwaddr_cntr_d2(2),
      O => cfg_lstatus_not0001
    );
  cfg_dstatus_not00011 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(3),
      I1 => poll_dwaddr_cntr_d2(1),
      I2 => poll_dwaddr_cntr_d2(0),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(4),
      I5 => poll_dwaddr_cntr_d2(2),
      O => cfg_dstatus_not0001
    );
  cfg_dcap_not00011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => poll_dwaddr_cntr_d2(0),
      I1 => poll_dwaddr_cntr_d2(2),
      I2 => poll_dwaddr_cntr_d2(3),
      I3 => poll_data_en_d_19716,
      I4 => poll_dwaddr_cntr_d2(1),
      I5 => poll_dwaddr_cntr_d2(4),
      O => cfg_dcap_not0001
    );
  fabric_ur_error_detected_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => mgmt_pso_ur_fell_d_19628,
      O => fabric_ur_error_detected_or0000
    );
  fabric_co_error_detected_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => mgmt_pso_co_fell_d_19625,
      O => fabric_co_error_detected_or0000
    );
  mgmt_wdata_mux0000_21_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => mgmt_pso(6),
      O => mgmt_wdata_mux0000_21_Q
    );
  mgmt_wdata_mux0000_18_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => mgmt_pso(8),
      O => mgmt_wdata_mux0000_18_Q
    );
  mgmt_pso_co_fell_d_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => mgmt_pso(10),
      I1 => mgmt_pso_co_d_19624,
      O => mgmt_pso_co_fell_d_and0000
    );
  mgmt_wdata_mux0000_17_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => mgmt_pso(9),
      O => mgmt_wdata_mux0000_17_Q
    );
  mgmt_pso_ur_fell_d_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => mgmt_pso(7),
      I1 => mgmt_pso_ur_d_19627,
      O => mgmt_pso_ur_fell_d_and0000
    );
  mgmt_addr_mux0000_9_1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => msi_ctrl_cfg_access_wr_reg_19712,
      I1 => poll_dwaddrx(1),
      I2 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_addr_mux0000(9)
    );
  mgmt_addr_mux0000_7_1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => msi_ctrl_cfg_access_wr_reg_19712,
      I2 => poll_dwaddrx(3),
      O => mgmt_addr_mux0000(7)
    );
  mgmt_addr_mux0000_5_1 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => msi_ctrl_cfg_access_wr_reg_19712,
      I1 => poll_dwaddrx(5),
      I2 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_addr_mux0000(5)
    );
  msi_ctrl_cfg_access_wr_reg_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => detected_h48read_d_19541,
      I1 => l0_stats_cfg_received,
      O => msi_ctrl_cfg_access_wr_reg_and0000
    );
  falseur_cfg_access_wr_reg_and00001 : LUT4
    generic map(
      INIT => X"A080"
    )
    port map (
      I0 => l0_stats_cfg_received,
      I1 => mgmt_pso_co_d_19624,
      I2 => detected_h68read_d_19544,
      I3 => mgmt_pso_ur_d_19627,
      O => falseur_cfg_access_wr_reg_and0000
    );
  falseur_cfg_access_wr_reg_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => l0_stats_cfg_transmitted,
      O => falseur_cfg_access_wr_reg_or0000
    );
  mgmt_wren_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => msi_ctrl_cfg_access_wr_reg_19712,
      I1 => poll_dwrw,
      I2 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_wren_or0000
    );
  mgmt_rden_or00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => wait_stg1_19744,
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      I3 => NlwRenamedSig_OI_mgmt_rden,
      I4 => rst_n,
      I5 => poll_dwrw,
      O => mgmt_rden_or0000
    );
  mgmt_addr_mux0000_10_11 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => msi_ctrl_cfg_access_wr_reg_19712,
      O => N4
    );
  detected_h68read_and00001 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => llk_rx_data_d(37),
      I1 => llk_rx_data_d(38),
      I2 => llk_rx_data_d(35),
      I3 => llk_rx_data_d(32),
      I4 => N0,
      I5 => detected_cfg_read1cycle_19530,
      O => detected_h68read_and0000
    );
  detected_h48read_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => N0,
      I1 => detected_cfg_read1cycle_19530,
      I2 => llk_rx_data_d(35),
      I3 => llk_rx_data_d(38),
      I4 => llk_rx_data_d(37),
      I5 => llk_rx_data_d(32),
      O => detected_h48read_and0000
    );
  detected_cfg_read1cycle_cmp_eq0000135 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_rx_data_d(43),
      I1 => llk_rx_data_d(41),
      I2 => llk_rx_data_d(45),
      I3 => llk_rx_data_d(44),
      I4 => llk_rx_data_d(46),
      I5 => llk_rx_data_d(47),
      O => detected_cfg_read1cycle_cmp_eq0000135_19533
    );
  detected_cfg_read1cycle_cmp_eq0000171 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_rx_data_d(34),
      I1 => llk_rx_data_d(33),
      I2 => llk_rx_data_d(36),
      I3 => llk_rx_data_d(39),
      I4 => llk_rx_data_d(40),
      I5 => llk_rx_data_d(42),
      O => detected_cfg_read1cycle_cmp_eq0000171_19535
    );
  detected_cfg_read1cycle_cmp_eq0000172 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => detected_cfg_read1cycle_cmp_eq0000135_19533,
      I1 => detected_cfg_read1cycle_cmp_eq0000171_19535,
      O => N0
    );
  detected_cfg_read1cycle_cmp_eq000028 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => llk_rx_data_d(32),
      I1 => llk_rx_data_d(58),
      I2 => llk_rx_data_d(37),
      I3 => llk_rx_data_d(35),
      I4 => llk_rx_data_d(52),
      I5 => llk_rx_data_d(51),
      O => detected_cfg_read1cycle_cmp_eq000028_19536
    );
  detected_cfg_read1cycle_cmp_eq000064 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_rx_data_d(49),
      I1 => llk_rx_data_d(50),
      I2 => llk_rx_data_d(48),
      I3 => llk_rx_data_d(38),
      I4 => llk_rx_data_d(59),
      I5 => llk_rx_data_d(57),
      O => detected_cfg_read1cycle_cmp_eq000064_19537
    );
  detected_cfg_read1cycle_cmp_eq00001201 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_rx_data_d(55),
      I1 => llk_rx_data_d(56),
      I2 => llk_rx_data_d(54),
      I3 => llk_rx_data_d(53),
      I4 => llk_rx_data_d(63),
      I5 => llk_rx_data_d(62),
      O => detected_cfg_read1cycle_cmp_eq00001201_19532
    );
  mgmt_addr_mux0000_8_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => poll_dwaddrx(2),
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      O => mgmt_addr_mux0000(8)
    );
  mgmt_addr_mux0000_6_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => poll_dwaddrx(4),
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      O => mgmt_addr_mux0000(6)
    );
  mgmt_addr_mux0000_4_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => poll_dwaddrx(6),
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      O => mgmt_addr_mux0000(4)
    );
  mgmt_addr_mux0000_10_2 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => poll_dwaddrx(0),
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      O => mgmt_addr_mux0000(10)
    );
  poll_dwaddr_cntr_not00011 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => falseur_cfg_access_wr_reg_19550,
      I1 => msi_ctrl_cfg_access_wr_reg_19712,
      I2 => NlwRenamedSig_OI_mgmt_rden,
      I3 => wait_stg1_19744,
      O => poll_dwaddr_cntr_not0001
    );
  mgmt_wren_or00011 : LUT5
    generic map(
      INIT => X"57575755"
    )
    port map (
      I0 => rst_n,
      I1 => msi_ctrl_cfg_access_wr_reg_19712,
      I2 => falseur_cfg_access_wr_reg_19550,
      I3 => NlwRenamedSig_OI_mgmt_rden,
      I4 => wait_stg1_19744,
      O => mgmt_wren_not0001_inv
    );
  detected_cfg_read1cycle_or0000_inv1 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => llk_rx_data_d(35),
      I1 => llk_rx_data_d(38),
      I2 => detected_cfg_read1cycle_cmp_eq0000135_19533,
      I3 => llk_rx_data_d(32),
      I4 => detected_cfg_read1cycle_cmp_eq0000171_19535,
      O => detected_cfg_read1cycle_or0000_inv
    );
  mgmt_wdata_and00001 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => poll_dwrw,
      I1 => falseur_cfg_access_wr_reg_19550,
      I2 => msi_ctrl_cfg_access_wr_reg_19712,
      O => mgmt_wdata_and0000
    );
  mgmt_wdata_not00011 : LUT5
    generic map(
      INIT => X"FFFFFF02"
    )
    port map (
      I0 => poll_dwrw,
      I1 => wait_stg1_19744,
      I2 => NlwRenamedSig_OI_mgmt_rden,
      I3 => msi_ctrl_cfg_access_wr_reg_19712,
      I4 => falseur_cfg_access_wr_reg_19550,
      O => mgmt_wdata_not0001
    );
  Mcount_poll_dwaddr_cntr_xor_0_11_INV_0 : INV
    port map (
      I => poll_dwaddr_cntr(0),
      O => Result(0)
    );
  msi_ctrl_cfg_access_wr_reg_inv1_INV_0 : INV
    port map (
      I => msi_ctrl_cfg_access_wr_reg_19712,
      O => msi_ctrl_cfg_access_wr_reg_inv
    );
  falseur_cfg_access_wr_reg_inv1_INV_0 : INV
    port map (
      I => falseur_cfg_access_wr_reg_19550,
      O => falseur_cfg_access_wr_reg_inv
    );
  rst_n_inv781_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  detected_cfg_read1cycle_cmp_eq000015611 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => detected_cfg_read1cycle_cmp_eq000064_19537,
      I1 => detected_cfg_read1cycle_cmp_eq0000171_19535,
      I2 => detected_cfg_read1cycle_cmp_eq000028_19536,
      I3 => llk_rx_data_d(60),
      I4 => detected_cfg_read1cycle_cmp_eq00001201_19532,
      I5 => detected_cfg_read1cycle_cmp_eq0000135_19533,
      O => detected_cfg_read1cycle_cmp_eq00001561
    );
  detected_cfg_read1cycle_cmp_eq00001561_f7 : MUXF7
    port map (
      I0 => detected_cfg_read1cycle_cmp_eq00001561,
      I1 => NlwRenamedSig_OI_mgmt_wdata(0),
      S => llk_rx_data_d(61),
      O => detected_cfg_read1cycle_cmp_eq0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_cf_pwr is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_to_turnoff_n : out STD_LOGIC; 
    send_pmeack : out STD_LOGIC; 
    l0_pwr_turn_off_req : in STD_LOGIC := 'X'; 
    l0_pme_req_in : out STD_LOGIC; 
    l0_pme_ack : in STD_LOGIC := 'X'; 
    cfg_pm_wake_n : in STD_LOGIC := 'X'; 
    cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
    cs_is_pm : in STD_LOGIC := 'X'; 
    grant : in STD_LOGIC := 'X' 
  );
end pcie_blk_cf_pwr;

architecture STRUCTURE of pcie_blk_cf_pwr is
  signal NlwRenamedSignal_l0_pme_req_in : STD_LOGIC; 
begin
  send_pmeack <= NlwRenamedSignal_l0_pme_req_in;
  l0_pme_req_in <= NlwRenamedSignal_l0_pme_req_in;
  XST_GND : GND
    port map (
      G => NlwRenamedSignal_l0_pme_req_in
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_cf_arb is
  port (
    clk : in STD_LOGIC := 'X'; 
    cs_is_nfl : out STD_LOGIC; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_arb_teof_n : out STD_LOGIC; 
    intr_req_valid : in STD_LOGIC := 'X'; 
    send_ftl : in STD_LOGIC := 'X'; 
    cfg_arb_tsrc_rdy_n : out STD_LOGIC; 
    send_pmeack : in STD_LOGIC := 'X'; 
    send_cplt : in STD_LOGIC := 'X'; 
    send_cplu : in STD_LOGIC := 'X'; 
    cs_is_ftl : out STD_LOGIC; 
    cfg_arb_tsof_n : out STD_LOGIC; 
    cs_is_intr : out STD_LOGIC; 
    send_cor : in STD_LOGIC := 'X'; 
    cs_is_pm : out STD_LOGIC; 
    cs_is_cplt : out STD_LOGIC; 
    cs_is_cplu : out STD_LOGIC; 
    cs_is_cor : out STD_LOGIC; 
    grant : out STD_LOGIC; 
    cfg_arb_tdst_rdy_n : in STD_LOGIC := 'X'; 
    send_nfl : in STD_LOGIC := 'X'; 
    cfg_arb_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    request_data : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
    cfg_arb_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
    msi_data : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    intr_vector : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    msi_laddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    msi_haddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_rd_hdr : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
    cmt_rd_hdr : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
    cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    intr_req_type : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end pcie_blk_cf_arb;

architecture STRUCTURE of pcie_blk_cf_arb is
  signal Mcount_wait_cntr_val : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N110 : STD_LOGIC; 
  signal N112 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal N118 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N122 : STD_LOGIC; 
  signal N123 : STD_LOGIC; 
  signal N124 : STD_LOGIC; 
  signal N125 : STD_LOGIC; 
  signal N126 : STD_LOGIC; 
  signal N127 : STD_LOGIC; 
  signal N128 : STD_LOGIC; 
  signal N129 : STD_LOGIC; 
  signal N130 : STD_LOGIC; 
  signal N131 : STD_LOGIC; 
  signal N132 : STD_LOGIC; 
  signal N133 : STD_LOGIC; 
  signal N134 : STD_LOGIC; 
  signal N135 : STD_LOGIC; 
  signal N136 : STD_LOGIC; 
  signal N137 : STD_LOGIC; 
  signal N138 : STD_LOGIC; 
  signal N139 : STD_LOGIC; 
  signal N140 : STD_LOGIC; 
  signal N141 : STD_LOGIC; 
  signal N142 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal N48 : STD_LOGIC; 
  signal N50 : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal N60 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal N64 : STD_LOGIC; 
  signal N66 : STD_LOGIC; 
  signal N68 : STD_LOGIC; 
  signal N70 : STD_LOGIC; 
  signal N72 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal N76 : STD_LOGIC; 
  signal N78 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal N82 : STD_LOGIC; 
  signal N84 : STD_LOGIC; 
  signal N86 : STD_LOGIC; 
  signal N88 : STD_LOGIC; 
  signal N90 : STD_LOGIC; 
  signal N92 : STD_LOGIC; 
  signal N94 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal Q_mux0006 : STD_LOGIC; 
  signal Q_mux0007 : STD_LOGIC; 
  signal byte_00_mux0000_3_1_18688 : STD_LOGIC; 
  signal byte_00_or0000_18693 : STD_LOGIC; 
  signal byte_06_0_Q : STD_LOGIC; 
  signal byte_06_1_Q : STD_LOGIC; 
  signal byte_06_2_Q : STD_LOGIC; 
  signal byte_06_3_Q : STD_LOGIC; 
  signal byte_06_5_Q : STD_LOGIC; 
  signal byte_06_7_Q : STD_LOGIC; 
  signal byte_06_mux0000_0_Q : STD_LOGIC; 
  signal byte_06_mux0000_1_Q : STD_LOGIC; 
  signal byte_06_mux0000_2_Q : STD_LOGIC; 
  signal byte_06_mux0000_3_Q : STD_LOGIC; 
  signal byte_06_mux0000_5_Q : STD_LOGIC; 
  signal byte_06_mux0000_7_Q : STD_LOGIC; 
  signal byte_07_mux0000_29_23_18753 : STD_LOGIC; 
  signal byte_07_mux0000_30_13 : STD_LOGIC; 
  signal byte_07_mux0000_30_131_18756 : STD_LOGIC; 
  signal cfg_arb_td_0_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_10_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_11_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_12_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_13_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_14_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_15_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_16_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_17_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_18_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_19_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_1_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_20_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_21_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_22_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_23_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_24_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_25_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_26_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_27_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_28_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_29_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_2_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_30_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_31_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_32_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_33_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_34_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_35_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_36_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_37_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_38_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_39_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_3_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_40_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_41_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_42_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_43_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_44_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_45_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_46_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_47_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_48_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_49_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_4_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_50_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_51_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_52_mux0000_18983 : STD_LOGIC; 
  signal cfg_arb_td_53_mux0000_18985 : STD_LOGIC; 
  signal cfg_arb_td_54_mux0000_18987 : STD_LOGIC; 
  signal cfg_arb_td_55_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_56_mux0000_18991 : STD_LOGIC; 
  signal cfg_arb_td_57_mux0000_18993 : STD_LOGIC; 
  signal cfg_arb_td_58_mux0000_18995 : STD_LOGIC; 
  signal cfg_arb_td_59_mux0000_18997 : STD_LOGIC; 
  signal cfg_arb_td_5_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_60_mux0000_19001 : STD_LOGIC; 
  signal cfg_arb_td_61_mux0000_19003 : STD_LOGIC; 
  signal cfg_arb_td_62_mux0000_19005 : STD_LOGIC; 
  signal cfg_arb_td_63_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_63_or0000 : STD_LOGIC; 
  signal cfg_arb_td_6_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_7_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_8_mux0000 : STD_LOGIC; 
  signal cfg_arb_td_9_mux0000 : STD_LOGIC; 
  signal cfg_arb_teof_n_mux0000 : STD_LOGIC; 
  signal cfg_arb_teof_n_mux00001_19019 : STD_LOGIC; 
  signal cfg_arb_tsof_n_mux0000_19023 : STD_LOGIC; 
  signal cfg_arb_tsrc_rdy_n_mux0000 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd1_19140 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd10_19141 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd10_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd11_19143 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd11_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd12_19145 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd12_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd13_19147 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd13_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd14_19149 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd14_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd2_19151 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd3_19152 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd3_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd4_19154 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd4_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd5_19156 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd5_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd6_19158 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd6_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd7_19160 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd7_In : STD_LOGIC; 
  signal cs_fsm_FSM_FFd9_19162 : STD_LOGIC; 
  signal cs_fsm_FSM_FFd9_In : STD_LOGIC; 
  signal cs_fsm_FSM_N1 : STD_LOGIC; 
  signal cs_fsm_FSM_N2 : STD_LOGIC; 
  signal cs_fsm_FSM_Scst_FSM_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_grant : STD_LOGIC; 
  signal grant_mux0000 : STD_LOGIC; 
  signal reg_req_pkt_tx_19256 : STD_LOGIC; 
  signal state_FSM_FFd1_19265 : STD_LOGIC; 
  signal state_FSM_FFd1_In : STD_LOGIC; 
  signal state_FSM_FFd2_19267 : STD_LOGIC; 
  signal state_FSM_FFd2_In : STD_LOGIC; 
  signal state_FSM_FFd3_19269 : STD_LOGIC; 
  signal state_FSM_FFd3_In : STD_LOGIC; 
  signal state_FSM_FFd4_19271 : STD_LOGIC; 
  signal wait_cntr_cst : STD_LOGIC; 
  signal wait_cntr_or0000 : STD_LOGIC; 
  signal Result : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal byte_00 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal byte_00_mux0000 : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal byte_01 : STD_LOGIC_VECTOR ( 6 downto 4 ); 
  signal byte_01_mux0000 : STD_LOGIC_VECTOR ( 6 downto 4 ); 
  signal byte_02 : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal byte_02_mux0000 : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal byte_03 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal byte_03_mux0000 : STD_LOGIC_VECTOR ( 7 downto 7 ); 
  signal byte_04 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_04_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_05 : STD_LOGIC_VECTOR ( 7 downto 3 ); 
  signal byte_05_mux0000 : STD_LOGIC_VECTOR ( 7 downto 3 ); 
  signal byte_07 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_07_mux0000 : STD_LOGIC_VECTOR ( 36 downto 29 ); 
  signal byte_08 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_08_mux0000 : STD_LOGIC_VECTOR ( 23 downto 16 ); 
  signal byte_09 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_09_mux0000 : STD_LOGIC_VECTOR ( 15 downto 8 ); 
  signal byte_10 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_10_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_11 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal byte_11_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal bytes_12_to_15 : STD_LOGIC_VECTOR ( 31 downto 2 ); 
  signal bytes_12_to_15_mux0000 : STD_LOGIC_VECTOR ( 29 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_arb_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_arb_trem_n : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal cfg_arb_trem_n_mux0000 : STD_LOGIC_VECTOR ( 7 downto 7 ); 
  signal request_data_mux0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal wait_cntr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  grant <= NlwRenamedSig_OI_grant;
  cfg_arb_td(63) <= NlwRenamedSig_OI_cfg_arb_td(63);
  cfg_arb_td(62) <= NlwRenamedSig_OI_cfg_arb_td(62);
  cfg_arb_td(61) <= NlwRenamedSig_OI_cfg_arb_td(61);
  cfg_arb_td(60) <= NlwRenamedSig_OI_cfg_arb_td(60);
  cfg_arb_td(59) <= NlwRenamedSig_OI_cfg_arb_td(59);
  cfg_arb_td(58) <= NlwRenamedSig_OI_cfg_arb_td(58);
  cfg_arb_td(57) <= NlwRenamedSig_OI_cfg_arb_td(57);
  cfg_arb_td(56) <= NlwRenamedSig_OI_cfg_arb_td(56);
  cfg_arb_td(55) <= NlwRenamedSig_OI_cfg_arb_td(55);
  cfg_arb_td(54) <= NlwRenamedSig_OI_cfg_arb_td(54);
  cfg_arb_td(53) <= NlwRenamedSig_OI_cfg_arb_td(53);
  cfg_arb_td(52) <= NlwRenamedSig_OI_cfg_arb_td(52);
  cfg_arb_td(51) <= NlwRenamedSig_OI_cfg_arb_td(51);
  cfg_arb_td(50) <= NlwRenamedSig_OI_cfg_arb_td(50);
  cfg_arb_td(49) <= NlwRenamedSig_OI_cfg_arb_td(49);
  cfg_arb_td(48) <= NlwRenamedSig_OI_cfg_arb_td(48);
  cfg_arb_td(47) <= NlwRenamedSig_OI_cfg_arb_td(47);
  cfg_arb_td(46) <= NlwRenamedSig_OI_cfg_arb_td(46);
  cfg_arb_td(45) <= NlwRenamedSig_OI_cfg_arb_td(45);
  cfg_arb_td(44) <= NlwRenamedSig_OI_cfg_arb_td(44);
  cfg_arb_td(43) <= NlwRenamedSig_OI_cfg_arb_td(43);
  cfg_arb_td(42) <= NlwRenamedSig_OI_cfg_arb_td(42);
  cfg_arb_td(41) <= NlwRenamedSig_OI_cfg_arb_td(41);
  cfg_arb_td(40) <= NlwRenamedSig_OI_cfg_arb_td(40);
  cfg_arb_td(39) <= NlwRenamedSig_OI_cfg_arb_td(39);
  cfg_arb_td(38) <= NlwRenamedSig_OI_cfg_arb_td(38);
  cfg_arb_td(37) <= NlwRenamedSig_OI_cfg_arb_td(37);
  cfg_arb_td(36) <= NlwRenamedSig_OI_cfg_arb_td(36);
  cfg_arb_td(35) <= NlwRenamedSig_OI_cfg_arb_td(35);
  cfg_arb_td(34) <= NlwRenamedSig_OI_cfg_arb_td(34);
  cfg_arb_td(33) <= NlwRenamedSig_OI_cfg_arb_td(33);
  cfg_arb_td(32) <= NlwRenamedSig_OI_cfg_arb_td(32);
  cfg_arb_td(31) <= NlwRenamedSig_OI_cfg_arb_td(31);
  cfg_arb_td(30) <= NlwRenamedSig_OI_cfg_arb_td(30);
  cfg_arb_td(29) <= NlwRenamedSig_OI_cfg_arb_td(29);
  cfg_arb_td(28) <= NlwRenamedSig_OI_cfg_arb_td(28);
  cfg_arb_td(27) <= NlwRenamedSig_OI_cfg_arb_td(27);
  cfg_arb_td(26) <= NlwRenamedSig_OI_cfg_arb_td(26);
  cfg_arb_td(25) <= NlwRenamedSig_OI_cfg_arb_td(25);
  cfg_arb_td(24) <= NlwRenamedSig_OI_cfg_arb_td(24);
  cfg_arb_td(23) <= NlwRenamedSig_OI_cfg_arb_td(23);
  cfg_arb_td(22) <= NlwRenamedSig_OI_cfg_arb_td(22);
  cfg_arb_td(21) <= NlwRenamedSig_OI_cfg_arb_td(21);
  cfg_arb_td(20) <= NlwRenamedSig_OI_cfg_arb_td(20);
  cfg_arb_td(19) <= NlwRenamedSig_OI_cfg_arb_td(19);
  cfg_arb_td(18) <= NlwRenamedSig_OI_cfg_arb_td(18);
  cfg_arb_td(17) <= NlwRenamedSig_OI_cfg_arb_td(17);
  cfg_arb_td(16) <= NlwRenamedSig_OI_cfg_arb_td(16);
  cfg_arb_td(15) <= NlwRenamedSig_OI_cfg_arb_td(15);
  cfg_arb_td(14) <= NlwRenamedSig_OI_cfg_arb_td(14);
  cfg_arb_td(13) <= NlwRenamedSig_OI_cfg_arb_td(13);
  cfg_arb_td(12) <= NlwRenamedSig_OI_cfg_arb_td(12);
  cfg_arb_td(11) <= NlwRenamedSig_OI_cfg_arb_td(11);
  cfg_arb_td(10) <= NlwRenamedSig_OI_cfg_arb_td(10);
  cfg_arb_td(9) <= NlwRenamedSig_OI_cfg_arb_td(9);
  cfg_arb_td(8) <= NlwRenamedSig_OI_cfg_arb_td(8);
  cfg_arb_td(7) <= NlwRenamedSig_OI_cfg_arb_td(7);
  cfg_arb_td(6) <= NlwRenamedSig_OI_cfg_arb_td(6);
  cfg_arb_td(5) <= NlwRenamedSig_OI_cfg_arb_td(5);
  cfg_arb_td(4) <= NlwRenamedSig_OI_cfg_arb_td(4);
  cfg_arb_td(3) <= NlwRenamedSig_OI_cfg_arb_td(3);
  cfg_arb_td(2) <= NlwRenamedSig_OI_cfg_arb_td(2);
  cfg_arb_td(1) <= NlwRenamedSig_OI_cfg_arb_td(1);
  cfg_arb_td(0) <= NlwRenamedSig_OI_cfg_arb_td(0);
  cfg_arb_trem_n(0) <= NlwRenamedSig_OI_cfg_arb_trem_n(0);
  request_data_48 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => request_data_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => request_data(48)
    );
  byte_01_4 : FDR
    port map (
      C => clk,
      D => byte_01_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_01(4)
    );
  byte_01_5 : FDR
    port map (
      C => clk,
      D => byte_01_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_01(5)
    );
  byte_01_6 : FDR
    port map (
      C => clk,
      D => byte_01_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_01(6)
    );
  byte_00_0 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(0)
    );
  byte_00_1 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(1)
    );
  byte_00_2 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(2)
    );
  byte_00_3 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(3)
    );
  byte_00_4 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(4)
    );
  byte_00_5 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(2),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(5)
    );
  byte_00_6 : FDR
    port map (
      C => clk,
      D => byte_00_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_00(6)
    );
  byte_04_0 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(0),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(0)
    );
  byte_04_1 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(1)
    );
  byte_04_2 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(2),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(2)
    );
  byte_04_3 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(3)
    );
  byte_04_4 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(4)
    );
  byte_04_5 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(5)
    );
  byte_04_6 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(6)
    );
  byte_04_7 : FDR
    port map (
      C => clk,
      D => byte_04_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_04(7)
    );
  byte_02_4 : FDR
    port map (
      C => clk,
      D => byte_02_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_02(4)
    );
  byte_02_5 : FDR
    port map (
      C => clk,
      D => byte_02_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_02(5)
    );
  byte_03_0 : FDR
    port map (
      C => clk,
      D => byte_03_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_03(0)
    );
  byte_07_0 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(29),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(0)
    );
  byte_07_1 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(30),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(1)
    );
  byte_07_2 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(31),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(2)
    );
  byte_07_3 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(32),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(3)
    );
  byte_07_4 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(33),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(4)
    );
  byte_07_5 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(34),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(5)
    );
  byte_07_6 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(35),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(6)
    );
  byte_07_7 : FDR
    port map (
      C => clk,
      D => byte_07_mux0000(36),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_07(7)
    );
  byte_05_3 : FDR
    port map (
      C => clk,
      D => byte_05_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_05(3)
    );
  byte_05_4 : FDR
    port map (
      C => clk,
      D => byte_05_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_05(4)
    );
  byte_05_5 : FDR
    port map (
      C => clk,
      D => byte_05_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_05(5)
    );
  byte_05_6 : FDR
    port map (
      C => clk,
      D => byte_05_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_05(6)
    );
  byte_05_7 : FDR
    port map (
      C => clk,
      D => byte_05_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_05(7)
    );
  byte_06_0 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_0_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_0_Q
    );
  byte_06_1 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_1_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_1_Q
    );
  byte_06_2 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_2_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_2_Q
    );
  byte_06_3 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_3_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_3_Q
    );
  byte_06_5 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_5_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_5_Q
    );
  byte_06_7 : FDR
    port map (
      C => clk,
      D => byte_06_mux0000_7_Q,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_06_7_Q
    );
  byte_10_0 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(0),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(0)
    );
  byte_10_1 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(1)
    );
  byte_10_2 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(2),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(2)
    );
  byte_10_3 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(3)
    );
  byte_10_4 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(4)
    );
  byte_10_5 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(5)
    );
  byte_10_6 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(6)
    );
  byte_10_7 : FDR
    port map (
      C => clk,
      D => byte_10_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_10(7)
    );
  byte_08_0 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(16),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(0)
    );
  byte_08_1 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(17),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(1)
    );
  byte_08_2 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(18),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(2)
    );
  byte_08_3 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(19),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(3)
    );
  byte_08_4 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(20),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(4)
    );
  byte_08_5 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(21),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(5)
    );
  byte_08_6 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(22),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(6)
    );
  byte_08_7 : FDR
    port map (
      C => clk,
      D => byte_08_mux0000(23),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_08(7)
    );
  byte_09_0 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(8),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(0)
    );
  byte_09_1 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(9),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(1)
    );
  byte_09_2 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(10),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(2)
    );
  byte_09_3 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(11),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(3)
    );
  byte_09_4 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(12),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(4)
    );
  byte_09_5 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(13),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(5)
    );
  byte_09_6 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(14),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(6)
    );
  byte_09_7 : FDR
    port map (
      C => clk,
      D => byte_09_mux0000(15),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_09(7)
    );
  byte_11_0 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(0),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(0)
    );
  byte_11_1 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(1)
    );
  byte_11_2 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(2),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(2)
    );
  byte_11_3 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(3)
    );
  byte_11_4 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(4)
    );
  byte_11_5 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(5)
    );
  byte_11_6 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(6)
    );
  byte_11_7 : FDR
    port map (
      C => clk,
      D => byte_11_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => byte_11(7)
    );
  bytes_12_to_15_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(29),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(2)
    );
  bytes_12_to_15_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(28),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(3)
    );
  bytes_12_to_15_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(27),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(4)
    );
  bytes_12_to_15_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(26),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(5)
    );
  bytes_12_to_15_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(25),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(6)
    );
  bytes_12_to_15_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(24),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(7)
    );
  bytes_12_to_15_8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(23),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(8)
    );
  bytes_12_to_15_9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(22),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(9)
    );
  bytes_12_to_15_10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(21),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(10)
    );
  bytes_12_to_15_11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(20),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(11)
    );
  bytes_12_to_15_12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(19),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(12)
    );
  bytes_12_to_15_13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(18),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(13)
    );
  bytes_12_to_15_14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(17),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(14)
    );
  bytes_12_to_15_15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(16),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(15)
    );
  bytes_12_to_15_16 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(15),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(16)
    );
  bytes_12_to_15_17 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(14),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(17)
    );
  bytes_12_to_15_18 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(13),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(18)
    );
  bytes_12_to_15_19 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(12),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(19)
    );
  bytes_12_to_15_20 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(11),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(20)
    );
  bytes_12_to_15_21 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(10),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(21)
    );
  bytes_12_to_15_22 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(9),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(22)
    );
  bytes_12_to_15_23 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(8),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(23)
    );
  bytes_12_to_15_24 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(7),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(24)
    );
  bytes_12_to_15_25 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(6),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(25)
    );
  bytes_12_to_15_26 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(5),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(26)
    );
  bytes_12_to_15_27 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(4),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(27)
    );
  bytes_12_to_15_28 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(3),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(28)
    );
  bytes_12_to_15_29 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(2),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(29)
    );
  bytes_12_to_15_30 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(30)
    );
  bytes_12_to_15_31 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bytes_12_to_15_mux0000(0),
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => bytes_12_to_15(31)
    );
  cfg_arb_td_63 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_63_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(63)
    );
  cfg_arb_tsof_n_10263 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_arb_tsof_n_mux0000_19023,
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => cfg_arb_tsof_n
    );
  cfg_arb_teof_n_10264 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_arb_teof_n_mux0000,
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => cfg_arb_teof_n
    );
  cfg_arb_td_60 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_60_mux0000_19001,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(60)
    );
  cfg_arb_td_62 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_62_mux0000_19005,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(62)
    );
  cfg_arb_td_61 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_61_mux0000_19003,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(61)
    );
  cfg_arb_td_57 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_57_mux0000_18993,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(57)
    );
  cfg_arb_td_59 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_59_mux0000_18997,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(59)
    );
  cfg_arb_td_58 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_58_mux0000_18995,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(58)
    );
  cfg_arb_td_54 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_54_mux0000_18987,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(54)
    );
  cfg_arb_td_56 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_56_mux0000_18991,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(56)
    );
  cfg_arb_td_55 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_55_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(55)
    );
  cfg_arb_td_51 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_51_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(51)
    );
  cfg_arb_td_53 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_53_mux0000_18985,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(53)
    );
  cfg_arb_td_52 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_52_mux0000_18983,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(52)
    );
  cfg_arb_td_48 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_48_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(48)
    );
  cfg_arb_td_50 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_50_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(50)
    );
  cfg_arb_td_49 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_49_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(49)
    );
  cfg_arb_td_45 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_45_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(45)
    );
  cfg_arb_td_47 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_47_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(47)
    );
  cfg_arb_td_46 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_46_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(46)
    );
  cfg_arb_td_44 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_44_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(44)
    );
  cfg_arb_td_43 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_43_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(43)
    );
  cfg_arb_td_40 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_40_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(40)
    );
  cfg_arb_td_42 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_42_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(42)
    );
  cfg_arb_td_41 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_41_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(41)
    );
  cfg_arb_td_37 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_37_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(37)
    );
  cfg_arb_td_39 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_39_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(39)
    );
  cfg_arb_td_38 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_38_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(38)
    );
  cfg_arb_td_34 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_34_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(34)
    );
  cfg_arb_td_36 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_36_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(36)
    );
  cfg_arb_td_35 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_35_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(35)
    );
  cfg_arb_td_31 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_31_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(31)
    );
  cfg_arb_td_33 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_33_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(33)
    );
  cfg_arb_td_32 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_32_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(32)
    );
  cfg_arb_td_28 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_28_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(28)
    );
  cfg_arb_td_30 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_30_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(30)
    );
  cfg_arb_td_29 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_29_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(29)
    );
  cfg_arb_td_25 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_25_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(25)
    );
  cfg_arb_td_27 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_27_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(27)
    );
  cfg_arb_td_26 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_26_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(26)
    );
  cfg_arb_td_22 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_22_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(22)
    );
  cfg_arb_td_24 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_24_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(24)
    );
  cfg_arb_td_23 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_23_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(23)
    );
  cfg_arb_td_19 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_19_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(19)
    );
  cfg_arb_td_21 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_21_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(21)
    );
  cfg_arb_td_20 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_20_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(20)
    );
  cfg_arb_td_16 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_16_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(16)
    );
  cfg_arb_td_18 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_18_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(18)
    );
  cfg_arb_td_17 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_17_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(17)
    );
  cfg_arb_td_13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_13_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(13)
    );
  cfg_arb_td_15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_15_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(15)
    );
  cfg_arb_td_14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_14_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(14)
    );
  cfg_arb_td_10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_10_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(10)
    );
  cfg_arb_td_12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_12_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(12)
    );
  cfg_arb_td_11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_11_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(11)
    );
  cfg_arb_td_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_7_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(7)
    );
  cfg_arb_td_9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_9_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(9)
    );
  cfg_arb_td_8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_8_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(8)
    );
  cfg_arb_td_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_4_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(4)
    );
  cfg_arb_td_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_6_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(6)
    );
  cfg_arb_td_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_5_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(5)
    );
  cfg_arb_td_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_1_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(1)
    );
  cfg_arb_td_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_3_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(3)
    );
  cfg_arb_td_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_2_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(2)
    );
  cfg_arb_tsrc_rdy_n_10327 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_arb_tsrc_rdy_n_mux0000,
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => cfg_arb_tsrc_rdy_n
    );
  cfg_arb_td_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cfg_arb_td_0_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_td(0)
    );
  cfg_arb_trem_n_0 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_arb_trem_n_mux0000(7),
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_cfg_arb_trem_n(0)
    );
  grant_10330 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => grant_mux0000,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => NlwRenamedSig_OI_grant
    );
  cs_is_cor_10331 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd9_19162,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_cor
    );
  cs_is_cplu_10332 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd13_19147,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_cplu
    );
  cs_is_cplt_10333 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd12_19145,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_cplt
    );
  cs_is_nfl_10334 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd10_19141,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_nfl
    );
  cs_is_ftl_10335 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd11_19143,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_ftl
    );
  cs_is_intr_10336 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => Q_mux0006,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_is_intr
    );
  reg_req_pkt_tx : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => Q_mux0007,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => reg_req_pkt_tx_19256
    );
  wait_cntr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_cntr_or0000,
      D => Result(0),
      R => Mcount_wait_cntr_val,
      Q => wait_cntr(0)
    );
  wait_cntr_1 : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => wait_cntr_or0000,
      D => Result(1),
      R => cs_fsm_FSM_Scst_FSM_inv,
      S => wait_cntr_cst,
      Q => wait_cntr(1)
    );
  state_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => state_FSM_FFd1_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => state_FSM_FFd1_19265
    );
  state_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => state_FSM_FFd2_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => state_FSM_FFd2_19267
    );
  state_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => state_FSM_FFd3_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => state_FSM_FFd3_19269
    );
  state_FSM_FFd4 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => cfg_arb_tsrc_rdy_n_mux0000,
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => state_FSM_FFd4_19271
    );
  cs_fsm_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd3_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd3_19152
    );
  cs_fsm_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd4_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd4_19154
    );
  cs_fsm_FSM_FFd7 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd7_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd7_19160
    );
  cs_fsm_FSM_FFd5 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd5_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd5_19156
    );
  cs_fsm_FSM_FFd6 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd6_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd6_19158
    );
  cs_fsm_FSM_FFd9 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd9_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd9_19162
    );
  cs_fsm_FSM_FFd10 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd10_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd10_19141
    );
  cs_fsm_FSM_FFd11 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd11_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd11_19143
    );
  cs_fsm_FSM_FFd14 : FDS
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd14_In,
      S => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd14_19149
    );
  cs_fsm_FSM_FFd12 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd12_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd12_19145
    );
  cs_fsm_FSM_FFd13 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd13_In,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd13_19147
    );
  cs_fsm_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd3_19152,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd2_19151
    );
  cs_fsm_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => cs_fsm_FSM_FFd2_19151,
      R => cs_fsm_FSM_Scst_FSM_inv,
      Q => cs_fsm_FSM_FFd1_19140
    );
  Mcount_wait_cntr_xor_1_11 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => wait_cntr(0),
      I1 => wait_cntr(1),
      O => Result(1)
    );
  request_data_mux0000_1_1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(48),
      I2 => cs_fsm_FSM_FFd12_19145,
      I3 => cmt_rd_hdr(48),
      O => request_data_mux0000(1)
    );
  cs_fsm_FSM_Out141 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => cs_fsm_FSM_FFd7_19160,
      I2 => cs_fsm_FSM_FFd6_19158,
      I3 => cs_fsm_FSM_FFd5_19156,
      O => Q_mux0006
    );
  cs_fsm_FSM_FFd13_In1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => send_cplu,
      I1 => cs_fsm_FSM_FFd14_19149,
      I2 => NlwRenamedSig_OI_grant,
      I3 => cs_fsm_FSM_FFd13_19147,
      O => cs_fsm_FSM_FFd13_In
    );
  cs_fsm_FSM_FFd12_In1 : LUT5
    generic map(
      INIT => X"4444F444"
    )
    port map (
      I0 => NlwRenamedSig_OI_grant,
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cs_fsm_FSM_FFd14_19149,
      I3 => send_cplt,
      I4 => send_cplu,
      O => cs_fsm_FSM_FFd12_In
    );
  state_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"EAAA4000"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => byte_00(5),
      I2 => byte_00(6),
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd2_19267,
      O => state_FSM_FFd2_In
    );
  cfg_arb_trem_n_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FFFFFFFF040404AE"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => NlwRenamedSig_OI_cfg_arb_trem_n(0),
      I2 => state_FSM_FFd4_19271,
      I3 => byte_00(5),
      I4 => byte_00(6),
      I5 => state_FSM_FFd2_19267,
      O => cfg_arb_trem_n_mux0000(7)
    );
  grant_mux00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd1_19265,
      O => grant_mux0000
    );
  cfg_arb_td_52_mux000031 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd2_19267,
      O => N2
    );
  cs_fsm_FSM_FFd9_In11 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => cs_fsm_FSM_FFd14_19149,
      I1 => send_cplt,
      I2 => send_cplu,
      O => cs_fsm_FSM_N2
    );
  cfg_arb_td_63_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => state_FSM_FFd2_19267,
      I1 => state_FSM_FFd4_19271,
      I2 => state_FSM_FFd3_19269,
      O => cfg_arb_td_63_or0000
    );
  cfg_arb_td_52_mux000021 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      O => N11
    );
  cfg_arb_td_52_mux000011 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd2_19267,
      O => N0
    );
  cs_fsm_FSM_FFd3_In11 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => cs_fsm_FSM_FFd14_19149,
      I1 => cs_fsm_FSM_FFd1_19140,
      I2 => cs_fsm_FSM_FFd2_19151,
      I3 => cs_fsm_FSM_FFd3_19152,
      O => Q_mux0007
    );
  cs_fsm_FSM_FFd10_In1 : LUT5
    generic map(
      INIT => X"4444F444"
    )
    port map (
      I0 => NlwRenamedSig_OI_grant,
      I1 => cs_fsm_FSM_FFd10_19141,
      I2 => cs_fsm_FSM_N2,
      I3 => send_nfl,
      I4 => send_ftl,
      O => cs_fsm_FSM_FFd10_In
    );
  cs_fsm_FSM_FFd9_In1 : LUT6
    generic map(
      INIT => X"1000FFFF10001000"
    )
    port map (
      I0 => send_nfl,
      I1 => send_ftl,
      I2 => cs_fsm_FSM_N2,
      I3 => send_cor,
      I4 => NlwRenamedSig_OI_grant,
      I5 => cs_fsm_FSM_FFd9_19162,
      O => cs_fsm_FSM_FFd9_In
    );
  cfg_arb_td_9_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_1_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(9),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(9),
      I5 => N0,
      O => cfg_arb_td_9_mux0000
    );
  cfg_arb_td_8_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_0_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(8),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(8),
      I5 => N0,
      O => cfg_arb_td_8_mux0000
    );
  cfg_arb_td_7_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(7),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(7),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(7),
      I5 => N0,
      O => cfg_arb_td_7_mux0000
    );
  cfg_arb_td_6_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(6),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(6),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(6),
      I5 => N0,
      O => cfg_arb_td_6_mux0000
    );
  cfg_arb_td_63_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_08(7),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(63),
      I3 => cfg_arb_td_63_or0000,
      I4 => intr_vector(7),
      I5 => N2,
      O => cfg_arb_td_63_mux0000
    );
  cfg_arb_td_5_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(5),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(5),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(5),
      I5 => N0,
      O => cfg_arb_td_5_mux0000
    );
  cfg_arb_td_55_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_09(7),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(55),
      I3 => cfg_arb_td_63_or0000,
      I4 => msi_data(15),
      I5 => N2,
      O => cfg_arb_td_55_mux0000
    );
  cfg_arb_td_51_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_09(3),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(51),
      I3 => cfg_arb_td_63_or0000,
      I4 => msi_data(11),
      I5 => N2,
      O => cfg_arb_td_51_mux0000
    );
  cfg_arb_td_50_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_09(2),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(50),
      I3 => cfg_arb_td_63_or0000,
      I4 => msi_data(10),
      I5 => N2,
      O => cfg_arb_td_50_mux0000
    );
  cfg_arb_td_4_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(4),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(4),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(4),
      I5 => N0,
      O => cfg_arb_td_4_mux0000
    );
  cfg_arb_td_49_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_09(1),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(49),
      I3 => cfg_arb_td_63_or0000,
      I4 => msi_data(9),
      I5 => N2,
      O => cfg_arb_td_49_mux0000
    );
  cfg_arb_td_48_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_09(0),
      I1 => N0,
      I2 => NlwRenamedSig_OI_cfg_arb_td(48),
      I3 => cfg_arb_td_63_or0000,
      I4 => msi_data(8),
      I5 => N2,
      O => cfg_arb_td_48_mux0000
    );
  cfg_arb_td_45_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_02(5),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(45),
      I3 => cfg_arb_td_63_or0000,
      I4 => byte_10(5),
      I5 => N0,
      O => cfg_arb_td_45_mux0000
    );
  cfg_arb_td_44_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_02(4),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(44),
      I3 => cfg_arb_td_63_or0000,
      I4 => byte_10(4),
      I5 => N0,
      O => cfg_arb_td_44_mux0000
    );
  cfg_arb_td_3_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(3),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(3),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(3),
      I5 => N0,
      O => cfg_arb_td_3_mux0000
    );
  cfg_arb_td_32_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_03(0),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(32),
      I3 => cfg_arb_td_63_or0000,
      I4 => byte_11(0),
      I5 => N0,
      O => cfg_arb_td_32_mux0000
    );
  cfg_arb_td_31_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(7),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(31),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(31),
      I5 => N0,
      O => cfg_arb_td_31_mux0000
    );
  cfg_arb_td_30_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(6),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(30),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(30),
      I5 => N0,
      O => cfg_arb_td_30_mux0000
    );
  cfg_arb_td_2_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_07(2),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(2),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(2),
      I5 => N0,
      O => cfg_arb_td_2_mux0000
    );
  cfg_arb_td_29_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(5),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(29),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(29),
      I5 => N0,
      O => cfg_arb_td_29_mux0000
    );
  cfg_arb_td_28_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(4),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(28),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(28),
      I5 => N0,
      O => cfg_arb_td_28_mux0000
    );
  cfg_arb_td_27_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(3),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(27),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(27),
      I5 => N0,
      O => cfg_arb_td_27_mux0000
    );
  cfg_arb_td_26_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(2),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(26),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(26),
      I5 => N0,
      O => cfg_arb_td_26_mux0000
    );
  cfg_arb_td_25_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(1),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(25),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(25),
      I5 => N0,
      O => cfg_arb_td_25_mux0000
    );
  cfg_arb_td_24_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_04(0),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(24),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(24),
      I5 => N0,
      O => cfg_arb_td_24_mux0000
    );
  cfg_arb_td_23_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_05(7),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(23),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(23),
      I5 => N0,
      O => cfg_arb_td_23_mux0000
    );
  cfg_arb_td_22_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_05(6),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(22),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(22),
      I5 => N0,
      O => cfg_arb_td_22_mux0000
    );
  cfg_arb_td_21_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_05(5),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(21),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(21),
      I5 => N0,
      O => cfg_arb_td_21_mux0000
    );
  cfg_arb_td_20_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_05(4),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(20),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(20),
      I5 => N0,
      O => cfg_arb_td_20_mux0000
    );
  cfg_arb_td_19_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_05(3),
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(19),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(19),
      I5 => N0,
      O => cfg_arb_td_19_mux0000
    );
  cfg_arb_td_15_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_7_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(15),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(15),
      I5 => N0,
      O => cfg_arb_td_15_mux0000
    );
  cfg_arb_td_13_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_5_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(13),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(13),
      I5 => N0,
      O => cfg_arb_td_13_mux0000
    );
  cfg_arb_td_11_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_3_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(11),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(11),
      I5 => N0,
      O => cfg_arb_td_11_mux0000
    );
  cfg_arb_td_10_mux00001 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => byte_06_2_Q,
      I1 => N11,
      I2 => NlwRenamedSig_OI_cfg_arb_td(10),
      I3 => cfg_arb_td_63_or0000,
      I4 => bytes_12_to_15(10),
      I5 => N0,
      O => cfg_arb_td_10_mux0000
    );
  wait_cntr_cst1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => rst_n,
      I1 => state_FSM_FFd1_19265,
      O => wait_cntr_cst
    );
  Mcount_wait_cntr_val1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => state_FSM_FFd1_19265,
      O => Mcount_wait_cntr_val
    );
  wait_cntr_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => wait_cntr(1),
      I1 => wait_cntr(0),
      O => wait_cntr_or0000
    );
  cfg_arb_tsof_n_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFF8F8FFF8"
    )
    port map (
      I0 => state_FSM_FFd4_19271,
      I1 => N21,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => cfg_arb_tdst_rdy_n,
      I5 => state_FSM_FFd1_19265,
      O => cfg_arb_tsof_n_mux0000_19023
    );
  cs_fsm_FSM_FFd14_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => cs_fsm_FSM_FFd1_19140,
      I1 => intr_req_valid,
      I2 => cs_fsm_FSM_N1,
      O => cs_fsm_FSM_FFd14_In
    );
  byte_05_mux0000_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_05(7),
      I2 => cfg_device_number(4),
      O => byte_05_mux0000(7)
    );
  byte_05_mux0000_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_05(6),
      I2 => cfg_device_number(3),
      O => byte_05_mux0000(6)
    );
  byte_05_mux0000_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_05(5),
      I2 => cfg_device_number(2),
      O => byte_05_mux0000(5)
    );
  byte_05_mux0000_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_05(4),
      I2 => cfg_device_number(1),
      O => byte_05_mux0000(4)
    );
  byte_05_mux0000_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_05(3),
      I2 => cfg_device_number(0),
      O => byte_05_mux0000(3)
    );
  byte_04_mux0000_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(7),
      I2 => cfg_bus_number(7),
      O => byte_04_mux0000(7)
    );
  byte_04_mux0000_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(6),
      I2 => cfg_bus_number(6),
      O => byte_04_mux0000(6)
    );
  byte_04_mux0000_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(5),
      I2 => cfg_bus_number(5),
      O => byte_04_mux0000(5)
    );
  byte_04_mux0000_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(4),
      I2 => cfg_bus_number(4),
      O => byte_04_mux0000(4)
    );
  byte_04_mux0000_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(3),
      I2 => cfg_bus_number(3),
      O => byte_04_mux0000(3)
    );
  byte_04_mux0000_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(2),
      I2 => cfg_bus_number(2),
      O => byte_04_mux0000(2)
    );
  byte_04_mux0000_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(1),
      I2 => cfg_bus_number(1),
      O => byte_04_mux0000(1)
    );
  byte_04_mux0000_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => byte_00_or0000_18693,
      I1 => byte_04(0),
      I2 => cfg_bus_number(0),
      O => byte_04_mux0000(0)
    );
  bytes_12_to_15_mux0000_29_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(2),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(2),
      O => bytes_12_to_15_mux0000(29)
    );
  bytes_12_to_15_mux0000_28_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(3),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(3),
      O => bytes_12_to_15_mux0000(28)
    );
  bytes_12_to_15_mux0000_27_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(4),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(4),
      O => bytes_12_to_15_mux0000(27)
    );
  bytes_12_to_15_mux0000_26_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(5),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(5),
      O => bytes_12_to_15_mux0000(26)
    );
  bytes_12_to_15_mux0000_25_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(6),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(6),
      O => bytes_12_to_15_mux0000(25)
    );
  bytes_12_to_15_mux0000_24_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(7),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(7),
      O => bytes_12_to_15_mux0000(24)
    );
  bytes_12_to_15_mux0000_23_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(8),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(8),
      O => bytes_12_to_15_mux0000(23)
    );
  bytes_12_to_15_mux0000_22_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(9),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(9),
      O => bytes_12_to_15_mux0000(22)
    );
  bytes_12_to_15_mux0000_21_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(10),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(10),
      O => bytes_12_to_15_mux0000(21)
    );
  bytes_12_to_15_mux0000_20_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(11),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(11),
      O => bytes_12_to_15_mux0000(20)
    );
  bytes_12_to_15_mux0000_19_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(12),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(12),
      O => bytes_12_to_15_mux0000(19)
    );
  bytes_12_to_15_mux0000_18_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(13),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(13),
      O => bytes_12_to_15_mux0000(18)
    );
  bytes_12_to_15_mux0000_17_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(14),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(14),
      O => bytes_12_to_15_mux0000(17)
    );
  bytes_12_to_15_mux0000_16_1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => msi_laddr(15),
      I2 => byte_00_or0000_18693,
      I3 => bytes_12_to_15(15),
      O => bytes_12_to_15_mux0000(16)
    );
  byte_03_mux0000_7_1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd5_19156,
      I1 => byte_03(0),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd4_19154,
      O => byte_03_mux0000(7)
    );
  byte_00_mux0000_6_1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => byte_00(1),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd12_19145,
      O => byte_00_mux0000(6)
    );
  byte_00_mux0000_5_1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd6_19158,
      I1 => byte_00(2),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd7_19160,
      O => byte_00_mux0000(5)
    );
  byte_00_mux0000_4_1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => byte_00(3),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd12_19145,
      O => byte_00_mux0000(4)
    );
  byte_00_mux0000_1_1 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd5_19156,
      I1 => byte_00(6),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd4_19154,
      O => byte_00_mux0000(1)
    );
  cs_fsm_FSM_FFd4_In11 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => cs_fsm_FSM_FFd14_19149,
      I1 => send_cplt,
      I2 => send_ftl,
      I3 => send_nfl,
      I4 => send_cor,
      I5 => send_cplu,
      O => cs_fsm_FSM_N1
    );
  bytes_12_to_15_mux0000_9_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(14),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(22),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(22),
      O => bytes_12_to_15_mux0000(9)
    );
  bytes_12_to_15_mux0000_8_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(15),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(23),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(23),
      O => bytes_12_to_15_mux0000(8)
    );
  bytes_12_to_15_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(0),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(24),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(24),
      O => bytes_12_to_15_mux0000(7)
    );
  bytes_12_to_15_mux0000_6_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(1),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(25),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(25),
      O => bytes_12_to_15_mux0000(6)
    );
  bytes_12_to_15_mux0000_5_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(2),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(26),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(26),
      O => bytes_12_to_15_mux0000(5)
    );
  bytes_12_to_15_mux0000_4_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(3),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(27),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(27),
      O => bytes_12_to_15_mux0000(4)
    );
  bytes_12_to_15_mux0000_3_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(4),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(28),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(28),
      O => bytes_12_to_15_mux0000(3)
    );
  bytes_12_to_15_mux0000_2_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(5),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(29),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(29),
      O => bytes_12_to_15_mux0000(2)
    );
  bytes_12_to_15_mux0000_1_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(6),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(30),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(30),
      O => bytes_12_to_15_mux0000(1)
    );
  bytes_12_to_15_mux0000_15_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(8),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(16),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(16),
      O => bytes_12_to_15_mux0000(15)
    );
  bytes_12_to_15_mux0000_14_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(9),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(17),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(17),
      O => bytes_12_to_15_mux0000(14)
    );
  bytes_12_to_15_mux0000_13_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(10),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(18),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(18),
      O => bytes_12_to_15_mux0000(13)
    );
  bytes_12_to_15_mux0000_12_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(11),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(19),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(19),
      O => bytes_12_to_15_mux0000(12)
    );
  bytes_12_to_15_mux0000_11_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(12),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(20),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(20),
      O => bytes_12_to_15_mux0000(11)
    );
  bytes_12_to_15_mux0000_10_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_data(13),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(21),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(21),
      O => bytes_12_to_15_mux0000(10)
    );
  bytes_12_to_15_mux0000_0_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => intr_vector(7),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => bytes_12_to_15(31),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_laddr(31),
      O => bytes_12_to_15_mux0000(0)
    );
  byte_11_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => msi_laddr(7),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => byte_11(7),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => msi_haddr(7),
      O => byte_11_mux0000(7)
    );
  byte_07_mux0000_36_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(36),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_07(7),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(36),
      O => byte_07_mux0000(36)
    );
  byte_07_mux0000_35_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(35),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_07(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(35),
      O => byte_07_mux0000(35)
    );
  byte_06_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(48),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_06_7_Q,
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(48),
      O => byte_06_mux0000_7_Q
    );
  byte_06_mux0000_5_1 : LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
    port map (
      I0 => cs_fsm_FSM_FFd12_19145,
      I1 => cmt_rd_hdr(48),
      I2 => cs_fsm_FSM_FFd13_19147,
      I3 => cfg_rd_hdr(48),
      I4 => byte_00_or0000_18693,
      I5 => byte_06_5_Q,
      O => byte_06_mux0000_5_Q
    );
  byte_06_mux0000_3_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(40),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_06_3_Q,
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(40),
      O => byte_06_mux0000_3_Q
    );
  byte_06_mux0000_2_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(39),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_06_2_Q,
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(39),
      O => byte_06_mux0000_2_Q
    );
  byte_06_mux0000_1_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(38),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_06_1_Q,
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(38),
      O => byte_06_mux0000_1_Q
    );
  byte_06_mux0000_0_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(37),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_06_0_Q,
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(37),
      O => byte_06_mux0000_0_Q
    );
  byte_02_mux0000_5_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(25),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_02(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(25),
      O => byte_02_mux0000(5)
    );
  byte_02_mux0000_4_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(24),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_02(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(24),
      O => byte_02_mux0000(4)
    );
  byte_01_mux0000_6_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(28),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_01(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(28),
      O => byte_01_mux0000(6)
    );
  byte_01_mux0000_5_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(27),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_01(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(27),
      O => byte_01_mux0000(5)
    );
  byte_01_mux0000_4_1 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cfg_rd_hdr(26),
      I1 => cs_fsm_FSM_FFd13_19147,
      I2 => byte_01(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(26),
      O => byte_01_mux0000(4)
    );
  byte_00_mux0000_7_1 : LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
    port map (
      I0 => cs_fsm_FSM_FFd12_19145,
      I1 => cmt_rd_hdr(49),
      I2 => cs_fsm_FSM_FFd13_19147,
      I3 => cfg_rd_hdr(49),
      I4 => byte_00_or0000_18693,
      I5 => byte_00(0),
      O => byte_00_mux0000(7)
    );
  byte_00_or0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cs_fsm_FSM_FFd6_19158,
      I2 => cs_fsm_FSM_FFd9_19162,
      I3 => cs_fsm_FSM_FFd11_19143,
      O => N44
    );
  byte_00_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd5_19156,
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cs_fsm_FSM_FFd4_19154,
      I3 => cs_fsm_FSM_FFd7_19160,
      I4 => cs_fsm_FSM_FFd10_19141,
      I5 => N44,
      O => byte_00_or0000_18693
    );
  byte_11_mux0000_1_SW0 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(42),
      I2 => byte_00_or0000_18693,
      I3 => byte_11(1),
      O => N48
    );
  byte_11_mux0000_1_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd12_19145,
      I1 => cmt_rd_hdr(42),
      I2 => N48,
      I3 => cs_fsm_FSM_FFd4_19154,
      I4 => msi_haddr(1),
      O => byte_11_mux0000(1)
    );
  byte_11_mux0000_0_SW0 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(41),
      I2 => byte_00_or0000_18693,
      I3 => byte_11(0),
      O => N50
    );
  byte_11_mux0000_0_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd12_19145,
      I1 => cmt_rd_hdr(41),
      I2 => N50,
      I3 => cs_fsm_FSM_FFd4_19154,
      I4 => msi_haddr(0),
      O => byte_11_mux0000(0)
    );
  byte_07_mux0000_32_SW0 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => byte_00_or0000_18693,
      I2 => byte_07(3),
      O => N52
    );
  byte_07_mux0000_32_Q : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => cmt_rd_hdr(32),
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cfg_rd_hdr(32),
      I3 => cs_fsm_FSM_FFd13_19147,
      I4 => cs_fsm_FSM_FFd5_19156,
      I5 => N52,
      O => byte_07_mux0000(32)
    );
  byte_00_mux0000_2_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd6_19158,
      I1 => cs_fsm_FSM_FFd9_19162,
      I2 => cs_fsm_FSM_FFd11_19143,
      O => N54
    );
  byte_00_mux0000_2_Q : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd10_19141,
      I1 => cs_fsm_FSM_FFd4_19154,
      I2 => byte_00(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd7_19160,
      I5 => N54,
      O => byte_00_mux0000(2)
    );
  byte_07_mux0000_33_SW0 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd9_19162,
      I1 => byte_07(4),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd11_19143,
      O => N56
    );
  byte_07_mux0000_33_Q : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => cmt_rd_hdr(33),
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cfg_rd_hdr(33),
      I3 => cs_fsm_FSM_FFd13_19147,
      I4 => cs_fsm_FSM_FFd10_19141,
      I5 => N56,
      O => byte_07_mux0000(33)
    );
  byte_07_mux0000_31_SW0 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd4_19154,
      I1 => byte_07(2),
      I2 => byte_00_or0000_18693,
      I3 => cs_fsm_FSM_FFd6_19158,
      O => N58
    );
  byte_07_mux0000_31_Q : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => cmt_rd_hdr(31),
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cfg_rd_hdr(31),
      I3 => cs_fsm_FSM_FFd13_19147,
      I4 => cs_fsm_FSM_FFd5_19156,
      I5 => N58,
      O => byte_07_mux0000(31)
    );
  byte_11_mux0000_6_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(47),
      I2 => byte_11(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(47),
      O => N60
    );
  byte_11_mux0000_6_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(6),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N60,
      I3 => msi_haddr(6),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_11_mux0000(6)
    );
  byte_11_mux0000_5_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(46),
      I2 => byte_11(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(46),
      O => N62
    );
  byte_11_mux0000_5_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(5),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N62,
      I3 => msi_haddr(5),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_11_mux0000(5)
    );
  byte_11_mux0000_4_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(45),
      I2 => byte_11(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(45),
      O => N64
    );
  byte_11_mux0000_4_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(4),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N64,
      I3 => msi_haddr(4),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_11_mux0000(4)
    );
  byte_11_mux0000_3_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(44),
      I2 => byte_11(3),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(44),
      O => N66
    );
  byte_11_mux0000_3_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(3),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N66,
      I3 => msi_haddr(3),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_11_mux0000(3)
    );
  byte_11_mux0000_2_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(43),
      I2 => byte_11(2),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(43),
      O => N68
    );
  byte_11_mux0000_2_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(2),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N68,
      I3 => msi_haddr(2),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_11_mux0000(2)
    );
  byte_10_mux0000_7_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(7),
      I2 => byte_10(7),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(7),
      O => N70
    );
  byte_10_mux0000_7_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(15),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N70,
      I3 => msi_haddr(15),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(7)
    );
  byte_10_mux0000_6_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(6),
      I2 => byte_10(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(6),
      O => N72
    );
  byte_10_mux0000_6_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(14),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N72,
      I3 => msi_haddr(14),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(6)
    );
  byte_10_mux0000_5_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(5),
      I2 => byte_10(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(5),
      O => N74
    );
  byte_10_mux0000_5_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(13),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N74,
      I3 => msi_haddr(13),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(5)
    );
  byte_10_mux0000_4_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(4),
      I2 => byte_10(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(4),
      O => N76
    );
  byte_10_mux0000_4_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(12),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N76,
      I3 => msi_haddr(12),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(4)
    );
  byte_10_mux0000_3_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(3),
      I2 => byte_10(3),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(3),
      O => N78
    );
  byte_10_mux0000_3_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(11),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N78,
      I3 => msi_haddr(11),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(3)
    );
  byte_10_mux0000_2_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(2),
      I2 => byte_10(2),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(2),
      O => N80
    );
  byte_10_mux0000_2_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(10),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N80,
      I3 => msi_haddr(10),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(2)
    );
  byte_10_mux0000_1_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(1),
      I2 => byte_10(1),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(1),
      O => N82
    );
  byte_10_mux0000_1_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(9),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N82,
      I3 => msi_haddr(9),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(1)
    );
  byte_10_mux0000_0_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(0),
      I2 => byte_10(0),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(0),
      O => N84
    );
  byte_10_mux0000_0_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(8),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N84,
      I3 => msi_haddr(8),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_10_mux0000(0)
    );
  byte_09_mux0000_9_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(9),
      I2 => byte_09(1),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(9),
      O => N86
    );
  byte_09_mux0000_9_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(17),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N86,
      I3 => msi_haddr(17),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(9)
    );
  byte_09_mux0000_8_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(8),
      I2 => byte_09(0),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(8),
      O => N88
    );
  byte_09_mux0000_8_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(16),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N88,
      I3 => msi_haddr(16),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(8)
    );
  byte_09_mux0000_15_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(15),
      I2 => byte_09(7),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(15),
      O => N90
    );
  byte_09_mux0000_15_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(23),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N90,
      I3 => msi_haddr(23),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(15)
    );
  byte_09_mux0000_14_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(14),
      I2 => byte_09(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(14),
      O => N92
    );
  byte_09_mux0000_14_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(22),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N92,
      I3 => msi_haddr(22),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(14)
    );
  byte_09_mux0000_13_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(13),
      I2 => byte_09(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(13),
      O => N94
    );
  byte_09_mux0000_13_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(21),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N94,
      I3 => msi_haddr(21),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(13)
    );
  byte_09_mux0000_12_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(12),
      I2 => byte_09(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(12),
      O => N96
    );
  byte_09_mux0000_12_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(20),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N96,
      I3 => msi_haddr(20),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(12)
    );
  byte_09_mux0000_11_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(11),
      I2 => byte_09(3),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(11),
      O => N98
    );
  byte_09_mux0000_11_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(19),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N98,
      I3 => msi_haddr(19),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(11)
    );
  byte_09_mux0000_10_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(10),
      I2 => byte_09(2),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(10),
      O => N100
    );
  byte_09_mux0000_10_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(18),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N100,
      I3 => msi_haddr(18),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_09_mux0000(10)
    );
  byte_08_mux0000_23_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(23),
      I2 => byte_08(7),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(23),
      O => N102
    );
  byte_08_mux0000_23_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(31),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N102,
      I3 => msi_haddr(31),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(23)
    );
  byte_08_mux0000_22_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(22),
      I2 => byte_08(6),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(22),
      O => N104
    );
  byte_08_mux0000_22_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(30),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N104,
      I3 => msi_haddr(30),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(22)
    );
  byte_08_mux0000_21_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(21),
      I2 => byte_08(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(21),
      O => N106
    );
  byte_08_mux0000_21_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(29),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N106,
      I3 => msi_haddr(29),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(21)
    );
  byte_08_mux0000_20_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(20),
      I2 => byte_08(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(20),
      O => N108
    );
  byte_08_mux0000_20_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(28),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N108,
      I3 => msi_haddr(28),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(20)
    );
  byte_08_mux0000_19_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(19),
      I2 => byte_08(3),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(19),
      O => N110
    );
  byte_08_mux0000_19_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(27),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N110,
      I3 => msi_haddr(27),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(19)
    );
  byte_08_mux0000_18_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(18),
      I2 => byte_08(2),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(18),
      O => N112
    );
  byte_08_mux0000_18_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(26),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N112,
      I3 => msi_haddr(26),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(18)
    );
  byte_08_mux0000_17_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(17),
      I2 => byte_08(1),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(17),
      O => N114
    );
  byte_08_mux0000_17_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(25),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N114,
      I3 => msi_haddr(25),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(17)
    );
  byte_08_mux0000_16_SW0 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd13_19147,
      I1 => cfg_rd_hdr(16),
      I2 => byte_08(0),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd12_19145,
      I5 => cmt_rd_hdr(16),
      O => N116
    );
  byte_08_mux0000_16_Q : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => msi_laddr(24),
      I1 => cs_fsm_FSM_FFd5_19156,
      I2 => N116,
      I3 => msi_haddr(24),
      I4 => cs_fsm_FSM_FFd4_19154,
      O => byte_08_mux0000(16)
    );
  byte_07_mux0000_34_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd9_19162,
      I1 => cs_fsm_FSM_FFd11_19143,
      I2 => byte_07(5),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd10_19141,
      I5 => cs_fsm_FSM_FFd6_19158,
      O => N118
    );
  byte_07_mux0000_34_Q : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => cmt_rd_hdr(34),
      I1 => cs_fsm_FSM_FFd12_19145,
      I2 => cfg_rd_hdr(34),
      I3 => cs_fsm_FSM_FFd13_19147,
      I4 => cs_fsm_FSM_FFd7_19160,
      I5 => N118,
      O => byte_07_mux0000(34)
    );
  byte_07_mux0000_29_34 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => byte_07_mux0000_29_23_18753,
      I1 => byte_00_or0000_18693,
      I2 => byte_07(0),
      O => byte_07_mux0000(29)
    );
  byte_07_mux0000_30_33 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCFC88F8"
    )
    port map (
      I0 => cs_fsm_FSM_FFd7_19160,
      I1 => intr_vector(1),
      I2 => byte_07(1),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd6_19158,
      I5 => byte_07_mux0000_30_13,
      O => byte_07_mux0000(30)
    );
  byte_07_mux0000_29_23_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd11_19143,
      I1 => cs_fsm_FSM_FFd10_19141,
      I2 => cmt_rd_hdr(29),
      I3 => cs_fsm_FSM_FFd12_19145,
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => cs_fsm_FSM_FFd5_19156,
      O => N120
    );
  byte_07_mux0000_29_23 : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => intr_vector(0),
      I1 => cs_fsm_FSM_FFd6_19158,
      I2 => N120,
      I3 => cs_fsm_FSM_FFd13_19147,
      I4 => cfg_rd_hdr(29),
      I5 => cs_fsm_FSM_FFd7_19160,
      O => byte_07_mux0000_29_23_18753
    );
  state_FSM_FFd1_In1 : LUT6
    generic map(
      INIT => X"FFFFAEEE55550444"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd3_19269,
      I2 => byte_00(5),
      I3 => byte_00(6),
      I4 => state_FSM_FFd2_19267,
      I5 => state_FSM_FFd1_19265,
      O => state_FSM_FFd1_In
    );
  cs_fsm_FSM_FFd3_In2 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => NlwRenamedSig_OI_grant,
      I1 => cs_fsm_FSM_FFd14_19149,
      I2 => cs_fsm_FSM_FFd1_19140,
      I3 => cs_fsm_FSM_FFd2_19151,
      I4 => cs_fsm_FSM_FFd3_19152,
      O => cs_fsm_FSM_FFd3_In
    );
  cs_fsm_FSM_FFd11_In1 : LUT6
    generic map(
      INIT => X"1000FFFF10001000"
    )
    port map (
      I0 => send_cplt,
      I1 => send_cplu,
      I2 => send_ftl,
      I3 => cs_fsm_FSM_FFd14_19149,
      I4 => NlwRenamedSig_OI_grant,
      I5 => cs_fsm_FSM_FFd11_19143,
      O => cs_fsm_FSM_FFd11_In
    );
  state_FSM_FFd3_In1 : LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
    port map (
      I0 => state_FSM_FFd4_19271,
      I1 => wait_cntr(1),
      I2 => reg_req_pkt_tx_19256,
      I3 => wait_cntr(0),
      I4 => cfg_arb_tdst_rdy_n,
      I5 => state_FSM_FFd3_19269,
      O => state_FSM_FFd3_In
    );
  cfg_arb_tsof_n_mux0000_SW0 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => wait_cntr(1),
      I1 => reg_req_pkt_tx_19256,
      I2 => wait_cntr(0),
      O => N21
    );
  cs_fsm_FSM_FFd7_In1 : LUT6
    generic map(
      INIT => X"1000FFFF10001000"
    )
    port map (
      I0 => intr_req_type(1),
      I1 => intr_req_type(0),
      I2 => cs_fsm_FSM_N1,
      I3 => intr_req_valid,
      I4 => NlwRenamedSig_OI_grant,
      I5 => cs_fsm_FSM_FFd7_19160,
      O => cs_fsm_FSM_FFd7_In
    );
  cs_fsm_FSM_FFd6_In1 : LUT6
    generic map(
      INIT => X"20002000FFFF2000"
    )
    port map (
      I0 => cs_fsm_FSM_N1,
      I1 => intr_req_type(1),
      I2 => intr_req_valid,
      I3 => intr_req_type(0),
      I4 => cs_fsm_FSM_FFd6_19158,
      I5 => NlwRenamedSig_OI_grant,
      O => cs_fsm_FSM_FFd6_In
    );
  cs_fsm_FSM_FFd5_In1 : LUT6
    generic map(
      INIT => X"20002000FFFF2000"
    )
    port map (
      I0 => intr_req_type(1),
      I1 => intr_req_type(0),
      I2 => cs_fsm_FSM_N1,
      I3 => intr_req_valid,
      I4 => cs_fsm_FSM_FFd5_19156,
      I5 => NlwRenamedSig_OI_grant,
      O => cs_fsm_FSM_FFd5_In
    );
  cs_fsm_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"F444444444444444"
    )
    port map (
      I0 => NlwRenamedSig_OI_grant,
      I1 => cs_fsm_FSM_FFd4_19154,
      I2 => cs_fsm_FSM_N1,
      I3 => intr_req_valid,
      I4 => intr_req_type(0),
      I5 => intr_req_type(1),
      O => cs_fsm_FSM_FFd4_In
    );
  cfg_arb_td_47_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(7),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(47),
      O => cfg_arb_td_47_mux0000
    );
  cfg_arb_td_46_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(6),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(46),
      O => cfg_arb_td_46_mux0000
    );
  cfg_arb_td_43_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(3),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(43),
      O => cfg_arb_td_43_mux0000
    );
  cfg_arb_td_42_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(2),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(42),
      O => cfg_arb_td_42_mux0000
    );
  cfg_arb_td_41_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(1),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(41),
      O => cfg_arb_td_41_mux0000
    );
  cfg_arb_td_40_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_10(0),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(40),
      O => cfg_arb_td_40_mux0000
    );
  cfg_arb_td_39_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(7),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(39),
      O => cfg_arb_td_39_mux0000
    );
  cfg_arb_td_38_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(6),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(38),
      O => cfg_arb_td_38_mux0000
    );
  cfg_arb_td_37_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(5),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(37),
      O => cfg_arb_td_37_mux0000
    );
  cfg_arb_td_36_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(4),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(36),
      O => cfg_arb_td_36_mux0000
    );
  cfg_arb_td_35_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(3),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(35),
      O => cfg_arb_td_35_mux0000
    );
  cfg_arb_td_34_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(2),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(34),
      O => cfg_arb_td_34_mux0000
    );
  cfg_arb_td_33_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => byte_11(1),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(33),
      O => cfg_arb_td_33_mux0000
    );
  cfg_arb_td_1_mux00001 : LUT6
    generic map(
      INIT => X"C8CDC8C8888D8888"
    )
    port map (
      I0 => state_FSM_FFd4_19271,
      I1 => byte_07(1),
      I2 => state_FSM_FFd3_19269,
      I3 => state_FSM_FFd2_19267,
      I4 => NlwRenamedSig_OI_cfg_arb_td(1),
      I5 => cfg_arb_tdst_rdy_n,
      O => cfg_arb_td_1_mux0000
    );
  cfg_arb_td_18_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => bytes_12_to_15(18),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(18),
      O => cfg_arb_td_18_mux0000
    );
  cfg_arb_td_17_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => bytes_12_to_15(17),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(17),
      O => cfg_arb_td_17_mux0000
    );
  cfg_arb_td_16_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => bytes_12_to_15(16),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(16),
      O => cfg_arb_td_16_mux0000
    );
  cfg_arb_td_14_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => bytes_12_to_15(14),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(14),
      O => cfg_arb_td_14_mux0000
    );
  cfg_arb_td_12_mux00001 : LUT6
    generic map(
      INIT => X"A280A28FA280A280"
    )
    port map (
      I0 => bytes_12_to_15(12),
      I1 => cfg_arb_tdst_rdy_n,
      I2 => state_FSM_FFd2_19267,
      I3 => state_FSM_FFd3_19269,
      I4 => state_FSM_FFd4_19271,
      I5 => NlwRenamedSig_OI_cfg_arb_td(12),
      O => cfg_arb_td_12_mux0000
    );
  cfg_arb_td_0_mux00001 : LUT6
    generic map(
      INIT => X"C8CDC8C8888D8888"
    )
    port map (
      I0 => state_FSM_FFd4_19271,
      I1 => byte_07(0),
      I2 => state_FSM_FFd3_19269,
      I3 => state_FSM_FFd2_19267,
      I4 => NlwRenamedSig_OI_cfg_arb_td(0),
      I5 => cfg_arb_tdst_rdy_n,
      O => cfg_arb_td_0_mux0000
    );
  cfg_arb_tsrc_rdy_n_mux00001 : LUT6
    generic map(
      INIT => X"F4F4F444F4F4F4F4"
    )
    port map (
      I0 => cfg_arb_tdst_rdy_n,
      I1 => state_FSM_FFd1_19265,
      I2 => state_FSM_FFd4_19271,
      I3 => wait_cntr(0),
      I4 => wait_cntr(1),
      I5 => reg_req_pkt_tx_19256,
      O => cfg_arb_tsrc_rdy_n_mux0000
    );
  cfg_arb_td_62_mux0000 : MUXF7
    port map (
      I0 => N122,
      I1 => N123,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_62_mux0000_19005
    );
  cfg_arb_td_62_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(62),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(6),
      I5 => byte_08(6),
      O => N122
    );
  cfg_arb_td_62_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(6),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(6),
      I4 => intr_vector(6),
      I5 => state_FSM_FFd4_19271,
      O => N123
    );
  cfg_arb_td_61_mux0000 : MUXF7
    port map (
      I0 => N124,
      I1 => N125,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_61_mux0000_19003
    );
  cfg_arb_td_61_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(61),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(5),
      I5 => byte_08(5),
      O => N124
    );
  cfg_arb_td_61_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(5),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(5),
      I4 => intr_vector(5),
      I5 => state_FSM_FFd4_19271,
      O => N125
    );
  cfg_arb_td_60_mux0000 : MUXF7
    port map (
      I0 => N126,
      I1 => N127,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_60_mux0000_19001
    );
  cfg_arb_td_60_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(60),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(4),
      I5 => byte_08(4),
      O => N126
    );
  cfg_arb_td_60_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(4),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(4),
      I4 => intr_vector(4),
      I5 => state_FSM_FFd4_19271,
      O => N127
    );
  cfg_arb_td_59_mux0000 : MUXF7
    port map (
      I0 => N128,
      I1 => N129,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_59_mux0000_18997
    );
  cfg_arb_td_59_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(59),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(3),
      I5 => byte_08(3),
      O => N128
    );
  cfg_arb_td_59_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(3),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(3),
      I4 => intr_vector(3),
      I5 => state_FSM_FFd4_19271,
      O => N129
    );
  cfg_arb_td_58_mux0000 : MUXF7
    port map (
      I0 => N130,
      I1 => N131,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_58_mux0000_18995
    );
  cfg_arb_td_58_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(58),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(2),
      I5 => byte_08(2),
      O => N130
    );
  cfg_arb_td_58_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(2),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(2),
      I4 => intr_vector(2),
      I5 => state_FSM_FFd4_19271,
      O => N131
    );
  cfg_arb_td_57_mux0000 : MUXF7
    port map (
      I0 => N132,
      I1 => N133,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_57_mux0000_18993
    );
  cfg_arb_td_57_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(57),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(1),
      I5 => byte_08(1),
      O => N132
    );
  cfg_arb_td_57_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(1),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(1),
      I4 => intr_vector(1),
      I5 => state_FSM_FFd4_19271,
      O => N133
    );
  cfg_arb_td_56_mux0000 : MUXF7
    port map (
      I0 => N134,
      I1 => N135,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_56_mux0000_18991
    );
  cfg_arb_td_56_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(56),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_00(0),
      I5 => byte_08(0),
      O => N134
    );
  cfg_arb_td_56_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_08(0),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_00(0),
      I4 => intr_vector(0),
      I5 => state_FSM_FFd4_19271,
      O => N135
    );
  cfg_arb_td_54_mux0000 : MUXF7
    port map (
      I0 => N136,
      I1 => N137,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_54_mux0000_18987
    );
  cfg_arb_td_54_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(54),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_01(6),
      I5 => byte_09(6),
      O => N136
    );
  cfg_arb_td_54_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_09(6),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_01(6),
      I4 => msi_data(14),
      I5 => state_FSM_FFd4_19271,
      O => N137
    );
  cfg_arb_td_53_mux0000 : MUXF7
    port map (
      I0 => N138,
      I1 => N139,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_53_mux0000_18985
    );
  cfg_arb_td_53_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(53),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_01(5),
      I5 => byte_09(5),
      O => N138
    );
  cfg_arb_td_53_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_09(5),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_01(5),
      I4 => msi_data(13),
      I5 => state_FSM_FFd4_19271,
      O => N139
    );
  cfg_arb_td_52_mux0000 : MUXF7
    port map (
      I0 => N140,
      I1 => N141,
      S => state_FSM_FFd2_19267,
      O => cfg_arb_td_52_mux0000_18983
    );
  cfg_arb_td_52_mux0000_F : LUT6
    generic map(
      INIT => X"FEFE02CEFEF20202"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_arb_td(52),
      I1 => state_FSM_FFd3_19269,
      I2 => state_FSM_FFd4_19271,
      I3 => cfg_arb_tdst_rdy_n,
      I4 => byte_01(4),
      I5 => byte_09(4),
      O => N140
    );
  cfg_arb_td_52_mux0000_G : LUT6
    generic map(
      INIT => X"FFCFFFC8EFCFE8C8"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_09(4),
      I2 => cfg_arb_tdst_rdy_n,
      I3 => byte_01(4),
      I4 => msi_data(12),
      I5 => state_FSM_FFd4_19271,
      O => N141
    );
  Mcount_wait_cntr_xor_0_11_INV_0 : INV
    port map (
      I => wait_cntr(0),
      O => Result(0)
    );
  cs_fsm_FSM_Scst_FSM_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => cs_fsm_FSM_Scst_FSM_inv
    );
  XST_VCC : VCC
    port map (
      P => N142
    );
  byte_00_mux0000_3_1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
    port map (
      I0 => cs_fsm_FSM_FFd7_19160,
      I1 => cs_fsm_FSM_FFd6_19158,
      I2 => byte_00(4),
      I3 => byte_00_or0000_18693,
      I4 => cs_fsm_FSM_FFd10_19141,
      I5 => cs_fsm_FSM_FFd11_19143,
      O => byte_00_mux0000_3_1_18688
    );
  byte_00_mux0000_3_f7 : MUXF7
    port map (
      I0 => byte_00_mux0000_3_1_18688,
      I1 => N142,
      S => cs_fsm_FSM_FFd9_19162,
      O => byte_00_mux0000(3)
    );
  byte_07_mux0000_30_131 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => cs_fsm_FSM_FFd12_19145,
      I1 => cmt_rd_hdr(30),
      I2 => cs_fsm_FSM_FFd13_19147,
      I3 => cfg_rd_hdr(30),
      I4 => cs_fsm_FSM_FFd4_19154,
      I5 => cs_fsm_FSM_FFd11_19143,
      O => byte_07_mux0000_30_131_18756
    );
  byte_07_mux0000_30_13_f7 : MUXF7
    port map (
      I0 => byte_07_mux0000_30_131_18756,
      I1 => N142,
      S => cs_fsm_FSM_FFd5_19156,
      O => byte_07_mux0000_30_13
    );
  cfg_arb_teof_n_mux00001 : LUT6
    generic map(
      INIT => X"FFFFAAFFFF80AA80"
    )
    port map (
      I0 => state_FSM_FFd3_19269,
      I1 => byte_00(6),
      I2 => byte_00(5),
      I3 => cfg_arb_tdst_rdy_n,
      I4 => state_FSM_FFd2_19267,
      I5 => state_FSM_FFd1_19265,
      O => cfg_arb_teof_n_mux00001_19019
    );
  cfg_arb_teof_n_mux0000_f7 : MUXF7
    port map (
      I0 => cfg_arb_teof_n_mux00001_19019,
      I1 => N142,
      S => state_FSM_FFd4_19271,
      O => cfg_arb_teof_n_mux0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_cf is
  port (
    rx_err_cpl_ur_n : in STD_LOGIC := 'X'; 
    l0_set_user_system_error : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_ur_lock_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    l0_set_user_received_master_abort : out STD_LOGIC; 
    llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
    l0_set_detected_nonfatal_error : out STD_LOGIC; 
    cfg_arb_teof_n : out STD_LOGIC; 
    cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
    serr_enable : in STD_LOGIC := 'X'; 
    mgmt_rden : out STD_LOGIC; 
    cfg_to_turnoff_n : out STD_LOGIC; 
    l0_set_detected_corr_error : out STD_LOGIC; 
    mac_link_up : in STD_LOGIC := 'X'; 
    mgmt_wren : out STD_LOGIC; 
    bus_master_enable : in STD_LOGIC := 'X'; 
    cfg_rd_en_n : in STD_LOGIC := 'X'; 
    cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
    cfg_arb_tsrc_rdy_n : out STD_LOGIC; 
    io_space_enable : in STD_LOGIC := 'X'; 
    l0_pwr_turn_off_req : in STD_LOGIC := 'X'; 
    parity_error_response : in STD_LOGIC := 'X'; 
    cfg_rd_wr_done_n : out STD_LOGIC; 
    l0_pme_req_in : out STD_LOGIC; 
    rx_err_cpl_ep_n : in STD_LOGIC := 'X'; 
    legacy_int_request : out STD_LOGIC; 
    rx_err_tlp_ur_n : in STD_LOGIC := 'X'; 
    l0_set_user_master_data_parity : out STD_LOGIC; 
    msi_8bit_en : in STD_LOGIC := 'X'; 
    cfg_err_locked_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    cfg_arb_tsof_n : out STD_LOGIC; 
    cfg_trn_pending_n : in STD_LOGIC := 'X'; 
    l0_set_user_detected_parity_error : out STD_LOGIC; 
    l0_set_user_signaled_target_abort : out STD_LOGIC; 
    l0_set_detected_fatal_error : out STD_LOGIC; 
    tx_err_wr_ep_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_malformed_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_p_cpl_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_msienable : out STD_LOGIC; 
    cfg_err_ur_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    cfg_wr_en_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_received : in STD_LOGIC := 'X'; 
    l0_pme_ack : in STD_LOGIC := 'X'; 
    msi_enable : in STD_LOGIC := 'X'; 
    cfg_pm_wake_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_rdy_n : out STD_LOGIC; 
    cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
    mem_space_enable : in STD_LOGIC := 'X'; 
    cfg_err_posted_n : in STD_LOGIC := 'X'; 
    rx_err_ep_n : in STD_LOGIC := 'X'; 
    l0_set_unsupported_request_other_error : out STD_LOGIC; 
    cfg_err_cpl_rdy_n : out STD_LOGIC; 
    l0_set_user_received_target_abort : out STD_LOGIC; 
    cfg_arb_tdst_rdy_n : in STD_LOGIC := 'X'; 
    rx_err_tlp_poisoned_n : in STD_LOGIC := 'X'; 
    cfg_err_cor_n : in STD_LOGIC := 'X'; 
    transactions_pending : out STD_LOGIC; 
    cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
    trn_lnk_up_n : out STD_LOGIC; 
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mgmt_bwren : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    mgmt_addr : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_arb_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_dcap : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_rx_xrom : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    msi_request : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_pmcsr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_arb_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_rx_bar0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    mgmt_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar4 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar5 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    l0_ltssm_state : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rx_err_tlp_hdr : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    mac_negotiated_link_width : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    mgmt_pso : in STD_LOGIC_VECTOR ( 16 downto 0 ); 
    l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    completer_id : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    cfg_dwaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_rx_data_d : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mgmt_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    max_read_request_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end pcie_blk_cf;

architecture STRUCTURE of pcie_blk_cf is
  component pcie_blk_cf_arb
    port (
      clk : in STD_LOGIC := 'X'; 
      cs_is_nfl : out STD_LOGIC; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_arb_teof_n : out STD_LOGIC; 
      intr_req_valid : in STD_LOGIC := 'X'; 
      send_ftl : in STD_LOGIC := 'X'; 
      cfg_arb_tsrc_rdy_n : out STD_LOGIC; 
      send_pmeack : in STD_LOGIC := 'X'; 
      send_cplt : in STD_LOGIC := 'X'; 
      send_cplu : in STD_LOGIC := 'X'; 
      cs_is_ftl : out STD_LOGIC; 
      cfg_arb_tsof_n : out STD_LOGIC; 
      cs_is_intr : out STD_LOGIC; 
      send_cor : in STD_LOGIC := 'X'; 
      cs_is_pm : out STD_LOGIC; 
      cs_is_cplt : out STD_LOGIC; 
      cs_is_cplu : out STD_LOGIC; 
      cs_is_cor : out STD_LOGIC; 
      grant : out STD_LOGIC; 
      cfg_arb_tdst_rdy_n : in STD_LOGIC := 'X'; 
      send_nfl : in STD_LOGIC := 'X'; 
      cfg_arb_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      request_data : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
      cfg_arb_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
      msi_data : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      intr_vector : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      msi_laddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      msi_haddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_rd_hdr : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
      cmt_rd_hdr : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
      cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      intr_req_type : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  component pcie_blk_cf_pwr
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_to_turnoff_n : out STD_LOGIC; 
      send_pmeack : out STD_LOGIC; 
      l0_pwr_turn_off_req : in STD_LOGIC := 'X'; 
      l0_pme_req_in : out STD_LOGIC; 
      l0_pme_ack : in STD_LOGIC := 'X'; 
      cfg_pm_wake_n : in STD_LOGIC := 'X'; 
      cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
      cs_is_pm : in STD_LOGIC := 'X'; 
      grant : in STD_LOGIC := 'X' 
    );
  end component;
  component pcie_blk_cf_mgmt
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
      mgmt_rden : out STD_LOGIC; 
      l0_set_detected_corr_error : in STD_LOGIC := 'X'; 
      mgmt_wren : out STD_LOGIC; 
      cfg_rd_en_n : in STD_LOGIC := 'X'; 
      cfg_rd_wr_done_n : out STD_LOGIC; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      l0_stats_cfg_received : in STD_LOGIC := 'X'; 
      l0_set_unsupported_request_other_error : in STD_LOGIC := 'X'; 
      cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
      cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_msguaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mgmt_bwren : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      mgmt_addr : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
      cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_dcap : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_xrom : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_pmcsr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_msgctrl : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_msgladdr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_msgdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_rx_bar0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      mgmt_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar4 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar5 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      mgmt_pso : in STD_LOGIC_VECTOR ( 16 downto 0 ); 
      l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      completer_id : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_dwaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_rx_data_d : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mgmt_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  component pcie_blk_cf_err
    port (
      rx_err_cpl_ur_n : in STD_LOGIC := 'X'; 
      l0_set_user_system_error : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      cs_is_nfl : in STD_LOGIC := 'X'; 
      rx_err_tlp_ur_lock_n : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      l0_set_user_received_master_abort : out STD_LOGIC; 
      l0_set_detected_nonfatal_error : out STD_LOGIC; 
      cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
      l0_set_detected_corr_error : out STD_LOGIC; 
      send_ftl : out STD_LOGIC; 
      cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
      send_cplt : out STD_LOGIC; 
      send_cplu : out STD_LOGIC; 
      cs_is_ftl : in STD_LOGIC := 'X'; 
      rx_err_cpl_ep_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_ur_n : in STD_LOGIC := 'X'; 
      l0_set_user_master_data_parity : out STD_LOGIC; 
      cfg_err_locked_n : in STD_LOGIC := 'X'; 
      l0_mac_link_up : in STD_LOGIC := 'X'; 
      l0_set_user_detected_parity_error : out STD_LOGIC; 
      l0_set_user_signaled_target_abort : out STD_LOGIC; 
      l0_set_detected_fatal_error : out STD_LOGIC; 
      tx_err_wr_ep_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_malformed_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_p_cpl_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
      cfg_err_ur_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      send_cor : out STD_LOGIC; 
      cfg_err_posted_n : in STD_LOGIC := 'X'; 
      rx_err_ep_n : in STD_LOGIC := 'X'; 
      l0_set_unsupported_request_other_error : out STD_LOGIC; 
      cs_is_cplt : in STD_LOGIC := 'X'; 
      cs_is_cplu : in STD_LOGIC := 'X'; 
      cs_is_cor : in STD_LOGIC := 'X'; 
      cfg_err_cpl_rdy_n : out STD_LOGIC; 
      l0_set_user_received_target_abort : out STD_LOGIC; 
      grant : in STD_LOGIC := 'X'; 
      rx_err_tlp_poisoned_n : in STD_LOGIC := 'X'; 
      send_nfl : out STD_LOGIC; 
      serr_en : in STD_LOGIC := 'X'; 
      cfg_err_cor_n : in STD_LOGIC := 'X'; 
      cfg_rd_hdr : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
      cmt_rd_hdr : out STD_LOGIC_VECTOR ( 49 downto 0 ); 
      rx_err_tlp_hdr : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      request_data : in STD_LOGIC_VECTOR ( 49 downto 0 ); 
      l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      cfg_command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component pcie_soft_cf_int
    port (
      clk : in STD_LOGIC := 'X'; 
      signaledint : out STD_LOGIC; 
      rst_n : in STD_LOGIC := 'X'; 
      intr_req_valid : out STD_LOGIC; 
      legacy_int_request : out STD_LOGIC; 
      msi_8bit_en : in STD_LOGIC := 'X'; 
      cfg_interrupt_msienable : out STD_LOGIC; 
      cfg_interrupt_n : in STD_LOGIC := 'X'; 
      cs_is_intr : in STD_LOGIC := 'X'; 
      msi_enable : in STD_LOGIC := 'X'; 
      cfg_interrupt_rdy_n : out STD_LOGIC; 
      grant : in STD_LOGIC := 'X'; 
      cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      intr_vector : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      msi_request : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      intr_req_type : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      cfg_msguaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      msi_laddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      msi_haddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_msgctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_msgdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  signal cs_is_cor : STD_LOGIC; 
  signal cs_is_cplt : STD_LOGIC; 
  signal cs_is_cplu : STD_LOGIC; 
  signal cs_is_ftl : STD_LOGIC; 
  signal cs_is_intr : STD_LOGIC; 
  signal cs_is_nfl : STD_LOGIC; 
  signal cs_is_pm : STD_LOGIC; 
  signal grant : STD_LOGIC; 
  signal intr_req_valid : STD_LOGIC; 
  signal NlwRenamedSig_OI_l0_set_detected_corr_error : STD_LOGIC; 
  signal NlwRenamedSig_OI_l0_set_unsupported_request_other_error : STD_LOGIC; 
  signal llk_tc_status_reg_21595 : STD_LOGIC; 
  signal send_cor : STD_LOGIC; 
  signal send_cplt : STD_LOGIC; 
  signal send_cplu : STD_LOGIC; 
  signal send_ftl : STD_LOGIC; 
  signal send_nfl : STD_LOGIC; 
  signal send_pmeack : STD_LOGIC; 
  signal NlwRenamedSig_OI_transactions_pending : STD_LOGIC; 
  signal NLW_interrupt_interface_signaledint_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_cpl_abort_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_cpl_unexpect_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_ecrc_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_locked_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_cpl_timeout_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_ur_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_rx_err_tlp_poisoned_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_error_manager_cfg_err_cor_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_management_interface_cfg_rd_en_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pwr_interface_cfg_pm_wake_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pwr_interface_cfg_turnoff_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSig_OI_cfg_bus_number : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_command : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_dcommand : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_device_number : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_function_number : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cfg_msgctrl : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cfg_msgdata : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cfg_msgladdr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cfg_msguaddr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cfg_rd_hdr : STD_LOGIC_VECTOR ( 49 downto 0 ); 
  signal cmt_rd_hdr : STD_LOGIC_VECTOR ( 49 downto 0 ); 
  signal completer_id_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal intr_req_type : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal intr_vector : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal request_data : STD_LOGIC_VECTOR ( 49 downto 0 ); 
begin
  l0_set_detected_corr_error <= NlwRenamedSig_OI_l0_set_detected_corr_error;
  l0_set_unsupported_request_other_error <= NlwRenamedSig_OI_l0_set_unsupported_request_other_error;
  transactions_pending <= NlwRenamedSig_OI_transactions_pending;
  cfg_device_number(4) <= NlwRenamedSig_OI_cfg_device_number(4);
  cfg_device_number(3) <= NlwRenamedSig_OI_cfg_device_number(3);
  cfg_device_number(2) <= NlwRenamedSig_OI_cfg_device_number(2);
  cfg_device_number(1) <= NlwRenamedSig_OI_cfg_device_number(1);
  cfg_device_number(0) <= NlwRenamedSig_OI_cfg_device_number(0);
  cfg_bus_number(7) <= NlwRenamedSig_OI_cfg_bus_number(7);
  cfg_bus_number(6) <= NlwRenamedSig_OI_cfg_bus_number(6);
  cfg_bus_number(5) <= NlwRenamedSig_OI_cfg_bus_number(5);
  cfg_bus_number(4) <= NlwRenamedSig_OI_cfg_bus_number(4);
  cfg_bus_number(3) <= NlwRenamedSig_OI_cfg_bus_number(3);
  cfg_bus_number(2) <= NlwRenamedSig_OI_cfg_bus_number(2);
  cfg_bus_number(1) <= NlwRenamedSig_OI_cfg_bus_number(1);
  cfg_bus_number(0) <= NlwRenamedSig_OI_cfg_bus_number(0);
  cfg_command(15) <= NlwRenamedSig_OI_cfg_command(15);
  cfg_command(14) <= NlwRenamedSig_OI_cfg_command(14);
  cfg_command(13) <= NlwRenamedSig_OI_cfg_command(13);
  cfg_command(12) <= NlwRenamedSig_OI_cfg_command(12);
  cfg_command(11) <= NlwRenamedSig_OI_cfg_command(11);
  cfg_command(10) <= NlwRenamedSig_OI_cfg_command(10);
  cfg_command(9) <= NlwRenamedSig_OI_cfg_command(9);
  cfg_command(8) <= NlwRenamedSig_OI_cfg_command(8);
  cfg_command(7) <= NlwRenamedSig_OI_cfg_command(7);
  cfg_command(6) <= NlwRenamedSig_OI_cfg_command(6);
  cfg_command(5) <= NlwRenamedSig_OI_cfg_command(5);
  cfg_command(4) <= NlwRenamedSig_OI_cfg_command(4);
  cfg_command(3) <= NlwRenamedSig_OI_cfg_command(3);
  cfg_command(2) <= NlwRenamedSig_OI_cfg_command(2);
  cfg_command(1) <= NlwRenamedSig_OI_cfg_command(1);
  cfg_command(0) <= NlwRenamedSig_OI_cfg_command(0);
  cfg_dcommand(15) <= NlwRenamedSig_OI_cfg_dcommand(15);
  cfg_dcommand(14) <= NlwRenamedSig_OI_cfg_dcommand(14);
  cfg_dcommand(13) <= NlwRenamedSig_OI_cfg_dcommand(13);
  cfg_dcommand(12) <= NlwRenamedSig_OI_cfg_dcommand(12);
  cfg_dcommand(11) <= NlwRenamedSig_OI_cfg_dcommand(11);
  cfg_dcommand(10) <= NlwRenamedSig_OI_cfg_dcommand(10);
  cfg_dcommand(9) <= NlwRenamedSig_OI_cfg_dcommand(9);
  cfg_dcommand(8) <= NlwRenamedSig_OI_cfg_dcommand(8);
  cfg_dcommand(7) <= NlwRenamedSig_OI_cfg_dcommand(7);
  cfg_dcommand(6) <= NlwRenamedSig_OI_cfg_dcommand(6);
  cfg_dcommand(5) <= NlwRenamedSig_OI_cfg_dcommand(5);
  cfg_dcommand(4) <= NlwRenamedSig_OI_cfg_dcommand(4);
  cfg_dcommand(3) <= NlwRenamedSig_OI_cfg_dcommand(3);
  cfg_dcommand(2) <= NlwRenamedSig_OI_cfg_dcommand(2);
  cfg_dcommand(1) <= NlwRenamedSig_OI_cfg_dcommand(1);
  cfg_dcommand(0) <= NlwRenamedSig_OI_cfg_dcommand(0);
  cfg_function_number(2) <= NlwRenamedSig_OI_cfg_function_number(2);
  cfg_function_number(1) <= NlwRenamedSig_OI_cfg_function_number(1);
  cfg_function_number(0) <= NlwRenamedSig_OI_cfg_function_number(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_transactions_pending
    );
  llk_tc_status_reg : FD
    port map (
      C => clk,
      D => llk_tc_status(0),
      Q => llk_tc_status_reg_21595
    );
  completer_id_reg_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(0),
      Q => completer_id_reg(0)
    );
  completer_id_reg_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(1),
      Q => completer_id_reg(1)
    );
  completer_id_reg_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(2),
      Q => completer_id_reg(2)
    );
  completer_id_reg_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(3),
      Q => completer_id_reg(3)
    );
  completer_id_reg_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(4),
      Q => completer_id_reg(4)
    );
  completer_id_reg_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(5),
      Q => completer_id_reg(5)
    );
  completer_id_reg_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(6),
      Q => completer_id_reg(6)
    );
  completer_id_reg_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(7),
      Q => completer_id_reg(7)
    );
  completer_id_reg_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(8),
      Q => completer_id_reg(8)
    );
  completer_id_reg_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(9),
      Q => completer_id_reg(9)
    );
  completer_id_reg_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(10),
      Q => completer_id_reg(10)
    );
  completer_id_reg_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(11),
      Q => completer_id_reg(11)
    );
  completer_id_reg_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => completer_id(12),
      Q => completer_id_reg(12)
    );
  cfg_arb : pcie_blk_cf_arb
    port map (
      clk => clk,
      cs_is_nfl => cs_is_nfl,
      rst_n => rst_n,
      cfg_arb_teof_n => cfg_arb_teof_n,
      intr_req_valid => intr_req_valid,
      send_ftl => send_ftl,
      cfg_arb_tsrc_rdy_n => cfg_arb_tsrc_rdy_n,
      send_pmeack => send_pmeack,
      send_cplt => send_cplt,
      send_cplu => send_cplu,
      cs_is_ftl => cs_is_ftl,
      cfg_arb_tsof_n => cfg_arb_tsof_n,
      cs_is_intr => cs_is_intr,
      send_cor => send_cor,
      cs_is_pm => cs_is_pm,
      cs_is_cplt => cs_is_cplt,
      cs_is_cplu => cs_is_cplu,
      cs_is_cor => cs_is_cor,
      grant => grant,
      cfg_arb_tdst_rdy_n => cfg_arb_tdst_rdy_n,
      send_nfl => send_nfl,
      cfg_arb_td(63) => cfg_arb_td(63),
      cfg_arb_td(62) => cfg_arb_td(62),
      cfg_arb_td(61) => cfg_arb_td(61),
      cfg_arb_td(60) => cfg_arb_td(60),
      cfg_arb_td(59) => cfg_arb_td(59),
      cfg_arb_td(58) => cfg_arb_td(58),
      cfg_arb_td(57) => cfg_arb_td(57),
      cfg_arb_td(56) => cfg_arb_td(56),
      cfg_arb_td(55) => cfg_arb_td(55),
      cfg_arb_td(54) => cfg_arb_td(54),
      cfg_arb_td(53) => cfg_arb_td(53),
      cfg_arb_td(52) => cfg_arb_td(52),
      cfg_arb_td(51) => cfg_arb_td(51),
      cfg_arb_td(50) => cfg_arb_td(50),
      cfg_arb_td(49) => cfg_arb_td(49),
      cfg_arb_td(48) => cfg_arb_td(48),
      cfg_arb_td(47) => cfg_arb_td(47),
      cfg_arb_td(46) => cfg_arb_td(46),
      cfg_arb_td(45) => cfg_arb_td(45),
      cfg_arb_td(44) => cfg_arb_td(44),
      cfg_arb_td(43) => cfg_arb_td(43),
      cfg_arb_td(42) => cfg_arb_td(42),
      cfg_arb_td(41) => cfg_arb_td(41),
      cfg_arb_td(40) => cfg_arb_td(40),
      cfg_arb_td(39) => cfg_arb_td(39),
      cfg_arb_td(38) => cfg_arb_td(38),
      cfg_arb_td(37) => cfg_arb_td(37),
      cfg_arb_td(36) => cfg_arb_td(36),
      cfg_arb_td(35) => cfg_arb_td(35),
      cfg_arb_td(34) => cfg_arb_td(34),
      cfg_arb_td(33) => cfg_arb_td(33),
      cfg_arb_td(32) => cfg_arb_td(32),
      cfg_arb_td(31) => cfg_arb_td(31),
      cfg_arb_td(30) => cfg_arb_td(30),
      cfg_arb_td(29) => cfg_arb_td(29),
      cfg_arb_td(28) => cfg_arb_td(28),
      cfg_arb_td(27) => cfg_arb_td(27),
      cfg_arb_td(26) => cfg_arb_td(26),
      cfg_arb_td(25) => cfg_arb_td(25),
      cfg_arb_td(24) => cfg_arb_td(24),
      cfg_arb_td(23) => cfg_arb_td(23),
      cfg_arb_td(22) => cfg_arb_td(22),
      cfg_arb_td(21) => cfg_arb_td(21),
      cfg_arb_td(20) => cfg_arb_td(20),
      cfg_arb_td(19) => cfg_arb_td(19),
      cfg_arb_td(18) => cfg_arb_td(18),
      cfg_arb_td(17) => cfg_arb_td(17),
      cfg_arb_td(16) => cfg_arb_td(16),
      cfg_arb_td(15) => cfg_arb_td(15),
      cfg_arb_td(14) => cfg_arb_td(14),
      cfg_arb_td(13) => cfg_arb_td(13),
      cfg_arb_td(12) => cfg_arb_td(12),
      cfg_arb_td(11) => cfg_arb_td(11),
      cfg_arb_td(10) => cfg_arb_td(10),
      cfg_arb_td(9) => cfg_arb_td(9),
      cfg_arb_td(8) => cfg_arb_td(8),
      cfg_arb_td(7) => cfg_arb_td(7),
      cfg_arb_td(6) => cfg_arb_td(6),
      cfg_arb_td(5) => cfg_arb_td(5),
      cfg_arb_td(4) => cfg_arb_td(4),
      cfg_arb_td(3) => cfg_arb_td(3),
      cfg_arb_td(2) => cfg_arb_td(2),
      cfg_arb_td(1) => cfg_arb_td(1),
      cfg_arb_td(0) => cfg_arb_td(0),
      request_data(49) => request_data(49),
      request_data(48) => request_data(48),
      request_data(47) => request_data(47),
      request_data(46) => request_data(46),
      request_data(45) => request_data(45),
      request_data(44) => request_data(44),
      request_data(43) => request_data(43),
      request_data(42) => request_data(42),
      request_data(41) => request_data(41),
      request_data(40) => request_data(40),
      request_data(39) => request_data(39),
      request_data(38) => request_data(38),
      request_data(37) => request_data(37),
      request_data(36) => request_data(36),
      request_data(35) => request_data(35),
      request_data(34) => request_data(34),
      request_data(33) => request_data(33),
      request_data(32) => request_data(32),
      request_data(31) => request_data(31),
      request_data(30) => request_data(30),
      request_data(29) => request_data(29),
      request_data(28) => request_data(28),
      request_data(27) => request_data(27),
      request_data(26) => request_data(26),
      request_data(25) => request_data(25),
      request_data(24) => request_data(24),
      request_data(23) => request_data(23),
      request_data(22) => request_data(22),
      request_data(21) => request_data(21),
      request_data(20) => request_data(20),
      request_data(19) => request_data(19),
      request_data(18) => request_data(18),
      request_data(17) => request_data(17),
      request_data(16) => request_data(16),
      request_data(15) => request_data(15),
      request_data(14) => request_data(14),
      request_data(13) => request_data(13),
      request_data(12) => request_data(12),
      request_data(11) => request_data(11),
      request_data(10) => request_data(10),
      request_data(9) => request_data(9),
      request_data(8) => request_data(8),
      request_data(7) => request_data(7),
      request_data(6) => request_data(6),
      request_data(5) => request_data(5),
      request_data(4) => request_data(4),
      request_data(3) => request_data(3),
      request_data(2) => request_data(2),
      request_data(1) => request_data(1),
      request_data(0) => request_data(0),
      cfg_arb_trem_n(7) => cfg_arb_trem_n(7),
      cfg_arb_trem_n(6) => cfg_arb_trem_n(6),
      cfg_arb_trem_n(5) => cfg_arb_trem_n(5),
      cfg_arb_trem_n(4) => cfg_arb_trem_n(4),
      cfg_arb_trem_n(3) => cfg_arb_trem_n(3),
      cfg_arb_trem_n(2) => cfg_arb_trem_n(2),
      cfg_arb_trem_n(1) => cfg_arb_trem_n(1),
      cfg_arb_trem_n(0) => cfg_arb_trem_n(0),
      cfg_device_number(4) => NlwRenamedSig_OI_cfg_device_number(4),
      cfg_device_number(3) => NlwRenamedSig_OI_cfg_device_number(3),
      cfg_device_number(2) => NlwRenamedSig_OI_cfg_device_number(2),
      cfg_device_number(1) => NlwRenamedSig_OI_cfg_device_number(1),
      cfg_device_number(0) => NlwRenamedSig_OI_cfg_device_number(0),
      msi_data(15) => cfg_msgdata(15),
      msi_data(14) => cfg_msgdata(14),
      msi_data(13) => cfg_msgdata(13),
      msi_data(12) => cfg_msgdata(12),
      msi_data(11) => cfg_msgdata(11),
      msi_data(10) => cfg_msgdata(10),
      msi_data(9) => cfg_msgdata(9),
      msi_data(8) => cfg_msgdata(8),
      msi_data(7) => cfg_msgdata(7),
      msi_data(6) => cfg_msgdata(6),
      msi_data(5) => cfg_msgdata(5),
      msi_data(4) => cfg_msgdata(4),
      msi_data(3) => cfg_msgdata(3),
      msi_data(2) => cfg_msgdata(2),
      msi_data(1) => cfg_msgdata(1),
      msi_data(0) => cfg_msgdata(0),
      intr_vector(7) => intr_vector(7),
      intr_vector(6) => intr_vector(6),
      intr_vector(5) => intr_vector(5),
      intr_vector(4) => intr_vector(4),
      intr_vector(3) => intr_vector(3),
      intr_vector(2) => intr_vector(2),
      intr_vector(1) => intr_vector(1),
      intr_vector(0) => intr_vector(0),
      msi_laddr(31) => cfg_msgladdr(31),
      msi_laddr(30) => cfg_msgladdr(30),
      msi_laddr(29) => cfg_msgladdr(29),
      msi_laddr(28) => cfg_msgladdr(28),
      msi_laddr(27) => cfg_msgladdr(27),
      msi_laddr(26) => cfg_msgladdr(26),
      msi_laddr(25) => cfg_msgladdr(25),
      msi_laddr(24) => cfg_msgladdr(24),
      msi_laddr(23) => cfg_msgladdr(23),
      msi_laddr(22) => cfg_msgladdr(22),
      msi_laddr(21) => cfg_msgladdr(21),
      msi_laddr(20) => cfg_msgladdr(20),
      msi_laddr(19) => cfg_msgladdr(19),
      msi_laddr(18) => cfg_msgladdr(18),
      msi_laddr(17) => cfg_msgladdr(17),
      msi_laddr(16) => cfg_msgladdr(16),
      msi_laddr(15) => cfg_msgladdr(15),
      msi_laddr(14) => cfg_msgladdr(14),
      msi_laddr(13) => cfg_msgladdr(13),
      msi_laddr(12) => cfg_msgladdr(12),
      msi_laddr(11) => cfg_msgladdr(11),
      msi_laddr(10) => cfg_msgladdr(10),
      msi_laddr(9) => cfg_msgladdr(9),
      msi_laddr(8) => cfg_msgladdr(8),
      msi_laddr(7) => cfg_msgladdr(7),
      msi_laddr(6) => cfg_msgladdr(6),
      msi_laddr(5) => cfg_msgladdr(5),
      msi_laddr(4) => cfg_msgladdr(4),
      msi_laddr(3) => cfg_msgladdr(3),
      msi_laddr(2) => cfg_msgladdr(2),
      msi_laddr(1) => cfg_msgladdr(1),
      msi_laddr(0) => cfg_msgladdr(0),
      msi_haddr(31) => cfg_msguaddr(31),
      msi_haddr(30) => cfg_msguaddr(30),
      msi_haddr(29) => cfg_msguaddr(29),
      msi_haddr(28) => cfg_msguaddr(28),
      msi_haddr(27) => cfg_msguaddr(27),
      msi_haddr(26) => cfg_msguaddr(26),
      msi_haddr(25) => cfg_msguaddr(25),
      msi_haddr(24) => cfg_msguaddr(24),
      msi_haddr(23) => cfg_msguaddr(23),
      msi_haddr(22) => cfg_msguaddr(22),
      msi_haddr(21) => cfg_msguaddr(21),
      msi_haddr(20) => cfg_msguaddr(20),
      msi_haddr(19) => cfg_msguaddr(19),
      msi_haddr(18) => cfg_msguaddr(18),
      msi_haddr(17) => cfg_msguaddr(17),
      msi_haddr(16) => cfg_msguaddr(16),
      msi_haddr(15) => cfg_msguaddr(15),
      msi_haddr(14) => cfg_msguaddr(14),
      msi_haddr(13) => cfg_msguaddr(13),
      msi_haddr(12) => cfg_msguaddr(12),
      msi_haddr(11) => cfg_msguaddr(11),
      msi_haddr(10) => cfg_msguaddr(10),
      msi_haddr(9) => cfg_msguaddr(9),
      msi_haddr(8) => cfg_msguaddr(8),
      msi_haddr(7) => cfg_msguaddr(7),
      msi_haddr(6) => cfg_msguaddr(6),
      msi_haddr(5) => cfg_msguaddr(5),
      msi_haddr(4) => cfg_msguaddr(4),
      msi_haddr(3) => cfg_msguaddr(3),
      msi_haddr(2) => cfg_msguaddr(2),
      msi_haddr(1) => cfg_msguaddr(1),
      msi_haddr(0) => cfg_msguaddr(0),
      cfg_bus_number(7) => NlwRenamedSig_OI_cfg_bus_number(7),
      cfg_bus_number(6) => NlwRenamedSig_OI_cfg_bus_number(6),
      cfg_bus_number(5) => NlwRenamedSig_OI_cfg_bus_number(5),
      cfg_bus_number(4) => NlwRenamedSig_OI_cfg_bus_number(4),
      cfg_bus_number(3) => NlwRenamedSig_OI_cfg_bus_number(3),
      cfg_bus_number(2) => NlwRenamedSig_OI_cfg_bus_number(2),
      cfg_bus_number(1) => NlwRenamedSig_OI_cfg_bus_number(1),
      cfg_bus_number(0) => NlwRenamedSig_OI_cfg_bus_number(0),
      cfg_rd_hdr(49) => cfg_rd_hdr(49),
      cfg_rd_hdr(48) => cfg_rd_hdr(48),
      cfg_rd_hdr(47) => cfg_rd_hdr(47),
      cfg_rd_hdr(46) => cfg_rd_hdr(46),
      cfg_rd_hdr(45) => cfg_rd_hdr(45),
      cfg_rd_hdr(44) => cfg_rd_hdr(44),
      cfg_rd_hdr(43) => cfg_rd_hdr(43),
      cfg_rd_hdr(42) => cfg_rd_hdr(42),
      cfg_rd_hdr(41) => cfg_rd_hdr(41),
      cfg_rd_hdr(40) => cfg_rd_hdr(40),
      cfg_rd_hdr(39) => cfg_rd_hdr(39),
      cfg_rd_hdr(38) => cfg_rd_hdr(38),
      cfg_rd_hdr(37) => cfg_rd_hdr(37),
      cfg_rd_hdr(36) => cfg_rd_hdr(36),
      cfg_rd_hdr(35) => cfg_rd_hdr(35),
      cfg_rd_hdr(34) => cfg_rd_hdr(34),
      cfg_rd_hdr(33) => cfg_rd_hdr(33),
      cfg_rd_hdr(32) => cfg_rd_hdr(32),
      cfg_rd_hdr(31) => cfg_rd_hdr(31),
      cfg_rd_hdr(30) => cfg_rd_hdr(30),
      cfg_rd_hdr(29) => cfg_rd_hdr(29),
      cfg_rd_hdr(28) => cfg_rd_hdr(28),
      cfg_rd_hdr(27) => cfg_rd_hdr(27),
      cfg_rd_hdr(26) => cfg_rd_hdr(26),
      cfg_rd_hdr(25) => cfg_rd_hdr(25),
      cfg_rd_hdr(24) => cfg_rd_hdr(24),
      cfg_rd_hdr(23) => cfg_rd_hdr(23),
      cfg_rd_hdr(22) => cfg_rd_hdr(22),
      cfg_rd_hdr(21) => cfg_rd_hdr(21),
      cfg_rd_hdr(20) => cfg_rd_hdr(20),
      cfg_rd_hdr(19) => cfg_rd_hdr(19),
      cfg_rd_hdr(18) => cfg_rd_hdr(18),
      cfg_rd_hdr(17) => cfg_rd_hdr(17),
      cfg_rd_hdr(16) => cfg_rd_hdr(16),
      cfg_rd_hdr(15) => cfg_rd_hdr(15),
      cfg_rd_hdr(14) => cfg_rd_hdr(14),
      cfg_rd_hdr(13) => cfg_rd_hdr(13),
      cfg_rd_hdr(12) => cfg_rd_hdr(12),
      cfg_rd_hdr(11) => cfg_rd_hdr(11),
      cfg_rd_hdr(10) => cfg_rd_hdr(10),
      cfg_rd_hdr(9) => cfg_rd_hdr(9),
      cfg_rd_hdr(8) => cfg_rd_hdr(8),
      cfg_rd_hdr(7) => cfg_rd_hdr(7),
      cfg_rd_hdr(6) => cfg_rd_hdr(6),
      cfg_rd_hdr(5) => cfg_rd_hdr(5),
      cfg_rd_hdr(4) => cfg_rd_hdr(4),
      cfg_rd_hdr(3) => cfg_rd_hdr(3),
      cfg_rd_hdr(2) => cfg_rd_hdr(2),
      cfg_rd_hdr(1) => cfg_rd_hdr(1),
      cfg_rd_hdr(0) => cfg_rd_hdr(0),
      cmt_rd_hdr(49) => cmt_rd_hdr(49),
      cmt_rd_hdr(48) => cmt_rd_hdr(48),
      cmt_rd_hdr(47) => cmt_rd_hdr(47),
      cmt_rd_hdr(46) => cmt_rd_hdr(46),
      cmt_rd_hdr(45) => cmt_rd_hdr(45),
      cmt_rd_hdr(44) => cmt_rd_hdr(44),
      cmt_rd_hdr(43) => cmt_rd_hdr(43),
      cmt_rd_hdr(42) => cmt_rd_hdr(42),
      cmt_rd_hdr(41) => cmt_rd_hdr(41),
      cmt_rd_hdr(40) => cmt_rd_hdr(40),
      cmt_rd_hdr(39) => cmt_rd_hdr(39),
      cmt_rd_hdr(38) => cmt_rd_hdr(38),
      cmt_rd_hdr(37) => cmt_rd_hdr(37),
      cmt_rd_hdr(36) => cmt_rd_hdr(36),
      cmt_rd_hdr(35) => cmt_rd_hdr(35),
      cmt_rd_hdr(34) => cmt_rd_hdr(34),
      cmt_rd_hdr(33) => cmt_rd_hdr(33),
      cmt_rd_hdr(32) => cmt_rd_hdr(32),
      cmt_rd_hdr(31) => cmt_rd_hdr(31),
      cmt_rd_hdr(30) => cmt_rd_hdr(30),
      cmt_rd_hdr(29) => cmt_rd_hdr(29),
      cmt_rd_hdr(28) => cmt_rd_hdr(28),
      cmt_rd_hdr(27) => cmt_rd_hdr(27),
      cmt_rd_hdr(26) => cmt_rd_hdr(26),
      cmt_rd_hdr(25) => cmt_rd_hdr(25),
      cmt_rd_hdr(24) => cmt_rd_hdr(24),
      cmt_rd_hdr(23) => cmt_rd_hdr(23),
      cmt_rd_hdr(22) => cmt_rd_hdr(22),
      cmt_rd_hdr(21) => cmt_rd_hdr(21),
      cmt_rd_hdr(20) => cmt_rd_hdr(20),
      cmt_rd_hdr(19) => cmt_rd_hdr(19),
      cmt_rd_hdr(18) => cmt_rd_hdr(18),
      cmt_rd_hdr(17) => cmt_rd_hdr(17),
      cmt_rd_hdr(16) => cmt_rd_hdr(16),
      cmt_rd_hdr(15) => cmt_rd_hdr(15),
      cmt_rd_hdr(14) => cmt_rd_hdr(14),
      cmt_rd_hdr(13) => cmt_rd_hdr(13),
      cmt_rd_hdr(12) => cmt_rd_hdr(12),
      cmt_rd_hdr(11) => cmt_rd_hdr(11),
      cmt_rd_hdr(10) => cmt_rd_hdr(10),
      cmt_rd_hdr(9) => cmt_rd_hdr(9),
      cmt_rd_hdr(8) => cmt_rd_hdr(8),
      cmt_rd_hdr(7) => cmt_rd_hdr(7),
      cmt_rd_hdr(6) => cmt_rd_hdr(6),
      cmt_rd_hdr(5) => cmt_rd_hdr(5),
      cmt_rd_hdr(4) => cmt_rd_hdr(4),
      cmt_rd_hdr(3) => cmt_rd_hdr(3),
      cmt_rd_hdr(2) => cmt_rd_hdr(2),
      cmt_rd_hdr(1) => cmt_rd_hdr(1),
      cmt_rd_hdr(0) => cmt_rd_hdr(0),
      cfg_function_number(2) => NlwRenamedSig_OI_cfg_function_number(2),
      cfg_function_number(1) => NlwRenamedSig_OI_cfg_function_number(1),
      cfg_function_number(0) => NlwRenamedSig_OI_cfg_function_number(0),
      intr_req_type(1) => intr_req_type(1),
      intr_req_type(0) => intr_req_type(0)
    );
  pwr_interface : pcie_blk_cf_pwr
    port map (
      clk => clk,
      rst_n => rst_n,
      cfg_to_turnoff_n => cfg_to_turnoff_n,
      send_pmeack => send_pmeack,
      l0_pwr_turn_off_req => l0_pwr_turn_off_req,
      l0_pme_req_in => l0_pme_req_in,
      l0_pme_ack => l0_pme_ack,
      cfg_pm_wake_n => NLW_pwr_interface_cfg_pm_wake_n_UNCONNECTED,
      cfg_turnoff_ok_n => NLW_pwr_interface_cfg_turnoff_ok_n_UNCONNECTED,
      cs_is_pm => cs_is_pm,
      grant => grant
    );
  management_interface : pcie_blk_cf_mgmt
    port map (
      clk => clk,
      rst_n => rst_n,
      llk_rx_src_rdy_n => llk_rx_src_rdy_n,
      mgmt_rden => mgmt_rden,
      l0_set_detected_corr_error => NlwRenamedSig_OI_l0_set_detected_corr_error,
      mgmt_wren => mgmt_wren,
      cfg_rd_en_n => NLW_management_interface_cfg_rd_en_n_UNCONNECTED,
      cfg_rd_wr_done_n => cfg_rd_wr_done_n,
      l0_stats_cfg_transmitted => l0_stats_cfg_transmitted,
      l0_stats_cfg_received => l0_stats_cfg_received,
      l0_set_unsupported_request_other_error => NlwRenamedSig_OI_l0_set_unsupported_request_other_error,
      cfg_device_number(4) => NlwRenamedSig_OI_cfg_device_number(4),
      cfg_device_number(3) => NlwRenamedSig_OI_cfg_device_number(3),
      cfg_device_number(2) => NlwRenamedSig_OI_cfg_device_number(2),
      cfg_device_number(1) => NlwRenamedSig_OI_cfg_device_number(1),
      cfg_device_number(0) => NlwRenamedSig_OI_cfg_device_number(0),
      cfg_dstatus(15) => cfg_dstatus(15),
      cfg_dstatus(14) => cfg_dstatus(14),
      cfg_dstatus(13) => cfg_dstatus(13),
      cfg_dstatus(12) => cfg_dstatus(12),
      cfg_dstatus(11) => cfg_dstatus(11),
      cfg_dstatus(10) => cfg_dstatus(10),
      cfg_dstatus(9) => cfg_dstatus(9),
      cfg_dstatus(8) => cfg_dstatus(8),
      cfg_dstatus(7) => cfg_dstatus(7),
      cfg_dstatus(6) => cfg_dstatus(6),
      cfg_dstatus(5) => cfg_dstatus(5),
      cfg_dstatus(4) => cfg_dstatus(4),
      cfg_dstatus(3) => cfg_dstatus(3),
      cfg_dstatus(2) => cfg_dstatus(2),
      cfg_dstatus(1) => cfg_dstatus(1),
      cfg_dstatus(0) => cfg_dstatus(0),
      cfg_msguaddr(31) => cfg_msguaddr(31),
      cfg_msguaddr(30) => cfg_msguaddr(30),
      cfg_msguaddr(29) => cfg_msguaddr(29),
      cfg_msguaddr(28) => cfg_msguaddr(28),
      cfg_msguaddr(27) => cfg_msguaddr(27),
      cfg_msguaddr(26) => cfg_msguaddr(26),
      cfg_msguaddr(25) => cfg_msguaddr(25),
      cfg_msguaddr(24) => cfg_msguaddr(24),
      cfg_msguaddr(23) => cfg_msguaddr(23),
      cfg_msguaddr(22) => cfg_msguaddr(22),
      cfg_msguaddr(21) => cfg_msguaddr(21),
      cfg_msguaddr(20) => cfg_msguaddr(20),
      cfg_msguaddr(19) => cfg_msguaddr(19),
      cfg_msguaddr(18) => cfg_msguaddr(18),
      cfg_msguaddr(17) => cfg_msguaddr(17),
      cfg_msguaddr(16) => cfg_msguaddr(16),
      cfg_msguaddr(15) => cfg_msguaddr(15),
      cfg_msguaddr(14) => cfg_msguaddr(14),
      cfg_msguaddr(13) => cfg_msguaddr(13),
      cfg_msguaddr(12) => cfg_msguaddr(12),
      cfg_msguaddr(11) => cfg_msguaddr(11),
      cfg_msguaddr(10) => cfg_msguaddr(10),
      cfg_msguaddr(9) => cfg_msguaddr(9),
      cfg_msguaddr(8) => cfg_msguaddr(8),
      cfg_msguaddr(7) => cfg_msguaddr(7),
      cfg_msguaddr(6) => cfg_msguaddr(6),
      cfg_msguaddr(5) => cfg_msguaddr(5),
      cfg_msguaddr(4) => cfg_msguaddr(4),
      cfg_msguaddr(3) => cfg_msguaddr(3),
      cfg_msguaddr(2) => cfg_msguaddr(2),
      cfg_msguaddr(1) => cfg_msguaddr(1),
      cfg_msguaddr(0) => cfg_msguaddr(0),
      cfg_lcommand(15) => cfg_lcommand(15),
      cfg_lcommand(14) => cfg_lcommand(14),
      cfg_lcommand(13) => cfg_lcommand(13),
      cfg_lcommand(12) => cfg_lcommand(12),
      cfg_lcommand(11) => cfg_lcommand(11),
      cfg_lcommand(10) => cfg_lcommand(10),
      cfg_lcommand(9) => cfg_lcommand(9),
      cfg_lcommand(8) => cfg_lcommand(8),
      cfg_lcommand(7) => cfg_lcommand(7),
      cfg_lcommand(6) => cfg_lcommand(6),
      cfg_lcommand(5) => cfg_lcommand(5),
      cfg_lcommand(4) => cfg_lcommand(4),
      cfg_lcommand(3) => cfg_lcommand(3),
      cfg_lcommand(2) => cfg_lcommand(2),
      cfg_lcommand(1) => cfg_lcommand(1),
      cfg_lcommand(0) => cfg_lcommand(0),
      mgmt_bwren(3) => mgmt_bwren(3),
      mgmt_bwren(2) => mgmt_bwren(2),
      mgmt_bwren(1) => mgmt_bwren(1),
      mgmt_bwren(0) => mgmt_bwren(0),
      mgmt_addr(10) => mgmt_addr(10),
      mgmt_addr(9) => mgmt_addr(9),
      mgmt_addr(8) => mgmt_addr(8),
      mgmt_addr(7) => mgmt_addr(7),
      mgmt_addr(6) => mgmt_addr(6),
      mgmt_addr(5) => mgmt_addr(5),
      mgmt_addr(4) => mgmt_addr(4),
      mgmt_addr(3) => mgmt_addr(3),
      mgmt_addr(2) => mgmt_addr(2),
      mgmt_addr(1) => mgmt_addr(1),
      mgmt_addr(0) => mgmt_addr(0),
      cfg_status(15) => cfg_status(15),
      cfg_status(14) => cfg_status(14),
      cfg_status(13) => cfg_status(13),
      cfg_status(12) => cfg_status(12),
      cfg_status(11) => cfg_status(11),
      cfg_status(10) => cfg_status(10),
      cfg_status(9) => cfg_status(9),
      cfg_status(8) => cfg_status(8),
      cfg_status(7) => cfg_status(7),
      cfg_status(6) => cfg_status(6),
      cfg_status(5) => cfg_status(5),
      cfg_status(4) => cfg_status(4),
      cfg_status(3) => cfg_status(3),
      cfg_status(2) => cfg_status(2),
      cfg_status(1) => cfg_status(1),
      cfg_status(0) => cfg_status(0),
      cfg_dcap(31) => cfg_dcap(31),
      cfg_dcap(30) => cfg_dcap(30),
      cfg_dcap(29) => cfg_dcap(29),
      cfg_dcap(28) => cfg_dcap(28),
      cfg_dcap(27) => cfg_dcap(27),
      cfg_dcap(26) => cfg_dcap(26),
      cfg_dcap(25) => cfg_dcap(25),
      cfg_dcap(24) => cfg_dcap(24),
      cfg_dcap(23) => cfg_dcap(23),
      cfg_dcap(22) => cfg_dcap(22),
      cfg_dcap(21) => cfg_dcap(21),
      cfg_dcap(20) => cfg_dcap(20),
      cfg_dcap(19) => cfg_dcap(19),
      cfg_dcap(18) => cfg_dcap(18),
      cfg_dcap(17) => cfg_dcap(17),
      cfg_dcap(16) => cfg_dcap(16),
      cfg_dcap(15) => cfg_dcap(15),
      cfg_dcap(14) => cfg_dcap(14),
      cfg_dcap(13) => cfg_dcap(13),
      cfg_dcap(12) => cfg_dcap(12),
      cfg_dcap(11) => cfg_dcap(11),
      cfg_dcap(10) => cfg_dcap(10),
      cfg_dcap(9) => cfg_dcap(9),
      cfg_dcap(8) => cfg_dcap(8),
      cfg_dcap(7) => cfg_dcap(7),
      cfg_dcap(6) => cfg_dcap(6),
      cfg_dcap(5) => cfg_dcap(5),
      cfg_dcap(4) => cfg_dcap(4),
      cfg_dcap(3) => cfg_dcap(3),
      cfg_dcap(2) => cfg_dcap(2),
      cfg_dcap(1) => cfg_dcap(1),
      cfg_dcap(0) => cfg_dcap(0),
      cfg_rx_xrom(31) => cfg_rx_xrom(31),
      cfg_rx_xrom(30) => cfg_rx_xrom(30),
      cfg_rx_xrom(29) => cfg_rx_xrom(29),
      cfg_rx_xrom(28) => cfg_rx_xrom(28),
      cfg_rx_xrom(27) => cfg_rx_xrom(27),
      cfg_rx_xrom(26) => cfg_rx_xrom(26),
      cfg_rx_xrom(25) => cfg_rx_xrom(25),
      cfg_rx_xrom(24) => cfg_rx_xrom(24),
      cfg_rx_xrom(23) => cfg_rx_xrom(23),
      cfg_rx_xrom(22) => cfg_rx_xrom(22),
      cfg_rx_xrom(21) => cfg_rx_xrom(21),
      cfg_rx_xrom(20) => cfg_rx_xrom(20),
      cfg_rx_xrom(19) => cfg_rx_xrom(19),
      cfg_rx_xrom(18) => cfg_rx_xrom(18),
      cfg_rx_xrom(17) => cfg_rx_xrom(17),
      cfg_rx_xrom(16) => cfg_rx_xrom(16),
      cfg_rx_xrom(15) => cfg_rx_xrom(15),
      cfg_rx_xrom(14) => cfg_rx_xrom(14),
      cfg_rx_xrom(13) => cfg_rx_xrom(13),
      cfg_rx_xrom(12) => cfg_rx_xrom(12),
      cfg_rx_xrom(11) => cfg_rx_xrom(11),
      cfg_rx_xrom(10) => cfg_rx_xrom(10),
      cfg_rx_xrom(9) => cfg_rx_xrom(9),
      cfg_rx_xrom(8) => cfg_rx_xrom(8),
      cfg_rx_xrom(7) => cfg_rx_xrom(7),
      cfg_rx_xrom(6) => cfg_rx_xrom(6),
      cfg_rx_xrom(5) => cfg_rx_xrom(5),
      cfg_rx_xrom(4) => cfg_rx_xrom(4),
      cfg_rx_xrom(3) => cfg_rx_xrom(3),
      cfg_rx_xrom(2) => cfg_rx_xrom(2),
      cfg_rx_xrom(1) => cfg_rx_xrom(1),
      cfg_rx_xrom(0) => cfg_rx_xrom(0),
      cfg_bus_number(7) => NlwRenamedSig_OI_cfg_bus_number(7),
      cfg_bus_number(6) => NlwRenamedSig_OI_cfg_bus_number(6),
      cfg_bus_number(5) => NlwRenamedSig_OI_cfg_bus_number(5),
      cfg_bus_number(4) => NlwRenamedSig_OI_cfg_bus_number(4),
      cfg_bus_number(3) => NlwRenamedSig_OI_cfg_bus_number(3),
      cfg_bus_number(2) => NlwRenamedSig_OI_cfg_bus_number(2),
      cfg_bus_number(1) => NlwRenamedSig_OI_cfg_bus_number(1),
      cfg_bus_number(0) => NlwRenamedSig_OI_cfg_bus_number(0),
      cfg_pmcsr(31) => cfg_pmcsr(31),
      cfg_pmcsr(30) => cfg_pmcsr(30),
      cfg_pmcsr(29) => cfg_pmcsr(29),
      cfg_pmcsr(28) => cfg_pmcsr(28),
      cfg_pmcsr(27) => cfg_pmcsr(27),
      cfg_pmcsr(26) => cfg_pmcsr(26),
      cfg_pmcsr(25) => cfg_pmcsr(25),
      cfg_pmcsr(24) => cfg_pmcsr(24),
      cfg_pmcsr(23) => cfg_pmcsr(23),
      cfg_pmcsr(22) => cfg_pmcsr(22),
      cfg_pmcsr(21) => cfg_pmcsr(21),
      cfg_pmcsr(20) => cfg_pmcsr(20),
      cfg_pmcsr(19) => cfg_pmcsr(19),
      cfg_pmcsr(18) => cfg_pmcsr(18),
      cfg_pmcsr(17) => cfg_pmcsr(17),
      cfg_pmcsr(16) => cfg_pmcsr(16),
      cfg_pmcsr(15) => cfg_pmcsr(15),
      cfg_pmcsr(14) => cfg_pmcsr(14),
      cfg_pmcsr(13) => cfg_pmcsr(13),
      cfg_pmcsr(12) => cfg_pmcsr(12),
      cfg_pmcsr(11) => cfg_pmcsr(11),
      cfg_pmcsr(10) => cfg_pmcsr(10),
      cfg_pmcsr(9) => cfg_pmcsr(9),
      cfg_pmcsr(8) => cfg_pmcsr(8),
      cfg_pmcsr(7) => cfg_pmcsr(7),
      cfg_pmcsr(6) => cfg_pmcsr(6),
      cfg_pmcsr(5) => cfg_pmcsr(5),
      cfg_pmcsr(4) => cfg_pmcsr(4),
      cfg_pmcsr(3) => cfg_pmcsr(3),
      cfg_pmcsr(2) => cfg_pmcsr(2),
      cfg_pmcsr(1) => cfg_pmcsr(1),
      cfg_pmcsr(0) => cfg_pmcsr(0),
      cfg_command(15) => NlwRenamedSig_OI_cfg_command(15),
      cfg_command(14) => NlwRenamedSig_OI_cfg_command(14),
      cfg_command(13) => NlwRenamedSig_OI_cfg_command(13),
      cfg_command(12) => NlwRenamedSig_OI_cfg_command(12),
      cfg_command(11) => NlwRenamedSig_OI_cfg_command(11),
      cfg_command(10) => NlwRenamedSig_OI_cfg_command(10),
      cfg_command(9) => NlwRenamedSig_OI_cfg_command(9),
      cfg_command(8) => NlwRenamedSig_OI_cfg_command(8),
      cfg_command(7) => NlwRenamedSig_OI_cfg_command(7),
      cfg_command(6) => NlwRenamedSig_OI_cfg_command(6),
      cfg_command(5) => NlwRenamedSig_OI_cfg_command(5),
      cfg_command(4) => NlwRenamedSig_OI_cfg_command(4),
      cfg_command(3) => NlwRenamedSig_OI_cfg_command(3),
      cfg_command(2) => NlwRenamedSig_OI_cfg_command(2),
      cfg_command(1) => NlwRenamedSig_OI_cfg_command(1),
      cfg_command(0) => NlwRenamedSig_OI_cfg_command(0),
      cfg_lstatus(15) => cfg_lstatus(15),
      cfg_lstatus(14) => cfg_lstatus(14),
      cfg_lstatus(13) => cfg_lstatus(13),
      cfg_lstatus(12) => cfg_lstatus(12),
      cfg_lstatus(11) => cfg_lstatus(11),
      cfg_lstatus(10) => cfg_lstatus(10),
      cfg_lstatus(9) => cfg_lstatus(9),
      cfg_lstatus(8) => cfg_lstatus(8),
      cfg_lstatus(7) => cfg_lstatus(7),
      cfg_lstatus(6) => cfg_lstatus(6),
      cfg_lstatus(5) => cfg_lstatus(5),
      cfg_lstatus(4) => cfg_lstatus(4),
      cfg_lstatus(3) => cfg_lstatus(3),
      cfg_lstatus(2) => cfg_lstatus(2),
      cfg_lstatus(1) => cfg_lstatus(1),
      cfg_lstatus(0) => cfg_lstatus(0),
      cfg_msgctrl(15) => cfg_msgctrl(15),
      cfg_msgctrl(14) => cfg_msgctrl(14),
      cfg_msgctrl(13) => cfg_msgctrl(13),
      cfg_msgctrl(12) => cfg_msgctrl(12),
      cfg_msgctrl(11) => cfg_msgctrl(11),
      cfg_msgctrl(10) => cfg_msgctrl(10),
      cfg_msgctrl(9) => cfg_msgctrl(9),
      cfg_msgctrl(8) => cfg_msgctrl(8),
      cfg_msgctrl(7) => cfg_msgctrl(7),
      cfg_msgctrl(6) => cfg_msgctrl(6),
      cfg_msgctrl(5) => cfg_msgctrl(5),
      cfg_msgctrl(4) => cfg_msgctrl(4),
      cfg_msgctrl(3) => cfg_msgctrl(3),
      cfg_msgctrl(2) => cfg_msgctrl(2),
      cfg_msgctrl(1) => cfg_msgctrl(1),
      cfg_msgctrl(0) => cfg_msgctrl(0),
      cfg_dcommand(15) => NlwRenamedSig_OI_cfg_dcommand(15),
      cfg_dcommand(14) => NlwRenamedSig_OI_cfg_dcommand(14),
      cfg_dcommand(13) => NlwRenamedSig_OI_cfg_dcommand(13),
      cfg_dcommand(12) => NlwRenamedSig_OI_cfg_dcommand(12),
      cfg_dcommand(11) => NlwRenamedSig_OI_cfg_dcommand(11),
      cfg_dcommand(10) => NlwRenamedSig_OI_cfg_dcommand(10),
      cfg_dcommand(9) => NlwRenamedSig_OI_cfg_dcommand(9),
      cfg_dcommand(8) => NlwRenamedSig_OI_cfg_dcommand(8),
      cfg_dcommand(7) => NlwRenamedSig_OI_cfg_dcommand(7),
      cfg_dcommand(6) => NlwRenamedSig_OI_cfg_dcommand(6),
      cfg_dcommand(5) => NlwRenamedSig_OI_cfg_dcommand(5),
      cfg_dcommand(4) => NlwRenamedSig_OI_cfg_dcommand(4),
      cfg_dcommand(3) => NlwRenamedSig_OI_cfg_dcommand(3),
      cfg_dcommand(2) => NlwRenamedSig_OI_cfg_dcommand(2),
      cfg_dcommand(1) => NlwRenamedSig_OI_cfg_dcommand(1),
      cfg_dcommand(0) => NlwRenamedSig_OI_cfg_dcommand(0),
      cfg_msgladdr(31) => cfg_msgladdr(31),
      cfg_msgladdr(30) => cfg_msgladdr(30),
      cfg_msgladdr(29) => cfg_msgladdr(29),
      cfg_msgladdr(28) => cfg_msgladdr(28),
      cfg_msgladdr(27) => cfg_msgladdr(27),
      cfg_msgladdr(26) => cfg_msgladdr(26),
      cfg_msgladdr(25) => cfg_msgladdr(25),
      cfg_msgladdr(24) => cfg_msgladdr(24),
      cfg_msgladdr(23) => cfg_msgladdr(23),
      cfg_msgladdr(22) => cfg_msgladdr(22),
      cfg_msgladdr(21) => cfg_msgladdr(21),
      cfg_msgladdr(20) => cfg_msgladdr(20),
      cfg_msgladdr(19) => cfg_msgladdr(19),
      cfg_msgladdr(18) => cfg_msgladdr(18),
      cfg_msgladdr(17) => cfg_msgladdr(17),
      cfg_msgladdr(16) => cfg_msgladdr(16),
      cfg_msgladdr(15) => cfg_msgladdr(15),
      cfg_msgladdr(14) => cfg_msgladdr(14),
      cfg_msgladdr(13) => cfg_msgladdr(13),
      cfg_msgladdr(12) => cfg_msgladdr(12),
      cfg_msgladdr(11) => cfg_msgladdr(11),
      cfg_msgladdr(10) => cfg_msgladdr(10),
      cfg_msgladdr(9) => cfg_msgladdr(9),
      cfg_msgladdr(8) => cfg_msgladdr(8),
      cfg_msgladdr(7) => cfg_msgladdr(7),
      cfg_msgladdr(6) => cfg_msgladdr(6),
      cfg_msgladdr(5) => cfg_msgladdr(5),
      cfg_msgladdr(4) => cfg_msgladdr(4),
      cfg_msgladdr(3) => cfg_msgladdr(3),
      cfg_msgladdr(2) => cfg_msgladdr(2),
      cfg_msgladdr(1) => cfg_msgladdr(1),
      cfg_msgladdr(0) => cfg_msgladdr(0),
      cfg_msgdata(15) => cfg_msgdata(15),
      cfg_msgdata(14) => cfg_msgdata(14),
      cfg_msgdata(13) => cfg_msgdata(13),
      cfg_msgdata(12) => cfg_msgdata(12),
      cfg_msgdata(11) => cfg_msgdata(11),
      cfg_msgdata(10) => cfg_msgdata(10),
      cfg_msgdata(9) => cfg_msgdata(9),
      cfg_msgdata(8) => cfg_msgdata(8),
      cfg_msgdata(7) => cfg_msgdata(7),
      cfg_msgdata(6) => cfg_msgdata(6),
      cfg_msgdata(5) => cfg_msgdata(5),
      cfg_msgdata(4) => cfg_msgdata(4),
      cfg_msgdata(3) => cfg_msgdata(3),
      cfg_msgdata(2) => cfg_msgdata(2),
      cfg_msgdata(1) => cfg_msgdata(1),
      cfg_msgdata(0) => cfg_msgdata(0),
      cfg_function_number(2) => NlwRenamedSig_OI_cfg_function_number(2),
      cfg_function_number(1) => NlwRenamedSig_OI_cfg_function_number(1),
      cfg_function_number(0) => NlwRenamedSig_OI_cfg_function_number(0),
      cfg_rx_bar0(31) => cfg_rx_bar0(31),
      cfg_rx_bar0(30) => cfg_rx_bar0(30),
      cfg_rx_bar0(29) => cfg_rx_bar0(29),
      cfg_rx_bar0(28) => cfg_rx_bar0(28),
      cfg_rx_bar0(27) => cfg_rx_bar0(27),
      cfg_rx_bar0(26) => cfg_rx_bar0(26),
      cfg_rx_bar0(25) => cfg_rx_bar0(25),
      cfg_rx_bar0(24) => cfg_rx_bar0(24),
      cfg_rx_bar0(23) => cfg_rx_bar0(23),
      cfg_rx_bar0(22) => cfg_rx_bar0(22),
      cfg_rx_bar0(21) => cfg_rx_bar0(21),
      cfg_rx_bar0(20) => cfg_rx_bar0(20),
      cfg_rx_bar0(19) => cfg_rx_bar0(19),
      cfg_rx_bar0(18) => cfg_rx_bar0(18),
      cfg_rx_bar0(17) => cfg_rx_bar0(17),
      cfg_rx_bar0(16) => cfg_rx_bar0(16),
      cfg_rx_bar0(15) => cfg_rx_bar0(15),
      cfg_rx_bar0(14) => cfg_rx_bar0(14),
      cfg_rx_bar0(13) => cfg_rx_bar0(13),
      cfg_rx_bar0(12) => cfg_rx_bar0(12),
      cfg_rx_bar0(11) => cfg_rx_bar0(11),
      cfg_rx_bar0(10) => cfg_rx_bar0(10),
      cfg_rx_bar0(9) => cfg_rx_bar0(9),
      cfg_rx_bar0(8) => cfg_rx_bar0(8),
      cfg_rx_bar0(7) => cfg_rx_bar0(7),
      cfg_rx_bar0(6) => cfg_rx_bar0(6),
      cfg_rx_bar0(5) => cfg_rx_bar0(5),
      cfg_rx_bar0(4) => cfg_rx_bar0(4),
      cfg_rx_bar0(3) => cfg_rx_bar0(3),
      cfg_rx_bar0(2) => cfg_rx_bar0(2),
      cfg_rx_bar0(1) => cfg_rx_bar0(1),
      cfg_rx_bar0(0) => cfg_rx_bar0(0),
      mgmt_wdata(31) => mgmt_wdata(31),
      mgmt_wdata(30) => mgmt_wdata(30),
      mgmt_wdata(29) => mgmt_wdata(29),
      mgmt_wdata(28) => mgmt_wdata(28),
      mgmt_wdata(27) => mgmt_wdata(27),
      mgmt_wdata(26) => mgmt_wdata(26),
      mgmt_wdata(25) => mgmt_wdata(25),
      mgmt_wdata(24) => mgmt_wdata(24),
      mgmt_wdata(23) => mgmt_wdata(23),
      mgmt_wdata(22) => mgmt_wdata(22),
      mgmt_wdata(21) => mgmt_wdata(21),
      mgmt_wdata(20) => mgmt_wdata(20),
      mgmt_wdata(19) => mgmt_wdata(19),
      mgmt_wdata(18) => mgmt_wdata(18),
      mgmt_wdata(17) => mgmt_wdata(17),
      mgmt_wdata(16) => mgmt_wdata(16),
      mgmt_wdata(15) => mgmt_wdata(15),
      mgmt_wdata(14) => mgmt_wdata(14),
      mgmt_wdata(13) => mgmt_wdata(13),
      mgmt_wdata(12) => mgmt_wdata(12),
      mgmt_wdata(11) => mgmt_wdata(11),
      mgmt_wdata(10) => mgmt_wdata(10),
      mgmt_wdata(9) => mgmt_wdata(9),
      mgmt_wdata(8) => mgmt_wdata(8),
      mgmt_wdata(7) => mgmt_wdata(7),
      mgmt_wdata(6) => mgmt_wdata(6),
      mgmt_wdata(5) => mgmt_wdata(5),
      mgmt_wdata(4) => mgmt_wdata(4),
      mgmt_wdata(3) => mgmt_wdata(3),
      mgmt_wdata(2) => mgmt_wdata(2),
      mgmt_wdata(1) => mgmt_wdata(1),
      mgmt_wdata(0) => mgmt_wdata(0),
      cfg_rx_bar1(31) => cfg_rx_bar1(31),
      cfg_rx_bar1(30) => cfg_rx_bar1(30),
      cfg_rx_bar1(29) => cfg_rx_bar1(29),
      cfg_rx_bar1(28) => cfg_rx_bar1(28),
      cfg_rx_bar1(27) => cfg_rx_bar1(27),
      cfg_rx_bar1(26) => cfg_rx_bar1(26),
      cfg_rx_bar1(25) => cfg_rx_bar1(25),
      cfg_rx_bar1(24) => cfg_rx_bar1(24),
      cfg_rx_bar1(23) => cfg_rx_bar1(23),
      cfg_rx_bar1(22) => cfg_rx_bar1(22),
      cfg_rx_bar1(21) => cfg_rx_bar1(21),
      cfg_rx_bar1(20) => cfg_rx_bar1(20),
      cfg_rx_bar1(19) => cfg_rx_bar1(19),
      cfg_rx_bar1(18) => cfg_rx_bar1(18),
      cfg_rx_bar1(17) => cfg_rx_bar1(17),
      cfg_rx_bar1(16) => cfg_rx_bar1(16),
      cfg_rx_bar1(15) => cfg_rx_bar1(15),
      cfg_rx_bar1(14) => cfg_rx_bar1(14),
      cfg_rx_bar1(13) => cfg_rx_bar1(13),
      cfg_rx_bar1(12) => cfg_rx_bar1(12),
      cfg_rx_bar1(11) => cfg_rx_bar1(11),
      cfg_rx_bar1(10) => cfg_rx_bar1(10),
      cfg_rx_bar1(9) => cfg_rx_bar1(9),
      cfg_rx_bar1(8) => cfg_rx_bar1(8),
      cfg_rx_bar1(7) => cfg_rx_bar1(7),
      cfg_rx_bar1(6) => cfg_rx_bar1(6),
      cfg_rx_bar1(5) => cfg_rx_bar1(5),
      cfg_rx_bar1(4) => cfg_rx_bar1(4),
      cfg_rx_bar1(3) => cfg_rx_bar1(3),
      cfg_rx_bar1(2) => cfg_rx_bar1(2),
      cfg_rx_bar1(1) => cfg_rx_bar1(1),
      cfg_rx_bar1(0) => cfg_rx_bar1(0),
      cfg_rx_bar2(31) => cfg_rx_bar2(31),
      cfg_rx_bar2(30) => cfg_rx_bar2(30),
      cfg_rx_bar2(29) => cfg_rx_bar2(29),
      cfg_rx_bar2(28) => cfg_rx_bar2(28),
      cfg_rx_bar2(27) => cfg_rx_bar2(27),
      cfg_rx_bar2(26) => cfg_rx_bar2(26),
      cfg_rx_bar2(25) => cfg_rx_bar2(25),
      cfg_rx_bar2(24) => cfg_rx_bar2(24),
      cfg_rx_bar2(23) => cfg_rx_bar2(23),
      cfg_rx_bar2(22) => cfg_rx_bar2(22),
      cfg_rx_bar2(21) => cfg_rx_bar2(21),
      cfg_rx_bar2(20) => cfg_rx_bar2(20),
      cfg_rx_bar2(19) => cfg_rx_bar2(19),
      cfg_rx_bar2(18) => cfg_rx_bar2(18),
      cfg_rx_bar2(17) => cfg_rx_bar2(17),
      cfg_rx_bar2(16) => cfg_rx_bar2(16),
      cfg_rx_bar2(15) => cfg_rx_bar2(15),
      cfg_rx_bar2(14) => cfg_rx_bar2(14),
      cfg_rx_bar2(13) => cfg_rx_bar2(13),
      cfg_rx_bar2(12) => cfg_rx_bar2(12),
      cfg_rx_bar2(11) => cfg_rx_bar2(11),
      cfg_rx_bar2(10) => cfg_rx_bar2(10),
      cfg_rx_bar2(9) => cfg_rx_bar2(9),
      cfg_rx_bar2(8) => cfg_rx_bar2(8),
      cfg_rx_bar2(7) => cfg_rx_bar2(7),
      cfg_rx_bar2(6) => cfg_rx_bar2(6),
      cfg_rx_bar2(5) => cfg_rx_bar2(5),
      cfg_rx_bar2(4) => cfg_rx_bar2(4),
      cfg_rx_bar2(3) => cfg_rx_bar2(3),
      cfg_rx_bar2(2) => cfg_rx_bar2(2),
      cfg_rx_bar2(1) => cfg_rx_bar2(1),
      cfg_rx_bar2(0) => cfg_rx_bar2(0),
      cfg_rx_bar3(31) => cfg_rx_bar3(31),
      cfg_rx_bar3(30) => cfg_rx_bar3(30),
      cfg_rx_bar3(29) => cfg_rx_bar3(29),
      cfg_rx_bar3(28) => cfg_rx_bar3(28),
      cfg_rx_bar3(27) => cfg_rx_bar3(27),
      cfg_rx_bar3(26) => cfg_rx_bar3(26),
      cfg_rx_bar3(25) => cfg_rx_bar3(25),
      cfg_rx_bar3(24) => cfg_rx_bar3(24),
      cfg_rx_bar3(23) => cfg_rx_bar3(23),
      cfg_rx_bar3(22) => cfg_rx_bar3(22),
      cfg_rx_bar3(21) => cfg_rx_bar3(21),
      cfg_rx_bar3(20) => cfg_rx_bar3(20),
      cfg_rx_bar3(19) => cfg_rx_bar3(19),
      cfg_rx_bar3(18) => cfg_rx_bar3(18),
      cfg_rx_bar3(17) => cfg_rx_bar3(17),
      cfg_rx_bar3(16) => cfg_rx_bar3(16),
      cfg_rx_bar3(15) => cfg_rx_bar3(15),
      cfg_rx_bar3(14) => cfg_rx_bar3(14),
      cfg_rx_bar3(13) => cfg_rx_bar3(13),
      cfg_rx_bar3(12) => cfg_rx_bar3(12),
      cfg_rx_bar3(11) => cfg_rx_bar3(11),
      cfg_rx_bar3(10) => cfg_rx_bar3(10),
      cfg_rx_bar3(9) => cfg_rx_bar3(9),
      cfg_rx_bar3(8) => cfg_rx_bar3(8),
      cfg_rx_bar3(7) => cfg_rx_bar3(7),
      cfg_rx_bar3(6) => cfg_rx_bar3(6),
      cfg_rx_bar3(5) => cfg_rx_bar3(5),
      cfg_rx_bar3(4) => cfg_rx_bar3(4),
      cfg_rx_bar3(3) => cfg_rx_bar3(3),
      cfg_rx_bar3(2) => cfg_rx_bar3(2),
      cfg_rx_bar3(1) => cfg_rx_bar3(1),
      cfg_rx_bar3(0) => cfg_rx_bar3(0),
      cfg_rx_bar4(31) => cfg_rx_bar4(31),
      cfg_rx_bar4(30) => cfg_rx_bar4(30),
      cfg_rx_bar4(29) => cfg_rx_bar4(29),
      cfg_rx_bar4(28) => cfg_rx_bar4(28),
      cfg_rx_bar4(27) => cfg_rx_bar4(27),
      cfg_rx_bar4(26) => cfg_rx_bar4(26),
      cfg_rx_bar4(25) => cfg_rx_bar4(25),
      cfg_rx_bar4(24) => cfg_rx_bar4(24),
      cfg_rx_bar4(23) => cfg_rx_bar4(23),
      cfg_rx_bar4(22) => cfg_rx_bar4(22),
      cfg_rx_bar4(21) => cfg_rx_bar4(21),
      cfg_rx_bar4(20) => cfg_rx_bar4(20),
      cfg_rx_bar4(19) => cfg_rx_bar4(19),
      cfg_rx_bar4(18) => cfg_rx_bar4(18),
      cfg_rx_bar4(17) => cfg_rx_bar4(17),
      cfg_rx_bar4(16) => cfg_rx_bar4(16),
      cfg_rx_bar4(15) => cfg_rx_bar4(15),
      cfg_rx_bar4(14) => cfg_rx_bar4(14),
      cfg_rx_bar4(13) => cfg_rx_bar4(13),
      cfg_rx_bar4(12) => cfg_rx_bar4(12),
      cfg_rx_bar4(11) => cfg_rx_bar4(11),
      cfg_rx_bar4(10) => cfg_rx_bar4(10),
      cfg_rx_bar4(9) => cfg_rx_bar4(9),
      cfg_rx_bar4(8) => cfg_rx_bar4(8),
      cfg_rx_bar4(7) => cfg_rx_bar4(7),
      cfg_rx_bar4(6) => cfg_rx_bar4(6),
      cfg_rx_bar4(5) => cfg_rx_bar4(5),
      cfg_rx_bar4(4) => cfg_rx_bar4(4),
      cfg_rx_bar4(3) => cfg_rx_bar4(3),
      cfg_rx_bar4(2) => cfg_rx_bar4(2),
      cfg_rx_bar4(1) => cfg_rx_bar4(1),
      cfg_rx_bar4(0) => cfg_rx_bar4(0),
      cfg_rx_bar5(31) => cfg_rx_bar5(31),
      cfg_rx_bar5(30) => cfg_rx_bar5(30),
      cfg_rx_bar5(29) => cfg_rx_bar5(29),
      cfg_rx_bar5(28) => cfg_rx_bar5(28),
      cfg_rx_bar5(27) => cfg_rx_bar5(27),
      cfg_rx_bar5(26) => cfg_rx_bar5(26),
      cfg_rx_bar5(25) => cfg_rx_bar5(25),
      cfg_rx_bar5(24) => cfg_rx_bar5(24),
      cfg_rx_bar5(23) => cfg_rx_bar5(23),
      cfg_rx_bar5(22) => cfg_rx_bar5(22),
      cfg_rx_bar5(21) => cfg_rx_bar5(21),
      cfg_rx_bar5(20) => cfg_rx_bar5(20),
      cfg_rx_bar5(19) => cfg_rx_bar5(19),
      cfg_rx_bar5(18) => cfg_rx_bar5(18),
      cfg_rx_bar5(17) => cfg_rx_bar5(17),
      cfg_rx_bar5(16) => cfg_rx_bar5(16),
      cfg_rx_bar5(15) => cfg_rx_bar5(15),
      cfg_rx_bar5(14) => cfg_rx_bar5(14),
      cfg_rx_bar5(13) => cfg_rx_bar5(13),
      cfg_rx_bar5(12) => cfg_rx_bar5(12),
      cfg_rx_bar5(11) => cfg_rx_bar5(11),
      cfg_rx_bar5(10) => cfg_rx_bar5(10),
      cfg_rx_bar5(9) => cfg_rx_bar5(9),
      cfg_rx_bar5(8) => cfg_rx_bar5(8),
      cfg_rx_bar5(7) => cfg_rx_bar5(7),
      cfg_rx_bar5(6) => cfg_rx_bar5(6),
      cfg_rx_bar5(5) => cfg_rx_bar5(5),
      cfg_rx_bar5(4) => cfg_rx_bar5(4),
      cfg_rx_bar5(3) => cfg_rx_bar5(3),
      cfg_rx_bar5(2) => cfg_rx_bar5(2),
      cfg_rx_bar5(1) => cfg_rx_bar5(1),
      cfg_rx_bar5(0) => cfg_rx_bar5(0),
      cfg_do(31) => cfg_do(31),
      cfg_do(30) => cfg_do(30),
      cfg_do(29) => cfg_do(29),
      cfg_do(28) => cfg_do(28),
      cfg_do(27) => cfg_do(27),
      cfg_do(26) => cfg_do(26),
      cfg_do(25) => cfg_do(25),
      cfg_do(24) => cfg_do(24),
      cfg_do(23) => cfg_do(23),
      cfg_do(22) => cfg_do(22),
      cfg_do(21) => cfg_do(21),
      cfg_do(20) => cfg_do(20),
      cfg_do(19) => cfg_do(19),
      cfg_do(18) => cfg_do(18),
      cfg_do(17) => cfg_do(17),
      cfg_do(16) => cfg_do(16),
      cfg_do(15) => cfg_do(15),
      cfg_do(14) => cfg_do(14),
      cfg_do(13) => cfg_do(13),
      cfg_do(12) => cfg_do(12),
      cfg_do(11) => cfg_do(11),
      cfg_do(10) => cfg_do(10),
      cfg_do(9) => cfg_do(9),
      cfg_do(8) => cfg_do(8),
      cfg_do(7) => cfg_do(7),
      cfg_do(6) => cfg_do(6),
      cfg_do(5) => cfg_do(5),
      cfg_do(4) => cfg_do(4),
      cfg_do(3) => cfg_do(3),
      cfg_do(2) => cfg_do(2),
      cfg_do(1) => cfg_do(1),
      cfg_do(0) => cfg_do(0),
      mgmt_pso(16) => mgmt_pso(16),
      mgmt_pso(15) => mgmt_pso(15),
      mgmt_pso(14) => mgmt_pso(14),
      mgmt_pso(13) => mgmt_pso(13),
      mgmt_pso(12) => mgmt_pso(12),
      mgmt_pso(11) => mgmt_pso(11),
      mgmt_pso(10) => mgmt_pso(10),
      mgmt_pso(9) => mgmt_pso(9),
      mgmt_pso(8) => mgmt_pso(8),
      mgmt_pso(7) => mgmt_pso(7),
      mgmt_pso(6) => mgmt_pso(6),
      mgmt_pso(5) => mgmt_pso(5),
      mgmt_pso(4) => mgmt_pso(4),
      mgmt_pso(3) => mgmt_pso(3),
      mgmt_pso(2) => mgmt_pso(2),
      mgmt_pso(1) => mgmt_pso(1),
      mgmt_pso(0) => mgmt_pso(0),
      l0_dll_error_vector(6) => l0_dll_error_vector(6),
      l0_dll_error_vector(5) => l0_dll_error_vector(5),
      l0_dll_error_vector(4) => l0_dll_error_vector(4),
      l0_dll_error_vector(3) => l0_dll_error_vector(3),
      l0_dll_error_vector(2) => l0_dll_error_vector(2),
      l0_dll_error_vector(1) => l0_dll_error_vector(1),
      l0_dll_error_vector(0) => l0_dll_error_vector(0),
      completer_id(12) => completer_id_reg(12),
      completer_id(11) => completer_id_reg(11),
      completer_id(10) => completer_id_reg(10),
      completer_id(9) => completer_id_reg(9),
      completer_id(8) => completer_id_reg(8),
      completer_id(7) => completer_id_reg(7),
      completer_id(6) => completer_id_reg(6),
      completer_id(5) => completer_id_reg(5),
      completer_id(4) => completer_id_reg(4),
      completer_id(3) => completer_id_reg(3),
      completer_id(2) => completer_id_reg(2),
      completer_id(1) => completer_id_reg(1),
      completer_id(0) => completer_id_reg(0),
      l0_rx_mac_link_error(1) => l0_rx_mac_link_error(1),
      l0_rx_mac_link_error(0) => l0_rx_mac_link_error(0),
      cfg_dsn(63) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(62) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(61) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(60) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(59) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(58) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(57) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(56) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(55) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(54) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(53) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(52) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(51) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(50) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(49) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(48) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(47) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(46) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(45) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(44) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(43) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(42) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(41) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(40) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(39) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(38) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(37) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(36) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(35) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(34) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(33) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(32) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(31) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(30) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(29) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(28) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(27) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(26) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(25) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(24) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(23) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(22) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(21) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(20) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(19) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(18) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(17) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(16) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(15) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(14) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(13) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(12) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(11) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(10) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(9) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(8) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(7) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(6) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(5) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(4) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(3) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(2) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(1) => NlwRenamedSig_OI_transactions_pending,
      cfg_dsn(0) => NlwRenamedSig_OI_transactions_pending,
      cfg_dwaddr(11) => cfg_dwaddr(11),
      cfg_dwaddr(10) => cfg_dwaddr(10),
      cfg_dwaddr(9) => cfg_dwaddr(9),
      cfg_dwaddr(8) => cfg_dwaddr(8),
      cfg_dwaddr(7) => cfg_dwaddr(7),
      cfg_dwaddr(6) => cfg_dwaddr(6),
      cfg_dwaddr(5) => cfg_dwaddr(5),
      cfg_dwaddr(4) => cfg_dwaddr(4),
      cfg_dwaddr(3) => cfg_dwaddr(3),
      cfg_dwaddr(2) => cfg_dwaddr(2),
      cfg_dwaddr(1) => cfg_dwaddr(1),
      cfg_dwaddr(0) => cfg_dwaddr(0),
      llk_rx_data_d(63) => llk_rx_data_d(63),
      llk_rx_data_d(62) => llk_rx_data_d(62),
      llk_rx_data_d(61) => llk_rx_data_d(61),
      llk_rx_data_d(60) => llk_rx_data_d(60),
      llk_rx_data_d(59) => llk_rx_data_d(59),
      llk_rx_data_d(58) => llk_rx_data_d(58),
      llk_rx_data_d(57) => llk_rx_data_d(57),
      llk_rx_data_d(56) => llk_rx_data_d(56),
      llk_rx_data_d(55) => llk_rx_data_d(55),
      llk_rx_data_d(54) => llk_rx_data_d(54),
      llk_rx_data_d(53) => llk_rx_data_d(53),
      llk_rx_data_d(52) => llk_rx_data_d(52),
      llk_rx_data_d(51) => llk_rx_data_d(51),
      llk_rx_data_d(50) => llk_rx_data_d(50),
      llk_rx_data_d(49) => llk_rx_data_d(49),
      llk_rx_data_d(48) => llk_rx_data_d(48),
      llk_rx_data_d(47) => llk_rx_data_d(47),
      llk_rx_data_d(46) => llk_rx_data_d(46),
      llk_rx_data_d(45) => llk_rx_data_d(45),
      llk_rx_data_d(44) => llk_rx_data_d(44),
      llk_rx_data_d(43) => llk_rx_data_d(43),
      llk_rx_data_d(42) => llk_rx_data_d(42),
      llk_rx_data_d(41) => llk_rx_data_d(41),
      llk_rx_data_d(40) => llk_rx_data_d(40),
      llk_rx_data_d(39) => llk_rx_data_d(39),
      llk_rx_data_d(38) => llk_rx_data_d(38),
      llk_rx_data_d(37) => llk_rx_data_d(37),
      llk_rx_data_d(36) => llk_rx_data_d(36),
      llk_rx_data_d(35) => llk_rx_data_d(35),
      llk_rx_data_d(34) => llk_rx_data_d(34),
      llk_rx_data_d(33) => llk_rx_data_d(33),
      llk_rx_data_d(32) => llk_rx_data_d(32),
      llk_rx_data_d(31) => llk_rx_data_d(31),
      llk_rx_data_d(30) => llk_rx_data_d(30),
      llk_rx_data_d(29) => llk_rx_data_d(29),
      llk_rx_data_d(28) => llk_rx_data_d(28),
      llk_rx_data_d(27) => llk_rx_data_d(27),
      llk_rx_data_d(26) => llk_rx_data_d(26),
      llk_rx_data_d(25) => llk_rx_data_d(25),
      llk_rx_data_d(24) => llk_rx_data_d(24),
      llk_rx_data_d(23) => llk_rx_data_d(23),
      llk_rx_data_d(22) => llk_rx_data_d(22),
      llk_rx_data_d(21) => llk_rx_data_d(21),
      llk_rx_data_d(20) => llk_rx_data_d(20),
      llk_rx_data_d(19) => llk_rx_data_d(19),
      llk_rx_data_d(18) => llk_rx_data_d(18),
      llk_rx_data_d(17) => llk_rx_data_d(17),
      llk_rx_data_d(16) => llk_rx_data_d(16),
      llk_rx_data_d(15) => llk_rx_data_d(15),
      llk_rx_data_d(14) => llk_rx_data_d(14),
      llk_rx_data_d(13) => llk_rx_data_d(13),
      llk_rx_data_d(12) => llk_rx_data_d(12),
      llk_rx_data_d(11) => llk_rx_data_d(11),
      llk_rx_data_d(10) => llk_rx_data_d(10),
      llk_rx_data_d(9) => llk_rx_data_d(9),
      llk_rx_data_d(8) => llk_rx_data_d(8),
      llk_rx_data_d(7) => llk_rx_data_d(7),
      llk_rx_data_d(6) => llk_rx_data_d(6),
      llk_rx_data_d(5) => llk_rx_data_d(5),
      llk_rx_data_d(4) => llk_rx_data_d(4),
      llk_rx_data_d(3) => llk_rx_data_d(3),
      llk_rx_data_d(2) => llk_rx_data_d(2),
      llk_rx_data_d(1) => llk_rx_data_d(1),
      llk_rx_data_d(0) => llk_rx_data_d(0),
      mgmt_rdata(31) => mgmt_rdata(31),
      mgmt_rdata(30) => mgmt_rdata(30),
      mgmt_rdata(29) => mgmt_rdata(29),
      mgmt_rdata(28) => mgmt_rdata(28),
      mgmt_rdata(27) => mgmt_rdata(27),
      mgmt_rdata(26) => mgmt_rdata(26),
      mgmt_rdata(25) => mgmt_rdata(25),
      mgmt_rdata(24) => mgmt_rdata(24),
      mgmt_rdata(23) => mgmt_rdata(23),
      mgmt_rdata(22) => mgmt_rdata(22),
      mgmt_rdata(21) => mgmt_rdata(21),
      mgmt_rdata(20) => mgmt_rdata(20),
      mgmt_rdata(19) => mgmt_rdata(19),
      mgmt_rdata(18) => mgmt_rdata(18),
      mgmt_rdata(17) => mgmt_rdata(17),
      mgmt_rdata(16) => mgmt_rdata(16),
      mgmt_rdata(15) => mgmt_rdata(15),
      mgmt_rdata(14) => mgmt_rdata(14),
      mgmt_rdata(13) => mgmt_rdata(13),
      mgmt_rdata(12) => mgmt_rdata(12),
      mgmt_rdata(11) => mgmt_rdata(11),
      mgmt_rdata(10) => mgmt_rdata(10),
      mgmt_rdata(9) => mgmt_rdata(9),
      mgmt_rdata(8) => mgmt_rdata(8),
      mgmt_rdata(7) => mgmt_rdata(7),
      mgmt_rdata(6) => mgmt_rdata(6),
      mgmt_rdata(5) => mgmt_rdata(5),
      mgmt_rdata(4) => mgmt_rdata(4),
      mgmt_rdata(3) => mgmt_rdata(3),
      mgmt_rdata(2) => mgmt_rdata(2),
      mgmt_rdata(1) => mgmt_rdata(1),
      mgmt_rdata(0) => mgmt_rdata(0)
    );
  error_manager : pcie_blk_cf_err
    port map (
      rx_err_cpl_ur_n => rx_err_cpl_ur_n,
      l0_set_user_system_error => l0_set_user_system_error,
      clk => clk,
      cs_is_nfl => cs_is_nfl,
      rx_err_tlp_ur_lock_n => rx_err_tlp_ur_lock_n,
      rst_n => rst_n,
      cfg_err_cpl_abort_n => NLW_error_manager_cfg_err_cpl_abort_n_UNCONNECTED,
      l0_set_user_received_master_abort => l0_set_user_received_master_abort,
      l0_set_detected_nonfatal_error => l0_set_detected_nonfatal_error,
      cfg_err_cpl_unexpect_n => NLW_error_manager_cfg_err_cpl_unexpect_n_UNCONNECTED,
      l0_set_detected_corr_error => NlwRenamedSig_OI_l0_set_detected_corr_error,
      send_ftl => send_ftl,
      cfg_err_ecrc_n => NLW_error_manager_cfg_err_ecrc_n_UNCONNECTED,
      send_cplt => send_cplt,
      send_cplu => send_cplu,
      cs_is_ftl => cs_is_ftl,
      rx_err_cpl_ep_n => rx_err_cpl_ep_n,
      rx_err_tlp_ur_n => rx_err_tlp_ur_n,
      l0_set_user_master_data_parity => l0_set_user_master_data_parity,
      cfg_err_locked_n => NLW_error_manager_cfg_err_locked_n_UNCONNECTED,
      l0_mac_link_up => mac_link_up,
      l0_set_user_detected_parity_error => l0_set_user_detected_parity_error,
      l0_set_user_signaled_target_abort => l0_set_user_signaled_target_abort,
      l0_set_detected_fatal_error => l0_set_detected_fatal_error,
      tx_err_wr_ep_n => tx_err_wr_ep_n,
      rx_err_tlp_malformed_n => rx_err_tlp_malformed_n,
      rx_err_tlp_p_cpl_n => rx_err_tlp_p_cpl_n,
      cfg_err_cpl_timeout_n => NLW_error_manager_cfg_err_cpl_timeout_n_UNCONNECTED,
      cfg_err_ur_n => NLW_error_manager_cfg_err_ur_n_UNCONNECTED,
      rx_err_cpl_abort_n => rx_err_cpl_abort_n,
      send_cor => send_cor,
      cfg_err_posted_n => NlwRenamedSig_OI_transactions_pending,
      rx_err_ep_n => rx_err_ep_n,
      l0_set_unsupported_request_other_error => NlwRenamedSig_OI_l0_set_unsupported_request_other_error,
      cs_is_cplt => cs_is_cplt,
      cs_is_cplu => cs_is_cplu,
      cs_is_cor => cs_is_cor,
      cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
      l0_set_user_received_target_abort => l0_set_user_received_target_abort,
      grant => grant,
      rx_err_tlp_poisoned_n => NLW_error_manager_rx_err_tlp_poisoned_n_UNCONNECTED,
      send_nfl => send_nfl,
      serr_en => serr_enable,
      cfg_err_cor_n => NLW_error_manager_cfg_err_cor_n_UNCONNECTED,
      cfg_rd_hdr(49) => cfg_rd_hdr(49),
      cfg_rd_hdr(48) => cfg_rd_hdr(48),
      cfg_rd_hdr(47) => cfg_rd_hdr(47),
      cfg_rd_hdr(46) => cfg_rd_hdr(46),
      cfg_rd_hdr(45) => cfg_rd_hdr(45),
      cfg_rd_hdr(44) => cfg_rd_hdr(44),
      cfg_rd_hdr(43) => cfg_rd_hdr(43),
      cfg_rd_hdr(42) => cfg_rd_hdr(42),
      cfg_rd_hdr(41) => cfg_rd_hdr(41),
      cfg_rd_hdr(40) => cfg_rd_hdr(40),
      cfg_rd_hdr(39) => cfg_rd_hdr(39),
      cfg_rd_hdr(38) => cfg_rd_hdr(38),
      cfg_rd_hdr(37) => cfg_rd_hdr(37),
      cfg_rd_hdr(36) => cfg_rd_hdr(36),
      cfg_rd_hdr(35) => cfg_rd_hdr(35),
      cfg_rd_hdr(34) => cfg_rd_hdr(34),
      cfg_rd_hdr(33) => cfg_rd_hdr(33),
      cfg_rd_hdr(32) => cfg_rd_hdr(32),
      cfg_rd_hdr(31) => cfg_rd_hdr(31),
      cfg_rd_hdr(30) => cfg_rd_hdr(30),
      cfg_rd_hdr(29) => cfg_rd_hdr(29),
      cfg_rd_hdr(28) => cfg_rd_hdr(28),
      cfg_rd_hdr(27) => cfg_rd_hdr(27),
      cfg_rd_hdr(26) => cfg_rd_hdr(26),
      cfg_rd_hdr(25) => cfg_rd_hdr(25),
      cfg_rd_hdr(24) => cfg_rd_hdr(24),
      cfg_rd_hdr(23) => cfg_rd_hdr(23),
      cfg_rd_hdr(22) => cfg_rd_hdr(22),
      cfg_rd_hdr(21) => cfg_rd_hdr(21),
      cfg_rd_hdr(20) => cfg_rd_hdr(20),
      cfg_rd_hdr(19) => cfg_rd_hdr(19),
      cfg_rd_hdr(18) => cfg_rd_hdr(18),
      cfg_rd_hdr(17) => cfg_rd_hdr(17),
      cfg_rd_hdr(16) => cfg_rd_hdr(16),
      cfg_rd_hdr(15) => cfg_rd_hdr(15),
      cfg_rd_hdr(14) => cfg_rd_hdr(14),
      cfg_rd_hdr(13) => cfg_rd_hdr(13),
      cfg_rd_hdr(12) => cfg_rd_hdr(12),
      cfg_rd_hdr(11) => cfg_rd_hdr(11),
      cfg_rd_hdr(10) => cfg_rd_hdr(10),
      cfg_rd_hdr(9) => cfg_rd_hdr(9),
      cfg_rd_hdr(8) => cfg_rd_hdr(8),
      cfg_rd_hdr(7) => cfg_rd_hdr(7),
      cfg_rd_hdr(6) => cfg_rd_hdr(6),
      cfg_rd_hdr(5) => cfg_rd_hdr(5),
      cfg_rd_hdr(4) => cfg_rd_hdr(4),
      cfg_rd_hdr(3) => cfg_rd_hdr(3),
      cfg_rd_hdr(2) => cfg_rd_hdr(2),
      cfg_rd_hdr(1) => cfg_rd_hdr(1),
      cfg_rd_hdr(0) => cfg_rd_hdr(0),
      cmt_rd_hdr(49) => cmt_rd_hdr(49),
      cmt_rd_hdr(48) => cmt_rd_hdr(48),
      cmt_rd_hdr(47) => cmt_rd_hdr(47),
      cmt_rd_hdr(46) => cmt_rd_hdr(46),
      cmt_rd_hdr(45) => cmt_rd_hdr(45),
      cmt_rd_hdr(44) => cmt_rd_hdr(44),
      cmt_rd_hdr(43) => cmt_rd_hdr(43),
      cmt_rd_hdr(42) => cmt_rd_hdr(42),
      cmt_rd_hdr(41) => cmt_rd_hdr(41),
      cmt_rd_hdr(40) => cmt_rd_hdr(40),
      cmt_rd_hdr(39) => cmt_rd_hdr(39),
      cmt_rd_hdr(38) => cmt_rd_hdr(38),
      cmt_rd_hdr(37) => cmt_rd_hdr(37),
      cmt_rd_hdr(36) => cmt_rd_hdr(36),
      cmt_rd_hdr(35) => cmt_rd_hdr(35),
      cmt_rd_hdr(34) => cmt_rd_hdr(34),
      cmt_rd_hdr(33) => cmt_rd_hdr(33),
      cmt_rd_hdr(32) => cmt_rd_hdr(32),
      cmt_rd_hdr(31) => cmt_rd_hdr(31),
      cmt_rd_hdr(30) => cmt_rd_hdr(30),
      cmt_rd_hdr(29) => cmt_rd_hdr(29),
      cmt_rd_hdr(28) => cmt_rd_hdr(28),
      cmt_rd_hdr(27) => cmt_rd_hdr(27),
      cmt_rd_hdr(26) => cmt_rd_hdr(26),
      cmt_rd_hdr(25) => cmt_rd_hdr(25),
      cmt_rd_hdr(24) => cmt_rd_hdr(24),
      cmt_rd_hdr(23) => cmt_rd_hdr(23),
      cmt_rd_hdr(22) => cmt_rd_hdr(22),
      cmt_rd_hdr(21) => cmt_rd_hdr(21),
      cmt_rd_hdr(20) => cmt_rd_hdr(20),
      cmt_rd_hdr(19) => cmt_rd_hdr(19),
      cmt_rd_hdr(18) => cmt_rd_hdr(18),
      cmt_rd_hdr(17) => cmt_rd_hdr(17),
      cmt_rd_hdr(16) => cmt_rd_hdr(16),
      cmt_rd_hdr(15) => cmt_rd_hdr(15),
      cmt_rd_hdr(14) => cmt_rd_hdr(14),
      cmt_rd_hdr(13) => cmt_rd_hdr(13),
      cmt_rd_hdr(12) => cmt_rd_hdr(12),
      cmt_rd_hdr(11) => cmt_rd_hdr(11),
      cmt_rd_hdr(10) => cmt_rd_hdr(10),
      cmt_rd_hdr(9) => cmt_rd_hdr(9),
      cmt_rd_hdr(8) => cmt_rd_hdr(8),
      cmt_rd_hdr(7) => cmt_rd_hdr(7),
      cmt_rd_hdr(6) => cmt_rd_hdr(6),
      cmt_rd_hdr(5) => cmt_rd_hdr(5),
      cmt_rd_hdr(4) => cmt_rd_hdr(4),
      cmt_rd_hdr(3) => cmt_rd_hdr(3),
      cmt_rd_hdr(2) => cmt_rd_hdr(2),
      cmt_rd_hdr(1) => cmt_rd_hdr(1),
      cmt_rd_hdr(0) => cmt_rd_hdr(0),
      rx_err_tlp_hdr(47) => rx_err_tlp_hdr(47),
      rx_err_tlp_hdr(46) => rx_err_tlp_hdr(46),
      rx_err_tlp_hdr(45) => rx_err_tlp_hdr(45),
      rx_err_tlp_hdr(44) => rx_err_tlp_hdr(44),
      rx_err_tlp_hdr(43) => rx_err_tlp_hdr(43),
      rx_err_tlp_hdr(42) => rx_err_tlp_hdr(42),
      rx_err_tlp_hdr(41) => rx_err_tlp_hdr(41),
      rx_err_tlp_hdr(40) => rx_err_tlp_hdr(40),
      rx_err_tlp_hdr(39) => rx_err_tlp_hdr(39),
      rx_err_tlp_hdr(38) => rx_err_tlp_hdr(38),
      rx_err_tlp_hdr(37) => rx_err_tlp_hdr(37),
      rx_err_tlp_hdr(36) => rx_err_tlp_hdr(36),
      rx_err_tlp_hdr(35) => rx_err_tlp_hdr(35),
      rx_err_tlp_hdr(34) => rx_err_tlp_hdr(34),
      rx_err_tlp_hdr(33) => rx_err_tlp_hdr(33),
      rx_err_tlp_hdr(32) => rx_err_tlp_hdr(32),
      rx_err_tlp_hdr(31) => rx_err_tlp_hdr(31),
      rx_err_tlp_hdr(30) => rx_err_tlp_hdr(30),
      rx_err_tlp_hdr(29) => rx_err_tlp_hdr(29),
      rx_err_tlp_hdr(28) => rx_err_tlp_hdr(28),
      rx_err_tlp_hdr(27) => rx_err_tlp_hdr(27),
      rx_err_tlp_hdr(26) => rx_err_tlp_hdr(26),
      rx_err_tlp_hdr(25) => rx_err_tlp_hdr(25),
      rx_err_tlp_hdr(24) => rx_err_tlp_hdr(24),
      rx_err_tlp_hdr(23) => rx_err_tlp_hdr(23),
      rx_err_tlp_hdr(22) => rx_err_tlp_hdr(22),
      rx_err_tlp_hdr(21) => rx_err_tlp_hdr(21),
      rx_err_tlp_hdr(20) => rx_err_tlp_hdr(20),
      rx_err_tlp_hdr(19) => rx_err_tlp_hdr(19),
      rx_err_tlp_hdr(18) => rx_err_tlp_hdr(18),
      rx_err_tlp_hdr(17) => rx_err_tlp_hdr(17),
      rx_err_tlp_hdr(16) => rx_err_tlp_hdr(16),
      rx_err_tlp_hdr(15) => rx_err_tlp_hdr(15),
      rx_err_tlp_hdr(14) => rx_err_tlp_hdr(14),
      rx_err_tlp_hdr(13) => rx_err_tlp_hdr(13),
      rx_err_tlp_hdr(12) => rx_err_tlp_hdr(12),
      rx_err_tlp_hdr(11) => rx_err_tlp_hdr(11),
      rx_err_tlp_hdr(10) => rx_err_tlp_hdr(10),
      rx_err_tlp_hdr(9) => rx_err_tlp_hdr(9),
      rx_err_tlp_hdr(8) => rx_err_tlp_hdr(8),
      rx_err_tlp_hdr(7) => rx_err_tlp_hdr(7),
      rx_err_tlp_hdr(6) => rx_err_tlp_hdr(6),
      rx_err_tlp_hdr(5) => rx_err_tlp_hdr(5),
      rx_err_tlp_hdr(4) => rx_err_tlp_hdr(4),
      rx_err_tlp_hdr(3) => rx_err_tlp_hdr(3),
      rx_err_tlp_hdr(2) => rx_err_tlp_hdr(2),
      rx_err_tlp_hdr(1) => rx_err_tlp_hdr(1),
      rx_err_tlp_hdr(0) => rx_err_tlp_hdr(0),
      request_data(49) => request_data(49),
      request_data(48) => request_data(48),
      request_data(47) => request_data(47),
      request_data(46) => request_data(46),
      request_data(45) => request_data(45),
      request_data(44) => request_data(44),
      request_data(43) => request_data(43),
      request_data(42) => request_data(42),
      request_data(41) => request_data(41),
      request_data(40) => request_data(40),
      request_data(39) => request_data(39),
      request_data(38) => request_data(38),
      request_data(37) => request_data(37),
      request_data(36) => request_data(36),
      request_data(35) => request_data(35),
      request_data(34) => request_data(34),
      request_data(33) => request_data(33),
      request_data(32) => request_data(32),
      request_data(31) => request_data(31),
      request_data(30) => request_data(30),
      request_data(29) => request_data(29),
      request_data(28) => request_data(28),
      request_data(27) => request_data(27),
      request_data(26) => request_data(26),
      request_data(25) => request_data(25),
      request_data(24) => request_data(24),
      request_data(23) => request_data(23),
      request_data(22) => request_data(22),
      request_data(21) => request_data(21),
      request_data(20) => request_data(20),
      request_data(19) => request_data(19),
      request_data(18) => request_data(18),
      request_data(17) => request_data(17),
      request_data(16) => request_data(16),
      request_data(15) => request_data(15),
      request_data(14) => request_data(14),
      request_data(13) => request_data(13),
      request_data(12) => request_data(12),
      request_data(11) => request_data(11),
      request_data(10) => request_data(10),
      request_data(9) => request_data(9),
      request_data(8) => request_data(8),
      request_data(7) => request_data(7),
      request_data(6) => request_data(6),
      request_data(5) => request_data(5),
      request_data(4) => request_data(4),
      request_data(3) => request_data(3),
      request_data(2) => request_data(2),
      request_data(1) => request_data(1),
      request_data(0) => request_data(0),
      l0_dll_error_vector(6) => l0_dll_error_vector(6),
      l0_dll_error_vector(5) => l0_dll_error_vector(5),
      l0_dll_error_vector(4) => l0_dll_error_vector(4),
      l0_dll_error_vector(3) => l0_dll_error_vector(3),
      l0_dll_error_vector(2) => l0_dll_error_vector(2),
      l0_dll_error_vector(1) => l0_dll_error_vector(1),
      l0_dll_error_vector(0) => l0_dll_error_vector(0),
      l0_rx_mac_link_error(1) => l0_rx_mac_link_error(1),
      l0_rx_mac_link_error(0) => l0_rx_mac_link_error(0),
      cfg_err_tlp_cpl_header(47) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(46) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(45) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(44) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(43) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(42) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(41) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(40) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(39) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(38) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(37) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(36) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(35) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(34) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(33) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(32) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(31) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(30) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(29) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(28) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(27) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(26) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(25) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(24) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(23) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(22) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(21) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(20) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(19) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(18) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(17) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(16) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(15) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(14) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(13) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(12) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(11) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(10) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(9) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(8) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(7) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(6) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(5) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(4) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(3) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(2) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(1) => NlwRenamedSig_OI_transactions_pending,
      cfg_err_tlp_cpl_header(0) => NlwRenamedSig_OI_transactions_pending,
      cfg_command(15) => NlwRenamedSig_OI_cfg_command(15),
      cfg_command(14) => NlwRenamedSig_OI_cfg_command(14),
      cfg_command(13) => NlwRenamedSig_OI_cfg_command(13),
      cfg_command(12) => NlwRenamedSig_OI_cfg_command(12),
      cfg_command(11) => NlwRenamedSig_OI_cfg_command(11),
      cfg_command(10) => NlwRenamedSig_OI_cfg_command(10),
      cfg_command(9) => NlwRenamedSig_OI_cfg_command(9),
      cfg_command(8) => NlwRenamedSig_OI_cfg_command(8),
      cfg_command(7) => NlwRenamedSig_OI_cfg_command(7),
      cfg_command(6) => NlwRenamedSig_OI_cfg_command(6),
      cfg_command(5) => NlwRenamedSig_OI_cfg_command(5),
      cfg_command(4) => NlwRenamedSig_OI_cfg_command(4),
      cfg_command(3) => NlwRenamedSig_OI_cfg_command(3),
      cfg_command(2) => NlwRenamedSig_OI_cfg_command(2),
      cfg_command(1) => NlwRenamedSig_OI_cfg_command(1),
      cfg_command(0) => NlwRenamedSig_OI_cfg_command(0),
      cfg_dcommand(15) => NlwRenamedSig_OI_cfg_dcommand(15),
      cfg_dcommand(14) => NlwRenamedSig_OI_cfg_dcommand(14),
      cfg_dcommand(13) => NlwRenamedSig_OI_cfg_dcommand(13),
      cfg_dcommand(12) => NlwRenamedSig_OI_cfg_dcommand(12),
      cfg_dcommand(11) => NlwRenamedSig_OI_cfg_dcommand(11),
      cfg_dcommand(10) => NlwRenamedSig_OI_cfg_dcommand(10),
      cfg_dcommand(9) => NlwRenamedSig_OI_cfg_dcommand(9),
      cfg_dcommand(8) => NlwRenamedSig_OI_cfg_dcommand(8),
      cfg_dcommand(7) => NlwRenamedSig_OI_cfg_dcommand(7),
      cfg_dcommand(6) => NlwRenamedSig_OI_cfg_dcommand(6),
      cfg_dcommand(5) => NlwRenamedSig_OI_cfg_dcommand(5),
      cfg_dcommand(4) => NlwRenamedSig_OI_cfg_dcommand(4),
      cfg_dcommand(3) => NlwRenamedSig_OI_cfg_dcommand(3),
      cfg_dcommand(2) => NlwRenamedSig_OI_cfg_dcommand(2),
      cfg_dcommand(1) => NlwRenamedSig_OI_cfg_dcommand(1),
      cfg_dcommand(0) => NlwRenamedSig_OI_cfg_dcommand(0)
    );
  interrupt_interface : pcie_soft_cf_int
    port map (
      clk => clk,
      signaledint => NLW_interrupt_interface_signaledint_UNCONNECTED,
      rst_n => rst_n,
      intr_req_valid => intr_req_valid,
      legacy_int_request => legacy_int_request,
      msi_8bit_en => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_n => cfg_interrupt_n,
      cs_is_intr => cs_is_intr,
      msi_enable => msi_enable,
      cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
      grant => grant,
      cfg_interrupt_assert_n => cfg_interrupt_assert_n,
      cfg_interrupt_do(7) => cfg_interrupt_do(7),
      cfg_interrupt_do(6) => cfg_interrupt_do(6),
      cfg_interrupt_do(5) => cfg_interrupt_do(5),
      cfg_interrupt_do(4) => cfg_interrupt_do(4),
      cfg_interrupt_do(3) => cfg_interrupt_do(3),
      cfg_interrupt_do(2) => cfg_interrupt_do(2),
      cfg_interrupt_do(1) => cfg_interrupt_do(1),
      cfg_interrupt_do(0) => cfg_interrupt_do(0),
      cfg_interrupt_mmenable(2) => cfg_interrupt_mmenable(2),
      cfg_interrupt_mmenable(1) => cfg_interrupt_mmenable(1),
      cfg_interrupt_mmenable(0) => cfg_interrupt_mmenable(0),
      intr_vector(7) => intr_vector(7),
      intr_vector(6) => intr_vector(6),
      intr_vector(5) => intr_vector(5),
      intr_vector(4) => intr_vector(4),
      intr_vector(3) => intr_vector(3),
      intr_vector(2) => intr_vector(2),
      intr_vector(1) => intr_vector(1),
      intr_vector(0) => intr_vector(0),
      msi_request(3) => msi_request(3),
      msi_request(2) => msi_request(2),
      msi_request(1) => msi_request(1),
      msi_request(0) => msi_request(0),
      intr_req_type(1) => intr_req_type(1),
      intr_req_type(0) => intr_req_type(0),
      cfg_msguaddr(31) => cfg_msguaddr(31),
      cfg_msguaddr(30) => cfg_msguaddr(30),
      cfg_msguaddr(29) => cfg_msguaddr(29),
      cfg_msguaddr(28) => cfg_msguaddr(28),
      cfg_msguaddr(27) => cfg_msguaddr(27),
      cfg_msguaddr(26) => cfg_msguaddr(26),
      cfg_msguaddr(25) => cfg_msguaddr(25),
      cfg_msguaddr(24) => cfg_msguaddr(24),
      cfg_msguaddr(23) => cfg_msguaddr(23),
      cfg_msguaddr(22) => cfg_msguaddr(22),
      cfg_msguaddr(21) => cfg_msguaddr(21),
      cfg_msguaddr(20) => cfg_msguaddr(20),
      cfg_msguaddr(19) => cfg_msguaddr(19),
      cfg_msguaddr(18) => cfg_msguaddr(18),
      cfg_msguaddr(17) => cfg_msguaddr(17),
      cfg_msguaddr(16) => cfg_msguaddr(16),
      cfg_msguaddr(15) => cfg_msguaddr(15),
      cfg_msguaddr(14) => cfg_msguaddr(14),
      cfg_msguaddr(13) => cfg_msguaddr(13),
      cfg_msguaddr(12) => cfg_msguaddr(12),
      cfg_msguaddr(11) => cfg_msguaddr(11),
      cfg_msguaddr(10) => cfg_msguaddr(10),
      cfg_msguaddr(9) => cfg_msguaddr(9),
      cfg_msguaddr(8) => cfg_msguaddr(8),
      cfg_msguaddr(7) => cfg_msguaddr(7),
      cfg_msguaddr(6) => cfg_msguaddr(6),
      cfg_msguaddr(5) => cfg_msguaddr(5),
      cfg_msguaddr(4) => cfg_msguaddr(4),
      cfg_msguaddr(3) => cfg_msguaddr(3),
      cfg_msguaddr(2) => cfg_msguaddr(2),
      cfg_msguaddr(1) => cfg_msguaddr(1),
      cfg_msguaddr(0) => cfg_msguaddr(0),
      cfg_interrupt_di(7) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(6) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(5) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(4) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(3) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(2) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(1) => NlwRenamedSig_OI_transactions_pending,
      cfg_interrupt_di(0) => NlwRenamedSig_OI_transactions_pending,
      msi_laddr(31) => cfg_msgladdr(31),
      msi_laddr(30) => cfg_msgladdr(30),
      msi_laddr(29) => cfg_msgladdr(29),
      msi_laddr(28) => cfg_msgladdr(28),
      msi_laddr(27) => cfg_msgladdr(27),
      msi_laddr(26) => cfg_msgladdr(26),
      msi_laddr(25) => cfg_msgladdr(25),
      msi_laddr(24) => cfg_msgladdr(24),
      msi_laddr(23) => cfg_msgladdr(23),
      msi_laddr(22) => cfg_msgladdr(22),
      msi_laddr(21) => cfg_msgladdr(21),
      msi_laddr(20) => cfg_msgladdr(20),
      msi_laddr(19) => cfg_msgladdr(19),
      msi_laddr(18) => cfg_msgladdr(18),
      msi_laddr(17) => cfg_msgladdr(17),
      msi_laddr(16) => cfg_msgladdr(16),
      msi_laddr(15) => cfg_msgladdr(15),
      msi_laddr(14) => cfg_msgladdr(14),
      msi_laddr(13) => cfg_msgladdr(13),
      msi_laddr(12) => cfg_msgladdr(12),
      msi_laddr(11) => cfg_msgladdr(11),
      msi_laddr(10) => cfg_msgladdr(10),
      msi_laddr(9) => cfg_msgladdr(9),
      msi_laddr(8) => cfg_msgladdr(8),
      msi_laddr(7) => cfg_msgladdr(7),
      msi_laddr(6) => cfg_msgladdr(6),
      msi_laddr(5) => cfg_msgladdr(5),
      msi_laddr(4) => cfg_msgladdr(4),
      msi_laddr(3) => cfg_msgladdr(3),
      msi_laddr(2) => cfg_msgladdr(2),
      msi_laddr(1) => cfg_msgladdr(1),
      msi_laddr(0) => cfg_msgladdr(0),
      msi_haddr(31) => cfg_msguaddr(31),
      msi_haddr(30) => cfg_msguaddr(30),
      msi_haddr(29) => cfg_msguaddr(29),
      msi_haddr(28) => cfg_msguaddr(28),
      msi_haddr(27) => cfg_msguaddr(27),
      msi_haddr(26) => cfg_msguaddr(26),
      msi_haddr(25) => cfg_msguaddr(25),
      msi_haddr(24) => cfg_msguaddr(24),
      msi_haddr(23) => cfg_msguaddr(23),
      msi_haddr(22) => cfg_msguaddr(22),
      msi_haddr(21) => cfg_msguaddr(21),
      msi_haddr(20) => cfg_msguaddr(20),
      msi_haddr(19) => cfg_msguaddr(19),
      msi_haddr(18) => cfg_msguaddr(18),
      msi_haddr(17) => cfg_msguaddr(17),
      msi_haddr(16) => cfg_msguaddr(16),
      msi_haddr(15) => cfg_msguaddr(15),
      msi_haddr(14) => cfg_msguaddr(14),
      msi_haddr(13) => cfg_msguaddr(13),
      msi_haddr(12) => cfg_msguaddr(12),
      msi_haddr(11) => cfg_msguaddr(11),
      msi_haddr(10) => cfg_msguaddr(10),
      msi_haddr(9) => cfg_msguaddr(9),
      msi_haddr(8) => cfg_msguaddr(8),
      msi_haddr(7) => cfg_msguaddr(7),
      msi_haddr(6) => cfg_msguaddr(6),
      msi_haddr(5) => cfg_msguaddr(5),
      msi_haddr(4) => cfg_msguaddr(4),
      msi_haddr(3) => cfg_msguaddr(3),
      msi_haddr(2) => cfg_msguaddr(2),
      msi_haddr(1) => cfg_msguaddr(1),
      msi_haddr(0) => cfg_msguaddr(0),
      cfg_command(15) => NlwRenamedSig_OI_cfg_command(15),
      cfg_command(14) => NlwRenamedSig_OI_cfg_command(14),
      cfg_command(13) => NlwRenamedSig_OI_cfg_command(13),
      cfg_command(12) => NlwRenamedSig_OI_cfg_command(12),
      cfg_command(11) => NlwRenamedSig_OI_cfg_command(11),
      cfg_command(10) => NlwRenamedSig_OI_cfg_command(10),
      cfg_command(9) => NlwRenamedSig_OI_cfg_command(9),
      cfg_command(8) => NlwRenamedSig_OI_cfg_command(8),
      cfg_command(7) => NlwRenamedSig_OI_cfg_command(7),
      cfg_command(6) => NlwRenamedSig_OI_cfg_command(6),
      cfg_command(5) => NlwRenamedSig_OI_cfg_command(5),
      cfg_command(4) => NlwRenamedSig_OI_cfg_command(4),
      cfg_command(3) => NlwRenamedSig_OI_cfg_command(3),
      cfg_command(2) => NlwRenamedSig_OI_cfg_command(2),
      cfg_command(1) => NlwRenamedSig_OI_cfg_command(1),
      cfg_command(0) => NlwRenamedSig_OI_cfg_command(0),
      cfg_msgctrl(15) => cfg_msgctrl(15),
      cfg_msgctrl(14) => cfg_msgctrl(14),
      cfg_msgctrl(13) => cfg_msgctrl(13),
      cfg_msgctrl(12) => cfg_msgctrl(12),
      cfg_msgctrl(11) => cfg_msgctrl(11),
      cfg_msgctrl(10) => cfg_msgctrl(10),
      cfg_msgctrl(9) => cfg_msgctrl(9),
      cfg_msgctrl(8) => cfg_msgctrl(8),
      cfg_msgctrl(7) => cfg_msgctrl(7),
      cfg_msgctrl(6) => cfg_msgctrl(6),
      cfg_msgctrl(5) => cfg_msgctrl(5),
      cfg_msgctrl(4) => cfg_msgctrl(4),
      cfg_msgctrl(3) => cfg_msgctrl(3),
      cfg_msgctrl(2) => cfg_msgctrl(2),
      cfg_msgctrl(1) => cfg_msgctrl(1),
      cfg_msgctrl(0) => cfg_msgctrl(0),
      cfg_msgdata(15) => cfg_msgdata(15),
      cfg_msgdata(14) => cfg_msgdata(14),
      cfg_msgdata(13) => cfg_msgdata(13),
      cfg_msgdata(12) => cfg_msgdata(12),
      cfg_msgdata(11) => cfg_msgdata(11),
      cfg_msgdata(10) => cfg_msgdata(10),
      cfg_msgdata(9) => cfg_msgdata(9),
      cfg_msgdata(8) => cfg_msgdata(8),
      cfg_msgdata(7) => cfg_msgdata(7),
      cfg_msgdata(6) => cfg_msgdata(6),
      cfg_msgdata(5) => cfg_msgdata(5),
      cfg_msgdata(4) => cfg_msgdata(4),
      cfg_msgdata(3) => cfg_msgdata(3),
      cfg_msgdata(2) => cfg_msgdata(2),
      cfg_msgdata(1) => cfg_msgdata(1),
      cfg_msgdata(0) => cfg_msgdata(0)
    );
  trn_lnk_up_n1_INV_0 : INV
    port map (
      I => llk_tc_status_reg_21595,
      O => trn_lnk_up_n
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity sync_fifo_2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    rd_en : in STD_LOGIC := 'X'; 
    afull : out STD_LOGIC; 
    empty : out STD_LOGIC; 
    rewind : in STD_LOGIC := 'X'; 
    wr_en : in STD_LOGIC := 'X'; 
    mark_addr : in STD_LOGIC := 'X'; 
    clear_addr : in STD_LOGIC := 'X'; 
    full : out STD_LOGIC; 
    aempty : out STD_LOGIC; 
    data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    dout : out STD_LOGIC_VECTOR ( 71 downto 0 ); 
    din : in STD_LOGIC_VECTOR ( 71 downto 0 ) 
  );
end sync_fifo_2;

architecture STRUCTURE of sync_fifo_2 is
  signal Result_0_1 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal data_count_int_not0002 : STD_LOGIC; 
  signal empty_int_26791 : STD_LOGIC; 
  signal empty_int_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_output_stage_empty : STD_LOGIC; 
  signal output_stage_empty_mux0000 : STD_LOGIC; 
  signal output_stage_empty_not0001 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal wr_en_int : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_2_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_0_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_1_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_3_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_4_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_7_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_5_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_6_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_8_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_9_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_12_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_10_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_11_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_13_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_14_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_15_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_16_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_17_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_18_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_21_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_19_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_20_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_22_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_23_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_24_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_25_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_26_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_27_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_30_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_28_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_29_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_31_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_32_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_33_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_34_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_35_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_36_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_39_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_37_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_38_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_40_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_41_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_44_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_42_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_43_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_45_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_46_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_49_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_47_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_48_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_50_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_51_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_52_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_53_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_54_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_55_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_58_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_56_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_57_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_59_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_60_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_61_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_62_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_63_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_64_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_67_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_65_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_66_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_68_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_69_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_70_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_dout_int_71_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal Mcount_data_count_int_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal Mcount_data_count_int_lut : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal Mcount_data_count_m1_lut : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal Result : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal NlwRenamedSig_OI_data_count_int : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal data_count_m1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal dout_int : STD_LOGIC_VECTOR ( 71 downto 0 ); 
  signal output_stage : STD_LOGIC_VECTOR ( 71 downto 0 ); 
begin
  empty <= NlwRenamedSig_OI_output_stage_empty;
  data_count(4) <= NlwRenamedSig_OI_data_count_int(4);
  data_count(3) <= NlwRenamedSig_OI_data_count_int(3);
  data_count(2) <= NlwRenamedSig_OI_data_count_int(2);
  data_count(1) <= NlwRenamedSig_OI_data_count_int(1);
  data_count(0) <= NlwRenamedSig_OI_data_count_int(0);
  dout(71) <= output_stage(71);
  dout(70) <= output_stage(70);
  dout(69) <= output_stage(69);
  dout(68) <= output_stage(68);
  dout(67) <= output_stage(67);
  dout(66) <= output_stage(66);
  dout(65) <= output_stage(65);
  dout(64) <= output_stage(64);
  dout(63) <= output_stage(63);
  dout(62) <= output_stage(62);
  dout(61) <= output_stage(61);
  dout(60) <= output_stage(60);
  dout(59) <= output_stage(59);
  dout(58) <= output_stage(58);
  dout(57) <= output_stage(57);
  dout(56) <= output_stage(56);
  dout(55) <= output_stage(55);
  dout(54) <= output_stage(54);
  dout(53) <= output_stage(53);
  dout(52) <= output_stage(52);
  dout(51) <= output_stage(51);
  dout(50) <= output_stage(50);
  dout(49) <= output_stage(49);
  dout(48) <= output_stage(48);
  dout(47) <= output_stage(47);
  dout(46) <= output_stage(46);
  dout(45) <= output_stage(45);
  dout(44) <= output_stage(44);
  dout(43) <= output_stage(43);
  dout(42) <= output_stage(42);
  dout(41) <= output_stage(41);
  dout(40) <= output_stage(40);
  dout(39) <= output_stage(39);
  dout(38) <= output_stage(38);
  dout(37) <= output_stage(37);
  dout(36) <= output_stage(36);
  dout(35) <= output_stage(35);
  dout(34) <= output_stage(34);
  dout(33) <= output_stage(33);
  dout(32) <= output_stage(32);
  dout(31) <= output_stage(31);
  dout(30) <= output_stage(30);
  dout(29) <= output_stage(29);
  dout(28) <= output_stage(28);
  dout(27) <= output_stage(27);
  dout(26) <= output_stage(26);
  dout(25) <= output_stage(25);
  dout(24) <= output_stage(24);
  dout(23) <= output_stage(23);
  dout(22) <= output_stage(22);
  dout(21) <= output_stage(21);
  dout(20) <= output_stage(20);
  dout(19) <= output_stage(19);
  dout(18) <= output_stage(18);
  dout(17) <= output_stage(17);
  dout(16) <= output_stage(16);
  dout(15) <= output_stage(15);
  dout(14) <= output_stage(14);
  dout(13) <= output_stage(13);
  dout(12) <= output_stage(12);
  dout(11) <= output_stage(11);
  dout(10) <= output_stage(10);
  dout(9) <= output_stage(9);
  dout(8) <= output_stage(8);
  dout(7) <= output_stage(7);
  dout(6) <= output_stage(6);
  dout(5) <= output_stage(5);
  dout(4) <= output_stage(4);
  dout(3) <= output_stage(3);
  dout(2) <= output_stage(2);
  dout(1) <= output_stage(1);
  dout(0) <= output_stage(0);
  XST_GND : GND
    port map (
      G => wr_en_int
    );
  empty_int : FDPE
    port map (
      C => clk,
      CE => empty_int_not0001,
      D => data_count_int_not0002,
      PRE => rst_n_inv,
      Q => empty_int_26791
    );
  output_stage_empty : FDPE
    port map (
      C => clk,
      CE => output_stage_empty_not0001,
      D => output_stage_empty_mux0000,
      PRE => rst_n_inv,
      Q => NlwRenamedSig_OI_output_stage_empty
    );
  output_stage_0 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(0),
      Q => output_stage(0)
    );
  output_stage_1 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(1),
      Q => output_stage(1)
    );
  output_stage_2 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(2),
      Q => output_stage(2)
    );
  output_stage_3 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(3),
      Q => output_stage(3)
    );
  output_stage_4 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(4),
      Q => output_stage(4)
    );
  output_stage_5 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(5),
      Q => output_stage(5)
    );
  output_stage_6 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(6),
      Q => output_stage(6)
    );
  output_stage_7 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(7),
      Q => output_stage(7)
    );
  output_stage_8 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(8),
      Q => output_stage(8)
    );
  output_stage_9 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(9),
      Q => output_stage(9)
    );
  output_stage_10 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(10),
      Q => output_stage(10)
    );
  output_stage_11 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(11),
      Q => output_stage(11)
    );
  output_stage_12 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(12),
      Q => output_stage(12)
    );
  output_stage_13 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(13),
      Q => output_stage(13)
    );
  output_stage_14 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(14),
      Q => output_stage(14)
    );
  output_stage_15 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(15),
      Q => output_stage(15)
    );
  output_stage_16 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(16),
      Q => output_stage(16)
    );
  output_stage_17 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(17),
      Q => output_stage(17)
    );
  output_stage_18 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(18),
      Q => output_stage(18)
    );
  output_stage_19 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(19),
      Q => output_stage(19)
    );
  output_stage_20 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(20),
      Q => output_stage(20)
    );
  output_stage_21 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(21),
      Q => output_stage(21)
    );
  output_stage_22 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(22),
      Q => output_stage(22)
    );
  output_stage_23 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(23),
      Q => output_stage(23)
    );
  output_stage_24 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(24),
      Q => output_stage(24)
    );
  output_stage_25 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(25),
      Q => output_stage(25)
    );
  output_stage_26 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(26),
      Q => output_stage(26)
    );
  output_stage_27 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(27),
      Q => output_stage(27)
    );
  output_stage_28 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(28),
      Q => output_stage(28)
    );
  output_stage_29 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(29),
      Q => output_stage(29)
    );
  output_stage_30 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(30),
      Q => output_stage(30)
    );
  output_stage_31 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(31),
      Q => output_stage(31)
    );
  output_stage_32 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(32),
      Q => output_stage(32)
    );
  output_stage_33 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(33),
      Q => output_stage(33)
    );
  output_stage_34 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(34),
      Q => output_stage(34)
    );
  output_stage_35 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(35),
      Q => output_stage(35)
    );
  output_stage_36 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(36),
      Q => output_stage(36)
    );
  output_stage_37 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(37),
      Q => output_stage(37)
    );
  output_stage_38 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(38),
      Q => output_stage(38)
    );
  output_stage_39 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(39),
      Q => output_stage(39)
    );
  output_stage_40 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(40),
      Q => output_stage(40)
    );
  output_stage_41 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(41),
      Q => output_stage(41)
    );
  output_stage_42 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(42),
      Q => output_stage(42)
    );
  output_stage_43 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(43),
      Q => output_stage(43)
    );
  output_stage_44 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(44),
      Q => output_stage(44)
    );
  output_stage_45 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(45),
      Q => output_stage(45)
    );
  output_stage_46 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(46),
      Q => output_stage(46)
    );
  output_stage_47 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(47),
      Q => output_stage(47)
    );
  output_stage_48 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(48),
      Q => output_stage(48)
    );
  output_stage_49 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(49),
      Q => output_stage(49)
    );
  output_stage_50 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(50),
      Q => output_stage(50)
    );
  output_stage_51 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(51),
      Q => output_stage(51)
    );
  output_stage_52 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(52),
      Q => output_stage(52)
    );
  output_stage_53 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(53),
      Q => output_stage(53)
    );
  output_stage_54 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(54),
      Q => output_stage(54)
    );
  output_stage_55 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(55),
      Q => output_stage(55)
    );
  output_stage_56 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(56),
      Q => output_stage(56)
    );
  output_stage_57 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(57),
      Q => output_stage(57)
    );
  output_stage_58 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(58),
      Q => output_stage(58)
    );
  output_stage_59 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(59),
      Q => output_stage(59)
    );
  output_stage_60 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(60),
      Q => output_stage(60)
    );
  output_stage_61 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(61),
      Q => output_stage(61)
    );
  output_stage_62 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(62),
      Q => output_stage(62)
    );
  output_stage_63 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(63),
      Q => output_stage(63)
    );
  output_stage_64 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(64),
      Q => output_stage(64)
    );
  output_stage_65 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(65),
      Q => output_stage(65)
    );
  output_stage_66 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(66),
      Q => output_stage(66)
    );
  output_stage_67 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(67),
      Q => output_stage(67)
    );
  output_stage_68 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(68),
      Q => output_stage(68)
    );
  output_stage_69 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(69),
      Q => output_stage(69)
    );
  output_stage_70 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(70),
      Q => output_stage(70)
    );
  output_stage_71 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => dout_int(71),
      Q => output_stage(71)
    );
  data_count_int_0 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(0),
      Q => NlwRenamedSig_OI_data_count_int(0)
    );
  data_count_int_1 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(1),
      Q => NlwRenamedSig_OI_data_count_int(1)
    );
  data_count_int_2 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(2),
      Q => NlwRenamedSig_OI_data_count_int(2)
    );
  data_count_int_3 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(3),
      Q => NlwRenamedSig_OI_data_count_int(3)
    );
  data_count_int_4 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(4),
      Q => NlwRenamedSig_OI_data_count_int(4)
    );
  data_count_m1_0 : FDPE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      D => Result_0_1,
      PRE => rst_n_inv,
      Q => data_count_m1(0)
    );
  data_count_m1_1 : FDPE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      D => Result_1_1,
      PRE => rst_n_inv,
      Q => data_count_m1(1)
    );
  data_count_m1_2 : FDPE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      D => Result_2_1,
      PRE => rst_n_inv,
      Q => data_count_m1(2)
    );
  data_count_m1_3 : FDPE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      D => Result_3_1,
      PRE => rst_n_inv,
      Q => data_count_m1(3)
    );
  Mshreg_dout_int_2_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(2),
      Q => dout_int(2),
      Q15 => NLW_Mshreg_dout_int_2_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_0_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(0),
      Q => dout_int(0),
      Q15 => NLW_Mshreg_dout_int_0_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_1_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(1),
      Q => dout_int(1),
      Q15 => NLW_Mshreg_dout_int_1_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_3_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(3),
      Q => dout_int(3),
      Q15 => NLW_Mshreg_dout_int_3_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_4_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(4),
      Q => dout_int(4),
      Q15 => NLW_Mshreg_dout_int_4_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_7_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(7),
      Q => dout_int(7),
      Q15 => NLW_Mshreg_dout_int_7_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_5_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(5),
      Q => dout_int(5),
      Q15 => NLW_Mshreg_dout_int_5_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_6_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(6),
      Q => dout_int(6),
      Q15 => NLW_Mshreg_dout_int_6_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_8_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(8),
      Q => dout_int(8),
      Q15 => NLW_Mshreg_dout_int_8_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_9_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(9),
      Q => dout_int(9),
      Q15 => NLW_Mshreg_dout_int_9_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_12_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(12),
      Q => dout_int(12),
      Q15 => NLW_Mshreg_dout_int_12_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_10_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(10),
      Q => dout_int(10),
      Q15 => NLW_Mshreg_dout_int_10_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_11_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(11),
      Q => dout_int(11),
      Q15 => NLW_Mshreg_dout_int_11_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_13_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(13),
      Q => dout_int(13),
      Q15 => NLW_Mshreg_dout_int_13_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_14_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(14),
      Q => dout_int(14),
      Q15 => NLW_Mshreg_dout_int_14_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_15_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(15),
      Q => dout_int(15),
      Q15 => NLW_Mshreg_dout_int_15_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_16_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(16),
      Q => dout_int(16),
      Q15 => NLW_Mshreg_dout_int_16_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_17_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(17),
      Q => dout_int(17),
      Q15 => NLW_Mshreg_dout_int_17_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_18_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(18),
      Q => dout_int(18),
      Q15 => NLW_Mshreg_dout_int_18_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_21_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(21),
      Q => dout_int(21),
      Q15 => NLW_Mshreg_dout_int_21_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_19_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(19),
      Q => dout_int(19),
      Q15 => NLW_Mshreg_dout_int_19_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_20_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(20),
      Q => dout_int(20),
      Q15 => NLW_Mshreg_dout_int_20_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_22_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(22),
      Q => dout_int(22),
      Q15 => NLW_Mshreg_dout_int_22_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_23_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(23),
      Q => dout_int(23),
      Q15 => NLW_Mshreg_dout_int_23_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_24_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(24),
      Q => dout_int(24),
      Q15 => NLW_Mshreg_dout_int_24_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_25_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(25),
      Q => dout_int(25),
      Q15 => NLW_Mshreg_dout_int_25_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_26_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(26),
      Q => dout_int(26),
      Q15 => NLW_Mshreg_dout_int_26_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_27_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(27),
      Q => dout_int(27),
      Q15 => NLW_Mshreg_dout_int_27_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_30_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(30),
      Q => dout_int(30),
      Q15 => NLW_Mshreg_dout_int_30_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_28_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(28),
      Q => dout_int(28),
      Q15 => NLW_Mshreg_dout_int_28_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_29_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(29),
      Q => dout_int(29),
      Q15 => NLW_Mshreg_dout_int_29_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_31_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(31),
      Q => dout_int(31),
      Q15 => NLW_Mshreg_dout_int_31_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_32_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(32),
      Q => dout_int(32),
      Q15 => NLW_Mshreg_dout_int_32_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_33_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(33),
      Q => dout_int(33),
      Q15 => NLW_Mshreg_dout_int_33_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_34_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(34),
      Q => dout_int(34),
      Q15 => NLW_Mshreg_dout_int_34_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_35_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(35),
      Q => dout_int(35),
      Q15 => NLW_Mshreg_dout_int_35_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_36_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(36),
      Q => dout_int(36),
      Q15 => NLW_Mshreg_dout_int_36_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_39_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(39),
      Q => dout_int(39),
      Q15 => NLW_Mshreg_dout_int_39_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_37_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(37),
      Q => dout_int(37),
      Q15 => NLW_Mshreg_dout_int_37_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_38_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(38),
      Q => dout_int(38),
      Q15 => NLW_Mshreg_dout_int_38_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_40_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(40),
      Q => dout_int(40),
      Q15 => NLW_Mshreg_dout_int_40_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_41_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(41),
      Q => dout_int(41),
      Q15 => NLW_Mshreg_dout_int_41_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_44_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(44),
      Q => dout_int(44),
      Q15 => NLW_Mshreg_dout_int_44_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_42_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(42),
      Q => dout_int(42),
      Q15 => NLW_Mshreg_dout_int_42_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_43_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(43),
      Q => dout_int(43),
      Q15 => NLW_Mshreg_dout_int_43_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_45_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(45),
      Q => dout_int(45),
      Q15 => NLW_Mshreg_dout_int_45_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_46_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(46),
      Q => dout_int(46),
      Q15 => NLW_Mshreg_dout_int_46_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_49_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(49),
      Q => dout_int(49),
      Q15 => NLW_Mshreg_dout_int_49_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_47_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(47),
      Q => dout_int(47),
      Q15 => NLW_Mshreg_dout_int_47_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_48_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(48),
      Q => dout_int(48),
      Q15 => NLW_Mshreg_dout_int_48_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_50_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(50),
      Q => dout_int(50),
      Q15 => NLW_Mshreg_dout_int_50_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_51_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(51),
      Q => dout_int(51),
      Q15 => NLW_Mshreg_dout_int_51_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_52_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(52),
      Q => dout_int(52),
      Q15 => NLW_Mshreg_dout_int_52_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_53_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(53),
      Q => dout_int(53),
      Q15 => NLW_Mshreg_dout_int_53_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_54_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(54),
      Q => dout_int(54),
      Q15 => NLW_Mshreg_dout_int_54_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_55_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(55),
      Q => dout_int(55),
      Q15 => NLW_Mshreg_dout_int_55_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_58_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(58),
      Q => dout_int(58),
      Q15 => NLW_Mshreg_dout_int_58_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_56_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(56),
      Q => dout_int(56),
      Q15 => NLW_Mshreg_dout_int_56_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_57_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(57),
      Q => dout_int(57),
      Q15 => NLW_Mshreg_dout_int_57_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_59_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(59),
      Q => dout_int(59),
      Q15 => NLW_Mshreg_dout_int_59_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_60_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(60),
      Q => dout_int(60),
      Q15 => NLW_Mshreg_dout_int_60_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_61_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(61),
      Q => dout_int(61),
      Q15 => NLW_Mshreg_dout_int_61_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_62_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(62),
      Q => dout_int(62),
      Q15 => NLW_Mshreg_dout_int_62_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_63_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(63),
      Q => dout_int(63),
      Q15 => NLW_Mshreg_dout_int_63_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_64_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(64),
      Q => dout_int(64),
      Q15 => NLW_Mshreg_dout_int_64_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_67_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(67),
      Q => dout_int(67),
      Q15 => NLW_Mshreg_dout_int_67_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_65_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(65),
      Q => dout_int(65),
      Q15 => NLW_Mshreg_dout_int_65_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_66_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(66),
      Q => dout_int(66),
      Q15 => NLW_Mshreg_dout_int_66_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_68_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(68),
      Q => dout_int(68),
      Q15 => NLW_Mshreg_dout_int_68_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_69_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(69),
      Q => dout_int(69),
      Q15 => NLW_Mshreg_dout_int_69_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_70_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(70),
      Q => dout_int(70),
      Q15 => NLW_Mshreg_dout_int_70_0_Q15_UNCONNECTED
    );
  Mshreg_dout_int_71_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => data_count_m1(0),
      A1 => data_count_m1(1),
      A2 => data_count_m1(2),
      A3 => data_count_m1(3),
      CE => wr_en_int,
      CLK => clk,
      D => din(71),
      Q => dout_int(71),
      Q15 => NLW_Mshreg_dout_int_71_0_Q15_UNCONNECTED
    );
  empty_int_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => data_count_int_not0002,
      I1 => NlwRenamedSig_OI_data_count_int(0),
      I2 => NlwRenamedSig_OI_data_count_int(1),
      I3 => NlwRenamedSig_OI_data_count_int(3),
      I4 => NlwRenamedSig_OI_data_count_int(2),
      I5 => NlwRenamedSig_OI_data_count_int(4),
      O => empty_int_not0001
    );
  internal_fifo_newdata_take1 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => empty_int_26791,
      I2 => rd_en,
      O => data_count_int_not0002
    );
  output_stage_empty_not00011 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => rd_en,
      I1 => empty_int_26791,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      O => output_stage_empty_not0001
    );
  output_stage_empty_mux00001 : LUT3
    generic map(
      INIT => X"F1"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => empty_int_26791,
      O => output_stage_empty_mux0000
    );
  Mcount_data_count_m1_lut_1_1 : LUT4
    generic map(
      INIT => X"AA56"
    )
    port map (
      I0 => data_count_m1(1),
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => rd_en,
      I3 => empty_int_26791,
      O => Mcount_data_count_m1_lut(1)
    );
  Mcount_data_count_int_lut_2_1 : LUT4
    generic map(
      INIT => X"AA56"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(2),
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => rd_en,
      I3 => empty_int_26791,
      O => Mcount_data_count_int_lut(2)
    );
  Mcount_data_count_int_lut_1_1 : LUT4
    generic map(
      INIT => X"AA56"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(1),
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => rd_en,
      I3 => empty_int_26791,
      O => Mcount_data_count_int_lut(1)
    );
  Mcount_data_count_m1_xor_3_11 : LUT6
    generic map(
      INIT => X"B4B4D2B4B4D2D2D2"
    )
    port map (
      I0 => data_count_int_not0002,
      I1 => data_count_m1(2),
      I2 => data_count_m1(3),
      I3 => Mcount_data_count_m1_lut(1),
      I4 => data_count_m1(0),
      I5 => data_count_m1(1),
      O => Result_3_1
    );
  Mcount_data_count_int_cy_2_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => Mcount_data_count_int_lut(2),
      I1 => NlwRenamedSig_OI_data_count_int(1),
      I2 => Mcount_data_count_int_lut(1),
      I3 => NlwRenamedSig_OI_data_count_int(0),
      I4 => NlwRenamedSig_OI_data_count_int(2),
      O => Mcount_data_count_int_cy(2)
    );
  Mcount_data_count_m1_xor_2_11 : LUT5
    generic map(
      INIT => X"99699666"
    )
    port map (
      I0 => data_count_m1(2),
      I1 => data_count_int_not0002,
      I2 => Mcount_data_count_m1_lut(1),
      I3 => data_count_m1(0),
      I4 => data_count_m1(1),
      O => Result_2_1
    );
  Mcount_data_count_int_xor_3_11 : LUT5
    generic map(
      INIT => X"6699659A"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(3),
      I1 => empty_int_26791,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      I3 => Mcount_data_count_int_cy(2),
      I4 => rd_en,
      O => Result(3)
    );
  Mcount_data_count_m1_xor_1_11 : LUT5
    generic map(
      INIT => X"6699659A"
    )
    port map (
      I0 => data_count_m1(1),
      I1 => empty_int_26791,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      I3 => data_count_m1(0),
      I4 => rd_en,
      O => Result_1_1
    );
  Mcount_data_count_int_xor_1_11 : LUT5
    generic map(
      INIT => X"6699659A"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(1),
      I1 => empty_int_26791,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      I3 => NlwRenamedSig_OI_data_count_int(0),
      I4 => rd_en,
      O => Result(1)
    );
  Mcount_data_count_int_xor_4_11 : LUT6
    generic map(
      INIT => X"5AAA59AAAAA5AAA6"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(4),
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => empty_int_26791,
      I3 => NlwRenamedSig_OI_data_count_int(3),
      I4 => rd_en,
      I5 => Mcount_data_count_int_cy(2),
      O => Result(4)
    );
  Mcount_data_count_int_xor_2_11 : LUT6
    generic map(
      INIT => X"5AAA59AAAAA5AAA6"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(2),
      I1 => rd_en,
      I2 => empty_int_26791,
      I3 => NlwRenamedSig_OI_data_count_int(0),
      I4 => NlwRenamedSig_OI_output_stage_empty,
      I5 => NlwRenamedSig_OI_data_count_int(1),
      O => Result(2)
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  Mcount_data_count_m1_xor_0_11_INV_0 : INV
    port map (
      I => data_count_m1(0),
      O => Result_0_1
    );
  Mcount_data_count_int_xor_0_11_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_data_count_int(0),
      O => Result(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity sync_fifo_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    rd_en : in STD_LOGIC := 'X'; 
    afull : out STD_LOGIC; 
    empty : out STD_LOGIC; 
    rewind : in STD_LOGIC := 'X'; 
    wr_en : in STD_LOGIC := 'X'; 
    mark_addr : in STD_LOGIC := 'X'; 
    clear_addr : in STD_LOGIC := 'X'; 
    full : out STD_LOGIC; 
    aempty : out STD_LOGIC; 
    data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    dout : out STD_LOGIC_VECTOR ( 71 downto 0 ); 
    din : in STD_LOGIC_VECTOR ( 71 downto 0 ) 
  );
end sync_fifo_1;

architecture STRUCTURE of sync_fifo_1 is
  signal Maccum_data_count_pkt_up_xor_9_rt_26127 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_1_rt_26149 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_2_rt_26151 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_3_rt_26153 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_4_rt_26155 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_5_rt_26157 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_6_rt_26159 : STD_LOGIC; 
  signal Mcount_bram_raddr_cy_7_rt_26161 : STD_LOGIC; 
  signal Mcount_bram_raddr_xor_8_rt_26163 : STD_LOGIC; 
  signal Mcount_bram_waddr : STD_LOGIC; 
  signal Mcount_bram_waddr1 : STD_LOGIC; 
  signal Mcount_bram_waddr2 : STD_LOGIC; 
  signal Mcount_bram_waddr3 : STD_LOGIC; 
  signal Mcount_bram_waddr4 : STD_LOGIC; 
  signal Mcount_bram_waddr5 : STD_LOGIC; 
  signal Mcount_bram_waddr6 : STD_LOGIC; 
  signal Mcount_bram_waddr7 : STD_LOGIC; 
  signal Mcount_bram_waddr8 : STD_LOGIC; 
  signal Mcount_data_count_pkt_down_cy_0_rt_26210 : STD_LOGIC; 
  signal Mcount_packet_size_int : STD_LOGIC; 
  signal Mcount_packet_size_int1 : STD_LOGIC; 
  signal Mcount_packet_size_int2 : STD_LOGIC; 
  signal Mcount_packet_size_int3 : STD_LOGIC; 
  signal Mcount_packet_size_int4 : STD_LOGIC; 
  signal Mcount_packet_size_int5 : STD_LOGIC; 
  signal Mcount_packet_size_int6 : STD_LOGIC; 
  signal Mcount_packet_size_int7 : STD_LOGIC; 
  signal Mcount_packet_size_int8 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_0_2 : STD_LOGIC; 
  signal Result_0_3 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_1_2 : STD_LOGIC; 
  signal Result_1_3 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_2_2 : STD_LOGIC; 
  signal Result_2_3 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_3_2 : STD_LOGIC; 
  signal Result_3_3 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_4_2 : STD_LOGIC; 
  signal Result_4_3 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_5_2 : STD_LOGIC; 
  signal Result_5_3 : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_6_2 : STD_LOGIC; 
  signal Result_6_3 : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal Result_7_2 : STD_LOGIC; 
  signal Result_7_3 : STD_LOGIC; 
  signal Result_8_1 : STD_LOGIC; 
  signal Result_8_2 : STD_LOGIC; 
  signal Result_8_3 : STD_LOGIC; 
  signal Result_9_1 : STD_LOGIC; 
  signal Result_9_2 : STD_LOGIC; 
  signal afull_not0001_26301 : STD_LOGIC; 
  signal bram_waddr_not0001 : STD_LOGIC; 
  signal clear_addr_d_26394 : STD_LOGIC; 
  signal clear_addr_d_and0000 : STD_LOGIC; 
  signal data_count_int_not0002 : STD_LOGIC; 
  signal data_count_int_not0003 : STD_LOGIC; 
  signal data_count_int_not0003_inv : STD_LOGIC; 
  signal data_count_pkt_down_not0001 : STD_LOGIC; 
  signal empty_int_26512 : STD_LOGIC; 
  signal empty_int_mux0000_26513 : STD_LOGIC; 
  signal empty_int_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_full : STD_LOGIC; 
  signal full_not0001 : STD_LOGIC; 
  signal internal_fifo_newdata_26517 : STD_LOGIC; 
  signal internal_fifo_newdata_not0001 : STD_LOGIC; 
  signal internal_fifo_newdata_take : STD_LOGIC; 
  signal mark_addr_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_output_stage_empty : STD_LOGIC; 
  signal output_stage_empty_mux0000 : STD_LOGIC; 
  signal output_stage_empty_not0001 : STD_LOGIC; 
  signal rewind_addr_not0001 : STD_LOGIC; 
  signal rewind_inv : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal wr_en_int : STD_LOGIC; 
  signal NLW_Mram_regBank_SBITERR_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_DBITERR_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_RDADDRU_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_WRADDRU_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mram_regBank_ECCPARITY_0_UNCONNECTED : STD_LOGIC; 
  signal Maccum_data_count_pkt_up_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Maccum_data_count_pkt_up_lut : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Madd_data_count_pkt_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Madd_data_count_pkt_lut : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Mcount_bram_raddr_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcount_bram_raddr_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_bram_waddr_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcount_bram_waddr_lut : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_data_count_int_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_data_count_int_lut : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Mcount_data_count_pkt_down_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_data_count_pkt_down_lut : STD_LOGIC_VECTOR ( 9 downto 1 ); 
  signal Mcount_packet_size_int_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcount_packet_size_int_lut : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal bram_raddr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal bram_style_fifo_dout_reg : STD_LOGIC_VECTOR ( 71 downto 0 ); 
  signal bram_waddr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal NlwRenamedSig_OI_data_count_int : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal data_count_pkt : STD_LOGIC_VECTOR ( 9 downto 1 ); 
  signal data_count_pkt_down : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal data_count_pkt_up : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal output_stage : STD_LOGIC_VECTOR ( 71 downto 0 ); 
  signal packet_size_int : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal rewind_addr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
begin
  empty <= NlwRenamedSig_OI_output_stage_empty;
  full <= NlwRenamedSig_OI_full;
  data_count(9) <= NlwRenamedSig_OI_data_count_int(9);
  data_count(8) <= NlwRenamedSig_OI_data_count_int(8);
  data_count(7) <= NlwRenamedSig_OI_data_count_int(7);
  data_count(6) <= NlwRenamedSig_OI_data_count_int(6);
  data_count(5) <= NlwRenamedSig_OI_data_count_int(5);
  data_count(4) <= NlwRenamedSig_OI_data_count_int(4);
  data_count(3) <= NlwRenamedSig_OI_data_count_int(3);
  data_count(2) <= NlwRenamedSig_OI_data_count_int(2);
  data_count(1) <= NlwRenamedSig_OI_data_count_int(1);
  data_count(0) <= NlwRenamedSig_OI_data_count_int(0);
  dout(71) <= output_stage(71);
  dout(70) <= output_stage(70);
  dout(69) <= output_stage(69);
  dout(68) <= output_stage(68);
  dout(67) <= output_stage(67);
  dout(66) <= output_stage(66);
  dout(65) <= output_stage(65);
  dout(64) <= output_stage(64);
  dout(63) <= output_stage(63);
  dout(62) <= output_stage(62);
  dout(61) <= output_stage(61);
  dout(60) <= output_stage(60);
  dout(59) <= output_stage(59);
  dout(58) <= output_stage(58);
  dout(57) <= output_stage(57);
  dout(56) <= output_stage(56);
  dout(55) <= output_stage(55);
  dout(54) <= output_stage(54);
  dout(53) <= output_stage(53);
  dout(52) <= output_stage(52);
  dout(51) <= output_stage(51);
  dout(50) <= output_stage(50);
  dout(49) <= output_stage(49);
  dout(48) <= output_stage(48);
  dout(47) <= output_stage(47);
  dout(46) <= output_stage(46);
  dout(45) <= output_stage(45);
  dout(44) <= output_stage(44);
  dout(43) <= output_stage(43);
  dout(42) <= output_stage(42);
  dout(41) <= output_stage(41);
  dout(40) <= output_stage(40);
  dout(39) <= output_stage(39);
  dout(38) <= output_stage(38);
  dout(37) <= output_stage(37);
  dout(36) <= output_stage(36);
  dout(35) <= output_stage(35);
  dout(34) <= output_stage(34);
  dout(33) <= output_stage(33);
  dout(32) <= output_stage(32);
  dout(31) <= output_stage(31);
  dout(30) <= output_stage(30);
  dout(29) <= output_stage(29);
  dout(28) <= output_stage(28);
  dout(27) <= output_stage(27);
  dout(26) <= output_stage(26);
  dout(25) <= output_stage(25);
  dout(24) <= output_stage(24);
  dout(23) <= output_stage(23);
  dout(22) <= output_stage(22);
  dout(21) <= output_stage(21);
  dout(20) <= output_stage(20);
  dout(19) <= output_stage(19);
  dout(18) <= output_stage(18);
  dout(17) <= output_stage(17);
  dout(16) <= output_stage(16);
  dout(15) <= output_stage(15);
  dout(14) <= output_stage(14);
  dout(13) <= output_stage(13);
  dout(12) <= output_stage(12);
  dout(11) <= output_stage(11);
  dout(10) <= output_stage(10);
  dout(9) <= output_stage(9);
  dout(8) <= output_stage(8);
  dout(7) <= output_stage(7);
  dout(6) <= output_stage(6);
  dout(5) <= output_stage(5);
  dout(4) <= output_stage(4);
  dout(3) <= output_stage(3);
  dout(2) <= output_stage(2);
  dout(1) <= output_stage(1);
  dout(0) <= output_stage(0);
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  afull_14669 : FDCE
    port map (
      C => clk,
      CE => afull_not0001_26301,
      CLR => rst_n_inv,
      D => data_count_int_not0003,
      Q => afull
    );
  full_14670 : FDCE
    port map (
      C => clk,
      CE => full_not0001,
      CLR => rst_n_inv,
      D => data_count_int_not0003,
      Q => NlwRenamedSig_OI_full
    );
  rewind_addr_0 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(0),
      Q => rewind_addr(0)
    );
  rewind_addr_1 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(1),
      Q => rewind_addr(1)
    );
  rewind_addr_2 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(2),
      Q => rewind_addr(2)
    );
  rewind_addr_3 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(3),
      Q => rewind_addr(3)
    );
  rewind_addr_4 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(4),
      Q => rewind_addr(4)
    );
  rewind_addr_5 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(5),
      Q => rewind_addr(5)
    );
  rewind_addr_6 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(6),
      Q => rewind_addr(6)
    );
  rewind_addr_7 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(7),
      Q => rewind_addr(7)
    );
  rewind_addr_8 : FDCE
    port map (
      C => clk,
      CE => rewind_addr_not0001,
      CLR => rst_n_inv,
      D => bram_waddr(8),
      Q => rewind_addr(8)
    );
  clear_addr_d : FDC
    port map (
      C => clk,
      CLR => rst_n_inv,
      D => clear_addr_d_and0000,
      Q => clear_addr_d_26394
    );
  empty_int : FDPE
    port map (
      C => clk,
      CE => empty_int_not0001,
      D => empty_int_mux0000_26513,
      PRE => rst_n_inv,
      Q => empty_int_26512
    );
  internal_fifo_newdata : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => internal_fifo_newdata_not0001,
      CLR => rst_n_inv,
      D => data_count_pkt_down_not0001,
      Q => internal_fifo_newdata_26517
    );
  output_stage_empty : FDPE
    port map (
      C => clk,
      CE => output_stage_empty_not0001,
      D => output_stage_empty_mux0000,
      PRE => rst_n_inv,
      Q => NlwRenamedSig_OI_output_stage_empty
    );
  output_stage_0 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(0),
      Q => output_stage(0)
    );
  output_stage_1 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(1),
      Q => output_stage(1)
    );
  output_stage_2 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(2),
      Q => output_stage(2)
    );
  output_stage_3 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(3),
      Q => output_stage(3)
    );
  output_stage_4 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(4),
      Q => output_stage(4)
    );
  output_stage_5 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(5),
      Q => output_stage(5)
    );
  output_stage_6 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(6),
      Q => output_stage(6)
    );
  output_stage_7 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(7),
      Q => output_stage(7)
    );
  output_stage_8 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(8),
      Q => output_stage(8)
    );
  output_stage_9 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(9),
      Q => output_stage(9)
    );
  output_stage_10 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(10),
      Q => output_stage(10)
    );
  output_stage_11 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(11),
      Q => output_stage(11)
    );
  output_stage_12 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(12),
      Q => output_stage(12)
    );
  output_stage_13 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(13),
      Q => output_stage(13)
    );
  output_stage_14 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(14),
      Q => output_stage(14)
    );
  output_stage_15 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(15),
      Q => output_stage(15)
    );
  output_stage_16 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(16),
      Q => output_stage(16)
    );
  output_stage_17 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(17),
      Q => output_stage(17)
    );
  output_stage_18 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(18),
      Q => output_stage(18)
    );
  output_stage_19 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(19),
      Q => output_stage(19)
    );
  output_stage_20 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(20),
      Q => output_stage(20)
    );
  output_stage_21 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(21),
      Q => output_stage(21)
    );
  output_stage_22 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(22),
      Q => output_stage(22)
    );
  output_stage_23 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(23),
      Q => output_stage(23)
    );
  output_stage_24 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(24),
      Q => output_stage(24)
    );
  output_stage_25 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(25),
      Q => output_stage(25)
    );
  output_stage_26 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(26),
      Q => output_stage(26)
    );
  output_stage_27 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(27),
      Q => output_stage(27)
    );
  output_stage_28 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(28),
      Q => output_stage(28)
    );
  output_stage_29 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(29),
      Q => output_stage(29)
    );
  output_stage_30 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(30),
      Q => output_stage(30)
    );
  output_stage_31 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(31),
      Q => output_stage(31)
    );
  output_stage_32 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(32),
      Q => output_stage(32)
    );
  output_stage_33 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(33),
      Q => output_stage(33)
    );
  output_stage_34 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(34),
      Q => output_stage(34)
    );
  output_stage_35 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(35),
      Q => output_stage(35)
    );
  output_stage_36 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(36),
      Q => output_stage(36)
    );
  output_stage_37 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(37),
      Q => output_stage(37)
    );
  output_stage_38 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(38),
      Q => output_stage(38)
    );
  output_stage_39 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(39),
      Q => output_stage(39)
    );
  output_stage_40 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(40),
      Q => output_stage(40)
    );
  output_stage_41 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(41),
      Q => output_stage(41)
    );
  output_stage_42 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(42),
      Q => output_stage(42)
    );
  output_stage_43 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(43),
      Q => output_stage(43)
    );
  output_stage_44 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(44),
      Q => output_stage(44)
    );
  output_stage_45 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(45),
      Q => output_stage(45)
    );
  output_stage_46 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(46),
      Q => output_stage(46)
    );
  output_stage_47 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(47),
      Q => output_stage(47)
    );
  output_stage_48 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(48),
      Q => output_stage(48)
    );
  output_stage_49 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(49),
      Q => output_stage(49)
    );
  output_stage_50 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(50),
      Q => output_stage(50)
    );
  output_stage_51 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(51),
      Q => output_stage(51)
    );
  output_stage_52 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(52),
      Q => output_stage(52)
    );
  output_stage_53 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(53),
      Q => output_stage(53)
    );
  output_stage_54 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(54),
      Q => output_stage(54)
    );
  output_stage_55 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(55),
      Q => output_stage(55)
    );
  output_stage_56 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(56),
      Q => output_stage(56)
    );
  output_stage_57 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(57),
      Q => output_stage(57)
    );
  output_stage_58 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(58),
      Q => output_stage(58)
    );
  output_stage_59 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(59),
      Q => output_stage(59)
    );
  output_stage_60 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(60),
      Q => output_stage(60)
    );
  output_stage_61 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(61),
      Q => output_stage(61)
    );
  output_stage_62 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(62),
      Q => output_stage(62)
    );
  output_stage_63 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(63),
      Q => output_stage(63)
    );
  output_stage_64 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(64),
      Q => output_stage(64)
    );
  output_stage_65 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(65),
      Q => output_stage(65)
    );
  output_stage_66 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(66),
      Q => output_stage(66)
    );
  output_stage_67 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(67),
      Q => output_stage(67)
    );
  output_stage_68 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(68),
      Q => output_stage(68)
    );
  output_stage_69 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(69),
      Q => output_stage(69)
    );
  output_stage_70 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(70),
      Q => output_stage(70)
    );
  output_stage_71 : FDCE
    port map (
      C => clk,
      CE => internal_fifo_newdata_take,
      CLR => rst_n_inv,
      D => bram_style_fifo_dout_reg(71),
      Q => output_stage(71)
    );
  Mcount_bram_waddr_lut_0_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(0),
      I2 => rewind_addr(0),
      O => Mcount_bram_waddr_lut(0)
    );
  Mcount_bram_waddr_cy_0_Q : MUXCY
    port map (
      CI => rewind_inv,
      DI => N0,
      S => Mcount_bram_waddr_lut(0),
      O => Mcount_bram_waddr_cy(0)
    );
  Mcount_bram_waddr_xor_0_Q : XORCY
    port map (
      CI => rewind_inv,
      LI => Mcount_bram_waddr_lut(0),
      O => Mcount_bram_waddr
    );
  Mcount_bram_waddr_lut_1_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(1),
      I2 => rewind_addr(1),
      O => Mcount_bram_waddr_lut(1)
    );
  Mcount_bram_waddr_cy_1_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(0),
      DI => N0,
      S => Mcount_bram_waddr_lut(1),
      O => Mcount_bram_waddr_cy(1)
    );
  Mcount_bram_waddr_xor_1_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(0),
      LI => Mcount_bram_waddr_lut(1),
      O => Mcount_bram_waddr1
    );
  Mcount_bram_waddr_lut_2_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(2),
      I2 => rewind_addr(2),
      O => Mcount_bram_waddr_lut(2)
    );
  Mcount_bram_waddr_cy_2_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(1),
      DI => N0,
      S => Mcount_bram_waddr_lut(2),
      O => Mcount_bram_waddr_cy(2)
    );
  Mcount_bram_waddr_xor_2_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(1),
      LI => Mcount_bram_waddr_lut(2),
      O => Mcount_bram_waddr2
    );
  Mcount_bram_waddr_lut_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(3),
      I2 => rewind_addr(3),
      O => Mcount_bram_waddr_lut(3)
    );
  Mcount_bram_waddr_cy_3_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(2),
      DI => N0,
      S => Mcount_bram_waddr_lut(3),
      O => Mcount_bram_waddr_cy(3)
    );
  Mcount_bram_waddr_xor_3_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(2),
      LI => Mcount_bram_waddr_lut(3),
      O => Mcount_bram_waddr3
    );
  Mcount_bram_waddr_lut_4_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(4),
      I2 => rewind_addr(4),
      O => Mcount_bram_waddr_lut(4)
    );
  Mcount_bram_waddr_cy_4_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(3),
      DI => N0,
      S => Mcount_bram_waddr_lut(4),
      O => Mcount_bram_waddr_cy(4)
    );
  Mcount_bram_waddr_xor_4_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(3),
      LI => Mcount_bram_waddr_lut(4),
      O => Mcount_bram_waddr4
    );
  Mcount_bram_waddr_lut_5_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(5),
      I2 => rewind_addr(5),
      O => Mcount_bram_waddr_lut(5)
    );
  Mcount_bram_waddr_cy_5_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(4),
      DI => N0,
      S => Mcount_bram_waddr_lut(5),
      O => Mcount_bram_waddr_cy(5)
    );
  Mcount_bram_waddr_xor_5_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(4),
      LI => Mcount_bram_waddr_lut(5),
      O => Mcount_bram_waddr5
    );
  Mcount_bram_waddr_lut_6_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(6),
      I2 => rewind_addr(6),
      O => Mcount_bram_waddr_lut(6)
    );
  Mcount_bram_waddr_cy_6_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(5),
      DI => N0,
      S => Mcount_bram_waddr_lut(6),
      O => Mcount_bram_waddr_cy(6)
    );
  Mcount_bram_waddr_xor_6_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(5),
      LI => Mcount_bram_waddr_lut(6),
      O => Mcount_bram_waddr6
    );
  Mcount_bram_waddr_lut_7_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(7),
      I2 => rewind_addr(7),
      O => Mcount_bram_waddr_lut(7)
    );
  Mcount_bram_waddr_cy_7_Q : MUXCY
    port map (
      CI => Mcount_bram_waddr_cy(6),
      DI => N0,
      S => Mcount_bram_waddr_lut(7),
      O => Mcount_bram_waddr_cy(7)
    );
  Mcount_bram_waddr_xor_7_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(6),
      LI => Mcount_bram_waddr_lut(7),
      O => Mcount_bram_waddr7
    );
  Mcount_bram_waddr_lut_8_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rewind,
      I1 => bram_waddr(8),
      I2 => rewind_addr(8),
      O => Mcount_bram_waddr_lut(8)
    );
  Mcount_bram_waddr_xor_8_Q : XORCY
    port map (
      CI => Mcount_bram_waddr_cy(7),
      LI => Mcount_bram_waddr_lut(8),
      O => Mcount_bram_waddr8
    );
  Mcount_packet_size_int_lut_0_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(0),
      I2 => N1,
      O => Mcount_packet_size_int_lut(0)
    );
  Mcount_packet_size_int_cy_0_Q : MUXCY
    port map (
      CI => mark_addr_inv,
      DI => N0,
      S => Mcount_packet_size_int_lut(0),
      O => Mcount_packet_size_int_cy(0)
    );
  Mcount_packet_size_int_xor_0_Q : XORCY
    port map (
      CI => mark_addr_inv,
      LI => Mcount_packet_size_int_lut(0),
      O => Mcount_packet_size_int
    );
  Mcount_packet_size_int_lut_1_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(1),
      I2 => N0,
      O => Mcount_packet_size_int_lut(1)
    );
  Mcount_packet_size_int_cy_1_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(0),
      DI => N0,
      S => Mcount_packet_size_int_lut(1),
      O => Mcount_packet_size_int_cy(1)
    );
  Mcount_packet_size_int_xor_1_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(0),
      LI => Mcount_packet_size_int_lut(1),
      O => Mcount_packet_size_int1
    );
  Mcount_packet_size_int_lut_2_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(2),
      I2 => N0,
      O => Mcount_packet_size_int_lut(2)
    );
  Mcount_packet_size_int_cy_2_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(1),
      DI => N0,
      S => Mcount_packet_size_int_lut(2),
      O => Mcount_packet_size_int_cy(2)
    );
  Mcount_packet_size_int_xor_2_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(1),
      LI => Mcount_packet_size_int_lut(2),
      O => Mcount_packet_size_int2
    );
  Mcount_packet_size_int_lut_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(3),
      I2 => N0,
      O => Mcount_packet_size_int_lut(3)
    );
  Mcount_packet_size_int_cy_3_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(2),
      DI => N0,
      S => Mcount_packet_size_int_lut(3),
      O => Mcount_packet_size_int_cy(3)
    );
  Mcount_packet_size_int_xor_3_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(2),
      LI => Mcount_packet_size_int_lut(3),
      O => Mcount_packet_size_int3
    );
  Mcount_packet_size_int_lut_4_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(4),
      I2 => N0,
      O => Mcount_packet_size_int_lut(4)
    );
  Mcount_packet_size_int_cy_4_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(3),
      DI => N0,
      S => Mcount_packet_size_int_lut(4),
      O => Mcount_packet_size_int_cy(4)
    );
  Mcount_packet_size_int_xor_4_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(3),
      LI => Mcount_packet_size_int_lut(4),
      O => Mcount_packet_size_int4
    );
  Mcount_packet_size_int_lut_5_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(5),
      I2 => N0,
      O => Mcount_packet_size_int_lut(5)
    );
  Mcount_packet_size_int_cy_5_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(4),
      DI => N0,
      S => Mcount_packet_size_int_lut(5),
      O => Mcount_packet_size_int_cy(5)
    );
  Mcount_packet_size_int_xor_5_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(4),
      LI => Mcount_packet_size_int_lut(5),
      O => Mcount_packet_size_int5
    );
  Mcount_packet_size_int_lut_6_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(6),
      I2 => N0,
      O => Mcount_packet_size_int_lut(6)
    );
  Mcount_packet_size_int_cy_6_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(5),
      DI => N0,
      S => Mcount_packet_size_int_lut(6),
      O => Mcount_packet_size_int_cy(6)
    );
  Mcount_packet_size_int_xor_6_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(5),
      LI => Mcount_packet_size_int_lut(6),
      O => Mcount_packet_size_int6
    );
  Mcount_packet_size_int_lut_7_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(7),
      I2 => N0,
      O => Mcount_packet_size_int_lut(7)
    );
  Mcount_packet_size_int_cy_7_Q : MUXCY
    port map (
      CI => Mcount_packet_size_int_cy(6),
      DI => N0,
      S => Mcount_packet_size_int_lut(7),
      O => Mcount_packet_size_int_cy(7)
    );
  Mcount_packet_size_int_xor_7_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(6),
      LI => Mcount_packet_size_int_lut(7),
      O => Mcount_packet_size_int7
    );
  Mcount_packet_size_int_lut_8_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => mark_addr,
      I1 => packet_size_int(8),
      I2 => N0,
      O => Mcount_packet_size_int_lut(8)
    );
  Mcount_packet_size_int_xor_8_Q : XORCY
    port map (
      CI => Mcount_packet_size_int_cy(7),
      LI => Mcount_packet_size_int_lut(8),
      O => Mcount_packet_size_int8
    );
  bram_waddr_0 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr,
      Q => bram_waddr(0)
    );
  bram_waddr_1 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr1,
      Q => bram_waddr(1)
    );
  bram_waddr_2 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr2,
      Q => bram_waddr(2)
    );
  bram_waddr_3 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr3,
      Q => bram_waddr(3)
    );
  bram_waddr_4 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr4,
      Q => bram_waddr(4)
    );
  bram_waddr_5 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr5,
      Q => bram_waddr(5)
    );
  bram_waddr_6 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr6,
      Q => bram_waddr(6)
    );
  bram_waddr_7 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr7,
      Q => bram_waddr(7)
    );
  bram_waddr_8 : FDCE
    port map (
      C => clk,
      CE => bram_waddr_not0001,
      CLR => rst_n_inv,
      D => Mcount_bram_waddr8,
      Q => bram_waddr(8)
    );
  data_count_int_0 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(0),
      Q => NlwRenamedSig_OI_data_count_int(0)
    );
  data_count_int_1 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(1),
      Q => NlwRenamedSig_OI_data_count_int(1)
    );
  data_count_int_2 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(2),
      Q => NlwRenamedSig_OI_data_count_int(2)
    );
  data_count_int_3 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(3),
      Q => NlwRenamedSig_OI_data_count_int(3)
    );
  data_count_int_4 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(4),
      Q => NlwRenamedSig_OI_data_count_int(4)
    );
  data_count_int_5 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(5),
      Q => NlwRenamedSig_OI_data_count_int(5)
    );
  data_count_int_6 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(6),
      Q => NlwRenamedSig_OI_data_count_int(6)
    );
  data_count_int_7 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(7),
      Q => NlwRenamedSig_OI_data_count_int(7)
    );
  data_count_int_8 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(8),
      Q => NlwRenamedSig_OI_data_count_int(8)
    );
  data_count_int_9 : FDCE
    port map (
      C => clk,
      CE => data_count_int_not0002,
      CLR => rst_n_inv,
      D => Result(9),
      Q => NlwRenamedSig_OI_data_count_int(9)
    );
  packet_size_int_0 : FDPE
    port map (
      C => clk,
      CE => wr_en_int,
      D => Mcount_packet_size_int,
      PRE => rst_n_inv,
      Q => packet_size_int(0)
    );
  bram_raddr_0 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_0_1,
      Q => bram_raddr(0)
    );
  bram_raddr_1 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_1_1,
      Q => bram_raddr(1)
    );
  bram_raddr_2 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_2_1,
      Q => bram_raddr(2)
    );
  bram_raddr_3 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_3_1,
      Q => bram_raddr(3)
    );
  bram_raddr_4 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_4_1,
      Q => bram_raddr(4)
    );
  bram_raddr_5 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_5_1,
      Q => bram_raddr(5)
    );
  bram_raddr_6 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_6_1,
      Q => bram_raddr(6)
    );
  bram_raddr_7 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_7_1,
      Q => bram_raddr(7)
    );
  bram_raddr_8 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_8_1,
      Q => bram_raddr(8)
    );
  packet_size_int_3 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int3,
      Q => packet_size_int(3)
    );
  packet_size_int_1 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int1,
      Q => packet_size_int(1)
    );
  packet_size_int_2 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int2,
      Q => packet_size_int(2)
    );
  packet_size_int_6 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int6,
      Q => packet_size_int(6)
    );
  packet_size_int_4 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int4,
      Q => packet_size_int(4)
    );
  packet_size_int_5 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int5,
      Q => packet_size_int(5)
    );
  packet_size_int_7 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int7,
      Q => packet_size_int(7)
    );
  packet_size_int_8 : FDCE
    port map (
      C => clk,
      CE => wr_en_int,
      CLR => rst_n_inv,
      D => Mcount_packet_size_int8,
      Q => packet_size_int(8)
    );
  data_count_pkt_down_0 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_0_2,
      Q => data_count_pkt_down(0)
    );
  data_count_pkt_down_1 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_1_2,
      Q => data_count_pkt_down(1)
    );
  data_count_pkt_down_2 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_2_2,
      Q => data_count_pkt_down(2)
    );
  data_count_pkt_down_3 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_3_2,
      Q => data_count_pkt_down(3)
    );
  data_count_pkt_down_4 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_4_2,
      Q => data_count_pkt_down(4)
    );
  data_count_pkt_down_5 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_5_2,
      Q => data_count_pkt_down(5)
    );
  data_count_pkt_down_6 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_6_2,
      Q => data_count_pkt_down(6)
    );
  data_count_pkt_down_7 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_7_2,
      Q => data_count_pkt_down(7)
    );
  data_count_pkt_down_8 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_8_2,
      Q => data_count_pkt_down(8)
    );
  data_count_pkt_down_9 : FDCE
    port map (
      C => clk,
      CE => data_count_pkt_down_not0001,
      CLR => rst_n_inv,
      D => Result_9_1,
      Q => data_count_pkt_down(9)
    );
  data_count_pkt_up_0 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_0_3,
      Q => data_count_pkt_up(0)
    );
  data_count_pkt_up_1 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_1_3,
      Q => data_count_pkt_up(1)
    );
  data_count_pkt_up_2 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_2_3,
      Q => data_count_pkt_up(2)
    );
  data_count_pkt_up_3 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_3_3,
      Q => data_count_pkt_up(3)
    );
  data_count_pkt_up_4 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_4_3,
      Q => data_count_pkt_up(4)
    );
  data_count_pkt_up_5 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_5_3,
      Q => data_count_pkt_up(5)
    );
  data_count_pkt_up_6 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_6_3,
      Q => data_count_pkt_up(6)
    );
  data_count_pkt_up_7 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_7_3,
      Q => data_count_pkt_up(7)
    );
  data_count_pkt_up_8 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_8_3,
      Q => data_count_pkt_up(8)
    );
  data_count_pkt_up_9 : FDCE
    port map (
      C => clk,
      CE => clear_addr_d_26394,
      CLR => rst_n_inv,
      D => Result_9_2,
      Q => data_count_pkt_up(9)
    );
  Madd_data_count_pkt_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(0),
      I1 => data_count_pkt_down(0),
      O => Madd_data_count_pkt_lut(0)
    );
  Madd_data_count_pkt_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => data_count_pkt_up(0),
      S => Madd_data_count_pkt_lut(0),
      O => Madd_data_count_pkt_cy(0)
    );
  Madd_data_count_pkt_lut_1_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(1),
      I1 => data_count_pkt_down(1),
      O => Madd_data_count_pkt_lut(1)
    );
  Madd_data_count_pkt_cy_1_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(0),
      DI => data_count_pkt_up(1),
      S => Madd_data_count_pkt_lut(1),
      O => Madd_data_count_pkt_cy(1)
    );
  Madd_data_count_pkt_xor_1_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(0),
      LI => Madd_data_count_pkt_lut(1),
      O => data_count_pkt(1)
    );
  Madd_data_count_pkt_lut_2_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(2),
      I1 => data_count_pkt_down(2),
      O => Madd_data_count_pkt_lut(2)
    );
  Madd_data_count_pkt_cy_2_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(1),
      DI => data_count_pkt_up(2),
      S => Madd_data_count_pkt_lut(2),
      O => Madd_data_count_pkt_cy(2)
    );
  Madd_data_count_pkt_xor_2_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(1),
      LI => Madd_data_count_pkt_lut(2),
      O => data_count_pkt(2)
    );
  Madd_data_count_pkt_lut_3_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(3),
      I1 => data_count_pkt_down(3),
      O => Madd_data_count_pkt_lut(3)
    );
  Madd_data_count_pkt_cy_3_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(2),
      DI => data_count_pkt_up(3),
      S => Madd_data_count_pkt_lut(3),
      O => Madd_data_count_pkt_cy(3)
    );
  Madd_data_count_pkt_xor_3_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(2),
      LI => Madd_data_count_pkt_lut(3),
      O => data_count_pkt(3)
    );
  Madd_data_count_pkt_lut_4_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(4),
      I1 => data_count_pkt_down(4),
      O => Madd_data_count_pkt_lut(4)
    );
  Madd_data_count_pkt_cy_4_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(3),
      DI => data_count_pkt_up(4),
      S => Madd_data_count_pkt_lut(4),
      O => Madd_data_count_pkt_cy(4)
    );
  Madd_data_count_pkt_xor_4_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(3),
      LI => Madd_data_count_pkt_lut(4),
      O => data_count_pkt(4)
    );
  Madd_data_count_pkt_lut_5_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(5),
      I1 => data_count_pkt_down(5),
      O => Madd_data_count_pkt_lut(5)
    );
  Madd_data_count_pkt_cy_5_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(4),
      DI => data_count_pkt_up(5),
      S => Madd_data_count_pkt_lut(5),
      O => Madd_data_count_pkt_cy(5)
    );
  Madd_data_count_pkt_xor_5_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(4),
      LI => Madd_data_count_pkt_lut(5),
      O => data_count_pkt(5)
    );
  Madd_data_count_pkt_lut_6_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(6),
      I1 => data_count_pkt_down(6),
      O => Madd_data_count_pkt_lut(6)
    );
  Madd_data_count_pkt_cy_6_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(5),
      DI => data_count_pkt_up(6),
      S => Madd_data_count_pkt_lut(6),
      O => Madd_data_count_pkt_cy(6)
    );
  Madd_data_count_pkt_xor_6_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(5),
      LI => Madd_data_count_pkt_lut(6),
      O => data_count_pkt(6)
    );
  Madd_data_count_pkt_lut_7_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(7),
      I1 => data_count_pkt_down(7),
      O => Madd_data_count_pkt_lut(7)
    );
  Madd_data_count_pkt_cy_7_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(6),
      DI => data_count_pkt_up(7),
      S => Madd_data_count_pkt_lut(7),
      O => Madd_data_count_pkt_cy(7)
    );
  Madd_data_count_pkt_xor_7_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(6),
      LI => Madd_data_count_pkt_lut(7),
      O => data_count_pkt(7)
    );
  Madd_data_count_pkt_lut_8_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(8),
      I1 => data_count_pkt_down(8),
      O => Madd_data_count_pkt_lut(8)
    );
  Madd_data_count_pkt_cy_8_Q : MUXCY
    port map (
      CI => Madd_data_count_pkt_cy(7),
      DI => data_count_pkt_up(8),
      S => Madd_data_count_pkt_lut(8),
      O => Madd_data_count_pkt_cy(8)
    );
  Madd_data_count_pkt_xor_8_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(7),
      LI => Madd_data_count_pkt_lut(8),
      O => data_count_pkt(8)
    );
  Madd_data_count_pkt_lut_9_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(9),
      I1 => data_count_pkt_down(9),
      O => Madd_data_count_pkt_lut(9)
    );
  Madd_data_count_pkt_xor_9_Q : XORCY
    port map (
      CI => Madd_data_count_pkt_cy(8),
      LI => Madd_data_count_pkt_lut(9),
      O => data_count_pkt(9)
    );
  Mcount_bram_raddr_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_bram_raddr_lut(0),
      O => Mcount_bram_raddr_cy(0)
    );
  Mcount_bram_raddr_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_bram_raddr_lut(0),
      O => Result_0_1
    );
  Mcount_bram_raddr_cy_1_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(0),
      DI => N0,
      S => Mcount_bram_raddr_cy_1_rt_26149,
      O => Mcount_bram_raddr_cy(1)
    );
  Mcount_bram_raddr_xor_1_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(0),
      LI => Mcount_bram_raddr_cy_1_rt_26149,
      O => Result_1_1
    );
  Mcount_bram_raddr_cy_2_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(1),
      DI => N0,
      S => Mcount_bram_raddr_cy_2_rt_26151,
      O => Mcount_bram_raddr_cy(2)
    );
  Mcount_bram_raddr_xor_2_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(1),
      LI => Mcount_bram_raddr_cy_2_rt_26151,
      O => Result_2_1
    );
  Mcount_bram_raddr_cy_3_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(2),
      DI => N0,
      S => Mcount_bram_raddr_cy_3_rt_26153,
      O => Mcount_bram_raddr_cy(3)
    );
  Mcount_bram_raddr_xor_3_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(2),
      LI => Mcount_bram_raddr_cy_3_rt_26153,
      O => Result_3_1
    );
  Mcount_bram_raddr_cy_4_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(3),
      DI => N0,
      S => Mcount_bram_raddr_cy_4_rt_26155,
      O => Mcount_bram_raddr_cy(4)
    );
  Mcount_bram_raddr_xor_4_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(3),
      LI => Mcount_bram_raddr_cy_4_rt_26155,
      O => Result_4_1
    );
  Mcount_bram_raddr_cy_5_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(4),
      DI => N0,
      S => Mcount_bram_raddr_cy_5_rt_26157,
      O => Mcount_bram_raddr_cy(5)
    );
  Mcount_bram_raddr_xor_5_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(4),
      LI => Mcount_bram_raddr_cy_5_rt_26157,
      O => Result_5_1
    );
  Mcount_bram_raddr_cy_6_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(5),
      DI => N0,
      S => Mcount_bram_raddr_cy_6_rt_26159,
      O => Mcount_bram_raddr_cy(6)
    );
  Mcount_bram_raddr_xor_6_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(5),
      LI => Mcount_bram_raddr_cy_6_rt_26159,
      O => Result_6_1
    );
  Mcount_bram_raddr_cy_7_Q : MUXCY
    port map (
      CI => Mcount_bram_raddr_cy(6),
      DI => N0,
      S => Mcount_bram_raddr_cy_7_rt_26161,
      O => Mcount_bram_raddr_cy(7)
    );
  Mcount_bram_raddr_xor_7_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(6),
      LI => Mcount_bram_raddr_cy_7_rt_26161,
      O => Result_7_1
    );
  Mcount_bram_raddr_xor_8_Q : XORCY
    port map (
      CI => Mcount_bram_raddr_cy(7),
      LI => Mcount_bram_raddr_xor_8_rt_26163,
      O => Result_8_1
    );
  Mcount_data_count_int_cy_0_Q : MUXCY
    port map (
      CI => data_count_int_not0003_inv,
      DI => NlwRenamedSig_OI_data_count_int(0),
      S => Mcount_data_count_int_lut(0),
      O => Mcount_data_count_int_cy(0)
    );
  Mcount_data_count_int_xor_0_Q : XORCY
    port map (
      CI => data_count_int_not0003_inv,
      LI => Mcount_data_count_int_lut(0),
      O => Result(0)
    );
  Mcount_data_count_int_cy_1_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(0),
      DI => NlwRenamedSig_OI_data_count_int(1),
      S => Mcount_data_count_int_lut(1),
      O => Mcount_data_count_int_cy(1)
    );
  Mcount_data_count_int_xor_1_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(0),
      LI => Mcount_data_count_int_lut(1),
      O => Result(1)
    );
  Mcount_data_count_int_cy_2_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(1),
      DI => NlwRenamedSig_OI_data_count_int(2),
      S => Mcount_data_count_int_lut(2),
      O => Mcount_data_count_int_cy(2)
    );
  Mcount_data_count_int_xor_2_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(1),
      LI => Mcount_data_count_int_lut(2),
      O => Result(2)
    );
  Mcount_data_count_int_cy_3_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(2),
      DI => NlwRenamedSig_OI_data_count_int(3),
      S => Mcount_data_count_int_lut(3),
      O => Mcount_data_count_int_cy(3)
    );
  Mcount_data_count_int_xor_3_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(2),
      LI => Mcount_data_count_int_lut(3),
      O => Result(3)
    );
  Mcount_data_count_int_cy_4_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(3),
      DI => NlwRenamedSig_OI_data_count_int(4),
      S => Mcount_data_count_int_lut(4),
      O => Mcount_data_count_int_cy(4)
    );
  Mcount_data_count_int_xor_4_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(3),
      LI => Mcount_data_count_int_lut(4),
      O => Result(4)
    );
  Mcount_data_count_int_cy_5_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(4),
      DI => NlwRenamedSig_OI_data_count_int(5),
      S => Mcount_data_count_int_lut(5),
      O => Mcount_data_count_int_cy(5)
    );
  Mcount_data_count_int_xor_5_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(4),
      LI => Mcount_data_count_int_lut(5),
      O => Result(5)
    );
  Mcount_data_count_int_cy_6_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(5),
      DI => NlwRenamedSig_OI_data_count_int(6),
      S => Mcount_data_count_int_lut(6),
      O => Mcount_data_count_int_cy(6)
    );
  Mcount_data_count_int_xor_6_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(5),
      LI => Mcount_data_count_int_lut(6),
      O => Result(6)
    );
  Mcount_data_count_int_cy_7_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(6),
      DI => NlwRenamedSig_OI_data_count_int(7),
      S => Mcount_data_count_int_lut(7),
      O => Mcount_data_count_int_cy(7)
    );
  Mcount_data_count_int_xor_7_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(6),
      LI => Mcount_data_count_int_lut(7),
      O => Result(7)
    );
  Mcount_data_count_int_cy_8_Q : MUXCY
    port map (
      CI => Mcount_data_count_int_cy(7),
      DI => NlwRenamedSig_OI_data_count_int(8),
      S => Mcount_data_count_int_lut(8),
      O => Mcount_data_count_int_cy(8)
    );
  Mcount_data_count_int_xor_8_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(7),
      LI => Mcount_data_count_int_lut(8),
      O => Result(8)
    );
  Mcount_data_count_int_xor_9_Q : XORCY
    port map (
      CI => Mcount_data_count_int_cy(8),
      LI => Mcount_data_count_int_lut(9),
      O => Result(9)
    );
  Mcount_data_count_pkt_down_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => Mcount_data_count_pkt_down_cy_0_rt_26210,
      O => Mcount_data_count_pkt_down_cy(0)
    );
  Mcount_data_count_pkt_down_xor_0_Q : XORCY
    port map (
      CI => N1,
      LI => Mcount_data_count_pkt_down_cy_0_rt_26210,
      O => Result_0_2
    );
  Mcount_data_count_pkt_down_cy_1_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(0),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(1),
      O => Mcount_data_count_pkt_down_cy(1)
    );
  Mcount_data_count_pkt_down_xor_1_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(0),
      LI => Mcount_data_count_pkt_down_lut(1),
      O => Result_1_2
    );
  Mcount_data_count_pkt_down_cy_2_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(1),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(2),
      O => Mcount_data_count_pkt_down_cy(2)
    );
  Mcount_data_count_pkt_down_xor_2_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(1),
      LI => Mcount_data_count_pkt_down_lut(2),
      O => Result_2_2
    );
  Mcount_data_count_pkt_down_cy_3_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(2),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(3),
      O => Mcount_data_count_pkt_down_cy(3)
    );
  Mcount_data_count_pkt_down_xor_3_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(2),
      LI => Mcount_data_count_pkt_down_lut(3),
      O => Result_3_2
    );
  Mcount_data_count_pkt_down_cy_4_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(3),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(4),
      O => Mcount_data_count_pkt_down_cy(4)
    );
  Mcount_data_count_pkt_down_xor_4_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(3),
      LI => Mcount_data_count_pkt_down_lut(4),
      O => Result_4_2
    );
  Mcount_data_count_pkt_down_cy_5_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(4),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(5),
      O => Mcount_data_count_pkt_down_cy(5)
    );
  Mcount_data_count_pkt_down_xor_5_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(4),
      LI => Mcount_data_count_pkt_down_lut(5),
      O => Result_5_2
    );
  Mcount_data_count_pkt_down_cy_6_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(5),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(6),
      O => Mcount_data_count_pkt_down_cy(6)
    );
  Mcount_data_count_pkt_down_xor_6_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(5),
      LI => Mcount_data_count_pkt_down_lut(6),
      O => Result_6_2
    );
  Mcount_data_count_pkt_down_cy_7_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(6),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(7),
      O => Mcount_data_count_pkt_down_cy(7)
    );
  Mcount_data_count_pkt_down_xor_7_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(6),
      LI => Mcount_data_count_pkt_down_lut(7),
      O => Result_7_2
    );
  Mcount_data_count_pkt_down_cy_8_Q : MUXCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(7),
      DI => N1,
      S => Mcount_data_count_pkt_down_lut(8),
      O => Mcount_data_count_pkt_down_cy(8)
    );
  Mcount_data_count_pkt_down_xor_8_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(7),
      LI => Mcount_data_count_pkt_down_lut(8),
      O => Result_8_2
    );
  Mcount_data_count_pkt_down_xor_9_Q : XORCY
    port map (
      CI => Mcount_data_count_pkt_down_cy(8),
      LI => Mcount_data_count_pkt_down_lut(9),
      O => Result_9_1
    );
  Maccum_data_count_pkt_up_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(0),
      I1 => packet_size_int(0),
      O => Maccum_data_count_pkt_up_lut(0)
    );
  Maccum_data_count_pkt_up_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => data_count_pkt_up(0),
      S => Maccum_data_count_pkt_up_lut(0),
      O => Maccum_data_count_pkt_up_cy(0)
    );
  Maccum_data_count_pkt_up_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Maccum_data_count_pkt_up_lut(0),
      O => Result_0_3
    );
  Maccum_data_count_pkt_up_lut_1_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(1),
      I1 => packet_size_int(1),
      O => Maccum_data_count_pkt_up_lut(1)
    );
  Maccum_data_count_pkt_up_cy_1_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(0),
      DI => data_count_pkt_up(1),
      S => Maccum_data_count_pkt_up_lut(1),
      O => Maccum_data_count_pkt_up_cy(1)
    );
  Maccum_data_count_pkt_up_xor_1_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(0),
      LI => Maccum_data_count_pkt_up_lut(1),
      O => Result_1_3
    );
  Maccum_data_count_pkt_up_lut_2_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(2),
      I1 => packet_size_int(2),
      O => Maccum_data_count_pkt_up_lut(2)
    );
  Maccum_data_count_pkt_up_cy_2_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(1),
      DI => data_count_pkt_up(2),
      S => Maccum_data_count_pkt_up_lut(2),
      O => Maccum_data_count_pkt_up_cy(2)
    );
  Maccum_data_count_pkt_up_xor_2_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(1),
      LI => Maccum_data_count_pkt_up_lut(2),
      O => Result_2_3
    );
  Maccum_data_count_pkt_up_lut_3_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(3),
      I1 => packet_size_int(3),
      O => Maccum_data_count_pkt_up_lut(3)
    );
  Maccum_data_count_pkt_up_cy_3_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(2),
      DI => data_count_pkt_up(3),
      S => Maccum_data_count_pkt_up_lut(3),
      O => Maccum_data_count_pkt_up_cy(3)
    );
  Maccum_data_count_pkt_up_xor_3_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(2),
      LI => Maccum_data_count_pkt_up_lut(3),
      O => Result_3_3
    );
  Maccum_data_count_pkt_up_lut_4_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(4),
      I1 => packet_size_int(4),
      O => Maccum_data_count_pkt_up_lut(4)
    );
  Maccum_data_count_pkt_up_cy_4_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(3),
      DI => data_count_pkt_up(4),
      S => Maccum_data_count_pkt_up_lut(4),
      O => Maccum_data_count_pkt_up_cy(4)
    );
  Maccum_data_count_pkt_up_xor_4_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(3),
      LI => Maccum_data_count_pkt_up_lut(4),
      O => Result_4_3
    );
  Maccum_data_count_pkt_up_lut_5_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(5),
      I1 => packet_size_int(5),
      O => Maccum_data_count_pkt_up_lut(5)
    );
  Maccum_data_count_pkt_up_cy_5_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(4),
      DI => data_count_pkt_up(5),
      S => Maccum_data_count_pkt_up_lut(5),
      O => Maccum_data_count_pkt_up_cy(5)
    );
  Maccum_data_count_pkt_up_xor_5_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(4),
      LI => Maccum_data_count_pkt_up_lut(5),
      O => Result_5_3
    );
  Maccum_data_count_pkt_up_lut_6_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(6),
      I1 => packet_size_int(6),
      O => Maccum_data_count_pkt_up_lut(6)
    );
  Maccum_data_count_pkt_up_cy_6_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(5),
      DI => data_count_pkt_up(6),
      S => Maccum_data_count_pkt_up_lut(6),
      O => Maccum_data_count_pkt_up_cy(6)
    );
  Maccum_data_count_pkt_up_xor_6_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(5),
      LI => Maccum_data_count_pkt_up_lut(6),
      O => Result_6_3
    );
  Maccum_data_count_pkt_up_lut_7_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(7),
      I1 => packet_size_int(7),
      O => Maccum_data_count_pkt_up_lut(7)
    );
  Maccum_data_count_pkt_up_cy_7_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(6),
      DI => data_count_pkt_up(7),
      S => Maccum_data_count_pkt_up_lut(7),
      O => Maccum_data_count_pkt_up_cy(7)
    );
  Maccum_data_count_pkt_up_xor_7_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(6),
      LI => Maccum_data_count_pkt_up_lut(7),
      O => Result_7_3
    );
  Maccum_data_count_pkt_up_lut_8_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => data_count_pkt_up(8),
      I1 => packet_size_int(8),
      O => Maccum_data_count_pkt_up_lut(8)
    );
  Maccum_data_count_pkt_up_cy_8_Q : MUXCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(7),
      DI => data_count_pkt_up(8),
      S => Maccum_data_count_pkt_up_lut(8),
      O => Maccum_data_count_pkt_up_cy(8)
    );
  Maccum_data_count_pkt_up_xor_8_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(7),
      LI => Maccum_data_count_pkt_up_lut(8),
      O => Result_8_3
    );
  Maccum_data_count_pkt_up_xor_9_Q : XORCY
    port map (
      CI => Maccum_data_count_pkt_up_cy(8),
      LI => Maccum_data_count_pkt_up_xor_9_rt_26127,
      O => Result_9_2
    );
  full_not000111 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(7),
      I1 => NlwRenamedSig_OI_data_count_int(9),
      I2 => NlwRenamedSig_OI_data_count_int(8),
      I3 => NlwRenamedSig_OI_data_count_int(5),
      O => N10
    );
  clear_addr_d_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => rewind,
      I1 => clear_addr,
      O => clear_addr_d_and0000
    );
  output_stage_empty_mux00001 : LUT3
    generic map(
      INIT => X"57"
    )
    port map (
      I0 => internal_fifo_newdata_26517,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      O => output_stage_empty_mux0000
    );
  bram_waddr_not00011 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => rewind,
      I1 => NlwRenamedSig_OI_full,
      I2 => wr_en,
      O => bram_waddr_not0001
    );
  internal_fifo_newdata_take1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => internal_fifo_newdata_26517,
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => rd_en,
      O => internal_fifo_newdata_take
    );
  empty_int_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => data_count_pkt(5),
      I1 => data_count_pkt(4),
      I2 => data_count_pkt(3),
      I3 => data_count_pkt(2),
      I4 => data_count_pkt(1),
      I5 => clear_addr_d_26394,
      O => N01
    );
  empty_int_mux0000 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => data_count_pkt_down_not0001,
      I1 => data_count_pkt(9),
      I2 => data_count_pkt(8),
      I3 => data_count_pkt(7),
      I4 => data_count_pkt(6),
      I5 => N01,
      O => empty_int_mux0000_26513
    );
  full_not00011 : LUT6
    generic map(
      INIT => X"F888888888888888"
    )
    port map (
      I0 => data_count_pkt_down_not0001,
      I1 => N11,
      I2 => NlwRenamedSig_OI_data_count_int(4),
      I3 => NlwRenamedSig_OI_data_count_int(6),
      I4 => N9,
      I5 => N10,
      O => full_not0001
    );
  afull_not0001211 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(1),
      I1 => NlwRenamedSig_OI_data_count_int(0),
      I2 => NlwRenamedSig_OI_data_count_int(2),
      I3 => NlwRenamedSig_OI_data_count_int(3),
      I4 => data_count_pkt_down_not0001,
      I5 => N11,
      O => N9
    );
  afull_not000111 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => rewind,
      I1 => wr_en,
      I2 => NlwRenamedSig_OI_full,
      O => N11
    );
  afull_not0001_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(3),
      I1 => NlwRenamedSig_OI_data_count_int(2),
      I2 => NlwRenamedSig_OI_data_count_int(1),
      I3 => NlwRenamedSig_OI_data_count_int(0),
      O => N2
    );
  afull_not0001 : LUT6
    generic map(
      INIT => X"0200020002000A08"
    )
    port map (
      I0 => N10,
      I1 => NlwRenamedSig_OI_data_count_int(4),
      I2 => NlwRenamedSig_OI_data_count_int(6),
      I3 => N9,
      I4 => data_count_int_not0003,
      I5 => N2,
      O => afull_not0001_26301
    );
  output_stage_empty_not00011 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => internal_fifo_newdata_26517,
      I1 => NlwRenamedSig_OI_output_stage_empty,
      I2 => rd_en,
      O => output_stage_empty_not0001
    );
  Mcount_bram_raddr_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(1),
      O => Mcount_bram_raddr_cy_1_rt_26149
    );
  Mcount_bram_raddr_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(2),
      O => Mcount_bram_raddr_cy_2_rt_26151
    );
  Mcount_bram_raddr_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(3),
      O => Mcount_bram_raddr_cy_3_rt_26153
    );
  Mcount_bram_raddr_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(4),
      O => Mcount_bram_raddr_cy_4_rt_26155
    );
  Mcount_bram_raddr_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(5),
      O => Mcount_bram_raddr_cy_5_rt_26157
    );
  Mcount_bram_raddr_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(6),
      O => Mcount_bram_raddr_cy_6_rt_26159
    );
  Mcount_bram_raddr_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(7),
      O => Mcount_bram_raddr_cy_7_rt_26161
    );
  Mcount_data_count_pkt_down_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_count_pkt_down(0),
      O => Mcount_data_count_pkt_down_cy_0_rt_26210
    );
  Mcount_bram_raddr_xor_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => bram_raddr(8),
      O => Mcount_bram_raddr_xor_8_rt_26163
    );
  Maccum_data_count_pkt_up_xor_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_count_pkt_up(9),
      O => Maccum_data_count_pkt_up_xor_9_rt_26127
    );
  wr_en_int1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => wr_en,
      I1 => rewind,
      I2 => NlwRenamedSig_OI_full,
      O => wr_en_int
    );
  rewind_addr_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => wr_en,
      I1 => rewind,
      I2 => NlwRenamedSig_OI_full,
      I3 => mark_addr,
      O => rewind_addr_not0001
    );
  internal_fifo_newdata_not00011 : LUT4
    generic map(
      INIT => X"F2A2"
    )
    port map (
      I0 => rd_en,
      I1 => empty_int_26512,
      I2 => internal_fifo_newdata_26517,
      I3 => NlwRenamedSig_OI_output_stage_empty,
      O => internal_fifo_newdata_not0001
    );
  rd_en_fwft1 : LUT4
    generic map(
      INIT => X"5540"
    )
    port map (
      I0 => empty_int_26512,
      I1 => internal_fifo_newdata_26517,
      I2 => NlwRenamedSig_OI_output_stage_empty,
      I3 => rd_en,
      O => data_count_pkt_down_not0001
    );
  data_count_int_not00021 : LUT4
    generic map(
      INIT => X"AA9A"
    )
    port map (
      I0 => data_count_pkt_down_not0001,
      I1 => rewind,
      I2 => wr_en,
      I3 => NlwRenamedSig_OI_full,
      O => data_count_int_not0002
    );
  empty_int_not00011 : LUT5
    generic map(
      INIT => X"FFFF3222"
    )
    port map (
      I0 => rd_en,
      I1 => empty_int_26512,
      I2 => internal_fifo_newdata_26517,
      I3 => NlwRenamedSig_OI_output_stage_empty,
      I4 => clear_addr_d_26394,
      O => empty_int_not0001
    );
  data_count_int_not00031 : LUT5
    generic map(
      INIT => X"FFFF13FF"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => internal_fifo_newdata_26517,
      I3 => N11,
      I4 => empty_int_26512,
      O => data_count_int_not0003
    );
  data_count_int_and00011 : LUT5
    generic map(
      INIT => X"0C080808"
    )
    port map (
      I0 => rd_en,
      I1 => N11,
      I2 => empty_int_26512,
      I3 => internal_fifo_newdata_26517,
      I4 => NlwRenamedSig_OI_output_stage_empty,
      O => data_count_int_not0003_inv
    );
  Mcount_data_count_int_lut_0_Q : LUT6
    generic map(
      INIT => X"55555555A9A55555"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_count_int(0),
      I1 => internal_fifo_newdata_26517,
      I2 => rd_en,
      I3 => NlwRenamedSig_OI_output_stage_empty,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(0)
    );
  Mcount_data_count_int_lut_1_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(1),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(1)
    );
  Mcount_data_count_int_lut_2_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(2),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(2)
    );
  Mcount_data_count_int_lut_3_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(3),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(3)
    );
  Mcount_data_count_int_lut_4_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(4),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(4)
    );
  Mcount_data_count_int_lut_5_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(5),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(5)
    );
  Mcount_data_count_int_lut_6_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(6),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(6)
    );
  Mcount_data_count_int_lut_7_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(7),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(7)
    );
  Mcount_data_count_int_lut_8_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(8),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(8)
    );
  Mcount_data_count_int_lut_9_Q : LUT6
    generic map(
      INIT => X"F0F0F0F01E3CF0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_output_stage_empty,
      I1 => rd_en,
      I2 => NlwRenamedSig_OI_data_count_int(9),
      I3 => internal_fifo_newdata_26517,
      I4 => N11,
      I5 => empty_int_26512,
      O => Mcount_data_count_int_lut(9)
    );
  Mcount_bram_raddr_lut_0_INV_0 : INV
    port map (
      I => bram_raddr(0),
      O => Mcount_bram_raddr_lut(0)
    );
  Mcount_data_count_pkt_down_lut_1_INV_0 : INV
    port map (
      I => data_count_pkt_down(1),
      O => Mcount_data_count_pkt_down_lut(1)
    );
  Mcount_data_count_pkt_down_lut_2_INV_0 : INV
    port map (
      I => data_count_pkt_down(2),
      O => Mcount_data_count_pkt_down_lut(2)
    );
  Mcount_data_count_pkt_down_lut_3_INV_0 : INV
    port map (
      I => data_count_pkt_down(3),
      O => Mcount_data_count_pkt_down_lut(3)
    );
  Mcount_data_count_pkt_down_lut_4_INV_0 : INV
    port map (
      I => data_count_pkt_down(4),
      O => Mcount_data_count_pkt_down_lut(4)
    );
  Mcount_data_count_pkt_down_lut_5_INV_0 : INV
    port map (
      I => data_count_pkt_down(5),
      O => Mcount_data_count_pkt_down_lut(5)
    );
  Mcount_data_count_pkt_down_lut_6_INV_0 : INV
    port map (
      I => data_count_pkt_down(6),
      O => Mcount_data_count_pkt_down_lut(6)
    );
  Mcount_data_count_pkt_down_lut_7_INV_0 : INV
    port map (
      I => data_count_pkt_down(7),
      O => Mcount_data_count_pkt_down_lut(7)
    );
  Mcount_data_count_pkt_down_lut_8_INV_0 : INV
    port map (
      I => data_count_pkt_down(8),
      O => Mcount_data_count_pkt_down_lut(8)
    );
  Mcount_data_count_pkt_down_lut_9_INV_0 : INV
    port map (
      I => data_count_pkt_down(9),
      O => Mcount_data_count_pkt_down_lut(9)
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  mark_addr_inv1_INV_0 : INV
    port map (
      I => mark_addr,
      O => mark_addr_inv
    );
  rewind_inv1_INV_0 : INV
    port map (
      I => rewind,
      O => rewind_inv
    );
  Mram_regBank : RAMB36SDP_EXP
    generic map(
      DO_REG => 0,
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "ALL",
      EN_ECC_WRITE => FALSE,
      EN_ECC_READ => FALSE,
      EN_ECC_SCRUB => FALSE,
      INIT => X"000000000000000000",
      SRVAL => X"000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      RDENU => data_count_pkt_down_not0001,
      RDENL => data_count_pkt_down_not0001,
      WRENU => N1,
      WRENL => N1,
      SSRU => N0,
      SSRL => N0,
      RDCLKU => clk,
      RDCLKL => clk,
      WRCLKU => clk,
      WRCLKL => clk,
      RDRCLKU => clk,
      RDRCLKL => clk,
      REGCEU => N0,
      REGCEL => N0,
      SBITERR => NLW_Mram_regBank_SBITERR_UNCONNECTED,
      DBITERR => NLW_Mram_regBank_DBITERR_UNCONNECTED,
      DI(63) => din(63),
      DI(62) => din(62),
      DI(61) => din(61),
      DI(60) => din(60),
      DI(59) => din(59),
      DI(58) => din(58),
      DI(57) => din(57),
      DI(56) => din(56),
      DI(55) => din(55),
      DI(54) => din(54),
      DI(53) => din(53),
      DI(52) => din(52),
      DI(51) => din(51),
      DI(50) => din(50),
      DI(49) => din(49),
      DI(48) => din(48),
      DI(47) => din(47),
      DI(46) => din(46),
      DI(45) => din(45),
      DI(44) => din(44),
      DI(43) => din(43),
      DI(42) => din(42),
      DI(41) => din(41),
      DI(40) => din(40),
      DI(39) => din(39),
      DI(38) => din(38),
      DI(37) => din(37),
      DI(36) => din(36),
      DI(35) => din(35),
      DI(34) => din(34),
      DI(33) => din(33),
      DI(32) => din(32),
      DI(31) => din(31),
      DI(30) => din(30),
      DI(29) => din(29),
      DI(28) => din(28),
      DI(27) => din(27),
      DI(26) => din(26),
      DI(25) => din(25),
      DI(24) => din(24),
      DI(23) => din(23),
      DI(22) => din(22),
      DI(21) => din(21),
      DI(20) => din(20),
      DI(19) => din(19),
      DI(18) => din(18),
      DI(17) => din(17),
      DI(16) => din(16),
      DI(15) => din(15),
      DI(14) => din(14),
      DI(13) => din(13),
      DI(12) => din(12),
      DI(11) => din(11),
      DI(10) => din(10),
      DI(9) => din(9),
      DI(8) => din(8),
      DI(7) => din(7),
      DI(6) => din(6),
      DI(5) => din(5),
      DI(4) => din(4),
      DI(3) => din(3),
      DI(2) => din(2),
      DI(1) => din(1),
      DI(0) => din(0),
      DIP(7) => din(71),
      DIP(6) => din(70),
      DIP(5) => din(69),
      DIP(4) => din(68),
      DIP(3) => din(67),
      DIP(2) => din(66),
      DIP(1) => din(65),
      DIP(0) => din(64),
      RDADDRL(15) => N1,
      RDADDRL(14) => bram_raddr(8),
      RDADDRL(13) => bram_raddr(7),
      RDADDRL(12) => bram_raddr(6),
      RDADDRL(11) => bram_raddr(5),
      RDADDRL(10) => bram_raddr(4),
      RDADDRL(9) => bram_raddr(3),
      RDADDRL(8) => bram_raddr(2),
      RDADDRL(7) => bram_raddr(1),
      RDADDRL(6) => bram_raddr(0),
      RDADDRL(5) => NLW_Mram_regBank_RDADDRL_5_UNCONNECTED,
      RDADDRL(4) => NLW_Mram_regBank_RDADDRL_4_UNCONNECTED,
      RDADDRL(3) => NLW_Mram_regBank_RDADDRL_3_UNCONNECTED,
      RDADDRL(2) => NLW_Mram_regBank_RDADDRL_2_UNCONNECTED,
      RDADDRL(1) => NLW_Mram_regBank_RDADDRL_1_UNCONNECTED,
      RDADDRL(0) => NLW_Mram_regBank_RDADDRL_0_UNCONNECTED,
      RDADDRU(14) => bram_raddr(8),
      RDADDRU(13) => bram_raddr(7),
      RDADDRU(12) => bram_raddr(6),
      RDADDRU(11) => bram_raddr(5),
      RDADDRU(10) => bram_raddr(4),
      RDADDRU(9) => bram_raddr(3),
      RDADDRU(8) => bram_raddr(2),
      RDADDRU(7) => bram_raddr(1),
      RDADDRU(6) => bram_raddr(0),
      RDADDRU(5) => NLW_Mram_regBank_RDADDRU_5_UNCONNECTED,
      RDADDRU(4) => NLW_Mram_regBank_RDADDRU_4_UNCONNECTED,
      RDADDRU(3) => NLW_Mram_regBank_RDADDRU_3_UNCONNECTED,
      RDADDRU(2) => NLW_Mram_regBank_RDADDRU_2_UNCONNECTED,
      RDADDRU(1) => NLW_Mram_regBank_RDADDRU_1_UNCONNECTED,
      RDADDRU(0) => NLW_Mram_regBank_RDADDRU_0_UNCONNECTED,
      WRADDRL(15) => N1,
      WRADDRL(14) => bram_waddr(8),
      WRADDRL(13) => bram_waddr(7),
      WRADDRL(12) => bram_waddr(6),
      WRADDRL(11) => bram_waddr(5),
      WRADDRL(10) => bram_waddr(4),
      WRADDRL(9) => bram_waddr(3),
      WRADDRL(8) => bram_waddr(2),
      WRADDRL(7) => bram_waddr(1),
      WRADDRL(6) => bram_waddr(0),
      WRADDRL(5) => NLW_Mram_regBank_WRADDRL_5_UNCONNECTED,
      WRADDRL(4) => NLW_Mram_regBank_WRADDRL_4_UNCONNECTED,
      WRADDRL(3) => NLW_Mram_regBank_WRADDRL_3_UNCONNECTED,
      WRADDRL(2) => NLW_Mram_regBank_WRADDRL_2_UNCONNECTED,
      WRADDRL(1) => NLW_Mram_regBank_WRADDRL_1_UNCONNECTED,
      WRADDRL(0) => NLW_Mram_regBank_WRADDRL_0_UNCONNECTED,
      WRADDRU(14) => bram_waddr(8),
      WRADDRU(13) => bram_waddr(7),
      WRADDRU(12) => bram_waddr(6),
      WRADDRU(11) => bram_waddr(5),
      WRADDRU(10) => bram_waddr(4),
      WRADDRU(9) => bram_waddr(3),
      WRADDRU(8) => bram_waddr(2),
      WRADDRU(7) => bram_waddr(1),
      WRADDRU(6) => bram_waddr(0),
      WRADDRU(5) => NLW_Mram_regBank_WRADDRU_5_UNCONNECTED,
      WRADDRU(4) => NLW_Mram_regBank_WRADDRU_4_UNCONNECTED,
      WRADDRU(3) => NLW_Mram_regBank_WRADDRU_3_UNCONNECTED,
      WRADDRU(2) => NLW_Mram_regBank_WRADDRU_2_UNCONNECTED,
      WRADDRU(1) => NLW_Mram_regBank_WRADDRU_1_UNCONNECTED,
      WRADDRU(0) => NLW_Mram_regBank_WRADDRU_0_UNCONNECTED,
      WEU(7) => wr_en_int,
      WEU(6) => wr_en_int,
      WEU(5) => wr_en_int,
      WEU(4) => wr_en_int,
      WEU(3) => wr_en_int,
      WEU(2) => wr_en_int,
      WEU(1) => wr_en_int,
      WEU(0) => wr_en_int,
      WEL(7) => wr_en_int,
      WEL(6) => wr_en_int,
      WEL(5) => wr_en_int,
      WEL(4) => wr_en_int,
      WEL(3) => wr_en_int,
      WEL(2) => wr_en_int,
      WEL(1) => wr_en_int,
      WEL(0) => wr_en_int,
      DO(63) => bram_style_fifo_dout_reg(63),
      DO(62) => bram_style_fifo_dout_reg(62),
      DO(61) => bram_style_fifo_dout_reg(61),
      DO(60) => bram_style_fifo_dout_reg(60),
      DO(59) => bram_style_fifo_dout_reg(59),
      DO(58) => bram_style_fifo_dout_reg(58),
      DO(57) => bram_style_fifo_dout_reg(57),
      DO(56) => bram_style_fifo_dout_reg(56),
      DO(55) => bram_style_fifo_dout_reg(55),
      DO(54) => bram_style_fifo_dout_reg(54),
      DO(53) => bram_style_fifo_dout_reg(53),
      DO(52) => bram_style_fifo_dout_reg(52),
      DO(51) => bram_style_fifo_dout_reg(51),
      DO(50) => bram_style_fifo_dout_reg(50),
      DO(49) => bram_style_fifo_dout_reg(49),
      DO(48) => bram_style_fifo_dout_reg(48),
      DO(47) => bram_style_fifo_dout_reg(47),
      DO(46) => bram_style_fifo_dout_reg(46),
      DO(45) => bram_style_fifo_dout_reg(45),
      DO(44) => bram_style_fifo_dout_reg(44),
      DO(43) => bram_style_fifo_dout_reg(43),
      DO(42) => bram_style_fifo_dout_reg(42),
      DO(41) => bram_style_fifo_dout_reg(41),
      DO(40) => bram_style_fifo_dout_reg(40),
      DO(39) => bram_style_fifo_dout_reg(39),
      DO(38) => bram_style_fifo_dout_reg(38),
      DO(37) => bram_style_fifo_dout_reg(37),
      DO(36) => bram_style_fifo_dout_reg(36),
      DO(35) => bram_style_fifo_dout_reg(35),
      DO(34) => bram_style_fifo_dout_reg(34),
      DO(33) => bram_style_fifo_dout_reg(33),
      DO(32) => bram_style_fifo_dout_reg(32),
      DO(31) => bram_style_fifo_dout_reg(31),
      DO(30) => bram_style_fifo_dout_reg(30),
      DO(29) => bram_style_fifo_dout_reg(29),
      DO(28) => bram_style_fifo_dout_reg(28),
      DO(27) => bram_style_fifo_dout_reg(27),
      DO(26) => bram_style_fifo_dout_reg(26),
      DO(25) => bram_style_fifo_dout_reg(25),
      DO(24) => bram_style_fifo_dout_reg(24),
      DO(23) => bram_style_fifo_dout_reg(23),
      DO(22) => bram_style_fifo_dout_reg(22),
      DO(21) => bram_style_fifo_dout_reg(21),
      DO(20) => bram_style_fifo_dout_reg(20),
      DO(19) => bram_style_fifo_dout_reg(19),
      DO(18) => bram_style_fifo_dout_reg(18),
      DO(17) => bram_style_fifo_dout_reg(17),
      DO(16) => bram_style_fifo_dout_reg(16),
      DO(15) => bram_style_fifo_dout_reg(15),
      DO(14) => bram_style_fifo_dout_reg(14),
      DO(13) => bram_style_fifo_dout_reg(13),
      DO(12) => bram_style_fifo_dout_reg(12),
      DO(11) => bram_style_fifo_dout_reg(11),
      DO(10) => bram_style_fifo_dout_reg(10),
      DO(9) => bram_style_fifo_dout_reg(9),
      DO(8) => bram_style_fifo_dout_reg(8),
      DO(7) => bram_style_fifo_dout_reg(7),
      DO(6) => bram_style_fifo_dout_reg(6),
      DO(5) => bram_style_fifo_dout_reg(5),
      DO(4) => bram_style_fifo_dout_reg(4),
      DO(3) => bram_style_fifo_dout_reg(3),
      DO(2) => bram_style_fifo_dout_reg(2),
      DO(1) => bram_style_fifo_dout_reg(1),
      DO(0) => bram_style_fifo_dout_reg(0),
      DOP(7) => bram_style_fifo_dout_reg(71),
      DOP(6) => bram_style_fifo_dout_reg(70),
      DOP(5) => bram_style_fifo_dout_reg(69),
      DOP(4) => bram_style_fifo_dout_reg(68),
      DOP(3) => bram_style_fifo_dout_reg(67),
      DOP(2) => bram_style_fifo_dout_reg(66),
      DOP(1) => bram_style_fifo_dout_reg(65),
      DOP(0) => bram_style_fifo_dout_reg(64),
      ECCPARITY(7) => NLW_Mram_regBank_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => NLW_Mram_regBank_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => NLW_Mram_regBank_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => NLW_Mram_regBank_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => NLW_Mram_regBank_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => NLW_Mram_regBank_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => NLW_Mram_regBank_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => NLW_Mram_regBank_ECCPARITY_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll_oqbqfifo is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    fifo_rem : in STD_LOGIC := 'X'; 
    trn_rsof : out STD_LOGIC; 
    trn_rdst_rdy : in STD_LOGIC := 'X'; 
    fifo_pcpl_ok : out STD_LOGIC; 
    fifo_np_ok : out STD_LOGIC; 
    trn_reof : out STD_LOGIC; 
    trn_rsrc_rdy : out STD_LOGIC; 
    fifo_preeof : in STD_LOGIC := 'X'; 
    fifo_wren : in STD_LOGIC := 'X'; 
    fifo_sof : in STD_LOGIC := 'X'; 
    fifo_dsc : in STD_LOGIC := 'X'; 
    trn_rnp_ok : in STD_LOGIC := 'X'; 
    fifo_eof : in STD_LOGIC := 'X'; 
    trn_rerrfwd : out STD_LOGIC; 
    fifo_pcpl_req : in STD_LOGIC := 'X'; 
    fifo_np : in STD_LOGIC := 'X'; 
    fifo_np_req : in STD_LOGIC := 'X'; 
    fifo_pcpl_abort : in STD_LOGIC := 'X'; 
    fifo_np_abort : in STD_LOGIC := 'X'; 
    trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_rrem : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    fifo_barenc : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end pcie_blk_ll_oqbqfifo;

architecture STRUCTURE of pcie_blk_ll_oqbqfifo is
  component sync_fifo_1
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      rd_en : in STD_LOGIC := 'X'; 
      afull : out STD_LOGIC; 
      empty : out STD_LOGIC; 
      rewind : in STD_LOGIC := 'X'; 
      wr_en : in STD_LOGIC := 'X'; 
      mark_addr : in STD_LOGIC := 'X'; 
      clear_addr : in STD_LOGIC := 'X'; 
      full : out STD_LOGIC; 
      aempty : out STD_LOGIC; 
      data_count : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      dout : out STD_LOGIC_VECTOR ( 71 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 71 downto 0 ) 
    );
  end component;
  component sync_fifo_2
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      rd_en : in STD_LOGIC := 'X'; 
      afull : out STD_LOGIC; 
      empty : out STD_LOGIC; 
      rewind : in STD_LOGIC := 'X'; 
      wr_en : in STD_LOGIC := 'X'; 
      mark_addr : in STD_LOGIC := 'X'; 
      clear_addr : in STD_LOGIC := 'X'; 
      full : out STD_LOGIC; 
      aempty : out STD_LOGIC; 
      data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
      dout : out STD_LOGIC_VECTOR ( 71 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 71 downto 0 ) 
    );
  end component;
  signal N01 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N321 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N65 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Q_and0000 : STD_LOGIC; 
  signal Q_and0001 : STD_LOGIC; 
  signal Q_and0002 : STD_LOGIC; 
  signal bq_empty : STD_LOGIC; 
  signal bq_pkt_avail_26991 : STD_LOGIC; 
  signal bq_pkt_avail_mux0000 : STD_LOGIC; 
  signal bq_pkt_avail_mux00001_26993 : STD_LOGIC; 
  signal bq_pkt_avail_mux00002_26994 : STD_LOGIC; 
  signal bq_pktcnt_and0000 : STD_LOGIC; 
  signal bq_pktcnt_not0001_27000 : STD_LOGIC; 
  signal bq_rden : STD_LOGIC; 
  signal bq_trn_in_progress : STD_LOGIC; 
  signal fifo_discard_np_27072 : STD_LOGIC; 
  signal fifo_discard_np_and0000 : STD_LOGIC; 
  signal fifo_np_ok_and0000 : STD_LOGIC; 
  signal fifo_pcpl_ok_not0001 : STD_LOGIC; 
  signal new_oq_pkt_wr_27085 : STD_LOGIC; 
  signal new_oq_pkt_wr_and0000 : STD_LOGIC; 
  signal new_oq_pkt_wr_d_27087 : STD_LOGIC; 
  signal new_oq_pkt_wr_d2_27088 : STD_LOGIC; 
  signal nonposted_or_rem_27089 : STD_LOGIC; 
  signal oq_afull : STD_LOGIC; 
  signal oq_empty : STD_LOGIC; 
  signal oq_pkt_avail_27172 : STD_LOGIC; 
  signal oq_pkt_avail_mux0000 : STD_LOGIC; 
  signal oq_pkt_avail_mux00006_27174 : STD_LOGIC; 
  signal oq_pktcnt_and0000 : STD_LOGIC; 
  signal oq_pktcnt_and0000_inv : STD_LOGIC; 
  signal oq_pktcnt_not0001 : STD_LOGIC; 
  signal oq_rden : STD_LOGIC; 
  signal oq_wren : STD_LOGIC; 
  signal oq_write_pkt_in_progress_reg_27189 : STD_LOGIC; 
  signal oq_write_pkt_in_progress_reg_and0001 : STD_LOGIC; 
  signal packet_in_progress_27191 : STD_LOGIC; 
  signal packet_in_progress_bq_27192 : STD_LOGIC; 
  signal packet_in_progress_bq_mux0000 : STD_LOGIC; 
  signal packet_in_progress_mux0000 : STD_LOGIC; 
  signal packet_in_progress_mux00001_27195 : STD_LOGIC; 
  signal packet_in_progress_mux00002_27196 : STD_LOGIC; 
  signal packet_in_progress_not0001 : STD_LOGIC; 
  signal packet_in_progress_oq_27198 : STD_LOGIC; 
  signal packet_in_progress_oq_mux0000 : STD_LOGIC; 
  signal packet_in_progress_oq_mux00001_27200 : STD_LOGIC; 
  signal packet_in_progress_oq_mux00002_27201 : STD_LOGIC; 
  signal packet_in_progress_or0000 : STD_LOGIC; 
  signal poisoned : STD_LOGIC; 
  signal poisoned_reg_27204 : STD_LOGIC; 
  signal poisoned_reg_mux0000 : STD_LOGIC; 
  signal poisoned_reg_not0001 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal trn_drain_np_27209 : STD_LOGIC; 
  signal trn_drain_np_and0000 : STD_LOGIC; 
  signal trn_np_27211 : STD_LOGIC; 
  signal trn_np_and0000_27212 : STD_LOGIC; 
  signal trn_np_and0001 : STD_LOGIC; 
  signal trn_rd_not0001_27346 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_reof : STD_LOGIC; 
  signal trn_reof_mux0000_27349 : STD_LOGIC; 
  signal trn_reof_not0001 : STD_LOGIC; 
  signal trn_rerrfwd_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_rsof : STD_LOGIC; 
  signal trn_rsof_and0000 : STD_LOGIC; 
  signal trn_rsof_mux0000 : STD_LOGIC; 
  signal trn_rsof_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_rsrc_rdy : STD_LOGIC; 
  signal trn_rsrc_rdy_mux0000 : STD_LOGIC; 
  signal trn_rsrc_rdy_mux00001_27361 : STD_LOGIC; 
  signal trn_rsrc_rdy_mux00002_27362 : STD_LOGIC; 
  signal trn_rsrc_rdy_not0001 : STD_LOGIC; 
  signal NLW_bq_fifo_afull_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_aempty_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_data_count_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_data_count_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_data_count_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_data_count_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_bq_fifo_data_count_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_aempty_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_oq_fifo_data_count_0_UNCONNECTED : STD_LOGIC; 
  signal Mcount_oq_pktcnt_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcount_oq_pktcnt_lut : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal bq_dout : STD_LOGIC_VECTOR ( 71 downto 0 ); 
  signal bq_pktcnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal np_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal np_count_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal oq_dout : STD_LOGIC_VECTOR ( 71 downto 0 ); 
  signal oq_pktcnt : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal trn_rbar_hit_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_trn_rd : STD_LOGIC_VECTOR ( 62 downto 56 ); 
  signal trn_rd_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal trn_rrem_mux0000 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  trn_rsof <= NlwRenamedSig_OI_trn_rsof;
  trn_reof <= NlwRenamedSig_OI_trn_reof;
  trn_rsrc_rdy <= NlwRenamedSig_OI_trn_rsrc_rdy;
  trn_rd(62) <= NlwRenamedSig_OI_trn_rd(62);
  trn_rd(61) <= NlwRenamedSig_OI_trn_rd(61);
  trn_rd(60) <= NlwRenamedSig_OI_trn_rd(60);
  trn_rd(59) <= NlwRenamedSig_OI_trn_rd(59);
  trn_rd(58) <= NlwRenamedSig_OI_trn_rd(58);
  trn_rd(57) <= NlwRenamedSig_OI_trn_rd(57);
  trn_rd(56) <= NlwRenamedSig_OI_trn_rd(56);
  XST_GND : GND
    port map (
      G => bq_pktcnt_and0000
    );
  oq_write_pkt_in_progress_reg : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_write_pkt_in_progress_reg_and0001,
      D => bq_pktcnt_and0000,
      R => rst_n_inv,
      S => Q_and0000,
      Q => oq_write_pkt_in_progress_reg_27189
    );
  trn_rd_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(0),
      R => rst_n_inv,
      Q => trn_rd(0)
    );
  trn_rd_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(1),
      R => rst_n_inv,
      Q => trn_rd(1)
    );
  trn_rd_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(2),
      R => rst_n_inv,
      Q => trn_rd(2)
    );
  trn_rd_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(3),
      R => rst_n_inv,
      Q => trn_rd(3)
    );
  trn_rd_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(4),
      R => rst_n_inv,
      Q => trn_rd(4)
    );
  trn_rd_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(5),
      R => rst_n_inv,
      Q => trn_rd(5)
    );
  trn_rd_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(6),
      R => rst_n_inv,
      Q => trn_rd(6)
    );
  trn_rd_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(7),
      R => rst_n_inv,
      Q => trn_rd(7)
    );
  trn_rd_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(8),
      R => rst_n_inv,
      Q => trn_rd(8)
    );
  trn_rd_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(9),
      R => rst_n_inv,
      Q => trn_rd(9)
    );
  trn_rd_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(10),
      R => rst_n_inv,
      Q => trn_rd(10)
    );
  trn_rd_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(11),
      R => rst_n_inv,
      Q => trn_rd(11)
    );
  trn_rd_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(12),
      R => rst_n_inv,
      Q => trn_rd(12)
    );
  trn_rd_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(13),
      R => rst_n_inv,
      Q => trn_rd(13)
    );
  trn_rd_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(14),
      R => rst_n_inv,
      Q => trn_rd(14)
    );
  trn_rd_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(15),
      R => rst_n_inv,
      Q => trn_rd(15)
    );
  trn_rd_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(16),
      R => rst_n_inv,
      Q => trn_rd(16)
    );
  trn_rd_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(17),
      R => rst_n_inv,
      Q => trn_rd(17)
    );
  trn_rd_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(18),
      R => rst_n_inv,
      Q => trn_rd(18)
    );
  trn_rd_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(19),
      R => rst_n_inv,
      Q => trn_rd(19)
    );
  trn_rd_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(20),
      R => rst_n_inv,
      Q => trn_rd(20)
    );
  trn_rd_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(21),
      R => rst_n_inv,
      Q => trn_rd(21)
    );
  trn_rd_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(22),
      R => rst_n_inv,
      Q => trn_rd(22)
    );
  trn_rd_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(23),
      R => rst_n_inv,
      Q => trn_rd(23)
    );
  trn_rd_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(24),
      R => rst_n_inv,
      Q => trn_rd(24)
    );
  trn_rd_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(25),
      R => rst_n_inv,
      Q => trn_rd(25)
    );
  trn_rd_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(26),
      R => rst_n_inv,
      Q => trn_rd(26)
    );
  trn_rd_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(27),
      R => rst_n_inv,
      Q => trn_rd(27)
    );
  trn_rd_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(28),
      R => rst_n_inv,
      Q => trn_rd(28)
    );
  trn_rd_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(29),
      R => rst_n_inv,
      Q => trn_rd(29)
    );
  trn_rd_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(30),
      R => rst_n_inv,
      Q => trn_rd(30)
    );
  trn_rd_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(31),
      R => rst_n_inv,
      Q => trn_rd(31)
    );
  trn_rd_32 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(32),
      R => rst_n_inv,
      Q => trn_rd(32)
    );
  trn_rd_33 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(33),
      R => rst_n_inv,
      Q => trn_rd(33)
    );
  trn_rd_34 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(34),
      R => rst_n_inv,
      Q => trn_rd(34)
    );
  trn_rd_35 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(35),
      R => rst_n_inv,
      Q => trn_rd(35)
    );
  trn_rd_36 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(36),
      R => rst_n_inv,
      Q => trn_rd(36)
    );
  trn_rd_37 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(37),
      R => rst_n_inv,
      Q => trn_rd(37)
    );
  trn_rd_38 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(38),
      R => rst_n_inv,
      Q => trn_rd(38)
    );
  trn_rd_39 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(39),
      R => rst_n_inv,
      Q => trn_rd(39)
    );
  trn_rd_40 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(40),
      R => rst_n_inv,
      Q => trn_rd(40)
    );
  trn_rd_41 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(41),
      R => rst_n_inv,
      Q => trn_rd(41)
    );
  trn_rd_42 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(42),
      R => rst_n_inv,
      Q => trn_rd(42)
    );
  trn_rd_43 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(43),
      R => rst_n_inv,
      Q => trn_rd(43)
    );
  trn_rd_44 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(44),
      R => rst_n_inv,
      Q => trn_rd(44)
    );
  trn_rd_45 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(45),
      R => rst_n_inv,
      Q => trn_rd(45)
    );
  trn_rd_46 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(46),
      R => rst_n_inv,
      Q => trn_rd(46)
    );
  trn_rd_47 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(47),
      R => rst_n_inv,
      Q => trn_rd(47)
    );
  trn_rd_48 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(48),
      R => rst_n_inv,
      Q => trn_rd(48)
    );
  trn_rd_49 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(49),
      R => rst_n_inv,
      Q => trn_rd(49)
    );
  trn_rd_50 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(50),
      R => rst_n_inv,
      Q => trn_rd(50)
    );
  trn_rd_51 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(51),
      R => rst_n_inv,
      Q => trn_rd(51)
    );
  trn_rd_52 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(52),
      R => rst_n_inv,
      Q => trn_rd(52)
    );
  trn_rd_53 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(53),
      R => rst_n_inv,
      Q => trn_rd(53)
    );
  trn_rd_54 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(54),
      R => rst_n_inv,
      Q => trn_rd(54)
    );
  trn_rd_55 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(55),
      R => rst_n_inv,
      Q => trn_rd(55)
    );
  trn_rd_56 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(56),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(56)
    );
  trn_rd_57 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(57),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(57)
    );
  trn_rd_58 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(58),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(58)
    );
  trn_rd_59 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(59),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(59)
    );
  trn_rd_60 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(60),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(60)
    );
  trn_rd_61 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(61),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(61)
    );
  trn_rd_62 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(62),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rd(62)
    );
  trn_rd_63 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rd_not0001_27346,
      D => trn_rd_mux0000(63),
      R => rst_n_inv,
      Q => trn_rd(63)
    );
  trn_rrem_0 : FDSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsof_not0001,
      D => trn_rrem_mux0000(0),
      S => rst_n_inv,
      Q => trn_rrem(0)
    );
  trn_rsof_14585 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsof_not0001,
      D => trn_rsof_mux0000,
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rsof
    );
  trn_reof_14586 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_reof_not0001,
      D => trn_reof_mux0000_27349,
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_reof
    );
  trn_rbar_hit_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsof_not0001,
      D => trn_rbar_hit_mux0000(0),
      R => rst_n_inv,
      Q => trn_rbar_hit(0)
    );
  trn_rbar_hit_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsof_not0001,
      D => trn_rbar_hit_mux0000(1),
      R => rst_n_inv,
      Q => trn_rbar_hit(1)
    );
  trn_rsrc_rdy_14589 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsrc_rdy_not0001,
      D => trn_rsrc_rdy_mux0000,
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_rsrc_rdy
    );
  packet_in_progress_bq : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => packet_in_progress_not0001,
      D => packet_in_progress_bq_mux0000,
      R => packet_in_progress_or0000,
      Q => packet_in_progress_bq_27192
    );
  trn_rerrfwd_14591 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_rsof_not0001,
      D => trn_rerrfwd_mux0000,
      R => rst_n_inv,
      Q => trn_rerrfwd
    );
  packet_in_progress : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => packet_in_progress_not0001,
      D => packet_in_progress_mux0000,
      R => packet_in_progress_or0000,
      Q => packet_in_progress_27191
    );
  packet_in_progress_oq : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => packet_in_progress_not0001,
      D => packet_in_progress_oq_mux0000,
      R => packet_in_progress_or0000,
      Q => packet_in_progress_oq_27198
    );
  poisoned_reg : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => poisoned_reg_not0001,
      D => poisoned_reg_mux0000,
      R => rst_n_inv,
      Q => poisoned_reg_27204
    );
  fifo_np_ok_14595 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => fifo_np_ok_and0000,
      S => rst_n_inv,
      Q => fifo_np_ok
    );
  fifo_pcpl_ok_14596 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => fifo_pcpl_ok_not0001,
      S => rst_n_inv,
      Q => fifo_pcpl_ok
    );
  trn_np : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trn_np_and0001,
      D => bq_pktcnt_and0000,
      R => rst_n_inv,
      S => trn_np_and0000_27212,
      Q => trn_np_27211
    );
  trn_drain_np : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => trn_drain_np_and0000,
      R => rst_n_inv,
      Q => trn_drain_np_27209
    );
  fifo_discard_np : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => fifo_discard_np_and0000,
      R => rst_n_inv,
      Q => fifo_discard_np_27072
    );
  np_count_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => np_count_mux0000(0),
      R => rst_n_inv,
      Q => np_count(0)
    );
  np_count_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => np_count_mux0000(1),
      R => rst_n_inv,
      Q => np_count(1)
    );
  np_count_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => np_count_mux0000(2),
      R => rst_n_inv,
      Q => np_count(2)
    );
  np_count_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => np_count_mux0000(3),
      R => rst_n_inv,
      Q => np_count(3)
    );
  new_oq_pkt_wr : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => new_oq_pkt_wr_and0000,
      R => rst_n_inv,
      Q => new_oq_pkt_wr_27085
    );
  oq_pkt_avail : FDRS
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => oq_pkt_avail_mux0000,
      R => rst_n_inv,
      S => oq_pktcnt_and0000,
      Q => oq_pkt_avail_27172
    );
  bq_pkt_avail : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => bq_pkt_avail_mux0000,
      R => rst_n_inv,
      Q => bq_pkt_avail_26991
    );
  new_oq_pkt_wr_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => new_oq_pkt_wr_27085,
      R => rst_n_inv,
      Q => new_oq_pkt_wr_d_27087
    );
  new_oq_pkt_wr_d2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => new_oq_pkt_wr_d_27087,
      R => rst_n_inv,
      Q => new_oq_pkt_wr_d2_27088
    );
  oq_pktcnt_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(0),
      R => rst_n_inv,
      Q => oq_pktcnt(0)
    );
  oq_pktcnt_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(1),
      R => rst_n_inv,
      Q => oq_pktcnt(1)
    );
  oq_pktcnt_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(2),
      R => rst_n_inv,
      Q => oq_pktcnt(2)
    );
  oq_pktcnt_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(3),
      R => rst_n_inv,
      Q => oq_pktcnt(3)
    );
  oq_pktcnt_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(4),
      R => rst_n_inv,
      Q => oq_pktcnt(4)
    );
  oq_pktcnt_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(5),
      R => rst_n_inv,
      Q => oq_pktcnt(5)
    );
  oq_pktcnt_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(6),
      R => rst_n_inv,
      Q => oq_pktcnt(6)
    );
  oq_pktcnt_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(7),
      R => rst_n_inv,
      Q => oq_pktcnt(7)
    );
  oq_pktcnt_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => oq_pktcnt_not0001,
      D => Result(8),
      R => rst_n_inv,
      Q => oq_pktcnt(8)
    );
  bq_pktcnt_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => bq_pktcnt_not0001_27000,
      D => Result_0_1,
      R => rst_n_inv,
      Q => bq_pktcnt(0)
    );
  bq_pktcnt_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => bq_pktcnt_not0001_27000,
      D => Result_1_1,
      R => rst_n_inv,
      Q => bq_pktcnt(1)
    );
  bq_pktcnt_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => bq_pktcnt_not0001_27000,
      D => Result_2_1,
      R => rst_n_inv,
      Q => bq_pktcnt(2)
    );
  bq_pktcnt_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => bq_pktcnt_not0001_27000,
      D => Result_3_1,
      R => rst_n_inv,
      Q => bq_pktcnt(3)
    );
  Mcount_oq_pktcnt_cy_0_Q : MUXCY
    port map (
      CI => oq_pktcnt_and0000_inv,
      DI => oq_pktcnt(0),
      S => Mcount_oq_pktcnt_lut(0),
      O => Mcount_oq_pktcnt_cy(0)
    );
  Mcount_oq_pktcnt_xor_0_Q : XORCY
    port map (
      CI => oq_pktcnt_and0000_inv,
      LI => Mcount_oq_pktcnt_lut(0),
      O => Result(0)
    );
  Mcount_oq_pktcnt_cy_1_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(0),
      DI => oq_pktcnt(1),
      S => Mcount_oq_pktcnt_lut(1),
      O => Mcount_oq_pktcnt_cy(1)
    );
  Mcount_oq_pktcnt_xor_1_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(0),
      LI => Mcount_oq_pktcnt_lut(1),
      O => Result(1)
    );
  Mcount_oq_pktcnt_cy_2_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(1),
      DI => oq_pktcnt(2),
      S => Mcount_oq_pktcnt_lut(2),
      O => Mcount_oq_pktcnt_cy(2)
    );
  Mcount_oq_pktcnt_xor_2_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(1),
      LI => Mcount_oq_pktcnt_lut(2),
      O => Result(2)
    );
  Mcount_oq_pktcnt_cy_3_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(2),
      DI => oq_pktcnt(3),
      S => Mcount_oq_pktcnt_lut(3),
      O => Mcount_oq_pktcnt_cy(3)
    );
  Mcount_oq_pktcnt_xor_3_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(2),
      LI => Mcount_oq_pktcnt_lut(3),
      O => Result(3)
    );
  Mcount_oq_pktcnt_cy_4_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(3),
      DI => oq_pktcnt(4),
      S => Mcount_oq_pktcnt_lut(4),
      O => Mcount_oq_pktcnt_cy(4)
    );
  Mcount_oq_pktcnt_xor_4_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(3),
      LI => Mcount_oq_pktcnt_lut(4),
      O => Result(4)
    );
  Mcount_oq_pktcnt_cy_5_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(4),
      DI => oq_pktcnt(5),
      S => Mcount_oq_pktcnt_lut(5),
      O => Mcount_oq_pktcnt_cy(5)
    );
  Mcount_oq_pktcnt_xor_5_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(4),
      LI => Mcount_oq_pktcnt_lut(5),
      O => Result(5)
    );
  Mcount_oq_pktcnt_cy_6_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(5),
      DI => oq_pktcnt(6),
      S => Mcount_oq_pktcnt_lut(6),
      O => Mcount_oq_pktcnt_cy(6)
    );
  Mcount_oq_pktcnt_xor_6_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(5),
      LI => Mcount_oq_pktcnt_lut(6),
      O => Result(6)
    );
  Mcount_oq_pktcnt_cy_7_Q : MUXCY
    port map (
      CI => Mcount_oq_pktcnt_cy(6),
      DI => oq_pktcnt(7),
      S => Mcount_oq_pktcnt_lut(7),
      O => Mcount_oq_pktcnt_cy(7)
    );
  Mcount_oq_pktcnt_xor_7_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(6),
      LI => Mcount_oq_pktcnt_lut(7),
      O => Result(7)
    );
  Mcount_oq_pktcnt_xor_8_Q : XORCY
    port map (
      CI => Mcount_oq_pktcnt_cy(7),
      LI => Mcount_oq_pktcnt_lut(8),
      O => Result(8)
    );
  fifo_discard_np_and00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => fifo_np,
      I1 => fifo_wren,
      I2 => fifo_dsc,
      O => fifo_discard_np_and0000
    );
  poisoned_reg_not00011 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_eof,
      I2 => fifo_sof,
      O => poisoned_reg_not0001
    );
  oq_write_pkt_in_progress_reg_and00011 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_dsc,
      I2 => fifo_eof,
      O => oq_write_pkt_in_progress_reg_and0001
    );
  fifo_np_ok_and00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => np_count(3),
      I1 => oq_afull,
      O => fifo_np_ok_and0000
    );
  trn_drain_np_and00001 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => trn_np_27211,
      I1 => NlwRenamedSig_OI_trn_reof,
      I2 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I3 => trn_rdst_rdy,
      O => trn_drain_np_and0000
    );
  np_count_mux0000_0_21 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => fifo_discard_np_27072,
      I1 => trn_drain_np_27209,
      I2 => fifo_np_req,
      I3 => np_count(0),
      O => np_count_mux0000(0)
    );
  np_count_mux0000_1_11 : LUT5
    generic map(
      INIT => X"D24BB4D2"
    )
    port map (
      I0 => fifo_discard_np_27072,
      I1 => fifo_np_req,
      I2 => np_count(1),
      I3 => np_count(0),
      I4 => trn_drain_np_27209,
      O => np_count_mux0000(1)
    );
  np_count_mux0000_2_11 : LUT6
    generic map(
      INIT => X"CCC6C6C39CCCCCC6"
    )
    port map (
      I0 => fifo_discard_np_27072,
      I1 => np_count(2),
      I2 => np_count(1),
      I3 => fifo_np_req,
      I4 => np_count(0),
      I5 => trn_drain_np_27209,
      O => np_count_mux0000(2)
    );
  poisoned1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => fifo_data(46),
      I1 => fifo_sof,
      I2 => poisoned_reg_27204,
      O => poisoned
    );
  poisoned_reg_mux000011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_sof,
      O => Q_and0000
    );
  trn_np_and00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsof,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      O => trn_np_and0001
    );
  nonposted_or_rem_SW0 : LUT5
    generic map(
      INIT => X"FEFEDC98"
    )
    port map (
      I0 => fifo_data(58),
      I1 => fifo_data(57),
      I2 => fifo_data(62),
      I3 => fifo_data(56),
      I4 => fifo_data(61),
      O => N01
    );
  nonposted_or_rem : LUT5
    generic map(
      INIT => X"4444444E"
    )
    port map (
      I0 => fifo_sof,
      I1 => fifo_rem,
      I2 => fifo_data(60),
      I3 => fifo_data(59),
      I4 => N01,
      O => nonposted_or_rem_27089
    );
  Q_and000211 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_sof,
      I2 => oq_write_pkt_in_progress_reg_27189,
      O => oq_wren
    );
  trn_np_and0000_SW0 : LUT5
    generic map(
      INIT => X"FEFEDC98"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rd(58),
      I1 => NlwRenamedSig_OI_trn_rd(57),
      I2 => NlwRenamedSig_OI_trn_rd(62),
      I3 => NlwRenamedSig_OI_trn_rd(56),
      I4 => NlwRenamedSig_OI_trn_rd(61),
      O => N2
    );
  trn_np_and0000 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => NlwRenamedSig_OI_trn_rsof,
      I2 => NlwRenamedSig_OI_trn_rd(60),
      I3 => NlwRenamedSig_OI_trn_rd(59),
      I4 => N2,
      O => trn_np_and0000_27212
    );
  trn_rrem_mux0000_0_Q : LUT6
    generic map(
      INIT => X"F5F5F5F5F5F5E4F5"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => bq_pktcnt_and0000,
      I2 => bq_dout(69),
      I3 => oq_dout(70),
      I4 => oq_dout(69),
      I5 => N10,
      O => trn_rrem_mux0000(0)
    );
  oq_pktcnt_not00011 : LUT4
    generic map(
      INIT => X"9AAA"
    )
    port map (
      I0 => new_oq_pkt_wr_d2_27088,
      I1 => oq_empty,
      I2 => oq_rden,
      I3 => oq_dout(71),
      O => oq_pktcnt_not0001
    );
  trn_reof_mux0000 : LUT6
    generic map(
      INIT => X"11F11111F3F33333"
    )
    port map (
      I0 => bq_empty,
      I1 => N12,
      I2 => N20,
      I3 => oq_empty,
      I4 => oq_dout(70),
      I5 => trn_rdst_rdy,
      O => trn_reof_mux0000_27349
    );
  trn_rbar_hit_mux0000_0_SW0 : LUT5
    generic map(
      INIT => X"BFFEFFFF"
    )
    port map (
      I0 => bq_dout(67),
      I1 => bq_dout(64),
      I2 => bq_dout(66),
      I3 => bq_dout(65),
      I4 => bq_trn_in_progress,
      O => N321
    );
  trn_rbar_hit_mux0000_0_Q : LUT6
    generic map(
      INIT => X"20000002FFFFFFFF"
    )
    port map (
      I0 => N20,
      I1 => oq_dout(67),
      I2 => oq_dout(64),
      I3 => oq_dout(66),
      I4 => oq_dout(65),
      I5 => N321,
      O => trn_rbar_hit_mux0000(0)
    );
  trn_rbar_hit_mux0000_1_SW0 : LUT5
    generic map(
      INIT => X"BEFDFFFF"
    )
    port map (
      I0 => bq_dout(67),
      I1 => bq_dout(65),
      I2 => bq_dout(66),
      I3 => bq_dout(64),
      I4 => bq_trn_in_progress,
      O => N36
    );
  trn_rbar_hit_mux0000_1_Q : LUT6
    generic map(
      INIT => X"20020008FFFFFFFF"
    )
    port map (
      I0 => N20,
      I1 => oq_dout(67),
      I2 => oq_dout(65),
      I3 => oq_dout(66),
      I4 => oq_dout(64),
      I5 => N36,
      O => trn_rbar_hit_mux0000(1)
    );
  oq_pkt_avail_mux00006 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => oq_pktcnt(5),
      I1 => oq_pktcnt(6),
      I2 => oq_pktcnt(7),
      I3 => oq_pktcnt(8),
      O => oq_pkt_avail_mux00006_27174
    );
  oq_pktcnt_and00001 : LUT4
    generic map(
      INIT => X"CC4C"
    )
    port map (
      I0 => oq_dout(71),
      I1 => new_oq_pkt_wr_d2_27088,
      I2 => oq_rden,
      I3 => oq_empty,
      O => oq_pktcnt_and0000
    );
  trn_rd_not000111 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => trn_rdst_rdy,
      O => N4
    );
  packet_in_progress_mux0000111 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => packet_in_progress_27191,
      O => N65
    );
  oq_fifo : sync_fifo_1
    port map (
      clk => clk,
      rst_n => rst_n,
      rd_en => oq_rden,
      afull => oq_afull,
      empty => oq_empty,
      rewind => Q_and0002,
      wr_en => oq_wren,
      mark_addr => Q_and0000,
      clear_addr => Q_and0001,
      full => NLW_oq_fifo_full_UNCONNECTED,
      aempty => NLW_oq_fifo_aempty_UNCONNECTED,
      data_count(9) => NLW_oq_fifo_data_count_9_UNCONNECTED,
      data_count(8) => NLW_oq_fifo_data_count_8_UNCONNECTED,
      data_count(7) => NLW_oq_fifo_data_count_7_UNCONNECTED,
      data_count(6) => NLW_oq_fifo_data_count_6_UNCONNECTED,
      data_count(5) => NLW_oq_fifo_data_count_5_UNCONNECTED,
      data_count(4) => NLW_oq_fifo_data_count_4_UNCONNECTED,
      data_count(3) => NLW_oq_fifo_data_count_3_UNCONNECTED,
      data_count(2) => NLW_oq_fifo_data_count_2_UNCONNECTED,
      data_count(1) => NLW_oq_fifo_data_count_1_UNCONNECTED,
      data_count(0) => NLW_oq_fifo_data_count_0_UNCONNECTED,
      dout(71) => oq_dout(71),
      dout(70) => oq_dout(70),
      dout(69) => oq_dout(69),
      dout(68) => oq_dout(68),
      dout(67) => oq_dout(67),
      dout(66) => oq_dout(66),
      dout(65) => oq_dout(65),
      dout(64) => oq_dout(64),
      dout(63) => oq_dout(63),
      dout(62) => oq_dout(62),
      dout(61) => oq_dout(61),
      dout(60) => oq_dout(60),
      dout(59) => oq_dout(59),
      dout(58) => oq_dout(58),
      dout(57) => oq_dout(57),
      dout(56) => oq_dout(56),
      dout(55) => oq_dout(55),
      dout(54) => oq_dout(54),
      dout(53) => oq_dout(53),
      dout(52) => oq_dout(52),
      dout(51) => oq_dout(51),
      dout(50) => oq_dout(50),
      dout(49) => oq_dout(49),
      dout(48) => oq_dout(48),
      dout(47) => oq_dout(47),
      dout(46) => oq_dout(46),
      dout(45) => oq_dout(45),
      dout(44) => oq_dout(44),
      dout(43) => oq_dout(43),
      dout(42) => oq_dout(42),
      dout(41) => oq_dout(41),
      dout(40) => oq_dout(40),
      dout(39) => oq_dout(39),
      dout(38) => oq_dout(38),
      dout(37) => oq_dout(37),
      dout(36) => oq_dout(36),
      dout(35) => oq_dout(35),
      dout(34) => oq_dout(34),
      dout(33) => oq_dout(33),
      dout(32) => oq_dout(32),
      dout(31) => oq_dout(31),
      dout(30) => oq_dout(30),
      dout(29) => oq_dout(29),
      dout(28) => oq_dout(28),
      dout(27) => oq_dout(27),
      dout(26) => oq_dout(26),
      dout(25) => oq_dout(25),
      dout(24) => oq_dout(24),
      dout(23) => oq_dout(23),
      dout(22) => oq_dout(22),
      dout(21) => oq_dout(21),
      dout(20) => oq_dout(20),
      dout(19) => oq_dout(19),
      dout(18) => oq_dout(18),
      dout(17) => oq_dout(17),
      dout(16) => oq_dout(16),
      dout(15) => oq_dout(15),
      dout(14) => oq_dout(14),
      dout(13) => oq_dout(13),
      dout(12) => oq_dout(12),
      dout(11) => oq_dout(11),
      dout(10) => oq_dout(10),
      dout(9) => oq_dout(9),
      dout(8) => oq_dout(8),
      dout(7) => oq_dout(7),
      dout(6) => oq_dout(6),
      dout(5) => oq_dout(5),
      dout(4) => oq_dout(4),
      dout(3) => oq_dout(3),
      dout(2) => oq_dout(2),
      dout(1) => oq_dout(1),
      dout(0) => oq_dout(0),
      din(71) => fifo_sof,
      din(70) => fifo_eof,
      din(69) => nonposted_or_rem_27089,
      din(68) => poisoned,
      din(67) => fifo_barenc(3),
      din(66) => fifo_barenc(2),
      din(65) => fifo_barenc(1),
      din(64) => fifo_barenc(0),
      din(63) => fifo_data(63),
      din(62) => fifo_data(62),
      din(61) => fifo_data(61),
      din(60) => fifo_data(60),
      din(59) => fifo_data(59),
      din(58) => fifo_data(58),
      din(57) => fifo_data(57),
      din(56) => fifo_data(56),
      din(55) => fifo_data(55),
      din(54) => fifo_data(54),
      din(53) => fifo_data(53),
      din(52) => fifo_data(52),
      din(51) => fifo_data(51),
      din(50) => fifo_data(50),
      din(49) => fifo_data(49),
      din(48) => fifo_data(48),
      din(47) => fifo_data(47),
      din(46) => fifo_data(46),
      din(45) => fifo_data(45),
      din(44) => fifo_data(44),
      din(43) => fifo_data(43),
      din(42) => fifo_data(42),
      din(41) => fifo_data(41),
      din(40) => fifo_data(40),
      din(39) => fifo_data(39),
      din(38) => fifo_data(38),
      din(37) => fifo_data(37),
      din(36) => fifo_data(36),
      din(35) => fifo_data(35),
      din(34) => fifo_data(34),
      din(33) => fifo_data(33),
      din(32) => fifo_data(32),
      din(31) => fifo_data(31),
      din(30) => fifo_data(30),
      din(29) => fifo_data(29),
      din(28) => fifo_data(28),
      din(27) => fifo_data(27),
      din(26) => fifo_data(26),
      din(25) => fifo_data(25),
      din(24) => fifo_data(24),
      din(23) => fifo_data(23),
      din(22) => fifo_data(22),
      din(21) => fifo_data(21),
      din(20) => fifo_data(20),
      din(19) => fifo_data(19),
      din(18) => fifo_data(18),
      din(17) => fifo_data(17),
      din(16) => fifo_data(16),
      din(15) => fifo_data(15),
      din(14) => fifo_data(14),
      din(13) => fifo_data(13),
      din(12) => fifo_data(12),
      din(11) => fifo_data(11),
      din(10) => fifo_data(10),
      din(9) => fifo_data(9),
      din(8) => fifo_data(8),
      din(7) => fifo_data(7),
      din(6) => fifo_data(6),
      din(5) => fifo_data(5),
      din(4) => fifo_data(4),
      din(3) => fifo_data(3),
      din(2) => fifo_data(2),
      din(1) => fifo_data(1),
      din(0) => fifo_data(0)
    );
  bq_fifo : sync_fifo_2
    port map (
      clk => clk,
      rst_n => rst_n,
      rd_en => bq_rden,
      afull => NLW_bq_fifo_afull_UNCONNECTED,
      empty => bq_empty,
      rewind => bq_pktcnt_and0000,
      wr_en => bq_pktcnt_and0000,
      mark_addr => bq_pktcnt_and0000,
      clear_addr => bq_pktcnt_and0000,
      full => NLW_bq_fifo_full_UNCONNECTED,
      aempty => NLW_bq_fifo_aempty_UNCONNECTED,
      data_count(4) => NLW_bq_fifo_data_count_4_UNCONNECTED,
      data_count(3) => NLW_bq_fifo_data_count_3_UNCONNECTED,
      data_count(2) => NLW_bq_fifo_data_count_2_UNCONNECTED,
      data_count(1) => NLW_bq_fifo_data_count_1_UNCONNECTED,
      data_count(0) => NLW_bq_fifo_data_count_0_UNCONNECTED,
      dout(71) => bq_dout(71),
      dout(70) => bq_dout(70),
      dout(69) => bq_dout(69),
      dout(68) => bq_dout(68),
      dout(67) => bq_dout(67),
      dout(66) => bq_dout(66),
      dout(65) => bq_dout(65),
      dout(64) => bq_dout(64),
      dout(63) => bq_dout(63),
      dout(62) => bq_dout(62),
      dout(61) => bq_dout(61),
      dout(60) => bq_dout(60),
      dout(59) => bq_dout(59),
      dout(58) => bq_dout(58),
      dout(57) => bq_dout(57),
      dout(56) => bq_dout(56),
      dout(55) => bq_dout(55),
      dout(54) => bq_dout(54),
      dout(53) => bq_dout(53),
      dout(52) => bq_dout(52),
      dout(51) => bq_dout(51),
      dout(50) => bq_dout(50),
      dout(49) => bq_dout(49),
      dout(48) => bq_dout(48),
      dout(47) => bq_dout(47),
      dout(46) => bq_dout(46),
      dout(45) => bq_dout(45),
      dout(44) => bq_dout(44),
      dout(43) => bq_dout(43),
      dout(42) => bq_dout(42),
      dout(41) => bq_dout(41),
      dout(40) => bq_dout(40),
      dout(39) => bq_dout(39),
      dout(38) => bq_dout(38),
      dout(37) => bq_dout(37),
      dout(36) => bq_dout(36),
      dout(35) => bq_dout(35),
      dout(34) => bq_dout(34),
      dout(33) => bq_dout(33),
      dout(32) => bq_dout(32),
      dout(31) => bq_dout(31),
      dout(30) => bq_dout(30),
      dout(29) => bq_dout(29),
      dout(28) => bq_dout(28),
      dout(27) => bq_dout(27),
      dout(26) => bq_dout(26),
      dout(25) => bq_dout(25),
      dout(24) => bq_dout(24),
      dout(23) => bq_dout(23),
      dout(22) => bq_dout(22),
      dout(21) => bq_dout(21),
      dout(20) => bq_dout(20),
      dout(19) => bq_dout(19),
      dout(18) => bq_dout(18),
      dout(17) => bq_dout(17),
      dout(16) => bq_dout(16),
      dout(15) => bq_dout(15),
      dout(14) => bq_dout(14),
      dout(13) => bq_dout(13),
      dout(12) => bq_dout(12),
      dout(11) => bq_dout(11),
      dout(10) => bq_dout(10),
      dout(9) => bq_dout(9),
      dout(8) => bq_dout(8),
      dout(7) => bq_dout(7),
      dout(6) => bq_dout(6),
      dout(5) => bq_dout(5),
      dout(4) => bq_dout(4),
      dout(3) => bq_dout(3),
      dout(2) => bq_dout(2),
      dout(1) => bq_dout(1),
      dout(0) => bq_dout(0),
      din(71) => oq_dout(71),
      din(70) => oq_dout(70),
      din(69) => oq_dout(69),
      din(68) => oq_dout(68),
      din(67) => oq_dout(67),
      din(66) => oq_dout(66),
      din(65) => oq_dout(65),
      din(64) => oq_dout(64),
      din(63) => oq_dout(63),
      din(62) => oq_dout(62),
      din(61) => oq_dout(61),
      din(60) => oq_dout(60),
      din(59) => oq_dout(59),
      din(58) => oq_dout(58),
      din(57) => oq_dout(57),
      din(56) => oq_dout(56),
      din(55) => oq_dout(55),
      din(54) => oq_dout(54),
      din(53) => oq_dout(53),
      din(52) => oq_dout(52),
      din(51) => oq_dout(51),
      din(50) => oq_dout(50),
      din(49) => oq_dout(49),
      din(48) => oq_dout(48),
      din(47) => oq_dout(47),
      din(46) => oq_dout(46),
      din(45) => oq_dout(45),
      din(44) => oq_dout(44),
      din(43) => oq_dout(43),
      din(42) => oq_dout(42),
      din(41) => oq_dout(41),
      din(40) => oq_dout(40),
      din(39) => oq_dout(39),
      din(38) => oq_dout(38),
      din(37) => oq_dout(37),
      din(36) => oq_dout(36),
      din(35) => oq_dout(35),
      din(34) => oq_dout(34),
      din(33) => oq_dout(33),
      din(32) => oq_dout(32),
      din(31) => oq_dout(31),
      din(30) => oq_dout(30),
      din(29) => oq_dout(29),
      din(28) => oq_dout(28),
      din(27) => oq_dout(27),
      din(26) => oq_dout(26),
      din(25) => oq_dout(25),
      din(24) => oq_dout(24),
      din(23) => oq_dout(23),
      din(22) => oq_dout(22),
      din(21) => oq_dout(21),
      din(20) => oq_dout(20),
      din(19) => oq_dout(19),
      din(18) => oq_dout(18),
      din(17) => oq_dout(17),
      din(16) => oq_dout(16),
      din(15) => oq_dout(15),
      din(14) => oq_dout(14),
      din(13) => oq_dout(13),
      din(12) => oq_dout(12),
      din(11) => oq_dout(11),
      din(10) => oq_dout(10),
      din(9) => oq_dout(9),
      din(8) => oq_dout(8),
      din(7) => oq_dout(7),
      din(6) => oq_dout(6),
      din(5) => oq_dout(5),
      din(4) => oq_dout(4),
      din(3) => oq_dout(3),
      din(2) => oq_dout(2),
      din(1) => oq_dout(1),
      din(0) => oq_dout(0)
    );
  oq_pkt_avail_mux000041_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => oq_pkt_avail_mux00006_27174,
      I1 => oq_pktcnt(1),
      I2 => oq_pktcnt(2),
      I3 => oq_pktcnt(3),
      I4 => oq_pktcnt(4),
      O => N21
    );
  oq_pkt_avail_mux000041 : LUT6
    generic map(
      INIT => X"FFFFFFFFC8CCCCCC"
    )
    port map (
      I0 => oq_empty,
      I1 => oq_pktcnt(0),
      I2 => new_oq_pkt_wr_d2_27088,
      I3 => oq_dout(71),
      I4 => oq_rden,
      I5 => N21,
      O => oq_pkt_avail_mux0000
    );
  bq_pktcnt_not0001 : LUT6
    generic map(
      INIT => X"00F0008000800080"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => N65,
      I2 => bq_dout(71),
      I3 => bq_empty,
      I4 => N4,
      I5 => packet_in_progress_bq_27192,
      O => bq_pktcnt_not0001_27000
    );
  packet_in_progress_not00011 : LUT6
    generic map(
      INIT => X"02220AAA02330AFF"
    )
    port map (
      I0 => N4,
      I1 => N20,
      I2 => bq_empty,
      I3 => bq_trn_in_progress,
      I4 => oq_empty,
      I5 => packet_in_progress_oq_27198,
      O => packet_in_progress_not0001
    );
  packet_in_progress_bq_mux00001 : LUT6
    generic map(
      INIT => X"AAAAEEEEA888ECCC"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => packet_in_progress_bq_27192,
      I2 => packet_in_progress_oq_27198,
      I3 => oq_dout(70),
      I4 => bq_dout(70),
      I5 => N65,
      O => packet_in_progress_bq_mux0000
    );
  Mcount_bq_pktcnt_xor_1_11 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => bq_pktcnt(1),
      I1 => bq_pktcnt(0),
      O => Result_1_1
    );
  trn_rsrc_rdy_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEF23"
    )
    port map (
      I0 => oq_empty,
      I1 => packet_in_progress_bq_27192,
      I2 => packet_in_progress_oq_27198,
      I3 => bq_empty,
      I4 => NlwRenamedSig_OI_trn_reof,
      I5 => N4,
      O => trn_rsrc_rdy_not0001
    );
  trn_reof_not00011 : LUT6
    generic map(
      INIT => X"FFFF3233FFFF1011"
    )
    port map (
      I0 => packet_in_progress_bq_27192,
      I1 => NlwRenamedSig_OI_trn_reof,
      I2 => oq_empty,
      I3 => packet_in_progress_oq_27198,
      I4 => N4,
      I5 => bq_empty,
      O => trn_reof_not0001
    );
  trn_rd_not0001 : LUT6
    generic map(
      INIT => X"2020207522222277"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => bq_empty,
      I2 => trn_rdst_rdy,
      I3 => oq_empty,
      I4 => N40,
      I5 => NlwRenamedSig_OI_trn_rsrc_rdy,
      O => trn_rd_not0001_27346
    );
  poisoned_reg_mux00002 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => fifo_sof,
      I1 => fifo_eof,
      I2 => fifo_data(46),
      I3 => fifo_wren,
      O => poisoned_reg_mux0000
    );
  Q_and00022 : LUT4
    generic map(
      INIT => X"A080"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_sof,
      I2 => fifo_dsc,
      I3 => oq_write_pkt_in_progress_reg_27189,
      O => Q_and0002
    );
  new_oq_pkt_wr_and000021 : LUT4
    generic map(
      INIT => X"A080"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_sof,
      I2 => fifo_eof,
      I3 => oq_write_pkt_in_progress_reg_27189,
      O => Q_and0001
    );
  packet_in_progress_or00001 : LUT4
    generic map(
      INIT => X"08FF"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => NlwRenamedSig_OI_trn_reof,
      I2 => trn_rdst_rdy,
      I3 => rst_n,
      O => packet_in_progress_or0000
    );
  trn_rsof_mux00001 : LUT6
    generic map(
      INIT => X"FFFFA888A888A888"
    )
    port map (
      I0 => bq_dout(71),
      I1 => packet_in_progress_bq_27192,
      I2 => bq_pkt_avail_26991,
      I3 => N65,
      I4 => oq_dout(71),
      I5 => N20,
      O => trn_rsof_mux0000
    );
  trn_rerrfwd_mux00001 : LUT6
    generic map(
      INIT => X"FFFFA888A888A888"
    )
    port map (
      I0 => bq_dout(68),
      I1 => packet_in_progress_bq_27192,
      I2 => bq_pkt_avail_26991,
      I3 => N65,
      I4 => oq_dout(68),
      I5 => N20,
      O => trn_rerrfwd_mux0000
    );
  trn_rrem_mux0000_0_SW0 : LUT5
    generic map(
      INIT => X"55545555"
    )
    port map (
      I0 => packet_in_progress_oq_27198,
      I1 => packet_in_progress_27191,
      I2 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I3 => bq_pkt_avail_26991,
      I4 => oq_pkt_avail_27172,
      O => N10
    );
  trn_rsof_not00011 : LUT6
    generic map(
      INIT => X"0501551105015555"
    )
    port map (
      I0 => trn_rsof_and0000,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => bq_empty,
      I3 => trn_rdst_rdy,
      I4 => bq_trn_in_progress,
      I5 => NlwRenamedSig_OI_trn_reof,
      O => trn_rsof_not0001
    );
  oq_rden1 : LUT6
    generic map(
      INIT => X"C4C4C4C4C4D5C4C4"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => packet_in_progress_oq_27198,
      I2 => trn_rdst_rdy,
      I3 => packet_in_progress_27191,
      I4 => oq_pkt_avail_27172,
      I5 => bq_pkt_avail_26991,
      O => oq_rden
    );
  trn_rd_not0001_SW0 : LUT6
    generic map(
      INIT => X"33323333BBBABBBB"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => packet_in_progress_oq_27198,
      I2 => bq_pkt_avail_26991,
      I3 => packet_in_progress_27191,
      I4 => oq_pkt_avail_27172,
      I5 => trn_rdst_rdy,
      O => N40
    );
  new_oq_pkt_wr_and00001 : LUT5
    generic map(
      INIT => X"22002000"
    )
    port map (
      I0 => fifo_wren,
      I1 => fifo_dsc,
      I2 => fifo_sof,
      I3 => fifo_eof,
      I4 => oq_write_pkt_in_progress_reg_27189,
      O => new_oq_pkt_wr_and0000
    );
  bq_trn_in_progress1 : LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      I0 => packet_in_progress_bq_27192,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => bq_pkt_avail_26991,
      I3 => packet_in_progress_27191,
      O => bq_trn_in_progress
    );
  oq_pktcnt_and0000_inv2 : LUT4
    generic map(
      INIT => X"08FF"
    )
    port map (
      I0 => oq_rden,
      I1 => oq_dout(71),
      I2 => oq_empty,
      I3 => new_oq_pkt_wr_d2_27088,
      O => oq_pktcnt_and0000_inv
    );
  Mcount_bq_pktcnt_xor_2_11 : LUT3
    generic map(
      INIT => X"C9"
    )
    port map (
      I0 => bq_pktcnt(1),
      I1 => bq_pktcnt(2),
      I2 => bq_pktcnt(0),
      O => Result_2_1
    );
  trn_rbar_hit_mux0000_0_11 : LUT6
    generic map(
      INIT => X"0A080A0B0A080A0A"
    )
    port map (
      I0 => packet_in_progress_oq_27198,
      I1 => packet_in_progress_27191,
      I2 => packet_in_progress_bq_27192,
      I3 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I4 => bq_pkt_avail_26991,
      I5 => oq_pkt_avail_27172,
      O => N20
    );
  Mcount_oq_pktcnt_lut_0_Q : LUT5
    generic map(
      INIT => X"5595AAAA"
    )
    port map (
      I0 => oq_pktcnt(0),
      I1 => oq_rden,
      I2 => oq_dout(71),
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(0)
    );
  Mcount_oq_pktcnt_lut_1_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(1),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(1)
    );
  Mcount_oq_pktcnt_lut_2_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(2),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(2)
    );
  Mcount_oq_pktcnt_lut_3_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(3),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(3)
    );
  Mcount_oq_pktcnt_lut_4_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(4),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(4)
    );
  Mcount_oq_pktcnt_lut_5_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(5),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(5)
    );
  Mcount_oq_pktcnt_lut_6_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(6),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(6)
    );
  Mcount_oq_pktcnt_lut_7_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(7),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(7)
    );
  Mcount_oq_pktcnt_lut_8_Q : LUT5
    generic map(
      INIT => X"AA6A5555"
    )
    port map (
      I0 => oq_pktcnt(8),
      I1 => oq_dout(71),
      I2 => oq_rden,
      I3 => oq_empty,
      I4 => new_oq_pkt_wr_d2_27088,
      O => Mcount_oq_pktcnt_lut(8)
    );
  trn_rd_mux0000_9_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(9),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(9),
      O => trn_rd_mux0000(9)
    );
  trn_rd_mux0000_8_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(8),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(8),
      O => trn_rd_mux0000(8)
    );
  trn_rd_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(7),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(7),
      O => trn_rd_mux0000(7)
    );
  trn_rd_mux0000_6_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(6),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(6),
      O => trn_rd_mux0000(6)
    );
  trn_rd_mux0000_63_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(63),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(63),
      O => trn_rd_mux0000(63)
    );
  trn_rd_mux0000_62_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(62),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(62),
      O => trn_rd_mux0000(62)
    );
  trn_rd_mux0000_61_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(61),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(61),
      O => trn_rd_mux0000(61)
    );
  trn_rd_mux0000_60_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(60),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(60),
      O => trn_rd_mux0000(60)
    );
  trn_rd_mux0000_5_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(5),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(5),
      O => trn_rd_mux0000(5)
    );
  trn_rd_mux0000_59_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(59),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(59),
      O => trn_rd_mux0000(59)
    );
  trn_rd_mux0000_58_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(58),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(58),
      O => trn_rd_mux0000(58)
    );
  trn_rd_mux0000_57_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(57),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(57),
      O => trn_rd_mux0000(57)
    );
  trn_rd_mux0000_56_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(56),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(56),
      O => trn_rd_mux0000(56)
    );
  trn_rd_mux0000_55_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(55),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(55),
      O => trn_rd_mux0000(55)
    );
  trn_rd_mux0000_54_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(54),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(54),
      O => trn_rd_mux0000(54)
    );
  trn_rd_mux0000_53_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(53),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(53),
      O => trn_rd_mux0000(53)
    );
  trn_rd_mux0000_52_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(52),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(52),
      O => trn_rd_mux0000(52)
    );
  trn_rd_mux0000_51_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(51),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(51),
      O => trn_rd_mux0000(51)
    );
  trn_rd_mux0000_50_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(50),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(50),
      O => trn_rd_mux0000(50)
    );
  trn_rd_mux0000_4_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(4),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(4),
      O => trn_rd_mux0000(4)
    );
  trn_rd_mux0000_49_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(49),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(49),
      O => trn_rd_mux0000(49)
    );
  trn_rd_mux0000_48_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(48),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(48),
      O => trn_rd_mux0000(48)
    );
  trn_rd_mux0000_47_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(47),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(47),
      O => trn_rd_mux0000(47)
    );
  trn_rd_mux0000_46_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(46),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(46),
      O => trn_rd_mux0000(46)
    );
  trn_rd_mux0000_45_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(45),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(45),
      O => trn_rd_mux0000(45)
    );
  trn_rd_mux0000_44_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(44),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(44),
      O => trn_rd_mux0000(44)
    );
  trn_rd_mux0000_43_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(43),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(43),
      O => trn_rd_mux0000(43)
    );
  trn_rd_mux0000_42_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(42),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(42),
      O => trn_rd_mux0000(42)
    );
  trn_rd_mux0000_41_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(41),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(41),
      O => trn_rd_mux0000(41)
    );
  trn_rd_mux0000_40_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(40),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(40),
      O => trn_rd_mux0000(40)
    );
  trn_rd_mux0000_3_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(3),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(3),
      O => trn_rd_mux0000(3)
    );
  trn_rd_mux0000_39_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(39),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(39),
      O => trn_rd_mux0000(39)
    );
  trn_rd_mux0000_38_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(38),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(38),
      O => trn_rd_mux0000(38)
    );
  trn_rd_mux0000_37_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(37),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(37),
      O => trn_rd_mux0000(37)
    );
  trn_rd_mux0000_36_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(36),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(36),
      O => trn_rd_mux0000(36)
    );
  trn_rd_mux0000_35_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(35),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(35),
      O => trn_rd_mux0000(35)
    );
  trn_rd_mux0000_34_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(34),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(34),
      O => trn_rd_mux0000(34)
    );
  trn_rd_mux0000_33_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(33),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(33),
      O => trn_rd_mux0000(33)
    );
  trn_rd_mux0000_32_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(32),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(32),
      O => trn_rd_mux0000(32)
    );
  trn_rd_mux0000_31_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(31),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(31),
      O => trn_rd_mux0000(31)
    );
  trn_rd_mux0000_30_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(30),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(30),
      O => trn_rd_mux0000(30)
    );
  trn_rd_mux0000_2_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(2),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(2),
      O => trn_rd_mux0000(2)
    );
  trn_rd_mux0000_29_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(29),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(29),
      O => trn_rd_mux0000(29)
    );
  trn_rd_mux0000_28_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(28),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(28),
      O => trn_rd_mux0000(28)
    );
  trn_rd_mux0000_27_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(27),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(27),
      O => trn_rd_mux0000(27)
    );
  trn_rd_mux0000_26_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(26),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(26),
      O => trn_rd_mux0000(26)
    );
  trn_rd_mux0000_25_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(25),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(25),
      O => trn_rd_mux0000(25)
    );
  trn_rd_mux0000_24_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(24),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(24),
      O => trn_rd_mux0000(24)
    );
  trn_rd_mux0000_23_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(23),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(23),
      O => trn_rd_mux0000(23)
    );
  trn_rd_mux0000_22_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(22),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(22),
      O => trn_rd_mux0000(22)
    );
  trn_rd_mux0000_21_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(21),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(21),
      O => trn_rd_mux0000(21)
    );
  trn_rd_mux0000_20_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(20),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(20),
      O => trn_rd_mux0000(20)
    );
  trn_rd_mux0000_1_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(1),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(1),
      O => trn_rd_mux0000(1)
    );
  trn_rd_mux0000_19_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(19),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(19),
      O => trn_rd_mux0000(19)
    );
  trn_rd_mux0000_18_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(18),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(18),
      O => trn_rd_mux0000(18)
    );
  trn_rd_mux0000_17_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(17),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(17),
      O => trn_rd_mux0000(17)
    );
  trn_rd_mux0000_16_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(16),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(16),
      O => trn_rd_mux0000(16)
    );
  trn_rd_mux0000_15_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(15),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(15),
      O => trn_rd_mux0000(15)
    );
  trn_rd_mux0000_14_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(14),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(14),
      O => trn_rd_mux0000(14)
    );
  trn_rd_mux0000_13_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(13),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(13),
      O => trn_rd_mux0000(13)
    );
  trn_rd_mux0000_12_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(12),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(12),
      O => trn_rd_mux0000(12)
    );
  trn_rd_mux0000_11_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(11),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(11),
      O => trn_rd_mux0000(11)
    );
  trn_rd_mux0000_10_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(10),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(10),
      O => trn_rd_mux0000(10)
    );
  trn_rd_mux0000_0_1 : LUT6
    generic map(
      INIT => X"FF00FFFDFF000200"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I2 => packet_in_progress_27191,
      I3 => bq_dout(0),
      I4 => packet_in_progress_bq_27192,
      I5 => oq_dout(0),
      O => trn_rd_mux0000(0)
    );
  trn_reof_mux0000_SW0 : LUT5
    generic map(
      INIT => X"77757777"
    )
    port map (
      I0 => bq_dout(70),
      I1 => packet_in_progress_bq_27192,
      I2 => packet_in_progress_27191,
      I3 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I4 => bq_pkt_avail_26991,
      O => N12
    );
  Mcount_bq_pktcnt_xor_3_11 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => bq_pktcnt(3),
      I1 => bq_pktcnt(2),
      I2 => bq_pktcnt(1),
      I3 => bq_pktcnt(0),
      O => Result_3_1
    );
  trn_rsof_and00001 : LUT6
    generic map(
      INIT => X"FFFF002000200020"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => trn_rdst_rdy,
      I2 => packet_in_progress_oq_27198,
      I3 => packet_in_progress_bq_27192,
      I4 => N20,
      I5 => oq_empty,
      O => trn_rsof_and0000
    );
  bq_rden1 : LUT6
    generic map(
      INIT => X"3010311130103010"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I1 => bq_empty,
      I2 => packet_in_progress_bq_27192,
      I3 => trn_rdst_rdy,
      I4 => packet_in_progress_27191,
      I5 => bq_pkt_avail_26991,
      O => bq_rden
    );
  np_count_mux0000_3_1 : MUXF7
    port map (
      I0 => N101,
      I1 => N11,
      S => np_count(3),
      O => np_count_mux0000(3)
    );
  np_count_mux0000_3_1_F : LUT6
    generic map(
      INIT => X"0004200004050004"
    )
    port map (
      I0 => np_count(1),
      I1 => fifo_discard_np_27072,
      I2 => np_count(2),
      I3 => fifo_np_req,
      I4 => trn_drain_np_27209,
      I5 => np_count(0),
      O => N101
    );
  np_count_mux0000_3_1_G : LUT6
    generic map(
      INIT => X"FFEFFFAEF7FFFFEF"
    )
    port map (
      I0 => np_count(1),
      I1 => np_count(0),
      I2 => fifo_discard_np_27072,
      I3 => np_count(2),
      I4 => fifo_np_req,
      I5 => trn_drain_np_27209,
      O => N11
    );
  fifo_pcpl_ok_not00011_INV_0 : INV
    port map (
      I => oq_afull,
      O => fifo_pcpl_ok_not0001
    );
  rst_n_inv241_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  Mcount_bq_pktcnt_xor_0_111_INV_0 : INV
    port map (
      I => bq_pktcnt(0),
      O => Result_0_1
    );
  trn_rsrc_rdy_mux00001 : LUT5
    generic map(
      INIT => X"5D5DFF5D"
    )
    port map (
      I0 => N4,
      I1 => bq_trn_in_progress,
      I2 => bq_empty,
      I3 => N20,
      I4 => oq_empty,
      O => trn_rsrc_rdy_mux00001_27361
    );
  trn_rsrc_rdy_mux00002 : LUT6
    generic map(
      INIT => X"2F2A2F2AFFFF2F2A"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => bq_empty,
      I2 => N4,
      I3 => packet_in_progress_oq_27198,
      I4 => N20,
      I5 => oq_empty,
      O => trn_rsrc_rdy_mux00002_27362
    );
  trn_rsrc_rdy_mux0000_f7 : MUXF7
    port map (
      I0 => trn_rsrc_rdy_mux00002_27362,
      I1 => trn_rsrc_rdy_mux00001_27361,
      S => NlwRenamedSig_OI_trn_reof,
      O => trn_rsrc_rdy_mux0000
    );
  bq_pkt_avail_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFEEEFEFE"
    )
    port map (
      I0 => bq_pktcnt(2),
      I1 => bq_pktcnt(1),
      I2 => bq_pktcnt(0),
      I3 => bq_empty,
      I4 => bq_dout(71),
      I5 => bq_pktcnt(3),
      O => bq_pkt_avail_mux00001_26993
    );
  bq_pkt_avail_mux00002 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => bq_pktcnt(1),
      I1 => bq_pktcnt(2),
      I2 => bq_pktcnt(3),
      I3 => bq_pktcnt(0),
      O => bq_pkt_avail_mux00002_26994
    );
  bq_pkt_avail_mux0000_f7 : MUXF7
    port map (
      I0 => bq_pkt_avail_mux00002_26994,
      I1 => bq_pkt_avail_mux00001_26993,
      S => bq_rden,
      O => bq_pkt_avail_mux0000
    );
  packet_in_progress_mux00001 : LUT5
    generic map(
      INIT => X"FFFFFF27"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => bq_dout(70),
      I2 => oq_dout(70),
      I3 => bq_pkt_avail_26991,
      I4 => oq_pkt_avail_27172,
      O => packet_in_progress_mux00001_27195
    );
  packet_in_progress_mux00002 : LUT6
    generic map(
      INIT => X"AAA2AAA2AAA2AAF2"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => bq_dout(70),
      I2 => oq_pkt_avail_27172,
      I3 => bq_pkt_avail_26991,
      I4 => NlwRenamedSig_OI_trn_rsrc_rdy,
      I5 => packet_in_progress_27191,
      O => packet_in_progress_mux00002_27196
    );
  packet_in_progress_mux0000_f7 : MUXF7
    port map (
      I0 => packet_in_progress_mux00002_27196,
      I1 => packet_in_progress_mux00001_27195,
      S => packet_in_progress_oq_27198,
      O => packet_in_progress_mux0000
    );
  packet_in_progress_oq_mux00001 : LUT5
    generic map(
      INIT => X"0C045D55"
    )
    port map (
      I0 => bq_trn_in_progress,
      I1 => oq_pkt_avail_27172,
      I2 => bq_pkt_avail_26991,
      I3 => bq_dout(70),
      I4 => oq_dout(70),
      O => packet_in_progress_oq_mux00001_27200
    );
  packet_in_progress_oq_mux00002 : LUT5
    generic map(
      INIT => X"44044000"
    )
    port map (
      I0 => bq_pkt_avail_26991,
      I1 => oq_pkt_avail_27172,
      I2 => bq_trn_in_progress,
      I3 => bq_dout(70),
      I4 => N65,
      O => packet_in_progress_oq_mux00002_27201
    );
  packet_in_progress_oq_mux0000_f7 : MUXF7
    port map (
      I0 => packet_in_progress_oq_mux00002_27201,
      I1 => packet_in_progress_oq_mux00001_27200,
      S => packet_in_progress_oq_27198,
      O => packet_in_progress_oq_mux0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity tlm_rx_data_snk_bar is
  port (
    legacy_mode_i : in STD_LOGIC := 'X'; 
    reset_i : in STD_LOGIC := 'X'; 
    check_rhit_src_rdy_o : out STD_LOGIC; 
    check_rfun_id_o : out STD_LOGIC; 
    check_rhit_lock_o : out STD_LOGIC; 
    check_rhit_ack_o : out STD_LOGIC; 
    check_rhit_i : in STD_LOGIC := 'X'; 
    check_rhit_o : out STD_LOGIC; 
    rhit_lat3_i : in STD_LOGIC := 'X'; 
    check_rmem32_o : out STD_LOGIC; 
    check_rdev_id_o : out STD_LOGIC; 
    clk_i : in STD_LOGIC := 'X'; 
    eval_check_i : in STD_LOGIC := 'X'; 
    check_rio_o : out STD_LOGIC; 
    check_rmem64_o : out STD_LOGIC; 
    check_rbus_id_o : out STD_LOGIC; 
    mem64_i : in STD_LOGIC := 'X'; 
    check_rhit_bar_o : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    check_raddr_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    addr_hi_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    check_rhit_bar_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    routing_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    req_id_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    addr_lo_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    req_id_cpl_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fulltype_oh_i : in STD_LOGIC_VECTOR ( 8 downto 0 ) 
  );
end tlm_rx_data_snk_bar;

architecture STRUCTURE of tlm_rx_data_snk_bar is
  signal Mshreg_eval_check_q3_25003 : STD_LOGIC; 
  signal Mshreg_lock_check_q3_25004 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal check_raddr_d_21_Q : STD_LOGIC; 
  signal check_raddr_d_22_Q : STD_LOGIC; 
  signal check_raddr_d_23_Q : STD_LOGIC; 
  signal check_raddr_d_24_Q : STD_LOGIC; 
  signal check_raddr_d_25_Q : STD_LOGIC; 
  signal check_raddr_d_26_Q : STD_LOGIC; 
  signal check_raddr_d_27_Q : STD_LOGIC; 
  signal check_raddr_d_28_Q : STD_LOGIC; 
  signal check_raddr_d_29_Q : STD_LOGIC; 
  signal check_raddr_d_30_Q : STD_LOGIC; 
  signal check_raddr_d_31_Q : STD_LOGIC; 
  signal check_raddr_d_48_Q : STD_LOGIC; 
  signal check_raddr_d_49_Q : STD_LOGIC; 
  signal check_raddr_d_50_Q : STD_LOGIC; 
  signal check_raddr_d_51_Q : STD_LOGIC; 
  signal check_raddr_d_52_Q : STD_LOGIC; 
  signal check_raddr_d_53_Q : STD_LOGIC; 
  signal check_raddr_d_54_Q : STD_LOGIC; 
  signal check_raddr_d_55_Q : STD_LOGIC; 
  signal check_raddr_d_56_Q : STD_LOGIC; 
  signal check_raddr_d_57_Q : STD_LOGIC; 
  signal check_raddr_d_58_Q : STD_LOGIC; 
  signal check_raddr_d_59_Q : STD_LOGIC; 
  signal check_raddr_d_60_Q : STD_LOGIC; 
  signal check_raddr_d_61_Q : STD_LOGIC; 
  signal check_raddr_d_62_Q : STD_LOGIC; 
  signal check_raddr_d_63_Q : STD_LOGIC; 
  signal check_rbus_id_d : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rbus_id_o : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rdev_id_o : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rfun_id_o : STD_LOGIC; 
  signal NlwRenamedSignal_check_rhit_o : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rio_o : STD_LOGIC; 
  signal check_rmem32_d : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rmem32_o : STD_LOGIC; 
  signal check_rmem32_o_or0000 : STD_LOGIC; 
  signal check_rmem64_d : STD_LOGIC; 
  signal NlwRenamedSig_OI_check_rmem64_o : STD_LOGIC; 
  signal check_rmemlock_d1a_25106 : STD_LOGIC; 
  signal eval_check_q1_25109 : STD_LOGIC; 
  signal eval_check_q1_inv : STD_LOGIC; 
  signal eval_check_q3_25111 : STD_LOGIC; 
  signal lock_check_q3_25118 : STD_LOGIC; 
  signal sent_check_q2_25156 : STD_LOGIC; 
  signal sent_check_q2_and0000_norst : STD_LOGIC; 
  signal sent_check_q3_25158 : STD_LOGIC; 
  signal NLW_Mshreg_eval_check_q3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_lock_check_q3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSignal_check_rhit_bar_o : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  check_rhit_src_rdy_o <= eval_check_q3_25111;
  check_rfun_id_o <= NlwRenamedSig_OI_check_rfun_id_o;
  check_rhit_lock_o <= lock_check_q3_25118;
  check_rhit_ack_o <= sent_check_q3_25158;
  NlwRenamedSignal_check_rhit_o <= check_rhit_i;
  check_rhit_o <= NlwRenamedSignal_check_rhit_o;
  check_rmem32_o <= NlwRenamedSig_OI_check_rmem32_o;
  check_rdev_id_o <= NlwRenamedSig_OI_check_rdev_id_o;
  check_rio_o <= NlwRenamedSig_OI_check_rio_o;
  check_rmem64_o <= NlwRenamedSig_OI_check_rmem64_o;
  check_rbus_id_o <= NlwRenamedSig_OI_check_rbus_id_o;
  check_rhit_bar_o(6) <= NlwRenamedSignal_check_rhit_bar_o(6);
  check_rhit_bar_o(5) <= NlwRenamedSignal_check_rhit_bar_o(5);
  check_rhit_bar_o(4) <= NlwRenamedSignal_check_rhit_bar_o(4);
  check_rhit_bar_o(3) <= NlwRenamedSignal_check_rhit_bar_o(3);
  check_rhit_bar_o(2) <= NlwRenamedSignal_check_rhit_bar_o(2);
  check_rhit_bar_o(1) <= NlwRenamedSignal_check_rhit_bar_o(1);
  check_rhit_bar_o(0) <= NlwRenamedSignal_check_rhit_bar_o(0);
  NlwRenamedSignal_check_rhit_bar_o(6) <= check_rhit_bar_i(6);
  NlwRenamedSignal_check_rhit_bar_o(5) <= check_rhit_bar_i(5);
  NlwRenamedSignal_check_rhit_bar_o(4) <= check_rhit_bar_i(4);
  NlwRenamedSignal_check_rhit_bar_o(3) <= check_rhit_bar_i(3);
  NlwRenamedSignal_check_rhit_bar_o(2) <= check_rhit_bar_i(2);
  NlwRenamedSignal_check_rhit_bar_o(1) <= check_rhit_bar_i(1);
  NlwRenamedSignal_check_rhit_bar_o(0) <= check_rhit_bar_i(0);
  check_rmem64_o_14239 : FDR
    port map (
      C => clk_i,
      D => check_rmem64_d,
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rmem64_o
    );
  check_raddr_o_21 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_21_Q,
      Q => check_raddr_o(21)
    );
  check_raddr_o_22 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_22_Q,
      Q => check_raddr_o(22)
    );
  check_raddr_o_23 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_23_Q,
      Q => check_raddr_o(23)
    );
  check_raddr_o_24 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_24_Q,
      Q => check_raddr_o(24)
    );
  check_raddr_o_25 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_25_Q,
      Q => check_raddr_o(25)
    );
  check_raddr_o_26 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_26_Q,
      Q => check_raddr_o(26)
    );
  check_raddr_o_27 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_27_Q,
      Q => check_raddr_o(27)
    );
  check_raddr_o_28 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_28_Q,
      Q => check_raddr_o(28)
    );
  check_raddr_o_29 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_29_Q,
      Q => check_raddr_o(29)
    );
  check_raddr_o_30 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_30_Q,
      Q => check_raddr_o(30)
    );
  check_raddr_o_31 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_31_Q,
      Q => check_raddr_o(31)
    );
  check_raddr_o_48 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_48_Q,
      Q => check_raddr_o(48)
    );
  check_raddr_o_49 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_49_Q,
      Q => check_raddr_o(49)
    );
  check_raddr_o_50 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_50_Q,
      Q => check_raddr_o(50)
    );
  check_raddr_o_51 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_51_Q,
      Q => check_raddr_o(51)
    );
  check_raddr_o_52 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_52_Q,
      Q => check_raddr_o(52)
    );
  check_raddr_o_53 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_53_Q,
      Q => check_raddr_o(53)
    );
  check_raddr_o_54 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_54_Q,
      Q => check_raddr_o(54)
    );
  check_raddr_o_55 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_55_Q,
      Q => check_raddr_o(55)
    );
  check_raddr_o_56 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_56_Q,
      Q => check_raddr_o(56)
    );
  check_raddr_o_57 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_57_Q,
      Q => check_raddr_o(57)
    );
  check_raddr_o_58 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_58_Q,
      Q => check_raddr_o(58)
    );
  check_raddr_o_59 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_59_Q,
      Q => check_raddr_o(59)
    );
  check_raddr_o_60 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_60_Q,
      Q => check_raddr_o(60)
    );
  check_raddr_o_61 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_61_Q,
      Q => check_raddr_o(61)
    );
  check_raddr_o_62 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_62_Q,
      Q => check_raddr_o(62)
    );
  check_raddr_o_63 : FDE
    port map (
      C => clk_i,
      CE => eval_check_i,
      D => check_raddr_d_63_Q,
      Q => check_raddr_o(63)
    );
  check_rmem32_o_14267 : FDR
    port map (
      C => clk_i,
      D => check_rmem32_d,
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rmem32_o
    );
  check_rmemlock_d1a : FDR
    port map (
      C => clk_i,
      D => fulltype_oh_i(4),
      R => check_rmem32_o_or0000,
      Q => check_rmemlock_d1a_25106
    );
  check_rio_o_14269 : FDR
    port map (
      C => clk_i,
      D => fulltype_oh_i(3),
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rio_o
    );
  check_rbus_id_o_14270 : FDR
    port map (
      C => clk_i,
      D => check_rbus_id_d,
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rbus_id_o
    );
  check_rdev_id_o_14271 : FDR
    port map (
      C => clk_i,
      D => check_rbus_id_d,
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rdev_id_o
    );
  check_rfun_id_o_14272 : FDR
    port map (
      C => clk_i,
      D => check_rbus_id_d,
      R => check_rmem32_o_or0000,
      Q => NlwRenamedSig_OI_check_rfun_id_o
    );
  eval_check_q1 : FD
    port map (
      C => clk_i,
      D => eval_check_i,
      Q => eval_check_q1_25109
    );
  sent_check_q2 : FDR
    port map (
      C => clk_i,
      D => sent_check_q2_and0000_norst,
      R => eval_check_q1_inv,
      Q => sent_check_q2_25156
    );
  sent_check_q3 : FD
    port map (
      C => clk_i,
      D => sent_check_q2_25156,
      Q => sent_check_q3_25158
    );
  check_rmem64_d1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(8),
      I1 => mem64_i,
      O => check_rmem64_d
    );
  check_rmem32_d1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => mem64_i,
      I1 => fulltype_oh_i(8),
      O => check_rmem32_d
    );
  check_raddr_d_mux0002_31_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(31),
      O => check_raddr_d_31_Q
    );
  check_raddr_d_mux0002_30_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(30),
      O => check_raddr_d_30_Q
    );
  check_raddr_d_mux0002_29_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(29),
      O => check_raddr_d_29_Q
    );
  check_raddr_d_mux0002_28_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(28),
      O => check_raddr_d_28_Q
    );
  check_raddr_d_mux0002_27_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(27),
      O => check_raddr_d_27_Q
    );
  check_raddr_d_mux0002_26_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(26),
      O => check_raddr_d_26_Q
    );
  check_raddr_d_mux0002_25_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(25),
      O => check_raddr_d_25_Q
    );
  check_raddr_d_mux0002_24_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(24),
      O => check_raddr_d_24_Q
    );
  check_raddr_d_mux0002_23_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(23),
      O => check_raddr_d_23_Q
    );
  check_raddr_d_mux0002_22_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(22),
      O => check_raddr_d_22_Q
    );
  check_raddr_d_mux0002_21_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_lo_i(21),
      O => check_raddr_d_21_Q
    );
  check_rbus_id_d1 : LUT5
    generic map(
      INIT => X"FFFF0008"
    )
    port map (
      I0 => routing_i(1),
      I1 => fulltype_oh_i(1),
      I2 => routing_i(0),
      I3 => routing_i(2),
      I4 => fulltype_oh_i(0),
      O => check_rbus_id_d
    );
  sent_check_q2_or00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => NlwRenamedSig_OI_check_rio_o,
      I1 => NlwRenamedSig_OI_check_rbus_id_o,
      I2 => NlwRenamedSig_OI_check_rdev_id_o,
      I3 => NlwRenamedSig_OI_check_rfun_id_o,
      I4 => NlwRenamedSig_OI_check_rmem32_o,
      I5 => NlwRenamedSig_OI_check_rmem64_o,
      O => sent_check_q2_and0000_norst
    );
  check_raddr_d_63_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(31),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(15),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(15),
      O => check_raddr_d_63_Q
    );
  check_raddr_d_62_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(30),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(14),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(14),
      O => check_raddr_d_62_Q
    );
  check_raddr_d_61_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(29),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(13),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(13),
      O => check_raddr_d_61_Q
    );
  check_raddr_d_60_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(28),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(12),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(12),
      O => check_raddr_d_60_Q
    );
  check_raddr_d_59_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(27),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(11),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(11),
      O => check_raddr_d_59_Q
    );
  check_raddr_d_58_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(26),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(10),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(10),
      O => check_raddr_d_58_Q
    );
  check_raddr_d_57_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(25),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(9),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(9),
      O => check_raddr_d_57_Q
    );
  check_raddr_d_56_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(24),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(8),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(8),
      O => check_raddr_d_56_Q
    );
  check_raddr_d_55_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(23),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(7),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(7),
      O => check_raddr_d_55_Q
    );
  check_raddr_d_54_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(22),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(6),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(6),
      O => check_raddr_d_54_Q
    );
  check_raddr_d_53_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(21),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(5),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(5),
      O => check_raddr_d_53_Q
    );
  check_raddr_d_52_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(20),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(4),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(4),
      O => check_raddr_d_52_Q
    );
  check_raddr_d_51_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(19),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(3),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(3),
      O => check_raddr_d_51_Q
    );
  check_raddr_d_50_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(18),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(2),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(2),
      O => check_raddr_d_50_Q
    );
  check_raddr_d_49_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(17),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(1),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(1),
      O => check_raddr_d_49_Q
    );
  check_raddr_d_48_1 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fulltype_oh_i(7),
      I1 => addr_hi_i(16),
      I2 => fulltype_oh_i(1),
      I3 => req_id_i(0),
      I4 => fulltype_oh_i(0),
      I5 => req_id_cpl_i(0),
      O => check_raddr_d_48_Q
    );
  check_rmem32_o_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => eval_check_i,
      I1 => reset_i,
      O => check_rmem32_o_or0000
    );
  eval_check_q1_inv1_INV_0 : INV
    port map (
      I => eval_check_q1_25109,
      O => eval_check_q1_inv
    );
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  Mshreg_eval_check_q3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      CE => N1,
      CLK => clk_i,
      D => eval_check_q1_25109,
      Q => Mshreg_eval_check_q3_25003,
      Q15 => NLW_Mshreg_eval_check_q3_Q15_UNCONNECTED
    );
  eval_check_q3 : FDE
    port map (
      C => clk_i,
      CE => N1,
      D => Mshreg_eval_check_q3_25003,
      Q => eval_check_q3_25111
    );
  Mshreg_lock_check_q3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N0,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      CE => N1,
      CLK => clk_i,
      D => check_rmemlock_d1a_25106,
      Q => Mshreg_lock_check_q3_25004,
      Q15 => NLW_Mshreg_lock_check_q3_Q15_UNCONNECTED
    );
  lock_check_q3 : FDE
    port map (
      C => clk_i,
      CE => N1,
      D => Mshreg_lock_check_q3_25004,
      Q => lock_check_q3_25118
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity tlm_rx_data_snk_pwr_mgmt is
  port (
    reset_i : in STD_LOGIC := 'X'; 
    ismsg_i : in STD_LOGIC := 'X'; 
    eval_pwr_mgmt_i : in STD_LOGIC := 'X'; 
    pm_turn_off_o : out STD_LOGIC; 
    eval_pwr_mgmt_data_i : in STD_LOGIC := 'X'; 
    pm_set_slot_pwr_o : out STD_LOGIC; 
    clk_i : in STD_LOGIC := 'X'; 
    act_pwr_mgmt_i : in STD_LOGIC := 'X'; 
    pm_as_nak_l1_o : out STD_LOGIC; 
    pm_msg_detect_o : out STD_LOGIC; 
    pm_set_slot_pwr_data_o : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    msgcode_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pwr_data_i : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end tlm_rx_data_snk_pwr_mgmt;

architecture STRUCTURE of tlm_rx_data_snk_pwr_mgmt is
  signal N01 : STD_LOGIC; 
  signal cur_pm_as_nak_l1_24983 : STD_LOGIC; 
  signal cur_pm_as_nak_l1_mux0000 : STD_LOGIC; 
  signal cur_pm_set_slot_pwr_24985 : STD_LOGIC; 
  signal cur_pm_set_slot_pwr_mux0000 : STD_LOGIC; 
  signal cur_pm_turn_off_24987 : STD_LOGIC; 
  signal cur_pm_turn_off_mux0000 : STD_LOGIC; 
  signal eval_pwr_mgmt_q1_24990 : STD_LOGIC; 
  signal pm_msg_detect_o_or0000 : STD_LOGIC; 
begin
  cur_pm_set_slot_pwr : FDRE
    port map (
      C => clk_i,
      CE => eval_pwr_mgmt_i,
      D => cur_pm_set_slot_pwr_mux0000,
      R => reset_i,
      Q => cur_pm_set_slot_pwr_24985
    );
  cur_pm_as_nak_l1 : FDRE
    port map (
      C => clk_i,
      CE => eval_pwr_mgmt_i,
      D => cur_pm_as_nak_l1_mux0000,
      R => reset_i,
      Q => cur_pm_as_nak_l1_24983
    );
  cur_pm_turn_off : FDRE
    port map (
      C => clk_i,
      CE => eval_pwr_mgmt_i,
      D => cur_pm_turn_off_mux0000,
      R => reset_i,
      Q => cur_pm_turn_off_24987
    );
  eval_pwr_mgmt_q1 : FDR
    port map (
      C => clk_i,
      D => eval_pwr_mgmt_i,
      R => reset_i,
      Q => eval_pwr_mgmt_q1_24990
    );
  pm_msg_detect_o_14232 : FDRE
    port map (
      C => clk_i,
      CE => eval_pwr_mgmt_q1_24990,
      D => pm_msg_detect_o_or0000,
      R => reset_i,
      Q => pm_msg_detect_o
    );
  pm_msg_detect_o_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => cur_pm_set_slot_pwr_24985,
      I1 => cur_pm_as_nak_l1_24983,
      I2 => cur_pm_turn_off_24987,
      O => pm_msg_detect_o_or0000
    );
  cur_pm_turn_off_mux00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => msgcode_i(0),
      I1 => N01,
      I2 => msgcode_i(3),
      I3 => msgcode_i(2),
      I4 => msgcode_i(6),
      O => cur_pm_turn_off_mux0000
    );
  cur_pm_set_slot_pwr_mux00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => N01,
      I1 => msgcode_i(6),
      I2 => msgcode_i(2),
      I3 => msgcode_i(3),
      I4 => msgcode_i(0),
      O => cur_pm_set_slot_pwr_mux0000
    );
  cur_pm_as_nak_l1_mux000011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => ismsg_i,
      I1 => msgcode_i(4),
      I2 => msgcode_i(7),
      I3 => msgcode_i(5),
      I4 => msgcode_i(1),
      O => N01
    );
  cur_pm_as_nak_l1_mux00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => N01,
      I1 => msgcode_i(2),
      I2 => msgcode_i(6),
      I3 => msgcode_i(3),
      I4 => msgcode_i(0),
      O => cur_pm_as_nak_l1_mux0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity tlm_rx_data_snk_mal is
  port (
    legacy_mode_i : in STD_LOGIC := 'X'; 
    reset_i : in STD_LOGIC := 'X'; 
    tlp_uc_o : out STD_LOGIC; 
    eval_formats_i : in STD_LOGIC := 'X'; 
    rem_i : in STD_LOGIC := 'X'; 
    td_i : in STD_LOGIC := 'X'; 
    tlp_ur_lock_o : out STD_LOGIC; 
    hit_src_rdy_i : in STD_LOGIC := 'X'; 
    hit_i : in STD_LOGIC := 'X'; 
    length_1dw_i : in STD_LOGIC := 'X'; 
    tlp_filt_o : out STD_LOGIC; 
    hit_lock_i : in STD_LOGIC := 'X'; 
    malformed_o : out STD_LOGIC; 
    ext_cfg_access_i : in STD_LOGIC := 'X'; 
    legacy_cfg_access_i : in STD_LOGIC := 'X'; 
    cfg_o : out STD_LOGIC; 
    hit_ack_i : in STD_LOGIC := 'X'; 
    tc0_i : in STD_LOGIC := 'X'; 
    load_aperture_i : in STD_LOGIC := 'X'; 
    eof_i : in STD_LOGIC := 'X'; 
    eval_fulltype_i : in STD_LOGIC := 'X'; 
    eval_msgcode_i : in STD_LOGIC := 'X'; 
    clk_i : in STD_LOGIC := 'X'; 
    hp_msg_detect_o : out STD_LOGIC; 
    sof_i : in STD_LOGIC := 'X'; 
    hit_lat3_i : in STD_LOGIC := 'X'; 
    pwr_mgmt_on_i : in STD_LOGIC := 'X'; 
    data_credits_vld_o : out STD_LOGIC; 
    tlp_ur_o : out STD_LOGIC; 
    data_credits_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    max_payload_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    fulltype_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    offset_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    msgcode_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    length_i : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    aperture_i : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end tlm_rx_data_snk_mal;

architecture STRUCTURE of tlm_rx_data_snk_mal is
  signal Mrom_delay_ct_mux0000 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_cy_3_1 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_cy_3_11_24792 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_2_1 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_2_11_24794 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_3_1 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_3_11_24796 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_5_1 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_5_11_24798 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_6_1 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_xor_6_11_24800 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal N151 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal N55 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal cfg0_ip_24817 : STD_LOGIC; 
  signal cfg0_ip_and0000 : STD_LOGIC; 
  signal cfg1_ip_24819 : STD_LOGIC; 
  signal cfg_o_or0000 : STD_LOGIC; 
  signal cpl_ip_24823 : STD_LOGIC; 
  signal cpl_ip_or0000 : STD_LOGIC; 
  signal delay_ct_24825 : STD_LOGIC; 
  signal delay_ct_inv : STD_LOGIC; 
  signal delay_ct_or0000 : STD_LOGIC; 
  signal eof_q1_24829 : STD_LOGIC; 
  signal eof_q2_24830 : STD_LOGIC; 
  signal eval_formats_q_24832 : STD_LOGIC; 
  signal filter_msgcode_24835 : STD_LOGIC; 
  signal filter_msgcode_mux0000 : STD_LOGIC; 
  signal filter_msgcode_q_24837 : STD_LOGIC; 
  signal fulltype_tc0_24852 : STD_LOGIC; 
  signal fulltype_tc0_or0000_24853 : STD_LOGIC; 
  signal hp_msg_detect_o_and0000 : STD_LOGIC; 
  signal ismsgany_24860 : STD_LOGIC; 
  signal ismsgany_mux0000 : STD_LOGIC; 
  signal load_aperture_q_24874 : STD_LOGIC; 
  signal malformed_eof_24875 : STD_LOGIC; 
  signal malformed_eof_and0000_24876 : STD_LOGIC; 
  signal malformed_fmt_24877 : STD_LOGIC; 
  signal malformed_fmt_or0000 : STD_LOGIC; 
  signal malformed_fmt_or00001_24879 : STD_LOGIC; 
  signal malformed_fmt_or00002_24880 : STD_LOGIC; 
  signal malformed_fulltype_24881 : STD_LOGIC; 
  signal malformed_fulltype_mux0000 : STD_LOGIC; 
  signal malformed_len_24883 : STD_LOGIC; 
  signal malformed_len_or0000 : STD_LOGIC; 
  signal malformed_maxsize_24885 : STD_LOGIC; 
  signal malformed_maxsize_and0000 : STD_LOGIC; 
  signal malformed_maxsize_and000031 : STD_LOGIC; 
  signal malformed_maxsize_and0000311_24888 : STD_LOGIC; 
  signal malformed_maxsize_and0000312_24889 : STD_LOGIC; 
  signal malformed_maxsize_and000097_24890 : STD_LOGIC; 
  signal malformed_message_24891 : STD_LOGIC; 
  signal malformed_message_mux0000_24892 : STD_LOGIC; 
  signal malformed_min_24893 : STD_LOGIC; 
  signal malformed_min_and0000 : STD_LOGIC; 
  signal malformed_min_mux0000 : STD_LOGIC; 
  signal malformed_min_mux00001_24896 : STD_LOGIC; 
  signal malformed_min_mux00002_24897 : STD_LOGIC; 
  signal malformed_o_or0000 : STD_LOGIC; 
  signal malformed_over_24900 : STD_LOGIC; 
  signal malformed_over_and0000_24901 : STD_LOGIC; 
  signal malformed_rem_24902 : STD_LOGIC; 
  signal malformed_rem_xor0000 : STD_LOGIC; 
  signal malformed_tc_24904 : STD_LOGIC; 
  signal malformed_tc_mux0000 : STD_LOGIC; 
  signal max_length_cmp_eq00001 : STD_LOGIC; 
  signal max_length_mux0000_3_1 : STD_LOGIC; 
  signal msgcode_dmatch_24913 : STD_LOGIC; 
  signal msgcode_dmatch_mux0000 : STD_LOGIC; 
  signal msgcode_dmatch_mux000010_24915 : STD_LOGIC; 
  signal msgcode_hotplug_24916 : STD_LOGIC; 
  signal msgcode_hotplug_or0000 : STD_LOGIC; 
  signal msgcode_legacy_24926 : STD_LOGIC; 
  signal msgcode_legacy_cmp_eq0000 : STD_LOGIC; 
  signal msgcode_sigdef_24934 : STD_LOGIC; 
  signal msgcode_sigdef_mux0000 : STD_LOGIC; 
  signal msgcode_sigdef_mux00004 : STD_LOGIC; 
  signal msgcode_vendef_24937 : STD_LOGIC; 
  signal msgcode_vendef_or0000 : STD_LOGIC; 
  signal msgcode_vendef_or00001_24939 : STD_LOGIC; 
  signal routing_vendef_24942 : STD_LOGIC; 
  signal routing_vendef_or0000 : STD_LOGIC; 
  signal sof_q1_24945 : STD_LOGIC; 
  signal tlp_uc_o_mux0000 : STD_LOGIC; 
  signal tlp_ur_lock_o_mux0000 : STD_LOGIC; 
  signal tlp_ur_o_mux0000 : STD_LOGIC; 
  signal type_1dw_24955 : STD_LOGIC; 
  signal type_1dw_or0000 : STD_LOGIC; 
  signal uc_cpl_lk_24957 : STD_LOGIC; 
  signal uc_cpl_lk_or0000 : STD_LOGIC; 
  signal uc_format_24959 : STD_LOGIC; 
  signal ur_format_24960 : STD_LOGIC; 
  signal ur_format_lock_24961 : STD_LOGIC; 
  signal ur_format_or0000 : STD_LOGIC; 
  signal ur_mem_lk_24963 : STD_LOGIC; 
  signal ur_mem_lk_or0000 : STD_LOGIC; 
  signal ur_pwr_mgmt_and0000 : STD_LOGIC; 
  signal ur_type1_cfg_24966 : STD_LOGIC; 
  signal Msub_word_ct_sub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal fulltype_in : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal max_length : STD_LOGIC_VECTOR ( 6 downto 5 ); 
  signal msgcode_routing : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal msgcode_routing_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal word_ct : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal word_ct_sub0000 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  max_length_5 : FD
    port map (
      C => clk_i,
      D => max_length_cmp_eq00001,
      Q => max_length(5)
    );
  max_length_6 : FD
    port map (
      C => clk_i,
      D => max_length_mux0000_3_1,
      Q => max_length(6)
    );
  malformed_maxsize : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => malformed_maxsize_and0000,
      R => reset_i,
      Q => malformed_maxsize_24885
    );
  malformed_min : FDRS
    port map (
      C => clk_i,
      D => malformed_min_mux0000,
      R => reset_i,
      S => malformed_min_and0000,
      Q => malformed_min_24893
    );
  type_1dw : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => type_1dw_or0000,
      R => reset_i,
      Q => type_1dw_24955
    );
  malformed_eof : FDR
    port map (
      C => clk_i,
      D => malformed_eof_and0000_24876,
      R => reset_i,
      Q => malformed_eof_24875
    );
  malformed_over : FDR
    port map (
      C => clk_i,
      D => malformed_over_and0000_24901,
      R => reset_i,
      Q => malformed_over_24900
    );
  malformed_o_14086 : FDRE
    port map (
      C => clk_i,
      CE => eof_q2_24830,
      D => malformed_o_or0000,
      R => reset_i,
      Q => malformed_o
    );
  malformed_fmt : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => malformed_fmt_or0000,
      R => reset_i,
      Q => malformed_fmt_24877
    );
  fulltype_in_0 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(0),
      Q => fulltype_in(0)
    );
  fulltype_in_1 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(1),
      Q => fulltype_in(1)
    );
  fulltype_in_2 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(2),
      Q => fulltype_in(2)
    );
  fulltype_in_3 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(3),
      Q => fulltype_in(3)
    );
  fulltype_in_4 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(4),
      Q => fulltype_in(4)
    );
  fulltype_in_5 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(5),
      Q => fulltype_in(5)
    );
  fulltype_in_6 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_i(6),
      Q => fulltype_in(6)
    );
  ismsgany : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => ismsgany_mux0000,
      Q => ismsgany_24860
    );
  fulltype_tc0 : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => fulltype_tc0_or0000_24853,
      Q => fulltype_tc0_24852
    );
  malformed_tc : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => malformed_tc_mux0000,
      R => reset_i,
      Q => malformed_tc_24904
    );
  malformed_fulltype : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => malformed_fulltype_mux0000,
      R => reset_i,
      Q => malformed_fulltype_24881
    );
  cpl_ip : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => cpl_ip_or0000,
      R => reset_i,
      Q => cpl_ip_24823
    );
  ur_mem_lk : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => ur_mem_lk_or0000,
      R => reset_i,
      Q => ur_mem_lk_24963
    );
  uc_cpl_lk : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => uc_cpl_lk_or0000,
      R => reset_i,
      Q => uc_cpl_lk_24957
    );
  ur_type1_cfg : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => ur_pwr_mgmt_and0000,
      R => reset_i,
      Q => ur_type1_cfg_24966
    );
  ur_format : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => ur_format_or0000,
      R => reset_i,
      Q => ur_format_24960
    );
  uc_format : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => uc_cpl_lk_24957,
      R => reset_i,
      Q => uc_format_24959
    );
  tlp_uc_o_14105 : FDRE
    port map (
      C => clk_i,
      CE => hit_src_rdy_i,
      D => tlp_uc_o_mux0000,
      R => reset_i,
      Q => tlp_uc_o
    );
  tlp_ur_o_14106 : FDRE
    port map (
      C => clk_i,
      CE => hit_src_rdy_i,
      D => tlp_ur_o_mux0000,
      R => reset_i,
      Q => tlp_ur_o
    );
  tlp_ur_lock_o_14107 : FDRE
    port map (
      C => clk_i,
      CE => hit_src_rdy_i,
      D => tlp_ur_lock_o_mux0000,
      R => reset_i,
      Q => tlp_ur_lock_o
    );
  msgcode_sigdef : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_sigdef_mux0000,
      Q => msgcode_sigdef_24934
    );
  routing_vendef : FDE
    port map (
      C => clk_i,
      CE => eval_fulltype_i,
      D => routing_vendef_or0000,
      Q => routing_vendef_24942
    );
  malformed_message : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => malformed_message_mux0000_24892,
      R => reset_i,
      Q => malformed_message_24891
    );
  msgcode_legacy : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_legacy_cmp_eq0000,
      Q => msgcode_legacy_24926
    );
  msgcode_hotplug : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_hotplug_or0000,
      Q => msgcode_hotplug_24916
    );
  msgcode_vendef : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_vendef_or0000,
      Q => msgcode_vendef_24937
    );
  filter_msgcode : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => filter_msgcode_mux0000,
      R => reset_i,
      Q => filter_msgcode_24835
    );
  cfg0_ip : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => cfg0_ip_and0000,
      R => reset_i,
      Q => cfg0_ip_24817
    );
  cfg1_ip : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk_i,
      CE => eval_formats_i,
      D => ur_pwr_mgmt_and0000,
      R => reset_i,
      Q => cfg1_ip_24819
    );
  load_aperture_q : FDR
    port map (
      C => clk_i,
      D => load_aperture_i,
      R => reset_i,
      Q => load_aperture_q_24874
    );
  sof_q1 : FDR
    port map (
      C => clk_i,
      D => sof_i,
      R => reset_i,
      Q => sof_q1_24945
    );
  eval_formats_q : FDR
    port map (
      C => clk_i,
      D => eval_formats_i,
      R => reset_i,
      Q => eval_formats_q_24832
    );
  eof_q1 : FDR
    port map (
      C => clk_i,
      D => eof_i,
      R => reset_i,
      Q => eof_q1_24829
    );
  msgcode_dmatch : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_dmatch_mux0000,
      Q => msgcode_dmatch_24913
    );
  msgcode_routing_0 : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_routing_mux0000(2),
      Q => msgcode_routing(0)
    );
  msgcode_routing_1 : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_routing_mux0000(1),
      Q => msgcode_routing(1)
    );
  msgcode_routing_2 : FDE
    port map (
      C => clk_i,
      CE => eval_msgcode_i,
      D => msgcode_routing_mux0000(0),
      Q => msgcode_routing(2)
    );
  malformed_len : FDRE
    port map (
      C => clk_i,
      CE => eof_q1_24829,
      D => malformed_len_or0000,
      R => reset_i,
      Q => malformed_len_24883
    );
  ur_format_lock : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => ur_mem_lk_24963,
      R => reset_i,
      Q => ur_format_lock_24961
    );
  filter_msgcode_q : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => filter_msgcode_24835,
      R => reset_i,
      Q => filter_msgcode_q_24837
    );
  cfg_o_14128 : FDRE
    port map (
      C => clk_i,
      CE => load_aperture_q_24874,
      D => cfg_o_or0000,
      R => reset_i,
      Q => cfg_o
    );
  hp_msg_detect_o_14129 : FDRE
    port map (
      C => clk_i,
      CE => eval_formats_q_24832,
      D => hp_msg_detect_o_and0000,
      R => reset_i,
      Q => hp_msg_detect_o
    );
  eof_q2 : FDR
    port map (
      C => clk_i,
      D => eof_q1_24829,
      R => reset_i,
      Q => eof_q2_24830
    );
  delay_ct : FDR
    port map (
      C => clk_i,
      D => Mrom_delay_ct_mux0000,
      R => delay_ct_or0000,
      Q => delay_ct_24825
    );
  malformed_rem : FDR
    port map (
      C => clk_i,
      D => malformed_rem_xor0000,
      R => reset_i,
      Q => malformed_rem_24902
    );
  tlp_filt_o_14133 : FDRE
    port map (
      C => clk_i,
      CE => hit_src_rdy_i,
      D => filter_msgcode_q_24837,
      R => reset_i,
      Q => tlp_filt_o
    );
  word_ct_0 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(0),
      R => reset_i,
      Q => word_ct(0)
    );
  word_ct_1 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(1),
      R => reset_i,
      Q => word_ct(1)
    );
  word_ct_2 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(2),
      R => reset_i,
      Q => word_ct(2)
    );
  word_ct_3 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(3),
      R => reset_i,
      Q => word_ct(3)
    );
  word_ct_4 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(4),
      R => reset_i,
      Q => word_ct(4)
    );
  word_ct_5 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(5),
      R => reset_i,
      Q => word_ct(5)
    );
  word_ct_6 : FDRE
    port map (
      C => clk_i,
      CE => delay_ct_inv,
      D => word_ct_sub0000(6),
      R => reset_i,
      Q => word_ct(6)
    );
  ur_format_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => ur_type1_cfg_24966,
      I1 => ur_mem_lk_24963,
      O => ur_format_or0000
    );
  malformed_o_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => malformed_len_24883,
      I1 => malformed_fmt_24877,
      O => malformed_o_or0000
    );
  hp_msg_detect_o_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => ismsgany_24860,
      I1 => msgcode_hotplug_24916,
      O => hp_msg_detect_o_and0000
    );
  filter_msgcode_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => ismsgany_24860,
      I1 => msgcode_legacy_24926,
      O => filter_msgcode_mux0000
    );
  cfg_o_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => cfg1_ip_24819,
      I1 => cfg0_ip_24817,
      O => cfg_o_or0000
    );
  msgcode_dmatch_mux000031 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => fulltype_i(4),
      I1 => fulltype_i(5),
      I2 => fulltype_i(3),
      O => ismsgany_mux0000
    );
  routing_vendef_or00001 : LUT3
    generic map(
      INIT => X"26"
    )
    port map (
      I0 => fulltype_i(1),
      I1 => fulltype_i(2),
      I2 => fulltype_i(0),
      O => routing_vendef_or0000
    );
  tlp_ur_o_mux00001 : LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      I0 => ur_format_24960,
      I1 => hit_i,
      I2 => hit_ack_i,
      I3 => cpl_ip_24823,
      O => tlp_ur_o_mux0000
    );
  tlp_uc_o_mux00001 : LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      I0 => cpl_ip_24823,
      I1 => hit_ack_i,
      I2 => hit_i,
      I3 => uc_format_24959,
      O => tlp_uc_o_mux0000
    );
  malformed_tc_mux00001 : LUT4
    generic map(
      INIT => X"5540"
    )
    port map (
      I0 => tc0_i,
      I1 => ismsgany_24860,
      I2 => msgcode_sigdef_24934,
      I3 => fulltype_tc0_24852,
      O => malformed_tc_mux0000
    );
  malformed_len_or00001 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => malformed_rem_24902,
      I1 => malformed_min_24893,
      I2 => malformed_eof_24875,
      I3 => malformed_over_24900,
      O => malformed_len_or0000
    );
  Msub_word_ct_sub0000_xor_0_11 : LUT4
    generic map(
      INIT => X"2A7F"
    )
    port map (
      I0 => eval_formats_i,
      I1 => length_i(1),
      I2 => fulltype_in(6),
      I3 => word_ct(0),
      O => word_ct_sub0000(0)
    );
  Mrom_delay_ct_mux00001 : LUT4
    generic map(
      INIT => X"EA80"
    )
    port map (
      I0 => td_i,
      I1 => length_i(0),
      I2 => fulltype_in(6),
      I3 => fulltype_in(5),
      O => Mrom_delay_ct_mux0000
    );
  cpl_ip_or00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => fulltype_in(1),
      I1 => fulltype_in(3),
      I2 => fulltype_in(5),
      I3 => fulltype_in(4),
      I4 => fulltype_in(2),
      O => cpl_ip_or0000
    );
  ur_pwr_mgmt_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => fulltype_in(0),
      I1 => fulltype_in(2),
      I2 => fulltype_in(5),
      I3 => fulltype_in(1),
      I4 => fulltype_in(3),
      I5 => fulltype_in(4),
      O => ur_pwr_mgmt_and0000
    );
  ur_mem_lk_or00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => fulltype_in(0),
      I1 => fulltype_in(2),
      I2 => fulltype_in(6),
      I3 => fulltype_in(1),
      I4 => fulltype_in(3),
      I5 => fulltype_in(4),
      O => ur_mem_lk_or0000
    );
  uc_cpl_lk_or000021 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => fulltype_in(0),
      I1 => fulltype_in(3),
      I2 => fulltype_in(5),
      I3 => fulltype_in(1),
      I4 => fulltype_in(4),
      I5 => fulltype_in(2),
      O => uc_cpl_lk_or0000
    );
  cfg0_ip_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => fulltype_in(2),
      I1 => fulltype_in(0),
      I2 => fulltype_in(5),
      I3 => fulltype_in(1),
      I4 => fulltype_in(3),
      I5 => fulltype_in(4),
      O => cfg0_ip_and0000
    );
  tlp_ur_lock_o_mux00001 : LUT6
    generic map(
      INIT => X"8888888888D88888"
    )
    port map (
      I0 => ur_format_24960,
      I1 => ur_format_lock_24961,
      I2 => hit_lock_i,
      I3 => hit_i,
      I4 => hit_ack_i,
      I5 => cpl_ip_24823,
      O => tlp_ur_lock_o_mux0000
    );
  Msub_word_ct_sub0000_xor_1_11 : LUT6
    generic map(
      INIT => X"D78282D7FFAAAAFF"
    )
    port map (
      I0 => eval_formats_i,
      I1 => length_i(1),
      I2 => length_i(2),
      I3 => word_ct(1),
      I4 => word_ct(0),
      I5 => fulltype_in(6),
      O => word_ct_sub0000(1)
    );
  type_1dw_or000011 : LUT6
    generic map(
      INIT => X"0000001100000100"
    )
    port map (
      I0 => fulltype_in(3),
      I1 => fulltype_in(5),
      I2 => fulltype_in(0),
      I3 => fulltype_in(1),
      I4 => fulltype_in(4),
      I5 => fulltype_in(2),
      O => type_1dw_or0000
    );
  msgcode_legacy_cmp_eq00001 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => msgcode_i(6),
      I1 => msgcode_i(4),
      I2 => msgcode_i(2),
      I3 => N18,
      O => msgcode_legacy_cmp_eq0000
    );
  max_length_mux0000_3_11 : LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      I0 => reset_i,
      I1 => max_payload_i(0),
      I2 => max_payload_i(1),
      I3 => max_payload_i(2),
      O => max_length_mux0000_3_1
    );
  max_length_cmp_eq000011 : LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      I0 => max_payload_i(0),
      I1 => max_payload_i(1),
      I2 => max_payload_i(2),
      I3 => reset_i,
      O => max_length_cmp_eq00001
    );
  malformed_rem_xor00001 : LUT5
    generic map(
      INIT => X"69999666"
    )
    port map (
      I0 => td_i,
      I1 => fulltype_in(5),
      I2 => length_i(0),
      I3 => fulltype_in(6),
      I4 => rem_i,
      O => malformed_rem_xor0000
    );
  msgcode_routing_mux0000_1_SW0 : LUT3
    generic map(
      INIT => X"7E"
    )
    port map (
      I0 => msgcode_i(4),
      I1 => msgcode_i(3),
      I2 => msgcode_i(0),
      O => N6
    );
  msgcode_routing_mux0000_1_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => msgcode_i(7),
      I1 => msgcode_i(6),
      I2 => msgcode_i(5),
      I3 => msgcode_i(2),
      I4 => msgcode_i(1),
      I5 => N6,
      O => msgcode_routing_mux0000(1)
    );
  malformed_eof_and0000_SW0 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => word_ct(0),
      I1 => word_ct(6),
      I2 => word_ct(5),
      I3 => delay_ct_24825,
      I4 => word_ct(4),
      O => N151
    );
  malformed_eof_and0000_SW1 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => word_ct(0),
      I1 => word_ct(6),
      I2 => word_ct(5),
      I3 => delay_ct_24825,
      I4 => word_ct(4),
      O => N16
    );
  malformed_eof_and0000 : LUT6
    generic map(
      INIT => X"1133332333333323"
    )
    port map (
      I0 => word_ct(1),
      I1 => eval_formats_i,
      I2 => N151,
      I3 => word_ct(3),
      I4 => word_ct(2),
      I5 => N16,
      O => malformed_eof_and0000_24876
    );
  msgcode_sigdef_mux000031 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => msgcode_i(0),
      I1 => msgcode_i(1),
      I2 => msgcode_i(3),
      I3 => msgcode_i(7),
      I4 => msgcode_i(5),
      O => N18
    );
  malformed_over_and0000_SW0 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => word_ct(5),
      I1 => word_ct(6),
      I2 => delay_ct_24825,
      I3 => word_ct(4),
      I4 => word_ct(0),
      O => N24
    );
  malformed_over_and0000 : LUT6
    generic map(
      INIT => X"00FF00FF00800000"
    )
    port map (
      I0 => word_ct(3),
      I1 => word_ct(2),
      I2 => word_ct(1),
      I3 => eval_formats_i,
      I4 => N24,
      I5 => malformed_over_24900,
      O => malformed_over_and0000_24901
    );
  msgcode_dmatch_mux000010 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => msgcode_i(0),
      I1 => msgcode_i(1),
      I2 => msgcode_i(2),
      I3 => msgcode_i(3),
      I4 => msgcode_i(5),
      I5 => msgcode_i(7),
      O => msgcode_dmatch_mux000010_24915
    );
  delay_ct_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => eval_formats_i,
      I1 => reset_i,
      O => delay_ct_or0000
    );
  msgcode_routing_mux0000_2_1 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => N22,
      I1 => msgcode_i(6),
      I2 => msgcode_i(4),
      I3 => msgcode_i(2),
      I4 => N18,
      O => msgcode_routing_mux0000(2)
    );
  Msub_word_ct_sub0000_xor_4_11 : LUT5
    generic map(
      INIT => X"A6669555"
    )
    port map (
      I0 => Msub_word_ct_sub0000_cy(3),
      I1 => eval_formats_i,
      I2 => fulltype_in(6),
      I3 => length_i(5),
      I4 => word_ct(4),
      O => word_ct_sub0000(4)
    );
  malformed_message_mux0000_SW0 : LUT5
    generic map(
      INIT => X"6FF6FFFF"
    )
    port map (
      I0 => fulltype_in(0),
      I1 => msgcode_routing(0),
      I2 => msgcode_routing(1),
      I3 => fulltype_in(1),
      I4 => msgcode_dmatch_24913,
      O => N28
    );
  malformed_message_mux0000 : LUT6
    generic map(
      INIT => X"4554EFFE5555FFFF"
    )
    port map (
      I0 => msgcode_vendef_24937,
      I1 => N28,
      I2 => fulltype_in(2),
      I3 => msgcode_routing(2),
      I4 => routing_vendef_24942,
      I5 => msgcode_sigdef_24934,
      O => malformed_message_mux0000_24892
    );
  malformed_maxsize_and000097 : LUT4
    generic map(
      INIT => X"A2F2"
    )
    port map (
      I0 => length_i(6),
      I1 => max_length(5),
      I2 => length_i(5),
      I3 => max_length(6),
      O => malformed_maxsize_and000097_24890
    );
  malformed_min_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => sof_i,
      I1 => eof_i,
      O => malformed_min_and0000
    );
  msgcode_routing_mux0000_0_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => msgcode_i(1),
      I1 => N22,
      I2 => N15,
      O => msgcode_routing_mux0000(0)
    );
  msgcode_sigdef_mux000021 : LUT5
    generic map(
      INIT => X"FFFF6400"
    )
    port map (
      I0 => msgcode_i(2),
      I1 => msgcode_i(6),
      I2 => msgcode_i(4),
      I3 => N18,
      I4 => msgcode_hotplug_or0000,
      O => N15
    );
  msgcode_sigdef_mux00001 : LUT6
    generic map(
      INIT => X"FF10FFFFFF10FF10"
    )
    port map (
      I0 => msgcode_i(2),
      I1 => msgcode_i(4),
      I2 => N18,
      I3 => N15,
      I4 => msgcode_i(1),
      I5 => N22,
      O => msgcode_sigdef_mux0000
    );
  msgcode_sigdef_mux000022_SW0 : LUT4
    generic map(
      INIT => X"F2E2"
    )
    port map (
      I0 => msgcode_i(1),
      I1 => msgcode_i(0),
      I2 => msgcode_i(3),
      I3 => msgcode_i(2),
      O => N35
    );
  msgcode_sigdef_mux000022 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => msgcode_i(6),
      I1 => msgcode_i(7),
      I2 => msgcode_i(5),
      I3 => msgcode_i(4),
      I4 => N35,
      O => msgcode_hotplug_or0000
    );
  msgcode_dmatch_mux000085_SW0 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => fulltype_i(3),
      I1 => fulltype_i(4),
      I2 => fulltype_i(5),
      I3 => fulltype_i(6),
      O => N45
    );
  msgcode_dmatch_mux000085 : LUT6
    generic map(
      INIT => X"31333133B9333133"
    )
    port map (
      I0 => msgcode_i(4),
      I1 => N45,
      I2 => msgcode_dmatch_mux000010_24915,
      I3 => msgcode_i(6),
      I4 => N18,
      I5 => msgcode_i(2),
      O => msgcode_dmatch_mux0000
    );
  malformed_maxsize_and0000126_SW0 : LUT6
    generic map(
      INIT => X"AAA8AAA8AAA8AAAB"
    )
    port map (
      I0 => malformed_maxsize_and000097_24890,
      I1 => length_i(0),
      I2 => length_i(1),
      I3 => length_i(2),
      I4 => length_i(5),
      I5 => length_i(6),
      O => N49
    );
  malformed_maxsize_and0000126 : LUT6
    generic map(
      INIT => X"AAAAAAAAA0A2A080"
    )
    port map (
      I0 => fulltype_in(6),
      I1 => length_i(3),
      I2 => malformed_maxsize_and000097_24890,
      I3 => length_i(4),
      I4 => N49,
      I5 => malformed_maxsize_and000031,
      O => malformed_maxsize_and0000
    );
  malformed_fulltype_mux00001 : MUXF7
    port map (
      I0 => N53,
      I1 => N54,
      S => fulltype_in(6),
      O => malformed_fulltype_mux0000
    );
  malformed_fulltype_mux00001_F : LUT6
    generic map(
      INIT => X"FF76FF76EF72EF62"
    )
    port map (
      I0 => fulltype_in(4),
      I1 => fulltype_in(5),
      I2 => fulltype_in(1),
      I3 => fulltype_in(3),
      I4 => fulltype_in(0),
      I5 => fulltype_in(2),
      O => N53
    );
  malformed_fulltype_mux00001_G : LUT6
    generic map(
      INIT => X"AAFFAAFEFFE7FFE2"
    )
    port map (
      I0 => fulltype_in(3),
      I1 => fulltype_in(1),
      I2 => fulltype_in(2),
      I3 => fulltype_in(4),
      I4 => fulltype_in(0),
      I5 => fulltype_in(5),
      O => N54
    );
  fulltype_tc0_or0000 : MUXF7
    port map (
      I0 => N55,
      I1 => N56,
      S => fulltype_i(5),
      O => fulltype_tc0_or0000_24853
    );
  fulltype_tc0_or0000_F : LUT6
    generic map(
      INIT => X"0410011004110110"
    )
    port map (
      I0 => fulltype_i(4),
      I1 => fulltype_i(3),
      I2 => fulltype_i(2),
      I3 => fulltype_i(1),
      I4 => fulltype_i(0),
      I5 => fulltype_i(6),
      O => N55
    );
  fulltype_tc0_or0000_G : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => fulltype_i(0),
      I1 => fulltype_i(6),
      I2 => fulltype_i(4),
      I3 => fulltype_i(1),
      I4 => fulltype_i(2),
      I5 => fulltype_i(3),
      O => N56
    );
  delay_ct_inv1_INV_0 : INV
    port map (
      I => delay_ct_24825,
      O => delay_ct_inv
    );
  XST_GND : GND
    port map (
      G => N58
    );
  malformed_fmt_or00001 : LUT6
    generic map(
      INIT => X"FFFFFEFFFEFFFEFF"
    )
    port map (
      I0 => malformed_maxsize_24885,
      I1 => malformed_fulltype_24881,
      I2 => malformed_tc_24904,
      I3 => length_1dw_i,
      I4 => malformed_message_24891,
      I5 => ismsgany_24860,
      O => malformed_fmt_or00001_24879
    );
  malformed_fmt_or00002 : LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
    port map (
      I0 => malformed_fulltype_24881,
      I1 => malformed_maxsize_24885,
      I2 => malformed_message_24891,
      I3 => ismsgany_24860,
      I4 => malformed_tc_24904,
      O => malformed_fmt_or00002_24880
    );
  malformed_fmt_or0000_f7 : MUXF7
    port map (
      I0 => malformed_fmt_or00002_24880,
      I1 => malformed_fmt_or00001_24879,
      S => type_1dw_24955,
      O => malformed_fmt_or0000
    );
  Msub_word_ct_sub0000_xor_2_11 : LUT4
    generic map(
      INIT => X"A9FF"
    )
    port map (
      I0 => length_i(3),
      I1 => length_i(2),
      I2 => length_i(1),
      I3 => fulltype_in(6),
      O => Msub_word_ct_sub0000_xor_2_1
    );
  Msub_word_ct_sub0000_xor_2_12 : LUT3
    generic map(
      INIT => X"C9"
    )
    port map (
      I0 => word_ct(1),
      I1 => word_ct(2),
      I2 => word_ct(0),
      O => Msub_word_ct_sub0000_xor_2_11_24794
    );
  Msub_word_ct_sub0000_xor_2_1_f7 : MUXF7
    port map (
      I0 => Msub_word_ct_sub0000_xor_2_11_24794,
      I1 => Msub_word_ct_sub0000_xor_2_1,
      S => eval_formats_i,
      O => word_ct_sub0000(2)
    );
  msgcode_vendef_or00001 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => msgcode_i(4),
      I1 => msgcode_i(6),
      I2 => msgcode_i(5),
      I3 => msgcode_i(3),
      I4 => msgcode_i(2),
      I5 => msgcode_i(1),
      O => msgcode_vendef_or00001_24939
    );
  msgcode_vendef_or0000_f7 : MUXF7
    port map (
      I0 => msgcode_vendef_or00001_24939,
      I1 => N58,
      S => msgcode_i(7),
      O => msgcode_vendef_or0000
    );
  malformed_min_mux00001 : LUT5
    generic map(
      INIT => X"C0C080C0"
    )
    port map (
      I0 => fulltype_in(5),
      I1 => sof_q1_24945,
      I2 => eof_i,
      I3 => rem_i,
      I4 => fulltype_in(6),
      O => malformed_min_mux00001_24896
    );
  malformed_min_mux00002 : LUT6
    generic map(
      INIT => X"8000888080808880"
    )
    port map (
      I0 => eof_i,
      I1 => sof_q1_24945,
      I2 => fulltype_in(6),
      I3 => fulltype_in(5),
      I4 => rem_i,
      I5 => length_1dw_i,
      O => malformed_min_mux00002_24897
    );
  malformed_min_mux0000_f7 : MUXF7
    port map (
      I0 => malformed_min_mux00002_24897,
      I1 => malformed_min_mux00001_24896,
      S => td_i,
      O => malformed_min_mux0000
    );
  msgcode_sigdef_mux000041 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => msgcode_i(3),
      I1 => msgcode_i(0),
      I2 => msgcode_i(6),
      I3 => msgcode_i(4),
      I4 => msgcode_i(5),
      I5 => msgcode_i(2),
      O => msgcode_sigdef_mux00004
    );
  msgcode_sigdef_mux00004_f7 : MUXF7
    port map (
      I0 => msgcode_sigdef_mux00004,
      I1 => N58,
      S => msgcode_i(7),
      O => N22
    );
  Msub_word_ct_sub0000_cy_3_11 : LUT5
    generic map(
      INIT => X"CCCCCCC8"
    )
    port map (
      I0 => length_i(1),
      I1 => fulltype_in(6),
      I2 => length_i(2),
      I3 => length_i(3),
      I4 => length_i(4),
      O => Msub_word_ct_sub0000_cy_3_1
    );
  Msub_word_ct_sub0000_cy_3_12 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => word_ct(2),
      I1 => word_ct(1),
      I2 => word_ct(0),
      I3 => word_ct(3),
      O => Msub_word_ct_sub0000_cy_3_11_24792
    );
  Msub_word_ct_sub0000_cy_3_1_f7 : MUXF7
    port map (
      I0 => Msub_word_ct_sub0000_cy_3_11_24792,
      I1 => Msub_word_ct_sub0000_cy_3_1,
      S => eval_formats_i,
      O => Msub_word_ct_sub0000_cy(3)
    );
  Msub_word_ct_sub0000_xor_5_11 : LUT6
    generic map(
      INIT => X"FE54DC7676767676"
    )
    port map (
      I0 => eval_formats_i,
      I1 => Msub_word_ct_sub0000_cy(3),
      I2 => word_ct(4),
      I3 => length_i(6),
      I4 => length_i(5),
      I5 => fulltype_in(6),
      O => Msub_word_ct_sub0000_xor_5_1
    );
  Msub_word_ct_sub0000_xor_5_12 : LUT6
    generic map(
      INIT => X"AB01892323232323"
    )
    port map (
      I0 => eval_formats_i,
      I1 => Msub_word_ct_sub0000_cy(3),
      I2 => word_ct(4),
      I3 => length_i(6),
      I4 => length_i(5),
      I5 => fulltype_in(6),
      O => Msub_word_ct_sub0000_xor_5_11_24798
    );
  Msub_word_ct_sub0000_xor_5_1_f7 : MUXF7
    port map (
      I0 => Msub_word_ct_sub0000_xor_5_11_24798,
      I1 => Msub_word_ct_sub0000_xor_5_1,
      S => word_ct(5),
      O => word_ct_sub0000(5)
    );
  Msub_word_ct_sub0000_xor_6_11 : LUT5
    generic map(
      INIT => X"AAA93333"
    )
    port map (
      I0 => length_i(7),
      I1 => Msub_word_ct_sub0000_cy(3),
      I2 => length_i(6),
      I3 => length_i(5),
      I4 => fulltype_in(6),
      O => Msub_word_ct_sub0000_xor_6_1
    );
  Msub_word_ct_sub0000_xor_6_12 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => word_ct(6),
      I1 => Msub_word_ct_sub0000_cy(3),
      I2 => word_ct(5),
      I3 => word_ct(4),
      O => Msub_word_ct_sub0000_xor_6_11_24800
    );
  Msub_word_ct_sub0000_xor_6_1_f7 : MUXF7
    port map (
      I0 => Msub_word_ct_sub0000_xor_6_11_24800,
      I1 => Msub_word_ct_sub0000_xor_6_1,
      S => eval_formats_i,
      O => word_ct_sub0000(6)
    );
  malformed_maxsize_and0000311 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF08"
    )
    port map (
      I0 => length_i(6),
      I1 => length_i(5),
      I2 => max_length(5),
      I3 => length_i(8),
      I4 => length_i(7),
      I5 => length_i(9),
      O => malformed_maxsize_and0000311_24888
    );
  malformed_maxsize_and0000312 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => length_i(6),
      I1 => max_length(5),
      I2 => length_i(8),
      I3 => length_i(7),
      I4 => length_i(9),
      O => malformed_maxsize_and0000312_24889
    );
  malformed_maxsize_and000031_f7 : MUXF7
    port map (
      I0 => malformed_maxsize_and0000312_24889,
      I1 => malformed_maxsize_and0000311_24888,
      S => max_length(6),
      O => malformed_maxsize_and000031
    );
  Msub_word_ct_sub0000_xor_3_11 : LUT5
    generic map(
      INIT => X"CCC9FFFF"
    )
    port map (
      I0 => length_i(3),
      I1 => length_i(4),
      I2 => length_i(1),
      I3 => length_i(2),
      I4 => fulltype_in(6),
      O => Msub_word_ct_sub0000_xor_3_1
    );
  Msub_word_ct_sub0000_xor_3_12 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => word_ct(3),
      I1 => word_ct(2),
      I2 => word_ct(1),
      I3 => word_ct(0),
      O => Msub_word_ct_sub0000_xor_3_11_24796
    );
  Msub_word_ct_sub0000_xor_3_1_f7 : MUXF7
    port map (
      I0 => Msub_word_ct_sub0000_xor_3_11_24796,
      I1 => Msub_word_ct_sub0000_xor_3_1,
      S => eval_formats_i,
      O => word_ct_sub0000(3)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity tlm_rx_data_snk is
  port (
    legacy_mode_i : in STD_LOGIC := 'X'; 
    reset_i : in STD_LOGIC := 'X'; 
    rem_i : in STD_LOGIC := 'X'; 
    locked_o : out STD_LOGIC; 
    rem_o : out STD_LOGIC; 
    td_ecrc_trim_i : in STD_LOGIC := 'X'; 
    check_rdev_o : out STD_LOGIC; 
    check_mem32_o : out STD_LOGIC; 
    stat_tlp_cpl_ep_o : out STD_LOGIC; 
    pm_turn_off_o : out STD_LOGIC; 
    pm_suspend_req_i : in STD_LOGIC := 'X'; 
    vend_msg_o : out STD_LOGIC; 
    ext_cfg_access_i : in STD_LOGIC := 'X'; 
    legacy_cfg_access_i : in STD_LOGIC := 'X'; 
    pm_set_slot_pwr_o : out STD_LOGIC; 
    cfg_o : out STD_LOGIC; 
    src_rdy_i : in STD_LOGIC := 'X'; 
    check_mem64_o : out STD_LOGIC; 
    check_rhit_i : in STD_LOGIC := 'X'; 
    src_rdy_o : out STD_LOGIC; 
    fc_unuse_o : out STD_LOGIC; 
    stat_tlp_cpl_abort_o : out STD_LOGIC; 
    cpl_o : out STD_LOGIC; 
    fc_use_np_o : out STD_LOGIC; 
    rid_o : out STD_LOGIC; 
    dsc_o : out STD_LOGIC; 
    eof_i : in STD_LOGIC := 'X'; 
    err_tlp_ur_lock_o : out STD_LOGIC; 
    eof_o : out STD_LOGIC; 
    hotplug_msg_enable_i : in STD_LOGIC := 'X'; 
    err_tlp_malformed_o : out STD_LOGIC; 
    rhit_bar_lat3_i : in STD_LOGIC := 'X'; 
    stat_tlp_ep_o : out STD_LOGIC; 
    check_rbus_o : out STD_LOGIC; 
    fc_use_cpl_o : out STD_LOGIC; 
    clk_i : in STD_LOGIC := 'X'; 
    np_o : out STD_LOGIC; 
    fc_use_p_o : out STD_LOGIC; 
    bar_src_rdy_o : out STD_LOGIC; 
    preeof_o : out STD_LOGIC; 
    vc_hit_o : out STD_LOGIC; 
    err_tlp_p_o : out STD_LOGIC; 
    check_rio_o : out STD_LOGIC; 
    sof_i : in STD_LOGIC := 'X'; 
    stat_tlp_cpl_ur_o : out STD_LOGIC; 
    sof_o : out STD_LOGIC; 
    err_tlp_ur_o : out STD_LOGIC; 
    src_dsc_i : in STD_LOGIC := 'X'; 
    check_rfun_o : out STD_LOGIC; 
    err_tlp_uc_o : out STD_LOGIC; 
    pm_as_nak_l1_o : out STD_LOGIC; 
    pm_set_slot_pwr_data_o : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    fc_use_data_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    check_raddr_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    bar_o : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    d_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    err_tlp_cpl_header_o : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
    check_rhit_bar_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    max_payload_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    d_i : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end tlm_rx_data_snk;

architecture STRUCTURE of tlm_rx_data_snk is
  component tlm_rx_data_snk_mal
    port (
      legacy_mode_i : in STD_LOGIC := 'X'; 
      reset_i : in STD_LOGIC := 'X'; 
      tlp_uc_o : out STD_LOGIC; 
      eval_formats_i : in STD_LOGIC := 'X'; 
      rem_i : in STD_LOGIC := 'X'; 
      td_i : in STD_LOGIC := 'X'; 
      tlp_ur_lock_o : out STD_LOGIC; 
      hit_src_rdy_i : in STD_LOGIC := 'X'; 
      hit_i : in STD_LOGIC := 'X'; 
      length_1dw_i : in STD_LOGIC := 'X'; 
      tlp_filt_o : out STD_LOGIC; 
      hit_lock_i : in STD_LOGIC := 'X'; 
      malformed_o : out STD_LOGIC; 
      ext_cfg_access_i : in STD_LOGIC := 'X'; 
      legacy_cfg_access_i : in STD_LOGIC := 'X'; 
      cfg_o : out STD_LOGIC; 
      hit_ack_i : in STD_LOGIC := 'X'; 
      tc0_i : in STD_LOGIC := 'X'; 
      load_aperture_i : in STD_LOGIC := 'X'; 
      eof_i : in STD_LOGIC := 'X'; 
      eval_fulltype_i : in STD_LOGIC := 'X'; 
      eval_msgcode_i : in STD_LOGIC := 'X'; 
      clk_i : in STD_LOGIC := 'X'; 
      hp_msg_detect_o : out STD_LOGIC; 
      sof_i : in STD_LOGIC := 'X'; 
      hit_lat3_i : in STD_LOGIC := 'X'; 
      pwr_mgmt_on_i : in STD_LOGIC := 'X'; 
      data_credits_vld_o : out STD_LOGIC; 
      tlp_ur_o : out STD_LOGIC; 
      data_credits_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
      max_payload_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      fulltype_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      offset_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      msgcode_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      length_i : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      aperture_i : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
    );
  end component;
  component tlm_rx_data_snk_pwr_mgmt
    port (
      reset_i : in STD_LOGIC := 'X'; 
      ismsg_i : in STD_LOGIC := 'X'; 
      eval_pwr_mgmt_i : in STD_LOGIC := 'X'; 
      pm_turn_off_o : out STD_LOGIC; 
      eval_pwr_mgmt_data_i : in STD_LOGIC := 'X'; 
      pm_set_slot_pwr_o : out STD_LOGIC; 
      clk_i : in STD_LOGIC := 'X'; 
      act_pwr_mgmt_i : in STD_LOGIC := 'X'; 
      pm_as_nak_l1_o : out STD_LOGIC; 
      pm_msg_detect_o : out STD_LOGIC; 
      pm_set_slot_pwr_data_o : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      msgcode_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pwr_data_i : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component tlm_rx_data_snk_bar
    port (
      legacy_mode_i : in STD_LOGIC := 'X'; 
      reset_i : in STD_LOGIC := 'X'; 
      check_rhit_src_rdy_o : out STD_LOGIC; 
      check_rfun_id_o : out STD_LOGIC; 
      check_rhit_lock_o : out STD_LOGIC; 
      check_rhit_ack_o : out STD_LOGIC; 
      check_rhit_i : in STD_LOGIC := 'X'; 
      check_rhit_o : out STD_LOGIC; 
      rhit_lat3_i : in STD_LOGIC := 'X'; 
      check_rmem32_o : out STD_LOGIC; 
      check_rdev_id_o : out STD_LOGIC; 
      clk_i : in STD_LOGIC := 'X'; 
      eval_check_i : in STD_LOGIC := 'X'; 
      check_rio_o : out STD_LOGIC; 
      check_rmem64_o : out STD_LOGIC; 
      check_rbus_id_o : out STD_LOGIC; 
      mem64_i : in STD_LOGIC := 'X'; 
      check_rhit_bar_o : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      check_raddr_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      addr_hi_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      check_rhit_bar_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      routing_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      req_id_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      addr_lo_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      req_id_cpl_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fulltype_oh_i : in STD_LOGIC_VECTOR ( 8 downto 0 ) 
    );
  end component;
  signal Madd_cur_bytes_missing_addsub0000_cy_1_11 : STD_LOGIC; 
  signal Madd_cur_bytes_missing_addsub0000_cy_1_111_25160 : STD_LOGIC; 
  signal Madd_cur_bytes_missing_index0000 : STD_LOGIC; 
  signal Mshreg_d_q5_0_25163 : STD_LOGIC; 
  signal Mshreg_d_q5_1_25164 : STD_LOGIC; 
  signal Mshreg_d_q5_10_25165 : STD_LOGIC; 
  signal Mshreg_d_q5_11_25166 : STD_LOGIC; 
  signal Mshreg_d_q5_12_25167 : STD_LOGIC; 
  signal Mshreg_d_q5_13_25168 : STD_LOGIC; 
  signal Mshreg_d_q5_14_25169 : STD_LOGIC; 
  signal Mshreg_d_q5_15_25170 : STD_LOGIC; 
  signal Mshreg_d_q5_16_25171 : STD_LOGIC; 
  signal Mshreg_d_q5_17_25172 : STD_LOGIC; 
  signal Mshreg_d_q5_18_25173 : STD_LOGIC; 
  signal Mshreg_d_q5_19_25174 : STD_LOGIC; 
  signal Mshreg_d_q5_2_25175 : STD_LOGIC; 
  signal Mshreg_d_q5_20_25176 : STD_LOGIC; 
  signal Mshreg_d_q5_21_25177 : STD_LOGIC; 
  signal Mshreg_d_q5_22_25178 : STD_LOGIC; 
  signal Mshreg_d_q5_23_25179 : STD_LOGIC; 
  signal Mshreg_d_q5_24_25180 : STD_LOGIC; 
  signal Mshreg_d_q5_25_25181 : STD_LOGIC; 
  signal Mshreg_d_q5_26_25182 : STD_LOGIC; 
  signal Mshreg_d_q5_27_25183 : STD_LOGIC; 
  signal Mshreg_d_q5_28_25184 : STD_LOGIC; 
  signal Mshreg_d_q5_29_25185 : STD_LOGIC; 
  signal Mshreg_d_q5_3_25186 : STD_LOGIC; 
  signal Mshreg_d_q5_30_25187 : STD_LOGIC; 
  signal Mshreg_d_q5_31_25188 : STD_LOGIC; 
  signal Mshreg_d_q5_32_25189 : STD_LOGIC; 
  signal Mshreg_d_q5_33_25190 : STD_LOGIC; 
  signal Mshreg_d_q5_34_25191 : STD_LOGIC; 
  signal Mshreg_d_q5_35_25192 : STD_LOGIC; 
  signal Mshreg_d_q5_36_25193 : STD_LOGIC; 
  signal Mshreg_d_q5_37_25194 : STD_LOGIC; 
  signal Mshreg_d_q5_38_25195 : STD_LOGIC; 
  signal Mshreg_d_q5_39_25196 : STD_LOGIC; 
  signal Mshreg_d_q5_4_25197 : STD_LOGIC; 
  signal Mshreg_d_q5_40_25198 : STD_LOGIC; 
  signal Mshreg_d_q5_41_25199 : STD_LOGIC; 
  signal Mshreg_d_q5_42_25200 : STD_LOGIC; 
  signal Mshreg_d_q5_43_25201 : STD_LOGIC; 
  signal Mshreg_d_q5_44_25202 : STD_LOGIC; 
  signal Mshreg_d_q5_45_25203 : STD_LOGIC; 
  signal Mshreg_d_q5_46_25204 : STD_LOGIC; 
  signal Mshreg_d_q5_47_25205 : STD_LOGIC; 
  signal Mshreg_d_q5_48_25206 : STD_LOGIC; 
  signal Mshreg_d_q5_49_25207 : STD_LOGIC; 
  signal Mshreg_d_q5_5_25208 : STD_LOGIC; 
  signal Mshreg_d_q5_50_25209 : STD_LOGIC; 
  signal Mshreg_d_q5_51_25210 : STD_LOGIC; 
  signal Mshreg_d_q5_52_25211 : STD_LOGIC; 
  signal Mshreg_d_q5_53_25212 : STD_LOGIC; 
  signal Mshreg_d_q5_54_25213 : STD_LOGIC; 
  signal Mshreg_d_q5_55_25214 : STD_LOGIC; 
  signal Mshreg_d_q5_56_25215 : STD_LOGIC; 
  signal Mshreg_d_q5_57_25216 : STD_LOGIC; 
  signal Mshreg_d_q5_58_25217 : STD_LOGIC; 
  signal Mshreg_d_q5_59_25218 : STD_LOGIC; 
  signal Mshreg_d_q5_6_25219 : STD_LOGIC; 
  signal Mshreg_d_q5_60_25220 : STD_LOGIC; 
  signal Mshreg_d_q5_61_25221 : STD_LOGIC; 
  signal Mshreg_d_q5_62_25222 : STD_LOGIC; 
  signal Mshreg_d_q5_63_25223 : STD_LOGIC; 
  signal Mshreg_d_q5_7_25224 : STD_LOGIC; 
  signal Mshreg_d_q5_8_25225 : STD_LOGIC; 
  signal Mshreg_d_q5_9_25226 : STD_LOGIC; 
  signal Mshreg_eof_nd_q_4_25227 : STD_LOGIC; 
  signal Mshreg_eof_q_3_25228 : STD_LOGIC; 
  signal Mshreg_rem_q_4_25229 : STD_LOGIC; 
  signal Mshreg_sof_q_5_25230 : STD_LOGIC; 
  signal Mshreg_src_rdy_q_4_25231 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal Q_COND_72 : STD_LOGIC; 
  signal Q_and0000 : STD_LOGIC; 
  signal Q_and0001 : STD_LOGIC; 
  signal bar_src_rdy_o_or0000 : STD_LOGIC; 
  signal cfg_o_mux0000 : STD_LOGIC; 
  signal cpl_o_mux0000 : STD_LOGIC; 
  signal cpl_o_not0001 : STD_LOGIC; 
  signal cur_byte_ct_or0000 : STD_LOGIC; 
  signal cur_cfg : STD_LOGIC; 
  signal cur_cpl_25404 : STD_LOGIC; 
  signal cur_cpl_abort_25405 : STD_LOGIC; 
  signal cur_cpl_abort_mux0000 : STD_LOGIC; 
  signal cur_cpl_ep_25407 : STD_LOGIC; 
  signal cur_cpl_ep_mux0000 : STD_LOGIC; 
  signal cur_cpl_ur_25441 : STD_LOGIC; 
  signal cur_cpl_ur_mux0000 : STD_LOGIC; 
  signal cur_drop_25443 : STD_LOGIC; 
  signal cur_ep_25444 : STD_LOGIC; 
  signal cur_ep_mux0000 : STD_LOGIC; 
  signal cur_ep_q_25446 : STD_LOGIC; 
  signal cur_fulltype_0_Q : STD_LOGIC; 
  signal cur_fulltype_1_Q : STD_LOGIC; 
  signal cur_fulltype_2_Q : STD_LOGIC; 
  signal cur_fulltype_3_Q : STD_LOGIC; 
  signal cur_fulltype_4_Q : STD_LOGIC; 
  signal cur_fulltype_6_Q : STD_LOGIC; 
  signal cur_fulltype_64_25455 : STD_LOGIC; 
  signal cur_fulltype_64_or0000 : STD_LOGIC; 
  signal cur_fulltype_mem_25457 : STD_LOGIC; 
  signal cur_fulltype_mem_or0000 : STD_LOGIC; 
  signal cur_fulltype_mux0000_0_Q : STD_LOGIC; 
  signal cur_fulltype_mux0000_1_Q : STD_LOGIC; 
  signal cur_fulltype_mux0000_2_Q : STD_LOGIC; 
  signal cur_fulltype_mux0000_3_Q : STD_LOGIC; 
  signal cur_fulltype_mux0000_4_Q : STD_LOGIC; 
  signal cur_fulltype_mux0000_6_Q : STD_LOGIC; 
  signal cur_fulltype_oh_0_Q : STD_LOGIC; 
  signal cur_fulltype_oh_1_Q : STD_LOGIC; 
  signal cur_fulltype_oh_3_Q : STD_LOGIC; 
  signal cur_fulltype_oh_4_Q : STD_LOGIC; 
  signal cur_fulltype_oh_5_Q : STD_LOGIC; 
  signal cur_fulltype_oh_7_Q : STD_LOGIC; 
  signal cur_fulltype_oh_8_Q : STD_LOGIC; 
  signal cur_fulltype_oh_or0001 : STD_LOGIC; 
  signal cur_fulltype_oh_or0002 : STD_LOGIC; 
  signal cur_fulltype_oh_or0003 : STD_LOGIC; 
  signal cur_fulltype_oh_or0005 : STD_LOGIC; 
  signal cur_fulltype_oh_or0006 : STD_LOGIC; 
  signal cur_hp_msg_detect : STD_LOGIC; 
  signal cur_length1_25479 : STD_LOGIC; 
  signal cur_length1_mux0000 : STD_LOGIC; 
  signal cur_length1_mux000018_25481 : STD_LOGIC; 
  signal cur_length1_mux000060_25482 : STD_LOGIC; 
  signal cur_locked_25503 : STD_LOGIC; 
  signal cur_locked_or0000 : STD_LOGIC; 
  signal cur_locked_or00001_25505 : STD_LOGIC; 
  signal cur_locked_or00002_25506 : STD_LOGIC; 
  signal cur_locked_q_25507 : STD_LOGIC; 
  signal cur_lower_addr_0_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_1_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_2_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_3_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_4_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_5_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_6_mux0000 : STD_LOGIC; 
  signal cur_lower_addr_6_not0001 : STD_LOGIC; 
  signal cur_np_25531 : STD_LOGIC; 
  signal cur_np_and0000 : STD_LOGIC; 
  signal cur_pm_msg_detect : STD_LOGIC; 
  signal cur_rem_25534 : STD_LOGIC; 
  signal cur_rem_not0001 : STD_LOGIC; 
  signal cur_tc0_25560 : STD_LOGIC; 
  signal cur_tc0_mux0000 : STD_LOGIC; 
  signal cur_td_25568 : STD_LOGIC; 
  signal cur_td_mux0000 : STD_LOGIC; 
  signal cur_td_q_25570 : STD_LOGIC; 
  signal cur_vend_msg_25571 : STD_LOGIC; 
  signal cur_vend_msg_and0000_25572 : STD_LOGIC; 
  signal dsc_o_mux0000 : STD_LOGIC; 
  signal dsc_o_mux00001_25897 : STD_LOGIC; 
  signal dsc_o_mux00002_25898 : STD_LOGIC; 
  signal eof_nd_q_1_Q : STD_LOGIC; 
  signal eof_nd_q_1_and0000 : STD_LOGIC; 
  signal eof_nd_q_4_Q : STD_LOGIC; 
  signal eof_nd_q_5_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_eof_o : STD_LOGIC; 
  signal eof_o_mux0000 : STD_LOGIC; 
  signal eof_q_1_Q : STD_LOGIC; 
  signal eof_q_3_Q : STD_LOGIC; 
  signal eof_q_4_Q : STD_LOGIC; 
  signal eof_q_5_Q : STD_LOGIC; 
  signal eof_q_6_Q : STD_LOGIC; 
  signal err_tlp_cpl_header_o_not0002 : STD_LOGIC; 
  signal err_tlp_malformed_o_and0000 : STD_LOGIC; 
  signal err_tlp_p_o_not0001 : STD_LOGIC; 
  signal err_tlp_ur_lock_o_and0000 : STD_LOGIC; 
  signal err_tlp_ur_o_and0000 : STD_LOGIC; 
  signal latch_1st_dword : STD_LOGIC; 
  signal latch_1st_dword_q1_26019 : STD_LOGIC; 
  signal latch_1st_dword_q2_26020 : STD_LOGIC; 
  signal latch_1st_dword_q3_26021 : STD_LOGIC; 
  signal latch_1st_dword_q4_26022 : STD_LOGIC; 
  signal latch_2nd_dword_q1_26023 : STD_LOGIC; 
  signal latch_2nd_dword_q2_26024 : STD_LOGIC; 
  signal latch_3rd_dword_q1_26025 : STD_LOGIC; 
  signal latch_4th_dword_q1_26026 : STD_LOGIC; 
  signal locked_o_mux0000 : STD_LOGIC; 
  signal malformed : STD_LOGIC; 
  signal next_cur_drop : STD_LOGIC; 
  signal NlwRenamedSig_OI_np_o : STD_LOGIC; 
  signal np_o_mux0000 : STD_LOGIC; 
  signal packet_ip_26047 : STD_LOGIC; 
  signal packet_ip_and0000 : STD_LOGIC; 
  signal rem_o_mux0000 : STD_LOGIC; 
  signal rem_q_1_Q : STD_LOGIC; 
  signal rem_q_1_or0000 : STD_LOGIC; 
  signal rem_q_1_xor0000 : STD_LOGIC; 
  signal rem_q_4_Q : STD_LOGIC; 
  signal rem_q_5_Q : STD_LOGIC; 
  signal rem_q_6_Q : STD_LOGIC; 
  signal remove_lastword_26071 : STD_LOGIC; 
  signal remove_lastword_mux0000 : STD_LOGIC; 
  signal remove_lastword_not0001 : STD_LOGIC; 
  signal rhit_ack : STD_LOGIC; 
  signal rhit_bar_d_0_Q : STD_LOGIC; 
  signal rhit_bar_d_1_Q : STD_LOGIC; 
  signal rhit_bar_d_6_Q : STD_LOGIC; 
  signal rhit_d : STD_LOGIC; 
  signal rhit_lock : STD_LOGIC; 
  signal rhit_src_rdy : STD_LOGIC; 
  signal sof_q_1_Q : STD_LOGIC; 
  signal sof_q_5_Q : STD_LOGIC; 
  signal sof_q_6_Q : STD_LOGIC; 
  signal src_rdy_o_mux0000_26092 : STD_LOGIC; 
  signal src_rdy_q_1_Q : STD_LOGIC; 
  signal src_rdy_q_1_and0000 : STD_LOGIC; 
  signal src_rdy_q_4_Q : STD_LOGIC; 
  signal src_rdy_q_5_Q : STD_LOGIC; 
  signal src_rdy_q_6_Q : STD_LOGIC; 
  signal stat_tlp_ep_o_or0000 : STD_LOGIC; 
  signal tlp_filt : STD_LOGIC; 
  signal tlp_uc : STD_LOGIC; 
  signal tlp_ur : STD_LOGIC; 
  signal tlp_ur_lock : STD_LOGIC; 
  signal vend_msg_o_mux0000 : STD_LOGIC; 
  signal NLW_bar_hit_check_rhit_bar_o_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_hit_check_rhit_bar_o_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_hit_check_rhit_bar_o_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_hit_check_rhit_bar_o_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_hit_fulltype_oh_i_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_hit_fulltype_oh_i_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pwr_mgmt_act_pwr_mgmt_i_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_vld_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_malformed_checks_data_credits_o_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_eof_nd_q_4_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_eof_q_3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_src_rdy_q_4_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_sof_q_5_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_1_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_4_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_7_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_5_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_6_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_8_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_9_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_10_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_11_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_12_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_13_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_16_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_14_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_15_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_17_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_18_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_19_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_20_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_21_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_22_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_23_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_24_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_25_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_26_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_27_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_28_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_29_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_30_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_33_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_31_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_32_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_34_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_35_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_36_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_37_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_38_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_39_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_40_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_41_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_42_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_43_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_44_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_45_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_46_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_47_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_50_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_48_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_49_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_51_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_52_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_53_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_54_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_55_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_56_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_57_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_58_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_59_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_60_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_61_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_62_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_d_q5_63_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_rem_q_4_Q15_UNCONNECTED : STD_LOGIC; 
  signal Madd_cur_bytes_missing_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Msub_cur_byte_ct_addsub0000_cy : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal Msub_cur_byte_ct_addsub0000_lut : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal NlwRenamedSig_OI_bar_o : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal byte_ct_1dw : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cur_attr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cur_attr_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cur_byte_ct : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal cur_byte_ct_1dw : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cur_byte_ct_addsub0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal cur_byte_ct_mux0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal cur_bytes_missing : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cur_bytes_missing_addsub0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal cur_cpl_header_fmt : STD_LOGIC_VECTOR ( 28 downto 0 ); 
  signal cur_cpl_stat : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cur_first_be_adj : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cur_fulltype_oh_mux0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal cur_length : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal cur_length_mux0000 : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal cur_lower_addr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal cur_msgcode : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cur_req_id : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cur_tag : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cur_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal cur_tc_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal d_mux : STD_LOGIC_VECTOR ( 47 downto 47 ); 
  signal d_o_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal d_q1 : STD_LOGIC_VECTOR ( 47 downto 47 ); 
  signal d_q5 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal d_q6 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal err_tlp_cpl_header_o_mux0000 : STD_LOGIC_VECTOR ( 47 downto 0 ); 
  signal first_be_missing : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal lower_addr32_in_q : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal lower_addr64_in_q : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal out_d1 : STD_LOGIC_VECTOR ( 2 downto 2 ); 
begin
  eof_o <= NlwRenamedSig_OI_eof_o;
  np_o <= NlwRenamedSig_OI_np_o;
  bar_o(5) <= NlwRenamedSig_OI_bar_o(2);
  bar_o(4) <= NlwRenamedSig_OI_bar_o(2);
  bar_o(3) <= NlwRenamedSig_OI_bar_o(2);
  bar_o(2) <= NlwRenamedSig_OI_bar_o(2);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_bar_o(2)
    );
  XST_VCC : VCC
    port map (
      P => out_d1(2)
    );
  err_tlp_malformed_o_13513 : FDR
    port map (
      C => clk_i,
      D => err_tlp_malformed_o_and0000,
      R => reset_i,
      Q => err_tlp_malformed_o
    );
  err_tlp_ur_o_13514 : FDR
    port map (
      C => clk_i,
      D => err_tlp_ur_o_and0000,
      R => reset_i,
      Q => err_tlp_ur_o
    );
  err_tlp_p_o_13515 : FDR
    port map (
      C => clk_i,
      D => err_tlp_p_o_not0001,
      R => reset_i,
      Q => err_tlp_p_o
    );
  err_tlp_ur_lock_o_13516 : FDR
    port map (
      C => clk_i,
      D => err_tlp_ur_lock_o_and0000,
      R => reset_i,
      Q => err_tlp_ur_lock_o
    );
  err_tlp_cpl_header_o_0 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(0),
      Q => err_tlp_cpl_header_o(0)
    );
  err_tlp_cpl_header_o_1 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(1),
      Q => err_tlp_cpl_header_o(1)
    );
  err_tlp_cpl_header_o_2 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(2),
      Q => err_tlp_cpl_header_o(2)
    );
  err_tlp_cpl_header_o_3 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(3),
      Q => err_tlp_cpl_header_o(3)
    );
  err_tlp_cpl_header_o_4 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(4),
      Q => err_tlp_cpl_header_o(4)
    );
  err_tlp_cpl_header_o_5 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(5),
      Q => err_tlp_cpl_header_o(5)
    );
  err_tlp_cpl_header_o_6 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(6),
      Q => err_tlp_cpl_header_o(6)
    );
  err_tlp_cpl_header_o_7 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(7),
      Q => err_tlp_cpl_header_o(7)
    );
  err_tlp_cpl_header_o_8 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(8),
      Q => err_tlp_cpl_header_o(8)
    );
  err_tlp_cpl_header_o_9 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(9),
      Q => err_tlp_cpl_header_o(9)
    );
  err_tlp_cpl_header_o_10 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(10),
      Q => err_tlp_cpl_header_o(10)
    );
  err_tlp_cpl_header_o_11 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(11),
      Q => err_tlp_cpl_header_o(11)
    );
  err_tlp_cpl_header_o_12 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(12),
      Q => err_tlp_cpl_header_o(12)
    );
  err_tlp_cpl_header_o_13 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(13),
      Q => err_tlp_cpl_header_o(13)
    );
  err_tlp_cpl_header_o_14 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(14),
      Q => err_tlp_cpl_header_o(14)
    );
  err_tlp_cpl_header_o_15 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(15),
      Q => err_tlp_cpl_header_o(15)
    );
  err_tlp_cpl_header_o_16 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(16),
      Q => err_tlp_cpl_header_o(16)
    );
  err_tlp_cpl_header_o_17 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(17),
      Q => err_tlp_cpl_header_o(17)
    );
  err_tlp_cpl_header_o_18 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(18),
      Q => err_tlp_cpl_header_o(18)
    );
  err_tlp_cpl_header_o_19 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(19),
      Q => err_tlp_cpl_header_o(19)
    );
  err_tlp_cpl_header_o_20 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(20),
      Q => err_tlp_cpl_header_o(20)
    );
  err_tlp_cpl_header_o_21 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(21),
      Q => err_tlp_cpl_header_o(21)
    );
  err_tlp_cpl_header_o_22 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(22),
      Q => err_tlp_cpl_header_o(22)
    );
  err_tlp_cpl_header_o_23 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(23),
      Q => err_tlp_cpl_header_o(23)
    );
  err_tlp_cpl_header_o_24 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(24),
      Q => err_tlp_cpl_header_o(24)
    );
  err_tlp_cpl_header_o_25 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(25),
      Q => err_tlp_cpl_header_o(25)
    );
  err_tlp_cpl_header_o_26 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(26),
      Q => err_tlp_cpl_header_o(26)
    );
  err_tlp_cpl_header_o_27 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(27),
      Q => err_tlp_cpl_header_o(27)
    );
  err_tlp_cpl_header_o_28 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(28),
      Q => err_tlp_cpl_header_o(28)
    );
  err_tlp_cpl_header_o_29 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(29),
      Q => err_tlp_cpl_header_o(29)
    );
  err_tlp_cpl_header_o_30 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(30),
      Q => err_tlp_cpl_header_o(30)
    );
  err_tlp_cpl_header_o_31 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(31),
      Q => err_tlp_cpl_header_o(31)
    );
  err_tlp_cpl_header_o_32 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(32),
      Q => err_tlp_cpl_header_o(32)
    );
  err_tlp_cpl_header_o_33 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(33),
      Q => err_tlp_cpl_header_o(33)
    );
  err_tlp_cpl_header_o_34 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(34),
      Q => err_tlp_cpl_header_o(34)
    );
  err_tlp_cpl_header_o_35 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(35),
      Q => err_tlp_cpl_header_o(35)
    );
  err_tlp_cpl_header_o_36 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(36),
      Q => err_tlp_cpl_header_o(36)
    );
  err_tlp_cpl_header_o_37 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(37),
      Q => err_tlp_cpl_header_o(37)
    );
  err_tlp_cpl_header_o_38 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(38),
      Q => err_tlp_cpl_header_o(38)
    );
  err_tlp_cpl_header_o_39 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(39),
      Q => err_tlp_cpl_header_o(39)
    );
  err_tlp_cpl_header_o_40 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(40),
      Q => err_tlp_cpl_header_o(40)
    );
  err_tlp_cpl_header_o_41 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(41),
      Q => err_tlp_cpl_header_o(41)
    );
  err_tlp_cpl_header_o_42 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(42),
      Q => err_tlp_cpl_header_o(42)
    );
  err_tlp_cpl_header_o_43 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(43),
      Q => err_tlp_cpl_header_o(43)
    );
  err_tlp_cpl_header_o_44 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(44),
      Q => err_tlp_cpl_header_o(44)
    );
  err_tlp_cpl_header_o_45 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(45),
      Q => err_tlp_cpl_header_o(45)
    );
  err_tlp_cpl_header_o_46 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(46),
      Q => err_tlp_cpl_header_o(46)
    );
  err_tlp_cpl_header_o_47 : FDE
    port map (
      C => clk_i,
      CE => err_tlp_cpl_header_o_not0002,
      D => err_tlp_cpl_header_o_mux0000(47),
      Q => err_tlp_cpl_header_o(47)
    );
  cur_drop : FDR
    port map (
      C => clk_i,
      D => next_cur_drop,
      R => reset_i,
      Q => cur_drop_25443
    );
  cur_byte_ct_1dw_0 : FDRE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => byte_ct_1dw(0),
      R => reset_i,
      Q => cur_byte_ct_1dw(0)
    );
  cur_byte_ct_1dw_1 : FDRE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => byte_ct_1dw(1),
      R => reset_i,
      Q => cur_byte_ct_1dw(1)
    );
  cur_byte_ct_1dw_2 : FDRE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => byte_ct_1dw(2),
      R => reset_i,
      Q => cur_byte_ct_1dw(2)
    );
  cur_first_be_adj_0 : FDRE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => first_be_missing(0),
      R => reset_i,
      Q => cur_first_be_adj(0)
    );
  cur_first_be_adj_1 : FDRE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => first_be_missing(1),
      R => reset_i,
      Q => cur_first_be_adj(1)
    );
  cur_lower_addr_6 : FDE
    port map (
      C => clk_i,
      CE => cur_lower_addr_6_not0001,
      D => cur_lower_addr_6_mux0000,
      Q => cur_lower_addr(6)
    );
  cur_lower_addr_5 : FDE
    port map (
      C => clk_i,
      CE => cur_lower_addr_6_not0001,
      D => cur_lower_addr_5_mux0000,
      Q => cur_lower_addr(5)
    );
  cur_lower_addr_4 : FDE
    port map (
      C => clk_i,
      CE => cur_lower_addr_6_not0001,
      D => cur_lower_addr_4_mux0000,
      Q => cur_lower_addr(4)
    );
  cur_lower_addr_3 : FDE
    port map (
      C => clk_i,
      CE => cur_lower_addr_6_not0001,
      D => cur_lower_addr_3_mux0000,
      Q => cur_lower_addr(3)
    );
  cur_lower_addr_2 : FDE
    port map (
      C => clk_i,
      CE => cur_lower_addr_6_not0001,
      D => cur_lower_addr_2_mux0000,
      Q => cur_lower_addr(2)
    );
  lower_addr64_in_q_2 : FD
    port map (
      C => clk_i,
      D => d_i(2),
      Q => lower_addr64_in_q(2)
    );
  lower_addr64_in_q_3 : FD
    port map (
      C => clk_i,
      D => d_i(3),
      Q => lower_addr64_in_q(3)
    );
  lower_addr64_in_q_4 : FD
    port map (
      C => clk_i,
      D => d_i(4),
      Q => lower_addr64_in_q(4)
    );
  lower_addr64_in_q_5 : FD
    port map (
      C => clk_i,
      D => d_i(5),
      Q => lower_addr64_in_q(5)
    );
  lower_addr64_in_q_6 : FD
    port map (
      C => clk_i,
      D => d_i(6),
      Q => lower_addr64_in_q(6)
    );
  lower_addr32_in_q_2 : FD
    port map (
      C => clk_i,
      D => d_i(34),
      Q => lower_addr32_in_q(2)
    );
  lower_addr32_in_q_3 : FD
    port map (
      C => clk_i,
      D => d_i(35),
      Q => lower_addr32_in_q(3)
    );
  lower_addr32_in_q_4 : FD
    port map (
      C => clk_i,
      D => d_i(36),
      Q => lower_addr32_in_q(4)
    );
  lower_addr32_in_q_5 : FD
    port map (
      C => clk_i,
      D => d_i(37),
      Q => lower_addr32_in_q(5)
    );
  lower_addr32_in_q_6 : FD
    port map (
      C => clk_i,
      D => d_i(38),
      Q => lower_addr32_in_q(6)
    );
  packet_ip : FDRE
    port map (
      C => clk_i,
      CE => src_rdy_i,
      D => packet_ip_and0000,
      R => reset_i,
      Q => packet_ip_26047
    );
  remove_lastword : FDRE
    port map (
      C => clk_i,
      CE => remove_lastword_not0001,
      D => remove_lastword_mux0000,
      R => reset_i,
      Q => remove_lastword_26071
    );
  sof_q_1 : FDR
    port map (
      C => clk_i,
      D => Q_and0000,
      R => reset_i,
      Q => sof_q_1_Q
    );
  eof_q_1 : FDR
    port map (
      C => clk_i,
      D => Q_and0001,
      R => reset_i,
      Q => eof_q_1_Q
    );
  src_rdy_q_1 : FDR
    port map (
      C => clk_i,
      D => src_rdy_q_1_and0000,
      R => reset_i,
      Q => src_rdy_q_1_Q
    );
  eof_nd_q_1 : FDR
    port map (
      C => clk_i,
      D => eof_nd_q_1_and0000,
      R => reset_i,
      Q => eof_nd_q_1_Q
    );
  sof_o_13592 : FDR
    port map (
      C => clk_i,
      D => Q_COND_72,
      R => reset_i,
      Q => sof_o
    );
  cur_rem : FDE
    port map (
      C => clk_i,
      CE => cur_rem_not0001,
      D => rem_i,
      Q => cur_rem_25534
    );
  rem_o_13594 : FDS
    port map (
      C => clk_i,
      D => rem_o_mux0000,
      S => reset_i,
      Q => rem_o
    );
  src_rdy_o_13595 : FDR
    port map (
      C => clk_i,
      D => src_rdy_o_mux0000_26092,
      R => reset_i,
      Q => src_rdy_o
    );
  dsc_o_13596 : FDR
    port map (
      C => clk_i,
      D => dsc_o_mux0000,
      R => reset_i,
      Q => dsc_o
    );
  eof_o_13597 : FDR
    port map (
      C => clk_i,
      D => eof_o_mux0000,
      R => reset_i,
      Q => NlwRenamedSig_OI_eof_o
    );
  d_q1_47 : FD
    port map (
      C => clk_i,
      D => d_mux(47),
      Q => d_q1(47)
    );
  d_o_0 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(0),
      Q => d_o(0)
    );
  d_o_1 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(1),
      Q => d_o(1)
    );
  d_o_2 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(2),
      Q => d_o(2)
    );
  d_o_3 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(3),
      Q => d_o(3)
    );
  d_o_4 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(4),
      Q => d_o(4)
    );
  d_o_5 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(5),
      Q => d_o(5)
    );
  d_o_6 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(6),
      Q => d_o(6)
    );
  d_o_7 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(7),
      Q => d_o(7)
    );
  d_o_8 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(8),
      Q => d_o(8)
    );
  d_o_9 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(9),
      Q => d_o(9)
    );
  d_o_10 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(10),
      Q => d_o(10)
    );
  d_o_11 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(11),
      Q => d_o(11)
    );
  d_o_12 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(12),
      Q => d_o(12)
    );
  d_o_13 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(13),
      Q => d_o(13)
    );
  d_o_14 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(14),
      Q => d_o(14)
    );
  d_o_15 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(15),
      Q => d_o(15)
    );
  d_o_16 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(16),
      Q => d_o(16)
    );
  d_o_17 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(17),
      Q => d_o(17)
    );
  d_o_18 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(18),
      Q => d_o(18)
    );
  d_o_19 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(19),
      Q => d_o(19)
    );
  d_o_20 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(20),
      Q => d_o(20)
    );
  d_o_21 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(21),
      Q => d_o(21)
    );
  d_o_22 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(22),
      Q => d_o(22)
    );
  d_o_23 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(23),
      Q => d_o(23)
    );
  d_o_24 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(24),
      Q => d_o(24)
    );
  d_o_25 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(25),
      Q => d_o(25)
    );
  d_o_26 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(26),
      Q => d_o(26)
    );
  d_o_27 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(27),
      Q => d_o(27)
    );
  d_o_28 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(28),
      Q => d_o(28)
    );
  d_o_29 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(29),
      Q => d_o(29)
    );
  d_o_30 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(30),
      Q => d_o(30)
    );
  d_o_31 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(31),
      Q => d_o(31)
    );
  d_o_32 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(32),
      Q => d_o(32)
    );
  d_o_33 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(33),
      Q => d_o(33)
    );
  d_o_34 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(34),
      Q => d_o(34)
    );
  d_o_35 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(35),
      Q => d_o(35)
    );
  d_o_36 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(36),
      Q => d_o(36)
    );
  d_o_37 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(37),
      Q => d_o(37)
    );
  d_o_38 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(38),
      Q => d_o(38)
    );
  d_o_39 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(39),
      Q => d_o(39)
    );
  d_o_40 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(40),
      Q => d_o(40)
    );
  d_o_41 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(41),
      Q => d_o(41)
    );
  d_o_42 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(42),
      Q => d_o(42)
    );
  d_o_43 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(43),
      Q => d_o(43)
    );
  d_o_44 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(44),
      Q => d_o(44)
    );
  d_o_45 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(45),
      Q => d_o(45)
    );
  d_o_46 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(46),
      Q => d_o(46)
    );
  d_o_47 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(47),
      Q => d_o(47)
    );
  d_o_48 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(48),
      Q => d_o(48)
    );
  d_o_49 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(49),
      Q => d_o(49)
    );
  d_o_50 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(50),
      Q => d_o(50)
    );
  d_o_51 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(51),
      Q => d_o(51)
    );
  d_o_52 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(52),
      Q => d_o(52)
    );
  d_o_53 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(53),
      Q => d_o(53)
    );
  d_o_54 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(54),
      Q => d_o(54)
    );
  d_o_55 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(55),
      Q => d_o(55)
    );
  d_o_56 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(56),
      Q => d_o(56)
    );
  d_o_57 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(57),
      Q => d_o(57)
    );
  d_o_58 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(58),
      Q => d_o(58)
    );
  d_o_59 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(59),
      Q => d_o(59)
    );
  d_o_60 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(60),
      Q => d_o(60)
    );
  d_o_61 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(61),
      Q => d_o(61)
    );
  d_o_62 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(62),
      Q => d_o(62)
    );
  d_o_63 : FD
    port map (
      C => clk_i,
      D => d_o_mux0000(63),
      Q => d_o(63)
    );
  cpl_o_13663 : FDE
    port map (
      C => clk_i,
      CE => cpl_o_not0001,
      D => cpl_o_mux0000,
      Q => cpl_o
    );
  locked_o_13664 : FDE
    port map (
      C => clk_i,
      CE => cpl_o_not0001,
      D => locked_o_mux0000,
      Q => locked_o
    );
  vend_msg_o_13665 : FDE
    port map (
      C => clk_i,
      CE => cpl_o_not0001,
      D => vend_msg_o_mux0000,
      Q => vend_msg_o
    );
  np_o_13666 : FDE
    port map (
      C => clk_i,
      CE => cpl_o_not0001,
      D => np_o_mux0000,
      Q => NlwRenamedSig_OI_np_o
    );
  cfg_o_13667 : FDE
    port map (
      C => clk_i,
      CE => cpl_o_not0001,
      D => cfg_o_mux0000,
      Q => cfg_o
    );
  bar_src_rdy_o_13668 : FDR
    port map (
      C => clk_i,
      D => out_d1(2),
      R => bar_src_rdy_o_or0000,
      Q => bar_src_rdy_o
    );
  latch_1st_dword_q1 : FDR
    port map (
      C => clk_i,
      D => latch_1st_dword,
      R => reset_i,
      Q => latch_1st_dword_q1_26019
    );
  latch_2nd_dword_q1 : FDR
    port map (
      C => clk_i,
      D => latch_1st_dword,
      R => reset_i,
      Q => latch_2nd_dword_q1_26023
    );
  cur_td : FD
    port map (
      C => clk_i,
      D => cur_td_mux0000,
      Q => cur_td_25568
    );
  cur_length_0 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(0),
      Q => cur_length(0)
    );
  cur_length_1 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(1),
      Q => cur_length(1)
    );
  cur_length_2 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(2),
      Q => cur_length(2)
    );
  cur_length_3 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(3),
      Q => cur_length(3)
    );
  cur_length_4 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(4),
      Q => cur_length(4)
    );
  cur_length_5 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(5),
      Q => cur_length(5)
    );
  cur_length_6 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(6),
      Q => cur_length(6)
    );
  cur_length_7 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(7),
      Q => cur_length(7)
    );
  cur_length_8 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(8),
      Q => cur_length(8)
    );
  cur_length_9 : FD
    port map (
      C => clk_i,
      D => cur_length_mux0000(9),
      Q => cur_length(9)
    );
  cur_tc_0 : FD
    port map (
      C => clk_i,
      D => cur_tc_mux0000(0),
      Q => cur_tc(0)
    );
  cur_tc_1 : FD
    port map (
      C => clk_i,
      D => cur_tc_mux0000(1),
      Q => cur_tc(1)
    );
  cur_tc_2 : FD
    port map (
      C => clk_i,
      D => cur_tc_mux0000(2),
      Q => cur_tc(2)
    );
  cur_tc0 : FD
    port map (
      C => clk_i,
      D => cur_tc0_mux0000,
      Q => cur_tc0_25560
    );
  cur_length1 : FD
    port map (
      C => clk_i,
      D => cur_length1_mux0000,
      Q => cur_length1_25479
    );
  cur_ep : FD
    port map (
      C => clk_i,
      D => cur_ep_mux0000,
      Q => cur_ep_25444
    );
  cur_attr_0 : FD
    port map (
      C => clk_i,
      D => cur_attr_mux0000(0),
      Q => cur_attr(0)
    );
  cur_attr_1 : FD
    port map (
      C => clk_i,
      D => cur_attr_mux0000(1),
      Q => cur_attr(1)
    );
  cur_fulltype_0 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_0_Q,
      Q => cur_fulltype_0_Q
    );
  cur_fulltype_1 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_1_Q,
      Q => cur_fulltype_1_Q
    );
  cur_fulltype_2 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_2_Q,
      Q => cur_fulltype_2_Q
    );
  cur_fulltype_3 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_3_Q,
      Q => cur_fulltype_3_Q
    );
  cur_fulltype_4 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_4_Q,
      Q => cur_fulltype_4_Q
    );
  cur_fulltype_6 : FD
    port map (
      C => clk_i,
      D => cur_fulltype_mux0000_6_Q,
      Q => cur_fulltype_6_Q
    );
  cur_fulltype_mem : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_mem_or0000,
      Q => cur_fulltype_mem_25457
    );
  cur_fulltype_64 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_64_or0000,
      Q => cur_fulltype_64_25455
    );
  cur_fulltype_oh_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_or0006,
      Q => cur_fulltype_oh_0_Q
    );
  cur_fulltype_oh_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_or0005,
      Q => cur_fulltype_oh_1_Q
    );
  cur_fulltype_oh_3 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_or0003,
      Q => cur_fulltype_oh_3_Q
    );
  cur_fulltype_oh_4 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_or0002,
      Q => cur_fulltype_oh_4_Q
    );
  cur_fulltype_oh_5 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_or0001,
      Q => cur_fulltype_oh_5_Q
    );
  cur_fulltype_oh_7 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_oh_mux0000(1),
      Q => cur_fulltype_oh_7_Q
    );
  cur_fulltype_oh_8 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_fulltype_mem_or0000,
      Q => cur_fulltype_oh_8_Q
    );
  cur_locked : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_locked_or0000,
      Q => cur_locked_25503
    );
  cur_req_id_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(16),
      Q => cur_req_id(0)
    );
  cur_req_id_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(17),
      Q => cur_req_id(1)
    );
  cur_req_id_2 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(18),
      Q => cur_req_id(2)
    );
  cur_req_id_3 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(19),
      Q => cur_req_id(3)
    );
  cur_req_id_4 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(20),
      Q => cur_req_id(4)
    );
  cur_req_id_5 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(21),
      Q => cur_req_id(5)
    );
  cur_req_id_6 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(22),
      Q => cur_req_id(6)
    );
  cur_req_id_7 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(23),
      Q => cur_req_id(7)
    );
  cur_req_id_8 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(24),
      Q => cur_req_id(8)
    );
  cur_req_id_9 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(25),
      Q => cur_req_id(9)
    );
  cur_req_id_10 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(26),
      Q => cur_req_id(10)
    );
  cur_req_id_11 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(27),
      Q => cur_req_id(11)
    );
  cur_req_id_12 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(28),
      Q => cur_req_id(12)
    );
  cur_req_id_13 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(29),
      Q => cur_req_id(13)
    );
  cur_req_id_14 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(30),
      Q => cur_req_id(14)
    );
  cur_req_id_15 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(31),
      Q => cur_req_id(15)
    );
  cur_tag_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(8),
      Q => cur_tag(0)
    );
  cur_tag_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(9),
      Q => cur_tag(1)
    );
  cur_tag_2 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(10),
      Q => cur_tag(2)
    );
  cur_tag_3 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(11),
      Q => cur_tag(3)
    );
  cur_tag_4 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(12),
      Q => cur_tag(4)
    );
  cur_tag_5 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(13),
      Q => cur_tag(5)
    );
  cur_tag_6 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(14),
      Q => cur_tag(6)
    );
  cur_tag_7 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(15),
      Q => cur_tag(7)
    );
  cur_msgcode_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(0),
      Q => cur_msgcode(0)
    );
  cur_msgcode_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(1),
      Q => cur_msgcode(1)
    );
  cur_msgcode_2 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(2),
      Q => cur_msgcode(2)
    );
  cur_msgcode_3 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(3),
      Q => cur_msgcode(3)
    );
  cur_msgcode_4 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(4),
      Q => cur_msgcode(4)
    );
  cur_msgcode_5 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(5),
      Q => cur_msgcode(5)
    );
  cur_msgcode_6 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(6),
      Q => cur_msgcode(6)
    );
  cur_msgcode_7 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(7),
      Q => cur_msgcode(7)
    );
  cur_cpl_stat_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(13),
      Q => cur_cpl_stat(0)
    );
  cur_cpl_stat_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(14),
      Q => cur_cpl_stat(1)
    );
  cur_cpl_stat_2 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => d_i(15),
      Q => cur_cpl_stat(2)
    );
  cur_bytes_missing_0 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => Madd_cur_bytes_missing_addsub0000_lut(0),
      Q => cur_bytes_missing(0)
    );
  cur_bytes_missing_1 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => cur_bytes_missing_addsub0000(1),
      Q => cur_bytes_missing(1)
    );
  cur_bytes_missing_2 : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword,
      D => Madd_cur_bytes_missing_index0000,
      Q => cur_bytes_missing(2)
    );
  latch_1st_dword_q2 : FDR
    port map (
      C => clk_i,
      D => latch_1st_dword_q1_26019,
      R => reset_i,
      Q => latch_1st_dword_q2_26020
    );
  latch_2nd_dword_q2 : FDR
    port map (
      C => clk_i,
      D => latch_2nd_dword_q1_26023,
      R => reset_i,
      Q => latch_2nd_dword_q2_26024
    );
  latch_3rd_dword_q1 : FDR
    port map (
      C => clk_i,
      D => sof_q_1_Q,
      R => reset_i,
      Q => latch_3rd_dword_q1_26025
    );
  latch_4th_dword_q1 : FDR
    port map (
      C => clk_i,
      D => sof_q_1_Q,
      R => reset_i,
      Q => latch_4th_dword_q1_26026
    );
  cur_cpl_ep : FDRE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_cpl_ep_mux0000,
      R => reset_i,
      Q => cur_cpl_ep_25407
    );
  cur_cpl_abort : FDRE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_cpl_abort_mux0000,
      R => reset_i,
      Q => cur_cpl_abort_25405
    );
  cur_cpl_ur : FDRE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_cpl_ur_mux0000,
      R => reset_i,
      Q => cur_cpl_ur_25441
    );
  cur_cpl_header_fmt_0 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(0),
      Q => cur_cpl_header_fmt(0)
    );
  cur_cpl_header_fmt_1 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(1),
      Q => cur_cpl_header_fmt(1)
    );
  cur_cpl_header_fmt_2 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(2),
      Q => cur_cpl_header_fmt(2)
    );
  cur_cpl_header_fmt_3 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(3),
      Q => cur_cpl_header_fmt(3)
    );
  cur_cpl_header_fmt_4 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(4),
      Q => cur_cpl_header_fmt(4)
    );
  cur_cpl_header_fmt_5 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(5),
      Q => cur_cpl_header_fmt(5)
    );
  cur_cpl_header_fmt_6 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(6),
      Q => cur_cpl_header_fmt(6)
    );
  cur_cpl_header_fmt_7 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tag(7),
      Q => cur_cpl_header_fmt(7)
    );
  cur_cpl_header_fmt_8 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(0),
      Q => cur_cpl_header_fmt(8)
    );
  cur_cpl_header_fmt_9 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(1),
      Q => cur_cpl_header_fmt(9)
    );
  cur_cpl_header_fmt_10 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(2),
      Q => cur_cpl_header_fmt(10)
    );
  cur_cpl_header_fmt_11 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(3),
      Q => cur_cpl_header_fmt(11)
    );
  cur_cpl_header_fmt_12 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(4),
      Q => cur_cpl_header_fmt(12)
    );
  cur_cpl_header_fmt_13 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(5),
      Q => cur_cpl_header_fmt(13)
    );
  cur_cpl_header_fmt_14 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(6),
      Q => cur_cpl_header_fmt(14)
    );
  cur_cpl_header_fmt_15 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(7),
      Q => cur_cpl_header_fmt(15)
    );
  cur_cpl_header_fmt_16 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(8),
      Q => cur_cpl_header_fmt(16)
    );
  cur_cpl_header_fmt_17 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(9),
      Q => cur_cpl_header_fmt(17)
    );
  cur_cpl_header_fmt_18 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(10),
      Q => cur_cpl_header_fmt(18)
    );
  cur_cpl_header_fmt_19 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(11),
      Q => cur_cpl_header_fmt(19)
    );
  cur_cpl_header_fmt_20 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(12),
      Q => cur_cpl_header_fmt(20)
    );
  cur_cpl_header_fmt_21 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(13),
      Q => cur_cpl_header_fmt(21)
    );
  cur_cpl_header_fmt_22 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(14),
      Q => cur_cpl_header_fmt(22)
    );
  cur_cpl_header_fmt_23 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_req_id(15),
      Q => cur_cpl_header_fmt(23)
    );
  cur_cpl_header_fmt_24 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_attr(0),
      Q => cur_cpl_header_fmt(24)
    );
  cur_cpl_header_fmt_25 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_attr(1),
      Q => cur_cpl_header_fmt(25)
    );
  cur_cpl_header_fmt_26 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tc(0),
      Q => cur_cpl_header_fmt(26)
    );
  cur_cpl_header_fmt_27 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tc(1),
      Q => cur_cpl_header_fmt(27)
    );
  cur_cpl_header_fmt_28 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_tc(2),
      Q => cur_cpl_header_fmt(28)
    );
  cur_byte_ct_0 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(0),
      Q => cur_byte_ct(0)
    );
  cur_byte_ct_1 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(1),
      Q => cur_byte_ct(1)
    );
  cur_byte_ct_2 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(2),
      Q => cur_byte_ct(2)
    );
  cur_byte_ct_3 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(3),
      Q => cur_byte_ct(3)
    );
  cur_byte_ct_4 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(4),
      Q => cur_byte_ct(4)
    );
  cur_byte_ct_5 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(5),
      Q => cur_byte_ct(5)
    );
  cur_byte_ct_6 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(6),
      Q => cur_byte_ct(6)
    );
  cur_byte_ct_7 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(7),
      Q => cur_byte_ct(7)
    );
  cur_byte_ct_8 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(8),
      Q => cur_byte_ct(8)
    );
  cur_byte_ct_9 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(9),
      Q => cur_byte_ct(9)
    );
  cur_byte_ct_10 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(10),
      Q => cur_byte_ct(10)
    );
  cur_byte_ct_11 : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_byte_ct_mux0000(11),
      Q => cur_byte_ct(11)
    );
  cur_lower_addr_1 : FDE
    port map (
      C => clk_i,
      CE => latch_3rd_dword_q1_26025,
      D => cur_lower_addr_1_mux0000,
      Q => cur_lower_addr(1)
    );
  cur_lower_addr_0 : FDE
    port map (
      C => clk_i,
      CE => latch_3rd_dword_q1_26025,
      D => cur_lower_addr_0_mux0000,
      Q => cur_lower_addr(0)
    );
  rem_q_1 : FDS
    port map (
      C => clk_i,
      D => rem_q_1_xor0000,
      S => rem_q_1_or0000,
      Q => rem_q_1_Q
    );
  cur_ep_q : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword_q2_26020,
      D => cur_ep_25444,
      Q => cur_ep_q_25446
    );
  cur_cpl : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword_q2_26020,
      D => cur_fulltype_oh_0_Q,
      Q => cur_cpl_25404
    );
  cur_locked_q : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword_q2_26020,
      D => cur_locked_25503,
      Q => cur_locked_q_25507
    );
  cur_np : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword_q2_26020,
      D => cur_np_and0000,
      Q => cur_np_25531
    );
  bar_o_0 : FDE
    port map (
      C => clk_i,
      CE => rhit_src_rdy,
      D => rhit_bar_d_0_Q,
      Q => bar_o(0)
    );
  bar_o_1 : FDE
    port map (
      C => clk_i,
      CE => rhit_src_rdy,
      D => rhit_bar_d_1_Q,
      Q => bar_o(1)
    );
  bar_o_6 : FDE
    port map (
      C => clk_i,
      CE => rhit_src_rdy,
      D => rhit_bar_d_6_Q,
      Q => bar_o(6)
    );
  cur_td_q : FDE
    port map (
      C => clk_i,
      CE => latch_1st_dword_q2_26020,
      D => cur_td_25568,
      Q => cur_td_q_25570
    );
  cur_vend_msg : FDE
    port map (
      C => clk_i,
      CE => latch_2nd_dword_q2_26024,
      D => cur_vend_msg_and0000_25572,
      Q => cur_vend_msg_25571
    );
  rid_o_13804 : FDE
    port map (
      C => clk_i,
      CE => rhit_src_rdy,
      D => rhit_d,
      Q => rid_o
    );
  latch_1st_dword_q3 : FDR
    port map (
      C => clk_i,
      D => latch_1st_dword_q2_26020,
      R => reset_i,
      Q => latch_1st_dword_q3_26021
    );
  stat_tlp_cpl_abort_o_13806 : FDR
    port map (
      C => clk_i,
      D => cur_cpl_abort_25405,
      R => stat_tlp_ep_o_or0000,
      Q => stat_tlp_cpl_abort_o
    );
  stat_tlp_ep_o_13807 : FDR
    port map (
      C => clk_i,
      D => cur_ep_q_25446,
      R => stat_tlp_ep_o_or0000,
      Q => stat_tlp_ep_o
    );
  stat_tlp_cpl_ep_o_13808 : FDR
    port map (
      C => clk_i,
      D => cur_cpl_ep_25407,
      R => stat_tlp_ep_o_or0000,
      Q => stat_tlp_cpl_ep_o
    );
  stat_tlp_cpl_ur_o_13809 : FDR
    port map (
      C => clk_i,
      D => cur_cpl_ur_25441,
      R => stat_tlp_ep_o_or0000,
      Q => stat_tlp_cpl_ur_o
    );
  eof_q_4 : FD
    port map (
      C => clk_i,
      D => eof_q_3_Q,
      Q => eof_q_4_Q
    );
  latch_1st_dword_q4 : FDR
    port map (
      C => clk_i,
      D => latch_1st_dword_q3_26021,
      R => reset_i,
      Q => latch_1st_dword_q4_26022
    );
  eof_q_5 : FD
    port map (
      C => clk_i,
      D => eof_q_4_Q,
      Q => eof_q_5_Q
    );
  src_rdy_q_5 : FD
    port map (
      C => clk_i,
      D => src_rdy_q_4_Q,
      Q => src_rdy_q_5_Q
    );
  eof_nd_q_5 : FD
    port map (
      C => clk_i,
      D => eof_nd_q_4_Q,
      Q => eof_nd_q_5_Q
    );
  sof_q_6 : FD
    port map (
      C => clk_i,
      D => sof_q_5_Q,
      Q => sof_q_6_Q
    );
  eof_q_6 : FD
    port map (
      C => clk_i,
      D => eof_q_5_Q,
      Q => eof_q_6_Q
    );
  src_rdy_q_6 : FD
    port map (
      C => clk_i,
      D => src_rdy_q_5_Q,
      Q => src_rdy_q_6_Q
    );
  d_q6_0 : FD
    port map (
      C => clk_i,
      D => d_q5(0),
      Q => d_q6(0)
    );
  d_q6_1 : FD
    port map (
      C => clk_i,
      D => d_q5(1),
      Q => d_q6(1)
    );
  d_q6_2 : FD
    port map (
      C => clk_i,
      D => d_q5(2),
      Q => d_q6(2)
    );
  d_q6_3 : FD
    port map (
      C => clk_i,
      D => d_q5(3),
      Q => d_q6(3)
    );
  d_q6_4 : FD
    port map (
      C => clk_i,
      D => d_q5(4),
      Q => d_q6(4)
    );
  d_q6_5 : FD
    port map (
      C => clk_i,
      D => d_q5(5),
      Q => d_q6(5)
    );
  d_q6_6 : FD
    port map (
      C => clk_i,
      D => d_q5(6),
      Q => d_q6(6)
    );
  d_q6_7 : FD
    port map (
      C => clk_i,
      D => d_q5(7),
      Q => d_q6(7)
    );
  d_q6_8 : FD
    port map (
      C => clk_i,
      D => d_q5(8),
      Q => d_q6(8)
    );
  d_q6_9 : FD
    port map (
      C => clk_i,
      D => d_q5(9),
      Q => d_q6(9)
    );
  d_q6_10 : FD
    port map (
      C => clk_i,
      D => d_q5(10),
      Q => d_q6(10)
    );
  d_q6_11 : FD
    port map (
      C => clk_i,
      D => d_q5(11),
      Q => d_q6(11)
    );
  d_q6_12 : FD
    port map (
      C => clk_i,
      D => d_q5(12),
      Q => d_q6(12)
    );
  d_q6_13 : FD
    port map (
      C => clk_i,
      D => d_q5(13),
      Q => d_q6(13)
    );
  d_q6_14 : FD
    port map (
      C => clk_i,
      D => d_q5(14),
      Q => d_q6(14)
    );
  d_q6_15 : FD
    port map (
      C => clk_i,
      D => d_q5(15),
      Q => d_q6(15)
    );
  d_q6_16 : FD
    port map (
      C => clk_i,
      D => d_q5(16),
      Q => d_q6(16)
    );
  d_q6_17 : FD
    port map (
      C => clk_i,
      D => d_q5(17),
      Q => d_q6(17)
    );
  d_q6_18 : FD
    port map (
      C => clk_i,
      D => d_q5(18),
      Q => d_q6(18)
    );
  d_q6_19 : FD
    port map (
      C => clk_i,
      D => d_q5(19),
      Q => d_q6(19)
    );
  d_q6_20 : FD
    port map (
      C => clk_i,
      D => d_q5(20),
      Q => d_q6(20)
    );
  d_q6_21 : FD
    port map (
      C => clk_i,
      D => d_q5(21),
      Q => d_q6(21)
    );
  d_q6_22 : FD
    port map (
      C => clk_i,
      D => d_q5(22),
      Q => d_q6(22)
    );
  d_q6_23 : FD
    port map (
      C => clk_i,
      D => d_q5(23),
      Q => d_q6(23)
    );
  d_q6_24 : FD
    port map (
      C => clk_i,
      D => d_q5(24),
      Q => d_q6(24)
    );
  d_q6_25 : FD
    port map (
      C => clk_i,
      D => d_q5(25),
      Q => d_q6(25)
    );
  d_q6_26 : FD
    port map (
      C => clk_i,
      D => d_q5(26),
      Q => d_q6(26)
    );
  d_q6_27 : FD
    port map (
      C => clk_i,
      D => d_q5(27),
      Q => d_q6(27)
    );
  d_q6_28 : FD
    port map (
      C => clk_i,
      D => d_q5(28),
      Q => d_q6(28)
    );
  d_q6_29 : FD
    port map (
      C => clk_i,
      D => d_q5(29),
      Q => d_q6(29)
    );
  d_q6_30 : FD
    port map (
      C => clk_i,
      D => d_q5(30),
      Q => d_q6(30)
    );
  d_q6_31 : FD
    port map (
      C => clk_i,
      D => d_q5(31),
      Q => d_q6(31)
    );
  d_q6_32 : FD
    port map (
      C => clk_i,
      D => d_q5(32),
      Q => d_q6(32)
    );
  d_q6_33 : FD
    port map (
      C => clk_i,
      D => d_q5(33),
      Q => d_q6(33)
    );
  d_q6_34 : FD
    port map (
      C => clk_i,
      D => d_q5(34),
      Q => d_q6(34)
    );
  d_q6_35 : FD
    port map (
      C => clk_i,
      D => d_q5(35),
      Q => d_q6(35)
    );
  d_q6_36 : FD
    port map (
      C => clk_i,
      D => d_q5(36),
      Q => d_q6(36)
    );
  d_q6_37 : FD
    port map (
      C => clk_i,
      D => d_q5(37),
      Q => d_q6(37)
    );
  d_q6_38 : FD
    port map (
      C => clk_i,
      D => d_q5(38),
      Q => d_q6(38)
    );
  d_q6_39 : FD
    port map (
      C => clk_i,
      D => d_q5(39),
      Q => d_q6(39)
    );
  d_q6_40 : FD
    port map (
      C => clk_i,
      D => d_q5(40),
      Q => d_q6(40)
    );
  d_q6_41 : FD
    port map (
      C => clk_i,
      D => d_q5(41),
      Q => d_q6(41)
    );
  d_q6_42 : FD
    port map (
      C => clk_i,
      D => d_q5(42),
      Q => d_q6(42)
    );
  d_q6_43 : FD
    port map (
      C => clk_i,
      D => d_q5(43),
      Q => d_q6(43)
    );
  d_q6_44 : FD
    port map (
      C => clk_i,
      D => d_q5(44),
      Q => d_q6(44)
    );
  d_q6_45 : FD
    port map (
      C => clk_i,
      D => d_q5(45),
      Q => d_q6(45)
    );
  d_q6_46 : FD
    port map (
      C => clk_i,
      D => d_q5(46),
      Q => d_q6(46)
    );
  d_q6_47 : FD
    port map (
      C => clk_i,
      D => d_q5(47),
      Q => d_q6(47)
    );
  d_q6_48 : FD
    port map (
      C => clk_i,
      D => d_q5(48),
      Q => d_q6(48)
    );
  d_q6_49 : FD
    port map (
      C => clk_i,
      D => d_q5(49),
      Q => d_q6(49)
    );
  d_q6_50 : FD
    port map (
      C => clk_i,
      D => d_q5(50),
      Q => d_q6(50)
    );
  d_q6_51 : FD
    port map (
      C => clk_i,
      D => d_q5(51),
      Q => d_q6(51)
    );
  d_q6_52 : FD
    port map (
      C => clk_i,
      D => d_q5(52),
      Q => d_q6(52)
    );
  d_q6_53 : FD
    port map (
      C => clk_i,
      D => d_q5(53),
      Q => d_q6(53)
    );
  d_q6_54 : FD
    port map (
      C => clk_i,
      D => d_q5(54),
      Q => d_q6(54)
    );
  d_q6_55 : FD
    port map (
      C => clk_i,
      D => d_q5(55),
      Q => d_q6(55)
    );
  d_q6_56 : FD
    port map (
      C => clk_i,
      D => d_q5(56),
      Q => d_q6(56)
    );
  d_q6_57 : FD
    port map (
      C => clk_i,
      D => d_q5(57),
      Q => d_q6(57)
    );
  d_q6_58 : FD
    port map (
      C => clk_i,
      D => d_q5(58),
      Q => d_q6(58)
    );
  d_q6_59 : FD
    port map (
      C => clk_i,
      D => d_q5(59),
      Q => d_q6(59)
    );
  d_q6_60 : FD
    port map (
      C => clk_i,
      D => d_q5(60),
      Q => d_q6(60)
    );
  d_q6_61 : FD
    port map (
      C => clk_i,
      D => d_q5(61),
      Q => d_q6(61)
    );
  d_q6_62 : FD
    port map (
      C => clk_i,
      D => d_q5(62),
      Q => d_q6(62)
    );
  d_q6_63 : FD
    port map (
      C => clk_i,
      D => d_q5(63),
      Q => d_q6(63)
    );
  rem_q_5 : FD
    port map (
      C => clk_i,
      D => rem_q_4_Q,
      Q => rem_q_5_Q
    );
  rem_q_6 : FD
    port map (
      C => clk_i,
      D => rem_q_5_Q,
      Q => rem_q_6_Q
    );
  Msub_cur_byte_ct_addsub0000_cy_0_Q : MUXCY
    port map (
      CI => out_d1(2),
      DI => NlwRenamedSig_OI_bar_o(2),
      S => Msub_cur_byte_ct_addsub0000_lut(0),
      O => Msub_cur_byte_ct_addsub0000_cy(0)
    );
  Msub_cur_byte_ct_addsub0000_xor_0_Q : XORCY
    port map (
      CI => out_d1(2),
      LI => Msub_cur_byte_ct_addsub0000_lut(0),
      O => cur_byte_ct_addsub0000(0)
    );
  Msub_cur_byte_ct_addsub0000_cy_1_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(0),
      DI => NlwRenamedSig_OI_bar_o(2),
      S => Msub_cur_byte_ct_addsub0000_lut(1),
      O => Msub_cur_byte_ct_addsub0000_cy(1)
    );
  Msub_cur_byte_ct_addsub0000_xor_1_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(0),
      LI => Msub_cur_byte_ct_addsub0000_lut(1),
      O => cur_byte_ct_addsub0000(1)
    );
  Msub_cur_byte_ct_addsub0000_lut_2_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cur_length(0),
      I1 => cur_bytes_missing(2),
      O => Msub_cur_byte_ct_addsub0000_lut(2)
    );
  Msub_cur_byte_ct_addsub0000_cy_2_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(1),
      DI => cur_length(0),
      S => Msub_cur_byte_ct_addsub0000_lut(2),
      O => Msub_cur_byte_ct_addsub0000_cy(2)
    );
  Msub_cur_byte_ct_addsub0000_xor_2_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(1),
      LI => Msub_cur_byte_ct_addsub0000_lut(2),
      O => cur_byte_ct_addsub0000(2)
    );
  Msub_cur_byte_ct_addsub0000_cy_3_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(2),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(3),
      O => Msub_cur_byte_ct_addsub0000_cy(3)
    );
  Msub_cur_byte_ct_addsub0000_xor_3_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(2),
      LI => Msub_cur_byte_ct_addsub0000_lut(3),
      O => cur_byte_ct_addsub0000(3)
    );
  Msub_cur_byte_ct_addsub0000_cy_4_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(3),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(4),
      O => Msub_cur_byte_ct_addsub0000_cy(4)
    );
  Msub_cur_byte_ct_addsub0000_xor_4_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(3),
      LI => Msub_cur_byte_ct_addsub0000_lut(4),
      O => cur_byte_ct_addsub0000(4)
    );
  Msub_cur_byte_ct_addsub0000_cy_5_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(4),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(5),
      O => Msub_cur_byte_ct_addsub0000_cy(5)
    );
  Msub_cur_byte_ct_addsub0000_xor_5_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(4),
      LI => Msub_cur_byte_ct_addsub0000_lut(5),
      O => cur_byte_ct_addsub0000(5)
    );
  Msub_cur_byte_ct_addsub0000_cy_6_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(5),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(6),
      O => Msub_cur_byte_ct_addsub0000_cy(6)
    );
  Msub_cur_byte_ct_addsub0000_xor_6_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(5),
      LI => Msub_cur_byte_ct_addsub0000_lut(6),
      O => cur_byte_ct_addsub0000(6)
    );
  Msub_cur_byte_ct_addsub0000_cy_7_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(6),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(7),
      O => Msub_cur_byte_ct_addsub0000_cy(7)
    );
  Msub_cur_byte_ct_addsub0000_xor_7_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(6),
      LI => Msub_cur_byte_ct_addsub0000_lut(7),
      O => cur_byte_ct_addsub0000(7)
    );
  Msub_cur_byte_ct_addsub0000_cy_8_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(7),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(8),
      O => Msub_cur_byte_ct_addsub0000_cy(8)
    );
  Msub_cur_byte_ct_addsub0000_xor_8_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(7),
      LI => Msub_cur_byte_ct_addsub0000_lut(8),
      O => cur_byte_ct_addsub0000(8)
    );
  Msub_cur_byte_ct_addsub0000_cy_9_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(8),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(9),
      O => Msub_cur_byte_ct_addsub0000_cy(9)
    );
  Msub_cur_byte_ct_addsub0000_xor_9_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(8),
      LI => Msub_cur_byte_ct_addsub0000_lut(9),
      O => cur_byte_ct_addsub0000(9)
    );
  Msub_cur_byte_ct_addsub0000_cy_10_Q : MUXCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(9),
      DI => out_d1(2),
      S => Msub_cur_byte_ct_addsub0000_lut(10),
      O => Msub_cur_byte_ct_addsub0000_cy(10)
    );
  Msub_cur_byte_ct_addsub0000_xor_10_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(9),
      LI => Msub_cur_byte_ct_addsub0000_lut(10),
      O => cur_byte_ct_addsub0000(10)
    );
  Msub_cur_byte_ct_addsub0000_xor_11_Q : XORCY
    port map (
      CI => Msub_cur_byte_ct_addsub0000_cy(10),
      LI => Msub_cur_byte_ct_addsub0000_lut(11),
      O => cur_byte_ct_addsub0000(11)
    );
  d_mux_47_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => sof_i,
      I1 => d_i(47),
      O => d_mux(47)
    );
  byte_ct_1dw_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => d_i(3),
      I1 => d_i(0),
      O => byte_ct_1dw(2)
    );
  cur_fulltype_oh_or00051 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => d_i(61),
      I1 => d_i(60),
      I2 => d_i(59),
      O => cur_fulltype_oh_or0005
    );
  byte_ct_1dw_0_1 : LUT4
    generic map(
      INIT => X"4B57"
    )
    port map (
      I0 => d_i(0),
      I1 => d_i(1),
      I2 => d_i(3),
      I3 => d_i(2),
      O => byte_ct_1dw(0)
    );
  byte_ct_1dw_1_1 : LUT4
    generic map(
      INIT => X"7660"
    )
    port map (
      I0 => d_i(0),
      I1 => d_i(3),
      I2 => d_i(1),
      I3 => d_i(2),
      O => byte_ct_1dw(1)
    );
  cur_fulltype_oh_or00061 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => d_i(57),
      I1 => d_i(59),
      I2 => d_i(60),
      I3 => d_i(61),
      I4 => d_i(58),
      O => cur_fulltype_oh_or0006
    );
  cur_fulltype_oh_or00021 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => d_i(56),
      I1 => d_i(62),
      I2 => d_i(58),
      I3 => d_i(59),
      I4 => d_i(60),
      I5 => d_i(57),
      O => cur_fulltype_oh_or0002
    );
  cur_fulltype_oh_or00011 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => d_i(62),
      I1 => d_i(56),
      I2 => d_i(58),
      I3 => d_i(59),
      I4 => d_i(60),
      I5 => d_i(57),
      O => cur_fulltype_oh_or0001
    );
  vend_msg_o_mux00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_vend_msg_25571,
      O => vend_msg_o_mux0000
    );
  cur_lower_addr_1_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_first_be_adj(1),
      O => cur_lower_addr_1_mux0000
    );
  cur_lower_addr_0_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_first_be_adj(0),
      O => cur_lower_addr_0_mux0000
    );
  cur_cpl_ep_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cur_fulltype_oh_0_Q,
      I1 => cur_ep_25444,
      O => cur_cpl_ep_mux0000
    );
  Mxor_rem_q_1_xor0000_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => cur_td_25568,
      I1 => rem_i,
      O => rem_q_1_xor0000
    );
  src_rdy_q_1_and00001 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => src_rdy_i,
      I1 => packet_ip_26047,
      I2 => sof_i,
      O => src_rdy_q_1_and0000
    );
  remove_lastword_mux00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_td_q_25570,
      I1 => eof_q_3_Q,
      I2 => cur_rem_25534,
      O => remove_lastword_mux0000
    );
  packet_ip_and00001 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => packet_ip_26047,
      I1 => eof_i,
      I2 => sof_i,
      O => packet_ip_and0000
    );
  cur_np_and00001 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => cur_fulltype_oh_5_Q,
      I1 => cur_fulltype_oh_1_Q,
      I2 => cur_fulltype_oh_0_Q,
      O => cur_np_and0000
    );
  np_o_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_np_25531,
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => np_o_mux0000
    );
  locked_o_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_locked_q_25507,
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => locked_o_mux0000
    );
  err_tlp_cpl_header_o_mux0000_9_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(9),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(9)
    );
  err_tlp_cpl_header_o_mux0000_8_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(8),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(8)
    );
  err_tlp_cpl_header_o_mux0000_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(7),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(7)
    );
  err_tlp_cpl_header_o_mux0000_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(6),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(6)
    );
  err_tlp_cpl_header_o_mux0000_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(5),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(5)
    );
  err_tlp_cpl_header_o_mux0000_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(4),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(4)
    );
  err_tlp_cpl_header_o_mux0000_47_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(6),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(47)
    );
  err_tlp_cpl_header_o_mux0000_46_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(5),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(46)
    );
  err_tlp_cpl_header_o_mux0000_45_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(4),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(45)
    );
  err_tlp_cpl_header_o_mux0000_44_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(3),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(44)
    );
  err_tlp_cpl_header_o_mux0000_43_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(2),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(43)
    );
  err_tlp_cpl_header_o_mux0000_42_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(1),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(42)
    );
  err_tlp_cpl_header_o_mux0000_41_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_lower_addr(0),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(41)
    );
  err_tlp_cpl_header_o_mux0000_40_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(11),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(40)
    );
  err_tlp_cpl_header_o_mux0000_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(3),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(3)
    );
  err_tlp_cpl_header_o_mux0000_39_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(10),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(39)
    );
  err_tlp_cpl_header_o_mux0000_38_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(9),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(38)
    );
  err_tlp_cpl_header_o_mux0000_37_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(8),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(37)
    );
  err_tlp_cpl_header_o_mux0000_36_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(7),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(36)
    );
  err_tlp_cpl_header_o_mux0000_35_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(6),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(35)
    );
  err_tlp_cpl_header_o_mux0000_34_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(5),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(34)
    );
  err_tlp_cpl_header_o_mux0000_33_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(4),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(33)
    );
  err_tlp_cpl_header_o_mux0000_32_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(3),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(32)
    );
  err_tlp_cpl_header_o_mux0000_31_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(2),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(31)
    );
  err_tlp_cpl_header_o_mux0000_30_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(1),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(30)
    );
  err_tlp_cpl_header_o_mux0000_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(2),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(2)
    );
  err_tlp_cpl_header_o_mux0000_29_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_byte_ct(0),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(29)
    );
  err_tlp_cpl_header_o_mux0000_28_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(28),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(28)
    );
  err_tlp_cpl_header_o_mux0000_27_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(27),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(27)
    );
  err_tlp_cpl_header_o_mux0000_26_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(26),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(26)
    );
  err_tlp_cpl_header_o_mux0000_25_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(25),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(25)
    );
  err_tlp_cpl_header_o_mux0000_24_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(24),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(24)
    );
  err_tlp_cpl_header_o_mux0000_23_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(23),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(23)
    );
  err_tlp_cpl_header_o_mux0000_22_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(22),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(22)
    );
  err_tlp_cpl_header_o_mux0000_21_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(21),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(21)
    );
  err_tlp_cpl_header_o_mux0000_20_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(20),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(20)
    );
  err_tlp_cpl_header_o_mux0000_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(1),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(1)
    );
  err_tlp_cpl_header_o_mux0000_19_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(19),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(19)
    );
  err_tlp_cpl_header_o_mux0000_18_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(18),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(18)
    );
  err_tlp_cpl_header_o_mux0000_17_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(17),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(17)
    );
  err_tlp_cpl_header_o_mux0000_16_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(16),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(16)
    );
  err_tlp_cpl_header_o_mux0000_15_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(15),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(15)
    );
  err_tlp_cpl_header_o_mux0000_14_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(14),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(14)
    );
  err_tlp_cpl_header_o_mux0000_13_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(13),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(13)
    );
  err_tlp_cpl_header_o_mux0000_12_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(12),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(12)
    );
  err_tlp_cpl_header_o_mux0000_11_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(11),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(11)
    );
  err_tlp_cpl_header_o_mux0000_10_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(10),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(10)
    );
  err_tlp_cpl_header_o_mux0000_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_header_fmt(0),
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => err_tlp_cpl_header_o_mux0000(0)
    );
  d_o_mux0000_9_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(9),
      I2 => d_q6(9),
      O => d_o_mux0000(9)
    );
  d_o_mux0000_8_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(8),
      I2 => d_q6(8),
      O => d_o_mux0000(8)
    );
  d_o_mux0000_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(7),
      I2 => d_q6(7),
      O => d_o_mux0000(7)
    );
  d_o_mux0000_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(6),
      I2 => d_q6(6),
      O => d_o_mux0000(6)
    );
  d_o_mux0000_63_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(63),
      I2 => d_q6(63),
      O => d_o_mux0000(63)
    );
  d_o_mux0000_62_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(62),
      I2 => d_q6(62),
      O => d_o_mux0000(62)
    );
  d_o_mux0000_61_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(61),
      I2 => d_q6(61),
      O => d_o_mux0000(61)
    );
  d_o_mux0000_60_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(60),
      I2 => d_q6(60),
      O => d_o_mux0000(60)
    );
  d_o_mux0000_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(5),
      I2 => d_q6(5),
      O => d_o_mux0000(5)
    );
  d_o_mux0000_59_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(59),
      I2 => d_q6(59),
      O => d_o_mux0000(59)
    );
  d_o_mux0000_58_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(58),
      I2 => d_q6(58),
      O => d_o_mux0000(58)
    );
  d_o_mux0000_57_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(57),
      I2 => d_q6(57),
      O => d_o_mux0000(57)
    );
  d_o_mux0000_56_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(56),
      I2 => d_q6(56),
      O => d_o_mux0000(56)
    );
  d_o_mux0000_55_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(55),
      I2 => d_q6(55),
      O => d_o_mux0000(55)
    );
  d_o_mux0000_54_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(54),
      I2 => d_q6(54),
      O => d_o_mux0000(54)
    );
  d_o_mux0000_53_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(53),
      I2 => d_q6(53),
      O => d_o_mux0000(53)
    );
  d_o_mux0000_52_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(52),
      I2 => d_q6(52),
      O => d_o_mux0000(52)
    );
  d_o_mux0000_51_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(51),
      I2 => d_q6(51),
      O => d_o_mux0000(51)
    );
  d_o_mux0000_50_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(50),
      I2 => d_q6(50),
      O => d_o_mux0000(50)
    );
  d_o_mux0000_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(4),
      I2 => d_q6(4),
      O => d_o_mux0000(4)
    );
  d_o_mux0000_49_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(49),
      I2 => d_q6(49),
      O => d_o_mux0000(49)
    );
  d_o_mux0000_48_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(48),
      I2 => d_q6(48),
      O => d_o_mux0000(48)
    );
  d_o_mux0000_47_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(47),
      I2 => d_q6(47),
      O => d_o_mux0000(47)
    );
  d_o_mux0000_46_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(46),
      I2 => d_q6(46),
      O => d_o_mux0000(46)
    );
  d_o_mux0000_45_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(45),
      I2 => d_q6(45),
      O => d_o_mux0000(45)
    );
  d_o_mux0000_44_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(44),
      I2 => d_q6(44),
      O => d_o_mux0000(44)
    );
  d_o_mux0000_43_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(43),
      I2 => d_q6(43),
      O => d_o_mux0000(43)
    );
  d_o_mux0000_42_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(42),
      I2 => d_q6(42),
      O => d_o_mux0000(42)
    );
  d_o_mux0000_41_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(41),
      I2 => d_q6(41),
      O => d_o_mux0000(41)
    );
  d_o_mux0000_40_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(40),
      I2 => d_q6(40),
      O => d_o_mux0000(40)
    );
  d_o_mux0000_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(3),
      I2 => d_q6(3),
      O => d_o_mux0000(3)
    );
  d_o_mux0000_39_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(39),
      I2 => d_q6(39),
      O => d_o_mux0000(39)
    );
  d_o_mux0000_38_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(38),
      I2 => d_q6(38),
      O => d_o_mux0000(38)
    );
  d_o_mux0000_37_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(37),
      I2 => d_q6(37),
      O => d_o_mux0000(37)
    );
  d_o_mux0000_36_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(36),
      I2 => d_q6(36),
      O => d_o_mux0000(36)
    );
  d_o_mux0000_35_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(35),
      I2 => d_q6(35),
      O => d_o_mux0000(35)
    );
  d_o_mux0000_34_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(34),
      I2 => d_q6(34),
      O => d_o_mux0000(34)
    );
  d_o_mux0000_33_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(33),
      I2 => d_q6(33),
      O => d_o_mux0000(33)
    );
  d_o_mux0000_32_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(32),
      I2 => d_q6(32),
      O => d_o_mux0000(32)
    );
  d_o_mux0000_31_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(31),
      I2 => d_q6(31),
      O => d_o_mux0000(31)
    );
  d_o_mux0000_30_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(30),
      I2 => d_q6(30),
      O => d_o_mux0000(30)
    );
  d_o_mux0000_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(2),
      I2 => d_q6(2),
      O => d_o_mux0000(2)
    );
  d_o_mux0000_29_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(29),
      I2 => d_q6(29),
      O => d_o_mux0000(29)
    );
  d_o_mux0000_28_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(28),
      I2 => d_q6(28),
      O => d_o_mux0000(28)
    );
  d_o_mux0000_27_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(27),
      I2 => d_q6(27),
      O => d_o_mux0000(27)
    );
  d_o_mux0000_26_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(26),
      I2 => d_q6(26),
      O => d_o_mux0000(26)
    );
  d_o_mux0000_25_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(25),
      I2 => d_q6(25),
      O => d_o_mux0000(25)
    );
  d_o_mux0000_24_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(24),
      I2 => d_q6(24),
      O => d_o_mux0000(24)
    );
  d_o_mux0000_23_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(23),
      I2 => d_q6(23),
      O => d_o_mux0000(23)
    );
  d_o_mux0000_22_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(22),
      I2 => d_q6(22),
      O => d_o_mux0000(22)
    );
  d_o_mux0000_21_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(21),
      I2 => d_q6(21),
      O => d_o_mux0000(21)
    );
  d_o_mux0000_20_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(20),
      I2 => d_q6(20),
      O => d_o_mux0000(20)
    );
  d_o_mux0000_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(1),
      I2 => d_q6(1),
      O => d_o_mux0000(1)
    );
  d_o_mux0000_19_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(19),
      I2 => d_q6(19),
      O => d_o_mux0000(19)
    );
  d_o_mux0000_18_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(18),
      I2 => d_q6(18),
      O => d_o_mux0000(18)
    );
  d_o_mux0000_17_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(17),
      I2 => d_q6(17),
      O => d_o_mux0000(17)
    );
  d_o_mux0000_16_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(16),
      I2 => d_q6(16),
      O => d_o_mux0000(16)
    );
  d_o_mux0000_15_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(15),
      I2 => d_q6(15),
      O => d_o_mux0000(15)
    );
  d_o_mux0000_14_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(14),
      I2 => d_q6(14),
      O => d_o_mux0000(14)
    );
  d_o_mux0000_13_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(13),
      I2 => d_q6(13),
      O => d_o_mux0000(13)
    );
  d_o_mux0000_12_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(12),
      I2 => d_q6(12),
      O => d_o_mux0000(12)
    );
  d_o_mux0000_11_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(11),
      I2 => d_q6(11),
      O => d_o_mux0000(11)
    );
  d_o_mux0000_10_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(10),
      I2 => d_q6(10),
      O => d_o_mux0000(10)
    );
  d_o_mux0000_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => d_q5(0),
      I2 => d_q6(0),
      O => d_o_mux0000(0)
    );
  cpl_o_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cpl_25404,
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => cpl_o_mux0000
    );
  cfg_o_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => cur_cfg,
      I2 => NlwRenamedSig_OI_bar_o(2),
      O => cfg_o_mux0000
    );
  cur_cpl_ur_mux00001 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cur_fulltype_oh_0_Q,
      I1 => cur_cpl_stat(1),
      I2 => cur_cpl_stat(2),
      I3 => cur_cpl_stat(0),
      O => cur_cpl_ur_mux0000
    );
  cur_cpl_abort_mux00001 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cur_fulltype_oh_0_Q,
      I1 => cur_cpl_stat(0),
      I2 => cur_cpl_stat(1),
      I3 => cur_cpl_stat(2),
      O => cur_cpl_abort_mux0000
    );
  err_tlp_malformed_o_and00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => malformed,
      I1 => rhit_bar_lat3_i,
      I2 => eof_nd_q_4_Q,
      I3 => eof_nd_q_5_Q,
      O => err_tlp_malformed_o_and0000
    );
  cur_lower_addr_6_mux00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_fulltype_64_25455,
      I2 => lower_addr32_in_q(6),
      I3 => lower_addr64_in_q(6),
      O => cur_lower_addr_6_mux0000
    );
  cur_lower_addr_5_mux00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_fulltype_64_25455,
      I2 => lower_addr32_in_q(5),
      I3 => lower_addr64_in_q(5),
      O => cur_lower_addr_5_mux0000
    );
  cur_lower_addr_4_mux00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_fulltype_64_25455,
      I2 => lower_addr32_in_q(4),
      I3 => lower_addr64_in_q(4),
      O => cur_lower_addr_4_mux0000
    );
  cur_lower_addr_3_mux00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_fulltype_64_25455,
      I2 => lower_addr32_in_q(3),
      I3 => lower_addr64_in_q(3),
      O => cur_lower_addr_3_mux0000
    );
  cur_lower_addr_2_mux00001 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_fulltype_mem_25457,
      I1 => cur_fulltype_64_25455,
      I2 => lower_addr32_in_q(2),
      I3 => lower_addr64_in_q(2),
      O => cur_lower_addr_2_mux0000
    );
  err_tlp_ur_o_and00001 : LUT5
    generic map(
      INIT => X"44044000"
    )
    port map (
      I0 => malformed,
      I1 => tlp_ur,
      I2 => rhit_bar_lat3_i,
      I3 => eof_nd_q_5_Q,
      I4 => eof_nd_q_4_Q,
      O => err_tlp_ur_o_and0000
    );
  err_tlp_ur_lock_o_and00001 : LUT5
    generic map(
      INIT => X"44044000"
    )
    port map (
      I0 => malformed,
      I1 => tlp_ur_lock,
      I2 => rhit_bar_lat3_i,
      I3 => eof_nd_q_5_Q,
      I4 => eof_nd_q_4_Q,
      O => err_tlp_ur_lock_o_and0000
    );
  rem_o_mux00001 : LUT5
    generic map(
      INIT => X"FDB96420"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => remove_lastword_26071,
      I2 => rem_q_6_Q,
      I3 => rem_q_4_Q,
      I4 => rem_q_5_Q,
      O => rem_o_mux0000
    );
  Q_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => sof_i,
      I1 => src_rdy_i,
      I2 => packet_ip_26047,
      O => Q_and0000
    );
  cur_fulltype_oh_mux0000_1_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => cur_fulltype_oh_or0003,
      I1 => cur_fulltype_mem_or0000,
      O => cur_fulltype_oh_mux0000(1)
    );
  cur_fulltype_64_or00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => d_i(61),
      I1 => cur_fulltype_mem_or0000,
      O => cur_fulltype_64_or0000
    );
  cur_fulltype_oh_or00031 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => d_i(57),
      I1 => d_i(56),
      I2 => d_i(59),
      I3 => d_i(60),
      I4 => d_i(61),
      I5 => d_i(58),
      O => cur_fulltype_oh_or0003
    );
  cur_fulltype_64_or000021 : LUT6
    generic map(
      INIT => X"0000000100010001"
    )
    port map (
      I0 => d_i(57),
      I1 => d_i(58),
      I2 => d_i(59),
      I3 => d_i(60),
      I4 => d_i(56),
      I5 => d_i(62),
      O => cur_fulltype_mem_or0000
    );
  bar_src_rdy_o_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rhit_src_rdy,
      I1 => reset_i,
      O => bar_src_rdy_o_or0000
    );
  remove_lastword_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => NlwRenamedSig_OI_eof_o,
      I1 => eof_q_3_Q,
      O => remove_lastword_not0001
    );
  err_tlp_cpl_header_o_not00021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => eof_q_3_Q,
      I1 => rhit_bar_lat3_i,
      O => err_tlp_cpl_header_o_not0002
    );
  cpl_o_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => latch_1st_dword_q4_26022,
      I1 => rhit_bar_lat3_i,
      O => cpl_o_not0001
    );
  cur_lower_addr_6_not00011 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cur_fulltype_64_25455,
      I1 => latch_3rd_dword_q1_26025,
      I2 => latch_4th_dword_q1_26026,
      O => cur_lower_addr_6_not0001
    );
  rem_q_1_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => eof_i,
      I1 => reset_i,
      O => rem_q_1_or0000
    );
  latch_1st_dword1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => sof_i,
      I1 => src_rdy_i,
      O => latch_1st_dword
    );
  dsc_q_1_and000011 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => src_rdy_i,
      I1 => eof_i,
      I2 => packet_ip_26047,
      O => Q_and0001
    );
  cur_byte_ct_mux0000_0_2 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_length1_25479,
      I2 => cur_byte_ct_addsub0000(0),
      I3 => cur_byte_ct_1dw(0),
      O => cur_byte_ct_mux0000(0)
    );
  cur_vend_msg_and0000_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => cur_msgcode(3),
      I1 => cur_msgcode(2),
      I2 => cur_msgcode(7),
      O => N29
    );
  cur_vend_msg_and0000 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => cur_msgcode(5),
      I1 => cur_fulltype_oh_1_Q,
      I2 => cur_msgcode(6),
      I3 => N29,
      I4 => cur_msgcode(1),
      I5 => cur_msgcode(4),
      O => cur_vend_msg_and0000_25572
    );
  first_be_missing_1_1 : LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      I0 => d_i(2),
      I1 => d_i(0),
      I2 => d_i(1),
      I3 => d_i(3),
      O => first_be_missing(1)
    );
  first_be_missing_0_1 : LUT4
    generic map(
      INIT => X"2232"
    )
    port map (
      I0 => d_i(1),
      I1 => d_i(0),
      I2 => d_i(3),
      I3 => d_i(2),
      O => first_be_missing(0)
    );
  Madd_cur_bytes_missing_addsub0000_lut_0_1 : LUT5
    generic map(
      INIT => X"9999AA9A"
    )
    port map (
      I0 => first_be_missing(0),
      I1 => d_i(7),
      I2 => d_i(4),
      I3 => d_i(5),
      I4 => d_i(6),
      O => Madd_cur_bytes_missing_addsub0000_lut(0)
    );
  next_cur_drop11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => malformed,
      I1 => tlp_filt,
      I2 => tlp_uc,
      I3 => tlp_ur,
      I4 => cur_hp_msg_detect,
      I5 => cur_pm_msg_detect,
      O => N3
    );
  Q_COND_721 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => sof_q_5_Q,
      I2 => sof_q_6_Q,
      O => Q_COND_72
    );
  cur_length1_mux000018 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => d_i(35),
      I1 => d_i(36),
      I2 => d_i(34),
      I3 => d_i(33),
      O => cur_length1_mux000018_25481
    );
  cur_length1_mux000060 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => d_i(32),
      I1 => d_i(41),
      I2 => d_i(40),
      I3 => d_i(39),
      I4 => d_i(38),
      I5 => d_i(37),
      O => cur_length1_mux000060_25482
    );
  cur_byte_ct_mux0000_1_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_length1_25479,
      I2 => cur_byte_ct_addsub0000(1),
      I3 => cur_byte_ct_1dw(1),
      O => cur_byte_ct_mux0000(1)
    );
  cur_byte_ct_mux0000_2_1 : LUT4
    generic map(
      INIT => X"FD75"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_length1_25479,
      I2 => cur_byte_ct_addsub0000(2),
      I3 => cur_byte_ct_1dw(2),
      O => cur_byte_ct_mux0000(2)
    );
  cur_byte_ct_or00001 : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => cur_fulltype_1_Q,
      I1 => cur_fulltype_2_Q,
      I2 => cur_fulltype_3_Q,
      I3 => cur_fulltype_4_Q,
      I4 => cur_fulltype_6_Q,
      O => cur_byte_ct_or0000
    );
  malformed_checks : tlm_rx_data_snk_mal
    port map (
      legacy_mode_i => NlwRenamedSig_OI_bar_o(2),
      reset_i => reset_i,
      tlp_uc_o => tlp_uc,
      eval_formats_i => latch_2nd_dword_q1_26023,
      rem_i => rem_i,
      td_i => cur_td_25568,
      tlp_ur_lock_o => tlp_ur_lock,
      hit_src_rdy_i => rhit_src_rdy,
      hit_i => rhit_d,
      length_1dw_i => cur_length1_25479,
      tlp_filt_o => tlp_filt,
      hit_lock_i => rhit_lock,
      malformed_o => malformed,
      ext_cfg_access_i => NlwRenamedSig_OI_bar_o(2),
      legacy_cfg_access_i => NlwRenamedSig_OI_bar_o(2),
      cfg_o => cur_cfg,
      hit_ack_i => rhit_ack,
      tc0_i => cur_tc0_25560,
      load_aperture_i => sof_q_1_Q,
      eof_i => Q_and0001,
      eval_fulltype_i => latch_1st_dword,
      eval_msgcode_i => latch_1st_dword,
      clk_i => clk_i,
      hp_msg_detect_o => cur_hp_msg_detect,
      sof_i => Q_and0000,
      hit_lat3_i => rhit_bar_lat3_i,
      pwr_mgmt_on_i => NlwRenamedSig_OI_bar_o(2),
      data_credits_vld_o => NLW_malformed_checks_data_credits_vld_o_UNCONNECTED,
      tlp_ur_o => tlp_ur,
      data_credits_o(5) => NLW_malformed_checks_data_credits_o_5_UNCONNECTED,
      data_credits_o(4) => NLW_malformed_checks_data_credits_o_4_UNCONNECTED,
      data_credits_o(3) => NLW_malformed_checks_data_credits_o_3_UNCONNECTED,
      data_credits_o(2) => NLW_malformed_checks_data_credits_o_2_UNCONNECTED,
      data_credits_o(1) => NLW_malformed_checks_data_credits_o_1_UNCONNECTED,
      data_credits_o(0) => NLW_malformed_checks_data_credits_o_0_UNCONNECTED,
      max_payload_i(2) => max_payload_i(2),
      max_payload_i(1) => max_payload_i(1),
      max_payload_i(0) => max_payload_i(0),
      fulltype_i(6) => d_i(62),
      fulltype_i(5) => d_i(61),
      fulltype_i(4) => d_i(60),
      fulltype_i(3) => d_i(59),
      fulltype_i(2) => d_i(58),
      fulltype_i(1) => d_i(57),
      fulltype_i(0) => d_i(56),
      offset_i(7) => d_i(39),
      offset_i(6) => d_i(38),
      offset_i(5) => d_i(37),
      offset_i(4) => d_i(36),
      offset_i(3) => d_i(35),
      offset_i(2) => d_i(34),
      offset_i(1) => NlwRenamedSig_OI_bar_o(2),
      offset_i(0) => NlwRenamedSig_OI_bar_o(2),
      msgcode_i(7) => d_i(7),
      msgcode_i(6) => d_i(6),
      msgcode_i(5) => d_i(5),
      msgcode_i(4) => d_i(4),
      msgcode_i(3) => d_i(3),
      msgcode_i(2) => d_i(2),
      msgcode_i(1) => d_i(1),
      msgcode_i(0) => d_i(0),
      length_i(9) => cur_length(9),
      length_i(8) => cur_length(8),
      length_i(7) => cur_length(7),
      length_i(6) => cur_length(6),
      length_i(5) => cur_length(5),
      length_i(4) => cur_length(4),
      length_i(3) => cur_length(3),
      length_i(2) => cur_length(2),
      length_i(1) => cur_length(1),
      length_i(0) => cur_length(0),
      aperture_i(3) => d_i(43),
      aperture_i(2) => d_i(42),
      aperture_i(1) => d_i(41),
      aperture_i(0) => d_i(40)
    );
  pwr_mgmt : tlm_rx_data_snk_pwr_mgmt
    port map (
      reset_i => reset_i,
      ismsg_i => cur_fulltype_oh_1_Q,
      eval_pwr_mgmt_i => latch_2nd_dword_q2_26024,
      pm_turn_off_o => pm_turn_off_o,
      eval_pwr_mgmt_data_i => latch_4th_dword_q1_26026,
      pm_set_slot_pwr_o => pm_set_slot_pwr_o,
      clk_i => clk_i,
      act_pwr_mgmt_i => NLW_pwr_mgmt_act_pwr_mgmt_i_UNCONNECTED,
      pm_as_nak_l1_o => pm_as_nak_l1_o,
      pm_msg_detect_o => cur_pm_msg_detect,
      pm_set_slot_pwr_data_o(9) => pm_set_slot_pwr_data_o(9),
      pm_set_slot_pwr_data_o(8) => pm_set_slot_pwr_data_o(8),
      pm_set_slot_pwr_data_o(7) => pm_set_slot_pwr_data_o(7),
      pm_set_slot_pwr_data_o(6) => pm_set_slot_pwr_data_o(6),
      pm_set_slot_pwr_data_o(5) => pm_set_slot_pwr_data_o(5),
      pm_set_slot_pwr_data_o(4) => pm_set_slot_pwr_data_o(4),
      pm_set_slot_pwr_data_o(3) => pm_set_slot_pwr_data_o(3),
      pm_set_slot_pwr_data_o(2) => pm_set_slot_pwr_data_o(2),
      pm_set_slot_pwr_data_o(1) => pm_set_slot_pwr_data_o(1),
      pm_set_slot_pwr_data_o(0) => pm_set_slot_pwr_data_o(0),
      msgcode_i(7) => cur_msgcode(7),
      msgcode_i(6) => cur_msgcode(6),
      msgcode_i(5) => cur_msgcode(5),
      msgcode_i(4) => cur_msgcode(4),
      msgcode_i(3) => cur_msgcode(3),
      msgcode_i(2) => cur_msgcode(2),
      msgcode_i(1) => cur_msgcode(1),
      msgcode_i(0) => cur_msgcode(0),
      pwr_data_i(9) => d_i(49),
      pwr_data_i(8) => d_i(48),
      pwr_data_i(7) => d_i(63),
      pwr_data_i(6) => d_i(62),
      pwr_data_i(5) => d_i(61),
      pwr_data_i(4) => d_i(60),
      pwr_data_i(3) => d_i(59),
      pwr_data_i(2) => d_i(58),
      pwr_data_i(1) => d_i(57),
      pwr_data_i(0) => d_i(56)
    );
  bar_hit : tlm_rx_data_snk_bar
    port map (
      legacy_mode_i => NlwRenamedSig_OI_bar_o(2),
      reset_i => reset_i,
      check_rhit_src_rdy_o => rhit_src_rdy,
      check_rfun_id_o => check_rfun_o,
      check_rhit_lock_o => rhit_lock,
      check_rhit_ack_o => rhit_ack,
      check_rhit_i => check_rhit_i,
      check_rhit_o => rhit_d,
      rhit_lat3_i => rhit_bar_lat3_i,
      check_rmem32_o => check_mem32_o,
      check_rdev_id_o => check_rdev_o,
      clk_i => clk_i,
      eval_check_i => sof_q_1_Q,
      check_rio_o => check_rio_o,
      check_rmem64_o => check_mem64_o,
      check_rbus_id_o => check_rbus_o,
      mem64_i => cur_fulltype_64_25455,
      check_rhit_bar_o(6) => rhit_bar_d_6_Q,
      check_rhit_bar_o(5) => NLW_bar_hit_check_rhit_bar_o_5_UNCONNECTED,
      check_rhit_bar_o(4) => NLW_bar_hit_check_rhit_bar_o_4_UNCONNECTED,
      check_rhit_bar_o(3) => NLW_bar_hit_check_rhit_bar_o_3_UNCONNECTED,
      check_rhit_bar_o(2) => NLW_bar_hit_check_rhit_bar_o_2_UNCONNECTED,
      check_rhit_bar_o(1) => rhit_bar_d_1_Q,
      check_rhit_bar_o(0) => rhit_bar_d_0_Q,
      check_raddr_o(63) => check_raddr_o(63),
      check_raddr_o(62) => check_raddr_o(62),
      check_raddr_o(61) => check_raddr_o(61),
      check_raddr_o(60) => check_raddr_o(60),
      check_raddr_o(59) => check_raddr_o(59),
      check_raddr_o(58) => check_raddr_o(58),
      check_raddr_o(57) => check_raddr_o(57),
      check_raddr_o(56) => check_raddr_o(56),
      check_raddr_o(55) => check_raddr_o(55),
      check_raddr_o(54) => check_raddr_o(54),
      check_raddr_o(53) => check_raddr_o(53),
      check_raddr_o(52) => check_raddr_o(52),
      check_raddr_o(51) => check_raddr_o(51),
      check_raddr_o(50) => check_raddr_o(50),
      check_raddr_o(49) => check_raddr_o(49),
      check_raddr_o(48) => check_raddr_o(48),
      check_raddr_o(47) => check_raddr_o(47),
      check_raddr_o(46) => check_raddr_o(46),
      check_raddr_o(45) => check_raddr_o(45),
      check_raddr_o(44) => check_raddr_o(44),
      check_raddr_o(43) => check_raddr_o(43),
      check_raddr_o(42) => check_raddr_o(42),
      check_raddr_o(41) => check_raddr_o(41),
      check_raddr_o(40) => check_raddr_o(40),
      check_raddr_o(39) => check_raddr_o(39),
      check_raddr_o(38) => check_raddr_o(38),
      check_raddr_o(37) => check_raddr_o(37),
      check_raddr_o(36) => check_raddr_o(36),
      check_raddr_o(35) => check_raddr_o(35),
      check_raddr_o(34) => check_raddr_o(34),
      check_raddr_o(33) => check_raddr_o(33),
      check_raddr_o(32) => check_raddr_o(32),
      check_raddr_o(31) => check_raddr_o(31),
      check_raddr_o(30) => check_raddr_o(30),
      check_raddr_o(29) => check_raddr_o(29),
      check_raddr_o(28) => check_raddr_o(28),
      check_raddr_o(27) => check_raddr_o(27),
      check_raddr_o(26) => check_raddr_o(26),
      check_raddr_o(25) => check_raddr_o(25),
      check_raddr_o(24) => check_raddr_o(24),
      check_raddr_o(23) => check_raddr_o(23),
      check_raddr_o(22) => check_raddr_o(22),
      check_raddr_o(21) => check_raddr_o(21),
      check_raddr_o(20) => check_raddr_o(20),
      check_raddr_o(19) => check_raddr_o(19),
      check_raddr_o(18) => check_raddr_o(18),
      check_raddr_o(17) => check_raddr_o(17),
      check_raddr_o(16) => check_raddr_o(16),
      check_raddr_o(15) => check_raddr_o(15),
      check_raddr_o(14) => check_raddr_o(14),
      check_raddr_o(13) => check_raddr_o(13),
      check_raddr_o(12) => check_raddr_o(12),
      check_raddr_o(11) => check_raddr_o(11),
      check_raddr_o(10) => check_raddr_o(10),
      check_raddr_o(9) => check_raddr_o(9),
      check_raddr_o(8) => check_raddr_o(8),
      check_raddr_o(7) => check_raddr_o(7),
      check_raddr_o(6) => check_raddr_o(6),
      check_raddr_o(5) => check_raddr_o(5),
      check_raddr_o(4) => check_raddr_o(4),
      check_raddr_o(3) => check_raddr_o(3),
      check_raddr_o(2) => check_raddr_o(2),
      check_raddr_o(1) => check_raddr_o(1),
      check_raddr_o(0) => check_raddr_o(0),
      addr_hi_i(31) => d_i(63),
      addr_hi_i(30) => d_i(62),
      addr_hi_i(29) => d_i(61),
      addr_hi_i(28) => d_i(60),
      addr_hi_i(27) => d_i(59),
      addr_hi_i(26) => d_i(58),
      addr_hi_i(25) => d_i(57),
      addr_hi_i(24) => d_i(56),
      addr_hi_i(23) => d_i(55),
      addr_hi_i(22) => d_i(54),
      addr_hi_i(21) => d_i(53),
      addr_hi_i(20) => d_i(52),
      addr_hi_i(19) => d_i(51),
      addr_hi_i(18) => d_i(50),
      addr_hi_i(17) => d_i(49),
      addr_hi_i(16) => d_i(48),
      addr_hi_i(15) => d_i(47),
      addr_hi_i(14) => d_i(46),
      addr_hi_i(13) => d_i(45),
      addr_hi_i(12) => d_i(44),
      addr_hi_i(11) => d_i(43),
      addr_hi_i(10) => d_i(42),
      addr_hi_i(9) => d_i(41),
      addr_hi_i(8) => d_i(40),
      addr_hi_i(7) => d_i(39),
      addr_hi_i(6) => d_i(38),
      addr_hi_i(5) => d_i(37),
      addr_hi_i(4) => d_i(36),
      addr_hi_i(3) => d_i(35),
      addr_hi_i(2) => d_i(34),
      addr_hi_i(1) => d_i(33),
      addr_hi_i(0) => d_i(32),
      check_rhit_bar_i(6) => check_rhit_bar_i(6),
      check_rhit_bar_i(5) => check_rhit_bar_i(5),
      check_rhit_bar_i(4) => check_rhit_bar_i(4),
      check_rhit_bar_i(3) => check_rhit_bar_i(3),
      check_rhit_bar_i(2) => check_rhit_bar_i(2),
      check_rhit_bar_i(1) => check_rhit_bar_i(1),
      check_rhit_bar_i(0) => check_rhit_bar_i(0),
      routing_i(2) => cur_fulltype_2_Q,
      routing_i(1) => cur_fulltype_1_Q,
      routing_i(0) => cur_fulltype_0_Q,
      req_id_i(15) => cur_req_id(15),
      req_id_i(14) => cur_req_id(14),
      req_id_i(13) => cur_req_id(13),
      req_id_i(12) => cur_req_id(12),
      req_id_i(11) => cur_req_id(11),
      req_id_i(10) => cur_req_id(10),
      req_id_i(9) => cur_req_id(9),
      req_id_i(8) => cur_req_id(8),
      req_id_i(7) => cur_req_id(7),
      req_id_i(6) => cur_req_id(6),
      req_id_i(5) => cur_req_id(5),
      req_id_i(4) => cur_req_id(4),
      req_id_i(3) => cur_req_id(3),
      req_id_i(2) => cur_req_id(2),
      req_id_i(1) => cur_req_id(1),
      req_id_i(0) => cur_req_id(0),
      addr_lo_i(31) => d_i(31),
      addr_lo_i(30) => d_i(30),
      addr_lo_i(29) => d_i(29),
      addr_lo_i(28) => d_i(28),
      addr_lo_i(27) => d_i(27),
      addr_lo_i(26) => d_i(26),
      addr_lo_i(25) => d_i(25),
      addr_lo_i(24) => d_i(24),
      addr_lo_i(23) => d_i(23),
      addr_lo_i(22) => d_i(22),
      addr_lo_i(21) => d_i(21),
      addr_lo_i(20) => d_i(20),
      addr_lo_i(19) => d_i(19),
      addr_lo_i(18) => d_i(18),
      addr_lo_i(17) => d_i(17),
      addr_lo_i(16) => d_i(16),
      addr_lo_i(15) => d_i(15),
      addr_lo_i(14) => d_i(14),
      addr_lo_i(13) => d_i(13),
      addr_lo_i(12) => d_i(12),
      addr_lo_i(11) => d_i(11),
      addr_lo_i(10) => d_i(10),
      addr_lo_i(9) => d_i(9),
      addr_lo_i(8) => d_i(8),
      addr_lo_i(7) => d_i(7),
      addr_lo_i(6) => d_i(6),
      addr_lo_i(5) => d_i(5),
      addr_lo_i(4) => d_i(4),
      addr_lo_i(3) => d_i(3),
      addr_lo_i(2) => d_i(2),
      addr_lo_i(1) => d_i(1),
      addr_lo_i(0) => d_i(0),
      req_id_cpl_i(15) => d_i(63),
      req_id_cpl_i(14) => d_i(62),
      req_id_cpl_i(13) => d_i(61),
      req_id_cpl_i(12) => d_i(60),
      req_id_cpl_i(11) => d_i(59),
      req_id_cpl_i(10) => d_i(58),
      req_id_cpl_i(9) => d_i(57),
      req_id_cpl_i(8) => d_i(56),
      req_id_cpl_i(7) => d_i(55),
      req_id_cpl_i(6) => d_i(54),
      req_id_cpl_i(5) => d_i(53),
      req_id_cpl_i(4) => d_i(52),
      req_id_cpl_i(3) => d_i(51),
      req_id_cpl_i(2) => d_i(50),
      req_id_cpl_i(1) => d_i(49),
      req_id_cpl_i(0) => d_i(48),
      fulltype_oh_i(8) => cur_fulltype_oh_8_Q,
      fulltype_oh_i(7) => cur_fulltype_oh_7_Q,
      fulltype_oh_i(6) => NLW_bar_hit_fulltype_oh_i_6_UNCONNECTED,
      fulltype_oh_i(5) => cur_fulltype_oh_5_Q,
      fulltype_oh_i(4) => cur_fulltype_oh_4_Q,
      fulltype_oh_i(3) => cur_fulltype_oh_3_Q,
      fulltype_oh_i(2) => NLW_bar_hit_fulltype_oh_i_2_UNCONNECTED,
      fulltype_oh_i(1) => cur_fulltype_oh_1_Q,
      fulltype_oh_i(0) => cur_fulltype_oh_0_Q
    );
  stat_tlp_ep_o_or00001 : LUT5
    generic map(
      INIT => X"FFFFFF27"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => eof_q_5_Q,
      I2 => eof_q_4_Q,
      I3 => N3,
      I4 => reset_i,
      O => stat_tlp_ep_o_or0000
    );
  eof_o_mux00001 : LUT5
    generic map(
      INIT => X"FDB96420"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => remove_lastword_26071,
      I2 => eof_q_6_Q,
      I3 => eof_q_4_Q,
      I4 => eof_q_5_Q,
      O => eof_o_mux0000
    );
  cur_td_mux00001 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_td_25568,
      I2 => src_rdy_i,
      I3 => d_i(47),
      O => cur_td_mux0000
    );
  cur_tc_mux0000_2_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_tc(2),
      I2 => src_rdy_i,
      I3 => d_i(54),
      O => cur_tc_mux0000(2)
    );
  cur_tc_mux0000_1_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_tc(1),
      I2 => src_rdy_i,
      I3 => d_i(53),
      O => cur_tc_mux0000(1)
    );
  cur_tc_mux0000_0_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_tc(0),
      I2 => src_rdy_i,
      I3 => d_i(52),
      O => cur_tc_mux0000(0)
    );
  cur_length_mux0000_9_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(9),
      I2 => src_rdy_i,
      I3 => d_i(41),
      O => cur_length_mux0000(9)
    );
  cur_length_mux0000_8_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(8),
      I2 => src_rdy_i,
      I3 => d_i(40),
      O => cur_length_mux0000(8)
    );
  cur_length_mux0000_7_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(7),
      I2 => src_rdy_i,
      I3 => d_i(39),
      O => cur_length_mux0000(7)
    );
  cur_length_mux0000_6_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(6),
      I2 => src_rdy_i,
      I3 => d_i(38),
      O => cur_length_mux0000(6)
    );
  cur_length_mux0000_5_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(5),
      I2 => src_rdy_i,
      I3 => d_i(37),
      O => cur_length_mux0000(5)
    );
  cur_length_mux0000_4_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(4),
      I2 => src_rdy_i,
      I3 => d_i(36),
      O => cur_length_mux0000(4)
    );
  cur_length_mux0000_3_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(3),
      I2 => src_rdy_i,
      I3 => d_i(35),
      O => cur_length_mux0000(3)
    );
  cur_length_mux0000_2_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(2),
      I2 => src_rdy_i,
      I3 => d_i(34),
      O => cur_length_mux0000(2)
    );
  cur_length_mux0000_1_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(1),
      I2 => src_rdy_i,
      I3 => d_i(33),
      O => cur_length_mux0000(1)
    );
  cur_length_mux0000_0_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length(0),
      I2 => src_rdy_i,
      I3 => d_i(32),
      O => cur_length_mux0000(0)
    );
  cur_fulltype_mux0000_6_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_6_Q,
      I2 => src_rdy_i,
      I3 => d_i(62),
      O => cur_fulltype_mux0000_6_Q
    );
  cur_fulltype_mux0000_4_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_4_Q,
      I2 => src_rdy_i,
      I3 => d_i(60),
      O => cur_fulltype_mux0000_4_Q
    );
  cur_fulltype_mux0000_3_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_3_Q,
      I2 => src_rdy_i,
      I3 => d_i(59),
      O => cur_fulltype_mux0000_3_Q
    );
  cur_fulltype_mux0000_2_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_2_Q,
      I2 => src_rdy_i,
      I3 => d_i(58),
      O => cur_fulltype_mux0000_2_Q
    );
  cur_fulltype_mux0000_1_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_1_Q,
      I2 => src_rdy_i,
      I3 => d_i(57),
      O => cur_fulltype_mux0000_1_Q
    );
  cur_fulltype_mux0000_0_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_fulltype_0_Q,
      I2 => src_rdy_i,
      I3 => d_i(56),
      O => cur_fulltype_mux0000_0_Q
    );
  cur_ep_mux00001 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_ep_25444,
      I2 => src_rdy_i,
      I3 => d_i(46),
      O => cur_ep_mux0000
    );
  cur_attr_mux0000_1_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_attr(1),
      I2 => src_rdy_i,
      I3 => d_i(45),
      O => cur_attr_mux0000(1)
    );
  cur_attr_mux0000_0_1 : LUT4
    generic map(
      INIT => X"EC4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_attr(0),
      I2 => src_rdy_i,
      I3 => d_i(44),
      O => cur_attr_mux0000(0)
    );
  cur_tc0_mux00001 : LUT6
    generic map(
      INIT => X"4C4C4C4C4C4C4CEC"
    )
    port map (
      I0 => sof_i,
      I1 => cur_tc0_25560,
      I2 => src_rdy_i,
      I3 => d_i(52),
      I4 => d_i(53),
      I5 => d_i(54),
      O => cur_tc0_mux0000
    );
  cur_rem_not00011 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => reset_i,
      I1 => eof_i,
      O => cur_rem_not0001
    );
  next_cur_drop2 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => N3,
      I1 => rhit_bar_lat3_i,
      I2 => eof_q_4_Q,
      I3 => eof_q_5_Q,
      O => next_cur_drop
    );
  eof_nd_q_1_and00001 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => src_rdy_i,
      I1 => src_dsc_i,
      I2 => eof_i,
      I3 => packet_ip_26047,
      O => eof_nd_q_1_and0000
    );
  cur_length1_mux000083 : LUT5
    generic map(
      INIT => X"EC4C4C4C"
    )
    port map (
      I0 => sof_i,
      I1 => cur_length1_25479,
      I2 => src_rdy_i,
      I3 => cur_length1_mux000018_25481,
      I4 => cur_length1_mux000060_25482,
      O => cur_length1_mux0000
    );
  cur_byte_ct_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(4),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(4)
    );
  cur_byte_ct_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(3),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(3)
    );
  cur_byte_ct_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(5),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(5)
    );
  cur_byte_ct_mux0000_6_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(6),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(6)
    );
  cur_byte_ct_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(7),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(7)
    );
  cur_byte_ct_mux0000_8_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(8),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(8)
    );
  cur_byte_ct_mux0000_9_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(9),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(9)
    );
  cur_byte_ct_mux0000_10_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(10),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(10)
    );
  cur_byte_ct_mux0000_11_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cur_byte_ct_or0000,
      I1 => cur_byte_ct_addsub0000(11),
      I2 => cur_length1_25479,
      O => cur_byte_ct_mux0000(11)
    );
  Madd_cur_bytes_missing_addsub0000_xor_1_11 : LUT6
    generic map(
      INIT => X"AAAA5566AAAA999A"
    )
    port map (
      I0 => first_be_missing(1),
      I1 => d_i(6),
      I2 => d_i(4),
      I3 => d_i(5),
      I4 => d_i(7),
      I5 => first_be_missing(0),
      O => cur_bytes_missing_addsub0000(1)
    );
  src_rdy_o_mux0000 : MUXF7
    port map (
      I0 => N2,
      I1 => N31,
      S => remove_lastword_26071,
      O => src_rdy_o_mux0000_26092
    );
  src_rdy_o_mux0000_F : LUT5
    generic map(
      INIT => X"C8FA4050"
    )
    port map (
      I0 => rhit_bar_lat3_i,
      I1 => Q_COND_72,
      I2 => src_rdy_q_5_Q,
      I3 => NlwRenamedSig_OI_eof_o,
      I4 => src_rdy_q_6_Q,
      O => N2
    );
  src_rdy_o_mux0000_G : LUT6
    generic map(
      INIT => X"40734040F3F3C0C0"
    )
    port map (
      I0 => rem_q_5_Q,
      I1 => rhit_bar_lat3_i,
      I2 => src_rdy_q_5_Q,
      I3 => rem_q_4_Q,
      I4 => src_rdy_q_4_Q,
      I5 => NlwRenamedSig_OI_eof_o,
      O => N31
    );
  Msub_cur_byte_ct_addsub0000_lut_0_INV_0 : INV
    port map (
      I => cur_bytes_missing(0),
      O => Msub_cur_byte_ct_addsub0000_lut(0)
    );
  Msub_cur_byte_ct_addsub0000_lut_1_INV_0 : INV
    port map (
      I => cur_bytes_missing(1),
      O => Msub_cur_byte_ct_addsub0000_lut(1)
    );
  Msub_cur_byte_ct_addsub0000_lut_3_INV_0 : INV
    port map (
      I => cur_length(1),
      O => Msub_cur_byte_ct_addsub0000_lut(3)
    );
  Msub_cur_byte_ct_addsub0000_lut_4_INV_0 : INV
    port map (
      I => cur_length(2),
      O => Msub_cur_byte_ct_addsub0000_lut(4)
    );
  Msub_cur_byte_ct_addsub0000_lut_5_INV_0 : INV
    port map (
      I => cur_length(3),
      O => Msub_cur_byte_ct_addsub0000_lut(5)
    );
  Msub_cur_byte_ct_addsub0000_lut_6_INV_0 : INV
    port map (
      I => cur_length(4),
      O => Msub_cur_byte_ct_addsub0000_lut(6)
    );
  Msub_cur_byte_ct_addsub0000_lut_7_INV_0 : INV
    port map (
      I => cur_length(5),
      O => Msub_cur_byte_ct_addsub0000_lut(7)
    );
  Msub_cur_byte_ct_addsub0000_lut_8_INV_0 : INV
    port map (
      I => cur_length(6),
      O => Msub_cur_byte_ct_addsub0000_lut(8)
    );
  Msub_cur_byte_ct_addsub0000_lut_9_INV_0 : INV
    port map (
      I => cur_length(7),
      O => Msub_cur_byte_ct_addsub0000_lut(9)
    );
  Msub_cur_byte_ct_addsub0000_lut_10_INV_0 : INV
    port map (
      I => cur_length(8),
      O => Msub_cur_byte_ct_addsub0000_lut(10)
    );
  Msub_cur_byte_ct_addsub0000_lut_11_INV_0 : INV
    port map (
      I => cur_length(9),
      O => Msub_cur_byte_ct_addsub0000_lut(11)
    );
  err_tlp_p_o_not00011_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_np_o,
      O => err_tlp_p_o_not0001
    );
  cur_locked_or00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => d_i(57),
      I1 => d_i(56),
      I2 => d_i(61),
      I3 => d_i(59),
      I4 => d_i(60),
      I5 => d_i(58),
      O => cur_locked_or00001_25505
    );
  cur_locked_or00002 : LUT6
    generic map(
      INIT => X"0000010000004100"
    )
    port map (
      I0 => d_i(60),
      I1 => d_i(59),
      I2 => d_i(57),
      I3 => d_i(56),
      I4 => d_i(58),
      I5 => d_i(61),
      O => cur_locked_or00002_25506
    );
  cur_locked_or0000_f7 : MUXF7
    port map (
      I0 => cur_locked_or00002_25506,
      I1 => cur_locked_or00001_25505,
      S => d_i(62),
      O => cur_locked_or0000
    );
  Madd_cur_bytes_missing_addsub0000_cy_1_111 : LUT5
    generic map(
      INIT => X"10101000"
    )
    port map (
      I0 => d_i(6),
      I1 => d_i(7),
      I2 => first_be_missing(1),
      I3 => d_i(4),
      I4 => d_i(5),
      O => Madd_cur_bytes_missing_addsub0000_cy_1_11
    );
  Madd_cur_bytes_missing_addsub0000_cy_1_112 : LUT6
    generic map(
      INIT => X"ABABABAA02020200"
    )
    port map (
      I0 => first_be_missing(1),
      I1 => d_i(6),
      I2 => d_i(7),
      I3 => d_i(4),
      I4 => d_i(5),
      I5 => first_be_missing(0),
      O => Madd_cur_bytes_missing_addsub0000_cy_1_111_25160
    );
  Madd_cur_bytes_missing_addsub0000_cy_1_11_f7 : MUXF7
    port map (
      I0 => Madd_cur_bytes_missing_addsub0000_cy_1_111_25160,
      I1 => Madd_cur_bytes_missing_addsub0000_cy_1_11,
      S => Madd_cur_bytes_missing_addsub0000_lut(0),
      O => Madd_cur_bytes_missing_index0000
    );
  dsc_o_mux00001 : LUT5
    generic map(
      INIT => X"EA404040"
    )
    port map (
      I0 => remove_lastword_26071,
      I1 => eof_q_6_Q,
      I2 => cur_drop_25443,
      I3 => N3,
      I4 => eof_q_5_Q,
      O => dsc_o_mux00001_25897
    );
  dsc_o_mux00002 : LUT5
    generic map(
      INIT => X"EA404040"
    )
    port map (
      I0 => remove_lastword_26071,
      I1 => eof_q_5_Q,
      I2 => cur_drop_25443,
      I3 => N3,
      I4 => eof_q_4_Q,
      O => dsc_o_mux00002_25898
    );
  dsc_o_mux0000_f7 : MUXF7
    port map (
      I0 => dsc_o_mux00002_25898,
      I1 => dsc_o_mux00001_25897,
      S => rhit_bar_lat3_i,
      O => dsc_o_mux0000
    );
  Mshreg_eof_nd_q_4 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => NlwRenamedSig_OI_bar_o(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => eof_nd_q_1_Q,
      Q => Mshreg_eof_nd_q_4_25227,
      Q15 => NLW_Mshreg_eof_nd_q_4_Q15_UNCONNECTED
    );
  eof_nd_q_4 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_eof_nd_q_4_25227,
      Q => eof_nd_q_4_Q
    );
  Mshreg_eof_q_3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_bar_o(2),
      A1 => NlwRenamedSig_OI_bar_o(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => eof_q_1_Q,
      Q => Mshreg_eof_q_3_25228,
      Q15 => NLW_Mshreg_eof_q_3_Q15_UNCONNECTED
    );
  eof_q_3 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_eof_q_3_25228,
      Q => eof_q_3_Q
    );
  Mshreg_src_rdy_q_4 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => NlwRenamedSig_OI_bar_o(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => src_rdy_q_1_Q,
      Q => Mshreg_src_rdy_q_4_25231,
      Q15 => NLW_Mshreg_src_rdy_q_4_Q15_UNCONNECTED
    );
  src_rdy_q_4 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_src_rdy_q_4_25231,
      Q => src_rdy_q_4_Q
    );
  Mshreg_sof_q_5 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_bar_o(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => sof_q_1_Q,
      Q => Mshreg_sof_q_5_25230,
      Q15 => NLW_Mshreg_sof_q_5_Q15_UNCONNECTED
    );
  sof_q_5 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_sof_q_5_25230,
      Q => sof_q_5_Q
    );
  Mshreg_d_q5_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(0),
      Q => Mshreg_d_q5_0_25163,
      Q15 => NLW_Mshreg_d_q5_0_Q15_UNCONNECTED
    );
  d_q5_0 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_0_25163,
      Q => d_q5(0)
    );
  Mshreg_d_q5_1 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(1),
      Q => Mshreg_d_q5_1_25164,
      Q15 => NLW_Mshreg_d_q5_1_Q15_UNCONNECTED
    );
  d_q5_1 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_1_25164,
      Q => d_q5(1)
    );
  Mshreg_d_q5_2 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(2),
      Q => Mshreg_d_q5_2_25175,
      Q15 => NLW_Mshreg_d_q5_2_Q15_UNCONNECTED
    );
  d_q5_2 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_2_25175,
      Q => d_q5(2)
    );
  Mshreg_d_q5_3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(3),
      Q => Mshreg_d_q5_3_25186,
      Q15 => NLW_Mshreg_d_q5_3_Q15_UNCONNECTED
    );
  d_q5_3 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_3_25186,
      Q => d_q5(3)
    );
  Mshreg_d_q5_4 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(4),
      Q => Mshreg_d_q5_4_25197,
      Q15 => NLW_Mshreg_d_q5_4_Q15_UNCONNECTED
    );
  d_q5_4 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_4_25197,
      Q => d_q5(4)
    );
  Mshreg_d_q5_7 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(7),
      Q => Mshreg_d_q5_7_25224,
      Q15 => NLW_Mshreg_d_q5_7_Q15_UNCONNECTED
    );
  d_q5_7 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_7_25224,
      Q => d_q5(7)
    );
  Mshreg_d_q5_5 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(5),
      Q => Mshreg_d_q5_5_25208,
      Q15 => NLW_Mshreg_d_q5_5_Q15_UNCONNECTED
    );
  d_q5_5 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_5_25208,
      Q => d_q5(5)
    );
  Mshreg_d_q5_6 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(6),
      Q => Mshreg_d_q5_6_25219,
      Q15 => NLW_Mshreg_d_q5_6_Q15_UNCONNECTED
    );
  d_q5_6 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_6_25219,
      Q => d_q5(6)
    );
  Mshreg_d_q5_8 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(8),
      Q => Mshreg_d_q5_8_25225,
      Q15 => NLW_Mshreg_d_q5_8_Q15_UNCONNECTED
    );
  d_q5_8 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_8_25225,
      Q => d_q5(8)
    );
  Mshreg_d_q5_9 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(9),
      Q => Mshreg_d_q5_9_25226,
      Q15 => NLW_Mshreg_d_q5_9_Q15_UNCONNECTED
    );
  d_q5_9 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_9_25226,
      Q => d_q5(9)
    );
  Mshreg_d_q5_10 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(10),
      Q => Mshreg_d_q5_10_25165,
      Q15 => NLW_Mshreg_d_q5_10_Q15_UNCONNECTED
    );
  d_q5_10 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_10_25165,
      Q => d_q5(10)
    );
  Mshreg_d_q5_11 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(11),
      Q => Mshreg_d_q5_11_25166,
      Q15 => NLW_Mshreg_d_q5_11_Q15_UNCONNECTED
    );
  d_q5_11 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_11_25166,
      Q => d_q5(11)
    );
  Mshreg_d_q5_12 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(12),
      Q => Mshreg_d_q5_12_25167,
      Q15 => NLW_Mshreg_d_q5_12_Q15_UNCONNECTED
    );
  d_q5_12 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_12_25167,
      Q => d_q5(12)
    );
  Mshreg_d_q5_13 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(13),
      Q => Mshreg_d_q5_13_25168,
      Q15 => NLW_Mshreg_d_q5_13_Q15_UNCONNECTED
    );
  d_q5_13 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_13_25168,
      Q => d_q5(13)
    );
  Mshreg_d_q5_16 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(16),
      Q => Mshreg_d_q5_16_25171,
      Q15 => NLW_Mshreg_d_q5_16_Q15_UNCONNECTED
    );
  d_q5_16 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_16_25171,
      Q => d_q5(16)
    );
  Mshreg_d_q5_14 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(14),
      Q => Mshreg_d_q5_14_25169,
      Q15 => NLW_Mshreg_d_q5_14_Q15_UNCONNECTED
    );
  d_q5_14 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_14_25169,
      Q => d_q5(14)
    );
  Mshreg_d_q5_15 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(15),
      Q => Mshreg_d_q5_15_25170,
      Q15 => NLW_Mshreg_d_q5_15_Q15_UNCONNECTED
    );
  d_q5_15 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_15_25170,
      Q => d_q5(15)
    );
  Mshreg_d_q5_17 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(17),
      Q => Mshreg_d_q5_17_25172,
      Q15 => NLW_Mshreg_d_q5_17_Q15_UNCONNECTED
    );
  d_q5_17 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_17_25172,
      Q => d_q5(17)
    );
  Mshreg_d_q5_18 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(18),
      Q => Mshreg_d_q5_18_25173,
      Q15 => NLW_Mshreg_d_q5_18_Q15_UNCONNECTED
    );
  d_q5_18 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_18_25173,
      Q => d_q5(18)
    );
  Mshreg_d_q5_19 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(19),
      Q => Mshreg_d_q5_19_25174,
      Q15 => NLW_Mshreg_d_q5_19_Q15_UNCONNECTED
    );
  d_q5_19 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_19_25174,
      Q => d_q5(19)
    );
  Mshreg_d_q5_20 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(20),
      Q => Mshreg_d_q5_20_25176,
      Q15 => NLW_Mshreg_d_q5_20_Q15_UNCONNECTED
    );
  d_q5_20 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_20_25176,
      Q => d_q5(20)
    );
  Mshreg_d_q5_21 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(21),
      Q => Mshreg_d_q5_21_25177,
      Q15 => NLW_Mshreg_d_q5_21_Q15_UNCONNECTED
    );
  d_q5_21 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_21_25177,
      Q => d_q5(21)
    );
  Mshreg_d_q5_22 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(22),
      Q => Mshreg_d_q5_22_25178,
      Q15 => NLW_Mshreg_d_q5_22_Q15_UNCONNECTED
    );
  d_q5_22 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_22_25178,
      Q => d_q5(22)
    );
  Mshreg_d_q5_23 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(23),
      Q => Mshreg_d_q5_23_25179,
      Q15 => NLW_Mshreg_d_q5_23_Q15_UNCONNECTED
    );
  d_q5_23 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_23_25179,
      Q => d_q5(23)
    );
  Mshreg_d_q5_24 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(24),
      Q => Mshreg_d_q5_24_25180,
      Q15 => NLW_Mshreg_d_q5_24_Q15_UNCONNECTED
    );
  d_q5_24 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_24_25180,
      Q => d_q5(24)
    );
  Mshreg_d_q5_25 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(25),
      Q => Mshreg_d_q5_25_25181,
      Q15 => NLW_Mshreg_d_q5_25_Q15_UNCONNECTED
    );
  d_q5_25 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_25_25181,
      Q => d_q5(25)
    );
  Mshreg_d_q5_26 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(26),
      Q => Mshreg_d_q5_26_25182,
      Q15 => NLW_Mshreg_d_q5_26_Q15_UNCONNECTED
    );
  d_q5_26 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_26_25182,
      Q => d_q5(26)
    );
  Mshreg_d_q5_27 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(27),
      Q => Mshreg_d_q5_27_25183,
      Q15 => NLW_Mshreg_d_q5_27_Q15_UNCONNECTED
    );
  d_q5_27 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_27_25183,
      Q => d_q5(27)
    );
  Mshreg_d_q5_28 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(28),
      Q => Mshreg_d_q5_28_25184,
      Q15 => NLW_Mshreg_d_q5_28_Q15_UNCONNECTED
    );
  d_q5_28 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_28_25184,
      Q => d_q5(28)
    );
  Mshreg_d_q5_29 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(29),
      Q => Mshreg_d_q5_29_25185,
      Q15 => NLW_Mshreg_d_q5_29_Q15_UNCONNECTED
    );
  d_q5_29 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_29_25185,
      Q => d_q5(29)
    );
  Mshreg_d_q5_30 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(30),
      Q => Mshreg_d_q5_30_25187,
      Q15 => NLW_Mshreg_d_q5_30_Q15_UNCONNECTED
    );
  d_q5_30 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_30_25187,
      Q => d_q5(30)
    );
  Mshreg_d_q5_33 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(33),
      Q => Mshreg_d_q5_33_25190,
      Q15 => NLW_Mshreg_d_q5_33_Q15_UNCONNECTED
    );
  d_q5_33 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_33_25190,
      Q => d_q5(33)
    );
  Mshreg_d_q5_31 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(31),
      Q => Mshreg_d_q5_31_25188,
      Q15 => NLW_Mshreg_d_q5_31_Q15_UNCONNECTED
    );
  d_q5_31 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_31_25188,
      Q => d_q5(31)
    );
  Mshreg_d_q5_32 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(32),
      Q => Mshreg_d_q5_32_25189,
      Q15 => NLW_Mshreg_d_q5_32_Q15_UNCONNECTED
    );
  d_q5_32 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_32_25189,
      Q => d_q5(32)
    );
  Mshreg_d_q5_34 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(34),
      Q => Mshreg_d_q5_34_25191,
      Q15 => NLW_Mshreg_d_q5_34_Q15_UNCONNECTED
    );
  d_q5_34 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_34_25191,
      Q => d_q5(34)
    );
  Mshreg_d_q5_35 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(35),
      Q => Mshreg_d_q5_35_25192,
      Q15 => NLW_Mshreg_d_q5_35_Q15_UNCONNECTED
    );
  d_q5_35 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_35_25192,
      Q => d_q5(35)
    );
  Mshreg_d_q5_36 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(36),
      Q => Mshreg_d_q5_36_25193,
      Q15 => NLW_Mshreg_d_q5_36_Q15_UNCONNECTED
    );
  d_q5_36 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_36_25193,
      Q => d_q5(36)
    );
  Mshreg_d_q5_37 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(37),
      Q => Mshreg_d_q5_37_25194,
      Q15 => NLW_Mshreg_d_q5_37_Q15_UNCONNECTED
    );
  d_q5_37 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_37_25194,
      Q => d_q5(37)
    );
  Mshreg_d_q5_38 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(38),
      Q => Mshreg_d_q5_38_25195,
      Q15 => NLW_Mshreg_d_q5_38_Q15_UNCONNECTED
    );
  d_q5_38 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_38_25195,
      Q => d_q5(38)
    );
  Mshreg_d_q5_39 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(39),
      Q => Mshreg_d_q5_39_25196,
      Q15 => NLW_Mshreg_d_q5_39_Q15_UNCONNECTED
    );
  d_q5_39 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_39_25196,
      Q => d_q5(39)
    );
  Mshreg_d_q5_40 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(40),
      Q => Mshreg_d_q5_40_25198,
      Q15 => NLW_Mshreg_d_q5_40_Q15_UNCONNECTED
    );
  d_q5_40 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_40_25198,
      Q => d_q5(40)
    );
  Mshreg_d_q5_41 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(41),
      Q => Mshreg_d_q5_41_25199,
      Q15 => NLW_Mshreg_d_q5_41_Q15_UNCONNECTED
    );
  d_q5_41 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_41_25199,
      Q => d_q5(41)
    );
  Mshreg_d_q5_42 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(42),
      Q => Mshreg_d_q5_42_25200,
      Q15 => NLW_Mshreg_d_q5_42_Q15_UNCONNECTED
    );
  d_q5_42 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_42_25200,
      Q => d_q5(42)
    );
  Mshreg_d_q5_43 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(43),
      Q => Mshreg_d_q5_43_25201,
      Q15 => NLW_Mshreg_d_q5_43_Q15_UNCONNECTED
    );
  d_q5_43 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_43_25201,
      Q => d_q5(43)
    );
  Mshreg_d_q5_44 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(44),
      Q => Mshreg_d_q5_44_25202,
      Q15 => NLW_Mshreg_d_q5_44_Q15_UNCONNECTED
    );
  d_q5_44 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_44_25202,
      Q => d_q5(44)
    );
  Mshreg_d_q5_45 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(45),
      Q => Mshreg_d_q5_45_25203,
      Q15 => NLW_Mshreg_d_q5_45_Q15_UNCONNECTED
    );
  d_q5_45 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_45_25203,
      Q => d_q5(45)
    );
  Mshreg_d_q5_46 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(46),
      Q => Mshreg_d_q5_46_25204,
      Q15 => NLW_Mshreg_d_q5_46_Q15_UNCONNECTED
    );
  d_q5_46 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_46_25204,
      Q => d_q5(46)
    );
  Mshreg_d_q5_47 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_bar_o(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_q1(47),
      Q => Mshreg_d_q5_47_25205,
      Q15 => NLW_Mshreg_d_q5_47_Q15_UNCONNECTED
    );
  d_q5_47 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_47_25205,
      Q => d_q5(47)
    );
  Mshreg_d_q5_50 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(50),
      Q => Mshreg_d_q5_50_25209,
      Q15 => NLW_Mshreg_d_q5_50_Q15_UNCONNECTED
    );
  d_q5_50 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_50_25209,
      Q => d_q5(50)
    );
  Mshreg_d_q5_48 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(48),
      Q => Mshreg_d_q5_48_25206,
      Q15 => NLW_Mshreg_d_q5_48_Q15_UNCONNECTED
    );
  d_q5_48 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_48_25206,
      Q => d_q5(48)
    );
  Mshreg_d_q5_49 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(49),
      Q => Mshreg_d_q5_49_25207,
      Q15 => NLW_Mshreg_d_q5_49_Q15_UNCONNECTED
    );
  d_q5_49 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_49_25207,
      Q => d_q5(49)
    );
  Mshreg_d_q5_51 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(51),
      Q => Mshreg_d_q5_51_25210,
      Q15 => NLW_Mshreg_d_q5_51_Q15_UNCONNECTED
    );
  d_q5_51 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_51_25210,
      Q => d_q5(51)
    );
  Mshreg_d_q5_52 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(52),
      Q => Mshreg_d_q5_52_25211,
      Q15 => NLW_Mshreg_d_q5_52_Q15_UNCONNECTED
    );
  d_q5_52 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_52_25211,
      Q => d_q5(52)
    );
  Mshreg_d_q5_53 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(53),
      Q => Mshreg_d_q5_53_25212,
      Q15 => NLW_Mshreg_d_q5_53_Q15_UNCONNECTED
    );
  d_q5_53 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_53_25212,
      Q => d_q5(53)
    );
  Mshreg_d_q5_54 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(54),
      Q => Mshreg_d_q5_54_25213,
      Q15 => NLW_Mshreg_d_q5_54_Q15_UNCONNECTED
    );
  d_q5_54 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_54_25213,
      Q => d_q5(54)
    );
  Mshreg_d_q5_55 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(55),
      Q => Mshreg_d_q5_55_25214,
      Q15 => NLW_Mshreg_d_q5_55_Q15_UNCONNECTED
    );
  d_q5_55 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_55_25214,
      Q => d_q5(55)
    );
  Mshreg_d_q5_56 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(56),
      Q => Mshreg_d_q5_56_25215,
      Q15 => NLW_Mshreg_d_q5_56_Q15_UNCONNECTED
    );
  d_q5_56 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_56_25215,
      Q => d_q5(56)
    );
  Mshreg_d_q5_57 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(57),
      Q => Mshreg_d_q5_57_25216,
      Q15 => NLW_Mshreg_d_q5_57_Q15_UNCONNECTED
    );
  d_q5_57 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_57_25216,
      Q => d_q5(57)
    );
  Mshreg_d_q5_58 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(58),
      Q => Mshreg_d_q5_58_25217,
      Q15 => NLW_Mshreg_d_q5_58_Q15_UNCONNECTED
    );
  d_q5_58 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_58_25217,
      Q => d_q5(58)
    );
  Mshreg_d_q5_59 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(59),
      Q => Mshreg_d_q5_59_25218,
      Q15 => NLW_Mshreg_d_q5_59_Q15_UNCONNECTED
    );
  d_q5_59 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_59_25218,
      Q => d_q5(59)
    );
  Mshreg_d_q5_60 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(60),
      Q => Mshreg_d_q5_60_25220,
      Q15 => NLW_Mshreg_d_q5_60_Q15_UNCONNECTED
    );
  d_q5_60 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_60_25220,
      Q => d_q5(60)
    );
  Mshreg_d_q5_61 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(61),
      Q => Mshreg_d_q5_61_25221,
      Q15 => NLW_Mshreg_d_q5_61_Q15_UNCONNECTED
    );
  d_q5_61 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_61_25221,
      Q => d_q5(61)
    );
  Mshreg_d_q5_62 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(62),
      Q => Mshreg_d_q5_62_25222,
      Q15 => NLW_Mshreg_d_q5_62_Q15_UNCONNECTED
    );
  d_q5_62 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_62_25222,
      Q => d_q5(62)
    );
  Mshreg_d_q5_63 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => out_d1(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => d_i(63),
      Q => Mshreg_d_q5_63_25223,
      Q15 => NLW_Mshreg_d_q5_63_Q15_UNCONNECTED
    );
  d_q5_63 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_d_q5_63_25223,
      Q => d_q5(63)
    );
  Mshreg_rem_q_4 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => out_d1(2),
      A1 => NlwRenamedSig_OI_bar_o(2),
      A2 => NlwRenamedSig_OI_bar_o(2),
      A3 => NlwRenamedSig_OI_bar_o(2),
      CE => out_d1(2),
      CLK => clk_i,
      D => rem_q_1_Q,
      Q => Mshreg_rem_q_4_25229,
      Q15 => NLW_Mshreg_rem_q_4_Q15_UNCONNECTED
    );
  rem_q_4 : FDE
    port map (
      C => clk_i,
      CE => out_d1(2),
      D => Mshreg_rem_q_4_25229,
      Q => rem_q_4_Q
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll_arb is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    llk_rx_dst_cont_req_n : out STD_LOGIC; 
    trn_rnp_ok_n : in STD_LOGIC := 'X'; 
    fifo_pcpl_ok : in STD_LOGIC := 'X'; 
    fifo_np_ok : in STD_LOGIC := 'X'; 
    llk_rx_dst_req_n : out STD_LOGIC; 
    llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    fifo_pcpl_req : out STD_LOGIC; 
    fifo_np_req : out STD_LOGIC; 
    cpl_tlp_cntr_inc : in STD_LOGIC := 'X'; 
    llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cpl_tlp_cntr : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end pcie_blk_ll_arb;

architecture STRUCTURE of pcie_blk_ll_arb is
  signal Mcount_cpl_tlp_rcntr_cy_1_rt_24495 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_cy_2_rt_24497 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p1_cy_1_rt_24501 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p1_cy_2_rt_24503 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p1_xor_3_rt_24505 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p2_cy_1_rt_24508 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p2_cy_2_rt_24510 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_p2_xor_3_rt_24512 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_xor_3_rt_24513 : STD_LOGIC; 
  signal Mmux_COND_90_3_24514 : STD_LOGIC; 
  signal Mmux_COND_90_4_24515 : STD_LOGIC; 
  signal Mmux_COND_91_3_24516 : STD_LOGIC; 
  signal Mmux_COND_91_4_24517 : STD_LOGIC; 
  signal Mmux_COND_92_3_24518 : STD_LOGIC; 
  signal Mmux_COND_92_4_24519 : STD_LOGIC; 
  signal Mmux_COND_93_3_24520 : STD_LOGIC; 
  signal Mmux_COND_93_4_24521 : STD_LOGIC; 
  signal Mmux_llk_rx_ch_fifo_int_mux0000_3_24522 : STD_LOGIC; 
  signal Mmux_llk_rx_ch_fifo_int_mux0000_31_24523 : STD_LOGIC; 
  signal Mmux_llk_rx_ch_fifo_int_mux0000_4_24524 : STD_LOGIC; 
  signal Mmux_llk_rx_ch_fifo_int_mux0000_41_24525 : STD_LOGIC; 
  signal Mmux_posted_avail_mux0000_3_24526 : STD_LOGIC; 
  signal Mmux_posted_avail_mux0000_4_24527 : STD_LOGIC; 
  signal Mmux_preferred_avail_mux0000_3_24528 : STD_LOGIC; 
  signal Mmux_preferred_avail_mux0000_4_24529 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N41 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_0_2 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_1_2 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_2_2 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_3_2 : STD_LOGIC; 
  signal Q_COND_90 : STD_LOGIC; 
  signal Q_COND_91 : STD_LOGIC; 
  signal Q_COND_92 : STD_LOGIC; 
  signal Q_COND_93 : STD_LOGIC; 
  signal any_available_24559 : STD_LOGIC; 
  signal any_available_d_24560 : STD_LOGIC; 
  signal any_available_or0000_24561 : STD_LOGIC; 
  signal completion_available_24579 : STD_LOGIC; 
  signal completion_available_cmp_eq0000 : STD_LOGIC; 
  signal completion_available_cmp_eq0001 : STD_LOGIC; 
  signal completion_available_cmp_eq0001_INV : STD_LOGIC; 
  signal completion_available_or0000 : STD_LOGIC; 
  signal cpl_avail_24584 : STD_LOGIC; 
  signal cpl_avail_and0000 : STD_LOGIC; 
  signal cpl_avail_not0001 : STD_LOGIC; 
  signal cpl_tlp_rcntr_and0000 : STD_LOGIC; 
  signal current_completion_available_n_d_24604 : STD_LOGIC; 
  signal current_completion_available_n_d_mux0000 : STD_LOGIC; 
  signal current_non_posted_available_n_d_24606 : STD_LOGIC; 
  signal current_posted_available_n_d_24607 : STD_LOGIC; 
  signal fifo_pcpl_ok_final_24611 : STD_LOGIC; 
  signal fifo_pcpl_ok_final_mux0000 : STD_LOGIC; 
  signal fifo_pcpl_ok_final_not0001 : STD_LOGIC; 
  signal final_xfer : STD_LOGIC; 
  signal force_service_pnp_queues_24615 : STD_LOGIC; 
  signal force_streaming_24616 : STD_LOGIC; 
  signal high_mask_1_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_2_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_3_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_4_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_5_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_6_cmp_lt0000 : STD_LOGIC; 
  signal high_mask_7_cmp_lt0000 : STD_LOGIC; 
  signal last_completion_24632 : STD_LOGIC; 
  signal last_completion_mux0000 : STD_LOGIC; 
  signal last_completion_mux00002_24634 : STD_LOGIC; 
  signal last_completion_mux000061_24635 : STD_LOGIC; 
  signal last_completion_not0001 : STD_LOGIC; 
  signal llk_rx_ch_completion_available_n_d_24645 : STD_LOGIC; 
  signal llk_rx_ch_non_posted_available_n_d_24660 : STD_LOGIC; 
  signal llk_rx_ch_posted_available_n_d_24669 : STD_LOGIC; 
  signal llk_rx_ch_tc_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_llk_rx_dst_cont_req_n : STD_LOGIC; 
  signal NlwRenamedSig_OI_llk_rx_dst_req_n : STD_LOGIC; 
  signal next_tc_avail_high_24698 : STD_LOGIC; 
  signal next_tc_avail_high_pre_24699 : STD_LOGIC; 
  signal next_tc_high_pre_and0002 : STD_LOGIC; 
  signal next_tc_high_pre_and0003 : STD_LOGIC; 
  signal next_tc_high_pre_and0004 : STD_LOGIC; 
  signal next_tc_high_pre_and0005 : STD_LOGIC; 
  signal next_tc_high_pre_and0006 : STD_LOGIC; 
  signal next_tc_is_same_lock_24711 : STD_LOGIC; 
  signal next_tc_is_same_lock_and0000 : STD_LOGIC; 
  signal next_tc_is_same_rdy_24713 : STD_LOGIC; 
  signal next_tc_is_same_rdy_and0000 : STD_LOGIC; 
  signal next_tc_is_same_rdy_cmp_eq0000 : STD_LOGIC; 
  signal pnp_waiting_24725 : STD_LOGIC; 
  signal pnp_waiting_or0000 : STD_LOGIC; 
  signal posted_avail_24727 : STD_LOGIC; 
  signal posted_avail_and0000 : STD_LOGIC; 
  signal posted_avail_and0001 : STD_LOGIC; 
  signal posted_avail_and0002 : STD_LOGIC; 
  signal posted_avail_and0003 : STD_LOGIC; 
  signal posted_avail_and0004 : STD_LOGIC; 
  signal posted_avail_and0005 : STD_LOGIC; 
  signal posted_avail_and0006 : STD_LOGIC; 
  signal posted_avail_and0007 : STD_LOGIC; 
  signal posted_avail_mux0000 : STD_LOGIC; 
  signal preferred_alt_mux0000_1_1_24739 : STD_LOGIC; 
  signal preferred_alt_mux0000_1_2_24740 : STD_LOGIC; 
  signal preferred_avail_24741 : STD_LOGIC; 
  signal preferred_avail_and0000 : STD_LOGIC; 
  signal preferred_avail_and0001 : STD_LOGIC; 
  signal preferred_avail_and0002 : STD_LOGIC; 
  signal preferred_avail_and0003 : STD_LOGIC; 
  signal preferred_avail_and0004 : STD_LOGIC; 
  signal preferred_avail_and0005 : STD_LOGIC; 
  signal preferred_avail_and0006 : STD_LOGIC; 
  signal preferred_avail_and0007 : STD_LOGIC; 
  signal preferred_avail_and00071_24750 : STD_LOGIC; 
  signal preferred_avail_and00072_24751 : STD_LOGIC; 
  signal preferred_avail_chosen_24752 : STD_LOGIC; 
  signal preferred_avail_chosen_and0000 : STD_LOGIC; 
  signal preferred_avail_mux0000 : STD_LOGIC; 
  signal preferred_timer_not0001 : STD_LOGIC; 
  signal preferred_timer_or0000 : STD_LOGIC; 
  signal preferred_timer_or0001 : STD_LOGIC; 
  signal preferred_vld_24762 : STD_LOGIC; 
  signal preferred_vld_and0001 : STD_LOGIC; 
  signal preferred_vld_mux0000 : STD_LOGIC; 
  signal preferred_vld_not0001 : STD_LOGIC; 
  signal rnp_rob_0_24766 : STD_LOGIC; 
  signal rnp_rob_0_not0000 : STD_LOGIC; 
  signal rnp_rob_Sclr_inv : STD_LOGIC; 
  signal rnp_rob_and0000 : STD_LOGIC; 
  signal rnp_rr_24770 : STD_LOGIC; 
  signal rnp_rr_and0000 : STD_LOGIC; 
  signal transaction_24773 : STD_LOGIC; 
  signal transaction_and0001 : STD_LOGIC; 
  signal transaction_first_24775 : STD_LOGIC; 
  signal transaction_first_mux0000 : STD_LOGIC; 
  signal transaction_first_not0001 : STD_LOGIC; 
  signal transaction_init_cpl : STD_LOGIC; 
  signal transaction_init_cpl1_24779 : STD_LOGIC; 
  signal transaction_not0001 : STD_LOGIC; 
  signal transaction_second_24781 : STD_LOGIC; 
  signal transaction_second_not0001 : STD_LOGIC; 
  signal transaction_stream_24783 : STD_LOGIC; 
  signal transaction_third_24784 : STD_LOGIC; 
  signal transaction_third_mux0000 : STD_LOGIC; 
  signal transaction_third_or0000 : STD_LOGIC; 
  signal trigger_xfer : STD_LOGIC; 
  signal trn_rcpl_streaming_n_reg_24788 : STD_LOGIC; 
  signal Mcount_cpl_tlp_rcntr_cy : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Mcount_cpl_tlp_rcntr_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cpl_tlp_rcntr_p1_cy : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Mcount_cpl_tlp_rcntr_p1_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cpl_tlp_rcntr_p2_cy : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Mcount_cpl_tlp_rcntr_p2_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal any_queue_available : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal any_queue_available_int : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cpl_tlp_rcntr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cpl_tlp_rcntr_p1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cpl_tlp_rcntr_p2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal high_mask : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_llk_rx_ch_fifo : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal llk_rx_ch_fifo_int : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal llk_rx_ch_fifo_int_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_llk_rx_ch_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal llk_rx_preferred_type_d : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal next_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal next_tc_high : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal next_tc_high_pre : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal next_tc_low : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal next_tc_low_pre : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal next_tc_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal preferred_alt : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal preferred_alt_mux0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal preferred_timer : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal preferred_timer_mux0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  llk_rx_dst_cont_req_n <= NlwRenamedSig_OI_llk_rx_dst_cont_req_n;
  llk_rx_dst_req_n <= NlwRenamedSig_OI_llk_rx_dst_req_n;
  llk_rx_ch_fifo(1) <= NlwRenamedSig_OI_llk_rx_ch_fifo(1);
  llk_rx_ch_fifo(0) <= NlwRenamedSig_OI_llk_rx_ch_fifo(0);
  llk_rx_ch_tc(2) <= NlwRenamedSig_OI_llk_rx_ch_tc(2);
  llk_rx_ch_tc(1) <= NlwRenamedSig_OI_llk_rx_ch_tc(1);
  llk_rx_ch_tc(0) <= NlwRenamedSig_OI_llk_rx_ch_tc(0);
  XST_GND : GND
    port map (
      G => high_mask(0)
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  preferred_avail_chosen : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => final_xfer,
      D => high_mask(0),
      R => rnp_rob_Sclr_inv,
      S => preferred_avail_chosen_and0000,
      Q => preferred_avail_chosen_24752
    );
  force_streaming : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => high_mask(0),
      R => rnp_rob_Sclr_inv,
      S => transaction_init_cpl,
      Q => force_streaming_24616
    );
  next_tc_high_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_high_pre(0),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_high(0)
    );
  next_tc_high_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_high_pre(1),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_high(1)
    );
  next_tc_high_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_high_pre(2),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_high(2)
    );
  any_queue_available_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(7),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(7)
    );
  next_tc_low_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_low_pre(0),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_low(0)
    );
  next_tc_low_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_low_pre(1),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_low(1)
    );
  next_tc_low_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_low_pre(2),
      R => rnp_rob_Sclr_inv,
      Q => next_tc_low(2)
    );
  next_tc_avail_high : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_avail_high_pre_24699,
      R => rnp_rob_Sclr_inv,
      Q => next_tc_avail_high_24698
    );
  any_queue_available_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(6),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(6)
    );
  any_queue_available_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(5),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(5)
    );
  any_queue_available_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(2),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(2)
    );
  any_queue_available_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(4),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(4)
    );
  any_queue_available_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(3),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(3)
    );
  any_queue_available_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(1),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(1)
    );
  any_queue_available_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_queue_available_int(0),
      R => rnp_rob_Sclr_inv,
      Q => any_queue_available(0)
    );
  next_tc_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_mux0000(0),
      R => rnp_rob_Sclr_inv,
      Q => next_tc(0)
    );
  next_tc_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_mux0000(1),
      R => rnp_rob_Sclr_inv,
      Q => next_tc(1)
    );
  next_tc_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_mux0000(2),
      R => rnp_rob_Sclr_inv,
      Q => next_tc(2)
    );
  any_available : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_available_or0000_24561,
      R => rnp_rob_Sclr_inv,
      Q => any_available_24559
    );
  current_completion_available_n_d : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => current_completion_available_n_d_mux0000,
      Q => current_completion_available_n_d_24604
    );
  transaction : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => transaction_not0001,
      D => transaction_first_mux0000,
      R => rnp_rob_Sclr_inv,
      S => transaction_init_cpl,
      Q => transaction_24773
    );
  transaction_first : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => transaction_first_not0001,
      D => transaction_first_mux0000,
      R => rnp_rob_Sclr_inv,
      S => transaction_init_cpl,
      Q => transaction_first_24775
    );
  next_tc_is_same_lock : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_is_same_lock_and0000,
      R => rnp_rob_Sclr_inv,
      Q => next_tc_is_same_lock_24711
    );
  transaction_stream : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => transaction_not0001,
      D => high_mask(0),
      R => rnp_rob_Sclr_inv,
      S => transaction_init_cpl,
      Q => transaction_stream_24783
    );
  next_tc_is_same_rdy : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => next_tc_is_same_rdy_and0000,
      R => rnp_rob_Sclr_inv,
      Q => next_tc_is_same_rdy_24713
    );
  pnp_waiting : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => pnp_waiting_or0000,
      R => rnp_rob_Sclr_inv,
      Q => pnp_waiting_24725
    );
  last_completion : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => last_completion_not0001,
      D => last_completion_mux0000,
      S => rnp_rob_Sclr_inv,
      Q => last_completion_24632
    );
  fifo_pcpl_ok_final : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => fifo_pcpl_ok_final_not0001,
      D => fifo_pcpl_ok_final_mux0000,
      S => rnp_rob_Sclr_inv,
      Q => fifo_pcpl_ok_final_24611
    );
  trn_rcpl_streaming_n_reg : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => high_mask(0),
      S => rnp_rob_Sclr_inv,
      Q => trn_rcpl_streaming_n_reg_24788
    );
  preferred_vld : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => preferred_vld_not0001,
      D => preferred_vld_mux0000,
      S => rnp_rob_Sclr_inv,
      Q => preferred_vld_24762
    );
  preferred_timer_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => preferred_timer_not0001,
      D => preferred_timer_mux0000(0),
      S => preferred_timer_or0000,
      Q => preferred_timer(0)
    );
  preferred_timer_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => preferred_timer_not0001,
      D => preferred_timer_mux0000(1),
      S => preferred_timer_or0000,
      Q => preferred_timer(1)
    );
  transaction_second : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => transaction_second_not0001,
      D => high_mask(0),
      R => rnp_rob_Sclr_inv,
      S => preferred_vld_and0001,
      Q => transaction_second_24781
    );
  transaction_third : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => transaction_second_not0001,
      D => transaction_third_mux0000,
      R => transaction_third_or0000,
      Q => transaction_third_24784
    );
  cpl_avail : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_avail_not0001,
      D => cpl_avail_and0000,
      Q => cpl_avail_24584
    );
  llk_rx_ch_non_posted_available_n_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_ch_non_posted_available_n(0),
      R => rnp_rob_Sclr_inv,
      Q => llk_rx_ch_non_posted_available_n_d_24660
    );
  llk_rx_preferred_type_d_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_preferred_type(0),
      R => rnp_rob_Sclr_inv,
      Q => llk_rx_preferred_type_d(0)
    );
  llk_rx_preferred_type_d_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_preferred_type(1),
      R => rnp_rob_Sclr_inv,
      Q => llk_rx_preferred_type_d(1)
    );
  llk_rx_ch_posted_available_n_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_ch_posted_available_n(0),
      R => rnp_rob_Sclr_inv,
      Q => llk_rx_ch_posted_available_n_d_24669
    );
  llk_rx_ch_completion_available_n_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_ch_completion_available_n(0),
      R => rnp_rob_Sclr_inv,
      Q => llk_rx_ch_completion_available_n_d_24645
    );
  preferred_alt_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => final_xfer,
      D => preferred_alt_mux0000(1),
      R => rnp_rob_Sclr_inv,
      Q => preferred_alt(1)
    );
  rnp_rr : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => rnp_rr_and0000,
      Q => rnp_rr_24770
    );
  llk_rx_ch_tc_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => next_tc(0),
      R => llk_rx_ch_tc_or0000,
      Q => NlwRenamedSig_OI_llk_rx_ch_tc(0)
    );
  llk_rx_ch_tc_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => next_tc(1),
      R => llk_rx_ch_tc_or0000,
      Q => NlwRenamedSig_OI_llk_rx_ch_tc(1)
    );
  llk_rx_ch_tc_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => next_tc(2),
      R => llk_rx_ch_tc_or0000,
      Q => NlwRenamedSig_OI_llk_rx_ch_tc(2)
    );
  any_available_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => any_available_24559,
      R => rnp_rob_Sclr_inv,
      Q => any_available_d_24560
    );
  completion_available : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => completion_available_cmp_eq0001_INV,
      D => fifo_pcpl_ok_final_24611,
      R => completion_available_or0000,
      Q => completion_available_24579
    );
  force_service_pnp_queues : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => pnp_waiting_24725,
      R => rnp_rob_Sclr_inv,
      Q => force_service_pnp_queues_24615
    );
  llk_rx_ch_fifo_int_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => llk_rx_ch_fifo_int_mux0000(0),
      R => llk_rx_ch_tc_or0000,
      Q => llk_rx_ch_fifo_int(0)
    );
  llk_rx_ch_fifo_int_1 : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => llk_rx_ch_fifo_int_mux0000(1),
      R => rnp_rob_Sclr_inv,
      S => transaction_init_cpl1_24779,
      Q => llk_rx_ch_fifo_int(1)
    );
  preferred_avail : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => preferred_avail_mux0000,
      R => rnp_rob_Sclr_inv,
      Q => preferred_avail_24741
    );
  posted_avail : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => trigger_xfer,
      D => posted_avail_mux0000,
      R => rnp_rob_Sclr_inv,
      Q => posted_avail_24727
    );
  current_posted_available_n_d : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => Q_COND_90,
      Q => current_posted_available_n_d_24607
    );
  current_non_posted_available_n_d : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => Q_COND_91,
      Q => current_non_posted_available_n_d_24606
    );
  high_mask_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_6_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(6)
    );
  high_mask_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_7_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(7)
    );
  high_mask_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_5_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(5)
    );
  high_mask_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_4_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(4)
    );
  high_mask_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_1_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(1)
    );
  high_mask_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_3_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(3)
    );
  high_mask_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => high_mask_2_cmp_lt0000,
      R => rnp_rob_Sclr_inv,
      Q => high_mask(2)
    );
  cpl_tlp_rcntr_p2_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result(1),
      S => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p2(1)
    );
  cpl_tlp_rcntr_p2_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result(0),
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p2(0)
    );
  cpl_tlp_rcntr_p2_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result(2),
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p2(2)
    );
  cpl_tlp_rcntr_p1_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_0_2,
      S => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p1(0)
    );
  cpl_tlp_rcntr_p1_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_1_2,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p1(1)
    );
  cpl_tlp_rcntr_p1_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_2_2,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p1(2)
    );
  cpl_tlp_rcntr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_0_1,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr(0)
    );
  cpl_tlp_rcntr_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_1_1,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr(1)
    );
  cpl_tlp_rcntr_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_2_1,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr(2)
    );
  cpl_tlp_rcntr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_3_1,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr(3)
    );
  cpl_tlp_rcntr_p2_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result(3),
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p2(3)
    );
  cpl_tlp_rcntr_p1_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cpl_tlp_rcntr_and0000,
      D => Result_3_2,
      R => rnp_rob_Sclr_inv,
      Q => cpl_tlp_rcntr_p1(3)
    );
  Mmux_COND_90_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_posted_available_n(2),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_posted_available_n(1),
      I4 => llk_rx_ch_posted_available_n(0),
      I5 => llk_rx_ch_posted_available_n(3),
      O => Mmux_COND_90_4_24515
    );
  Mmux_COND_90_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_posted_available_n(6),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_posted_available_n(5),
      I4 => llk_rx_ch_posted_available_n(4),
      I5 => llk_rx_ch_posted_available_n(7),
      O => Mmux_COND_90_3_24514
    );
  Mmux_COND_93_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => any_queue_available_int(2),
      I2 => next_tc(1),
      I3 => any_queue_available_int(1),
      I4 => any_queue_available_int(0),
      I5 => any_queue_available_int(3),
      O => Mmux_COND_93_4_24521
    );
  Mmux_COND_93_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => any_queue_available_int(6),
      I2 => next_tc(1),
      I3 => any_queue_available_int(5),
      I4 => any_queue_available_int(4),
      I5 => any_queue_available_int(7),
      O => Mmux_COND_93_3_24520
    );
  Mmux_COND_91_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_non_posted_available_n(2),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_non_posted_available_n(1),
      I4 => llk_rx_ch_non_posted_available_n(0),
      I5 => llk_rx_ch_non_posted_available_n(3),
      O => Mmux_COND_91_4_24517
    );
  Mmux_COND_91_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_non_posted_available_n(6),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_non_posted_available_n(5),
      I4 => llk_rx_ch_non_posted_available_n(4),
      I5 => llk_rx_ch_non_posted_available_n(7),
      O => Mmux_COND_91_3_24516
    );
  Mmux_COND_92_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_completion_available_n(2),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_completion_available_n(1),
      I4 => llk_rx_ch_completion_available_n(0),
      I5 => llk_rx_ch_completion_available_n(3),
      O => Mmux_COND_92_4_24519
    );
  Mmux_COND_92_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I1 => llk_rx_ch_completion_available_n(6),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => llk_rx_ch_completion_available_n(5),
      I4 => llk_rx_ch_completion_available_n(4),
      I5 => llk_rx_ch_completion_available_n(7),
      O => Mmux_COND_92_3_24518
    );
  Mmux_posted_avail_mux0000_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => posted_avail_and0005,
      I2 => next_tc(1),
      I3 => posted_avail_and0006,
      I4 => posted_avail_and0007,
      I5 => posted_avail_and0004,
      O => Mmux_posted_avail_mux0000_4_24527
    );
  Mmux_posted_avail_mux0000_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => posted_avail_and0001,
      I2 => next_tc(1),
      I3 => posted_avail_and0002,
      I4 => posted_avail_and0003,
      I5 => posted_avail_and0000,
      O => Mmux_posted_avail_mux0000_3_24526
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_41 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => llk_rx_preferred_type(5),
      I2 => next_tc(1),
      I3 => llk_rx_preferred_type(3),
      I4 => llk_rx_preferred_type(1),
      I5 => llk_rx_preferred_type(7),
      O => Mmux_llk_rx_ch_fifo_int_mux0000_41_24525
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_31 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => llk_rx_preferred_type(13),
      I2 => next_tc(1),
      I3 => llk_rx_preferred_type(11),
      I4 => llk_rx_preferred_type(9),
      I5 => llk_rx_preferred_type(15),
      O => Mmux_llk_rx_ch_fifo_int_mux0000_31_24523
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => llk_rx_preferred_type(4),
      I2 => next_tc(1),
      I3 => llk_rx_preferred_type(2),
      I4 => llk_rx_preferred_type(0),
      I5 => llk_rx_preferred_type(6),
      O => Mmux_llk_rx_ch_fifo_int_mux0000_4_24524
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => llk_rx_preferred_type(12),
      I2 => next_tc(1),
      I3 => llk_rx_preferred_type(10),
      I4 => llk_rx_preferred_type(8),
      I5 => llk_rx_preferred_type(14),
      O => Mmux_llk_rx_ch_fifo_int_mux0000_3_24522
    );
  Mmux_preferred_avail_mux0000_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => preferred_avail_and0005,
      I2 => next_tc(1),
      I3 => preferred_avail_and0006,
      I4 => preferred_avail_and0007,
      I5 => preferred_avail_and0004,
      O => Mmux_preferred_avail_mux0000_4_24529
    );
  Mmux_preferred_avail_mux0000_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => next_tc(0),
      I1 => preferred_avail_and0001,
      I2 => next_tc(1),
      I3 => preferred_avail_and0002,
      I4 => preferred_avail_and0003,
      I5 => preferred_avail_and0000,
      O => Mmux_preferred_avail_mux0000_3_24528
    );
  Mcount_cpl_tlp_rcntr_p1_cy_0_Q : MUXCY
    port map (
      CI => high_mask(0),
      DI => N1,
      S => Mcount_cpl_tlp_rcntr_p1_lut(0),
      O => Mcount_cpl_tlp_rcntr_p1_cy(0)
    );
  Mcount_cpl_tlp_rcntr_p1_xor_0_Q : XORCY
    port map (
      CI => high_mask(0),
      LI => Mcount_cpl_tlp_rcntr_p1_lut(0),
      O => Result_0_2
    );
  Mcount_cpl_tlp_rcntr_p1_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p1_cy(0),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_p1_cy_1_rt_24501,
      O => Mcount_cpl_tlp_rcntr_p1_cy(1)
    );
  Mcount_cpl_tlp_rcntr_p1_xor_1_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p1_cy(0),
      LI => Mcount_cpl_tlp_rcntr_p1_cy_1_rt_24501,
      O => Result_1_2
    );
  Mcount_cpl_tlp_rcntr_p1_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p1_cy(1),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_p1_cy_2_rt_24503,
      O => Mcount_cpl_tlp_rcntr_p1_cy(2)
    );
  Mcount_cpl_tlp_rcntr_p1_xor_2_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p1_cy(1),
      LI => Mcount_cpl_tlp_rcntr_p1_cy_2_rt_24503,
      O => Result_2_2
    );
  Mcount_cpl_tlp_rcntr_p1_xor_3_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p1_cy(2),
      LI => Mcount_cpl_tlp_rcntr_p1_xor_3_rt_24505,
      O => Result_3_2
    );
  Mcount_cpl_tlp_rcntr_p2_cy_0_Q : MUXCY
    port map (
      CI => high_mask(0),
      DI => N1,
      S => Mcount_cpl_tlp_rcntr_p2_lut(0),
      O => Mcount_cpl_tlp_rcntr_p2_cy(0)
    );
  Mcount_cpl_tlp_rcntr_p2_xor_0_Q : XORCY
    port map (
      CI => high_mask(0),
      LI => Mcount_cpl_tlp_rcntr_p2_lut(0),
      O => Result(0)
    );
  Mcount_cpl_tlp_rcntr_p2_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p2_cy(0),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_p2_cy_1_rt_24508,
      O => Mcount_cpl_tlp_rcntr_p2_cy(1)
    );
  Mcount_cpl_tlp_rcntr_p2_xor_1_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p2_cy(0),
      LI => Mcount_cpl_tlp_rcntr_p2_cy_1_rt_24508,
      O => Result(1)
    );
  Mcount_cpl_tlp_rcntr_p2_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p2_cy(1),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_p2_cy_2_rt_24510,
      O => Mcount_cpl_tlp_rcntr_p2_cy(2)
    );
  Mcount_cpl_tlp_rcntr_p2_xor_2_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p2_cy(1),
      LI => Mcount_cpl_tlp_rcntr_p2_cy_2_rt_24510,
      O => Result(2)
    );
  Mcount_cpl_tlp_rcntr_p2_xor_3_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_p2_cy(2),
      LI => Mcount_cpl_tlp_rcntr_p2_xor_3_rt_24512,
      O => Result(3)
    );
  Mcount_cpl_tlp_rcntr_cy_0_Q : MUXCY
    port map (
      CI => high_mask(0),
      DI => N1,
      S => Mcount_cpl_tlp_rcntr_lut(0),
      O => Mcount_cpl_tlp_rcntr_cy(0)
    );
  Mcount_cpl_tlp_rcntr_xor_0_Q : XORCY
    port map (
      CI => high_mask(0),
      LI => Mcount_cpl_tlp_rcntr_lut(0),
      O => Result_0_1
    );
  Mcount_cpl_tlp_rcntr_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_cy(0),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_cy_1_rt_24495,
      O => Mcount_cpl_tlp_rcntr_cy(1)
    );
  Mcount_cpl_tlp_rcntr_xor_1_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_cy(0),
      LI => Mcount_cpl_tlp_rcntr_cy_1_rt_24495,
      O => Result_1_1
    );
  Mcount_cpl_tlp_rcntr_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_cy(1),
      DI => high_mask(0),
      S => Mcount_cpl_tlp_rcntr_cy_2_rt_24497,
      O => Mcount_cpl_tlp_rcntr_cy(2)
    );
  Mcount_cpl_tlp_rcntr_xor_2_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_cy(1),
      LI => Mcount_cpl_tlp_rcntr_cy_2_rt_24497,
      O => Result_2_1
    );
  Mcount_cpl_tlp_rcntr_xor_3_Q : XORCY
    port map (
      CI => Mcount_cpl_tlp_rcntr_cy(2),
      LI => Mcount_cpl_tlp_rcntr_xor_3_rt_24513,
      O => Result_3_1
    );
  rnp_rob_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => rnp_rob_and0000,
      D => rnp_rob_0_not0000,
      R => rnp_rob_Sclr_inv,
      Q => rnp_rob_0_24766
    );
  pnp_waiting_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(0),
      I1 => llk_rx_ch_non_posted_available_n(0),
      O => pnp_waiting_or0000
    );
  fifo_pcpl_ok_final_mux00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => llk_rx_src_last_req_n,
      O => fifo_pcpl_ok_final_mux0000
    );
  cpl_avail_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_completion_available_n(0),
      I1 => fifo_pcpl_ok,
      O => cpl_avail_and0000
    );
  rnp_rr_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => llk_rx_preferred_type(0),
      I1 => llk_rx_ch_completion_available_n(0),
      I2 => llk_rx_ch_posted_available_n(0),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(0),
      I5 => llk_rx_preferred_type(1),
      O => rnp_rr_and0000
    );
  fifo_pcpl_ok_final_not00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => llk_rx_src_last_req_n,
      I1 => fifo_pcpl_ok,
      O => fifo_pcpl_ok_final_not0001
    );
  high_mask_6_cmp_lt00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => high_mask_6_cmp_lt0000
    );
  high_mask_2_cmp_lt00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      O => high_mask_2_cmp_lt0000
    );
  high_mask_7_cmp_lt00001 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      O => high_mask_7_cmp_lt0000
    );
  high_mask_5_cmp_lt00001 : LUT3
    generic map(
      INIT => X"57"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      O => high_mask_5_cmp_lt0000
    );
  high_mask_3_cmp_lt00001 : LUT3
    generic map(
      INIT => X"15"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      O => high_mask_3_cmp_lt0000
    );
  high_mask_1_cmp_lt00001 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      O => high_mask_1_cmp_lt0000
    );
  next_tc_mux0000_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => next_tc_avail_high_24698,
      I1 => next_tc_low(2),
      I2 => next_tc_high(2),
      O => next_tc_mux0000(2)
    );
  next_tc_mux0000_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => next_tc_avail_high_24698,
      I1 => next_tc_low(1),
      I2 => next_tc_high(1),
      O => next_tc_mux0000(1)
    );
  next_tc_mux0000_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => next_tc_avail_high_24698,
      I1 => next_tc_low(0),
      I2 => next_tc_high(0),
      O => next_tc_mux0000(0)
    );
  posted_avail_and00071 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(0),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0007
    );
  rnp_rob_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_src_last_req_n,
      I1 => rnp_rr_24770,
      O => rnp_rob_and0000
    );
  preferred_timer_not00011 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => transaction_third_24784,
      I1 => transaction_24773,
      I2 => preferred_timer(0),
      I3 => preferred_timer(1),
      O => preferred_timer_not0001
    );
  transaction_second_not00011 : LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
    port map (
      I0 => preferred_timer(1),
      I1 => preferred_timer(0),
      I2 => transaction_third_24784,
      I3 => transaction_24773,
      I4 => transaction_second_24781,
      O => transaction_second_not0001
    );
  preferred_avail_and00041 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(6),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(3),
      I5 => llk_rx_ch_posted_available_n(3),
      O => preferred_avail_and0004
    );
  preferred_avail_and00001 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(14),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(7),
      I5 => llk_rx_ch_posted_available_n(7),
      O => preferred_avail_and0000
    );
  next_tc_is_same_lock_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => preferred_vld_24762,
      I1 => next_tc_is_same_rdy_cmp_eq0000,
      O => next_tc_is_same_lock_and0000
    );
  preferred_vld_mux00001 : LUT5
    generic map(
      INIT => X"00010101"
    )
    port map (
      I0 => preferred_timer(1),
      I1 => preferred_vld_and0001,
      I2 => transaction_second_24781,
      I3 => transaction_24773,
      I4 => transaction_third_24784,
      O => preferred_vld_mux0000
    );
  next_tc_is_same_rdy_cmp_eq000031 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => next_tc(0),
      I1 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I2 => next_tc(1),
      I3 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I4 => next_tc(2),
      I5 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => next_tc_is_same_rdy_cmp_eq0000
    );
  any_available_or0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => any_queue_available(2),
      I1 => any_queue_available(1),
      I2 => any_queue_available(0),
      O => N32
    );
  any_available_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => any_queue_available(7),
      I1 => any_queue_available(6),
      I2 => any_queue_available(5),
      I3 => any_queue_available(4),
      I4 => any_queue_available(3),
      I5 => N32,
      O => any_available_or0000_24561
    );
  next_tc_low_pre_2_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => any_queue_available(3),
      I1 => any_queue_available(2),
      I2 => any_queue_available(1),
      I3 => any_queue_available(0),
      O => N34
    );
  next_tc_low_pre_2_Q : LUT6
    generic map(
      INIT => X"5555555555555554"
    )
    port map (
      I0 => N34,
      I1 => any_queue_available(7),
      I2 => any_queue_available(6),
      I3 => any_queue_available(5),
      I4 => any_queue_available(4),
      I5 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => next_tc_low_pre(2)
    );
  preferred_avail_and00031 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(8),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(4),
      I5 => llk_rx_ch_posted_available_n(4),
      O => preferred_avail_and0003
    );
  preferred_avail_chosen_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => transaction_first_24775,
      I1 => preferred_avail_24741,
      O => preferred_avail_chosen_and0000
    );
  preferred_avail_and00061 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(2),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(1),
      I5 => llk_rx_ch_posted_available_n(1),
      O => preferred_avail_and0006
    );
  preferred_avail_and00021 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(10),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(5),
      I5 => llk_rx_ch_posted_available_n(5),
      O => preferred_avail_and0002
    );
  trigger_xfer1 : LUT4
    generic map(
      INIT => X"5F4C"
    )
    port map (
      I0 => llk_rx_src_last_req_n,
      I1 => any_available_d_24560,
      I2 => transaction_24773,
      I3 => next_tc_is_same_rdy_24713,
      O => trigger_xfer
    );
  transaction_and00011 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => transaction_first_24775,
      I1 => preferred_avail_24741,
      I2 => posted_avail_24727,
      I3 => cpl_avail_24584,
      I4 => transaction_stream_24783,
      O => transaction_and0001
    );
  preferred_vld_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
    port map (
      I0 => preferred_timer(0),
      I1 => preferred_vld_and0001,
      I2 => transaction_third_24784,
      I3 => transaction_24773,
      I4 => preferred_timer(1),
      I5 => transaction_second_24781,
      O => preferred_vld_not0001
    );
  next_tc_high_pre_and00021 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => high_mask(3),
      I1 => any_queue_available(3),
      O => next_tc_high_pre_and0002
    );
  next_tc_high_pre_2_Q : LUT6
    generic map(
      INIT => X"5555555555555554"
    )
    port map (
      I0 => N41,
      I1 => next_tc_high_pre_and0006,
      I2 => next_tc_high_pre_and0005,
      I3 => next_tc_high_pre_and0004,
      I4 => next_tc_high_pre_and0003,
      I5 => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => next_tc_high_pre(2)
    );
  preferred_avail_and00051 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(4),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(2),
      I5 => llk_rx_ch_posted_available_n(2),
      O => preferred_avail_and0005
    );
  next_tc_avail_high_pre_SW0 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => high_mask(2),
      I1 => any_queue_available(2),
      I2 => high_mask(1),
      I3 => any_queue_available(1),
      O => N45
    );
  next_tc_avail_high_pre : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => next_tc_high_pre_and0006,
      I1 => next_tc_high_pre_and0005,
      I2 => next_tc_high_pre_and0004,
      I3 => next_tc_high_pre_and0003,
      I4 => next_tc_high_pre_and0002,
      I5 => N45,
      O => next_tc_avail_high_pre_24699
    );
  preferred_avail_and00011 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_preferred_type(12),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(6),
      I5 => llk_rx_ch_posted_available_n(6),
      O => preferred_avail_and0001
    );
  current_completion_available_n_d_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => trn_rcpl_streaming_n_reg_24788,
      I1 => Q_COND_92,
      O => current_completion_available_n_d_mux0000
    );
  next_tc_high_pre_and00031 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => high_mask(4),
      I1 => any_queue_available(4),
      O => next_tc_high_pre_and0003
    );
  preferred_timer_mux0000_0_1 : LUT4
    generic map(
      INIT => X"6555"
    )
    port map (
      I0 => preferred_timer(0),
      I1 => preferred_timer_or0001,
      I2 => transaction_24773,
      I3 => transaction_third_24784,
      O => preferred_timer_mux0000(0)
    );
  transaction_third_mux00001 : LUT5
    generic map(
      INIT => X"02008A88"
    )
    port map (
      I0 => transaction_24773,
      I1 => transaction_second_24781,
      I2 => preferred_timer_or0001,
      I3 => transaction_third_24784,
      I4 => transaction_stream_24783,
      O => transaction_third_mux0000
    );
  preferred_timer_or00011 : LUT5
    generic map(
      INIT => X"1015BABF"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_ch_fifo(1),
      I1 => current_non_posted_available_n_d_24606,
      I2 => NlwRenamedSig_OI_llk_rx_ch_fifo(0),
      I3 => current_posted_available_n_d_24607,
      I4 => current_completion_available_n_d_24604,
      O => preferred_timer_or0001
    );
  preferred_timer_mux0000_1_1 : LUT5
    generic map(
      INIT => X"A5A5E1A5"
    )
    port map (
      I0 => preferred_timer(0),
      I1 => transaction_third_24784,
      I2 => preferred_timer(1),
      I3 => transaction_24773,
      I4 => preferred_timer_or0001,
      O => preferred_timer_mux0000(1)
    );
  posted_avail_and00041 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(3),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0004
    );
  posted_avail_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(7),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0000
    );
  any_queue_available_int_0_or00011 : LUT6
    generic map(
      INIT => X"2A222A22FFFF2A22"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => llk_rx_ch_posted_available_n(0),
      I2 => llk_rx_ch_completion_available_n(0),
      I3 => trn_rcpl_streaming_n_reg_24788,
      I4 => fifo_np_ok,
      I5 => llk_rx_ch_non_posted_available_n(0),
      O => any_queue_available_int(0)
    );
  preferred_timer_or00001 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => transaction_second_24781,
      I1 => rst_n,
      I2 => preferred_vld_and0001,
      O => preferred_timer_or0000
    );
  transaction_init_cpl1 : LUT5
    generic map(
      INIT => X"00022222"
    )
    port map (
      I0 => completion_available_24579,
      I1 => trn_rcpl_streaming_n_reg_24788,
      I2 => llk_rx_src_last_req_n,
      I3 => last_completion_24632,
      I4 => transaction_24773,
      O => transaction_init_cpl
    );
  preferred_vld_and00011 : LUT5
    generic map(
      INIT => X"CCCCCCC8"
    )
    port map (
      I0 => cpl_avail_24584,
      I1 => transaction_first_24775,
      I2 => posted_avail_24727,
      I3 => preferred_avail_24741,
      I4 => transaction_stream_24783,
      O => preferred_vld_and0001
    );
  posted_avail_and00031 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(4),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0003
    );
  posted_avail_and00061 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(1),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0006
    );
  posted_avail_and00021 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(5),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0002
    );
  next_tc_high_pre_and00041 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => high_mask(5),
      I1 => any_queue_available(5),
      O => next_tc_high_pre_and0004
    );
  llk_rx_ch_fifo_0_1 : LUT4
    generic map(
      INIT => X"CCC8"
    )
    port map (
      I0 => force_streaming_24616,
      I1 => llk_rx_ch_fifo_int(0),
      I2 => preferred_avail_24741,
      I3 => preferred_avail_chosen_24752,
      O => NlwRenamedSig_OI_llk_rx_ch_fifo(0)
    );
  last_completion_mux00002 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => force_service_pnp_queues_24615,
      O => last_completion_mux00002_24634
    );
  last_completion_mux000061 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => cpl_tlp_cntr(1),
      I1 => cpl_tlp_rcntr_p2(1),
      I2 => cpl_tlp_cntr(2),
      I3 => cpl_tlp_rcntr_p2(2),
      I4 => cpl_tlp_cntr(3),
      I5 => cpl_tlp_rcntr_p2(3),
      O => last_completion_mux000061_24635
    );
  posted_avail_and00051 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(2),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0005
    );
  posted_avail_and00011 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n(6),
      I1 => fifo_pcpl_ok,
      O => posted_avail_and0001
    );
  next_tc_is_same_rdy_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => next_tc_is_same_rdy_cmp_eq0000,
      I1 => Q_COND_93,
      O => next_tc_is_same_rdy_and0000
    );
  next_tc_high_pre_and00051 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => high_mask(6),
      I1 => any_queue_available(6),
      O => next_tc_high_pre_and0005
    );
  llk_rx_dst_cont_req_n1 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => last_completion_24632,
      I1 => transaction_24773,
      I2 => NlwRenamedSig_OI_llk_rx_ch_fifo(1),
      I3 => trn_rcpl_streaming_n_reg_24788,
      O => NlwRenamedSig_OI_llk_rx_dst_cont_req_n
    );
  completion_available_or00001 : LUT6
    generic map(
      INIT => X"FFF88F88FFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_dst_cont_req_n,
      I1 => force_service_pnp_queues_24615,
      I2 => llk_rx_src_last_req_n,
      I3 => completion_available_cmp_eq0000,
      I4 => completion_available_cmp_eq0001,
      I5 => rst_n,
      O => completion_available_or0000
    );
  completion_available_cmp_eq00014_SW0 : LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      I0 => cpl_tlp_cntr(0),
      I1 => cpl_tlp_rcntr(0),
      I2 => cpl_tlp_cntr(1),
      I3 => cpl_tlp_rcntr(1),
      O => N56
    );
  completion_available_cmp_eq00014 : LUT5
    generic map(
      INIT => X"00008421"
    )
    port map (
      I0 => cpl_tlp_rcntr(3),
      I1 => cpl_tlp_rcntr(2),
      I2 => cpl_tlp_cntr(3),
      I3 => cpl_tlp_cntr(2),
      I4 => N56,
      O => completion_available_cmp_eq0001
    );
  completion_available_cmp_eq00004_SW0 : LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      I0 => cpl_tlp_cntr(0),
      I1 => cpl_tlp_rcntr_p1(0),
      I2 => cpl_tlp_cntr(1),
      I3 => cpl_tlp_rcntr_p1(1),
      O => N58
    );
  completion_available_cmp_eq00004 : LUT5
    generic map(
      INIT => X"00008421"
    )
    port map (
      I0 => cpl_tlp_rcntr_p1(3),
      I1 => cpl_tlp_rcntr_p1(2),
      I2 => cpl_tlp_cntr(3),
      I3 => cpl_tlp_cntr(2),
      I4 => N58,
      O => completion_available_cmp_eq0000
    );
  transaction_first_not00011 : LUT6
    generic map(
      INIT => X"FFFFDDFDFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_rx_dst_req_n,
      I1 => transaction_and0001,
      I2 => next_tc_is_same_lock_24711,
      I3 => transaction_24773,
      I4 => trigger_xfer,
      I5 => llk_rx_src_last_req_n,
      O => transaction_first_not0001
    );
  next_tc_high_pre_and00061 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => high_mask(7),
      I1 => any_queue_available(7),
      O => next_tc_high_pre_and0006
    );
  llk_rx_ch_fifo_1_1 : LUT6
    generic map(
      INIT => X"CCCDCCC8CCC8CCC8"
    )
    port map (
      I0 => preferred_avail_chosen_24752,
      I1 => llk_rx_ch_fifo_int(1),
      I2 => preferred_avail_24741,
      I3 => force_streaming_24616,
      I4 => preferred_alt(1),
      I5 => high_mask(0),
      O => NlwRenamedSig_OI_llk_rx_ch_fifo(1)
    );
  Mcount_cpl_tlp_rcntr_p1_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p1(1),
      O => Mcount_cpl_tlp_rcntr_p1_cy_1_rt_24501
    );
  Mcount_cpl_tlp_rcntr_p1_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p1(2),
      O => Mcount_cpl_tlp_rcntr_p1_cy_2_rt_24503
    );
  Mcount_cpl_tlp_rcntr_p2_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p2(1),
      O => Mcount_cpl_tlp_rcntr_p2_cy_1_rt_24508
    );
  Mcount_cpl_tlp_rcntr_p2_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p2(2),
      O => Mcount_cpl_tlp_rcntr_p2_cy_2_rt_24510
    );
  Mcount_cpl_tlp_rcntr_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr(1),
      O => Mcount_cpl_tlp_rcntr_cy_1_rt_24495
    );
  Mcount_cpl_tlp_rcntr_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr(2),
      O => Mcount_cpl_tlp_rcntr_cy_2_rt_24497
    );
  Mcount_cpl_tlp_rcntr_p1_xor_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p1(3),
      O => Mcount_cpl_tlp_rcntr_p1_xor_3_rt_24505
    );
  Mcount_cpl_tlp_rcntr_p2_xor_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr_p2(3),
      O => Mcount_cpl_tlp_rcntr_p2_xor_3_rt_24512
    );
  Mcount_cpl_tlp_rcntr_xor_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cpl_tlp_rcntr(3),
      O => Mcount_cpl_tlp_rcntr_xor_3_rt_24513
    );
  Mmux_COND_90_2_f7 : MUXF7
    port map (
      I0 => Mmux_COND_90_4_24515,
      I1 => Mmux_COND_90_3_24514,
      S => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => Q_COND_90
    );
  Mmux_COND_91_2_f7 : MUXF7
    port map (
      I0 => Mmux_COND_91_4_24517,
      I1 => Mmux_COND_91_3_24516,
      S => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => Q_COND_91
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_2_f7_0 : MUXF7
    port map (
      I0 => Mmux_llk_rx_ch_fifo_int_mux0000_41_24525,
      I1 => Mmux_llk_rx_ch_fifo_int_mux0000_31_24523,
      S => next_tc(2),
      O => llk_rx_ch_fifo_int_mux0000(1)
    );
  Mmux_COND_92_2_f7 : MUXF7
    port map (
      I0 => Mmux_COND_92_4_24519,
      I1 => Mmux_COND_92_3_24518,
      S => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => Q_COND_92
    );
  Mmux_llk_rx_ch_fifo_int_mux0000_2_f7 : MUXF7
    port map (
      I0 => Mmux_llk_rx_ch_fifo_int_mux0000_4_24524,
      I1 => Mmux_llk_rx_ch_fifo_int_mux0000_3_24522,
      S => next_tc(2),
      O => llk_rx_ch_fifo_int_mux0000(0)
    );
  Mmux_posted_avail_mux0000_2_f7 : MUXF7
    port map (
      I0 => Mmux_posted_avail_mux0000_4_24527,
      I1 => Mmux_posted_avail_mux0000_3_24526,
      S => next_tc(2),
      O => posted_avail_mux0000
    );
  Mmux_COND_93_2_f7 : MUXF7
    port map (
      I0 => Mmux_COND_93_4_24521,
      I1 => Mmux_COND_93_3_24520,
      S => next_tc(2),
      O => Q_COND_93
    );
  Mmux_preferred_avail_mux0000_2_f7 : MUXF7
    port map (
      I0 => Mmux_preferred_avail_mux0000_4_24529,
      I1 => Mmux_preferred_avail_mux0000_3_24528,
      S => next_tc(2),
      O => preferred_avail_mux0000
    );
  last_completion_mux0000110 : LUT6
    generic map(
      INIT => X"FFFFFFFFD7558200"
    )
    port map (
      I0 => cpl_tlp_rcntr_and0000,
      I1 => cpl_tlp_cntr(0),
      I2 => cpl_tlp_rcntr_p2(0),
      I3 => last_completion_mux000061_24635,
      I4 => completion_available_cmp_eq0000,
      I5 => last_completion_mux00002_24634,
      O => last_completion_mux0000
    );
  next_tc_high_pre_1_SW2 : LUT6
    generic map(
      INIT => X"1111111011101110"
    )
    port map (
      I0 => next_tc_high_pre_and0003,
      I1 => next_tc_high_pre_and0004,
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => next_tc_high_pre_and0005,
      I4 => any_queue_available(7),
      I5 => high_mask(7),
      O => N0
    );
  next_tc_high_pre_1_Q : LUT6
    generic map(
      INIT => X"3F3F3F3F3F2A2A2A"
    )
    port map (
      I0 => next_tc_high_pre_and0002,
      I1 => any_queue_available(1),
      I2 => high_mask(1),
      I3 => any_queue_available(2),
      I4 => high_mask(2),
      I5 => N0,
      O => next_tc_high_pre(1)
    );
  next_tc_high_pre_0_SW2 : LUT6
    generic map(
      INIT => X"5555555511551050"
    )
    port map (
      I0 => next_tc_high_pre_and0003,
      I1 => any_queue_available(6),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I3 => high_mask(6),
      I4 => next_tc_high_pre_and0006,
      I5 => next_tc_high_pre_and0004,
      O => N2
    );
  next_tc_high_pre_0_Q : LUT6
    generic map(
      INIT => X"F333F222FFFFFAAA"
    )
    port map (
      I0 => N2,
      I1 => any_queue_available(2),
      I2 => high_mask(1),
      I3 => any_queue_available(1),
      I4 => next_tc_high_pre_and0002,
      I5 => high_mask(2),
      O => next_tc_high_pre(0)
    );
  next_tc_low_pre_1_SW2 : LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      I0 => any_queue_available(6),
      I1 => any_queue_available(7),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(1),
      I3 => any_queue_available(4),
      O => N4
    );
  next_tc_low_pre_1_Q : LUT6
    generic map(
      INIT => X"1111111110101011"
    )
    port map (
      I0 => any_queue_available(0),
      I1 => any_queue_available(1),
      I2 => any_queue_available(2),
      I3 => any_queue_available(5),
      I4 => N4,
      I5 => any_queue_available(3),
      O => next_tc_low_pre(1)
    );
  next_tc_low_pre_0_SW2 : LUT4
    generic map(
      INIT => X"5501"
    )
    port map (
      I0 => any_queue_available(5),
      I1 => any_queue_available(7),
      I2 => NlwRenamedSig_OI_llk_rx_ch_tc(0),
      I3 => any_queue_available(6),
      O => N6
    );
  next_tc_low_pre_0_Q : LUT6
    generic map(
      INIT => X"2322232223222323"
    )
    port map (
      I0 => any_queue_available(1),
      I1 => any_queue_available(0),
      I2 => any_queue_available(2),
      I3 => any_queue_available(3),
      I4 => any_queue_available(4),
      I5 => N6,
      O => next_tc_low_pre(0)
    );
  transaction_first_mux00001 : LUT6
    generic map(
      INIT => X"0011001000550050"
    )
    port map (
      I0 => transaction_and0001,
      I1 => transaction_24773,
      I2 => any_available_d_24560,
      I3 => next_tc_is_same_lock_24711,
      I4 => next_tc_is_same_rdy_24713,
      I5 => llk_rx_src_last_req_n,
      O => transaction_first_mux0000
    );
  transaction_not00011 : LUT6
    generic map(
      INIT => X"BFBFBFBFBFBFBFBB"
    )
    port map (
      I0 => transaction_and0001,
      I1 => llk_rx_src_last_req_n,
      I2 => transaction_24773,
      I3 => next_tc_is_same_lock_24711,
      I4 => any_available_d_24560,
      I5 => next_tc_is_same_rdy_24713,
      O => transaction_not0001
    );
  fifo_np_req1 : LUT5
    generic map(
      INIT => X"C0C0C080"
    )
    port map (
      I0 => force_streaming_24616,
      I1 => transaction_first_24775,
      I2 => llk_rx_ch_fifo_int(0),
      I3 => preferred_avail_24741,
      I4 => preferred_avail_chosen_24752,
      O => fifo_np_req
    );
  cpl_avail_not00011 : LUT5
    generic map(
      INIT => X"50F040C0"
    )
    port map (
      I0 => llk_rx_src_last_req_n,
      I1 => any_available_d_24560,
      I2 => rst_n,
      I3 => transaction_24773,
      I4 => next_tc_is_same_rdy_24713,
      O => cpl_avail_not0001
    );
  next_tc_high_pre_2_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => high_mask(2),
      I1 => any_queue_available(2),
      I2 => high_mask(3),
      I3 => any_queue_available(3),
      I4 => high_mask(1),
      I5 => any_queue_available(1),
      O => N41
    );
  any_queue_available_int_3_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(3),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(3),
      O => any_queue_available_int(3)
    );
  any_queue_available_int_7_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(7),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(7),
      O => any_queue_available_int(7)
    );
  transaction_third_or00001 : LUT6
    generic map(
      INIT => X"CCCCCCC8FFFFFFFF"
    )
    port map (
      I0 => transaction_stream_24783,
      I1 => transaction_first_24775,
      I2 => cpl_avail_24584,
      I3 => posted_avail_24727,
      I4 => preferred_avail_24741,
      I5 => rst_n,
      O => transaction_third_or0000
    );
  transaction_init_cpl11 : LUT6
    generic map(
      INIT => X"0000004040404040"
    )
    port map (
      I0 => trn_rcpl_streaming_n_reg_24788,
      I1 => completion_available_24579,
      I2 => rst_n,
      I3 => llk_rx_src_last_req_n,
      I4 => last_completion_24632,
      I5 => transaction_24773,
      O => transaction_init_cpl1_24779
    );
  llk_rx_ch_tc_or00001 : LUT6
    generic map(
      INIT => X"00022222FFFFFFFF"
    )
    port map (
      I0 => completion_available_24579,
      I1 => trn_rcpl_streaming_n_reg_24788,
      I2 => last_completion_24632,
      I3 => llk_rx_src_last_req_n,
      I4 => transaction_24773,
      I5 => rst_n,
      O => llk_rx_ch_tc_or0000
    );
  any_queue_available_int_4_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(4),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(4),
      O => any_queue_available_int(4)
    );
  completion_available_cmp_eq0001_INV1 : LUT5
    generic map(
      INIT => X"FFFF6FF6"
    )
    port map (
      I0 => cpl_tlp_cntr(2),
      I1 => cpl_tlp_rcntr(2),
      I2 => cpl_tlp_cntr(3),
      I3 => cpl_tlp_rcntr(3),
      I4 => N56,
      O => completion_available_cmp_eq0001_INV
    );
  last_completion_not00011 : LUT6
    generic map(
      INIT => X"FF02FF02FF02FF22"
    )
    port map (
      I0 => completion_available_24579,
      I1 => trn_rcpl_streaming_n_reg_24788,
      I2 => transaction_24773,
      I3 => cpl_tlp_rcntr_and0000,
      I4 => last_completion_24632,
      I5 => llk_rx_src_last_req_n,
      O => last_completion_not0001
    );
  any_queue_available_int_1_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(1),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(1),
      O => any_queue_available_int(1)
    );
  any_queue_available_int_5_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(5),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(5),
      O => any_queue_available_int(5)
    );
  any_queue_available_int_2_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(2),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(2),
      O => any_queue_available_int(2)
    );
  any_queue_available_int_6_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => fifo_np_ok,
      I1 => llk_rx_ch_non_posted_available_n(6),
      I2 => fifo_pcpl_ok,
      I3 => llk_rx_ch_posted_available_n(6),
      O => any_queue_available_int(6)
    );
  cpl_tlp_rcntr_and00001 : LUT6
    generic map(
      INIT => X"000A000A000A0008"
    )
    port map (
      I0 => llk_rx_ch_fifo_int(1),
      I1 => force_streaming_24616,
      I2 => llk_rx_src_last_req_n,
      I3 => llk_rx_ch_fifo_int(0),
      I4 => preferred_avail_24741,
      I5 => preferred_avail_chosen_24752,
      O => cpl_tlp_rcntr_and0000
    );
  llk_rx_dst_req_n_13494 : MUXF7
    port map (
      I0 => N10,
      I1 => N11,
      S => llk_rx_src_last_req_n,
      O => NlwRenamedSig_OI_llk_rx_dst_req_n
    );
  llk_rx_dst_req_n_F : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => trn_rcpl_streaming_n_reg_24788,
      I1 => transaction_24773,
      I2 => NlwRenamedSig_OI_llk_rx_ch_fifo(1),
      I3 => last_completion_24632,
      O => N10
    );
  llk_rx_dst_req_n_G : LUT6
    generic map(
      INIT => X"00040105FFFFFFFF"
    )
    port map (
      I0 => posted_avail_24727,
      I1 => trn_rcpl_streaming_n_reg_24788,
      I2 => preferred_avail_24741,
      I3 => cpl_avail_24584,
      I4 => NlwRenamedSig_OI_llk_rx_ch_fifo(1),
      I5 => transaction_24773,
      O => N11
    );
  Mcount_cpl_tlp_rcntr_p1_lut_0_INV_0 : INV
    port map (
      I => cpl_tlp_rcntr_p1(0),
      O => Mcount_cpl_tlp_rcntr_p1_lut(0)
    );
  Mcount_cpl_tlp_rcntr_p2_lut_0_INV_0 : INV
    port map (
      I => cpl_tlp_rcntr_p2(0),
      O => Mcount_cpl_tlp_rcntr_p2_lut(0)
    );
  Mcount_cpl_tlp_rcntr_lut_0_INV_0 : INV
    port map (
      I => cpl_tlp_rcntr(0),
      O => Mcount_cpl_tlp_rcntr_lut(0)
    );
  final_xfer1_INV_0 : INV
    port map (
      I => llk_rx_src_last_req_n,
      O => final_xfer
    );
  rnp_rob_0_not00001_INV_0 : INV
    port map (
      I => rnp_rob_0_24766,
      O => rnp_rob_0_not0000
    );
  high_mask_4_cmp_lt00001_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_llk_rx_ch_tc(2),
      O => high_mask_4_cmp_lt0000
    );
  rnp_rob_Sclr_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rnp_rob_Sclr_inv
    );
  preferred_alt_mux0000_1_1 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => llk_rx_preferred_type_d(0),
      I1 => llk_rx_preferred_type_d(1),
      I2 => llk_rx_ch_non_posted_available_n_d_24660,
      I3 => llk_rx_ch_completion_available_n_d_24645,
      I4 => fifo_np_ok,
      O => preferred_alt_mux0000_1_1_24739
    );
  preferred_alt_mux0000_1_2 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => llk_rx_ch_posted_available_n_d_24669,
      I1 => llk_rx_preferred_type_d(0),
      I2 => llk_rx_preferred_type_d(1),
      I3 => llk_rx_ch_non_posted_available_n_d_24660,
      I4 => llk_rx_ch_completion_available_n_d_24645,
      I5 => fifo_np_ok,
      O => preferred_alt_mux0000_1_2_24740
    );
  preferred_alt_mux0000_1_f7 : MUXF7
    port map (
      I0 => preferred_alt_mux0000_1_2_24740,
      I1 => preferred_alt_mux0000_1_1_24739,
      S => rnp_rob_0_24766,
      O => preferred_alt_mux0000(1)
    );
  preferred_avail_and00071 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => fifo_pcpl_ok,
      I1 => preferred_vld_24762,
      I2 => llk_rx_ch_completion_available_n(0),
      O => preferred_avail_and00071_24750
    );
  preferred_avail_and00072 : LUT6
    generic map(
      INIT => X"0000800008088808"
    )
    port map (
      I0 => preferred_vld_24762,
      I1 => fifo_pcpl_ok,
      I2 => llk_rx_preferred_type(0),
      I3 => fifo_np_ok,
      I4 => llk_rx_ch_non_posted_available_n(0),
      I5 => llk_rx_ch_posted_available_n(0),
      O => preferred_avail_and00072_24751
    );
  preferred_avail_and0007_f7 : MUXF7
    port map (
      I0 => preferred_avail_and00072_24751,
      I1 => preferred_avail_and00071_24750,
      S => llk_rx_preferred_type(1),
      O => preferred_avail_and0007
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cmm_decoder is
  port (
    clk : in STD_LOGIC := 'X'; 
    cmmt_rbar_hit_lat2_n : out STD_LOGIC; 
    rcheck_bus_id : in STD_LOGIC := 'X'; 
    phantom_functions_enabled : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    rmem32 : in STD_LOGIC := 'X'; 
    rmem64 : in STD_LOGIC := 'X'; 
    rcheck_dev_id : in STD_LOGIC := 'X'; 
    rcheck_fun_id : in STD_LOGIC := 'X'; 
    rhit : out STD_LOGIC; 
    rio : in STD_LOGIC := 'X'; 
    bar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    bar4_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bar0_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    phantom_functions_supported : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    xrom_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bar5_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bar1_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    bar2_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bus_num : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    raddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pme_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    bar3_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    device_num : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
    cfg : in STD_LOGIC_VECTOR ( 671 downto 0 ); 
    function_num : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end cmm_decoder;

architecture STRUCTURE of cmm_decoder is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal bar01_64_hit_high_24278 : STD_LOGIC; 
  signal bar01_64_hit_high_and0000 : STD_LOGIC; 
  signal bar01_64_hit_high_cmp_eq0000 : STD_LOGIC; 
  signal bar01_64_hit_low_24281 : STD_LOGIC; 
  signal bar01_64_hit_low_and0000 : STD_LOGIC; 
  signal bar01_64_hit_low_cmp_eq0000 : STD_LOGIC; 
  signal bar0_32_hit_nc_24284 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000133_24286 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000169_24287 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000245_24288 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000249_24289 : STD_LOGIC; 
  signal bar0_32_hit_nc_and0000267_24290 : STD_LOGIC; 
  signal bar0_32_hit_nc_and00004_24291 : STD_LOGIC; 
  signal bar0_32_hit_nc_and000040_24292 : STD_LOGIC; 
  signal bar0_32_hit_nc_and000076_24293 : STD_LOGIC; 
  signal bar0_eq_raddr_24294 : STD_LOGIC; 
  signal bar0_eq_raddr_cmp_eq0000 : STD_LOGIC; 
  signal bar1_32_hit_nc_24327 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000133_24329 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000169_24330 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000245_24331 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000249_24332 : STD_LOGIC; 
  signal bar1_32_hit_nc_and0000314_24333 : STD_LOGIC; 
  signal bar1_32_hit_nc_and000040_24334 : STD_LOGIC; 
  signal bar1_32_hit_nc_and000076_24335 : STD_LOGIC; 
  signal bar1_eq_raddr_24336 : STD_LOGIC; 
  signal bar1_eq_raddr_cmp_eq0000 : STD_LOGIC; 
  signal bar6_32_hit : STD_LOGIC; 
  signal bar6_32_hit_nc_24403 : STD_LOGIC; 
  signal bar6_32_hit_nc_and0000 : STD_LOGIC; 
  signal bar6_eq_raddr_24405 : STD_LOGIC; 
  signal bar6_eq_raddr_cmp_eq0000 : STD_LOGIC; 
  signal bar_hit_0_or0000 : STD_LOGIC; 
  signal bar_hit_1_or0000 : STD_LOGIC; 
  signal bdf_check_24413 : STD_LOGIC; 
  signal bdf_check_or0000 : STD_LOGIC; 
  signal bdf_hit_24415 : STD_LOGIC; 
  signal bdf_hit_and0000 : STD_LOGIC; 
  signal bdf_hit_cmp_eq0000 : STD_LOGIC; 
  signal rhit_or0000_24467 : STD_LOGIC; 
  signal Mcompar_bar01_64_hit_high_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcompar_bar01_64_hit_high_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcompar_bar01_64_hit_low_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcompar_bar01_64_hit_low_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_bar0_eq_raddr_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcompar_bar0_eq_raddr_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcompar_bar1_eq_raddr_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcompar_bar1_eq_raddr_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcompar_bar6_eq_raddr_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Mcompar_bar6_eq_raddr_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcompar_bdf_hit_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Mcompar_bdf_hit_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal NlwRenamedSig_OI_bar_hit : STD_LOGIC_VECTOR ( 2 downto 2 ); 
begin
  cmmt_rbar_hit_lat2_n <= NlwRenamedSig_OI_bar_hit(2);
  bar_hit(5) <= NlwRenamedSig_OI_bar_hit(2);
  bar_hit(4) <= NlwRenamedSig_OI_bar_hit(2);
  bar_hit(3) <= NlwRenamedSig_OI_bar_hit(2);
  bar_hit(2) <= NlwRenamedSig_OI_bar_hit(2);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_bar_hit(2)
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  bar1_32_hit_nc : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar1_32_hit_nc_and0000,
      Q => bar1_32_hit_nc_24327
    );
  bar0_32_hit_nc : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar0_32_hit_nc_and0000,
      Q => bar0_32_hit_nc_24284
    );
  bar6_32_hit_nc : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar6_32_hit_nc_and0000,
      Q => bar6_32_hit_nc_24403
    );
  bar01_64_hit_low : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar01_64_hit_low_and0000,
      Q => bar01_64_hit_low_24281
    );
  bar01_64_hit_high : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar01_64_hit_high_and0000,
      Q => bar01_64_hit_high_24278
    );
  bdf_hit : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bdf_hit_and0000,
      Q => bdf_hit_24415
    );
  bar_hit_6 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar6_32_hit,
      Q => bar_hit(6)
    );
  bdf_check : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bdf_check_or0000,
      Q => bdf_check_24413
    );
  rhit_13148 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => rhit_or0000_24467,
      Q => rhit
    );
  bar_hit_1 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar_hit_1_or0000,
      Q => bar_hit(1)
    );
  bar_hit_0 : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar_hit_0_or0000,
      Q => bar_hit(0)
    );
  bar0_eq_raddr : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar0_eq_raddr_cmp_eq0000,
      Q => bar0_eq_raddr_24294
    );
  bar1_eq_raddr : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar1_eq_raddr_cmp_eq0000,
      Q => bar1_eq_raddr_24336
    );
  bar6_eq_raddr : FDC
    port map (
      C => clk,
      CLR => rst,
      D => bar6_eq_raddr_cmp_eq0000,
      Q => bar6_eq_raddr_24405
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => xrom_reg(11),
      I1 => xrom_reg(12),
      I2 => xrom_reg(13),
      I3 => xrom_reg(14),
      I4 => xrom_reg(15),
      I5 => xrom_reg(16),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(0)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(0),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(0)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_1_Q : LUT5
    generic map(
      INIT => X"01000001"
    )
    port map (
      I0 => xrom_reg(17),
      I1 => xrom_reg(18),
      I2 => xrom_reg(19),
      I3 => raddr(52),
      I4 => xrom_reg(20),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(1)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(1),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(1)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_2_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(53),
      I1 => xrom_reg(21),
      I2 => raddr(54),
      I3 => xrom_reg(22),
      I4 => raddr(55),
      I5 => xrom_reg(23),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(2)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(2),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(2)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(56),
      I1 => xrom_reg(24),
      I2 => raddr(57),
      I3 => xrom_reg(25),
      I4 => raddr(58),
      I5 => xrom_reg(26),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(3)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(3),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(3)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(59),
      I1 => xrom_reg(27),
      I2 => raddr(60),
      I3 => xrom_reg(28),
      I4 => raddr(61),
      I5 => xrom_reg(29),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(4)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(4),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(4)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_lut_5_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => raddr(62),
      I1 => xrom_reg(30),
      I2 => raddr(63),
      I3 => xrom_reg(31),
      O => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(5)
    );
  Mcompar_bar6_eq_raddr_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_bar6_eq_raddr_cmp_eq0000_cy(4),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar6_eq_raddr_cmp_eq0000_lut(5),
      O => bar6_eq_raddr_cmp_eq0000
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar0_reg(4),
      I1 => bar0_reg(5),
      I2 => bar0_reg(6),
      I3 => bar0_reg(7),
      I4 => bar0_reg(8),
      I5 => bar0_reg(9),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(0)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(0),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(0)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar0_reg(10),
      I1 => bar0_reg(11),
      I2 => bar0_reg(12),
      I3 => bar0_reg(13),
      I4 => bar0_reg(14),
      I5 => bar0_reg(15),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(1)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(1),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(1)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_2_Q : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => bar0_reg(16),
      I1 => bar0_reg(17),
      I2 => bar0_reg(18),
      I3 => bar0_reg(19),
      I4 => bar0_reg(20),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(2)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(2),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(2)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(53),
      I1 => bar0_reg(21),
      I2 => raddr(54),
      I3 => bar0_reg(22),
      I4 => raddr(55),
      I5 => bar0_reg(23),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(3)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(3),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(3)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(56),
      I1 => bar0_reg(24),
      I2 => raddr(57),
      I3 => bar0_reg(25),
      I4 => raddr(58),
      I5 => bar0_reg(26),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(4)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(4),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(4)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_5_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(59),
      I1 => bar0_reg(27),
      I2 => raddr(60),
      I3 => bar0_reg(28),
      I4 => raddr(61),
      I5 => bar0_reg(29),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(5)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(4),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(5),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(5)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_lut_6_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => raddr(62),
      I1 => bar0_reg(30),
      I2 => raddr(63),
      I3 => bar0_reg(31),
      O => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(6)
    );
  Mcompar_bar0_eq_raddr_cmp_eq0000_cy_6_Q : MUXCY
    port map (
      CI => Mcompar_bar0_eq_raddr_cmp_eq0000_cy(5),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar0_eq_raddr_cmp_eq0000_lut(6),
      O => bar0_eq_raddr_cmp_eq0000
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(4),
      I1 => bar1_reg(5),
      I2 => bar1_reg(6),
      I3 => bar1_reg(7),
      I4 => bar1_reg(8),
      I5 => bar1_reg(9),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(0)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(0),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(0)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(10),
      I1 => bar1_reg(11),
      I2 => bar1_reg(12),
      I3 => bar1_reg(13),
      I4 => bar1_reg(14),
      I5 => bar1_reg(15),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(1)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(1),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(1)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_2_Q : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => bar1_reg(16),
      I1 => bar1_reg(17),
      I2 => bar1_reg(18),
      I3 => bar1_reg(19),
      I4 => bar1_reg(20),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(2)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(2),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(2)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(53),
      I1 => bar1_reg(21),
      I2 => raddr(54),
      I3 => bar1_reg(22),
      I4 => raddr(55),
      I5 => bar1_reg(23),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(3)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(3),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(3)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(56),
      I1 => bar1_reg(24),
      I2 => raddr(57),
      I3 => bar1_reg(25),
      I4 => raddr(58),
      I5 => bar1_reg(26),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(4)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(4),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(4)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_5_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(59),
      I1 => bar1_reg(27),
      I2 => raddr(60),
      I3 => bar1_reg(28),
      I4 => raddr(61),
      I5 => bar1_reg(29),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(5)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(4),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(5),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(5)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_lut_6_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => raddr(62),
      I1 => bar1_reg(30),
      I2 => raddr(63),
      I3 => bar1_reg(31),
      O => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(6)
    );
  Mcompar_bar1_eq_raddr_cmp_eq0000_cy_6_Q : MUXCY
    port map (
      CI => Mcompar_bar1_eq_raddr_cmp_eq0000_cy(5),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar1_eq_raddr_cmp_eq0000_lut(6),
      O => bar1_eq_raddr_cmp_eq0000
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(0),
      I1 => bar1_reg(1),
      I2 => bar1_reg(2),
      I3 => bar1_reg(3),
      I4 => bar1_reg(4),
      I5 => bar1_reg(5),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(0)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(0),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(0)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(6),
      I1 => bar1_reg(7),
      I2 => bar1_reg(8),
      I3 => bar1_reg(9),
      I4 => bar1_reg(10),
      I5 => bar1_reg(11),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(1)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(1),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(1)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_2_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(12),
      I1 => bar1_reg(13),
      I2 => bar1_reg(14),
      I3 => bar1_reg(15),
      I4 => bar1_reg(16),
      I5 => bar1_reg(17),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(2)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(2),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(2)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_3_Q : LUT5
    generic map(
      INIT => X"01000001"
    )
    port map (
      I0 => bar1_reg(18),
      I1 => bar1_reg(19),
      I2 => bar1_reg(20),
      I3 => raddr(53),
      I4 => bar1_reg(21),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(3)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(3),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(3)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(54),
      I1 => bar1_reg(22),
      I2 => raddr(55),
      I3 => bar1_reg(23),
      I4 => raddr(56),
      I5 => bar1_reg(24),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(4)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(4),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(4)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_5_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(57),
      I1 => bar1_reg(25),
      I2 => raddr(58),
      I3 => bar1_reg(26),
      I4 => raddr(59),
      I5 => bar1_reg(27),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(5)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(4),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(5),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(5)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_6_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(60),
      I1 => bar1_reg(28),
      I2 => raddr(61),
      I3 => bar1_reg(29),
      I4 => raddr(62),
      I5 => bar1_reg(30),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(6)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_6_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(5),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(6),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(6)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_lut_7_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => raddr(63),
      I1 => bar1_reg(31),
      O => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(7)
    );
  Mcompar_bar01_64_hit_low_cmp_eq0000_cy_7_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_low_cmp_eq0000_cy(6),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_low_cmp_eq0000_lut(7),
      O => bar01_64_hit_low_cmp_eq0000
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar0_reg(4),
      I1 => bar0_reg(5),
      I2 => bar0_reg(6),
      I3 => bar0_reg(7),
      I4 => bar0_reg(8),
      I5 => bar0_reg(9),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(0)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(0),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(0)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar0_reg(10),
      I1 => bar0_reg(11),
      I2 => bar0_reg(12),
      I3 => bar0_reg(13),
      I4 => bar0_reg(14),
      I5 => bar0_reg(15),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(1)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(1),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(1)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_2_Q : LUT5
    generic map(
      INIT => X"00000001"
    )
    port map (
      I0 => bar0_reg(16),
      I1 => bar0_reg(17),
      I2 => bar0_reg(18),
      I3 => bar0_reg(19),
      I4 => bar0_reg(20),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(2)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(2),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(2)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(21),
      I1 => bar0_reg(21),
      I2 => raddr(22),
      I3 => bar0_reg(22),
      I4 => raddr(23),
      I5 => bar0_reg(23),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(3)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(3),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(3)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(24),
      I1 => bar0_reg(24),
      I2 => raddr(25),
      I3 => bar0_reg(25),
      I4 => raddr(26),
      I5 => bar0_reg(26),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(4)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(4),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(4)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_5_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => raddr(27),
      I1 => bar0_reg(27),
      I2 => raddr(28),
      I3 => bar0_reg(28),
      I4 => raddr(29),
      I5 => bar0_reg(29),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(5)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(4),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(5),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(5)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_lut_6_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => raddr(30),
      I1 => bar0_reg(30),
      I2 => raddr(31),
      I3 => bar0_reg(31),
      O => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(6)
    );
  Mcompar_bar01_64_hit_high_cmp_eq0000_cy_6_Q : MUXCY
    port map (
      CI => Mcompar_bar01_64_hit_high_cmp_eq0000_cy(5),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bar01_64_hit_high_cmp_eq0000_lut(6),
      O => bar01_64_hit_high_cmp_eq0000
    );
  Mcompar_bdf_hit_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => device_num(0),
      I1 => raddr(51),
      I2 => device_num(1),
      I3 => raddr(52),
      I4 => device_num(2),
      I5 => raddr(53),
      O => Mcompar_bdf_hit_cmp_eq0000_lut(0)
    );
  Mcompar_bdf_hit_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bdf_hit_cmp_eq0000_lut(0),
      O => Mcompar_bdf_hit_cmp_eq0000_cy(0)
    );
  Mcompar_bdf_hit_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => device_num(3),
      I1 => raddr(54),
      I2 => device_num(4),
      I3 => raddr(55),
      I4 => bus_num(0),
      I5 => raddr(56),
      O => Mcompar_bdf_hit_cmp_eq0000_lut(1)
    );
  Mcompar_bdf_hit_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_bdf_hit_cmp_eq0000_cy(0),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bdf_hit_cmp_eq0000_lut(1),
      O => Mcompar_bdf_hit_cmp_eq0000_cy(1)
    );
  Mcompar_bdf_hit_cmp_eq0000_lut_2_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => bus_num(1),
      I1 => raddr(57),
      I2 => bus_num(2),
      I3 => raddr(58),
      I4 => bus_num(3),
      I5 => raddr(59),
      O => Mcompar_bdf_hit_cmp_eq0000_lut(2)
    );
  Mcompar_bdf_hit_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_bdf_hit_cmp_eq0000_cy(1),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bdf_hit_cmp_eq0000_lut(2),
      O => Mcompar_bdf_hit_cmp_eq0000_cy(2)
    );
  Mcompar_bdf_hit_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => bus_num(4),
      I1 => raddr(60),
      I2 => bus_num(5),
      I3 => raddr(61),
      I4 => bus_num(6),
      I5 => raddr(62),
      O => Mcompar_bdf_hit_cmp_eq0000_lut(3)
    );
  Mcompar_bdf_hit_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_bdf_hit_cmp_eq0000_cy(2),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bdf_hit_cmp_eq0000_lut(3),
      O => Mcompar_bdf_hit_cmp_eq0000_cy(3)
    );
  Mcompar_bdf_hit_cmp_eq0000_lut_4_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => bus_num(7),
      I1 => raddr(63),
      O => Mcompar_bdf_hit_cmp_eq0000_lut(4)
    );
  Mcompar_bdf_hit_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_bdf_hit_cmp_eq0000_cy(3),
      DI => NlwRenamedSig_OI_bar_hit(2),
      S => Mcompar_bdf_hit_cmp_eq0000_lut(4),
      O => bdf_hit_cmp_eq0000
    );
  bdf_check_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => rcheck_fun_id,
      I1 => rcheck_bus_id,
      I2 => rcheck_dev_id,
      O => bdf_check_or0000
    );
  bar_hit_1_or00001 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => bar01_64_hit_low_24281,
      I1 => bar01_64_hit_high_24278,
      I2 => bar1_32_hit_nc_24327,
      I3 => bar1_eq_raddr_24336,
      O => bar_hit_1_or0000
    );
  bar_hit_0_or00001 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => bar01_64_hit_low_24281,
      I1 => bar01_64_hit_high_24278,
      I2 => bar0_32_hit_nc_24284,
      I3 => bar0_eq_raddr_24294,
      O => bar_hit_0_or0000
    );
  bar6_32_hit_nc_and00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => xrom_reg(0),
      I1 => rmem32,
      I2 => command(1),
      I3 => pme_pmcsr(1),
      I4 => pme_pmcsr(0),
      O => bar6_32_hit_nc_and0000
    );
  bar6_32_hit1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => bar6_32_hit_nc_24403,
      I1 => bar6_eq_raddr_24405,
      O => bar6_32_hit
    );
  rhit_or0000_SW0 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => bdf_hit_24415,
      I1 => bdf_check_24413,
      I2 => bar1_eq_raddr_24336,
      I3 => bar1_32_hit_nc_24327,
      O => N0
    );
  rhit_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => bar0_eq_raddr_24294,
      I1 => bar0_32_hit_nc_24284,
      I2 => bar01_64_hit_low_24281,
      I3 => bar01_64_hit_high_24278,
      I4 => bar6_32_hit,
      I5 => N0,
      O => rhit_or0000_24467
    );
  bdf_hit_and00001 : LUT5
    generic map(
      INIT => X"000C0004"
    )
    port map (
      I0 => raddr(50),
      I1 => bdf_hit_cmp_eq0000,
      I2 => raddr(48),
      I3 => raddr(49),
      I4 => phantom_functions_enabled,
      O => bdf_hit_and0000
    );
  bar01_64_hit_high_and00001 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => bar01_64_hit_high_cmp_eq0000,
      I1 => bar0_reg(0),
      I2 => bar0_reg(1),
      I3 => bar0_reg(2),
      O => bar01_64_hit_high_and0000
    );
  bar01_64_hit_low_and00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => rmem64,
      I1 => bar01_64_hit_low_cmp_eq0000,
      I2 => command(1),
      I3 => pme_pmcsr(1),
      I4 => pme_pmcsr(0),
      O => bar01_64_hit_low_and0000
    );
  bar0_32_hit_nc_and00004 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => bar0_reg(1),
      I1 => bar0_reg(2),
      I2 => bar0_reg(0),
      O => bar0_32_hit_nc_and00004_24291
    );
  bar0_32_hit_nc_and000040 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(28),
      I1 => bar1_reg(29),
      I2 => bar1_reg(9),
      I3 => bar1_reg(8),
      I4 => bar1_reg(7),
      I5 => bar1_reg(6),
      O => bar0_32_hit_nc_and000040_24292
    );
  bar0_32_hit_nc_and000076 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(4),
      I1 => bar1_reg(5),
      I2 => bar1_reg(21),
      I3 => bar1_reg(20),
      I4 => bar1_reg(1),
      I5 => bar1_reg(19),
      O => bar0_32_hit_nc_and000076_24293
    );
  bar0_32_hit_nc_and0000133 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(0),
      I1 => bar1_reg(10),
      I2 => bar1_reg(16),
      I3 => bar1_reg(15),
      I4 => bar1_reg(14),
      I5 => bar1_reg(13),
      O => bar0_32_hit_nc_and0000133_24286
    );
  bar0_32_hit_nc_and0000169 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(11),
      I1 => bar1_reg(12),
      I2 => bar1_reg(3),
      I3 => bar1_reg(31),
      I4 => bar1_reg(30),
      I5 => bar1_reg(2),
      O => bar0_32_hit_nc_and0000169_24287
    );
  bar0_32_hit_nc_and0000245 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar1_reg(17),
      I1 => bar1_reg(18),
      I2 => bar1_reg(27),
      I3 => bar1_reg(26),
      I4 => bar1_reg(25),
      I5 => bar1_reg(24),
      O => bar0_32_hit_nc_and0000245_24288
    );
  bar0_32_hit_nc_and0000249 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => bar1_reg(22),
      I1 => bar1_reg(23),
      O => bar0_32_hit_nc_and0000249_24289
    );
  bar0_32_hit_nc_and0000267 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => bar0_32_hit_nc_and000040_24292,
      I1 => bar0_32_hit_nc_and000076_24293,
      I2 => bar0_32_hit_nc_and0000133_24286,
      I3 => bar0_32_hit_nc_and0000169_24287,
      I4 => bar0_32_hit_nc_and0000245_24288,
      I5 => bar0_32_hit_nc_and0000249_24289,
      O => bar0_32_hit_nc_and0000267_24290
    );
  bar1_32_hit_nc_and000040 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar2_reg(28),
      I1 => bar2_reg(29),
      I2 => bar2_reg(9),
      I3 => bar2_reg(8),
      I4 => bar2_reg(7),
      I5 => bar2_reg(6),
      O => bar1_32_hit_nc_and000040_24334
    );
  bar1_32_hit_nc_and000076 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar2_reg(4),
      I1 => bar2_reg(5),
      I2 => bar2_reg(21),
      I3 => bar2_reg(20),
      I4 => bar2_reg(1),
      I5 => bar2_reg(19),
      O => bar1_32_hit_nc_and000076_24335
    );
  bar1_32_hit_nc_and0000133 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar2_reg(0),
      I1 => bar2_reg(10),
      I2 => bar2_reg(16),
      I3 => bar2_reg(15),
      I4 => bar2_reg(14),
      I5 => bar2_reg(13),
      O => bar1_32_hit_nc_and0000133_24329
    );
  bar1_32_hit_nc_and0000169 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar2_reg(11),
      I1 => bar2_reg(12),
      I2 => bar2_reg(3),
      I3 => bar2_reg(31),
      I4 => bar2_reg(30),
      I5 => bar2_reg(2),
      O => bar1_32_hit_nc_and0000169_24330
    );
  bar1_32_hit_nc_and0000245 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => bar2_reg(17),
      I1 => bar2_reg(18),
      I2 => bar2_reg(27),
      I3 => bar2_reg(26),
      I4 => bar2_reg(25),
      I5 => bar2_reg(24),
      O => bar1_32_hit_nc_and0000245_24331
    );
  bar1_32_hit_nc_and0000249 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => bar2_reg(22),
      I1 => bar2_reg(23),
      O => bar1_32_hit_nc_and0000249_24332
    );
  bar1_32_hit_nc_and0000314 : LUT6
    generic map(
      INIT => X"00C000C0008000C0"
    )
    port map (
      I0 => bar0_reg(0),
      I1 => command(1),
      I2 => rmem32,
      I3 => pme_pmcsr(1),
      I4 => bar0_reg(2),
      I5 => bar0_reg(1),
      O => bar1_32_hit_nc_and0000314_24333
    );
  bar1_32_hit_nc_and0000326_SW0 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => bar1_32_hit_nc_and0000133_24329,
      I1 => bar1_32_hit_nc_and0000169_24330,
      I2 => bar1_32_hit_nc_and0000245_24331,
      I3 => bar1_32_hit_nc_and0000249_24332,
      I4 => bar1_32_hit_nc_and000040_24334,
      I5 => bar1_32_hit_nc_and000076_24335,
      O => N2
    );
  bar1_32_hit_nc_and0000326 : LUT6
    generic map(
      INIT => X"2222222222222022"
    )
    port map (
      I0 => bar1_32_hit_nc_and0000314_24333,
      I1 => pme_pmcsr(0),
      I2 => bar1_reg(1),
      I3 => bar1_reg(2),
      I4 => bar1_reg(0),
      I5 => N2,
      O => bar1_32_hit_nc_and0000
    );
  bar0_32_hit_nc_and0000308 : LUT6
    generic map(
      INIT => X"0200020002000000"
    )
    port map (
      I0 => command(1),
      I1 => pme_pmcsr(1),
      I2 => pme_pmcsr(0),
      I3 => rmem32,
      I4 => bar0_32_hit_nc_and00004_24291,
      I5 => bar0_32_hit_nc_and0000267_24290,
      O => bar0_32_hit_nc_and0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_plus_ll_rx is
  port (
    rx_err_cpl_ur_n : out STD_LOGIC; 
    trn_rsrc_rdy_n : out STD_LOGIC; 
    l0_stats_tlp_received : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    llk_rx_eof_n : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
    trn_rerrfwd_n : out STD_LOGIC; 
    llk_rx_dst_cont_req_n : out STD_LOGIC; 
    trn_rnp_ok_n : in STD_LOGIC := 'X'; 
    err_tlp_malformed : out STD_LOGIC; 
    err_tlp_ur_lock : out STD_LOGIC; 
    trn_rsof_n : out STD_LOGIC; 
    io_space_enable : in STD_LOGIC := 'X'; 
    llk_rx_dst_req_n : out STD_LOGIC; 
    llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    llk_rx_sof_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_ep_n : out STD_LOGIC; 
    err_tlp_uc : out STD_LOGIC; 
    trn_rsrc_dsc_n : out STD_LOGIC; 
    err_tlp_ur : out STD_LOGIC; 
    llk_rx_src_dsc_n : in STD_LOGIC := 'X'; 
    trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_abort_n : out STD_LOGIC; 
    err_tlp_p : out STD_LOGIC; 
    mem_space_enable : in STD_LOGIC := 'X'; 
    rx_err_ep_n : out STD_LOGIC; 
    rx_ch_credits_received_inc : in STD_LOGIC := 'X'; 
    trn_reof_n : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    err_tlp_cpl_header : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
    trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_data_d : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
    llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_valid_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rx_ch_credits_received : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_rx_xrom : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_rx_bar0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    llk_rx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end pcie_blk_plus_ll_rx;

architecture STRUCTURE of pcie_blk_plus_ll_rx is
  component cmm_decoder
    port (
      clk : in STD_LOGIC := 'X'; 
      cmmt_rbar_hit_lat2_n : out STD_LOGIC; 
      rcheck_bus_id : in STD_LOGIC := 'X'; 
      phantom_functions_enabled : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      rmem32 : in STD_LOGIC := 'X'; 
      rmem64 : in STD_LOGIC := 'X'; 
      rcheck_dev_id : in STD_LOGIC := 'X'; 
      rcheck_fun_id : in STD_LOGIC := 'X'; 
      rhit : out STD_LOGIC; 
      rio : in STD_LOGIC := 'X'; 
      bar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      bar4_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bar0_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      phantom_functions_supported : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      xrom_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bar5_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bar1_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      command : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      bar2_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bus_num : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      raddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pme_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      bar3_reg : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      device_num : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
      cfg : in STD_LOGIC_VECTOR ( 671 downto 0 ); 
      function_num : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component pcie_blk_ll_arb
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      llk_rx_dst_cont_req_n : out STD_LOGIC; 
      trn_rnp_ok_n : in STD_LOGIC := 'X'; 
      fifo_pcpl_ok : in STD_LOGIC := 'X'; 
      fifo_np_ok : in STD_LOGIC := 'X'; 
      llk_rx_dst_req_n : out STD_LOGIC; 
      llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      fifo_pcpl_req : out STD_LOGIC; 
      fifo_np_req : out STD_LOGIC; 
      cpl_tlp_cntr_inc : in STD_LOGIC := 'X'; 
      llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cpl_tlp_cntr : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  component tlm_rx_data_snk
    port (
      legacy_mode_i : in STD_LOGIC := 'X'; 
      reset_i : in STD_LOGIC := 'X'; 
      rem_i : in STD_LOGIC := 'X'; 
      locked_o : out STD_LOGIC; 
      rem_o : out STD_LOGIC; 
      td_ecrc_trim_i : in STD_LOGIC := 'X'; 
      check_rdev_o : out STD_LOGIC; 
      check_mem32_o : out STD_LOGIC; 
      stat_tlp_cpl_ep_o : out STD_LOGIC; 
      pm_turn_off_o : out STD_LOGIC; 
      pm_suspend_req_i : in STD_LOGIC := 'X'; 
      vend_msg_o : out STD_LOGIC; 
      ext_cfg_access_i : in STD_LOGIC := 'X'; 
      legacy_cfg_access_i : in STD_LOGIC := 'X'; 
      pm_set_slot_pwr_o : out STD_LOGIC; 
      cfg_o : out STD_LOGIC; 
      src_rdy_i : in STD_LOGIC := 'X'; 
      check_mem64_o : out STD_LOGIC; 
      check_rhit_i : in STD_LOGIC := 'X'; 
      src_rdy_o : out STD_LOGIC; 
      fc_unuse_o : out STD_LOGIC; 
      stat_tlp_cpl_abort_o : out STD_LOGIC; 
      cpl_o : out STD_LOGIC; 
      fc_use_np_o : out STD_LOGIC; 
      rid_o : out STD_LOGIC; 
      dsc_o : out STD_LOGIC; 
      eof_i : in STD_LOGIC := 'X'; 
      err_tlp_ur_lock_o : out STD_LOGIC; 
      eof_o : out STD_LOGIC; 
      hotplug_msg_enable_i : in STD_LOGIC := 'X'; 
      err_tlp_malformed_o : out STD_LOGIC; 
      rhit_bar_lat3_i : in STD_LOGIC := 'X'; 
      stat_tlp_ep_o : out STD_LOGIC; 
      check_rbus_o : out STD_LOGIC; 
      fc_use_cpl_o : out STD_LOGIC; 
      clk_i : in STD_LOGIC := 'X'; 
      np_o : out STD_LOGIC; 
      fc_use_p_o : out STD_LOGIC; 
      bar_src_rdy_o : out STD_LOGIC; 
      preeof_o : out STD_LOGIC; 
      vc_hit_o : out STD_LOGIC; 
      err_tlp_p_o : out STD_LOGIC; 
      check_rio_o : out STD_LOGIC; 
      sof_i : in STD_LOGIC := 'X'; 
      stat_tlp_cpl_ur_o : out STD_LOGIC; 
      sof_o : out STD_LOGIC; 
      err_tlp_ur_o : out STD_LOGIC; 
      src_dsc_i : in STD_LOGIC := 'X'; 
      check_rfun_o : out STD_LOGIC; 
      err_tlp_uc_o : out STD_LOGIC; 
      pm_as_nak_l1_o : out STD_LOGIC; 
      pm_set_slot_pwr_data_o : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      fc_use_data_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
      check_raddr_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      bar_o : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      d_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      err_tlp_cpl_header_o : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
      check_rhit_bar_i : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      max_payload_i : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      d_i : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component pcie_blk_ll_oqbqfifo
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      fifo_rem : in STD_LOGIC := 'X'; 
      trn_rsof : out STD_LOGIC; 
      trn_rdst_rdy : in STD_LOGIC := 'X'; 
      fifo_pcpl_ok : out STD_LOGIC; 
      fifo_np_ok : out STD_LOGIC; 
      trn_reof : out STD_LOGIC; 
      trn_rsrc_rdy : out STD_LOGIC; 
      fifo_preeof : in STD_LOGIC := 'X'; 
      fifo_wren : in STD_LOGIC := 'X'; 
      fifo_sof : in STD_LOGIC := 'X'; 
      fifo_dsc : in STD_LOGIC := 'X'; 
      trn_rnp_ok : in STD_LOGIC := 'X'; 
      fifo_eof : in STD_LOGIC := 'X'; 
      trn_rerrfwd : out STD_LOGIC; 
      fifo_pcpl_req : in STD_LOGIC := 'X'; 
      fifo_np : in STD_LOGIC := 'X'; 
      fifo_np_req : in STD_LOGIC := 'X'; 
      fifo_pcpl_abort : in STD_LOGIC := 'X'; 
      fifo_np_abort : in STD_LOGIC := 'X'; 
      trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_rrem : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      fifo_barenc : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal Q_and0000 : STD_LOGIC; 
  signal check_mem32 : STD_LOGIC; 
  signal check_mem64 : STD_LOGIC; 
  signal check_rbus : STD_LOGIC; 
  signal check_rdev : STD_LOGIC; 
  signal check_rfun : STD_LOGIC; 
  signal check_rhit : STD_LOGIC; 
  signal check_rhit_bar_lat3 : STD_LOGIC; 
  signal check_rio : STD_LOGIC; 
  signal fifo_inst_not0000 : STD_LOGIC; 
  signal fifo_np_ok : STD_LOGIC; 
  signal fifo_np_req : STD_LOGIC; 
  signal fifo_pcpl_ok : STD_LOGIC; 
  signal fifo_pcpl_req : STD_LOGIC; 
  signal llk_rx_eof_n_d_27922 : STD_LOGIC; 
  signal llk_rx_sof_n_d_27940 : STD_LOGIC; 
  signal llk_rx_src_rdy_n_d_27943 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal rx_err_cpl_abort : STD_LOGIC; 
  signal rx_err_cpl_ep : STD_LOGIC; 
  signal rx_err_cpl_ur : STD_LOGIC; 
  signal rx_err_ep : STD_LOGIC; 
  signal snk_bar_0_Q : STD_LOGIC; 
  signal snk_bar_1_Q : STD_LOGIC; 
  signal snk_bar_6_Q : STD_LOGIC; 
  signal snk_bar_ok_27972 : STD_LOGIC; 
  signal snk_bar_ok_and0000 : STD_LOGIC; 
  signal snk_bar_ok_and00001_27974 : STD_LOGIC; 
  signal snk_bar_ok_and00002_27975 : STD_LOGIC; 
  signal snk_bar_src_rdy : STD_LOGIC; 
  signal snk_cfg : STD_LOGIC; 
  signal snk_cpl : STD_LOGIC; 
  signal snk_eof : STD_LOGIC; 
  signal snk_inst_not0001 : STD_LOGIC; 
  signal snk_inst_not0002 : STD_LOGIC; 
  signal snk_inst_not0003 : STD_LOGIC; 
  signal snk_inst_not0004 : STD_LOGIC; 
  signal snk_locked : STD_LOGIC; 
  signal snk_np : STD_LOGIC; 
  signal snk_np_reg_28058 : STD_LOGIC; 
  signal snk_preeof : STD_LOGIC; 
  signal snk_rem : STD_LOGIC; 
  signal snk_rid : STD_LOGIC; 
  signal snk_sof : STD_LOGIC; 
  signal snk_src_dsc : STD_LOGIC; 
  signal snk_src_rdy : STD_LOGIC; 
  signal snk_vend_msg : STD_LOGIC; 
  signal trn_reof : STD_LOGIC; 
  signal trn_rerrfwd : STD_LOGIC; 
  signal trn_rsof : STD_LOGIC; 
  signal trn_rsrc_rdy : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rnp_ok_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_fifo_pcpl_abort_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_fifo_np_abort_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rbar_hit_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rbar_hit_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rbar_hit_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rbar_hit_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rbar_hit_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo_inst_trn_rrem_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_td_ecrc_trim_i_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_turn_off_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_unuse_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_np_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_cpl_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_p_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_vc_hit_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_as_nak_l1_o_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_pm_set_slot_pwr_data_o_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_fc_use_data_o_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_bar_o_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_bar_o_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_bar_o_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_snk_inst_bar_o_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_arb_inst_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_arb_inst_trn_rcpl_streaming_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_phantom_functions_supported_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_command_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_671_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_670_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_669_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_668_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_667_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_666_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_665_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_664_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_663_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_662_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_661_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_660_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_659_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_658_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_657_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_656_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_655_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_654_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_653_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_652_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_651_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_650_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_649_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_648_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_647_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_646_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_645_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_644_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_643_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_642_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_641_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_640_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_639_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_638_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_637_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_636_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_635_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_634_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_633_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_632_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_631_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_630_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_629_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_628_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_627_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_626_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_625_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_624_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_623_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_622_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_621_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_620_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_619_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_618_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_617_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_616_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_615_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_614_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_613_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_612_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_611_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_610_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_609_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_608_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_607_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_606_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_605_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_604_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_603_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_602_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_601_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_600_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_599_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_598_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_597_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_596_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_595_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_594_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_593_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_592_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_591_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_590_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_589_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_588_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_587_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_586_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_585_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_584_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_583_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_582_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_581_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_580_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_579_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_578_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_577_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_576_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_575_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_574_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_573_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_572_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_571_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_570_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_569_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_568_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_567_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_566_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_565_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_564_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_563_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_562_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_561_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_560_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_559_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_558_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_557_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_556_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_555_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_554_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_553_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_552_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_551_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_550_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_549_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_548_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_547_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_546_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_545_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_544_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_543_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_542_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_541_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_540_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_539_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_538_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_537_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_536_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_535_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_534_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_533_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_532_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_531_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_530_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_529_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_528_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_527_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_526_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_525_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_524_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_523_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_522_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_521_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_520_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_519_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_518_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_517_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_516_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_515_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_514_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_513_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_512_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_511_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_510_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_509_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_508_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_507_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_506_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_505_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_504_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_503_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_502_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_501_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_500_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_499_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_498_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_497_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_496_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_495_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_494_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_493_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_492_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_491_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_490_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_489_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_488_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_487_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_486_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_485_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_484_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_483_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_482_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_481_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_480_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_479_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_478_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_477_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_476_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_475_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_474_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_473_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_472_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_471_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_470_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_469_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_468_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_467_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_466_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_465_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_464_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_463_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_462_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_461_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_460_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_459_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_458_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_457_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_456_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_455_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_454_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_453_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_452_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_451_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_450_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_449_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_448_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_447_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_446_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_445_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_444_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_443_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_442_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_441_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_440_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_439_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_438_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_437_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_436_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_435_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_434_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_433_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_432_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_431_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_430_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_429_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_428_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_427_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_426_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_425_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_424_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_423_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_422_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_421_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_420_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_419_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_418_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_417_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_416_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_415_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_414_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_413_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_412_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_411_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_410_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_409_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_408_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_407_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_406_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_405_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_404_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_403_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_402_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_401_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_400_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_399_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_398_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_397_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_396_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_395_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_394_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_393_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_392_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_391_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_390_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_389_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_388_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_387_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_386_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_385_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_384_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_383_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_382_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_381_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_380_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_379_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_378_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_377_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_376_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_375_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_374_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_373_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_372_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_371_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_370_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_369_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_368_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_367_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_366_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_365_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_364_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_363_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_362_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_361_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_360_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_359_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_358_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_357_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_356_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_355_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_354_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_353_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_352_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_351_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_350_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_349_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_348_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_347_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_346_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_345_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_344_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_343_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_342_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_341_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_340_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_320_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_319_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_318_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_317_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_316_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_315_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_314_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_313_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_312_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_311_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_310_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_309_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_308_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_307_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_306_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_305_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_304_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_303_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_302_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_301_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_300_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_299_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_298_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_297_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_296_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_295_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_294_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_293_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_292_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_291_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_290_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_289_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_288_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_287_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_286_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_285_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_284_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_283_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_282_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_281_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_280_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_279_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_278_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_277_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_276_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_275_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_274_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_273_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_272_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_271_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_270_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_269_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_268_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_267_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_266_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_265_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_264_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_263_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_262_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_261_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_260_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_259_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_258_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_257_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_256_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_127_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_126_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_125_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_124_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_123_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_122_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_121_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_120_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_119_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_118_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_117_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_95_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_94_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_93_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_92_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_91_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_90_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_89_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_88_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_87_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_86_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_85_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_bar_decoder_cfg_0_UNCONNECTED : STD_LOGIC; 
  signal cfg_temp : STD_LOGIC_VECTOR ( 339 downto 339 ); 
  signal check_raddr : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal check_rhit_bar : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal NlwRenamedSig_OI_llk_rx_data_d : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal llk_rx_valid_n_d : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal snk_barenc : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal snk_barenc_mux0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal snk_d : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal trn_rbar_hit : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal trn_rrem : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  llk_rx_data_d(63) <= NlwRenamedSig_OI_llk_rx_data_d(63);
  llk_rx_data_d(62) <= NlwRenamedSig_OI_llk_rx_data_d(62);
  llk_rx_data_d(61) <= NlwRenamedSig_OI_llk_rx_data_d(61);
  llk_rx_data_d(60) <= NlwRenamedSig_OI_llk_rx_data_d(60);
  llk_rx_data_d(59) <= NlwRenamedSig_OI_llk_rx_data_d(59);
  llk_rx_data_d(58) <= NlwRenamedSig_OI_llk_rx_data_d(58);
  llk_rx_data_d(57) <= NlwRenamedSig_OI_llk_rx_data_d(57);
  llk_rx_data_d(56) <= NlwRenamedSig_OI_llk_rx_data_d(56);
  llk_rx_data_d(55) <= NlwRenamedSig_OI_llk_rx_data_d(55);
  llk_rx_data_d(54) <= NlwRenamedSig_OI_llk_rx_data_d(54);
  llk_rx_data_d(53) <= NlwRenamedSig_OI_llk_rx_data_d(53);
  llk_rx_data_d(52) <= NlwRenamedSig_OI_llk_rx_data_d(52);
  llk_rx_data_d(51) <= NlwRenamedSig_OI_llk_rx_data_d(51);
  llk_rx_data_d(50) <= NlwRenamedSig_OI_llk_rx_data_d(50);
  llk_rx_data_d(49) <= NlwRenamedSig_OI_llk_rx_data_d(49);
  llk_rx_data_d(48) <= NlwRenamedSig_OI_llk_rx_data_d(48);
  llk_rx_data_d(47) <= NlwRenamedSig_OI_llk_rx_data_d(47);
  llk_rx_data_d(46) <= NlwRenamedSig_OI_llk_rx_data_d(46);
  llk_rx_data_d(45) <= NlwRenamedSig_OI_llk_rx_data_d(45);
  llk_rx_data_d(44) <= NlwRenamedSig_OI_llk_rx_data_d(44);
  llk_rx_data_d(43) <= NlwRenamedSig_OI_llk_rx_data_d(43);
  llk_rx_data_d(42) <= NlwRenamedSig_OI_llk_rx_data_d(42);
  llk_rx_data_d(41) <= NlwRenamedSig_OI_llk_rx_data_d(41);
  llk_rx_data_d(40) <= NlwRenamedSig_OI_llk_rx_data_d(40);
  llk_rx_data_d(39) <= NlwRenamedSig_OI_llk_rx_data_d(39);
  llk_rx_data_d(38) <= NlwRenamedSig_OI_llk_rx_data_d(38);
  llk_rx_data_d(37) <= NlwRenamedSig_OI_llk_rx_data_d(37);
  llk_rx_data_d(36) <= NlwRenamedSig_OI_llk_rx_data_d(36);
  llk_rx_data_d(35) <= NlwRenamedSig_OI_llk_rx_data_d(35);
  llk_rx_data_d(34) <= NlwRenamedSig_OI_llk_rx_data_d(34);
  llk_rx_data_d(33) <= NlwRenamedSig_OI_llk_rx_data_d(33);
  llk_rx_data_d(32) <= NlwRenamedSig_OI_llk_rx_data_d(32);
  llk_rx_data_d(31) <= NlwRenamedSig_OI_llk_rx_data_d(31);
  llk_rx_data_d(30) <= NlwRenamedSig_OI_llk_rx_data_d(30);
  llk_rx_data_d(29) <= NlwRenamedSig_OI_llk_rx_data_d(29);
  llk_rx_data_d(28) <= NlwRenamedSig_OI_llk_rx_data_d(28);
  llk_rx_data_d(27) <= NlwRenamedSig_OI_llk_rx_data_d(27);
  llk_rx_data_d(26) <= NlwRenamedSig_OI_llk_rx_data_d(26);
  llk_rx_data_d(25) <= NlwRenamedSig_OI_llk_rx_data_d(25);
  llk_rx_data_d(24) <= NlwRenamedSig_OI_llk_rx_data_d(24);
  llk_rx_data_d(23) <= NlwRenamedSig_OI_llk_rx_data_d(23);
  llk_rx_data_d(22) <= NlwRenamedSig_OI_llk_rx_data_d(22);
  llk_rx_data_d(21) <= NlwRenamedSig_OI_llk_rx_data_d(21);
  llk_rx_data_d(20) <= NlwRenamedSig_OI_llk_rx_data_d(20);
  llk_rx_data_d(19) <= NlwRenamedSig_OI_llk_rx_data_d(19);
  llk_rx_data_d(18) <= NlwRenamedSig_OI_llk_rx_data_d(18);
  llk_rx_data_d(17) <= NlwRenamedSig_OI_llk_rx_data_d(17);
  llk_rx_data_d(16) <= NlwRenamedSig_OI_llk_rx_data_d(16);
  llk_rx_data_d(15) <= NlwRenamedSig_OI_llk_rx_data_d(15);
  llk_rx_data_d(14) <= NlwRenamedSig_OI_llk_rx_data_d(14);
  llk_rx_data_d(13) <= NlwRenamedSig_OI_llk_rx_data_d(13);
  llk_rx_data_d(12) <= NlwRenamedSig_OI_llk_rx_data_d(12);
  llk_rx_data_d(11) <= NlwRenamedSig_OI_llk_rx_data_d(11);
  llk_rx_data_d(10) <= NlwRenamedSig_OI_llk_rx_data_d(10);
  llk_rx_data_d(9) <= NlwRenamedSig_OI_llk_rx_data_d(9);
  llk_rx_data_d(8) <= NlwRenamedSig_OI_llk_rx_data_d(8);
  llk_rx_data_d(7) <= NlwRenamedSig_OI_llk_rx_data_d(7);
  llk_rx_data_d(6) <= NlwRenamedSig_OI_llk_rx_data_d(6);
  llk_rx_data_d(5) <= NlwRenamedSig_OI_llk_rx_data_d(5);
  llk_rx_data_d(4) <= NlwRenamedSig_OI_llk_rx_data_d(4);
  llk_rx_data_d(3) <= NlwRenamedSig_OI_llk_rx_data_d(3);
  llk_rx_data_d(2) <= NlwRenamedSig_OI_llk_rx_data_d(2);
  llk_rx_data_d(1) <= NlwRenamedSig_OI_llk_rx_data_d(1);
  llk_rx_data_d(0) <= NlwRenamedSig_OI_llk_rx_data_d(0);
  XST_GND : GND
    port map (
      G => cfg_temp(339)
    );
  llk_rx_sof_n_d : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_sof_n,
      S => rst_n_inv,
      Q => llk_rx_sof_n_d_27940
    );
  llk_rx_eof_n_d : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_eof_n,
      S => rst_n_inv,
      Q => llk_rx_eof_n_d_27922
    );
  llk_rx_valid_n_d_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_valid_n(0),
      R => rst_n_inv,
      Q => llk_rx_valid_n_d(0)
    );
  llk_rx_data_d_0 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(0),
      Q => NlwRenamedSig_OI_llk_rx_data_d(0)
    );
  llk_rx_data_d_1 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(1),
      Q => NlwRenamedSig_OI_llk_rx_data_d(1)
    );
  llk_rx_data_d_2 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(2),
      Q => NlwRenamedSig_OI_llk_rx_data_d(2)
    );
  llk_rx_data_d_3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(3),
      Q => NlwRenamedSig_OI_llk_rx_data_d(3)
    );
  llk_rx_data_d_4 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(4),
      Q => NlwRenamedSig_OI_llk_rx_data_d(4)
    );
  llk_rx_data_d_5 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(5),
      Q => NlwRenamedSig_OI_llk_rx_data_d(5)
    );
  llk_rx_data_d_6 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(6),
      Q => NlwRenamedSig_OI_llk_rx_data_d(6)
    );
  llk_rx_data_d_7 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(7),
      Q => NlwRenamedSig_OI_llk_rx_data_d(7)
    );
  llk_rx_data_d_8 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(8),
      Q => NlwRenamedSig_OI_llk_rx_data_d(8)
    );
  llk_rx_data_d_9 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(9),
      Q => NlwRenamedSig_OI_llk_rx_data_d(9)
    );
  llk_rx_data_d_10 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(10),
      Q => NlwRenamedSig_OI_llk_rx_data_d(10)
    );
  llk_rx_data_d_11 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(11),
      Q => NlwRenamedSig_OI_llk_rx_data_d(11)
    );
  llk_rx_data_d_12 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(12),
      Q => NlwRenamedSig_OI_llk_rx_data_d(12)
    );
  llk_rx_data_d_13 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(13),
      Q => NlwRenamedSig_OI_llk_rx_data_d(13)
    );
  llk_rx_data_d_14 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(14),
      Q => NlwRenamedSig_OI_llk_rx_data_d(14)
    );
  llk_rx_data_d_15 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(15),
      Q => NlwRenamedSig_OI_llk_rx_data_d(15)
    );
  llk_rx_data_d_16 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(16),
      Q => NlwRenamedSig_OI_llk_rx_data_d(16)
    );
  llk_rx_data_d_17 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(17),
      Q => NlwRenamedSig_OI_llk_rx_data_d(17)
    );
  llk_rx_data_d_18 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(18),
      Q => NlwRenamedSig_OI_llk_rx_data_d(18)
    );
  llk_rx_data_d_19 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(19),
      Q => NlwRenamedSig_OI_llk_rx_data_d(19)
    );
  llk_rx_data_d_20 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(20),
      Q => NlwRenamedSig_OI_llk_rx_data_d(20)
    );
  llk_rx_data_d_21 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(21),
      Q => NlwRenamedSig_OI_llk_rx_data_d(21)
    );
  llk_rx_data_d_22 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(22),
      Q => NlwRenamedSig_OI_llk_rx_data_d(22)
    );
  llk_rx_data_d_23 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(23),
      Q => NlwRenamedSig_OI_llk_rx_data_d(23)
    );
  llk_rx_data_d_24 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(24),
      Q => NlwRenamedSig_OI_llk_rx_data_d(24)
    );
  llk_rx_data_d_25 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(25),
      Q => NlwRenamedSig_OI_llk_rx_data_d(25)
    );
  llk_rx_data_d_26 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(26),
      Q => NlwRenamedSig_OI_llk_rx_data_d(26)
    );
  llk_rx_data_d_27 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(27),
      Q => NlwRenamedSig_OI_llk_rx_data_d(27)
    );
  llk_rx_data_d_28 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(28),
      Q => NlwRenamedSig_OI_llk_rx_data_d(28)
    );
  llk_rx_data_d_29 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(29),
      Q => NlwRenamedSig_OI_llk_rx_data_d(29)
    );
  llk_rx_data_d_30 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(30),
      Q => NlwRenamedSig_OI_llk_rx_data_d(30)
    );
  llk_rx_data_d_31 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_data(31),
      Q => NlwRenamedSig_OI_llk_rx_data_d(31)
    );
  llk_rx_data_d_32 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(32),
      Q => NlwRenamedSig_OI_llk_rx_data_d(32)
    );
  llk_rx_data_d_33 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(33),
      Q => NlwRenamedSig_OI_llk_rx_data_d(33)
    );
  llk_rx_data_d_34 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(34),
      Q => NlwRenamedSig_OI_llk_rx_data_d(34)
    );
  llk_rx_data_d_35 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(35),
      Q => NlwRenamedSig_OI_llk_rx_data_d(35)
    );
  llk_rx_data_d_36 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(36),
      Q => NlwRenamedSig_OI_llk_rx_data_d(36)
    );
  llk_rx_data_d_37 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(37),
      Q => NlwRenamedSig_OI_llk_rx_data_d(37)
    );
  llk_rx_data_d_38 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(38),
      Q => NlwRenamedSig_OI_llk_rx_data_d(38)
    );
  llk_rx_data_d_39 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(39),
      Q => NlwRenamedSig_OI_llk_rx_data_d(39)
    );
  llk_rx_data_d_40 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(40),
      Q => NlwRenamedSig_OI_llk_rx_data_d(40)
    );
  llk_rx_data_d_41 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(41),
      Q => NlwRenamedSig_OI_llk_rx_data_d(41)
    );
  llk_rx_data_d_42 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(42),
      Q => NlwRenamedSig_OI_llk_rx_data_d(42)
    );
  llk_rx_data_d_43 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(43),
      Q => NlwRenamedSig_OI_llk_rx_data_d(43)
    );
  llk_rx_data_d_44 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(44),
      Q => NlwRenamedSig_OI_llk_rx_data_d(44)
    );
  llk_rx_data_d_45 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(45),
      Q => NlwRenamedSig_OI_llk_rx_data_d(45)
    );
  llk_rx_data_d_46 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(46),
      Q => NlwRenamedSig_OI_llk_rx_data_d(46)
    );
  llk_rx_data_d_47 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(47),
      Q => NlwRenamedSig_OI_llk_rx_data_d(47)
    );
  llk_rx_data_d_48 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(48),
      Q => NlwRenamedSig_OI_llk_rx_data_d(48)
    );
  llk_rx_data_d_49 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(49),
      Q => NlwRenamedSig_OI_llk_rx_data_d(49)
    );
  llk_rx_data_d_50 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(50),
      Q => NlwRenamedSig_OI_llk_rx_data_d(50)
    );
  llk_rx_data_d_51 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(51),
      Q => NlwRenamedSig_OI_llk_rx_data_d(51)
    );
  llk_rx_data_d_52 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(52),
      Q => NlwRenamedSig_OI_llk_rx_data_d(52)
    );
  llk_rx_data_d_53 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(53),
      Q => NlwRenamedSig_OI_llk_rx_data_d(53)
    );
  llk_rx_data_d_54 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(54),
      Q => NlwRenamedSig_OI_llk_rx_data_d(54)
    );
  llk_rx_data_d_55 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(55),
      Q => NlwRenamedSig_OI_llk_rx_data_d(55)
    );
  llk_rx_data_d_56 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(56),
      Q => NlwRenamedSig_OI_llk_rx_data_d(56)
    );
  llk_rx_data_d_57 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(57),
      Q => NlwRenamedSig_OI_llk_rx_data_d(57)
    );
  llk_rx_data_d_58 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(58),
      Q => NlwRenamedSig_OI_llk_rx_data_d(58)
    );
  llk_rx_data_d_59 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(59),
      Q => NlwRenamedSig_OI_llk_rx_data_d(59)
    );
  llk_rx_data_d_60 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(60),
      Q => NlwRenamedSig_OI_llk_rx_data_d(60)
    );
  llk_rx_data_d_61 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(61),
      Q => NlwRenamedSig_OI_llk_rx_data_d(61)
    );
  llk_rx_data_d_62 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(62),
      Q => NlwRenamedSig_OI_llk_rx_data_d(62)
    );
  llk_rx_data_d_63 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => llk_rx_data(63),
      Q => NlwRenamedSig_OI_llk_rx_data_d(63)
    );
  llk_rx_src_rdy_n_d : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => llk_rx_src_rdy_n,
      S => rst_n_inv,
      Q => llk_rx_src_rdy_n_d_27943
    );
  snk_barenc_0 : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_barenc_mux0000(3),
      Q => snk_barenc(0)
    );
  snk_barenc_1 : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_barenc_mux0000(2),
      Q => snk_barenc(1)
    );
  snk_barenc_2 : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_barenc_mux0000(1),
      Q => snk_barenc(2)
    );
  snk_barenc_3 : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_barenc_mux0000(0),
      Q => snk_barenc(3)
    );
  snk_np_reg : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_np,
      Q => snk_np_reg_28058
    );
  snk_bar_ok : FDE
    port map (
      C => clk,
      CE => snk_bar_src_rdy,
      D => snk_bar_ok_and0000,
      Q => snk_bar_ok_27972
    );
  bar_decoder : cmm_decoder
    port map (
      clk => clk,
      cmmt_rbar_hit_lat2_n => check_rhit_bar_lat3,
      rcheck_bus_id => check_rbus,
      phantom_functions_enabled => cfg_dcommand(9),
      rst => rst_n_inv,
      rmem32 => check_mem32,
      rmem64 => check_mem64,
      rcheck_dev_id => check_rdev,
      rcheck_fun_id => check_rfun,
      rhit => check_rhit,
      rio => check_rio,
      bar_hit(6) => check_rhit_bar(6),
      bar_hit(5) => check_rhit_bar(5),
      bar_hit(4) => check_rhit_bar(4),
      bar_hit(3) => check_rhit_bar(3),
      bar_hit(2) => check_rhit_bar(2),
      bar_hit(1) => check_rhit_bar(1),
      bar_hit(0) => check_rhit_bar(0),
      bar4_reg(31) => cfg_rx_bar4(31),
      bar4_reg(30) => cfg_rx_bar4(30),
      bar4_reg(29) => cfg_rx_bar4(29),
      bar4_reg(28) => cfg_rx_bar4(28),
      bar4_reg(27) => cfg_rx_bar4(27),
      bar4_reg(26) => cfg_rx_bar4(26),
      bar4_reg(25) => cfg_rx_bar4(25),
      bar4_reg(24) => cfg_rx_bar4(24),
      bar4_reg(23) => cfg_rx_bar4(23),
      bar4_reg(22) => cfg_rx_bar4(22),
      bar4_reg(21) => cfg_rx_bar4(21),
      bar4_reg(20) => cfg_rx_bar4(20),
      bar4_reg(19) => cfg_rx_bar4(19),
      bar4_reg(18) => cfg_rx_bar4(18),
      bar4_reg(17) => cfg_rx_bar4(17),
      bar4_reg(16) => cfg_rx_bar4(16),
      bar4_reg(15) => cfg_rx_bar4(15),
      bar4_reg(14) => cfg_rx_bar4(14),
      bar4_reg(13) => cfg_rx_bar4(13),
      bar4_reg(12) => cfg_rx_bar4(12),
      bar4_reg(11) => cfg_rx_bar4(11),
      bar4_reg(10) => cfg_rx_bar4(10),
      bar4_reg(9) => cfg_rx_bar4(9),
      bar4_reg(8) => cfg_rx_bar4(8),
      bar4_reg(7) => cfg_rx_bar4(7),
      bar4_reg(6) => cfg_rx_bar4(6),
      bar4_reg(5) => cfg_rx_bar4(5),
      bar4_reg(4) => cfg_rx_bar4(4),
      bar4_reg(3) => cfg_rx_bar4(3),
      bar4_reg(2) => cfg_rx_bar4(2),
      bar4_reg(1) => cfg_rx_bar4(1),
      bar4_reg(0) => cfg_rx_bar4(0),
      bar0_reg(31) => cfg_rx_bar0(31),
      bar0_reg(30) => cfg_rx_bar0(30),
      bar0_reg(29) => cfg_rx_bar0(29),
      bar0_reg(28) => cfg_rx_bar0(28),
      bar0_reg(27) => cfg_rx_bar0(27),
      bar0_reg(26) => cfg_rx_bar0(26),
      bar0_reg(25) => cfg_rx_bar0(25),
      bar0_reg(24) => cfg_rx_bar0(24),
      bar0_reg(23) => cfg_rx_bar0(23),
      bar0_reg(22) => cfg_rx_bar0(22),
      bar0_reg(21) => cfg_rx_bar0(21),
      bar0_reg(20) => cfg_rx_bar0(20),
      bar0_reg(19) => cfg_rx_bar0(19),
      bar0_reg(18) => cfg_rx_bar0(18),
      bar0_reg(17) => cfg_rx_bar0(17),
      bar0_reg(16) => cfg_rx_bar0(16),
      bar0_reg(15) => cfg_rx_bar0(15),
      bar0_reg(14) => cfg_rx_bar0(14),
      bar0_reg(13) => cfg_rx_bar0(13),
      bar0_reg(12) => cfg_rx_bar0(12),
      bar0_reg(11) => cfg_rx_bar0(11),
      bar0_reg(10) => cfg_rx_bar0(10),
      bar0_reg(9) => cfg_rx_bar0(9),
      bar0_reg(8) => cfg_rx_bar0(8),
      bar0_reg(7) => cfg_rx_bar0(7),
      bar0_reg(6) => cfg_rx_bar0(6),
      bar0_reg(5) => cfg_rx_bar0(5),
      bar0_reg(4) => cfg_rx_bar0(4),
      bar0_reg(3) => cfg_rx_bar0(3),
      bar0_reg(2) => cfg_rx_bar0(2),
      bar0_reg(1) => cfg_rx_bar0(1),
      bar0_reg(0) => cfg_rx_bar0(0),
      phantom_functions_supported(1) => cfg_temp(339),
      phantom_functions_supported(0) => NLW_bar_decoder_phantom_functions_supported_0_UNCONNECTED,
      xrom_reg(31) => cfg_rx_xrom(31),
      xrom_reg(30) => cfg_rx_xrom(30),
      xrom_reg(29) => cfg_rx_xrom(29),
      xrom_reg(28) => cfg_rx_xrom(28),
      xrom_reg(27) => cfg_rx_xrom(27),
      xrom_reg(26) => cfg_rx_xrom(26),
      xrom_reg(25) => cfg_rx_xrom(25),
      xrom_reg(24) => cfg_rx_xrom(24),
      xrom_reg(23) => cfg_rx_xrom(23),
      xrom_reg(22) => cfg_rx_xrom(22),
      xrom_reg(21) => cfg_rx_xrom(21),
      xrom_reg(20) => cfg_rx_xrom(20),
      xrom_reg(19) => cfg_rx_xrom(19),
      xrom_reg(18) => cfg_rx_xrom(18),
      xrom_reg(17) => cfg_rx_xrom(17),
      xrom_reg(16) => cfg_rx_xrom(16),
      xrom_reg(15) => cfg_rx_xrom(15),
      xrom_reg(14) => cfg_rx_xrom(14),
      xrom_reg(13) => cfg_rx_xrom(13),
      xrom_reg(12) => cfg_rx_xrom(12),
      xrom_reg(11) => cfg_rx_xrom(11),
      xrom_reg(10) => cfg_rx_xrom(10),
      xrom_reg(9) => cfg_rx_xrom(9),
      xrom_reg(8) => cfg_rx_xrom(8),
      xrom_reg(7) => cfg_rx_xrom(7),
      xrom_reg(6) => cfg_rx_xrom(6),
      xrom_reg(5) => cfg_rx_xrom(5),
      xrom_reg(4) => cfg_rx_xrom(4),
      xrom_reg(3) => cfg_rx_xrom(3),
      xrom_reg(2) => cfg_rx_xrom(2),
      xrom_reg(1) => cfg_rx_xrom(1),
      xrom_reg(0) => cfg_rx_xrom(0),
      bar5_reg(31) => cfg_rx_bar5(31),
      bar5_reg(30) => cfg_rx_bar5(30),
      bar5_reg(29) => cfg_rx_bar5(29),
      bar5_reg(28) => cfg_rx_bar5(28),
      bar5_reg(27) => cfg_rx_bar5(27),
      bar5_reg(26) => cfg_rx_bar5(26),
      bar5_reg(25) => cfg_rx_bar5(25),
      bar5_reg(24) => cfg_rx_bar5(24),
      bar5_reg(23) => cfg_rx_bar5(23),
      bar5_reg(22) => cfg_rx_bar5(22),
      bar5_reg(21) => cfg_rx_bar5(21),
      bar5_reg(20) => cfg_rx_bar5(20),
      bar5_reg(19) => cfg_rx_bar5(19),
      bar5_reg(18) => cfg_rx_bar5(18),
      bar5_reg(17) => cfg_rx_bar5(17),
      bar5_reg(16) => cfg_rx_bar5(16),
      bar5_reg(15) => cfg_rx_bar5(15),
      bar5_reg(14) => cfg_rx_bar5(14),
      bar5_reg(13) => cfg_rx_bar5(13),
      bar5_reg(12) => cfg_rx_bar5(12),
      bar5_reg(11) => cfg_rx_bar5(11),
      bar5_reg(10) => cfg_rx_bar5(10),
      bar5_reg(9) => cfg_rx_bar5(9),
      bar5_reg(8) => cfg_rx_bar5(8),
      bar5_reg(7) => cfg_rx_bar5(7),
      bar5_reg(6) => cfg_rx_bar5(6),
      bar5_reg(5) => cfg_rx_bar5(5),
      bar5_reg(4) => cfg_rx_bar5(4),
      bar5_reg(3) => cfg_rx_bar5(3),
      bar5_reg(2) => cfg_rx_bar5(2),
      bar5_reg(1) => cfg_rx_bar5(1),
      bar5_reg(0) => cfg_rx_bar5(0),
      bar1_reg(31) => cfg_rx_bar1(31),
      bar1_reg(30) => cfg_rx_bar1(30),
      bar1_reg(29) => cfg_rx_bar1(29),
      bar1_reg(28) => cfg_rx_bar1(28),
      bar1_reg(27) => cfg_rx_bar1(27),
      bar1_reg(26) => cfg_rx_bar1(26),
      bar1_reg(25) => cfg_rx_bar1(25),
      bar1_reg(24) => cfg_rx_bar1(24),
      bar1_reg(23) => cfg_rx_bar1(23),
      bar1_reg(22) => cfg_rx_bar1(22),
      bar1_reg(21) => cfg_rx_bar1(21),
      bar1_reg(20) => cfg_rx_bar1(20),
      bar1_reg(19) => cfg_rx_bar1(19),
      bar1_reg(18) => cfg_rx_bar1(18),
      bar1_reg(17) => cfg_rx_bar1(17),
      bar1_reg(16) => cfg_rx_bar1(16),
      bar1_reg(15) => cfg_rx_bar1(15),
      bar1_reg(14) => cfg_rx_bar1(14),
      bar1_reg(13) => cfg_rx_bar1(13),
      bar1_reg(12) => cfg_rx_bar1(12),
      bar1_reg(11) => cfg_rx_bar1(11),
      bar1_reg(10) => cfg_rx_bar1(10),
      bar1_reg(9) => cfg_rx_bar1(9),
      bar1_reg(8) => cfg_rx_bar1(8),
      bar1_reg(7) => cfg_rx_bar1(7),
      bar1_reg(6) => cfg_rx_bar1(6),
      bar1_reg(5) => cfg_rx_bar1(5),
      bar1_reg(4) => cfg_rx_bar1(4),
      bar1_reg(3) => cfg_rx_bar1(3),
      bar1_reg(2) => cfg_rx_bar1(2),
      bar1_reg(1) => cfg_rx_bar1(1),
      bar1_reg(0) => cfg_rx_bar1(0),
      command(15) => NLW_bar_decoder_command_15_UNCONNECTED,
      command(14) => NLW_bar_decoder_command_14_UNCONNECTED,
      command(13) => NLW_bar_decoder_command_13_UNCONNECTED,
      command(12) => NLW_bar_decoder_command_12_UNCONNECTED,
      command(11) => NLW_bar_decoder_command_11_UNCONNECTED,
      command(10) => NLW_bar_decoder_command_10_UNCONNECTED,
      command(9) => NLW_bar_decoder_command_9_UNCONNECTED,
      command(8) => NLW_bar_decoder_command_8_UNCONNECTED,
      command(7) => NLW_bar_decoder_command_7_UNCONNECTED,
      command(6) => NLW_bar_decoder_command_6_UNCONNECTED,
      command(5) => NLW_bar_decoder_command_5_UNCONNECTED,
      command(4) => NLW_bar_decoder_command_4_UNCONNECTED,
      command(3) => NLW_bar_decoder_command_3_UNCONNECTED,
      command(2) => NLW_bar_decoder_command_2_UNCONNECTED,
      command(1) => mem_space_enable,
      command(0) => io_space_enable,
      bar2_reg(31) => cfg_rx_bar2(31),
      bar2_reg(30) => cfg_rx_bar2(30),
      bar2_reg(29) => cfg_rx_bar2(29),
      bar2_reg(28) => cfg_rx_bar2(28),
      bar2_reg(27) => cfg_rx_bar2(27),
      bar2_reg(26) => cfg_rx_bar2(26),
      bar2_reg(25) => cfg_rx_bar2(25),
      bar2_reg(24) => cfg_rx_bar2(24),
      bar2_reg(23) => cfg_rx_bar2(23),
      bar2_reg(22) => cfg_rx_bar2(22),
      bar2_reg(21) => cfg_rx_bar2(21),
      bar2_reg(20) => cfg_rx_bar2(20),
      bar2_reg(19) => cfg_rx_bar2(19),
      bar2_reg(18) => cfg_rx_bar2(18),
      bar2_reg(17) => cfg_rx_bar2(17),
      bar2_reg(16) => cfg_rx_bar2(16),
      bar2_reg(15) => cfg_rx_bar2(15),
      bar2_reg(14) => cfg_rx_bar2(14),
      bar2_reg(13) => cfg_rx_bar2(13),
      bar2_reg(12) => cfg_rx_bar2(12),
      bar2_reg(11) => cfg_rx_bar2(11),
      bar2_reg(10) => cfg_rx_bar2(10),
      bar2_reg(9) => cfg_rx_bar2(9),
      bar2_reg(8) => cfg_rx_bar2(8),
      bar2_reg(7) => cfg_rx_bar2(7),
      bar2_reg(6) => cfg_rx_bar2(6),
      bar2_reg(5) => cfg_rx_bar2(5),
      bar2_reg(4) => cfg_rx_bar2(4),
      bar2_reg(3) => cfg_rx_bar2(3),
      bar2_reg(2) => cfg_rx_bar2(2),
      bar2_reg(1) => cfg_rx_bar2(1),
      bar2_reg(0) => cfg_rx_bar2(0),
      bus_num(7) => cfg_bus_number(7),
      bus_num(6) => cfg_bus_number(6),
      bus_num(5) => cfg_bus_number(5),
      bus_num(4) => cfg_bus_number(4),
      bus_num(3) => cfg_bus_number(3),
      bus_num(2) => cfg_bus_number(2),
      bus_num(1) => cfg_bus_number(1),
      bus_num(0) => cfg_bus_number(0),
      raddr(63) => check_raddr(63),
      raddr(62) => check_raddr(62),
      raddr(61) => check_raddr(61),
      raddr(60) => check_raddr(60),
      raddr(59) => check_raddr(59),
      raddr(58) => check_raddr(58),
      raddr(57) => check_raddr(57),
      raddr(56) => check_raddr(56),
      raddr(55) => check_raddr(55),
      raddr(54) => check_raddr(54),
      raddr(53) => check_raddr(53),
      raddr(52) => check_raddr(52),
      raddr(51) => check_raddr(51),
      raddr(50) => check_raddr(50),
      raddr(49) => check_raddr(49),
      raddr(48) => check_raddr(48),
      raddr(47) => check_raddr(47),
      raddr(46) => check_raddr(46),
      raddr(45) => check_raddr(45),
      raddr(44) => check_raddr(44),
      raddr(43) => check_raddr(43),
      raddr(42) => check_raddr(42),
      raddr(41) => check_raddr(41),
      raddr(40) => check_raddr(40),
      raddr(39) => check_raddr(39),
      raddr(38) => check_raddr(38),
      raddr(37) => check_raddr(37),
      raddr(36) => check_raddr(36),
      raddr(35) => check_raddr(35),
      raddr(34) => check_raddr(34),
      raddr(33) => check_raddr(33),
      raddr(32) => check_raddr(32),
      raddr(31) => check_raddr(31),
      raddr(30) => check_raddr(30),
      raddr(29) => check_raddr(29),
      raddr(28) => check_raddr(28),
      raddr(27) => check_raddr(27),
      raddr(26) => check_raddr(26),
      raddr(25) => check_raddr(25),
      raddr(24) => check_raddr(24),
      raddr(23) => check_raddr(23),
      raddr(22) => check_raddr(22),
      raddr(21) => check_raddr(21),
      raddr(20) => check_raddr(20),
      raddr(19) => check_raddr(19),
      raddr(18) => check_raddr(18),
      raddr(17) => check_raddr(17),
      raddr(16) => check_raddr(16),
      raddr(15) => check_raddr(15),
      raddr(14) => check_raddr(14),
      raddr(13) => check_raddr(13),
      raddr(12) => check_raddr(12),
      raddr(11) => check_raddr(11),
      raddr(10) => check_raddr(10),
      raddr(9) => check_raddr(9),
      raddr(8) => check_raddr(8),
      raddr(7) => check_raddr(7),
      raddr(6) => check_raddr(6),
      raddr(5) => check_raddr(5),
      raddr(4) => check_raddr(4),
      raddr(3) => check_raddr(3),
      raddr(2) => check_raddr(2),
      raddr(1) => check_raddr(1),
      raddr(0) => check_raddr(0),
      pme_pmcsr(15) => cfg_pmcsr(15),
      pme_pmcsr(14) => cfg_pmcsr(14),
      pme_pmcsr(13) => cfg_pmcsr(13),
      pme_pmcsr(12) => cfg_pmcsr(12),
      pme_pmcsr(11) => cfg_pmcsr(11),
      pme_pmcsr(10) => cfg_pmcsr(10),
      pme_pmcsr(9) => cfg_pmcsr(9),
      pme_pmcsr(8) => cfg_pmcsr(8),
      pme_pmcsr(7) => cfg_pmcsr(7),
      pme_pmcsr(6) => cfg_pmcsr(6),
      pme_pmcsr(5) => cfg_pmcsr(5),
      pme_pmcsr(4) => cfg_pmcsr(4),
      pme_pmcsr(3) => cfg_pmcsr(3),
      pme_pmcsr(2) => cfg_pmcsr(2),
      pme_pmcsr(1) => cfg_pmcsr(1),
      pme_pmcsr(0) => cfg_pmcsr(0),
      bar3_reg(31) => cfg_rx_bar3(31),
      bar3_reg(30) => cfg_rx_bar3(30),
      bar3_reg(29) => cfg_rx_bar3(29),
      bar3_reg(28) => cfg_rx_bar3(28),
      bar3_reg(27) => cfg_rx_bar3(27),
      bar3_reg(26) => cfg_rx_bar3(26),
      bar3_reg(25) => cfg_rx_bar3(25),
      bar3_reg(24) => cfg_rx_bar3(24),
      bar3_reg(23) => cfg_rx_bar3(23),
      bar3_reg(22) => cfg_rx_bar3(22),
      bar3_reg(21) => cfg_rx_bar3(21),
      bar3_reg(20) => cfg_rx_bar3(20),
      bar3_reg(19) => cfg_rx_bar3(19),
      bar3_reg(18) => cfg_rx_bar3(18),
      bar3_reg(17) => cfg_rx_bar3(17),
      bar3_reg(16) => cfg_rx_bar3(16),
      bar3_reg(15) => cfg_rx_bar3(15),
      bar3_reg(14) => cfg_rx_bar3(14),
      bar3_reg(13) => cfg_rx_bar3(13),
      bar3_reg(12) => cfg_rx_bar3(12),
      bar3_reg(11) => cfg_rx_bar3(11),
      bar3_reg(10) => cfg_rx_bar3(10),
      bar3_reg(9) => cfg_rx_bar3(9),
      bar3_reg(8) => cfg_rx_bar3(8),
      bar3_reg(7) => cfg_rx_bar3(7),
      bar3_reg(6) => cfg_rx_bar3(6),
      bar3_reg(5) => cfg_rx_bar3(5),
      bar3_reg(4) => cfg_rx_bar3(4),
      bar3_reg(3) => cfg_rx_bar3(3),
      bar3_reg(2) => cfg_rx_bar3(2),
      bar3_reg(1) => cfg_rx_bar3(1),
      bar3_reg(0) => cfg_rx_bar3(0),
      device_num(4) => cfg_device_number(4),
      device_num(3) => cfg_device_number(3),
      device_num(2) => cfg_device_number(2),
      device_num(1) => cfg_device_number(1),
      device_num(0) => cfg_device_number(0),
      cfg(671) => NLW_bar_decoder_cfg_671_UNCONNECTED,
      cfg(670) => NLW_bar_decoder_cfg_670_UNCONNECTED,
      cfg(669) => NLW_bar_decoder_cfg_669_UNCONNECTED,
      cfg(668) => NLW_bar_decoder_cfg_668_UNCONNECTED,
      cfg(667) => NLW_bar_decoder_cfg_667_UNCONNECTED,
      cfg(666) => NLW_bar_decoder_cfg_666_UNCONNECTED,
      cfg(665) => NLW_bar_decoder_cfg_665_UNCONNECTED,
      cfg(664) => NLW_bar_decoder_cfg_664_UNCONNECTED,
      cfg(663) => NLW_bar_decoder_cfg_663_UNCONNECTED,
      cfg(662) => NLW_bar_decoder_cfg_662_UNCONNECTED,
      cfg(661) => NLW_bar_decoder_cfg_661_UNCONNECTED,
      cfg(660) => NLW_bar_decoder_cfg_660_UNCONNECTED,
      cfg(659) => NLW_bar_decoder_cfg_659_UNCONNECTED,
      cfg(658) => NLW_bar_decoder_cfg_658_UNCONNECTED,
      cfg(657) => NLW_bar_decoder_cfg_657_UNCONNECTED,
      cfg(656) => NLW_bar_decoder_cfg_656_UNCONNECTED,
      cfg(655) => NLW_bar_decoder_cfg_655_UNCONNECTED,
      cfg(654) => NLW_bar_decoder_cfg_654_UNCONNECTED,
      cfg(653) => NLW_bar_decoder_cfg_653_UNCONNECTED,
      cfg(652) => NLW_bar_decoder_cfg_652_UNCONNECTED,
      cfg(651) => NLW_bar_decoder_cfg_651_UNCONNECTED,
      cfg(650) => NLW_bar_decoder_cfg_650_UNCONNECTED,
      cfg(649) => NLW_bar_decoder_cfg_649_UNCONNECTED,
      cfg(648) => NLW_bar_decoder_cfg_648_UNCONNECTED,
      cfg(647) => NLW_bar_decoder_cfg_647_UNCONNECTED,
      cfg(646) => NLW_bar_decoder_cfg_646_UNCONNECTED,
      cfg(645) => NLW_bar_decoder_cfg_645_UNCONNECTED,
      cfg(644) => NLW_bar_decoder_cfg_644_UNCONNECTED,
      cfg(643) => NLW_bar_decoder_cfg_643_UNCONNECTED,
      cfg(642) => NLW_bar_decoder_cfg_642_UNCONNECTED,
      cfg(641) => NLW_bar_decoder_cfg_641_UNCONNECTED,
      cfg(640) => NLW_bar_decoder_cfg_640_UNCONNECTED,
      cfg(639) => NLW_bar_decoder_cfg_639_UNCONNECTED,
      cfg(638) => NLW_bar_decoder_cfg_638_UNCONNECTED,
      cfg(637) => NLW_bar_decoder_cfg_637_UNCONNECTED,
      cfg(636) => NLW_bar_decoder_cfg_636_UNCONNECTED,
      cfg(635) => NLW_bar_decoder_cfg_635_UNCONNECTED,
      cfg(634) => NLW_bar_decoder_cfg_634_UNCONNECTED,
      cfg(633) => NLW_bar_decoder_cfg_633_UNCONNECTED,
      cfg(632) => NLW_bar_decoder_cfg_632_UNCONNECTED,
      cfg(631) => NLW_bar_decoder_cfg_631_UNCONNECTED,
      cfg(630) => NLW_bar_decoder_cfg_630_UNCONNECTED,
      cfg(629) => NLW_bar_decoder_cfg_629_UNCONNECTED,
      cfg(628) => NLW_bar_decoder_cfg_628_UNCONNECTED,
      cfg(627) => NLW_bar_decoder_cfg_627_UNCONNECTED,
      cfg(626) => NLW_bar_decoder_cfg_626_UNCONNECTED,
      cfg(625) => NLW_bar_decoder_cfg_625_UNCONNECTED,
      cfg(624) => NLW_bar_decoder_cfg_624_UNCONNECTED,
      cfg(623) => NLW_bar_decoder_cfg_623_UNCONNECTED,
      cfg(622) => NLW_bar_decoder_cfg_622_UNCONNECTED,
      cfg(621) => NLW_bar_decoder_cfg_621_UNCONNECTED,
      cfg(620) => NLW_bar_decoder_cfg_620_UNCONNECTED,
      cfg(619) => NLW_bar_decoder_cfg_619_UNCONNECTED,
      cfg(618) => NLW_bar_decoder_cfg_618_UNCONNECTED,
      cfg(617) => NLW_bar_decoder_cfg_617_UNCONNECTED,
      cfg(616) => NLW_bar_decoder_cfg_616_UNCONNECTED,
      cfg(615) => NLW_bar_decoder_cfg_615_UNCONNECTED,
      cfg(614) => NLW_bar_decoder_cfg_614_UNCONNECTED,
      cfg(613) => NLW_bar_decoder_cfg_613_UNCONNECTED,
      cfg(612) => NLW_bar_decoder_cfg_612_UNCONNECTED,
      cfg(611) => NLW_bar_decoder_cfg_611_UNCONNECTED,
      cfg(610) => NLW_bar_decoder_cfg_610_UNCONNECTED,
      cfg(609) => NLW_bar_decoder_cfg_609_UNCONNECTED,
      cfg(608) => NLW_bar_decoder_cfg_608_UNCONNECTED,
      cfg(607) => NLW_bar_decoder_cfg_607_UNCONNECTED,
      cfg(606) => NLW_bar_decoder_cfg_606_UNCONNECTED,
      cfg(605) => NLW_bar_decoder_cfg_605_UNCONNECTED,
      cfg(604) => NLW_bar_decoder_cfg_604_UNCONNECTED,
      cfg(603) => NLW_bar_decoder_cfg_603_UNCONNECTED,
      cfg(602) => NLW_bar_decoder_cfg_602_UNCONNECTED,
      cfg(601) => NLW_bar_decoder_cfg_601_UNCONNECTED,
      cfg(600) => NLW_bar_decoder_cfg_600_UNCONNECTED,
      cfg(599) => NLW_bar_decoder_cfg_599_UNCONNECTED,
      cfg(598) => NLW_bar_decoder_cfg_598_UNCONNECTED,
      cfg(597) => NLW_bar_decoder_cfg_597_UNCONNECTED,
      cfg(596) => NLW_bar_decoder_cfg_596_UNCONNECTED,
      cfg(595) => NLW_bar_decoder_cfg_595_UNCONNECTED,
      cfg(594) => NLW_bar_decoder_cfg_594_UNCONNECTED,
      cfg(593) => NLW_bar_decoder_cfg_593_UNCONNECTED,
      cfg(592) => NLW_bar_decoder_cfg_592_UNCONNECTED,
      cfg(591) => NLW_bar_decoder_cfg_591_UNCONNECTED,
      cfg(590) => NLW_bar_decoder_cfg_590_UNCONNECTED,
      cfg(589) => NLW_bar_decoder_cfg_589_UNCONNECTED,
      cfg(588) => NLW_bar_decoder_cfg_588_UNCONNECTED,
      cfg(587) => NLW_bar_decoder_cfg_587_UNCONNECTED,
      cfg(586) => NLW_bar_decoder_cfg_586_UNCONNECTED,
      cfg(585) => NLW_bar_decoder_cfg_585_UNCONNECTED,
      cfg(584) => NLW_bar_decoder_cfg_584_UNCONNECTED,
      cfg(583) => NLW_bar_decoder_cfg_583_UNCONNECTED,
      cfg(582) => NLW_bar_decoder_cfg_582_UNCONNECTED,
      cfg(581) => NLW_bar_decoder_cfg_581_UNCONNECTED,
      cfg(580) => NLW_bar_decoder_cfg_580_UNCONNECTED,
      cfg(579) => NLW_bar_decoder_cfg_579_UNCONNECTED,
      cfg(578) => NLW_bar_decoder_cfg_578_UNCONNECTED,
      cfg(577) => NLW_bar_decoder_cfg_577_UNCONNECTED,
      cfg(576) => NLW_bar_decoder_cfg_576_UNCONNECTED,
      cfg(575) => NLW_bar_decoder_cfg_575_UNCONNECTED,
      cfg(574) => NLW_bar_decoder_cfg_574_UNCONNECTED,
      cfg(573) => NLW_bar_decoder_cfg_573_UNCONNECTED,
      cfg(572) => NLW_bar_decoder_cfg_572_UNCONNECTED,
      cfg(571) => NLW_bar_decoder_cfg_571_UNCONNECTED,
      cfg(570) => NLW_bar_decoder_cfg_570_UNCONNECTED,
      cfg(569) => NLW_bar_decoder_cfg_569_UNCONNECTED,
      cfg(568) => NLW_bar_decoder_cfg_568_UNCONNECTED,
      cfg(567) => NLW_bar_decoder_cfg_567_UNCONNECTED,
      cfg(566) => NLW_bar_decoder_cfg_566_UNCONNECTED,
      cfg(565) => NLW_bar_decoder_cfg_565_UNCONNECTED,
      cfg(564) => NLW_bar_decoder_cfg_564_UNCONNECTED,
      cfg(563) => NLW_bar_decoder_cfg_563_UNCONNECTED,
      cfg(562) => NLW_bar_decoder_cfg_562_UNCONNECTED,
      cfg(561) => NLW_bar_decoder_cfg_561_UNCONNECTED,
      cfg(560) => NLW_bar_decoder_cfg_560_UNCONNECTED,
      cfg(559) => NLW_bar_decoder_cfg_559_UNCONNECTED,
      cfg(558) => NLW_bar_decoder_cfg_558_UNCONNECTED,
      cfg(557) => NLW_bar_decoder_cfg_557_UNCONNECTED,
      cfg(556) => NLW_bar_decoder_cfg_556_UNCONNECTED,
      cfg(555) => NLW_bar_decoder_cfg_555_UNCONNECTED,
      cfg(554) => NLW_bar_decoder_cfg_554_UNCONNECTED,
      cfg(553) => NLW_bar_decoder_cfg_553_UNCONNECTED,
      cfg(552) => NLW_bar_decoder_cfg_552_UNCONNECTED,
      cfg(551) => NLW_bar_decoder_cfg_551_UNCONNECTED,
      cfg(550) => NLW_bar_decoder_cfg_550_UNCONNECTED,
      cfg(549) => NLW_bar_decoder_cfg_549_UNCONNECTED,
      cfg(548) => NLW_bar_decoder_cfg_548_UNCONNECTED,
      cfg(547) => NLW_bar_decoder_cfg_547_UNCONNECTED,
      cfg(546) => NLW_bar_decoder_cfg_546_UNCONNECTED,
      cfg(545) => NLW_bar_decoder_cfg_545_UNCONNECTED,
      cfg(544) => NLW_bar_decoder_cfg_544_UNCONNECTED,
      cfg(543) => NLW_bar_decoder_cfg_543_UNCONNECTED,
      cfg(542) => NLW_bar_decoder_cfg_542_UNCONNECTED,
      cfg(541) => NLW_bar_decoder_cfg_541_UNCONNECTED,
      cfg(540) => NLW_bar_decoder_cfg_540_UNCONNECTED,
      cfg(539) => NLW_bar_decoder_cfg_539_UNCONNECTED,
      cfg(538) => NLW_bar_decoder_cfg_538_UNCONNECTED,
      cfg(537) => NLW_bar_decoder_cfg_537_UNCONNECTED,
      cfg(536) => NLW_bar_decoder_cfg_536_UNCONNECTED,
      cfg(535) => NLW_bar_decoder_cfg_535_UNCONNECTED,
      cfg(534) => NLW_bar_decoder_cfg_534_UNCONNECTED,
      cfg(533) => NLW_bar_decoder_cfg_533_UNCONNECTED,
      cfg(532) => NLW_bar_decoder_cfg_532_UNCONNECTED,
      cfg(531) => NLW_bar_decoder_cfg_531_UNCONNECTED,
      cfg(530) => NLW_bar_decoder_cfg_530_UNCONNECTED,
      cfg(529) => NLW_bar_decoder_cfg_529_UNCONNECTED,
      cfg(528) => NLW_bar_decoder_cfg_528_UNCONNECTED,
      cfg(527) => NLW_bar_decoder_cfg_527_UNCONNECTED,
      cfg(526) => NLW_bar_decoder_cfg_526_UNCONNECTED,
      cfg(525) => NLW_bar_decoder_cfg_525_UNCONNECTED,
      cfg(524) => NLW_bar_decoder_cfg_524_UNCONNECTED,
      cfg(523) => NLW_bar_decoder_cfg_523_UNCONNECTED,
      cfg(522) => NLW_bar_decoder_cfg_522_UNCONNECTED,
      cfg(521) => NLW_bar_decoder_cfg_521_UNCONNECTED,
      cfg(520) => NLW_bar_decoder_cfg_520_UNCONNECTED,
      cfg(519) => NLW_bar_decoder_cfg_519_UNCONNECTED,
      cfg(518) => NLW_bar_decoder_cfg_518_UNCONNECTED,
      cfg(517) => NLW_bar_decoder_cfg_517_UNCONNECTED,
      cfg(516) => NLW_bar_decoder_cfg_516_UNCONNECTED,
      cfg(515) => NLW_bar_decoder_cfg_515_UNCONNECTED,
      cfg(514) => NLW_bar_decoder_cfg_514_UNCONNECTED,
      cfg(513) => NLW_bar_decoder_cfg_513_UNCONNECTED,
      cfg(512) => NLW_bar_decoder_cfg_512_UNCONNECTED,
      cfg(511) => NLW_bar_decoder_cfg_511_UNCONNECTED,
      cfg(510) => NLW_bar_decoder_cfg_510_UNCONNECTED,
      cfg(509) => NLW_bar_decoder_cfg_509_UNCONNECTED,
      cfg(508) => NLW_bar_decoder_cfg_508_UNCONNECTED,
      cfg(507) => NLW_bar_decoder_cfg_507_UNCONNECTED,
      cfg(506) => NLW_bar_decoder_cfg_506_UNCONNECTED,
      cfg(505) => NLW_bar_decoder_cfg_505_UNCONNECTED,
      cfg(504) => NLW_bar_decoder_cfg_504_UNCONNECTED,
      cfg(503) => NLW_bar_decoder_cfg_503_UNCONNECTED,
      cfg(502) => NLW_bar_decoder_cfg_502_UNCONNECTED,
      cfg(501) => NLW_bar_decoder_cfg_501_UNCONNECTED,
      cfg(500) => NLW_bar_decoder_cfg_500_UNCONNECTED,
      cfg(499) => NLW_bar_decoder_cfg_499_UNCONNECTED,
      cfg(498) => NLW_bar_decoder_cfg_498_UNCONNECTED,
      cfg(497) => NLW_bar_decoder_cfg_497_UNCONNECTED,
      cfg(496) => NLW_bar_decoder_cfg_496_UNCONNECTED,
      cfg(495) => NLW_bar_decoder_cfg_495_UNCONNECTED,
      cfg(494) => NLW_bar_decoder_cfg_494_UNCONNECTED,
      cfg(493) => NLW_bar_decoder_cfg_493_UNCONNECTED,
      cfg(492) => NLW_bar_decoder_cfg_492_UNCONNECTED,
      cfg(491) => NLW_bar_decoder_cfg_491_UNCONNECTED,
      cfg(490) => NLW_bar_decoder_cfg_490_UNCONNECTED,
      cfg(489) => NLW_bar_decoder_cfg_489_UNCONNECTED,
      cfg(488) => NLW_bar_decoder_cfg_488_UNCONNECTED,
      cfg(487) => NLW_bar_decoder_cfg_487_UNCONNECTED,
      cfg(486) => NLW_bar_decoder_cfg_486_UNCONNECTED,
      cfg(485) => NLW_bar_decoder_cfg_485_UNCONNECTED,
      cfg(484) => NLW_bar_decoder_cfg_484_UNCONNECTED,
      cfg(483) => NLW_bar_decoder_cfg_483_UNCONNECTED,
      cfg(482) => NLW_bar_decoder_cfg_482_UNCONNECTED,
      cfg(481) => NLW_bar_decoder_cfg_481_UNCONNECTED,
      cfg(480) => NLW_bar_decoder_cfg_480_UNCONNECTED,
      cfg(479) => NLW_bar_decoder_cfg_479_UNCONNECTED,
      cfg(478) => NLW_bar_decoder_cfg_478_UNCONNECTED,
      cfg(477) => NLW_bar_decoder_cfg_477_UNCONNECTED,
      cfg(476) => NLW_bar_decoder_cfg_476_UNCONNECTED,
      cfg(475) => NLW_bar_decoder_cfg_475_UNCONNECTED,
      cfg(474) => NLW_bar_decoder_cfg_474_UNCONNECTED,
      cfg(473) => NLW_bar_decoder_cfg_473_UNCONNECTED,
      cfg(472) => NLW_bar_decoder_cfg_472_UNCONNECTED,
      cfg(471) => NLW_bar_decoder_cfg_471_UNCONNECTED,
      cfg(470) => NLW_bar_decoder_cfg_470_UNCONNECTED,
      cfg(469) => NLW_bar_decoder_cfg_469_UNCONNECTED,
      cfg(468) => NLW_bar_decoder_cfg_468_UNCONNECTED,
      cfg(467) => NLW_bar_decoder_cfg_467_UNCONNECTED,
      cfg(466) => NLW_bar_decoder_cfg_466_UNCONNECTED,
      cfg(465) => NLW_bar_decoder_cfg_465_UNCONNECTED,
      cfg(464) => NLW_bar_decoder_cfg_464_UNCONNECTED,
      cfg(463) => NLW_bar_decoder_cfg_463_UNCONNECTED,
      cfg(462) => NLW_bar_decoder_cfg_462_UNCONNECTED,
      cfg(461) => NLW_bar_decoder_cfg_461_UNCONNECTED,
      cfg(460) => NLW_bar_decoder_cfg_460_UNCONNECTED,
      cfg(459) => NLW_bar_decoder_cfg_459_UNCONNECTED,
      cfg(458) => NLW_bar_decoder_cfg_458_UNCONNECTED,
      cfg(457) => NLW_bar_decoder_cfg_457_UNCONNECTED,
      cfg(456) => NLW_bar_decoder_cfg_456_UNCONNECTED,
      cfg(455) => NLW_bar_decoder_cfg_455_UNCONNECTED,
      cfg(454) => NLW_bar_decoder_cfg_454_UNCONNECTED,
      cfg(453) => NLW_bar_decoder_cfg_453_UNCONNECTED,
      cfg(452) => NLW_bar_decoder_cfg_452_UNCONNECTED,
      cfg(451) => NLW_bar_decoder_cfg_451_UNCONNECTED,
      cfg(450) => NLW_bar_decoder_cfg_450_UNCONNECTED,
      cfg(449) => NLW_bar_decoder_cfg_449_UNCONNECTED,
      cfg(448) => NLW_bar_decoder_cfg_448_UNCONNECTED,
      cfg(447) => NLW_bar_decoder_cfg_447_UNCONNECTED,
      cfg(446) => NLW_bar_decoder_cfg_446_UNCONNECTED,
      cfg(445) => NLW_bar_decoder_cfg_445_UNCONNECTED,
      cfg(444) => NLW_bar_decoder_cfg_444_UNCONNECTED,
      cfg(443) => NLW_bar_decoder_cfg_443_UNCONNECTED,
      cfg(442) => NLW_bar_decoder_cfg_442_UNCONNECTED,
      cfg(441) => NLW_bar_decoder_cfg_441_UNCONNECTED,
      cfg(440) => NLW_bar_decoder_cfg_440_UNCONNECTED,
      cfg(439) => NLW_bar_decoder_cfg_439_UNCONNECTED,
      cfg(438) => NLW_bar_decoder_cfg_438_UNCONNECTED,
      cfg(437) => NLW_bar_decoder_cfg_437_UNCONNECTED,
      cfg(436) => NLW_bar_decoder_cfg_436_UNCONNECTED,
      cfg(435) => NLW_bar_decoder_cfg_435_UNCONNECTED,
      cfg(434) => NLW_bar_decoder_cfg_434_UNCONNECTED,
      cfg(433) => NLW_bar_decoder_cfg_433_UNCONNECTED,
      cfg(432) => NLW_bar_decoder_cfg_432_UNCONNECTED,
      cfg(431) => NLW_bar_decoder_cfg_431_UNCONNECTED,
      cfg(430) => NLW_bar_decoder_cfg_430_UNCONNECTED,
      cfg(429) => NLW_bar_decoder_cfg_429_UNCONNECTED,
      cfg(428) => NLW_bar_decoder_cfg_428_UNCONNECTED,
      cfg(427) => NLW_bar_decoder_cfg_427_UNCONNECTED,
      cfg(426) => NLW_bar_decoder_cfg_426_UNCONNECTED,
      cfg(425) => NLW_bar_decoder_cfg_425_UNCONNECTED,
      cfg(424) => NLW_bar_decoder_cfg_424_UNCONNECTED,
      cfg(423) => NLW_bar_decoder_cfg_423_UNCONNECTED,
      cfg(422) => NLW_bar_decoder_cfg_422_UNCONNECTED,
      cfg(421) => NLW_bar_decoder_cfg_421_UNCONNECTED,
      cfg(420) => NLW_bar_decoder_cfg_420_UNCONNECTED,
      cfg(419) => NLW_bar_decoder_cfg_419_UNCONNECTED,
      cfg(418) => NLW_bar_decoder_cfg_418_UNCONNECTED,
      cfg(417) => NLW_bar_decoder_cfg_417_UNCONNECTED,
      cfg(416) => NLW_bar_decoder_cfg_416_UNCONNECTED,
      cfg(415) => NLW_bar_decoder_cfg_415_UNCONNECTED,
      cfg(414) => NLW_bar_decoder_cfg_414_UNCONNECTED,
      cfg(413) => NLW_bar_decoder_cfg_413_UNCONNECTED,
      cfg(412) => NLW_bar_decoder_cfg_412_UNCONNECTED,
      cfg(411) => NLW_bar_decoder_cfg_411_UNCONNECTED,
      cfg(410) => NLW_bar_decoder_cfg_410_UNCONNECTED,
      cfg(409) => NLW_bar_decoder_cfg_409_UNCONNECTED,
      cfg(408) => NLW_bar_decoder_cfg_408_UNCONNECTED,
      cfg(407) => NLW_bar_decoder_cfg_407_UNCONNECTED,
      cfg(406) => NLW_bar_decoder_cfg_406_UNCONNECTED,
      cfg(405) => NLW_bar_decoder_cfg_405_UNCONNECTED,
      cfg(404) => NLW_bar_decoder_cfg_404_UNCONNECTED,
      cfg(403) => NLW_bar_decoder_cfg_403_UNCONNECTED,
      cfg(402) => NLW_bar_decoder_cfg_402_UNCONNECTED,
      cfg(401) => NLW_bar_decoder_cfg_401_UNCONNECTED,
      cfg(400) => NLW_bar_decoder_cfg_400_UNCONNECTED,
      cfg(399) => NLW_bar_decoder_cfg_399_UNCONNECTED,
      cfg(398) => NLW_bar_decoder_cfg_398_UNCONNECTED,
      cfg(397) => NLW_bar_decoder_cfg_397_UNCONNECTED,
      cfg(396) => NLW_bar_decoder_cfg_396_UNCONNECTED,
      cfg(395) => NLW_bar_decoder_cfg_395_UNCONNECTED,
      cfg(394) => NLW_bar_decoder_cfg_394_UNCONNECTED,
      cfg(393) => NLW_bar_decoder_cfg_393_UNCONNECTED,
      cfg(392) => NLW_bar_decoder_cfg_392_UNCONNECTED,
      cfg(391) => NLW_bar_decoder_cfg_391_UNCONNECTED,
      cfg(390) => NLW_bar_decoder_cfg_390_UNCONNECTED,
      cfg(389) => NLW_bar_decoder_cfg_389_UNCONNECTED,
      cfg(388) => NLW_bar_decoder_cfg_388_UNCONNECTED,
      cfg(387) => NLW_bar_decoder_cfg_387_UNCONNECTED,
      cfg(386) => NLW_bar_decoder_cfg_386_UNCONNECTED,
      cfg(385) => NLW_bar_decoder_cfg_385_UNCONNECTED,
      cfg(384) => NLW_bar_decoder_cfg_384_UNCONNECTED,
      cfg(383) => NLW_bar_decoder_cfg_383_UNCONNECTED,
      cfg(382) => NLW_bar_decoder_cfg_382_UNCONNECTED,
      cfg(381) => NLW_bar_decoder_cfg_381_UNCONNECTED,
      cfg(380) => NLW_bar_decoder_cfg_380_UNCONNECTED,
      cfg(379) => NLW_bar_decoder_cfg_379_UNCONNECTED,
      cfg(378) => NLW_bar_decoder_cfg_378_UNCONNECTED,
      cfg(377) => NLW_bar_decoder_cfg_377_UNCONNECTED,
      cfg(376) => NLW_bar_decoder_cfg_376_UNCONNECTED,
      cfg(375) => NLW_bar_decoder_cfg_375_UNCONNECTED,
      cfg(374) => NLW_bar_decoder_cfg_374_UNCONNECTED,
      cfg(373) => NLW_bar_decoder_cfg_373_UNCONNECTED,
      cfg(372) => NLW_bar_decoder_cfg_372_UNCONNECTED,
      cfg(371) => NLW_bar_decoder_cfg_371_UNCONNECTED,
      cfg(370) => NLW_bar_decoder_cfg_370_UNCONNECTED,
      cfg(369) => NLW_bar_decoder_cfg_369_UNCONNECTED,
      cfg(368) => NLW_bar_decoder_cfg_368_UNCONNECTED,
      cfg(367) => NLW_bar_decoder_cfg_367_UNCONNECTED,
      cfg(366) => NLW_bar_decoder_cfg_366_UNCONNECTED,
      cfg(365) => NLW_bar_decoder_cfg_365_UNCONNECTED,
      cfg(364) => NLW_bar_decoder_cfg_364_UNCONNECTED,
      cfg(363) => NLW_bar_decoder_cfg_363_UNCONNECTED,
      cfg(362) => NLW_bar_decoder_cfg_362_UNCONNECTED,
      cfg(361) => NLW_bar_decoder_cfg_361_UNCONNECTED,
      cfg(360) => NLW_bar_decoder_cfg_360_UNCONNECTED,
      cfg(359) => NLW_bar_decoder_cfg_359_UNCONNECTED,
      cfg(358) => NLW_bar_decoder_cfg_358_UNCONNECTED,
      cfg(357) => NLW_bar_decoder_cfg_357_UNCONNECTED,
      cfg(356) => NLW_bar_decoder_cfg_356_UNCONNECTED,
      cfg(355) => NLW_bar_decoder_cfg_355_UNCONNECTED,
      cfg(354) => NLW_bar_decoder_cfg_354_UNCONNECTED,
      cfg(353) => NLW_bar_decoder_cfg_353_UNCONNECTED,
      cfg(352) => NLW_bar_decoder_cfg_352_UNCONNECTED,
      cfg(351) => NLW_bar_decoder_cfg_351_UNCONNECTED,
      cfg(350) => NLW_bar_decoder_cfg_350_UNCONNECTED,
      cfg(349) => NLW_bar_decoder_cfg_349_UNCONNECTED,
      cfg(348) => NLW_bar_decoder_cfg_348_UNCONNECTED,
      cfg(347) => NLW_bar_decoder_cfg_347_UNCONNECTED,
      cfg(346) => NLW_bar_decoder_cfg_346_UNCONNECTED,
      cfg(345) => NLW_bar_decoder_cfg_345_UNCONNECTED,
      cfg(344) => NLW_bar_decoder_cfg_344_UNCONNECTED,
      cfg(343) => NLW_bar_decoder_cfg_343_UNCONNECTED,
      cfg(342) => NLW_bar_decoder_cfg_342_UNCONNECTED,
      cfg(341) => NLW_bar_decoder_cfg_341_UNCONNECTED,
      cfg(340) => NLW_bar_decoder_cfg_340_UNCONNECTED,
      cfg(339) => cfg_temp(339),
      cfg(338) => cfg_temp(339),
      cfg(337) => cfg_temp(339),
      cfg(336) => cfg_temp(339),
      cfg(335) => cfg_temp(339),
      cfg(334) => cfg_temp(339),
      cfg(333) => cfg_temp(339),
      cfg(332) => cfg_temp(339),
      cfg(331) => cfg_temp(339),
      cfg(330) => cfg_temp(339),
      cfg(329) => cfg_temp(339),
      cfg(328) => cfg_temp(339),
      cfg(327) => cfg_temp(339),
      cfg(326) => cfg_temp(339),
      cfg(325) => cfg_temp(339),
      cfg(324) => cfg_temp(339),
      cfg(323) => cfg_temp(339),
      cfg(322) => cfg_temp(339),
      cfg(321) => cfg_temp(339),
      cfg(320) => NLW_bar_decoder_cfg_320_UNCONNECTED,
      cfg(319) => NLW_bar_decoder_cfg_319_UNCONNECTED,
      cfg(318) => NLW_bar_decoder_cfg_318_UNCONNECTED,
      cfg(317) => NLW_bar_decoder_cfg_317_UNCONNECTED,
      cfg(316) => NLW_bar_decoder_cfg_316_UNCONNECTED,
      cfg(315) => NLW_bar_decoder_cfg_315_UNCONNECTED,
      cfg(314) => NLW_bar_decoder_cfg_314_UNCONNECTED,
      cfg(313) => NLW_bar_decoder_cfg_313_UNCONNECTED,
      cfg(312) => NLW_bar_decoder_cfg_312_UNCONNECTED,
      cfg(311) => NLW_bar_decoder_cfg_311_UNCONNECTED,
      cfg(310) => NLW_bar_decoder_cfg_310_UNCONNECTED,
      cfg(309) => NLW_bar_decoder_cfg_309_UNCONNECTED,
      cfg(308) => NLW_bar_decoder_cfg_308_UNCONNECTED,
      cfg(307) => NLW_bar_decoder_cfg_307_UNCONNECTED,
      cfg(306) => NLW_bar_decoder_cfg_306_UNCONNECTED,
      cfg(305) => NLW_bar_decoder_cfg_305_UNCONNECTED,
      cfg(304) => NLW_bar_decoder_cfg_304_UNCONNECTED,
      cfg(303) => NLW_bar_decoder_cfg_303_UNCONNECTED,
      cfg(302) => NLW_bar_decoder_cfg_302_UNCONNECTED,
      cfg(301) => NLW_bar_decoder_cfg_301_UNCONNECTED,
      cfg(300) => NLW_bar_decoder_cfg_300_UNCONNECTED,
      cfg(299) => NLW_bar_decoder_cfg_299_UNCONNECTED,
      cfg(298) => NLW_bar_decoder_cfg_298_UNCONNECTED,
      cfg(297) => NLW_bar_decoder_cfg_297_UNCONNECTED,
      cfg(296) => NLW_bar_decoder_cfg_296_UNCONNECTED,
      cfg(295) => NLW_bar_decoder_cfg_295_UNCONNECTED,
      cfg(294) => NLW_bar_decoder_cfg_294_UNCONNECTED,
      cfg(293) => NLW_bar_decoder_cfg_293_UNCONNECTED,
      cfg(292) => NLW_bar_decoder_cfg_292_UNCONNECTED,
      cfg(291) => NLW_bar_decoder_cfg_291_UNCONNECTED,
      cfg(290) => NLW_bar_decoder_cfg_290_UNCONNECTED,
      cfg(289) => NLW_bar_decoder_cfg_289_UNCONNECTED,
      cfg(288) => NLW_bar_decoder_cfg_288_UNCONNECTED,
      cfg(287) => NLW_bar_decoder_cfg_287_UNCONNECTED,
      cfg(286) => NLW_bar_decoder_cfg_286_UNCONNECTED,
      cfg(285) => NLW_bar_decoder_cfg_285_UNCONNECTED,
      cfg(284) => NLW_bar_decoder_cfg_284_UNCONNECTED,
      cfg(283) => NLW_bar_decoder_cfg_283_UNCONNECTED,
      cfg(282) => NLW_bar_decoder_cfg_282_UNCONNECTED,
      cfg(281) => NLW_bar_decoder_cfg_281_UNCONNECTED,
      cfg(280) => NLW_bar_decoder_cfg_280_UNCONNECTED,
      cfg(279) => NLW_bar_decoder_cfg_279_UNCONNECTED,
      cfg(278) => NLW_bar_decoder_cfg_278_UNCONNECTED,
      cfg(277) => NLW_bar_decoder_cfg_277_UNCONNECTED,
      cfg(276) => NLW_bar_decoder_cfg_276_UNCONNECTED,
      cfg(275) => NLW_bar_decoder_cfg_275_UNCONNECTED,
      cfg(274) => NLW_bar_decoder_cfg_274_UNCONNECTED,
      cfg(273) => NLW_bar_decoder_cfg_273_UNCONNECTED,
      cfg(272) => NLW_bar_decoder_cfg_272_UNCONNECTED,
      cfg(271) => NLW_bar_decoder_cfg_271_UNCONNECTED,
      cfg(270) => NLW_bar_decoder_cfg_270_UNCONNECTED,
      cfg(269) => NLW_bar_decoder_cfg_269_UNCONNECTED,
      cfg(268) => NLW_bar_decoder_cfg_268_UNCONNECTED,
      cfg(267) => NLW_bar_decoder_cfg_267_UNCONNECTED,
      cfg(266) => NLW_bar_decoder_cfg_266_UNCONNECTED,
      cfg(265) => NLW_bar_decoder_cfg_265_UNCONNECTED,
      cfg(264) => NLW_bar_decoder_cfg_264_UNCONNECTED,
      cfg(263) => NLW_bar_decoder_cfg_263_UNCONNECTED,
      cfg(262) => NLW_bar_decoder_cfg_262_UNCONNECTED,
      cfg(261) => NLW_bar_decoder_cfg_261_UNCONNECTED,
      cfg(260) => NLW_bar_decoder_cfg_260_UNCONNECTED,
      cfg(259) => NLW_bar_decoder_cfg_259_UNCONNECTED,
      cfg(258) => NLW_bar_decoder_cfg_258_UNCONNECTED,
      cfg(257) => NLW_bar_decoder_cfg_257_UNCONNECTED,
      cfg(256) => NLW_bar_decoder_cfg_256_UNCONNECTED,
      cfg(255) => cfg_temp(339),
      cfg(254) => cfg_temp(339),
      cfg(253) => cfg_temp(339),
      cfg(252) => cfg_temp(339),
      cfg(251) => cfg_temp(339),
      cfg(250) => cfg_temp(339),
      cfg(249) => cfg_temp(339),
      cfg(248) => cfg_temp(339),
      cfg(247) => cfg_temp(339),
      cfg(246) => cfg_temp(339),
      cfg(245) => cfg_temp(339),
      cfg(244) => cfg_temp(339),
      cfg(243) => cfg_temp(339),
      cfg(242) => cfg_temp(339),
      cfg(241) => cfg_temp(339),
      cfg(240) => cfg_temp(339),
      cfg(239) => cfg_temp(339),
      cfg(238) => cfg_temp(339),
      cfg(237) => cfg_temp(339),
      cfg(236) => cfg_temp(339),
      cfg(235) => cfg_temp(339),
      cfg(234) => cfg_temp(339),
      cfg(233) => cfg_temp(339),
      cfg(232) => cfg_temp(339),
      cfg(231) => cfg_temp(339),
      cfg(230) => cfg_temp(339),
      cfg(229) => cfg_temp(339),
      cfg(228) => cfg_temp(339),
      cfg(227) => cfg_temp(339),
      cfg(226) => cfg_temp(339),
      cfg(225) => cfg_temp(339),
      cfg(224) => cfg_temp(339),
      cfg(223) => cfg_temp(339),
      cfg(222) => cfg_temp(339),
      cfg(221) => cfg_temp(339),
      cfg(220) => cfg_temp(339),
      cfg(219) => cfg_temp(339),
      cfg(218) => cfg_temp(339),
      cfg(217) => cfg_temp(339),
      cfg(216) => cfg_temp(339),
      cfg(215) => cfg_temp(339),
      cfg(214) => cfg_temp(339),
      cfg(213) => cfg_temp(339),
      cfg(212) => cfg_temp(339),
      cfg(211) => cfg_temp(339),
      cfg(210) => cfg_temp(339),
      cfg(209) => cfg_temp(339),
      cfg(208) => cfg_temp(339),
      cfg(207) => cfg_temp(339),
      cfg(206) => cfg_temp(339),
      cfg(205) => cfg_temp(339),
      cfg(204) => cfg_temp(339),
      cfg(203) => cfg_temp(339),
      cfg(202) => cfg_temp(339),
      cfg(201) => cfg_temp(339),
      cfg(200) => cfg_temp(339),
      cfg(199) => cfg_temp(339),
      cfg(198) => cfg_temp(339),
      cfg(197) => cfg_temp(339),
      cfg(196) => cfg_temp(339),
      cfg(195) => cfg_temp(339),
      cfg(194) => cfg_temp(339),
      cfg(193) => cfg_temp(339),
      cfg(192) => cfg_temp(339),
      cfg(191) => cfg_temp(339),
      cfg(190) => cfg_temp(339),
      cfg(189) => cfg_temp(339),
      cfg(188) => cfg_temp(339),
      cfg(187) => cfg_temp(339),
      cfg(186) => cfg_temp(339),
      cfg(185) => cfg_temp(339),
      cfg(184) => cfg_temp(339),
      cfg(183) => cfg_temp(339),
      cfg(182) => cfg_temp(339),
      cfg(181) => cfg_temp(339),
      cfg(180) => cfg_temp(339),
      cfg(179) => cfg_temp(339),
      cfg(178) => cfg_temp(339),
      cfg(177) => cfg_temp(339),
      cfg(176) => cfg_temp(339),
      cfg(175) => cfg_temp(339),
      cfg(174) => cfg_temp(339),
      cfg(173) => cfg_temp(339),
      cfg(172) => cfg_temp(339),
      cfg(171) => cfg_temp(339),
      cfg(170) => cfg_temp(339),
      cfg(169) => cfg_temp(339),
      cfg(168) => cfg_temp(339),
      cfg(167) => cfg_temp(339),
      cfg(166) => cfg_temp(339),
      cfg(165) => cfg_temp(339),
      cfg(164) => cfg_temp(339),
      cfg(163) => cfg_temp(339),
      cfg(162) => cfg_temp(339),
      cfg(161) => cfg_temp(339),
      cfg(160) => cfg_temp(339),
      cfg(159) => cfg_temp(339),
      cfg(158) => cfg_temp(339),
      cfg(157) => cfg_temp(339),
      cfg(156) => cfg_temp(339),
      cfg(155) => cfg_temp(339),
      cfg(154) => cfg_temp(339),
      cfg(153) => cfg_temp(339),
      cfg(152) => cfg_temp(339),
      cfg(151) => cfg_temp(339),
      cfg(150) => cfg_temp(339),
      cfg(149) => cfg_temp(339),
      cfg(148) => cfg_temp(339),
      cfg(147) => cfg_temp(339),
      cfg(146) => cfg_temp(339),
      cfg(145) => cfg_temp(339),
      cfg(144) => cfg_temp(339),
      cfg(143) => cfg_temp(339),
      cfg(142) => cfg_temp(339),
      cfg(141) => cfg_temp(339),
      cfg(140) => cfg_temp(339),
      cfg(139) => cfg_temp(339),
      cfg(138) => cfg_temp(339),
      cfg(137) => cfg_temp(339),
      cfg(136) => cfg_temp(339),
      cfg(135) => cfg_temp(339),
      cfg(134) => cfg_temp(339),
      cfg(133) => cfg_temp(339),
      cfg(132) => cfg_temp(339),
      cfg(131) => cfg_temp(339),
      cfg(130) => cfg_temp(339),
      cfg(129) => cfg_temp(339),
      cfg(128) => cfg_temp(339),
      cfg(127) => NLW_bar_decoder_cfg_127_UNCONNECTED,
      cfg(126) => NLW_bar_decoder_cfg_126_UNCONNECTED,
      cfg(125) => NLW_bar_decoder_cfg_125_UNCONNECTED,
      cfg(124) => NLW_bar_decoder_cfg_124_UNCONNECTED,
      cfg(123) => NLW_bar_decoder_cfg_123_UNCONNECTED,
      cfg(122) => NLW_bar_decoder_cfg_122_UNCONNECTED,
      cfg(121) => NLW_bar_decoder_cfg_121_UNCONNECTED,
      cfg(120) => NLW_bar_decoder_cfg_120_UNCONNECTED,
      cfg(119) => NLW_bar_decoder_cfg_119_UNCONNECTED,
      cfg(118) => NLW_bar_decoder_cfg_118_UNCONNECTED,
      cfg(117) => NLW_bar_decoder_cfg_117_UNCONNECTED,
      cfg(116) => cfg_temp(339),
      cfg(115) => cfg_temp(339),
      cfg(114) => cfg_temp(339),
      cfg(113) => cfg_temp(339),
      cfg(112) => cfg_temp(339),
      cfg(111) => cfg_temp(339),
      cfg(110) => cfg_temp(339),
      cfg(109) => cfg_temp(339),
      cfg(108) => cfg_temp(339),
      cfg(107) => cfg_temp(339),
      cfg(106) => cfg_temp(339),
      cfg(105) => cfg_temp(339),
      cfg(104) => cfg_temp(339),
      cfg(103) => cfg_temp(339),
      cfg(102) => cfg_temp(339),
      cfg(101) => cfg_temp(339),
      cfg(100) => cfg_temp(339),
      cfg(99) => cfg_temp(339),
      cfg(98) => cfg_temp(339),
      cfg(97) => cfg_temp(339),
      cfg(96) => cfg_temp(339),
      cfg(95) => NLW_bar_decoder_cfg_95_UNCONNECTED,
      cfg(94) => NLW_bar_decoder_cfg_94_UNCONNECTED,
      cfg(93) => NLW_bar_decoder_cfg_93_UNCONNECTED,
      cfg(92) => NLW_bar_decoder_cfg_92_UNCONNECTED,
      cfg(91) => NLW_bar_decoder_cfg_91_UNCONNECTED,
      cfg(90) => NLW_bar_decoder_cfg_90_UNCONNECTED,
      cfg(89) => NLW_bar_decoder_cfg_89_UNCONNECTED,
      cfg(88) => NLW_bar_decoder_cfg_88_UNCONNECTED,
      cfg(87) => NLW_bar_decoder_cfg_87_UNCONNECTED,
      cfg(86) => NLW_bar_decoder_cfg_86_UNCONNECTED,
      cfg(85) => NLW_bar_decoder_cfg_85_UNCONNECTED,
      cfg(84) => cfg_temp(339),
      cfg(83) => cfg_temp(339),
      cfg(82) => cfg_temp(339),
      cfg(81) => cfg_temp(339),
      cfg(80) => cfg_temp(339),
      cfg(79) => cfg_temp(339),
      cfg(78) => cfg_temp(339),
      cfg(77) => cfg_temp(339),
      cfg(76) => cfg_temp(339),
      cfg(75) => cfg_temp(339),
      cfg(74) => cfg_temp(339),
      cfg(73) => cfg_temp(339),
      cfg(72) => cfg_temp(339),
      cfg(71) => cfg_temp(339),
      cfg(70) => cfg_temp(339),
      cfg(69) => cfg_temp(339),
      cfg(68) => cfg_temp(339),
      cfg(67) => cfg_temp(339),
      cfg(66) => cfg_temp(339),
      cfg(65) => cfg_temp(339),
      cfg(64) => cfg_temp(339),
      cfg(63) => NLW_bar_decoder_cfg_63_UNCONNECTED,
      cfg(62) => NLW_bar_decoder_cfg_62_UNCONNECTED,
      cfg(61) => NLW_bar_decoder_cfg_61_UNCONNECTED,
      cfg(60) => NLW_bar_decoder_cfg_60_UNCONNECTED,
      cfg(59) => NLW_bar_decoder_cfg_59_UNCONNECTED,
      cfg(58) => NLW_bar_decoder_cfg_58_UNCONNECTED,
      cfg(57) => NLW_bar_decoder_cfg_57_UNCONNECTED,
      cfg(56) => NLW_bar_decoder_cfg_56_UNCONNECTED,
      cfg(55) => NLW_bar_decoder_cfg_55_UNCONNECTED,
      cfg(54) => NLW_bar_decoder_cfg_54_UNCONNECTED,
      cfg(53) => NLW_bar_decoder_cfg_53_UNCONNECTED,
      cfg(52) => NLW_bar_decoder_cfg_52_UNCONNECTED,
      cfg(51) => NLW_bar_decoder_cfg_51_UNCONNECTED,
      cfg(50) => NLW_bar_decoder_cfg_50_UNCONNECTED,
      cfg(49) => NLW_bar_decoder_cfg_49_UNCONNECTED,
      cfg(48) => NLW_bar_decoder_cfg_48_UNCONNECTED,
      cfg(47) => NLW_bar_decoder_cfg_47_UNCONNECTED,
      cfg(46) => NLW_bar_decoder_cfg_46_UNCONNECTED,
      cfg(45) => NLW_bar_decoder_cfg_45_UNCONNECTED,
      cfg(44) => NLW_bar_decoder_cfg_44_UNCONNECTED,
      cfg(43) => NLW_bar_decoder_cfg_43_UNCONNECTED,
      cfg(42) => NLW_bar_decoder_cfg_42_UNCONNECTED,
      cfg(41) => NLW_bar_decoder_cfg_41_UNCONNECTED,
      cfg(40) => NLW_bar_decoder_cfg_40_UNCONNECTED,
      cfg(39) => NLW_bar_decoder_cfg_39_UNCONNECTED,
      cfg(38) => NLW_bar_decoder_cfg_38_UNCONNECTED,
      cfg(37) => NLW_bar_decoder_cfg_37_UNCONNECTED,
      cfg(36) => NLW_bar_decoder_cfg_36_UNCONNECTED,
      cfg(35) => NLW_bar_decoder_cfg_35_UNCONNECTED,
      cfg(34) => NLW_bar_decoder_cfg_34_UNCONNECTED,
      cfg(33) => NLW_bar_decoder_cfg_33_UNCONNECTED,
      cfg(32) => NLW_bar_decoder_cfg_32_UNCONNECTED,
      cfg(31) => NLW_bar_decoder_cfg_31_UNCONNECTED,
      cfg(30) => NLW_bar_decoder_cfg_30_UNCONNECTED,
      cfg(29) => NLW_bar_decoder_cfg_29_UNCONNECTED,
      cfg(28) => NLW_bar_decoder_cfg_28_UNCONNECTED,
      cfg(27) => NLW_bar_decoder_cfg_27_UNCONNECTED,
      cfg(26) => NLW_bar_decoder_cfg_26_UNCONNECTED,
      cfg(25) => NLW_bar_decoder_cfg_25_UNCONNECTED,
      cfg(24) => NLW_bar_decoder_cfg_24_UNCONNECTED,
      cfg(23) => NLW_bar_decoder_cfg_23_UNCONNECTED,
      cfg(22) => NLW_bar_decoder_cfg_22_UNCONNECTED,
      cfg(21) => NLW_bar_decoder_cfg_21_UNCONNECTED,
      cfg(20) => NLW_bar_decoder_cfg_20_UNCONNECTED,
      cfg(19) => NLW_bar_decoder_cfg_19_UNCONNECTED,
      cfg(18) => NLW_bar_decoder_cfg_18_UNCONNECTED,
      cfg(17) => NLW_bar_decoder_cfg_17_UNCONNECTED,
      cfg(16) => NLW_bar_decoder_cfg_16_UNCONNECTED,
      cfg(15) => NLW_bar_decoder_cfg_15_UNCONNECTED,
      cfg(14) => NLW_bar_decoder_cfg_14_UNCONNECTED,
      cfg(13) => NLW_bar_decoder_cfg_13_UNCONNECTED,
      cfg(12) => NLW_bar_decoder_cfg_12_UNCONNECTED,
      cfg(11) => NLW_bar_decoder_cfg_11_UNCONNECTED,
      cfg(10) => NLW_bar_decoder_cfg_10_UNCONNECTED,
      cfg(9) => NLW_bar_decoder_cfg_9_UNCONNECTED,
      cfg(8) => NLW_bar_decoder_cfg_8_UNCONNECTED,
      cfg(7) => NLW_bar_decoder_cfg_7_UNCONNECTED,
      cfg(6) => NLW_bar_decoder_cfg_6_UNCONNECTED,
      cfg(5) => NLW_bar_decoder_cfg_5_UNCONNECTED,
      cfg(4) => NLW_bar_decoder_cfg_4_UNCONNECTED,
      cfg(3) => NLW_bar_decoder_cfg_3_UNCONNECTED,
      cfg(2) => NLW_bar_decoder_cfg_2_UNCONNECTED,
      cfg(1) => NLW_bar_decoder_cfg_1_UNCONNECTED,
      cfg(0) => NLW_bar_decoder_cfg_0_UNCONNECTED,
      function_num(2) => cfg_function_number(2),
      function_num(1) => cfg_function_number(1),
      function_num(0) => cfg_function_number(0)
    );
  arb_inst : pcie_blk_ll_arb
    port map (
      clk => clk,
      rst_n => rst_n,
      llk_rx_dst_cont_req_n => llk_rx_dst_cont_req_n,
      trn_rnp_ok_n => NLW_arb_inst_trn_rnp_ok_n_UNCONNECTED,
      fifo_pcpl_ok => fifo_pcpl_ok,
      fifo_np_ok => fifo_np_ok,
      llk_rx_dst_req_n => llk_rx_dst_req_n,
      llk_rx_src_last_req_n => llk_rx_src_last_req_n,
      trn_rcpl_streaming_n => NLW_arb_inst_trn_rcpl_streaming_n_UNCONNECTED,
      fifo_pcpl_req => fifo_pcpl_req,
      fifo_np_req => fifo_np_req,
      cpl_tlp_cntr_inc => rx_ch_credits_received_inc,
      llk_rx_ch_fifo(1) => llk_rx_ch_fifo(1),
      llk_rx_ch_fifo(0) => llk_rx_ch_fifo(0),
      llk_rx_ch_tc(2) => llk_rx_ch_tc(2),
      llk_rx_ch_tc(1) => llk_rx_ch_tc(1),
      llk_rx_ch_tc(0) => llk_rx_ch_tc(0),
      llk_rx_ch_posted_available_n(7) => llk_rx_ch_posted_available_n(7),
      llk_rx_ch_posted_available_n(6) => llk_rx_ch_posted_available_n(6),
      llk_rx_ch_posted_available_n(5) => llk_rx_ch_posted_available_n(5),
      llk_rx_ch_posted_available_n(4) => llk_rx_ch_posted_available_n(4),
      llk_rx_ch_posted_available_n(3) => llk_rx_ch_posted_available_n(3),
      llk_rx_ch_posted_available_n(2) => llk_rx_ch_posted_available_n(2),
      llk_rx_ch_posted_available_n(1) => llk_rx_ch_posted_available_n(1),
      llk_rx_ch_posted_available_n(0) => llk_rx_ch_posted_available_n(0),
      llk_rx_ch_non_posted_available_n(7) => llk_rx_ch_non_posted_available_n(7),
      llk_rx_ch_non_posted_available_n(6) => llk_rx_ch_non_posted_available_n(6),
      llk_rx_ch_non_posted_available_n(5) => llk_rx_ch_non_posted_available_n(5),
      llk_rx_ch_non_posted_available_n(4) => llk_rx_ch_non_posted_available_n(4),
      llk_rx_ch_non_posted_available_n(3) => llk_rx_ch_non_posted_available_n(3),
      llk_rx_ch_non_posted_available_n(2) => llk_rx_ch_non_posted_available_n(2),
      llk_rx_ch_non_posted_available_n(1) => llk_rx_ch_non_posted_available_n(1),
      llk_rx_ch_non_posted_available_n(0) => llk_rx_ch_non_posted_available_n(0),
      llk_rx_ch_completion_available_n(7) => llk_rx_ch_completion_available_n(7),
      llk_rx_ch_completion_available_n(6) => llk_rx_ch_completion_available_n(6),
      llk_rx_ch_completion_available_n(5) => llk_rx_ch_completion_available_n(5),
      llk_rx_ch_completion_available_n(4) => llk_rx_ch_completion_available_n(4),
      llk_rx_ch_completion_available_n(3) => llk_rx_ch_completion_available_n(3),
      llk_rx_ch_completion_available_n(2) => llk_rx_ch_completion_available_n(2),
      llk_rx_ch_completion_available_n(1) => llk_rx_ch_completion_available_n(1),
      llk_rx_ch_completion_available_n(0) => llk_rx_ch_completion_available_n(0),
      llk_rx_preferred_type(15) => llk_rx_preferred_type(15),
      llk_rx_preferred_type(14) => llk_rx_preferred_type(14),
      llk_rx_preferred_type(13) => llk_rx_preferred_type(13),
      llk_rx_preferred_type(12) => llk_rx_preferred_type(12),
      llk_rx_preferred_type(11) => llk_rx_preferred_type(11),
      llk_rx_preferred_type(10) => llk_rx_preferred_type(10),
      llk_rx_preferred_type(9) => llk_rx_preferred_type(9),
      llk_rx_preferred_type(8) => llk_rx_preferred_type(8),
      llk_rx_preferred_type(7) => llk_rx_preferred_type(7),
      llk_rx_preferred_type(6) => llk_rx_preferred_type(6),
      llk_rx_preferred_type(5) => llk_rx_preferred_type(5),
      llk_rx_preferred_type(4) => llk_rx_preferred_type(4),
      llk_rx_preferred_type(3) => llk_rx_preferred_type(3),
      llk_rx_preferred_type(2) => llk_rx_preferred_type(2),
      llk_rx_preferred_type(1) => llk_rx_preferred_type(1),
      llk_rx_preferred_type(0) => llk_rx_preferred_type(0),
      cpl_tlp_cntr(7) => rx_ch_credits_received(7),
      cpl_tlp_cntr(6) => rx_ch_credits_received(6),
      cpl_tlp_cntr(5) => rx_ch_credits_received(5),
      cpl_tlp_cntr(4) => rx_ch_credits_received(4),
      cpl_tlp_cntr(3) => rx_ch_credits_received(3),
      cpl_tlp_cntr(2) => rx_ch_credits_received(2),
      cpl_tlp_cntr(1) => rx_ch_credits_received(1),
      cpl_tlp_cntr(0) => rx_ch_credits_received(0)
    );
  snk_inst : tlm_rx_data_snk
    port map (
      legacy_mode_i => cfg_temp(339),
      reset_i => rst_n_inv,
      rem_i => snk_inst_not0003,
      locked_o => snk_locked,
      rem_o => snk_rem,
      td_ecrc_trim_i => NLW_snk_inst_td_ecrc_trim_i_UNCONNECTED,
      check_rdev_o => check_rdev,
      check_mem32_o => check_mem32,
      stat_tlp_cpl_ep_o => rx_err_cpl_ep,
      pm_turn_off_o => NLW_snk_inst_pm_turn_off_o_UNCONNECTED,
      pm_suspend_req_i => cfg_temp(339),
      vend_msg_o => snk_vend_msg,
      ext_cfg_access_i => cfg_temp(339),
      legacy_cfg_access_i => cfg_temp(339),
      pm_set_slot_pwr_o => NLW_snk_inst_pm_set_slot_pwr_o_UNCONNECTED,
      cfg_o => snk_cfg,
      src_rdy_i => snk_inst_not0004,
      check_mem64_o => check_mem64,
      check_rhit_i => check_rhit,
      src_rdy_o => snk_src_rdy,
      fc_unuse_o => NLW_snk_inst_fc_unuse_o_UNCONNECTED,
      stat_tlp_cpl_abort_o => rx_err_cpl_abort,
      cpl_o => snk_cpl,
      fc_use_np_o => NLW_snk_inst_fc_use_np_o_UNCONNECTED,
      rid_o => snk_rid,
      dsc_o => snk_src_dsc,
      eof_i => snk_inst_not0002,
      err_tlp_ur_lock_o => err_tlp_ur_lock,
      eof_o => snk_eof,
      hotplug_msg_enable_i => cfg_temp(339),
      err_tlp_malformed_o => err_tlp_malformed,
      rhit_bar_lat3_i => check_rhit_bar_lat3,
      stat_tlp_ep_o => rx_err_ep,
      check_rbus_o => check_rbus,
      fc_use_cpl_o => NLW_snk_inst_fc_use_cpl_o_UNCONNECTED,
      clk_i => clk,
      np_o => snk_np,
      fc_use_p_o => NLW_snk_inst_fc_use_p_o_UNCONNECTED,
      bar_src_rdy_o => snk_bar_src_rdy,
      preeof_o => snk_preeof,
      vc_hit_o => NLW_snk_inst_vc_hit_o_UNCONNECTED,
      err_tlp_p_o => err_tlp_p,
      check_rio_o => check_rio,
      sof_i => snk_inst_not0001,
      stat_tlp_cpl_ur_o => rx_err_cpl_ur,
      sof_o => snk_sof,
      err_tlp_ur_o => err_tlp_ur,
      src_dsc_i => cfg_temp(339),
      check_rfun_o => check_rfun,
      err_tlp_uc_o => err_tlp_uc,
      pm_as_nak_l1_o => NLW_snk_inst_pm_as_nak_l1_o_UNCONNECTED,
      pm_set_slot_pwr_data_o(9) => NLW_snk_inst_pm_set_slot_pwr_data_o_9_UNCONNECTED,
      pm_set_slot_pwr_data_o(8) => NLW_snk_inst_pm_set_slot_pwr_data_o_8_UNCONNECTED,
      pm_set_slot_pwr_data_o(7) => NLW_snk_inst_pm_set_slot_pwr_data_o_7_UNCONNECTED,
      pm_set_slot_pwr_data_o(6) => NLW_snk_inst_pm_set_slot_pwr_data_o_6_UNCONNECTED,
      pm_set_slot_pwr_data_o(5) => NLW_snk_inst_pm_set_slot_pwr_data_o_5_UNCONNECTED,
      pm_set_slot_pwr_data_o(4) => NLW_snk_inst_pm_set_slot_pwr_data_o_4_UNCONNECTED,
      pm_set_slot_pwr_data_o(3) => NLW_snk_inst_pm_set_slot_pwr_data_o_3_UNCONNECTED,
      pm_set_slot_pwr_data_o(2) => NLW_snk_inst_pm_set_slot_pwr_data_o_2_UNCONNECTED,
      pm_set_slot_pwr_data_o(1) => NLW_snk_inst_pm_set_slot_pwr_data_o_1_UNCONNECTED,
      pm_set_slot_pwr_data_o(0) => NLW_snk_inst_pm_set_slot_pwr_data_o_0_UNCONNECTED,
      fc_use_data_o(5) => NLW_snk_inst_fc_use_data_o_5_UNCONNECTED,
      fc_use_data_o(4) => NLW_snk_inst_fc_use_data_o_4_UNCONNECTED,
      fc_use_data_o(3) => NLW_snk_inst_fc_use_data_o_3_UNCONNECTED,
      fc_use_data_o(2) => NLW_snk_inst_fc_use_data_o_2_UNCONNECTED,
      fc_use_data_o(1) => NLW_snk_inst_fc_use_data_o_1_UNCONNECTED,
      fc_use_data_o(0) => NLW_snk_inst_fc_use_data_o_0_UNCONNECTED,
      check_raddr_o(63) => check_raddr(63),
      check_raddr_o(62) => check_raddr(62),
      check_raddr_o(61) => check_raddr(61),
      check_raddr_o(60) => check_raddr(60),
      check_raddr_o(59) => check_raddr(59),
      check_raddr_o(58) => check_raddr(58),
      check_raddr_o(57) => check_raddr(57),
      check_raddr_o(56) => check_raddr(56),
      check_raddr_o(55) => check_raddr(55),
      check_raddr_o(54) => check_raddr(54),
      check_raddr_o(53) => check_raddr(53),
      check_raddr_o(52) => check_raddr(52),
      check_raddr_o(51) => check_raddr(51),
      check_raddr_o(50) => check_raddr(50),
      check_raddr_o(49) => check_raddr(49),
      check_raddr_o(48) => check_raddr(48),
      check_raddr_o(47) => check_raddr(47),
      check_raddr_o(46) => check_raddr(46),
      check_raddr_o(45) => check_raddr(45),
      check_raddr_o(44) => check_raddr(44),
      check_raddr_o(43) => check_raddr(43),
      check_raddr_o(42) => check_raddr(42),
      check_raddr_o(41) => check_raddr(41),
      check_raddr_o(40) => check_raddr(40),
      check_raddr_o(39) => check_raddr(39),
      check_raddr_o(38) => check_raddr(38),
      check_raddr_o(37) => check_raddr(37),
      check_raddr_o(36) => check_raddr(36),
      check_raddr_o(35) => check_raddr(35),
      check_raddr_o(34) => check_raddr(34),
      check_raddr_o(33) => check_raddr(33),
      check_raddr_o(32) => check_raddr(32),
      check_raddr_o(31) => check_raddr(31),
      check_raddr_o(30) => check_raddr(30),
      check_raddr_o(29) => check_raddr(29),
      check_raddr_o(28) => check_raddr(28),
      check_raddr_o(27) => check_raddr(27),
      check_raddr_o(26) => check_raddr(26),
      check_raddr_o(25) => check_raddr(25),
      check_raddr_o(24) => check_raddr(24),
      check_raddr_o(23) => check_raddr(23),
      check_raddr_o(22) => check_raddr(22),
      check_raddr_o(21) => check_raddr(21),
      check_raddr_o(20) => check_raddr(20),
      check_raddr_o(19) => check_raddr(19),
      check_raddr_o(18) => check_raddr(18),
      check_raddr_o(17) => check_raddr(17),
      check_raddr_o(16) => check_raddr(16),
      check_raddr_o(15) => check_raddr(15),
      check_raddr_o(14) => check_raddr(14),
      check_raddr_o(13) => check_raddr(13),
      check_raddr_o(12) => check_raddr(12),
      check_raddr_o(11) => check_raddr(11),
      check_raddr_o(10) => check_raddr(10),
      check_raddr_o(9) => check_raddr(9),
      check_raddr_o(8) => check_raddr(8),
      check_raddr_o(7) => check_raddr(7),
      check_raddr_o(6) => check_raddr(6),
      check_raddr_o(5) => check_raddr(5),
      check_raddr_o(4) => check_raddr(4),
      check_raddr_o(3) => check_raddr(3),
      check_raddr_o(2) => check_raddr(2),
      check_raddr_o(1) => check_raddr(1),
      check_raddr_o(0) => check_raddr(0),
      bar_o(6) => snk_bar_6_Q,
      bar_o(5) => NLW_snk_inst_bar_o_5_UNCONNECTED,
      bar_o(4) => NLW_snk_inst_bar_o_4_UNCONNECTED,
      bar_o(3) => NLW_snk_inst_bar_o_3_UNCONNECTED,
      bar_o(2) => NLW_snk_inst_bar_o_2_UNCONNECTED,
      bar_o(1) => snk_bar_1_Q,
      bar_o(0) => snk_bar_0_Q,
      d_o(63) => snk_d(63),
      d_o(62) => snk_d(62),
      d_o(61) => snk_d(61),
      d_o(60) => snk_d(60),
      d_o(59) => snk_d(59),
      d_o(58) => snk_d(58),
      d_o(57) => snk_d(57),
      d_o(56) => snk_d(56),
      d_o(55) => snk_d(55),
      d_o(54) => snk_d(54),
      d_o(53) => snk_d(53),
      d_o(52) => snk_d(52),
      d_o(51) => snk_d(51),
      d_o(50) => snk_d(50),
      d_o(49) => snk_d(49),
      d_o(48) => snk_d(48),
      d_o(47) => snk_d(47),
      d_o(46) => snk_d(46),
      d_o(45) => snk_d(45),
      d_o(44) => snk_d(44),
      d_o(43) => snk_d(43),
      d_o(42) => snk_d(42),
      d_o(41) => snk_d(41),
      d_o(40) => snk_d(40),
      d_o(39) => snk_d(39),
      d_o(38) => snk_d(38),
      d_o(37) => snk_d(37),
      d_o(36) => snk_d(36),
      d_o(35) => snk_d(35),
      d_o(34) => snk_d(34),
      d_o(33) => snk_d(33),
      d_o(32) => snk_d(32),
      d_o(31) => snk_d(31),
      d_o(30) => snk_d(30),
      d_o(29) => snk_d(29),
      d_o(28) => snk_d(28),
      d_o(27) => snk_d(27),
      d_o(26) => snk_d(26),
      d_o(25) => snk_d(25),
      d_o(24) => snk_d(24),
      d_o(23) => snk_d(23),
      d_o(22) => snk_d(22),
      d_o(21) => snk_d(21),
      d_o(20) => snk_d(20),
      d_o(19) => snk_d(19),
      d_o(18) => snk_d(18),
      d_o(17) => snk_d(17),
      d_o(16) => snk_d(16),
      d_o(15) => snk_d(15),
      d_o(14) => snk_d(14),
      d_o(13) => snk_d(13),
      d_o(12) => snk_d(12),
      d_o(11) => snk_d(11),
      d_o(10) => snk_d(10),
      d_o(9) => snk_d(9),
      d_o(8) => snk_d(8),
      d_o(7) => snk_d(7),
      d_o(6) => snk_d(6),
      d_o(5) => snk_d(5),
      d_o(4) => snk_d(4),
      d_o(3) => snk_d(3),
      d_o(2) => snk_d(2),
      d_o(1) => snk_d(1),
      d_o(0) => snk_d(0),
      err_tlp_cpl_header_o(47) => err_tlp_cpl_header(47),
      err_tlp_cpl_header_o(46) => err_tlp_cpl_header(46),
      err_tlp_cpl_header_o(45) => err_tlp_cpl_header(45),
      err_tlp_cpl_header_o(44) => err_tlp_cpl_header(44),
      err_tlp_cpl_header_o(43) => err_tlp_cpl_header(43),
      err_tlp_cpl_header_o(42) => err_tlp_cpl_header(42),
      err_tlp_cpl_header_o(41) => err_tlp_cpl_header(41),
      err_tlp_cpl_header_o(40) => err_tlp_cpl_header(40),
      err_tlp_cpl_header_o(39) => err_tlp_cpl_header(39),
      err_tlp_cpl_header_o(38) => err_tlp_cpl_header(38),
      err_tlp_cpl_header_o(37) => err_tlp_cpl_header(37),
      err_tlp_cpl_header_o(36) => err_tlp_cpl_header(36),
      err_tlp_cpl_header_o(35) => err_tlp_cpl_header(35),
      err_tlp_cpl_header_o(34) => err_tlp_cpl_header(34),
      err_tlp_cpl_header_o(33) => err_tlp_cpl_header(33),
      err_tlp_cpl_header_o(32) => err_tlp_cpl_header(32),
      err_tlp_cpl_header_o(31) => err_tlp_cpl_header(31),
      err_tlp_cpl_header_o(30) => err_tlp_cpl_header(30),
      err_tlp_cpl_header_o(29) => err_tlp_cpl_header(29),
      err_tlp_cpl_header_o(28) => err_tlp_cpl_header(28),
      err_tlp_cpl_header_o(27) => err_tlp_cpl_header(27),
      err_tlp_cpl_header_o(26) => err_tlp_cpl_header(26),
      err_tlp_cpl_header_o(25) => err_tlp_cpl_header(25),
      err_tlp_cpl_header_o(24) => err_tlp_cpl_header(24),
      err_tlp_cpl_header_o(23) => err_tlp_cpl_header(23),
      err_tlp_cpl_header_o(22) => err_tlp_cpl_header(22),
      err_tlp_cpl_header_o(21) => err_tlp_cpl_header(21),
      err_tlp_cpl_header_o(20) => err_tlp_cpl_header(20),
      err_tlp_cpl_header_o(19) => err_tlp_cpl_header(19),
      err_tlp_cpl_header_o(18) => err_tlp_cpl_header(18),
      err_tlp_cpl_header_o(17) => err_tlp_cpl_header(17),
      err_tlp_cpl_header_o(16) => err_tlp_cpl_header(16),
      err_tlp_cpl_header_o(15) => err_tlp_cpl_header(15),
      err_tlp_cpl_header_o(14) => err_tlp_cpl_header(14),
      err_tlp_cpl_header_o(13) => err_tlp_cpl_header(13),
      err_tlp_cpl_header_o(12) => err_tlp_cpl_header(12),
      err_tlp_cpl_header_o(11) => err_tlp_cpl_header(11),
      err_tlp_cpl_header_o(10) => err_tlp_cpl_header(10),
      err_tlp_cpl_header_o(9) => err_tlp_cpl_header(9),
      err_tlp_cpl_header_o(8) => err_tlp_cpl_header(8),
      err_tlp_cpl_header_o(7) => err_tlp_cpl_header(7),
      err_tlp_cpl_header_o(6) => err_tlp_cpl_header(6),
      err_tlp_cpl_header_o(5) => err_tlp_cpl_header(5),
      err_tlp_cpl_header_o(4) => err_tlp_cpl_header(4),
      err_tlp_cpl_header_o(3) => err_tlp_cpl_header(3),
      err_tlp_cpl_header_o(2) => err_tlp_cpl_header(2),
      err_tlp_cpl_header_o(1) => err_tlp_cpl_header(1),
      err_tlp_cpl_header_o(0) => err_tlp_cpl_header(0),
      check_rhit_bar_i(6) => check_rhit_bar(6),
      check_rhit_bar_i(5) => check_rhit_bar(5),
      check_rhit_bar_i(4) => check_rhit_bar(4),
      check_rhit_bar_i(3) => check_rhit_bar(3),
      check_rhit_bar_i(2) => check_rhit_bar(2),
      check_rhit_bar_i(1) => check_rhit_bar(1),
      check_rhit_bar_i(0) => check_rhit_bar(0),
      max_payload_i(2) => max_payload_size(2),
      max_payload_i(1) => max_payload_size(1),
      max_payload_i(0) => max_payload_size(0),
      d_i(63) => NlwRenamedSig_OI_llk_rx_data_d(63),
      d_i(62) => NlwRenamedSig_OI_llk_rx_data_d(62),
      d_i(61) => NlwRenamedSig_OI_llk_rx_data_d(61),
      d_i(60) => NlwRenamedSig_OI_llk_rx_data_d(60),
      d_i(59) => NlwRenamedSig_OI_llk_rx_data_d(59),
      d_i(58) => NlwRenamedSig_OI_llk_rx_data_d(58),
      d_i(57) => NlwRenamedSig_OI_llk_rx_data_d(57),
      d_i(56) => NlwRenamedSig_OI_llk_rx_data_d(56),
      d_i(55) => NlwRenamedSig_OI_llk_rx_data_d(55),
      d_i(54) => NlwRenamedSig_OI_llk_rx_data_d(54),
      d_i(53) => NlwRenamedSig_OI_llk_rx_data_d(53),
      d_i(52) => NlwRenamedSig_OI_llk_rx_data_d(52),
      d_i(51) => NlwRenamedSig_OI_llk_rx_data_d(51),
      d_i(50) => NlwRenamedSig_OI_llk_rx_data_d(50),
      d_i(49) => NlwRenamedSig_OI_llk_rx_data_d(49),
      d_i(48) => NlwRenamedSig_OI_llk_rx_data_d(48),
      d_i(47) => NlwRenamedSig_OI_llk_rx_data_d(47),
      d_i(46) => NlwRenamedSig_OI_llk_rx_data_d(46),
      d_i(45) => NlwRenamedSig_OI_llk_rx_data_d(45),
      d_i(44) => NlwRenamedSig_OI_llk_rx_data_d(44),
      d_i(43) => NlwRenamedSig_OI_llk_rx_data_d(43),
      d_i(42) => NlwRenamedSig_OI_llk_rx_data_d(42),
      d_i(41) => NlwRenamedSig_OI_llk_rx_data_d(41),
      d_i(40) => NlwRenamedSig_OI_llk_rx_data_d(40),
      d_i(39) => NlwRenamedSig_OI_llk_rx_data_d(39),
      d_i(38) => NlwRenamedSig_OI_llk_rx_data_d(38),
      d_i(37) => NlwRenamedSig_OI_llk_rx_data_d(37),
      d_i(36) => NlwRenamedSig_OI_llk_rx_data_d(36),
      d_i(35) => NlwRenamedSig_OI_llk_rx_data_d(35),
      d_i(34) => NlwRenamedSig_OI_llk_rx_data_d(34),
      d_i(33) => NlwRenamedSig_OI_llk_rx_data_d(33),
      d_i(32) => NlwRenamedSig_OI_llk_rx_data_d(32),
      d_i(31) => NlwRenamedSig_OI_llk_rx_data_d(31),
      d_i(30) => NlwRenamedSig_OI_llk_rx_data_d(30),
      d_i(29) => NlwRenamedSig_OI_llk_rx_data_d(29),
      d_i(28) => NlwRenamedSig_OI_llk_rx_data_d(28),
      d_i(27) => NlwRenamedSig_OI_llk_rx_data_d(27),
      d_i(26) => NlwRenamedSig_OI_llk_rx_data_d(26),
      d_i(25) => NlwRenamedSig_OI_llk_rx_data_d(25),
      d_i(24) => NlwRenamedSig_OI_llk_rx_data_d(24),
      d_i(23) => NlwRenamedSig_OI_llk_rx_data_d(23),
      d_i(22) => NlwRenamedSig_OI_llk_rx_data_d(22),
      d_i(21) => NlwRenamedSig_OI_llk_rx_data_d(21),
      d_i(20) => NlwRenamedSig_OI_llk_rx_data_d(20),
      d_i(19) => NlwRenamedSig_OI_llk_rx_data_d(19),
      d_i(18) => NlwRenamedSig_OI_llk_rx_data_d(18),
      d_i(17) => NlwRenamedSig_OI_llk_rx_data_d(17),
      d_i(16) => NlwRenamedSig_OI_llk_rx_data_d(16),
      d_i(15) => NlwRenamedSig_OI_llk_rx_data_d(15),
      d_i(14) => NlwRenamedSig_OI_llk_rx_data_d(14),
      d_i(13) => NlwRenamedSig_OI_llk_rx_data_d(13),
      d_i(12) => NlwRenamedSig_OI_llk_rx_data_d(12),
      d_i(11) => NlwRenamedSig_OI_llk_rx_data_d(11),
      d_i(10) => NlwRenamedSig_OI_llk_rx_data_d(10),
      d_i(9) => NlwRenamedSig_OI_llk_rx_data_d(9),
      d_i(8) => NlwRenamedSig_OI_llk_rx_data_d(8),
      d_i(7) => NlwRenamedSig_OI_llk_rx_data_d(7),
      d_i(6) => NlwRenamedSig_OI_llk_rx_data_d(6),
      d_i(5) => NlwRenamedSig_OI_llk_rx_data_d(5),
      d_i(4) => NlwRenamedSig_OI_llk_rx_data_d(4),
      d_i(3) => NlwRenamedSig_OI_llk_rx_data_d(3),
      d_i(2) => NlwRenamedSig_OI_llk_rx_data_d(2),
      d_i(1) => NlwRenamedSig_OI_llk_rx_data_d(1),
      d_i(0) => NlwRenamedSig_OI_llk_rx_data_d(0)
    );
  fifo_inst : pcie_blk_ll_oqbqfifo
    port map (
      clk => clk,
      rst_n => rst_n,
      fifo_rem => snk_rem,
      trn_rsof => trn_rsof,
      trn_rdst_rdy => fifo_inst_not0000,
      fifo_pcpl_ok => fifo_pcpl_ok,
      fifo_np_ok => fifo_np_ok,
      trn_reof => trn_reof,
      trn_rsrc_rdy => trn_rsrc_rdy,
      fifo_preeof => snk_preeof,
      fifo_wren => snk_src_rdy,
      fifo_sof => Q_and0000,
      fifo_dsc => snk_src_dsc,
      trn_rnp_ok => NLW_fifo_inst_trn_rnp_ok_UNCONNECTED,
      fifo_eof => snk_eof,
      trn_rerrfwd => trn_rerrfwd,
      fifo_pcpl_req => fifo_pcpl_req,
      fifo_np => snk_np_reg_28058,
      fifo_np_req => fifo_np_req,
      fifo_pcpl_abort => NLW_fifo_inst_fifo_pcpl_abort_UNCONNECTED,
      fifo_np_abort => NLW_fifo_inst_fifo_np_abort_UNCONNECTED,
      trn_rbar_hit(6) => NLW_fifo_inst_trn_rbar_hit_6_UNCONNECTED,
      trn_rbar_hit(5) => NLW_fifo_inst_trn_rbar_hit_5_UNCONNECTED,
      trn_rbar_hit(4) => NLW_fifo_inst_trn_rbar_hit_4_UNCONNECTED,
      trn_rbar_hit(3) => NLW_fifo_inst_trn_rbar_hit_3_UNCONNECTED,
      trn_rbar_hit(2) => NLW_fifo_inst_trn_rbar_hit_2_UNCONNECTED,
      trn_rbar_hit(1) => trn_rbar_hit(1),
      trn_rbar_hit(0) => trn_rbar_hit(0),
      trn_rrem(7) => NLW_fifo_inst_trn_rrem_7_UNCONNECTED,
      trn_rrem(6) => NLW_fifo_inst_trn_rrem_6_UNCONNECTED,
      trn_rrem(5) => NLW_fifo_inst_trn_rrem_5_UNCONNECTED,
      trn_rrem(4) => NLW_fifo_inst_trn_rrem_4_UNCONNECTED,
      trn_rrem(3) => NLW_fifo_inst_trn_rrem_3_UNCONNECTED,
      trn_rrem(2) => NLW_fifo_inst_trn_rrem_2_UNCONNECTED,
      trn_rrem(1) => NLW_fifo_inst_trn_rrem_1_UNCONNECTED,
      trn_rrem(0) => trn_rrem(0),
      trn_rd(63) => trn_rd(63),
      trn_rd(62) => trn_rd(62),
      trn_rd(61) => trn_rd(61),
      trn_rd(60) => trn_rd(60),
      trn_rd(59) => trn_rd(59),
      trn_rd(58) => trn_rd(58),
      trn_rd(57) => trn_rd(57),
      trn_rd(56) => trn_rd(56),
      trn_rd(55) => trn_rd(55),
      trn_rd(54) => trn_rd(54),
      trn_rd(53) => trn_rd(53),
      trn_rd(52) => trn_rd(52),
      trn_rd(51) => trn_rd(51),
      trn_rd(50) => trn_rd(50),
      trn_rd(49) => trn_rd(49),
      trn_rd(48) => trn_rd(48),
      trn_rd(47) => trn_rd(47),
      trn_rd(46) => trn_rd(46),
      trn_rd(45) => trn_rd(45),
      trn_rd(44) => trn_rd(44),
      trn_rd(43) => trn_rd(43),
      trn_rd(42) => trn_rd(42),
      trn_rd(41) => trn_rd(41),
      trn_rd(40) => trn_rd(40),
      trn_rd(39) => trn_rd(39),
      trn_rd(38) => trn_rd(38),
      trn_rd(37) => trn_rd(37),
      trn_rd(36) => trn_rd(36),
      trn_rd(35) => trn_rd(35),
      trn_rd(34) => trn_rd(34),
      trn_rd(33) => trn_rd(33),
      trn_rd(32) => trn_rd(32),
      trn_rd(31) => trn_rd(31),
      trn_rd(30) => trn_rd(30),
      trn_rd(29) => trn_rd(29),
      trn_rd(28) => trn_rd(28),
      trn_rd(27) => trn_rd(27),
      trn_rd(26) => trn_rd(26),
      trn_rd(25) => trn_rd(25),
      trn_rd(24) => trn_rd(24),
      trn_rd(23) => trn_rd(23),
      trn_rd(22) => trn_rd(22),
      trn_rd(21) => trn_rd(21),
      trn_rd(20) => trn_rd(20),
      trn_rd(19) => trn_rd(19),
      trn_rd(18) => trn_rd(18),
      trn_rd(17) => trn_rd(17),
      trn_rd(16) => trn_rd(16),
      trn_rd(15) => trn_rd(15),
      trn_rd(14) => trn_rd(14),
      trn_rd(13) => trn_rd(13),
      trn_rd(12) => trn_rd(12),
      trn_rd(11) => trn_rd(11),
      trn_rd(10) => trn_rd(10),
      trn_rd(9) => trn_rd(9),
      trn_rd(8) => trn_rd(8),
      trn_rd(7) => trn_rd(7),
      trn_rd(6) => trn_rd(6),
      trn_rd(5) => trn_rd(5),
      trn_rd(4) => trn_rd(4),
      trn_rd(3) => trn_rd(3),
      trn_rd(2) => trn_rd(2),
      trn_rd(1) => trn_rd(1),
      trn_rd(0) => trn_rd(0),
      fifo_barenc(3) => snk_barenc(3),
      fifo_barenc(2) => snk_barenc(2),
      fifo_barenc(1) => snk_barenc(1),
      fifo_barenc(0) => snk_barenc(0),
      fifo_data(63) => snk_d(63),
      fifo_data(62) => snk_d(62),
      fifo_data(61) => snk_d(61),
      fifo_data(60) => snk_d(60),
      fifo_data(59) => snk_d(59),
      fifo_data(58) => snk_d(58),
      fifo_data(57) => snk_d(57),
      fifo_data(56) => snk_d(56),
      fifo_data(55) => snk_d(55),
      fifo_data(54) => snk_d(54),
      fifo_data(53) => snk_d(53),
      fifo_data(52) => snk_d(52),
      fifo_data(51) => snk_d(51),
      fifo_data(50) => snk_d(50),
      fifo_data(49) => snk_d(49),
      fifo_data(48) => snk_d(48),
      fifo_data(47) => snk_d(47),
      fifo_data(46) => snk_d(46),
      fifo_data(45) => snk_d(45),
      fifo_data(44) => snk_d(44),
      fifo_data(43) => snk_d(43),
      fifo_data(42) => snk_d(42),
      fifo_data(41) => snk_d(41),
      fifo_data(40) => snk_d(40),
      fifo_data(39) => snk_d(39),
      fifo_data(38) => snk_d(38),
      fifo_data(37) => snk_d(37),
      fifo_data(36) => snk_d(36),
      fifo_data(35) => snk_d(35),
      fifo_data(34) => snk_d(34),
      fifo_data(33) => snk_d(33),
      fifo_data(32) => snk_d(32),
      fifo_data(31) => snk_d(31),
      fifo_data(30) => snk_d(30),
      fifo_data(29) => snk_d(29),
      fifo_data(28) => snk_d(28),
      fifo_data(27) => snk_d(27),
      fifo_data(26) => snk_d(26),
      fifo_data(25) => snk_d(25),
      fifo_data(24) => snk_d(24),
      fifo_data(23) => snk_d(23),
      fifo_data(22) => snk_d(22),
      fifo_data(21) => snk_d(21),
      fifo_data(20) => snk_d(20),
      fifo_data(19) => snk_d(19),
      fifo_data(18) => snk_d(18),
      fifo_data(17) => snk_d(17),
      fifo_data(16) => snk_d(16),
      fifo_data(15) => snk_d(15),
      fifo_data(14) => snk_d(14),
      fifo_data(13) => snk_d(13),
      fifo_data(12) => snk_d(12),
      fifo_data(11) => snk_d(11),
      fifo_data(10) => snk_d(10),
      fifo_data(9) => snk_d(9),
      fifo_data(8) => snk_d(8),
      fifo_data(7) => snk_d(7),
      fifo_data(6) => snk_d(6),
      fifo_data(5) => snk_d(5),
      fifo_data(4) => snk_d(4),
      fifo_data(3) => snk_d(3),
      fifo_data(2) => snk_d(2),
      fifo_data(1) => snk_d(1),
      fifo_data(0) => snk_d(0)
    );
  snk_barenc_mux0000_3_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => snk_bar_6_Q,
      I1 => snk_bar_1_Q,
      O => snk_barenc_mux0000(3)
    );
  snk_barenc_mux0000_1_1 : LUT3
    generic map(
      INIT => X"EB"
    )
    port map (
      I0 => snk_bar_6_Q,
      I1 => snk_bar_1_Q,
      I2 => snk_bar_0_Q,
      O => snk_barenc_mux0000(1)
    );
  Q_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => snk_sof,
      I1 => snk_bar_ok_27972,
      O => Q_and0000
    );
  snk_barenc_mux0000_2_1 : LUT3
    generic map(
      INIT => X"42"
    )
    port map (
      I0 => snk_bar_6_Q,
      I1 => snk_bar_0_Q,
      I2 => snk_bar_1_Q,
      O => snk_barenc_mux0000(2)
    );
  snk_barenc_mux0000_0_1 : LUT3
    generic map(
      INIT => X"C9"
    )
    port map (
      I0 => snk_bar_0_Q,
      I1 => snk_bar_6_Q,
      I2 => snk_bar_1_Q,
      O => snk_barenc_mux0000(0)
    );
  trn_rrem_n_0_1_INV_0 : INV
    port map (
      I => trn_rrem(0),
      O => trn_rrem_n(0)
    );
  trn_rerrfwd_n1_INV_0 : INV
    port map (
      I => trn_rerrfwd,
      O => trn_rerrfwd_n
    );
  trn_rbar_hit_n_1_1_INV_0 : INV
    port map (
      I => trn_rbar_hit(1),
      O => trn_rbar_hit_n(1)
    );
  trn_rbar_hit_n_0_1_INV_0 : INV
    port map (
      I => trn_rbar_hit(0),
      O => trn_rbar_hit_n(0)
    );
  rx_err_ep_n1_INV_0 : INV
    port map (
      I => rx_err_ep,
      O => rx_err_ep_n
    );
  rx_err_cpl_ur_n1_INV_0 : INV
    port map (
      I => rx_err_cpl_ur,
      O => rx_err_cpl_ur_n
    );
  rx_err_cpl_ep_n1_INV_0 : INV
    port map (
      I => rx_err_cpl_ep,
      O => rx_err_cpl_ep_n
    );
  rx_err_cpl_abort_n1_INV_0 : INV
    port map (
      I => rx_err_cpl_abort,
      O => rx_err_cpl_abort_n
    );
  trn_reof_n1_INV_0 : INV
    port map (
      I => trn_reof,
      O => trn_reof_n
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  trn_rsof_n1_INV_0 : INV
    port map (
      I => trn_rsof,
      O => trn_rsof_n
    );
  snk_inst_not00031_INV_0 : INV
    port map (
      I => llk_rx_valid_n_d(0),
      O => snk_inst_not0003
    );
  snk_inst_not00021_INV_0 : INV
    port map (
      I => llk_rx_eof_n_d_27922,
      O => snk_inst_not0002
    );
  snk_inst_not00041_INV_0 : INV
    port map (
      I => llk_rx_src_rdy_n_d_27943,
      O => snk_inst_not0004
    );
  snk_inst_not00011_INV_0 : INV
    port map (
      I => llk_rx_sof_n_d_27940,
      O => snk_inst_not0001
    );
  trn_rsrc_rdy_n1_INV_0 : INV
    port map (
      I => trn_rsrc_rdy,
      O => trn_rsrc_rdy_n
    );
  fifo_inst_not00001_INV_0 : INV
    port map (
      I => trn_rdst_rdy_n,
      O => fifo_inst_not0000
    );
  snk_bar_ok_and00001 : LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      I0 => snk_vend_msg,
      I1 => snk_locked,
      I2 => snk_cfg,
      I3 => snk_rid,
      O => snk_bar_ok_and00001_27974
    );
  snk_bar_ok_and00002 : LUT6
    generic map(
      INIT => X"1111111111111110"
    )
    port map (
      I0 => snk_locked,
      I1 => snk_cfg,
      I2 => snk_vend_msg,
      I3 => snk_bar_6_Q,
      I4 => snk_bar_1_Q,
      I5 => snk_bar_0_Q,
      O => snk_bar_ok_and00002_27975
    );
  snk_bar_ok_and0000_f7 : MUXF7
    port map (
      I0 => snk_bar_ok_and00002_27975,
      I1 => snk_bar_ok_and00001_27974,
      S => snk_cpl,
      O => snk_bar_ok_and0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll_tx is
  port (
    clear_cpl_count : out STD_LOGIC; 
    llk_tx_src_rdy_n : out STD_LOGIC; 
    trn_terrfwd_n : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    trn_pfc_cplh_cl_upd : in STD_LOGIC := 'X'; 
    llk_tx_sop_n : out STD_LOGIC; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    llk_tx_src_dsc_n : out STD_LOGIC; 
    llk_tx_eof_n : out STD_LOGIC; 
    llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tbuf_av_cpl : out STD_LOGIC; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    npd_credit_limited : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    pd_credit_limited : in STD_LOGIC := 'X'; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    llk_tx_eop_n : out STD_LOGIC; 
    cd_credit_limited : in STD_LOGIC := 'X'; 
    llk_tx_sof_n : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    tx_pd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_cplh_cl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_npd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_ch_credits_consumed : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_cd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_npd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_cd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_pd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end pcie_blk_ll_tx;

architecture STRUCTURE of pcie_blk_ll_tx is
  signal Maccum_user_pd_data_credits_in_cy_10_rt_23066 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_cy_6_rt_23073 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_cy_7_rt_23075 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_cy_8_rt_23077 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_cy_9_rt_23079 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_xor_11_rt_23086 : STD_LOGIC; 
  signal Madd_cpl_in_count_add0000_Madd_xor_0_113_23087 : STD_LOGIC; 
  signal Madd_cpl_in_count_add0000_Madd_xor_0_128_23088 : STD_LOGIC; 
  signal Madd_cpl_in_count_add0000_Madd_xor_4_11 : STD_LOGIC; 
  signal Madd_cpl_in_count_add0000_Madd_xor_4_111_23090 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi_23103 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi1_23104 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi2_23105 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi3_23106 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi4_23107 : STD_LOGIC; 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi5_23108 : STD_LOGIC; 
  signal Msub_cpls_buffered_lut_2_Q : STD_LOGIC; 
  signal Msub_cpls_buffered_lut_4_Q : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal block_cnt_0_mux0000 : STD_LOGIC; 
  signal block_cnt_0_mux00001_23162 : STD_LOGIC; 
  signal block_cnt_0_mux00002_23163 : STD_LOGIC; 
  signal block_cnt_1_mux0000 : STD_LOGIC; 
  signal block_fifo_23166 : STD_LOGIC; 
  signal block_fifo_and0000 : STD_LOGIC; 
  signal block_sof_23168 : STD_LOGIC; 
  signal block_sof_mux0000 : STD_LOGIC; 
  signal block_sof_not0001 : STD_LOGIC; 
  signal buf_rd : STD_LOGIC; 
  signal dsc_buf_23183 : STD_LOGIC; 
  signal dsc_buf_not0001 : STD_LOGIC; 
  signal dsc_q1_23185 : STD_LOGIC; 
  signal dsc_q1_mux0000 : STD_LOGIC; 
  signal dsc_q2_23187 : STD_LOGIC; 
  signal dsc_q3_23188 : STD_LOGIC; 
  signal eof_buf_23189 : STD_LOGIC; 
  signal eof_buf_not0001 : STD_LOGIC; 
  signal eof_q1_23191 : STD_LOGIC; 
  signal eof_q1_mux0000 : STD_LOGIC; 
  signal eof_q1_not0001 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_23194 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux0001 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux0001110_23196 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux000149 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux0001491_23198 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux0001492_23199 : STD_LOGIC; 
  signal eof_q1_or_eof_q2_only_mux000161_23200 : STD_LOGIC; 
  signal eof_q2_23201 : STD_LOGIC; 
  signal eof_q2_only_23202 : STD_LOGIC; 
  signal eof_q2_only_mux0000_23203 : STD_LOGIC; 
  signal eof_q3_23204 : STD_LOGIC; 
  signal eof_q3_and0000 : STD_LOGIC; 
  signal eof_q3_only_23206 : STD_LOGIC; 
  signal eof_q3_only_mux0000_23207 : STD_LOGIC; 
  signal fifo_last_and0000 : STD_LOGIC; 
  signal fifo_q2_and0000 : STD_LOGIC; 
  signal fifo_q2_and0007 : STD_LOGIC; 
  signal fifo_q2_or0001 : STD_LOGIC; 
  signal fifo_q2_or00011_23216 : STD_LOGIC; 
  signal fifo_q2_or00012_23217 : STD_LOGIC; 
  signal len_eq1_q2_23221 : STD_LOGIC; 
  signal len_eq1_q2_and0000 : STD_LOGIC; 
  signal len_eq1_q2_and000030_23223 : STD_LOGIC; 
  signal len_eq1_q2_and000066_23224 : STD_LOGIC; 
  signal llk_tlp_halt_23225 : STD_LOGIC; 
  signal llk_tlp_halt_or0000 : STD_LOGIC; 
  signal llk_tlp_halt_or0000150_23227 : STD_LOGIC; 
  signal llk_tlp_halt_or0000167_23228 : STD_LOGIC; 
  signal llk_tlp_halt_or0000196_23229 : STD_LOGIC; 
  signal llk_tlp_halt_or000051_23230 : STD_LOGIC; 
  signal llk_tlp_halt_or000063_23231 : STD_LOGIC; 
  signal llk_tlp_halt_or000095_23232 : STD_LOGIC; 
  signal llk_tx_ch_tc_not0001_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_llk_tx_eop_n : STD_LOGIC; 
  signal llk_tx_src_rdy_n_int : STD_LOGIC; 
  signal pd_credit_limited_inv : STD_LOGIC; 
  signal pd_credits_near_gte_far_23262 : STD_LOGIC; 
  signal pd_credits_near_gte_far_cmp_ge0000 : STD_LOGIC; 
  signal pd_q1_reg_23264 : STD_LOGIC; 
  signal pd_q1_reg_or0000 : STD_LOGIC; 
  signal rem_buf_23266 : STD_LOGIC; 
  signal rem_buf_not0001 : STD_LOGIC; 
  signal rem_q1_23268 : STD_LOGIC; 
  signal rem_q1_mux0000 : STD_LOGIC; 
  signal rem_q2_23270 : STD_LOGIC; 
  signal rem_q2_or0000 : STD_LOGIC; 
  signal rem_q3_23272 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal shift_pipe : STD_LOGIC; 
  signal shift_pipe_input0 : STD_LOGIC; 
  signal sof_buf_23277 : STD_LOGIC; 
  signal sof_buf_not0001 : STD_LOGIC; 
  signal sof_gap_q3_23279 : STD_LOGIC; 
  signal sof_gap_q3_and_block_23280 : STD_LOGIC; 
  signal sof_gap_q3_and_block_mux0000 : STD_LOGIC; 
  signal sof_gap_q3_and_block_or0000 : STD_LOGIC; 
  signal sof_gap_q3_mux0000_23283 : STD_LOGIC; 
  signal sof_gap_q3_not0001 : STD_LOGIC; 
  signal sof_q1_23285 : STD_LOGIC; 
  signal sof_q1_mux0000_23286 : STD_LOGIC; 
  signal sof_q2_23287 : STD_LOGIC; 
  signal sof_q2_reg_23288 : STD_LOGIC; 
  signal sof_q3_23289 : STD_LOGIC; 
  signal sofpd_q2_rose : STD_LOGIC; 
  signal tc_fifo_change_23291 : STD_LOGIC; 
  signal tc_fifo_change_or0000 : STD_LOGIC; 
  signal tc_fifo_change_or00002_23293 : STD_LOGIC; 
  signal tc_fifo_change_or000079_23294 : STD_LOGIC; 
  signal td_buf_not0001_inv : STD_LOGIC; 
  signal td_q1_not0001 : STD_LOGIC; 
  signal td_q3_0_Q : STD_LOGIC; 
  signal td_q3_1_Q : STD_LOGIC; 
  signal td_q3_10_Q : STD_LOGIC; 
  signal td_q3_11_Q : STD_LOGIC; 
  signal td_q3_12_Q : STD_LOGIC; 
  signal td_q3_13_Q : STD_LOGIC; 
  signal td_q3_14_Q : STD_LOGIC; 
  signal td_q3_15_Q : STD_LOGIC; 
  signal td_q3_16_Q : STD_LOGIC; 
  signal td_q3_17_Q : STD_LOGIC; 
  signal td_q3_18_Q : STD_LOGIC; 
  signal td_q3_19_Q : STD_LOGIC; 
  signal td_q3_2_Q : STD_LOGIC; 
  signal td_q3_20_Q : STD_LOGIC; 
  signal td_q3_21_Q : STD_LOGIC; 
  signal td_q3_22_Q : STD_LOGIC; 
  signal td_q3_23_Q : STD_LOGIC; 
  signal td_q3_24_Q : STD_LOGIC; 
  signal td_q3_25_Q : STD_LOGIC; 
  signal td_q3_26_Q : STD_LOGIC; 
  signal td_q3_27_Q : STD_LOGIC; 
  signal td_q3_28_Q : STD_LOGIC; 
  signal td_q3_29_Q : STD_LOGIC; 
  signal td_q3_3_Q : STD_LOGIC; 
  signal td_q3_30_Q : STD_LOGIC; 
  signal td_q3_31_Q : STD_LOGIC; 
  signal td_q3_32_Q : STD_LOGIC; 
  signal td_q3_33_Q : STD_LOGIC; 
  signal td_q3_34_Q : STD_LOGIC; 
  signal td_q3_35_Q : STD_LOGIC; 
  signal td_q3_36_Q : STD_LOGIC; 
  signal td_q3_37_Q : STD_LOGIC; 
  signal td_q3_38_Q : STD_LOGIC; 
  signal td_q3_39_Q : STD_LOGIC; 
  signal td_q3_4_Q : STD_LOGIC; 
  signal td_q3_40_Q : STD_LOGIC; 
  signal td_q3_41_Q : STD_LOGIC; 
  signal td_q3_42_Q : STD_LOGIC; 
  signal td_q3_43_Q : STD_LOGIC; 
  signal td_q3_44_Q : STD_LOGIC; 
  signal td_q3_45_Q : STD_LOGIC; 
  signal td_q3_46_Q : STD_LOGIC; 
  signal td_q3_47_Q : STD_LOGIC; 
  signal td_q3_48_Q : STD_LOGIC; 
  signal td_q3_49_Q : STD_LOGIC; 
  signal td_q3_5_Q : STD_LOGIC; 
  signal td_q3_50_Q : STD_LOGIC; 
  signal td_q3_51_Q : STD_LOGIC; 
  signal td_q3_52_Q : STD_LOGIC; 
  signal td_q3_53_Q : STD_LOGIC; 
  signal td_q3_54_Q : STD_LOGIC; 
  signal td_q3_55_Q : STD_LOGIC; 
  signal td_q3_56_Q : STD_LOGIC; 
  signal td_q3_6_Q : STD_LOGIC; 
  signal td_q3_62_Q : STD_LOGIC; 
  signal td_q3_63_Q : STD_LOGIC; 
  signal td_q3_7_Q : STD_LOGIC; 
  signal td_q3_8_Q : STD_LOGIC; 
  signal td_q3_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_tdst_rdy_n : STD_LOGIC; 
  signal trn_tdst_rdy_n_not0001 : STD_LOGIC; 
  signal vld_buf_23749 : STD_LOGIC; 
  signal vld_buf_and0000 : STD_LOGIC; 
  signal vld_q1_23751 : STD_LOGIC; 
  signal vld_q1_or0000 : STD_LOGIC; 
  signal vld_q2_23753 : STD_LOGIC; 
  signal vld_q3_23754 : STD_LOGIC; 
  signal Maccum_user_pd_data_credits_in_cy : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal Maccum_user_pd_data_credits_in_lut : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Madd_td_q2_credits_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Msub_near_end_pd_credits_buffered_cy : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal Msub_near_end_pd_credits_buffered_lut : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal block_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cpl_in_count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal cpl_in_count_add0000 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal fifo_last : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal fifo_q2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal fifo_q3 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_llk_tx_ch_fifo : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_llk_tx_ch_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal NlwRenamedSig_OI_llk_tx_enable_n : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal near_end_pd_credits_buffered : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tc_last : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal tc_q2 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal tc_q3 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal td_buf : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal td_q1 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal td_q1_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal td_q2 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal td_q2_credits : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal td_q2_credits_add0000 : STD_LOGIC_VECTOR ( 5 downto 1 ); 
  signal NlwRenamedSig_OI_td_q3 : STD_LOGIC_VECTOR ( 61 downto 57 ); 
  signal user_pd_data_credits_in : STD_LOGIC_VECTOR ( 11 downto 0 ); 
begin
  llk_tx_sop_n <= NlwRenamedSig_OI_llk_tx_eop_n;
  trn_tdst_rdy_n <= NlwRenamedSig_OI_trn_tdst_rdy_n;
  trn_tdst_dsc_n <= NlwRenamedSig_OI_llk_tx_eop_n;
  llk_tx_eop_n <= NlwRenamedSig_OI_llk_tx_eop_n;
  llk_tx_ch_fifo(1) <= NlwRenamedSig_OI_llk_tx_ch_fifo(1);
  llk_tx_ch_fifo(0) <= NlwRenamedSig_OI_llk_tx_ch_fifo(0);
  llk_tx_ch_tc(2) <= NlwRenamedSig_OI_llk_tx_ch_tc(2);
  llk_tx_ch_tc(1) <= NlwRenamedSig_OI_llk_tx_ch_tc(1);
  llk_tx_ch_tc(0) <= NlwRenamedSig_OI_llk_tx_ch_tc(0);
  llk_tx_enable_n(1) <= NlwRenamedSig_OI_llk_tx_enable_n(1);
  llk_tx_data(63) <= td_q3_63_Q;
  llk_tx_data(62) <= td_q3_62_Q;
  llk_tx_data(61) <= NlwRenamedSig_OI_td_q3(61);
  llk_tx_data(60) <= NlwRenamedSig_OI_td_q3(60);
  llk_tx_data(59) <= NlwRenamedSig_OI_td_q3(59);
  llk_tx_data(58) <= NlwRenamedSig_OI_td_q3(58);
  llk_tx_data(57) <= NlwRenamedSig_OI_td_q3(57);
  llk_tx_data(56) <= td_q3_56_Q;
  llk_tx_data(55) <= td_q3_55_Q;
  llk_tx_data(54) <= td_q3_54_Q;
  llk_tx_data(53) <= td_q3_53_Q;
  llk_tx_data(52) <= td_q3_52_Q;
  llk_tx_data(51) <= td_q3_51_Q;
  llk_tx_data(50) <= td_q3_50_Q;
  llk_tx_data(49) <= td_q3_49_Q;
  llk_tx_data(48) <= td_q3_48_Q;
  llk_tx_data(47) <= td_q3_47_Q;
  llk_tx_data(46) <= td_q3_46_Q;
  llk_tx_data(45) <= td_q3_45_Q;
  llk_tx_data(44) <= td_q3_44_Q;
  llk_tx_data(43) <= td_q3_43_Q;
  llk_tx_data(42) <= td_q3_42_Q;
  llk_tx_data(41) <= td_q3_41_Q;
  llk_tx_data(40) <= td_q3_40_Q;
  llk_tx_data(39) <= td_q3_39_Q;
  llk_tx_data(38) <= td_q3_38_Q;
  llk_tx_data(37) <= td_q3_37_Q;
  llk_tx_data(36) <= td_q3_36_Q;
  llk_tx_data(35) <= td_q3_35_Q;
  llk_tx_data(34) <= td_q3_34_Q;
  llk_tx_data(33) <= td_q3_33_Q;
  llk_tx_data(32) <= td_q3_32_Q;
  llk_tx_data(31) <= td_q3_31_Q;
  llk_tx_data(30) <= td_q3_30_Q;
  llk_tx_data(29) <= td_q3_29_Q;
  llk_tx_data(28) <= td_q3_28_Q;
  llk_tx_data(27) <= td_q3_27_Q;
  llk_tx_data(26) <= td_q3_26_Q;
  llk_tx_data(25) <= td_q3_25_Q;
  llk_tx_data(24) <= td_q3_24_Q;
  llk_tx_data(23) <= td_q3_23_Q;
  llk_tx_data(22) <= td_q3_22_Q;
  llk_tx_data(21) <= td_q3_21_Q;
  llk_tx_data(20) <= td_q3_20_Q;
  llk_tx_data(19) <= td_q3_19_Q;
  llk_tx_data(18) <= td_q3_18_Q;
  llk_tx_data(17) <= td_q3_17_Q;
  llk_tx_data(16) <= td_q3_16_Q;
  llk_tx_data(15) <= td_q3_15_Q;
  llk_tx_data(14) <= td_q3_14_Q;
  llk_tx_data(13) <= td_q3_13_Q;
  llk_tx_data(12) <= td_q3_12_Q;
  llk_tx_data(11) <= td_q3_11_Q;
  llk_tx_data(10) <= td_q3_10_Q;
  llk_tx_data(9) <= td_q3_9_Q;
  llk_tx_data(8) <= td_q3_8_Q;
  llk_tx_data(7) <= td_q3_7_Q;
  llk_tx_data(6) <= td_q3_6_Q;
  llk_tx_data(5) <= td_q3_5_Q;
  llk_tx_data(4) <= td_q3_4_Q;
  llk_tx_data(3) <= td_q3_3_Q;
  llk_tx_data(2) <= td_q3_2_Q;
  llk_tx_data(1) <= td_q3_1_Q;
  llk_tx_data(0) <= td_q3_0_Q;
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_llk_tx_enable_n(1)
    );
  XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_llk_tx_eop_n
    );
  td_buf_0 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(0),
      Q => td_buf(0)
    );
  td_buf_1 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(1),
      Q => td_buf(1)
    );
  td_buf_2 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(2),
      Q => td_buf(2)
    );
  td_buf_3 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(3),
      Q => td_buf(3)
    );
  td_buf_4 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(4),
      Q => td_buf(4)
    );
  td_buf_5 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(5),
      Q => td_buf(5)
    );
  td_buf_6 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(6),
      Q => td_buf(6)
    );
  td_buf_7 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(7),
      Q => td_buf(7)
    );
  td_buf_8 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(8),
      Q => td_buf(8)
    );
  td_buf_9 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(9),
      Q => td_buf(9)
    );
  td_buf_10 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(10),
      Q => td_buf(10)
    );
  td_buf_11 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(11),
      Q => td_buf(11)
    );
  td_buf_12 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(12),
      Q => td_buf(12)
    );
  td_buf_13 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(13),
      Q => td_buf(13)
    );
  td_buf_14 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(14),
      Q => td_buf(14)
    );
  td_buf_15 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(15),
      Q => td_buf(15)
    );
  td_buf_16 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(16),
      Q => td_buf(16)
    );
  td_buf_17 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(17),
      Q => td_buf(17)
    );
  td_buf_18 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(18),
      Q => td_buf(18)
    );
  td_buf_19 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(19),
      Q => td_buf(19)
    );
  td_buf_20 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(20),
      Q => td_buf(20)
    );
  td_buf_21 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(21),
      Q => td_buf(21)
    );
  td_buf_22 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(22),
      Q => td_buf(22)
    );
  td_buf_23 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(23),
      Q => td_buf(23)
    );
  td_buf_24 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(24),
      Q => td_buf(24)
    );
  td_buf_25 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(25),
      Q => td_buf(25)
    );
  td_buf_26 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(26),
      Q => td_buf(26)
    );
  td_buf_27 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(27),
      Q => td_buf(27)
    );
  td_buf_28 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(28),
      Q => td_buf(28)
    );
  td_buf_29 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(29),
      Q => td_buf(29)
    );
  td_buf_30 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(30),
      Q => td_buf(30)
    );
  td_buf_31 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(31),
      Q => td_buf(31)
    );
  td_buf_32 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(32),
      Q => td_buf(32)
    );
  td_buf_33 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(33),
      Q => td_buf(33)
    );
  td_buf_34 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(34),
      Q => td_buf(34)
    );
  td_buf_35 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(35),
      Q => td_buf(35)
    );
  td_buf_36 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(36),
      Q => td_buf(36)
    );
  td_buf_37 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(37),
      Q => td_buf(37)
    );
  td_buf_38 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(38),
      Q => td_buf(38)
    );
  td_buf_39 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(39),
      Q => td_buf(39)
    );
  td_buf_40 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(40),
      Q => td_buf(40)
    );
  td_buf_41 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(41),
      Q => td_buf(41)
    );
  td_buf_42 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(42),
      Q => td_buf(42)
    );
  td_buf_43 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(43),
      Q => td_buf(43)
    );
  td_buf_44 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(44),
      Q => td_buf(44)
    );
  td_buf_45 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(45),
      Q => td_buf(45)
    );
  td_buf_46 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(46),
      Q => td_buf(46)
    );
  td_buf_47 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(47),
      Q => td_buf(47)
    );
  td_buf_48 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(48),
      Q => td_buf(48)
    );
  td_buf_49 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(49),
      Q => td_buf(49)
    );
  td_buf_50 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(50),
      Q => td_buf(50)
    );
  td_buf_51 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(51),
      Q => td_buf(51)
    );
  td_buf_52 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(52),
      Q => td_buf(52)
    );
  td_buf_53 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(53),
      Q => td_buf(53)
    );
  td_buf_54 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(54),
      Q => td_buf(54)
    );
  td_buf_55 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(55),
      Q => td_buf(55)
    );
  td_buf_56 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(56),
      Q => td_buf(56)
    );
  td_buf_57 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(57),
      Q => td_buf(57)
    );
  td_buf_58 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(58),
      Q => td_buf(58)
    );
  td_buf_59 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(59),
      Q => td_buf(59)
    );
  td_buf_60 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(60),
      Q => td_buf(60)
    );
  td_buf_61 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(61),
      Q => td_buf(61)
    );
  td_buf_62 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(62),
      Q => td_buf(62)
    );
  td_buf_63 : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => trn_td(63),
      Q => td_buf(63)
    );
  vld_buf : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => buf_rd,
      D => NlwRenamedSig_OI_llk_tx_enable_n(1),
      R => rst_n_inv,
      S => vld_buf_and0000,
      Q => vld_buf_23749
    );
  sof_buf : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => sof_buf_not0001,
      Q => sof_buf_23277
    );
  eof_buf : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => eof_buf_not0001,
      Q => eof_buf_23189
    );
  rem_buf : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => rem_buf_not0001,
      Q => rem_buf_23266
    );
  dsc_buf : FDE
    port map (
      C => clk,
      CE => td_buf_not0001_inv,
      D => dsc_buf_not0001,
      Q => dsc_buf_23183
    );
  trn_tdst_rdy_n_12536 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => trn_tdst_rdy_n_not0001,
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_tdst_rdy_n
    );
  vld_q1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => vld_q1_or0000,
      R => rst_n_inv,
      Q => vld_q1_23751
    );
  sof_q1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => sof_q1_mux0000_23286,
      R => rst_n_inv,
      Q => sof_q1_23285
    );
  eof_q1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => eof_q1_not0001,
      D => eof_q1_mux0000,
      R => rst_n_inv,
      Q => eof_q1_23191
    );
  dsc_q1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => eof_q1_not0001,
      D => dsc_q1_mux0000,
      R => rst_n_inv,
      Q => dsc_q1_23185
    );
  td_q1_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(0),
      Q => td_q1(0)
    );
  td_q1_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(1),
      Q => td_q1(1)
    );
  td_q1_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(2),
      Q => td_q1(2)
    );
  td_q1_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(3),
      Q => td_q1(3)
    );
  td_q1_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(4),
      Q => td_q1(4)
    );
  td_q1_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(5),
      Q => td_q1(5)
    );
  td_q1_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(6),
      Q => td_q1(6)
    );
  td_q1_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(7),
      Q => td_q1(7)
    );
  td_q1_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(8),
      Q => td_q1(8)
    );
  td_q1_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(9),
      Q => td_q1(9)
    );
  td_q1_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(10),
      Q => td_q1(10)
    );
  td_q1_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(11),
      Q => td_q1(11)
    );
  td_q1_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(12),
      Q => td_q1(12)
    );
  td_q1_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(13),
      Q => td_q1(13)
    );
  td_q1_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(14),
      Q => td_q1(14)
    );
  td_q1_15 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(15),
      Q => td_q1(15)
    );
  td_q1_16 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(16),
      Q => td_q1(16)
    );
  td_q1_17 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(17),
      Q => td_q1(17)
    );
  td_q1_18 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(18),
      Q => td_q1(18)
    );
  td_q1_19 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(19),
      Q => td_q1(19)
    );
  td_q1_20 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(20),
      Q => td_q1(20)
    );
  td_q1_21 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(21),
      Q => td_q1(21)
    );
  td_q1_22 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(22),
      Q => td_q1(22)
    );
  td_q1_23 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(23),
      Q => td_q1(23)
    );
  td_q1_24 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(24),
      Q => td_q1(24)
    );
  td_q1_25 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(25),
      Q => td_q1(25)
    );
  td_q1_26 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(26),
      Q => td_q1(26)
    );
  td_q1_27 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(27),
      Q => td_q1(27)
    );
  td_q1_28 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(28),
      Q => td_q1(28)
    );
  td_q1_29 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(29),
      Q => td_q1(29)
    );
  td_q1_30 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(30),
      Q => td_q1(30)
    );
  td_q1_31 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(31),
      Q => td_q1(31)
    );
  td_q1_32 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(32),
      Q => td_q1(32)
    );
  td_q1_33 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(33),
      Q => td_q1(33)
    );
  td_q1_34 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(34),
      Q => td_q1(34)
    );
  td_q1_35 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(35),
      Q => td_q1(35)
    );
  td_q1_36 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(36),
      Q => td_q1(36)
    );
  td_q1_37 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(37),
      Q => td_q1(37)
    );
  td_q1_38 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(38),
      Q => td_q1(38)
    );
  td_q1_39 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(39),
      Q => td_q1(39)
    );
  td_q1_40 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(40),
      Q => td_q1(40)
    );
  td_q1_41 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(41),
      Q => td_q1(41)
    );
  td_q1_42 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(42),
      Q => td_q1(42)
    );
  td_q1_43 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(43),
      Q => td_q1(43)
    );
  td_q1_44 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(44),
      Q => td_q1(44)
    );
  td_q1_45 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(45),
      Q => td_q1(45)
    );
  td_q1_46 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(46),
      Q => td_q1(46)
    );
  td_q1_47 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(47),
      Q => td_q1(47)
    );
  td_q1_48 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(48),
      Q => td_q1(48)
    );
  td_q1_49 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(49),
      Q => td_q1(49)
    );
  td_q1_50 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(50),
      Q => td_q1(50)
    );
  td_q1_51 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(51),
      Q => td_q1(51)
    );
  td_q1_52 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(52),
      Q => td_q1(52)
    );
  td_q1_53 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(53),
      Q => td_q1(53)
    );
  td_q1_54 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(54),
      Q => td_q1(54)
    );
  td_q1_55 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(55),
      Q => td_q1(55)
    );
  td_q1_56 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(56),
      Q => td_q1(56)
    );
  td_q1_57 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(57),
      Q => td_q1(57)
    );
  td_q1_58 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(58),
      Q => td_q1(58)
    );
  td_q1_59 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(59),
      Q => td_q1(59)
    );
  td_q1_60 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(60),
      Q => td_q1(60)
    );
  td_q1_61 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(61),
      Q => td_q1(61)
    );
  td_q1_62 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(62),
      Q => td_q1(62)
    );
  td_q1_63 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => td_q1_mux0000(63),
      Q => td_q1(63)
    );
  rem_q1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => td_q1_not0001,
      D => rem_q1_mux0000,
      Q => rem_q1_23268
    );
  len_eq1_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => len_eq1_q2_and0000,
      R => rst_n_inv,
      Q => len_eq1_q2_23221
    );
  fifo_q2_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => fifo_q2_or0001,
      Q => fifo_q2(0)
    );
  fifo_q2_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => fifo_q2_and0007,
      Q => fifo_q2(1)
    );
  sof_gap_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sof_gap_q3_not0001,
      D => sof_gap_q3_mux0000_23283,
      R => rst_n_inv,
      Q => sof_gap_q3_23279
    );
  block_sof : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => block_sof_not0001,
      D => block_sof_mux0000,
      S => rst_n_inv,
      Q => block_sof_23168
    );
  sof_gap_q3_and_block : FDR
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => sof_gap_q3_and_block_mux0000,
      R => sof_gap_q3_and_block_or0000,
      Q => sof_gap_q3_and_block_23280
    );
  block_cnt_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => block_cnt_1_mux0000,
      R => rst_n_inv,
      Q => block_cnt(1)
    );
  block_cnt_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => block_cnt_0_mux0000,
      R => rst_n_inv,
      Q => block_cnt(0)
    );
  tc_fifo_change : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_llk_tx_eop_n,
      R => tc_fifo_change_or0000,
      Q => tc_fifo_change_23291
    );
  eof_q3_only : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => eof_q3_only_mux0000_23207,
      R => rst_n_inv,
      Q => eof_q3_only_23206
    );
  eof_q2_only : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => eof_q2_only_mux0000_23203,
      R => rst_n_inv,
      Q => eof_q2_only_23202
    );
  eof_q1_or_eof_q2_only : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => eof_q1_or_eof_q2_only_mux0001,
      R => rst_n_inv,
      Q => eof_q1_or_eof_q2_only_23194
    );
  llk_tlp_halt : FDR
    port map (
      C => clk,
      D => llk_tlp_halt_or0000,
      R => rst_n_inv,
      Q => llk_tlp_halt_23225
    );
  vld_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => vld_q1_23751,
      R => rst_n_inv,
      Q => vld_q2_23753
    );
  fifo_q3_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => fifo_q2(0),
      R => rst_n_inv,
      Q => fifo_q3(0)
    );
  fifo_q3_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => fifo_q2(1),
      R => rst_n_inv,
      Q => fifo_q3(1)
    );
  tc_q2_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q1(52),
      Q => tc_q2(0)
    );
  tc_q2_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q1(53),
      Q => tc_q2(1)
    );
  tc_q2_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q1(54),
      Q => tc_q2(2)
    );
  fifo_last_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => fifo_q2(0),
      R => rst_n_inv,
      Q => fifo_last(0)
    );
  fifo_last_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => fifo_q2(1),
      R => rst_n_inv,
      Q => fifo_last(1)
    );
  vld_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => vld_q2_23753,
      R => rst_n_inv,
      Q => vld_q3_23754
    );
  td_q2_credits_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => Madd_td_q2_credits_add0000_lut(0),
      R => rst_n_inv,
      Q => td_q2_credits(0)
    );
  td_q2_credits_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q2_credits_add0000(1),
      R => rst_n_inv,
      Q => td_q2_credits(1)
    );
  td_q2_credits_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q2_credits_add0000(2),
      R => rst_n_inv,
      Q => td_q2_credits(2)
    );
  td_q2_credits_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q2_credits_add0000(3),
      R => rst_n_inv,
      Q => td_q2_credits(3)
    );
  td_q2_credits_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q2_credits_add0000(4),
      R => rst_n_inv,
      Q => td_q2_credits(4)
    );
  td_q2_credits_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_q2_and0000,
      D => td_q2_credits_add0000(5),
      R => rst_n_inv,
      Q => td_q2_credits(5)
    );
  tc_q3_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(0),
      R => rst_n_inv,
      Q => tc_q3(0)
    );
  tc_q3_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(1),
      R => rst_n_inv,
      Q => tc_q3(1)
    );
  tc_q3_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(2),
      R => rst_n_inv,
      Q => tc_q3(2)
    );
  tc_last_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(0),
      R => rst_n_inv,
      Q => tc_last(0)
    );
  tc_last_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(1),
      R => rst_n_inv,
      Q => tc_last(1)
    );
  tc_last_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => fifo_last_and0000,
      D => tc_q2(2),
      R => rst_n_inv,
      Q => tc_last(2)
    );
  llk_tx_ch_fifo_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => llk_tx_ch_tc_not0001_inv,
      D => fifo_q3(0),
      S => rst_n_inv,
      Q => NlwRenamedSig_OI_llk_tx_ch_fifo(0)
    );
  llk_tx_ch_fifo_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => llk_tx_ch_tc_not0001_inv,
      D => fifo_q3(1),
      S => rst_n_inv,
      Q => NlwRenamedSig_OI_llk_tx_ch_fifo(1)
    );
  cpl_in_count_0 : FDR
    port map (
      C => clk,
      D => cpl_in_count_add0000(0),
      R => rst_n_inv,
      Q => cpl_in_count(0)
    );
  cpl_in_count_1 : FDR
    port map (
      C => clk,
      D => cpl_in_count_add0000(1),
      R => rst_n_inv,
      Q => cpl_in_count(1)
    );
  cpl_in_count_2 : FDR
    port map (
      C => clk,
      D => cpl_in_count_add0000(2),
      R => rst_n_inv,
      Q => cpl_in_count(2)
    );
  cpl_in_count_3 : FDR
    port map (
      C => clk,
      D => cpl_in_count_add0000(3),
      R => rst_n_inv,
      Q => cpl_in_count(3)
    );
  cpl_in_count_4 : FDR
    port map (
      C => clk,
      D => cpl_in_count_add0000(4),
      R => rst_n_inv,
      Q => cpl_in_count(4)
    );
  llk_tx_ch_tc_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => llk_tx_ch_tc_not0001_inv,
      D => tc_q3(0),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_llk_tx_ch_tc(0)
    );
  llk_tx_ch_tc_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => llk_tx_ch_tc_not0001_inv,
      D => tc_q3(1),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_llk_tx_ch_tc(1)
    );
  llk_tx_ch_tc_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => llk_tx_ch_tc_not0001_inv,
      D => tc_q3(2),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_llk_tx_ch_tc(2)
    );
  sof_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => sof_q1_23285,
      R => rst_n_inv,
      Q => sof_q2_23287
    );
  eof_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => eof_q3_and0000,
      R => rst_n_inv,
      Q => eof_q3_23204
    );
  td_q2_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(0),
      R => rst_n_inv,
      Q => td_q2(0)
    );
  td_q2_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(1),
      R => rst_n_inv,
      Q => td_q2(1)
    );
  td_q2_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(2),
      R => rst_n_inv,
      Q => td_q2(2)
    );
  td_q2_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(3),
      R => rst_n_inv,
      Q => td_q2(3)
    );
  td_q2_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(4),
      R => rst_n_inv,
      Q => td_q2(4)
    );
  td_q2_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(5),
      R => rst_n_inv,
      Q => td_q2(5)
    );
  td_q2_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(6),
      R => rst_n_inv,
      Q => td_q2(6)
    );
  td_q2_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(7),
      R => rst_n_inv,
      Q => td_q2(7)
    );
  td_q2_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(8),
      R => rst_n_inv,
      Q => td_q2(8)
    );
  td_q2_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(9),
      R => rst_n_inv,
      Q => td_q2(9)
    );
  td_q2_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(10),
      R => rst_n_inv,
      Q => td_q2(10)
    );
  td_q2_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(11),
      R => rst_n_inv,
      Q => td_q2(11)
    );
  td_q2_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(12),
      R => rst_n_inv,
      Q => td_q2(12)
    );
  td_q2_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(13),
      R => rst_n_inv,
      Q => td_q2(13)
    );
  td_q2_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(14),
      R => rst_n_inv,
      Q => td_q2(14)
    );
  td_q2_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(15),
      R => rst_n_inv,
      Q => td_q2(15)
    );
  td_q2_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(16),
      R => rst_n_inv,
      Q => td_q2(16)
    );
  td_q2_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(17),
      R => rst_n_inv,
      Q => td_q2(17)
    );
  td_q2_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(18),
      R => rst_n_inv,
      Q => td_q2(18)
    );
  td_q2_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(19),
      R => rst_n_inv,
      Q => td_q2(19)
    );
  td_q2_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(20),
      R => rst_n_inv,
      Q => td_q2(20)
    );
  td_q2_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(21),
      R => rst_n_inv,
      Q => td_q2(21)
    );
  td_q2_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(22),
      R => rst_n_inv,
      Q => td_q2(22)
    );
  td_q2_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(23),
      R => rst_n_inv,
      Q => td_q2(23)
    );
  td_q2_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(24),
      R => rst_n_inv,
      Q => td_q2(24)
    );
  td_q2_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(25),
      R => rst_n_inv,
      Q => td_q2(25)
    );
  td_q2_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(26),
      R => rst_n_inv,
      Q => td_q2(26)
    );
  td_q2_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(27),
      R => rst_n_inv,
      Q => td_q2(27)
    );
  td_q2_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(28),
      R => rst_n_inv,
      Q => td_q2(28)
    );
  td_q2_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(29),
      R => rst_n_inv,
      Q => td_q2(29)
    );
  td_q2_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(30),
      R => rst_n_inv,
      Q => td_q2(30)
    );
  td_q2_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(31),
      R => rst_n_inv,
      Q => td_q2(31)
    );
  td_q2_32 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(32),
      R => rst_n_inv,
      Q => td_q2(32)
    );
  td_q2_33 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(33),
      R => rst_n_inv,
      Q => td_q2(33)
    );
  td_q2_34 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(34),
      R => rst_n_inv,
      Q => td_q2(34)
    );
  td_q2_35 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(35),
      R => rst_n_inv,
      Q => td_q2(35)
    );
  td_q2_36 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(36),
      R => rst_n_inv,
      Q => td_q2(36)
    );
  td_q2_37 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(37),
      R => rst_n_inv,
      Q => td_q2(37)
    );
  td_q2_38 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(38),
      R => rst_n_inv,
      Q => td_q2(38)
    );
  td_q2_39 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(39),
      R => rst_n_inv,
      Q => td_q2(39)
    );
  td_q2_40 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(40),
      R => rst_n_inv,
      Q => td_q2(40)
    );
  td_q2_41 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(41),
      R => rst_n_inv,
      Q => td_q2(41)
    );
  td_q2_42 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(42),
      R => rst_n_inv,
      Q => td_q2(42)
    );
  td_q2_43 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(43),
      R => rst_n_inv,
      Q => td_q2(43)
    );
  td_q2_44 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(44),
      R => rst_n_inv,
      Q => td_q2(44)
    );
  td_q2_45 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(45),
      R => rst_n_inv,
      Q => td_q2(45)
    );
  td_q2_46 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(46),
      R => rst_n_inv,
      Q => td_q2(46)
    );
  td_q2_47 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(47),
      R => rst_n_inv,
      Q => td_q2(47)
    );
  td_q2_48 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(48),
      R => rst_n_inv,
      Q => td_q2(48)
    );
  td_q2_49 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(49),
      R => rst_n_inv,
      Q => td_q2(49)
    );
  td_q2_50 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(50),
      R => rst_n_inv,
      Q => td_q2(50)
    );
  td_q2_51 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(51),
      R => rst_n_inv,
      Q => td_q2(51)
    );
  td_q2_52 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(52),
      R => rst_n_inv,
      Q => td_q2(52)
    );
  td_q2_53 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(53),
      R => rst_n_inv,
      Q => td_q2(53)
    );
  td_q2_54 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(54),
      R => rst_n_inv,
      Q => td_q2(54)
    );
  td_q2_55 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(55),
      R => rst_n_inv,
      Q => td_q2(55)
    );
  td_q2_56 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(56),
      R => rst_n_inv,
      Q => td_q2(56)
    );
  td_q2_57 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(57),
      R => rst_n_inv,
      Q => td_q2(57)
    );
  td_q2_58 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(58),
      R => rst_n_inv,
      Q => td_q2(58)
    );
  td_q2_59 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(59),
      R => rst_n_inv,
      Q => td_q2(59)
    );
  td_q2_60 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(60),
      R => rst_n_inv,
      Q => td_q2(60)
    );
  td_q2_61 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(61),
      R => rst_n_inv,
      Q => td_q2(61)
    );
  td_q2_62 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(62),
      R => rst_n_inv,
      Q => td_q2(62)
    );
  td_q2_63 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q1(63),
      R => rst_n_inv,
      Q => td_q2(63)
    );
  pd_q1_reg : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => pd_q1_reg_or0000,
      R => rst_n_inv,
      Q => pd_q1_reg_23264
    );
  eof_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => eof_q1_23191,
      R => rst_n_inv,
      Q => eof_q2_23201
    );
  rem_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => rem_q2_or0000,
      R => rst_n_inv,
      Q => rem_q2_23270
    );
  dsc_q2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => dsc_q1_23185,
      R => rst_n_inv,
      Q => dsc_q2_23187
    );
  sof_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => sof_q2_23287,
      R => rst_n_inv,
      Q => sof_q3_23289
    );
  sof_q2_reg : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => sof_q2_23287,
      R => rst_n_inv,
      Q => sof_q2_reg_23288
    );
  td_q3_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(0),
      R => rst_n_inv,
      Q => td_q3_0_Q
    );
  td_q3_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(1),
      R => rst_n_inv,
      Q => td_q3_1_Q
    );
  td_q3_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(2),
      R => rst_n_inv,
      Q => td_q3_2_Q
    );
  td_q3_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(3),
      R => rst_n_inv,
      Q => td_q3_3_Q
    );
  td_q3_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(4),
      R => rst_n_inv,
      Q => td_q3_4_Q
    );
  td_q3_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(5),
      R => rst_n_inv,
      Q => td_q3_5_Q
    );
  td_q3_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(6),
      R => rst_n_inv,
      Q => td_q3_6_Q
    );
  td_q3_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(7),
      R => rst_n_inv,
      Q => td_q3_7_Q
    );
  td_q3_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(8),
      R => rst_n_inv,
      Q => td_q3_8_Q
    );
  td_q3_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(9),
      R => rst_n_inv,
      Q => td_q3_9_Q
    );
  td_q3_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(10),
      R => rst_n_inv,
      Q => td_q3_10_Q
    );
  td_q3_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(11),
      R => rst_n_inv,
      Q => td_q3_11_Q
    );
  td_q3_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(12),
      R => rst_n_inv,
      Q => td_q3_12_Q
    );
  td_q3_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(13),
      R => rst_n_inv,
      Q => td_q3_13_Q
    );
  td_q3_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(14),
      R => rst_n_inv,
      Q => td_q3_14_Q
    );
  td_q3_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(15),
      R => rst_n_inv,
      Q => td_q3_15_Q
    );
  td_q3_16 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(16),
      R => rst_n_inv,
      Q => td_q3_16_Q
    );
  td_q3_17 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(17),
      R => rst_n_inv,
      Q => td_q3_17_Q
    );
  td_q3_18 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(18),
      R => rst_n_inv,
      Q => td_q3_18_Q
    );
  td_q3_19 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(19),
      R => rst_n_inv,
      Q => td_q3_19_Q
    );
  td_q3_20 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(20),
      R => rst_n_inv,
      Q => td_q3_20_Q
    );
  td_q3_21 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(21),
      R => rst_n_inv,
      Q => td_q3_21_Q
    );
  td_q3_22 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(22),
      R => rst_n_inv,
      Q => td_q3_22_Q
    );
  td_q3_23 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(23),
      R => rst_n_inv,
      Q => td_q3_23_Q
    );
  td_q3_24 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(24),
      R => rst_n_inv,
      Q => td_q3_24_Q
    );
  td_q3_25 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(25),
      R => rst_n_inv,
      Q => td_q3_25_Q
    );
  td_q3_26 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(26),
      R => rst_n_inv,
      Q => td_q3_26_Q
    );
  td_q3_27 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(27),
      R => rst_n_inv,
      Q => td_q3_27_Q
    );
  td_q3_28 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(28),
      R => rst_n_inv,
      Q => td_q3_28_Q
    );
  td_q3_29 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(29),
      R => rst_n_inv,
      Q => td_q3_29_Q
    );
  td_q3_30 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(30),
      R => rst_n_inv,
      Q => td_q3_30_Q
    );
  td_q3_31 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(31),
      R => rst_n_inv,
      Q => td_q3_31_Q
    );
  td_q3_32 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(32),
      R => rst_n_inv,
      Q => td_q3_32_Q
    );
  td_q3_33 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(33),
      R => rst_n_inv,
      Q => td_q3_33_Q
    );
  td_q3_34 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(34),
      R => rst_n_inv,
      Q => td_q3_34_Q
    );
  td_q3_35 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(35),
      R => rst_n_inv,
      Q => td_q3_35_Q
    );
  td_q3_36 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(36),
      R => rst_n_inv,
      Q => td_q3_36_Q
    );
  td_q3_37 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(37),
      R => rst_n_inv,
      Q => td_q3_37_Q
    );
  td_q3_38 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(38),
      R => rst_n_inv,
      Q => td_q3_38_Q
    );
  td_q3_39 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(39),
      R => rst_n_inv,
      Q => td_q3_39_Q
    );
  td_q3_40 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(40),
      R => rst_n_inv,
      Q => td_q3_40_Q
    );
  td_q3_41 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(41),
      R => rst_n_inv,
      Q => td_q3_41_Q
    );
  td_q3_42 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(42),
      R => rst_n_inv,
      Q => td_q3_42_Q
    );
  td_q3_43 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(43),
      R => rst_n_inv,
      Q => td_q3_43_Q
    );
  td_q3_44 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(44),
      R => rst_n_inv,
      Q => td_q3_44_Q
    );
  td_q3_45 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(45),
      R => rst_n_inv,
      Q => td_q3_45_Q
    );
  td_q3_46 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(46),
      R => rst_n_inv,
      Q => td_q3_46_Q
    );
  td_q3_47 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(47),
      R => rst_n_inv,
      Q => td_q3_47_Q
    );
  td_q3_48 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(48),
      R => rst_n_inv,
      Q => td_q3_48_Q
    );
  td_q3_49 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(49),
      R => rst_n_inv,
      Q => td_q3_49_Q
    );
  td_q3_50 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(50),
      R => rst_n_inv,
      Q => td_q3_50_Q
    );
  td_q3_51 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(51),
      R => rst_n_inv,
      Q => td_q3_51_Q
    );
  td_q3_52 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(52),
      R => rst_n_inv,
      Q => td_q3_52_Q
    );
  td_q3_53 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(53),
      R => rst_n_inv,
      Q => td_q3_53_Q
    );
  td_q3_54 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(54),
      R => rst_n_inv,
      Q => td_q3_54_Q
    );
  td_q3_55 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(55),
      R => rst_n_inv,
      Q => td_q3_55_Q
    );
  td_q3_56 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(56),
      R => rst_n_inv,
      Q => td_q3_56_Q
    );
  td_q3_57 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(57),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_td_q3(57)
    );
  td_q3_58 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(58),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_td_q3(58)
    );
  td_q3_59 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(59),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_td_q3(59)
    );
  td_q3_60 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(60),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_td_q3(60)
    );
  td_q3_61 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(61),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_td_q3(61)
    );
  td_q3_62 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(62),
      R => rst_n_inv,
      Q => td_q3_62_Q
    );
  td_q3_63 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => td_q2(63),
      R => rst_n_inv,
      Q => td_q3_63_Q
    );
  rem_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => rem_q2_23270,
      R => rst_n_inv,
      Q => rem_q3_23272
    );
  dsc_q3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => shift_pipe,
      D => dsc_q2_23187,
      R => rst_n_inv,
      Q => dsc_q3_23188
    );
  block_fifo : FDRSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => block_fifo_and0000,
      D => NlwRenamedSig_OI_llk_tx_enable_n(1),
      R => rst_n_inv,
      S => eof_q3_23204,
      Q => block_fifo_23166
    );
  pd_credits_near_gte_far : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => pd_credits_near_gte_far_cmp_ge0000,
      R => pd_credit_limited_inv,
      Q => pd_credits_near_gte_far_23262
    );
  user_pd_data_credits_in_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(0),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(0)
    );
  user_pd_data_credits_in_1 : FDSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(1),
      S => rst_n_inv,
      Q => user_pd_data_credits_in(1)
    );
  user_pd_data_credits_in_2 : FDSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(2),
      S => rst_n_inv,
      Q => user_pd_data_credits_in(2)
    );
  user_pd_data_credits_in_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(5),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(5)
    );
  user_pd_data_credits_in_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(3),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(3)
    );
  user_pd_data_credits_in_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(4),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(4)
    );
  user_pd_data_credits_in_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(8),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(8)
    );
  user_pd_data_credits_in_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(6),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(6)
    );
  user_pd_data_credits_in_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(7),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(7)
    );
  user_pd_data_credits_in_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(9),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(9)
    );
  user_pd_data_credits_in_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(10),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(10)
    );
  user_pd_data_credits_in_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => sofpd_q2_rose,
      D => Result(11),
      R => rst_n_inv,
      Q => user_pd_data_credits_in(11)
    );
  Msub_near_end_pd_credits_buffered_lut_0_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(0),
      I1 => tx_pd_credits_consumed(0),
      O => Msub_near_end_pd_credits_buffered_lut(0)
    );
  Msub_near_end_pd_credits_buffered_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_llk_tx_eop_n,
      DI => user_pd_data_credits_in(0),
      S => Msub_near_end_pd_credits_buffered_lut(0),
      O => Msub_near_end_pd_credits_buffered_cy(0)
    );
  Msub_near_end_pd_credits_buffered_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_llk_tx_eop_n,
      LI => Msub_near_end_pd_credits_buffered_lut(0),
      O => near_end_pd_credits_buffered(0)
    );
  Msub_near_end_pd_credits_buffered_lut_1_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(1),
      I1 => tx_pd_credits_consumed(1),
      O => Msub_near_end_pd_credits_buffered_lut(1)
    );
  Msub_near_end_pd_credits_buffered_cy_1_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(0),
      DI => user_pd_data_credits_in(1),
      S => Msub_near_end_pd_credits_buffered_lut(1),
      O => Msub_near_end_pd_credits_buffered_cy(1)
    );
  Msub_near_end_pd_credits_buffered_xor_1_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(0),
      LI => Msub_near_end_pd_credits_buffered_lut(1),
      O => near_end_pd_credits_buffered(1)
    );
  Msub_near_end_pd_credits_buffered_lut_2_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(2),
      I1 => tx_pd_credits_consumed(2),
      O => Msub_near_end_pd_credits_buffered_lut(2)
    );
  Msub_near_end_pd_credits_buffered_cy_2_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(1),
      DI => user_pd_data_credits_in(2),
      S => Msub_near_end_pd_credits_buffered_lut(2),
      O => Msub_near_end_pd_credits_buffered_cy(2)
    );
  Msub_near_end_pd_credits_buffered_xor_2_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(1),
      LI => Msub_near_end_pd_credits_buffered_lut(2),
      O => near_end_pd_credits_buffered(2)
    );
  Msub_near_end_pd_credits_buffered_lut_3_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(3),
      I1 => tx_pd_credits_consumed(3),
      O => Msub_near_end_pd_credits_buffered_lut(3)
    );
  Msub_near_end_pd_credits_buffered_cy_3_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(2),
      DI => user_pd_data_credits_in(3),
      S => Msub_near_end_pd_credits_buffered_lut(3),
      O => Msub_near_end_pd_credits_buffered_cy(3)
    );
  Msub_near_end_pd_credits_buffered_xor_3_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(2),
      LI => Msub_near_end_pd_credits_buffered_lut(3),
      O => near_end_pd_credits_buffered(3)
    );
  Msub_near_end_pd_credits_buffered_lut_4_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(4),
      I1 => tx_pd_credits_consumed(4),
      O => Msub_near_end_pd_credits_buffered_lut(4)
    );
  Msub_near_end_pd_credits_buffered_cy_4_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(3),
      DI => user_pd_data_credits_in(4),
      S => Msub_near_end_pd_credits_buffered_lut(4),
      O => Msub_near_end_pd_credits_buffered_cy(4)
    );
  Msub_near_end_pd_credits_buffered_xor_4_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(3),
      LI => Msub_near_end_pd_credits_buffered_lut(4),
      O => near_end_pd_credits_buffered(4)
    );
  Msub_near_end_pd_credits_buffered_lut_5_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(5),
      I1 => tx_pd_credits_consumed(5),
      O => Msub_near_end_pd_credits_buffered_lut(5)
    );
  Msub_near_end_pd_credits_buffered_cy_5_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(4),
      DI => user_pd_data_credits_in(5),
      S => Msub_near_end_pd_credits_buffered_lut(5),
      O => Msub_near_end_pd_credits_buffered_cy(5)
    );
  Msub_near_end_pd_credits_buffered_xor_5_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(4),
      LI => Msub_near_end_pd_credits_buffered_lut(5),
      O => near_end_pd_credits_buffered(5)
    );
  Msub_near_end_pd_credits_buffered_lut_6_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(6),
      I1 => tx_pd_credits_consumed(6),
      O => Msub_near_end_pd_credits_buffered_lut(6)
    );
  Msub_near_end_pd_credits_buffered_cy_6_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(5),
      DI => user_pd_data_credits_in(6),
      S => Msub_near_end_pd_credits_buffered_lut(6),
      O => Msub_near_end_pd_credits_buffered_cy(6)
    );
  Msub_near_end_pd_credits_buffered_xor_6_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(5),
      LI => Msub_near_end_pd_credits_buffered_lut(6),
      O => near_end_pd_credits_buffered(6)
    );
  Msub_near_end_pd_credits_buffered_lut_7_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(7),
      I1 => tx_pd_credits_consumed(7),
      O => Msub_near_end_pd_credits_buffered_lut(7)
    );
  Msub_near_end_pd_credits_buffered_cy_7_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(6),
      DI => user_pd_data_credits_in(7),
      S => Msub_near_end_pd_credits_buffered_lut(7),
      O => Msub_near_end_pd_credits_buffered_cy(7)
    );
  Msub_near_end_pd_credits_buffered_xor_7_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(6),
      LI => Msub_near_end_pd_credits_buffered_lut(7),
      O => near_end_pd_credits_buffered(7)
    );
  Msub_near_end_pd_credits_buffered_lut_8_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(8),
      I1 => tx_pd_credits_consumed(8),
      O => Msub_near_end_pd_credits_buffered_lut(8)
    );
  Msub_near_end_pd_credits_buffered_cy_8_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(7),
      DI => user_pd_data_credits_in(8),
      S => Msub_near_end_pd_credits_buffered_lut(8),
      O => Msub_near_end_pd_credits_buffered_cy(8)
    );
  Msub_near_end_pd_credits_buffered_xor_8_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(7),
      LI => Msub_near_end_pd_credits_buffered_lut(8),
      O => near_end_pd_credits_buffered(8)
    );
  Msub_near_end_pd_credits_buffered_lut_9_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(9),
      I1 => tx_pd_credits_consumed(9),
      O => Msub_near_end_pd_credits_buffered_lut(9)
    );
  Msub_near_end_pd_credits_buffered_cy_9_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(8),
      DI => user_pd_data_credits_in(9),
      S => Msub_near_end_pd_credits_buffered_lut(9),
      O => Msub_near_end_pd_credits_buffered_cy(9)
    );
  Msub_near_end_pd_credits_buffered_xor_9_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(8),
      LI => Msub_near_end_pd_credits_buffered_lut(9),
      O => near_end_pd_credits_buffered(9)
    );
  Msub_near_end_pd_credits_buffered_lut_10_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(10),
      I1 => tx_pd_credits_consumed(10),
      O => Msub_near_end_pd_credits_buffered_lut(10)
    );
  Msub_near_end_pd_credits_buffered_cy_10_Q : MUXCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(9),
      DI => user_pd_data_credits_in(10),
      S => Msub_near_end_pd_credits_buffered_lut(10),
      O => Msub_near_end_pd_credits_buffered_cy(10)
    );
  Msub_near_end_pd_credits_buffered_xor_10_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(9),
      LI => Msub_near_end_pd_credits_buffered_lut(10),
      O => near_end_pd_credits_buffered(10)
    );
  Msub_near_end_pd_credits_buffered_lut_11_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => user_pd_data_credits_in(11),
      I1 => tx_pd_credits_consumed(11),
      O => Msub_near_end_pd_credits_buffered_lut(11)
    );
  Msub_near_end_pd_credits_buffered_xor_11_Q : XORCY
    port map (
      CI => Msub_near_end_pd_credits_buffered_cy(10),
      LI => Msub_near_end_pd_credits_buffered_lut(11),
      O => near_end_pd_credits_buffered(11)
    );
  Maccum_user_pd_data_credits_in_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(0),
      I1 => td_q2_credits(0),
      O => Maccum_user_pd_data_credits_in_lut(0)
    );
  Maccum_user_pd_data_credits_in_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      DI => user_pd_data_credits_in(0),
      S => Maccum_user_pd_data_credits_in_lut(0),
      O => Maccum_user_pd_data_credits_in_cy(0)
    );
  Maccum_user_pd_data_credits_in_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      LI => Maccum_user_pd_data_credits_in_lut(0),
      O => Result(0)
    );
  Maccum_user_pd_data_credits_in_lut_1_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(1),
      I1 => td_q2_credits(1),
      O => Maccum_user_pd_data_credits_in_lut(1)
    );
  Maccum_user_pd_data_credits_in_cy_1_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(0),
      DI => user_pd_data_credits_in(1),
      S => Maccum_user_pd_data_credits_in_lut(1),
      O => Maccum_user_pd_data_credits_in_cy(1)
    );
  Maccum_user_pd_data_credits_in_xor_1_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(0),
      LI => Maccum_user_pd_data_credits_in_lut(1),
      O => Result(1)
    );
  Maccum_user_pd_data_credits_in_lut_2_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(2),
      I1 => td_q2_credits(2),
      O => Maccum_user_pd_data_credits_in_lut(2)
    );
  Maccum_user_pd_data_credits_in_cy_2_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(1),
      DI => user_pd_data_credits_in(2),
      S => Maccum_user_pd_data_credits_in_lut(2),
      O => Maccum_user_pd_data_credits_in_cy(2)
    );
  Maccum_user_pd_data_credits_in_xor_2_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(1),
      LI => Maccum_user_pd_data_credits_in_lut(2),
      O => Result(2)
    );
  Maccum_user_pd_data_credits_in_lut_3_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(3),
      I1 => td_q2_credits(3),
      O => Maccum_user_pd_data_credits_in_lut(3)
    );
  Maccum_user_pd_data_credits_in_cy_3_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(2),
      DI => user_pd_data_credits_in(3),
      S => Maccum_user_pd_data_credits_in_lut(3),
      O => Maccum_user_pd_data_credits_in_cy(3)
    );
  Maccum_user_pd_data_credits_in_xor_3_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(2),
      LI => Maccum_user_pd_data_credits_in_lut(3),
      O => Result(3)
    );
  Maccum_user_pd_data_credits_in_lut_4_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(4),
      I1 => td_q2_credits(4),
      O => Maccum_user_pd_data_credits_in_lut(4)
    );
  Maccum_user_pd_data_credits_in_cy_4_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(3),
      DI => user_pd_data_credits_in(4),
      S => Maccum_user_pd_data_credits_in_lut(4),
      O => Maccum_user_pd_data_credits_in_cy(4)
    );
  Maccum_user_pd_data_credits_in_xor_4_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(3),
      LI => Maccum_user_pd_data_credits_in_lut(4),
      O => Result(4)
    );
  Maccum_user_pd_data_credits_in_lut_5_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => user_pd_data_credits_in(5),
      I1 => td_q2_credits(5),
      O => Maccum_user_pd_data_credits_in_lut(5)
    );
  Maccum_user_pd_data_credits_in_cy_5_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(4),
      DI => user_pd_data_credits_in(5),
      S => Maccum_user_pd_data_credits_in_lut(5),
      O => Maccum_user_pd_data_credits_in_cy(5)
    );
  Maccum_user_pd_data_credits_in_xor_5_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(4),
      LI => Maccum_user_pd_data_credits_in_lut(5),
      O => Result(5)
    );
  Maccum_user_pd_data_credits_in_cy_6_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(5),
      DI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      S => Maccum_user_pd_data_credits_in_cy_6_rt_23073,
      O => Maccum_user_pd_data_credits_in_cy(6)
    );
  Maccum_user_pd_data_credits_in_xor_6_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(5),
      LI => Maccum_user_pd_data_credits_in_cy_6_rt_23073,
      O => Result(6)
    );
  Maccum_user_pd_data_credits_in_cy_7_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(6),
      DI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      S => Maccum_user_pd_data_credits_in_cy_7_rt_23075,
      O => Maccum_user_pd_data_credits_in_cy(7)
    );
  Maccum_user_pd_data_credits_in_xor_7_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(6),
      LI => Maccum_user_pd_data_credits_in_cy_7_rt_23075,
      O => Result(7)
    );
  Maccum_user_pd_data_credits_in_cy_8_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(7),
      DI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      S => Maccum_user_pd_data_credits_in_cy_8_rt_23077,
      O => Maccum_user_pd_data_credits_in_cy(8)
    );
  Maccum_user_pd_data_credits_in_xor_8_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(7),
      LI => Maccum_user_pd_data_credits_in_cy_8_rt_23077,
      O => Result(8)
    );
  Maccum_user_pd_data_credits_in_cy_9_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(8),
      DI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      S => Maccum_user_pd_data_credits_in_cy_9_rt_23079,
      O => Maccum_user_pd_data_credits_in_cy(9)
    );
  Maccum_user_pd_data_credits_in_xor_9_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(8),
      LI => Maccum_user_pd_data_credits_in_cy_9_rt_23079,
      O => Result(9)
    );
  Maccum_user_pd_data_credits_in_cy_10_Q : MUXCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(9),
      DI => NlwRenamedSig_OI_llk_tx_enable_n(1),
      S => Maccum_user_pd_data_credits_in_cy_10_rt_23066,
      O => Maccum_user_pd_data_credits_in_cy(10)
    );
  Maccum_user_pd_data_credits_in_xor_10_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(9),
      LI => Maccum_user_pd_data_credits_in_cy_10_rt_23066,
      O => Result(10)
    );
  Maccum_user_pd_data_credits_in_xor_11_Q : XORCY
    port map (
      CI => Maccum_user_pd_data_credits_in_cy(10),
      LI => Maccum_user_pd_data_credits_in_xor_11_rt_23086,
      O => Result(11)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(1),
      I1 => near_end_pd_credits_buffered(0),
      I2 => tx_pd_credits_available(0),
      I3 => tx_pd_credits_available(1),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi_23103
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_0_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(0),
      I1 => tx_pd_credits_available(0),
      I2 => near_end_pd_credits_buffered(1),
      I3 => tx_pd_credits_available(1),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(0)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_llk_tx_eop_n,
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi_23103,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(0),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(0)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi1 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(3),
      I1 => near_end_pd_credits_buffered(2),
      I2 => tx_pd_credits_available(2),
      I3 => tx_pd_credits_available(3),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi1_23104
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_1_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(2),
      I1 => tx_pd_credits_available(2),
      I2 => near_end_pd_credits_buffered(3),
      I3 => tx_pd_credits_available(3),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(1)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(0),
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi1_23104,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(1),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(1)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi2 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(5),
      I1 => near_end_pd_credits_buffered(4),
      I2 => tx_pd_credits_available(4),
      I3 => tx_pd_credits_available(5),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi2_23105
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_2_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(4),
      I1 => tx_pd_credits_available(4),
      I2 => near_end_pd_credits_buffered(5),
      I3 => tx_pd_credits_available(5),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(2)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(1),
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi2_23105,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(2),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(2)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi3 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(7),
      I1 => near_end_pd_credits_buffered(6),
      I2 => tx_pd_credits_available(6),
      I3 => tx_pd_credits_available(7),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi3_23106
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_3_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(6),
      I1 => tx_pd_credits_available(6),
      I2 => near_end_pd_credits_buffered(7),
      I3 => tx_pd_credits_available(7),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(3)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(2),
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi3_23106,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(3),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(3)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi4 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(9),
      I1 => near_end_pd_credits_buffered(8),
      I2 => tx_pd_credits_available(8),
      I3 => tx_pd_credits_available(9),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi4_23107
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_4_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(8),
      I1 => tx_pd_credits_available(8),
      I2 => near_end_pd_credits_buffered(9),
      I3 => tx_pd_credits_available(9),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(4)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(3),
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi4_23107,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(4),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(4)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi5 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => near_end_pd_credits_buffered(11),
      I1 => near_end_pd_credits_buffered(10),
      I2 => tx_pd_credits_available(10),
      I3 => tx_pd_credits_available(11),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi5_23108
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut_5_Q : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => near_end_pd_credits_buffered(10),
      I1 => tx_pd_credits_available(10),
      I2 => near_end_pd_credits_buffered(11),
      I3 => tx_pd_credits_available(11),
      O => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(5)
    );
  Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_cy(4),
      DI => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lutdi5_23108,
      S => Mcompar_pd_credits_near_gte_far_cmp_ge0000_lut(5),
      O => pd_credits_near_gte_far_cmp_ge0000
    );
  shift_pipe1 : LUT6
    generic map(
      INIT => X"23232323232323FF"
    )
    port map (
      I0 => shift_pipe_input0,
      I1 => vld_q3_23754,
      I2 => trn_tsrc_rdy_n,
      I3 => llk_tx_src_rdy_n_int,
      I4 => llk_tlp_halt_23225,
      I5 => llk_tx_dst_rdy_n,
      O => shift_pipe
    );
  llk_tx_src_rdy_n1 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => llk_tlp_halt_23225,
      I1 => vld_q3_23754,
      I2 => N1,
      I3 => sof_gap_q3_and_block_23280,
      O => llk_tx_src_rdy_n
    );
  rem_q2_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => eof_q1_23191,
      I1 => rem_q1_23268,
      O => rem_q2_or0000
    );
  eof_q3_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => eof_q2_23201,
      I1 => vld_q2_23753,
      O => eof_q3_and0000
    );
  fifo_q2_and00071 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => td_q1(57),
      I1 => td_q1(59),
      I2 => td_q1(60),
      I3 => td_q1(61),
      I4 => td_q1(58),
      O => fifo_q2_and0007
    );
  pd_q1_reg_or00001 : LUT6
    generic map(
      INIT => X"4040404400000004"
    )
    port map (
      I0 => td_q1(59),
      I1 => td_q1(62),
      I2 => td_q1(60),
      I3 => td_q1(57),
      I4 => td_q1(58),
      I5 => td_q1(61),
      O => pd_q1_reg_or0000
    );
  td_buf_and00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      O => td_buf_not0001_inv
    );
  block_sof_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => sof_q2_23287,
      I1 => tc_fifo_change_23291,
      O => block_sof_not0001
    );
  sofpd_q2_rose1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => pd_q1_reg_23264,
      I1 => sof_q2_23287,
      I2 => sof_q2_reg_23288,
      O => sofpd_q2_rose
    );
  sof_gap_q3_and_block_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => tc_fifo_change_23291,
      O => sof_gap_q3_and_block_or0000
    );
  block_cnt_1_mux00001 : LUT4
    generic map(
      INIT => X"CDC8"
    )
    port map (
      I0 => llk_tlp_halt_23225,
      I1 => block_cnt(1),
      I2 => llk_tx_dst_rdy_n,
      I3 => block_cnt(0),
      O => block_cnt_1_mux0000
    );
  len_eq1_q2_and000030 : LUT6
    generic map(
      INIT => X"AAAAAAAA00000002"
    )
    port map (
      I0 => td_q1(32),
      I1 => td_q1(59),
      I2 => td_q1(60),
      I3 => td_q1(58),
      I4 => td_q1(57),
      I5 => td_q1(62),
      O => len_eq1_q2_and000030_23223
    );
  len_eq1_q2_and000066 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => td_q1(40),
      I1 => td_q1(41),
      I2 => td_q1(34),
      I3 => td_q1(33),
      I4 => td_q1(39),
      I5 => td_q1(38),
      O => len_eq1_q2_and000066_23224
    );
  block_fifo_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => block_cnt(1),
      I1 => llk_tlp_halt_23225,
      I2 => llk_tx_dst_rdy_n,
      O => block_fifo_and0000
    );
  Madd_td_q2_credits_add0000_lut_0_1 : LUT3
    generic map(
      INIT => X"56"
    )
    port map (
      I0 => td_q1(34),
      I1 => td_q1(33),
      I2 => td_q1(32),
      O => Madd_td_q2_credits_add0000_lut(0)
    );
  Madd_td_q2_credits_add0000_xor_4_11 : LUT4
    generic map(
      INIT => X"9AAA"
    )
    port map (
      I0 => td_q1(38),
      I1 => N91,
      I2 => td_q1(37),
      I3 => td_q1(36),
      O => td_q2_credits_add0000(4)
    );
  Madd_td_q2_credits_add0000_xor_5_11 : LUT5
    generic map(
      INIT => X"9CCCCCCC"
    )
    port map (
      I0 => N91,
      I1 => td_q1(39),
      I2 => td_q1(38),
      I3 => td_q1(37),
      I4 => td_q1(36),
      O => td_q2_credits_add0000(5)
    );
  trn_tdst_rdy_n_not00011 : LUT5
    generic map(
      INIT => X"55550100"
    )
    port map (
      I0 => shift_pipe,
      I1 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I2 => trn_tsrc_rdy_n,
      I3 => vld_q1_23751,
      I4 => vld_buf_23749,
      O => trn_tdst_rdy_n_not0001
    );
  llk_tx_ch_tc_and0000_SW0 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => tc_q3(2),
      I1 => NlwRenamedSig_OI_llk_tx_ch_tc(2),
      I2 => tc_q3(1),
      I3 => NlwRenamedSig_OI_llk_tx_ch_tc(1),
      I4 => tc_q3(0),
      I5 => NlwRenamedSig_OI_llk_tx_ch_tc(0),
      O => N4
    );
  llk_tx_ch_tc_and0000 : LUT6
    generic map(
      INIT => X"060F0F060F0F0F0F"
    )
    port map (
      I0 => fifo_q3(1),
      I1 => NlwRenamedSig_OI_llk_tx_ch_fifo(1),
      I2 => block_fifo_23166,
      I3 => fifo_q3(0),
      I4 => NlwRenamedSig_OI_llk_tx_ch_fifo(0),
      I5 => N4,
      O => llk_tx_ch_tc_not0001_inv
    );
  tc_fifo_change_or00002 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => block_fifo_23166,
      O => tc_fifo_change_or00002_23293
    );
  tc_fifo_change_or000079 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_tx_ch_tc(1),
      I1 => tc_q3(1),
      I2 => fifo_q3(1),
      I3 => NlwRenamedSig_OI_llk_tx_ch_fifo(1),
      I4 => fifo_q3(0),
      I5 => NlwRenamedSig_OI_llk_tx_ch_fifo(0),
      O => tc_fifo_change_or000079_23294
    );
  fifo_q2_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => sof_q1_23285,
      I1 => shift_pipe,
      O => fifo_q2_and0000
    );
  sof_gap_q3_not00011 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => shift_pipe,
      I1 => sof_q2_23287,
      I2 => vld_q2_23753,
      O => sof_gap_q3_not0001
    );
  td_q1_not00011 : LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      I0 => vld_q1_23751,
      I1 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I2 => trn_tsrc_rdy_n,
      I3 => shift_pipe,
      O => td_q1_not0001
    );
  Madd_cpl_in_count_add0000_Madd_xor_0_113 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => NlwRenamedSig_OI_td_q3(57),
      I1 => NlwRenamedSig_OI_td_q3(59),
      I2 => sof_q3_23289,
      I3 => llk_tx_dst_rdy_n,
      O => Madd_cpl_in_count_add0000_Madd_xor_0_113_23087
    );
  Madd_cpl_in_count_add0000_Madd_xor_0_128 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => sof_gap_q3_and_block_23280,
      I1 => NlwRenamedSig_OI_td_q3(60),
      I2 => NlwRenamedSig_OI_td_q3(61),
      I3 => llk_tlp_halt_23225,
      I4 => vld_q3_23754,
      I5 => NlwRenamedSig_OI_td_q3(58),
      O => Madd_cpl_in_count_add0000_Madd_xor_0_128_23088
    );
  vld_buf_and00001 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => shift_pipe,
      I1 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I2 => trn_tsrc_rdy_n,
      I3 => vld_q1_23751,
      O => vld_buf_and0000
    );
  llk_tlp_halt_cmp_ge000061 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => tx_ch_credits_consumed(0),
      I1 => cpl_in_count(0),
      O => N33
    );
  Madd_cpl_in_count_add0000_Madd_cy_0_11_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_td_q3(60),
      I1 => sof_gap_q3_and_block_23280,
      I2 => llk_tlp_halt_23225,
      I3 => NlwRenamedSig_OI_td_q3(61),
      I4 => sof_q3_23289,
      I5 => NlwRenamedSig_OI_td_q3(58),
      O => N61
    );
  Madd_cpl_in_count_add0000_Madd_cy_0_11 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => NlwRenamedSig_OI_td_q3(57),
      I1 => N1,
      I2 => vld_q3_23754,
      I3 => NlwRenamedSig_OI_td_q3(59),
      I4 => llk_tx_dst_rdy_n,
      I5 => N61,
      O => N18
    );
  llk_tlp_halt_or0000111 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => shift_pipe,
      I1 => sof_q2_23287,
      O => fifo_last_and0000
    );
  sof_gap_q3_and_block_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFF302030A0"
    )
    port map (
      I0 => block_sof_23168,
      I1 => shift_pipe,
      I2 => sof_gap_q3_23279,
      I3 => sof_q2_23287,
      I4 => vld_q2_23753,
      I5 => sof_gap_q3_mux0000_23283,
      O => sof_gap_q3_and_block_mux0000
    );
  sof_gap_q3_mux0000_SW0 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => fifo_q2(1),
      I1 => fifo_last(1),
      I2 => fifo_q2(0),
      I3 => fifo_last(0),
      I4 => tc_q2(2),
      I5 => tc_last(2),
      O => N8
    );
  sof_gap_q3_mux0000 : LUT6
    generic map(
      INIT => X"60F0F060F0F0F0F0"
    )
    port map (
      I0 => tc_last(0),
      I1 => tc_q2(0),
      I2 => fifo_last_and0000,
      I3 => tc_last(1),
      I4 => tc_q2(1),
      I5 => N8,
      O => sof_gap_q3_mux0000_23283
    );
  llk_tlp_halt_or0000196 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => len_eq1_q2_23221,
      I1 => fifo_q2(1),
      I2 => fifo_q2(0),
      I3 => pd_credits_near_gte_far_23262,
      O => llk_tlp_halt_or0000196_23229
    );
  shift_pipe_input01 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => vld_buf_23749,
      I1 => eof_q1_23191,
      I2 => eof_q2_only_23202,
      I3 => eof_q3_only_23206,
      O => shift_pipe_input0
    );
  sof_q1_mux000021 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => shift_pipe,
      I1 => vld_buf_23749,
      O => buf_rd
    );
  dsc_q1_mux000011 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => vld_q1_23751,
      I2 => shift_pipe,
      I3 => trn_tsrc_rdy_n,
      O => N0
    );
  Madd_cpl_in_count_add0000_Madd_xor_0_1110 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => eof_q1_or_eof_q2_only_23194,
      I1 => vld_buf_23749,
      I2 => trn_tsrc_rdy_n,
      I3 => eof_q3_only_23206,
      O => N1
    );
  eof_q3_only_mux000011 : LUT6
    generic map(
      INIT => X"2A2A2A2A2AFF2A2A"
    )
    port map (
      I0 => N0,
      I1 => sof_buf_23277,
      I2 => vld_buf_23749,
      I3 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I4 => trn_tsof_n,
      I5 => trn_tsrc_rdy_n,
      O => N6
    );
  sof_q1_mux0000_SW0 : LUT6
    generic map(
      INIT => X"F111F111F1111111"
    )
    port map (
      I0 => trn_tsof_n,
      I1 => N0,
      I2 => sof_buf_23277,
      I3 => buf_rd,
      I4 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I5 => trn_tsrc_rdy_n,
      O => N10
    );
  sof_q1_mux0000 : LUT5
    generic map(
      INIT => X"FF50EF40"
    )
    port map (
      I0 => shift_pipe,
      I1 => vld_q1_23751,
      I2 => sof_q1_23285,
      I3 => N10,
      I4 => N11,
      O => sof_q1_mux0000_23286
    );
  eof_q1_or_eof_q2_only_mux0001110 : LUT6
    generic map(
      INIT => X"EF2FEA2AEFAFEAAA"
    )
    port map (
      I0 => eof_q1_23191,
      I1 => vld_buf_23749,
      I2 => shift_pipe,
      I3 => eof_buf_23189,
      I4 => eof_q2_only_23202,
      I5 => sof_buf_23277,
      O => eof_q1_or_eof_q2_only_mux0001110_23196
    );
  Msub_cpls_buffered_lut_4_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cpl_in_count(4),
      I1 => tx_ch_credits_consumed(4),
      O => Msub_cpls_buffered_lut_4_Q
    );
  eof_q2_only_mux0000_SW0 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => trn_tsof_n,
      I1 => eof_q2_23201,
      I2 => vld_q1_23751,
      I3 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      O => N13
    );
  eof_q2_only_mux0000 : LUT6
    generic map(
      INIT => X"FFEA554055405540"
    )
    port map (
      I0 => shift_pipe,
      I1 => eof_q2_only_23202,
      I2 => N0,
      I3 => N13,
      I4 => eof_q1_23191,
      I5 => N6,
      O => eof_q2_only_mux0000_23203
    );
  eof_q3_only_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsof_n,
      I2 => sof_q2_23287,
      I3 => trn_tsrc_rdy_n,
      I4 => vld_q1_23751,
      O => N15
    );
  eof_q3_only_mux0000_SW1 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => eof_q2_23201,
      I1 => vld_q2_23753,
      I2 => N6,
      I3 => sof_q1_23285,
      O => N16
    );
  eof_q3_only_mux0000 : LUT6
    generic map(
      INIT => X"40405540EAEAFFEA"
    )
    port map (
      I0 => shift_pipe,
      I1 => N0,
      I2 => eof_q3_only_23206,
      I3 => eof_q3_23204,
      I4 => N15,
      I5 => N16,
      O => eof_q3_only_mux0000_23207
    );
  Msub_cpls_buffered_lut_2_1 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cpl_in_count(2),
      I1 => tx_ch_credits_consumed(2),
      O => Msub_cpls_buffered_lut_2_Q
    );
  Maccum_user_pd_data_credits_in_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(6),
      O => Maccum_user_pd_data_credits_in_cy_6_rt_23073
    );
  Maccum_user_pd_data_credits_in_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(7),
      O => Maccum_user_pd_data_credits_in_cy_7_rt_23075
    );
  Maccum_user_pd_data_credits_in_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(8),
      O => Maccum_user_pd_data_credits_in_cy_8_rt_23077
    );
  Maccum_user_pd_data_credits_in_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(9),
      O => Maccum_user_pd_data_credits_in_cy_9_rt_23079
    );
  Maccum_user_pd_data_credits_in_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(10),
      O => Maccum_user_pd_data_credits_in_cy_10_rt_23066
    );
  Maccum_user_pd_data_credits_in_xor_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => user_pd_data_credits_in(11),
      O => Maccum_user_pd_data_credits_in_xor_11_rt_23086
    );
  len_eq1_q2_and000092 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => len_eq1_q2_and000030_23223,
      I1 => len_eq1_q2_and000066_23224,
      I2 => td_q1(36),
      I3 => td_q1(37),
      I4 => td_q1(35),
      O => len_eq1_q2_and0000
    );
  tc_fifo_change_or000094 : LUT6
    generic map(
      INIT => X"FFFFFFFF90090000"
    )
    port map (
      I0 => NlwRenamedSig_OI_llk_tx_ch_tc(0),
      I1 => tc_q3(0),
      I2 => NlwRenamedSig_OI_llk_tx_ch_tc(2),
      I3 => tc_q3(2),
      I4 => tc_fifo_change_or000079_23294,
      I5 => tc_fifo_change_or00002_23293,
      O => tc_fifo_change_or0000
    );
  llk_tlp_halt_or0000167 : LUT6
    generic map(
      INIT => X"FFFFFF2FFFFFF222"
    )
    port map (
      I0 => cpl_in_count(3),
      I1 => Msub_cpls_buffered_lut_4_Q,
      I2 => Msub_cpls_buffered_lut_2_Q,
      I3 => llk_tlp_halt_or0000150_23227,
      I4 => llk_tlp_halt_or000063_23231,
      I5 => llk_tlp_halt_or000095_23232,
      O => llk_tlp_halt_or0000167_23228
    );
  eof_q1_or_eof_q2_only_mux0001125 : LUT5
    generic map(
      INIT => X"FFFFEEEA"
    )
    port map (
      I0 => eof_q1_or_eof_q2_only_mux000149,
      I1 => eof_q1_or_eof_q2_only_mux0001110_23196,
      I2 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I3 => trn_tsrc_rdy_n,
      I4 => eof_q1_or_eof_q2_only_mux000161_23200,
      O => eof_q1_or_eof_q2_only_mux0001
    );
  sof_q1_mux0000_SW1 : LUT5
    generic map(
      INIT => X"FFFFFF51"
    )
    port map (
      I0 => trn_tsof_n,
      I1 => vld_q1_23751,
      I2 => shift_pipe,
      I3 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      O => N11
    );
  Madd_td_q2_credits_add0000_xor_1_11 : LUT4
    generic map(
      INIT => X"56AA"
    )
    port map (
      I0 => td_q1(35),
      I1 => td_q1(32),
      I2 => td_q1(33),
      I3 => td_q1(34),
      O => td_q2_credits_add0000(1)
    );
  Madd_td_q2_credits_add0000_xor_2_111 : LUT4
    generic map(
      INIT => X"57FF"
    )
    port map (
      I0 => td_q1(35),
      I1 => td_q1(32),
      I2 => td_q1(33),
      I3 => td_q1(34),
      O => N91
    );
  vld_q1_or00001 : LUT5
    generic map(
      INIT => X"FF1FF111"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      I2 => shift_pipe,
      I3 => vld_buf_23749,
      I4 => vld_q1_23751,
      O => vld_q1_or0000
    );
  llk_tlp_halt_or000063 : LUT6
    generic map(
      INIT => X"FFFF0820FFFF88A8"
    )
    port map (
      I0 => N33,
      I1 => Msub_cpls_buffered_lut_2_Q,
      I2 => cpl_in_count(1),
      I3 => tx_ch_credits_consumed(1),
      I4 => llk_tlp_halt_or000051_23230,
      I5 => Msub_cpls_buffered_lut_4_Q,
      O => llk_tlp_halt_or000063_23231
    );
  Madd_cpl_in_count_add0000_Madd_xor_0_176 : LUT6
    generic map(
      INIT => X"FFF9FFFF66606666"
    )
    port map (
      I0 => cpl_in_count(0),
      I1 => l0_stats_cfg_transmitted,
      I2 => Madd_cpl_in_count_add0000_Madd_xor_0_113_23087,
      I3 => Madd_cpl_in_count_add0000_Madd_xor_0_128_23088,
      I4 => N1,
      I5 => N18,
      O => cpl_in_count_add0000(0)
    );
  td_q1_mux0000_9_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(9),
      I4 => td_buf(9),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(9)
    );
  td_q1_mux0000_8_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(8),
      I4 => td_buf(8),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(8)
    );
  td_q1_mux0000_7_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(7),
      I4 => td_buf(7),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(7)
    );
  td_q1_mux0000_6_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(6),
      I4 => td_buf(6),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(6)
    );
  td_q1_mux0000_63_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(63),
      I4 => td_buf(63),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(63)
    );
  td_q1_mux0000_62_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(62),
      I4 => td_buf(62),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(62)
    );
  td_q1_mux0000_61_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(61),
      I4 => td_buf(61),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(61)
    );
  td_q1_mux0000_60_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(60),
      I4 => td_buf(60),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(60)
    );
  td_q1_mux0000_5_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(5),
      I4 => td_buf(5),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(5)
    );
  td_q1_mux0000_59_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(59),
      I4 => td_buf(59),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(59)
    );
  td_q1_mux0000_58_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(58),
      I4 => td_buf(58),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(58)
    );
  td_q1_mux0000_57_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(57),
      I4 => td_buf(57),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(57)
    );
  td_q1_mux0000_56_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(56),
      I4 => td_buf(56),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(56)
    );
  td_q1_mux0000_55_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(55),
      I4 => td_buf(55),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(55)
    );
  td_q1_mux0000_54_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(54),
      I4 => td_buf(54),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(54)
    );
  td_q1_mux0000_53_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(53),
      I4 => td_buf(53),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(53)
    );
  td_q1_mux0000_52_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(52),
      I4 => td_buf(52),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(52)
    );
  td_q1_mux0000_51_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(51),
      I4 => td_buf(51),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(51)
    );
  td_q1_mux0000_50_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(50),
      I4 => td_buf(50),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(50)
    );
  td_q1_mux0000_4_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(4),
      I4 => td_buf(4),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(4)
    );
  td_q1_mux0000_49_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(49),
      I4 => td_buf(49),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(49)
    );
  td_q1_mux0000_48_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(48),
      I4 => td_buf(48),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(48)
    );
  td_q1_mux0000_47_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(47),
      I4 => td_buf(47),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(47)
    );
  td_q1_mux0000_46_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(46),
      I4 => td_buf(46),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(46)
    );
  td_q1_mux0000_45_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(45),
      I4 => td_buf(45),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(45)
    );
  td_q1_mux0000_44_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(44),
      I4 => td_buf(44),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(44)
    );
  td_q1_mux0000_43_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(43),
      I4 => td_buf(43),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(43)
    );
  td_q1_mux0000_42_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(42),
      I4 => td_buf(42),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(42)
    );
  td_q1_mux0000_41_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(41),
      I4 => td_buf(41),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(41)
    );
  td_q1_mux0000_40_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(40),
      I4 => td_buf(40),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(40)
    );
  td_q1_mux0000_3_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(3),
      I4 => td_buf(3),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(3)
    );
  td_q1_mux0000_39_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(39),
      I4 => td_buf(39),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(39)
    );
  td_q1_mux0000_38_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(38),
      I4 => td_buf(38),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(38)
    );
  td_q1_mux0000_37_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(37),
      I4 => td_buf(37),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(37)
    );
  td_q1_mux0000_36_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(36),
      I4 => td_buf(36),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(36)
    );
  td_q1_mux0000_35_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(35),
      I4 => td_buf(35),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(35)
    );
  td_q1_mux0000_34_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(34),
      I4 => td_buf(34),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(34)
    );
  td_q1_mux0000_33_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(33),
      I4 => td_buf(33),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(33)
    );
  td_q1_mux0000_32_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(32),
      I4 => td_buf(32),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(32)
    );
  td_q1_mux0000_31_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(31),
      I4 => td_buf(31),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(31)
    );
  td_q1_mux0000_30_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(30),
      I4 => td_buf(30),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(30)
    );
  td_q1_mux0000_2_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(2),
      I4 => td_buf(2),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(2)
    );
  td_q1_mux0000_29_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(29),
      I4 => td_buf(29),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(29)
    );
  td_q1_mux0000_28_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(28),
      I4 => td_buf(28),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(28)
    );
  td_q1_mux0000_27_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(27),
      I4 => td_buf(27),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(27)
    );
  td_q1_mux0000_26_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(26),
      I4 => td_buf(26),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(26)
    );
  td_q1_mux0000_25_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(25),
      I4 => td_buf(25),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(25)
    );
  td_q1_mux0000_24_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(24),
      I4 => td_buf(24),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(24)
    );
  td_q1_mux0000_23_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(23),
      I4 => td_buf(23),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(23)
    );
  td_q1_mux0000_22_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(22),
      I4 => td_buf(22),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(22)
    );
  td_q1_mux0000_21_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(21),
      I4 => td_buf(21),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(21)
    );
  td_q1_mux0000_20_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(20),
      I4 => td_buf(20),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(20)
    );
  td_q1_mux0000_1_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(1),
      I4 => td_buf(1),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(1)
    );
  td_q1_mux0000_19_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(19),
      I4 => td_buf(19),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(19)
    );
  td_q1_mux0000_18_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(18),
      I4 => td_buf(18),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(18)
    );
  td_q1_mux0000_17_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(17),
      I4 => td_buf(17),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(17)
    );
  td_q1_mux0000_16_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(16),
      I4 => td_buf(16),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(16)
    );
  td_q1_mux0000_15_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(15),
      I4 => td_buf(15),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(15)
    );
  td_q1_mux0000_14_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(14),
      I4 => td_buf(14),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(14)
    );
  td_q1_mux0000_13_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(13),
      I4 => td_buf(13),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(13)
    );
  td_q1_mux0000_12_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(12),
      I4 => td_buf(12),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(12)
    );
  td_q1_mux0000_11_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(11),
      I4 => td_buf(11),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(11)
    );
  td_q1_mux0000_10_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(10),
      I4 => td_buf(10),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(10)
    );
  td_q1_mux0000_0_1 : LUT6
    generic map(
      INIT => X"FFFB0400FFFA0500"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_td(0),
      I4 => td_buf(0),
      I5 => vld_q1_23751,
      O => td_q1_mux0000(0)
    );
  rem_q1_mux00001 : LUT6
    generic map(
      INIT => X"FBFF0004FAFF0005"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_trem_n(0),
      I4 => rem_buf_23266,
      I5 => vld_q1_23751,
      O => rem_q1_mux0000
    );
  eof_q1_mux00001 : LUT6
    generic map(
      INIT => X"FBFF0004FAFF0005"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_teof_n,
      I4 => eof_buf_23189,
      I5 => vld_q1_23751,
      O => eof_q1_mux0000
    );
  dsc_q1_mux00002 : LUT6
    generic map(
      INIT => X"FBFF0004FAFF0005"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_tsrc_dsc_n,
      I4 => dsc_buf_23183,
      I5 => vld_q1_23751,
      O => dsc_q1_mux0000
    );
  llk_tlp_halt_or0000212 : LUT6
    generic map(
      INIT => X"FFFFF00088888000"
    )
    port map (
      I0 => llk_tlp_halt_or0000167_23228,
      I1 => fifo_q2(1),
      I2 => sof_q2_23287,
      I3 => shift_pipe,
      I4 => llk_tlp_halt_23225,
      I5 => llk_tlp_halt_or0000196_23229,
      O => llk_tlp_halt_or0000
    );
  llk_tx_src_rdy_n_int1 : LUT6
    generic map(
      INIT => X"DDDDDDDDDDDFDDDD"
    )
    port map (
      I0 => vld_q3_23754,
      I1 => sof_gap_q3_and_block_23280,
      I2 => vld_buf_23749,
      I3 => eof_q3_only_23206,
      I4 => trn_tsrc_rdy_n,
      I5 => eof_q1_or_eof_q2_only_23194,
      O => llk_tx_src_rdy_n_int
    );
  eof_q1_or_eof_q2_only_mux000161 : LUT5
    generic map(
      INIT => X"00040005"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => shift_pipe,
      I2 => trn_tsrc_rdy_n,
      I3 => trn_teof_n,
      I4 => vld_q1_23751,
      O => eof_q1_or_eof_q2_only_mux000161_23200
    );
  eof_q1_not00011 : LUT5
    generic map(
      INIT => X"888A888F"
    )
    port map (
      I0 => shift_pipe,
      I1 => vld_buf_23749,
      I2 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I3 => trn_tsrc_rdy_n,
      I4 => vld_q1_23751,
      O => eof_q1_not0001
    );
  Madd_td_q2_credits_add0000_xor_2_12 : LUT5
    generic map(
      INIT => X"666AAAAA"
    )
    port map (
      I0 => td_q1(36),
      I1 => td_q1(35),
      I2 => td_q1(32),
      I3 => td_q1(33),
      I4 => td_q1(34),
      O => td_q2_credits_add0000(2)
    );
  Madd_td_q2_credits_add0000_xor_3_11 : LUT6
    generic map(
      INIT => X"36CCCCCCCCCCCCCC"
    )
    port map (
      I0 => td_q1(33),
      I1 => td_q1(37),
      I2 => td_q1(32),
      I3 => td_q1(36),
      I4 => td_q1(34),
      I5 => td_q1(35),
      O => td_q2_credits_add0000(3)
    );
  Madd_cpl_in_count_add0000_Madd_xor_1_11 : LUT4
    generic map(
      INIT => X"566A"
    )
    port map (
      I0 => cpl_in_count(1),
      I1 => cpl_in_count(0),
      I2 => l0_stats_cfg_transmitted,
      I3 => N18,
      O => cpl_in_count_add0000(1)
    );
  Madd_cpl_in_count_add0000_Madd_xor_2_11 : LUT5
    generic map(
      INIT => X"1E78F0F0"
    )
    port map (
      I0 => cpl_in_count(0),
      I1 => l0_stats_cfg_transmitted,
      I2 => cpl_in_count(2),
      I3 => N18,
      I4 => cpl_in_count(1),
      O => cpl_in_count_add0000(2)
    );
  Madd_cpl_in_count_add0000_Madd_xor_3_11 : LUT6
    generic map(
      INIT => X"1E78F0F0F0F0F0F0"
    )
    port map (
      I0 => cpl_in_count(0),
      I1 => l0_stats_cfg_transmitted,
      I2 => cpl_in_count(3),
      I3 => N18,
      I4 => cpl_in_count(1),
      I5 => cpl_in_count(2),
      O => cpl_in_count_add0000(3)
    );
  llk_tlp_halt_or000051 : LUT4
    generic map(
      INIT => X"0090"
    )
    port map (
      I0 => cpl_in_count(4),
      I1 => tx_ch_credits_consumed(4),
      I2 => tx_ch_credits_consumed(3),
      I3 => cpl_in_count(3),
      O => llk_tlp_halt_or000051_23230
    );
  llk_tlp_halt_or0000150 : LUT6
    generic map(
      INIT => X"3AA3BAAB1FF1BFFB"
    )
    port map (
      I0 => cpl_in_count(1),
      I1 => N33,
      I2 => tx_ch_credits_consumed(3),
      I3 => cpl_in_count(3),
      I4 => Msub_cpls_buffered_lut_4_Q,
      I5 => tx_ch_credits_consumed(1),
      O => llk_tlp_halt_or0000150_23227
    );
  llk_tlp_halt_or000095 : LUT5
    generic map(
      INIT => X"69EBEB69"
    )
    port map (
      I0 => cpl_in_count(2),
      I1 => cpl_in_count(3),
      I2 => tx_ch_credits_consumed(3),
      I3 => cpl_in_count(4),
      I4 => tx_ch_credits_consumed(4),
      O => llk_tlp_halt_or000095_23232
    );
  llk_tx_src_dsc_n1_INV_0 : INV
    port map (
      I => dsc_q3_23188,
      O => llk_tx_src_dsc_n
    );
  llk_tx_sof_n1_INV_0 : INV
    port map (
      I => sof_q3_23289,
      O => llk_tx_sof_n
    );
  llk_tx_eof_n1_INV_0 : INV
    port map (
      I => eof_q3_23204,
      O => llk_tx_eof_n
    );
  llk_tx_enable_n_not00011_INV_0 : INV
    port map (
      I => rem_q3_23272,
      O => llk_tx_enable_n(0)
    );
  sof_buf_not00011_INV_0 : INV
    port map (
      I => trn_tsof_n,
      O => sof_buf_not0001
    );
  rem_buf_not00011_INV_0 : INV
    port map (
      I => trn_trem_n(0),
      O => rem_buf_not0001
    );
  eof_buf_not00011_INV_0 : INV
    port map (
      I => trn_teof_n,
      O => eof_buf_not0001
    );
  dsc_buf_not00011_INV_0 : INV
    port map (
      I => trn_tsrc_dsc_n,
      O => dsc_buf_not0001
    );
  block_sof_mux00001_INV_0 : INV
    port map (
      I => tc_fifo_change_23291,
      O => block_sof_mux0000
    );
  rst_n_inv401_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  pd_credit_limited_inv1_INV_0 : INV
    port map (
      I => pd_credit_limited,
      O => pd_credit_limited_inv
    );
  fifo_q2_or00011 : LUT6
    generic map(
      INIT => X"0000001100000100"
    )
    port map (
      I0 => td_q1(61),
      I1 => td_q1(60),
      I2 => td_q1(56),
      I3 => td_q1(57),
      I4 => td_q1(59),
      I5 => td_q1(58),
      O => fifo_q2_or00011_23216
    );
  fifo_q2_or00012 : LUT6
    generic map(
      INIT => X"0000000100070007"
    )
    port map (
      I0 => td_q1(61),
      I1 => td_q1(58),
      I2 => td_q1(60),
      I3 => td_q1(59),
      I4 => td_q1(56),
      I5 => td_q1(57),
      O => fifo_q2_or00012_23217
    );
  fifo_q2_or0001_f7 : MUXF7
    port map (
      I0 => fifo_q2_or00012_23217,
      I1 => fifo_q2_or00011_23216,
      S => td_q1(62),
      O => fifo_q2_or0001
    );
  block_cnt_0_mux00001 : LUT6
    generic map(
      INIT => X"EEFEEEEE00100000"
    )
    port map (
      I0 => llk_tx_dst_rdy_n,
      I1 => llk_tlp_halt_23225,
      I2 => N1,
      I3 => sof_gap_q3_and_block_23280,
      I4 => eof_q3_23204,
      I5 => block_cnt(0),
      O => block_cnt_0_mux00001_23162
    );
  block_cnt_0_mux00002 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => block_cnt(0),
      I1 => llk_tx_dst_rdy_n,
      I2 => llk_tlp_halt_23225,
      O => block_cnt_0_mux00002_23163
    );
  block_cnt_0_mux0000_f7 : MUXF7
    port map (
      I0 => block_cnt_0_mux00002_23163,
      I1 => block_cnt_0_mux00001_23162,
      S => vld_q3_23754,
      O => block_cnt_0_mux0000
    );
  Madd_cpl_in_count_add0000_Madd_xor_4_111 : LUT6
    generic map(
      INIT => X"36CCCCCCCCCCCCCC"
    )
    port map (
      I0 => cpl_in_count(0),
      I1 => cpl_in_count(4),
      I2 => l0_stats_cfg_transmitted,
      I3 => cpl_in_count(1),
      I4 => cpl_in_count(2),
      I5 => cpl_in_count(3),
      O => Madd_cpl_in_count_add0000_Madd_xor_4_11
    );
  Madd_cpl_in_count_add0000_Madd_xor_4_112 : LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
    port map (
      I0 => cpl_in_count(0),
      I1 => cpl_in_count(4),
      I2 => l0_stats_cfg_transmitted,
      I3 => cpl_in_count(1),
      I4 => cpl_in_count(2),
      I5 => cpl_in_count(3),
      O => Madd_cpl_in_count_add0000_Madd_xor_4_111_23090
    );
  Madd_cpl_in_count_add0000_Madd_xor_4_11_f7 : MUXF7
    port map (
      I0 => Madd_cpl_in_count_add0000_Madd_xor_4_111_23090,
      I1 => Madd_cpl_in_count_add0000_Madd_xor_4_11,
      S => N18,
      O => cpl_in_count_add0000(4)
    );
  eof_q1_or_eof_q2_only_mux0001491 : LUT6
    generic map(
      INIT => X"5454545454F45454"
    )
    port map (
      I0 => shift_pipe,
      I1 => eof_q2_only_23202,
      I2 => eof_q1_23191,
      I3 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I4 => trn_tsof_n,
      I5 => trn_tsrc_rdy_n,
      O => eof_q1_or_eof_q2_only_mux0001491_23198
    );
  eof_q1_or_eof_q2_only_mux0001492 : LUT6
    generic map(
      INIT => X"0030001000200000"
    )
    port map (
      I0 => shift_pipe,
      I1 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I2 => trn_tsof_n,
      I3 => trn_tsrc_rdy_n,
      I4 => eof_q1_23191,
      I5 => eof_q2_23201,
      O => eof_q1_or_eof_q2_only_mux0001492_23199
    );
  eof_q1_or_eof_q2_only_mux000149_f7 : MUXF7
    port map (
      I0 => eof_q1_or_eof_q2_only_mux0001492_23199,
      I1 => eof_q1_or_eof_q2_only_mux0001491_23198,
      S => vld_q1_23751,
      O => eof_q1_or_eof_q2_only_mux000149
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll_tx_arb is
  port (
    tx_src_rdy_n : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    tx_sof_n : out STD_LOGIC; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_tx_dst_rdy_n : out STD_LOGIC; 
    cfg_tx_eof_n : in STD_LOGIC := 'X'; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
    cfg_tx_sof_n : in STD_LOGIC := 'X'; 
    tx_src_dsc_n : out STD_LOGIC; 
    tx_dst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    cfg_tx_rem_n : in STD_LOGIC := 'X'; 
    tx_eof_n : out STD_LOGIC; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    tx_rem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end pcie_blk_ll_tx_arb;

architecture STRUCTURE of pcie_blk_ll_tx_arb is
  signal N0 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N205 : STD_LOGIC; 
  signal N208 : STD_LOGIC; 
  signal N210 : STD_LOGIC; 
  signal N212 : STD_LOGIC; 
  signal N214 : STD_LOGIC; 
  signal N216 : STD_LOGIC; 
  signal N218 : STD_LOGIC; 
  signal N220 : STD_LOGIC; 
  signal N222 : STD_LOGIC; 
  signal N224 : STD_LOGIC; 
  signal N226 : STD_LOGIC; 
  signal N228 : STD_LOGIC; 
  signal N230 : STD_LOGIC; 
  signal N232 : STD_LOGIC; 
  signal N234 : STD_LOGIC; 
  signal N236 : STD_LOGIC; 
  signal N238 : STD_LOGIC; 
  signal N240 : STD_LOGIC; 
  signal N242 : STD_LOGIC; 
  signal N244 : STD_LOGIC; 
  signal N246 : STD_LOGIC; 
  signal N248 : STD_LOGIC; 
  signal N250 : STD_LOGIC; 
  signal N252 : STD_LOGIC; 
  signal N254 : STD_LOGIC; 
  signal N256 : STD_LOGIC; 
  signal N258 : STD_LOGIC; 
  signal N260 : STD_LOGIC; 
  signal N262 : STD_LOGIC; 
  signal N264 : STD_LOGIC; 
  signal N266 : STD_LOGIC; 
  signal N268 : STD_LOGIC; 
  signal N270 : STD_LOGIC; 
  signal N272 : STD_LOGIC; 
  signal N274 : STD_LOGIC; 
  signal N276 : STD_LOGIC; 
  signal N278 : STD_LOGIC; 
  signal N280 : STD_LOGIC; 
  signal N282 : STD_LOGIC; 
  signal N284 : STD_LOGIC; 
  signal N286 : STD_LOGIC; 
  signal N288 : STD_LOGIC; 
  signal N290 : STD_LOGIC; 
  signal N292 : STD_LOGIC; 
  signal N294 : STD_LOGIC; 
  signal N296 : STD_LOGIC; 
  signal N298 : STD_LOGIC; 
  signal N300 : STD_LOGIC; 
  signal N302 : STD_LOGIC; 
  signal N304 : STD_LOGIC; 
  signal N306 : STD_LOGIC; 
  signal N308 : STD_LOGIC; 
  signal N310 : STD_LOGIC; 
  signal N312 : STD_LOGIC; 
  signal N314 : STD_LOGIC; 
  signal N316 : STD_LOGIC; 
  signal N318 : STD_LOGIC; 
  signal N320 : STD_LOGIC; 
  signal N322 : STD_LOGIC; 
  signal N324 : STD_LOGIC; 
  signal N326 : STD_LOGIC; 
  signal N328 : STD_LOGIC; 
  signal N330 : STD_LOGIC; 
  signal N332 : STD_LOGIC; 
  signal N334 : STD_LOGIC; 
  signal N336 : STD_LOGIC; 
  signal N338 : STD_LOGIC; 
  signal N340 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal buf_eof_n_22632 : STD_LOGIC; 
  signal buf_eof_n_mux0000 : STD_LOGIC; 
  signal buf_rem_n_22634 : STD_LOGIC; 
  signal buf_rem_n_mux0000 : STD_LOGIC; 
  signal buf_sof_n_22636 : STD_LOGIC; 
  signal buf_sof_n_mux0000 : STD_LOGIC; 
  signal buf_td_not0001 : STD_LOGIC; 
  signal buf_vld_22767 : STD_LOGIC; 
  signal buf_vld_mux0000 : STD_LOGIC; 
  signal buf_vld_not0001 : STD_LOGIC; 
  signal cfg_done : STD_LOGIC; 
  signal cfg_in_pkt_22771 : STD_LOGIC; 
  signal cfg_start : STD_LOGIC; 
  signal NlwRenamedSig_OI_cfg_tx_dst_rdy_n : STD_LOGIC; 
  signal cfg_tx_dst_rdy_n_or0000_22774 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_tdst_rdy_n : STD_LOGIC; 
  signal trn_tdst_rdy_n_or0000 : STD_LOGIC; 
  signal trn_tdst_rdy_n_or00001_22912 : STD_LOGIC; 
  signal trn_tdst_rdy_n_or00002_22913 : STD_LOGIC; 
  signal trn_tdst_rdy_n_or0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_eof_n : STD_LOGIC; 
  signal tx_eof_n_mux0000_22921 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_rem_n_bit : STD_LOGIC; 
  signal tx_rem_n_bit_mux0000_22924 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_sof_n : STD_LOGIC; 
  signal tx_sof_n_mux0000_22926 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_src_dsc_n : STD_LOGIC; 
  signal tx_src_dsc_n_mux0000_22928 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_src_rdy_n : STD_LOGIC; 
  signal tx_src_rdy_n_mux0000 : STD_LOGIC; 
  signal tx_src_rdy_n_not0001 : STD_LOGIC; 
  signal tx_td_or0000 : STD_LOGIC; 
  signal usr_done : STD_LOGIC; 
  signal usr_in_pkt_23062 : STD_LOGIC; 
  signal usr_start : STD_LOGIC; 
  signal buf_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal buf_td_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal NlwRenamedSig_OI_tx_rem_n : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal NlwRenamedSig_OI_tx_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal tx_td_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  tx_src_rdy_n <= NlwRenamedSig_OI_tx_src_rdy_n;
  tx_sof_n <= NlwRenamedSig_OI_tx_sof_n;
  cfg_tx_dst_rdy_n <= NlwRenamedSig_OI_cfg_tx_dst_rdy_n;
  trn_tdst_rdy_n <= NlwRenamedSig_OI_trn_tdst_rdy_n;
  tx_src_dsc_n <= NlwRenamedSig_OI_tx_src_dsc_n;
  tx_eof_n <= NlwRenamedSig_OI_tx_eof_n;
  tx_rem_n(7) <= NlwRenamedSig_OI_tx_rem_n(4);
  tx_rem_n(6) <= NlwRenamedSig_OI_tx_rem_n(4);
  tx_rem_n(5) <= NlwRenamedSig_OI_tx_rem_n(4);
  tx_rem_n(4) <= NlwRenamedSig_OI_tx_rem_n(4);
  tx_rem_n(3) <= NlwRenamedSig_OI_tx_rem_n_bit;
  tx_rem_n(2) <= NlwRenamedSig_OI_tx_rem_n_bit;
  tx_rem_n(1) <= NlwRenamedSig_OI_tx_rem_n_bit;
  tx_rem_n(0) <= NlwRenamedSig_OI_tx_rem_n_bit;
  tx_td(63) <= NlwRenamedSig_OI_tx_td(63);
  tx_td(62) <= NlwRenamedSig_OI_tx_td(62);
  tx_td(61) <= NlwRenamedSig_OI_tx_td(61);
  tx_td(60) <= NlwRenamedSig_OI_tx_td(60);
  tx_td(59) <= NlwRenamedSig_OI_tx_td(59);
  tx_td(58) <= NlwRenamedSig_OI_tx_td(58);
  tx_td(57) <= NlwRenamedSig_OI_tx_td(57);
  tx_td(56) <= NlwRenamedSig_OI_tx_td(56);
  tx_td(55) <= NlwRenamedSig_OI_tx_td(55);
  tx_td(54) <= NlwRenamedSig_OI_tx_td(54);
  tx_td(53) <= NlwRenamedSig_OI_tx_td(53);
  tx_td(52) <= NlwRenamedSig_OI_tx_td(52);
  tx_td(51) <= NlwRenamedSig_OI_tx_td(51);
  tx_td(50) <= NlwRenamedSig_OI_tx_td(50);
  tx_td(49) <= NlwRenamedSig_OI_tx_td(49);
  tx_td(48) <= NlwRenamedSig_OI_tx_td(48);
  tx_td(47) <= NlwRenamedSig_OI_tx_td(47);
  tx_td(46) <= NlwRenamedSig_OI_tx_td(46);
  tx_td(45) <= NlwRenamedSig_OI_tx_td(45);
  tx_td(44) <= NlwRenamedSig_OI_tx_td(44);
  tx_td(43) <= NlwRenamedSig_OI_tx_td(43);
  tx_td(42) <= NlwRenamedSig_OI_tx_td(42);
  tx_td(41) <= NlwRenamedSig_OI_tx_td(41);
  tx_td(40) <= NlwRenamedSig_OI_tx_td(40);
  tx_td(39) <= NlwRenamedSig_OI_tx_td(39);
  tx_td(38) <= NlwRenamedSig_OI_tx_td(38);
  tx_td(37) <= NlwRenamedSig_OI_tx_td(37);
  tx_td(36) <= NlwRenamedSig_OI_tx_td(36);
  tx_td(35) <= NlwRenamedSig_OI_tx_td(35);
  tx_td(34) <= NlwRenamedSig_OI_tx_td(34);
  tx_td(33) <= NlwRenamedSig_OI_tx_td(33);
  tx_td(32) <= NlwRenamedSig_OI_tx_td(32);
  tx_td(31) <= NlwRenamedSig_OI_tx_td(31);
  tx_td(30) <= NlwRenamedSig_OI_tx_td(30);
  tx_td(29) <= NlwRenamedSig_OI_tx_td(29);
  tx_td(28) <= NlwRenamedSig_OI_tx_td(28);
  tx_td(27) <= NlwRenamedSig_OI_tx_td(27);
  tx_td(26) <= NlwRenamedSig_OI_tx_td(26);
  tx_td(25) <= NlwRenamedSig_OI_tx_td(25);
  tx_td(24) <= NlwRenamedSig_OI_tx_td(24);
  tx_td(23) <= NlwRenamedSig_OI_tx_td(23);
  tx_td(22) <= NlwRenamedSig_OI_tx_td(22);
  tx_td(21) <= NlwRenamedSig_OI_tx_td(21);
  tx_td(20) <= NlwRenamedSig_OI_tx_td(20);
  tx_td(19) <= NlwRenamedSig_OI_tx_td(19);
  tx_td(18) <= NlwRenamedSig_OI_tx_td(18);
  tx_td(17) <= NlwRenamedSig_OI_tx_td(17);
  tx_td(16) <= NlwRenamedSig_OI_tx_td(16);
  tx_td(15) <= NlwRenamedSig_OI_tx_td(15);
  tx_td(14) <= NlwRenamedSig_OI_tx_td(14);
  tx_td(13) <= NlwRenamedSig_OI_tx_td(13);
  tx_td(12) <= NlwRenamedSig_OI_tx_td(12);
  tx_td(11) <= NlwRenamedSig_OI_tx_td(11);
  tx_td(10) <= NlwRenamedSig_OI_tx_td(10);
  tx_td(9) <= NlwRenamedSig_OI_tx_td(9);
  tx_td(8) <= NlwRenamedSig_OI_tx_td(8);
  tx_td(7) <= NlwRenamedSig_OI_tx_td(7);
  tx_td(6) <= NlwRenamedSig_OI_tx_td(6);
  tx_td(5) <= NlwRenamedSig_OI_tx_td(5);
  tx_td(4) <= NlwRenamedSig_OI_tx_td(4);
  tx_td(3) <= NlwRenamedSig_OI_tx_td(3);
  tx_td(2) <= NlwRenamedSig_OI_tx_td(2);
  tx_td(1) <= NlwRenamedSig_OI_tx_td(1);
  tx_td(0) <= NlwRenamedSig_OI_tx_td(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_tx_rem_n(4)
    );
  trn_tdst_rdy_n_12099 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => trn_tdst_rdy_n_or0001,
      S => trn_tdst_rdy_n_or0000,
      Q => NlwRenamedSig_OI_trn_tdst_rdy_n
    );
  cfg_tx_dst_rdy_n_12100 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => trn_tdst_rdy_n_or0001,
      S => cfg_tx_dst_rdy_n_or0000_22774,
      Q => NlwRenamedSig_OI_cfg_tx_dst_rdy_n
    );
  usr_in_pkt : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => usr_done,
      D => NlwRenamedSig_OI_tx_rem_n(4),
      R => rst_n_inv,
      S => usr_start,
      Q => usr_in_pkt_23062
    );
  cfg_in_pkt : FDRSE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cfg_done,
      D => NlwRenamedSig_OI_tx_rem_n(4),
      R => rst_n_inv,
      S => cfg_start,
      Q => cfg_in_pkt_22771
    );
  buf_vld : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => buf_vld_not0001,
      D => buf_vld_mux0000,
      R => rst_n_inv,
      Q => buf_vld_22767
    );
  buf_td_0 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(0),
      Q => buf_td(0)
    );
  buf_td_1 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(1),
      Q => buf_td(1)
    );
  buf_td_2 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(2),
      Q => buf_td(2)
    );
  buf_td_3 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(3),
      Q => buf_td(3)
    );
  buf_td_4 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(4),
      Q => buf_td(4)
    );
  buf_td_5 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(5),
      Q => buf_td(5)
    );
  buf_td_6 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(6),
      Q => buf_td(6)
    );
  buf_td_7 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(7),
      Q => buf_td(7)
    );
  buf_td_8 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(8),
      Q => buf_td(8)
    );
  buf_td_9 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(9),
      Q => buf_td(9)
    );
  buf_td_10 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(10),
      Q => buf_td(10)
    );
  buf_td_11 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(11),
      Q => buf_td(11)
    );
  buf_td_12 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(12),
      Q => buf_td(12)
    );
  buf_td_13 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(13),
      Q => buf_td(13)
    );
  buf_td_14 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(14),
      Q => buf_td(14)
    );
  buf_td_15 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(15),
      Q => buf_td(15)
    );
  buf_td_16 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(16),
      Q => buf_td(16)
    );
  buf_td_17 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(17),
      Q => buf_td(17)
    );
  buf_td_18 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(18),
      Q => buf_td(18)
    );
  buf_td_19 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(19),
      Q => buf_td(19)
    );
  buf_td_20 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(20),
      Q => buf_td(20)
    );
  buf_td_21 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(21),
      Q => buf_td(21)
    );
  buf_td_22 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(22),
      Q => buf_td(22)
    );
  buf_td_23 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(23),
      Q => buf_td(23)
    );
  buf_td_24 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(24),
      Q => buf_td(24)
    );
  buf_td_25 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(25),
      Q => buf_td(25)
    );
  buf_td_26 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(26),
      Q => buf_td(26)
    );
  buf_td_27 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(27),
      Q => buf_td(27)
    );
  buf_td_28 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(28),
      Q => buf_td(28)
    );
  buf_td_29 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(29),
      Q => buf_td(29)
    );
  buf_td_30 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(30),
      Q => buf_td(30)
    );
  buf_td_31 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(31),
      Q => buf_td(31)
    );
  buf_td_32 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(32),
      Q => buf_td(32)
    );
  buf_td_33 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(33),
      Q => buf_td(33)
    );
  buf_td_34 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(34),
      Q => buf_td(34)
    );
  buf_td_35 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(35),
      Q => buf_td(35)
    );
  buf_td_36 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(36),
      Q => buf_td(36)
    );
  buf_td_37 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(37),
      Q => buf_td(37)
    );
  buf_td_38 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(38),
      Q => buf_td(38)
    );
  buf_td_39 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(39),
      Q => buf_td(39)
    );
  buf_td_40 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(40),
      Q => buf_td(40)
    );
  buf_td_41 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(41),
      Q => buf_td(41)
    );
  buf_td_42 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(42),
      Q => buf_td(42)
    );
  buf_td_43 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(43),
      Q => buf_td(43)
    );
  buf_td_44 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(44),
      Q => buf_td(44)
    );
  buf_td_45 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(45),
      Q => buf_td(45)
    );
  buf_td_46 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(46),
      Q => buf_td(46)
    );
  buf_td_47 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(47),
      Q => buf_td(47)
    );
  buf_td_48 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(48),
      Q => buf_td(48)
    );
  buf_td_49 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(49),
      Q => buf_td(49)
    );
  buf_td_50 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(50),
      Q => buf_td(50)
    );
  buf_td_51 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(51),
      Q => buf_td(51)
    );
  buf_td_52 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(52),
      Q => buf_td(52)
    );
  buf_td_53 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(53),
      Q => buf_td(53)
    );
  buf_td_54 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(54),
      Q => buf_td(54)
    );
  buf_td_55 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(55),
      Q => buf_td(55)
    );
  buf_td_56 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(56),
      Q => buf_td(56)
    );
  buf_td_57 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(57),
      Q => buf_td(57)
    );
  buf_td_58 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(58),
      Q => buf_td(58)
    );
  buf_td_59 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(59),
      Q => buf_td(59)
    );
  buf_td_60 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(60),
      Q => buf_td(60)
    );
  buf_td_61 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(61),
      Q => buf_td(61)
    );
  buf_td_62 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(62),
      Q => buf_td(62)
    );
  buf_td_63 : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_td_mux0000(63),
      Q => buf_td(63)
    );
  buf_sof_n : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_sof_n_mux0000,
      Q => buf_sof_n_22636
    );
  buf_eof_n : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_eof_n_mux0000,
      Q => buf_eof_n_22632
    );
  buf_rem_n : FDE
    port map (
      C => clk,
      CE => buf_td_not0001,
      D => buf_rem_n_mux0000,
      Q => buf_rem_n_22634
    );
  tx_src_rdy_n_12171 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => tx_src_rdy_n_not0001,
      D => tx_src_rdy_n_mux0000,
      S => rst_n_inv,
      Q => NlwRenamedSig_OI_tx_src_rdy_n
    );
  tx_td_0 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(0),
      Q => NlwRenamedSig_OI_tx_td(0)
    );
  tx_td_1 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(1),
      Q => NlwRenamedSig_OI_tx_td(1)
    );
  tx_td_2 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(2),
      Q => NlwRenamedSig_OI_tx_td(2)
    );
  tx_td_3 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(3),
      Q => NlwRenamedSig_OI_tx_td(3)
    );
  tx_td_4 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(4),
      Q => NlwRenamedSig_OI_tx_td(4)
    );
  tx_td_5 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(5),
      Q => NlwRenamedSig_OI_tx_td(5)
    );
  tx_td_6 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(6),
      Q => NlwRenamedSig_OI_tx_td(6)
    );
  tx_td_7 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(7),
      Q => NlwRenamedSig_OI_tx_td(7)
    );
  tx_td_8 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(8),
      Q => NlwRenamedSig_OI_tx_td(8)
    );
  tx_td_9 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(9),
      Q => NlwRenamedSig_OI_tx_td(9)
    );
  tx_td_10 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(10),
      Q => NlwRenamedSig_OI_tx_td(10)
    );
  tx_td_11 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(11),
      Q => NlwRenamedSig_OI_tx_td(11)
    );
  tx_td_12 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(12),
      Q => NlwRenamedSig_OI_tx_td(12)
    );
  tx_td_13 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(13),
      Q => NlwRenamedSig_OI_tx_td(13)
    );
  tx_td_14 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(14),
      Q => NlwRenamedSig_OI_tx_td(14)
    );
  tx_td_15 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(15),
      Q => NlwRenamedSig_OI_tx_td(15)
    );
  tx_td_16 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(16),
      Q => NlwRenamedSig_OI_tx_td(16)
    );
  tx_td_17 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(17),
      Q => NlwRenamedSig_OI_tx_td(17)
    );
  tx_td_18 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(18),
      Q => NlwRenamedSig_OI_tx_td(18)
    );
  tx_td_19 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(19),
      Q => NlwRenamedSig_OI_tx_td(19)
    );
  tx_td_20 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(20),
      Q => NlwRenamedSig_OI_tx_td(20)
    );
  tx_td_21 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(21),
      Q => NlwRenamedSig_OI_tx_td(21)
    );
  tx_td_22 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(22),
      Q => NlwRenamedSig_OI_tx_td(22)
    );
  tx_td_23 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(23),
      Q => NlwRenamedSig_OI_tx_td(23)
    );
  tx_td_24 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(24),
      Q => NlwRenamedSig_OI_tx_td(24)
    );
  tx_td_25 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(25),
      Q => NlwRenamedSig_OI_tx_td(25)
    );
  tx_td_26 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(26),
      Q => NlwRenamedSig_OI_tx_td(26)
    );
  tx_td_27 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(27),
      Q => NlwRenamedSig_OI_tx_td(27)
    );
  tx_td_28 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(28),
      Q => NlwRenamedSig_OI_tx_td(28)
    );
  tx_td_29 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(29),
      Q => NlwRenamedSig_OI_tx_td(29)
    );
  tx_td_30 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(30),
      Q => NlwRenamedSig_OI_tx_td(30)
    );
  tx_td_31 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(31),
      Q => NlwRenamedSig_OI_tx_td(31)
    );
  tx_td_32 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(32),
      Q => NlwRenamedSig_OI_tx_td(32)
    );
  tx_td_33 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(33),
      Q => NlwRenamedSig_OI_tx_td(33)
    );
  tx_td_34 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(34),
      Q => NlwRenamedSig_OI_tx_td(34)
    );
  tx_td_35 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(35),
      Q => NlwRenamedSig_OI_tx_td(35)
    );
  tx_td_36 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(36),
      Q => NlwRenamedSig_OI_tx_td(36)
    );
  tx_td_37 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(37),
      Q => NlwRenamedSig_OI_tx_td(37)
    );
  tx_td_38 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(38),
      Q => NlwRenamedSig_OI_tx_td(38)
    );
  tx_td_39 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(39),
      Q => NlwRenamedSig_OI_tx_td(39)
    );
  tx_td_40 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(40),
      Q => NlwRenamedSig_OI_tx_td(40)
    );
  tx_td_41 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(41),
      Q => NlwRenamedSig_OI_tx_td(41)
    );
  tx_td_42 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(42),
      Q => NlwRenamedSig_OI_tx_td(42)
    );
  tx_td_43 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(43),
      Q => NlwRenamedSig_OI_tx_td(43)
    );
  tx_td_44 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(44),
      Q => NlwRenamedSig_OI_tx_td(44)
    );
  tx_td_45 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(45),
      Q => NlwRenamedSig_OI_tx_td(45)
    );
  tx_td_46 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(46),
      Q => NlwRenamedSig_OI_tx_td(46)
    );
  tx_td_47 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(47),
      Q => NlwRenamedSig_OI_tx_td(47)
    );
  tx_td_48 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(48),
      Q => NlwRenamedSig_OI_tx_td(48)
    );
  tx_td_49 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(49),
      Q => NlwRenamedSig_OI_tx_td(49)
    );
  tx_td_50 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(50),
      Q => NlwRenamedSig_OI_tx_td(50)
    );
  tx_td_51 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(51),
      Q => NlwRenamedSig_OI_tx_td(51)
    );
  tx_td_52 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(52),
      Q => NlwRenamedSig_OI_tx_td(52)
    );
  tx_td_53 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(53),
      Q => NlwRenamedSig_OI_tx_td(53)
    );
  tx_td_54 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(54),
      Q => NlwRenamedSig_OI_tx_td(54)
    );
  tx_td_55 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(55),
      Q => NlwRenamedSig_OI_tx_td(55)
    );
  tx_td_56 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(56),
      Q => NlwRenamedSig_OI_tx_td(56)
    );
  tx_td_57 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(57),
      Q => NlwRenamedSig_OI_tx_td(57)
    );
  tx_td_58 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(58),
      Q => NlwRenamedSig_OI_tx_td(58)
    );
  tx_td_59 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(59),
      Q => NlwRenamedSig_OI_tx_td(59)
    );
  tx_td_60 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(60),
      Q => NlwRenamedSig_OI_tx_td(60)
    );
  tx_td_61 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(61),
      Q => NlwRenamedSig_OI_tx_td(61)
    );
  tx_td_62 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(62),
      Q => NlwRenamedSig_OI_tx_td(62)
    );
  tx_td_63 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_td_mux0000(63),
      Q => NlwRenamedSig_OI_tx_td(63)
    );
  tx_sof_n_12236 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_sof_n_mux0000_22926,
      Q => NlwRenamedSig_OI_tx_sof_n
    );
  tx_eof_n_12237 : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_eof_n_mux0000_22921,
      Q => NlwRenamedSig_OI_tx_eof_n
    );
  tx_src_dsc_n_12238 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => rst_n,
      D => tx_src_dsc_n_mux0000_22928,
      Q => NlwRenamedSig_OI_tx_src_dsc_n
    );
  tx_rem_n_bit : FDE
    port map (
      C => clk,
      CE => rst_n,
      D => tx_rem_n_bit_mux0000_22924,
      Q => NlwRenamedSig_OI_tx_rem_n_bit
    );
  tx_td_cmp_eq0001111 : LUT3
    generic map(
      INIT => X"F1"
    )
    port map (
      I0 => buf_vld_22767,
      I1 => tx_dst_rdy_n,
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      O => N8
    );
  tx_td_or000031 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => buf_vld_22767,
      I1 => NlwRenamedSig_OI_tx_src_rdy_n,
      I2 => tx_dst_rdy_n,
      O => N9
    );
  buf_vld_mux00001 : LUT6
    generic map(
      INIT => X"2220222202000202"
    )
    port map (
      I0 => tx_dst_rdy_n,
      I1 => NlwRenamedSig_OI_tx_src_rdy_n,
      I2 => N7,
      I3 => usr_in_pkt_23062,
      I4 => trn_tsof_n,
      I5 => N12,
      O => buf_vld_mux0000
    );
  tx_td_or000041 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => cfg_tx_src_rdy_n,
      I1 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      O => N12
    );
  tx_td_or000021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      O => N7
    );
  tx_eof_n_mux0000_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => trn_tsrc_rdy_n,
      I1 => trn_teof_n,
      I2 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I3 => cfg_tx_src_rdy_n,
      I4 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I5 => cfg_tx_eof_n,
      O => N208
    );
  tx_eof_n_mux0000 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N208,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_eof_n,
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_eof_n_22632,
      O => tx_eof_n_mux0000_22921
    );
  tx_td_mux0000_9_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N210,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(9),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(9),
      O => tx_td_mux0000(9)
    );
  tx_td_mux0000_8_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N212,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(8),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(8),
      O => tx_td_mux0000(8)
    );
  tx_td_mux0000_7_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N214,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(7),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(7),
      O => tx_td_mux0000(7)
    );
  tx_td_mux0000_6_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N216,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(6),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(6),
      O => tx_td_mux0000(6)
    );
  tx_td_mux0000_63_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N218,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(63),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(63),
      O => tx_td_mux0000(63)
    );
  tx_td_mux0000_62_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N220,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(62),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(62),
      O => tx_td_mux0000(62)
    );
  tx_td_mux0000_61_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N222,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(61),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(61),
      O => tx_td_mux0000(61)
    );
  tx_td_mux0000_60_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N224,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(60),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(60),
      O => tx_td_mux0000(60)
    );
  tx_td_mux0000_5_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N226,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(5),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(5),
      O => tx_td_mux0000(5)
    );
  tx_td_mux0000_59_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N228,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(59),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(59),
      O => tx_td_mux0000(59)
    );
  tx_td_mux0000_58_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N230,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(58),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(58),
      O => tx_td_mux0000(58)
    );
  tx_td_mux0000_57_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N232,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(57),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(57),
      O => tx_td_mux0000(57)
    );
  tx_td_mux0000_56_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N234,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(56),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(56),
      O => tx_td_mux0000(56)
    );
  tx_td_mux0000_55_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N236,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(55),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(55),
      O => tx_td_mux0000(55)
    );
  tx_td_mux0000_54_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N238,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(54),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(54),
      O => tx_td_mux0000(54)
    );
  tx_td_mux0000_53_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N240,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(53),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(53),
      O => tx_td_mux0000(53)
    );
  tx_td_mux0000_52_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N242,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(52),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(52),
      O => tx_td_mux0000(52)
    );
  tx_td_mux0000_51_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N244,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(51),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(51),
      O => tx_td_mux0000(51)
    );
  tx_td_mux0000_50_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N246,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(50),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(50),
      O => tx_td_mux0000(50)
    );
  tx_td_mux0000_4_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N248,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(4),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(4),
      O => tx_td_mux0000(4)
    );
  tx_td_mux0000_49_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N250,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(49),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(49),
      O => tx_td_mux0000(49)
    );
  tx_td_mux0000_48_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N252,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(48),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(48),
      O => tx_td_mux0000(48)
    );
  tx_td_mux0000_47_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N254,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(47),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(47),
      O => tx_td_mux0000(47)
    );
  tx_td_mux0000_46_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N256,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(46),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(46),
      O => tx_td_mux0000(46)
    );
  tx_td_mux0000_45_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N258,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(45),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(45),
      O => tx_td_mux0000(45)
    );
  tx_td_mux0000_44_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N260,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(44),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(44),
      O => tx_td_mux0000(44)
    );
  tx_td_mux0000_43_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N262,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(43),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(43),
      O => tx_td_mux0000(43)
    );
  tx_td_mux0000_42_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N264,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(42),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(42),
      O => tx_td_mux0000(42)
    );
  tx_td_mux0000_41_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N266,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(41),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(41),
      O => tx_td_mux0000(41)
    );
  tx_td_mux0000_40_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N268,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(40),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(40),
      O => tx_td_mux0000(40)
    );
  tx_td_mux0000_3_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N270,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(3),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(3),
      O => tx_td_mux0000(3)
    );
  tx_td_mux0000_39_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N272,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(39),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(39),
      O => tx_td_mux0000(39)
    );
  tx_td_mux0000_38_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N274,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(38),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(38),
      O => tx_td_mux0000(38)
    );
  tx_td_mux0000_37_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N276,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(37),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(37),
      O => tx_td_mux0000(37)
    );
  tx_td_mux0000_36_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N278,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(36),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(36),
      O => tx_td_mux0000(36)
    );
  tx_td_mux0000_35_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N280,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(35),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(35),
      O => tx_td_mux0000(35)
    );
  tx_td_mux0000_34_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N282,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(34),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(34),
      O => tx_td_mux0000(34)
    );
  tx_td_mux0000_33_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N284,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(33),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(33),
      O => tx_td_mux0000(33)
    );
  tx_td_mux0000_32_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N286,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(32),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(32),
      O => tx_td_mux0000(32)
    );
  tx_td_mux0000_31_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N288,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(31),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(31),
      O => tx_td_mux0000(31)
    );
  tx_td_mux0000_30_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N290,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(30),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(30),
      O => tx_td_mux0000(30)
    );
  tx_td_mux0000_2_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N292,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(2),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(2),
      O => tx_td_mux0000(2)
    );
  tx_td_mux0000_29_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N294,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(29),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(29),
      O => tx_td_mux0000(29)
    );
  tx_td_mux0000_28_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N296,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(28),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(28),
      O => tx_td_mux0000(28)
    );
  tx_td_mux0000_27_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N298,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(27),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(27),
      O => tx_td_mux0000(27)
    );
  tx_td_mux0000_26_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N300,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(26),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(26),
      O => tx_td_mux0000(26)
    );
  tx_td_mux0000_25_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N302,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(25),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(25),
      O => tx_td_mux0000(25)
    );
  tx_td_mux0000_24_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N304,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(24),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(24),
      O => tx_td_mux0000(24)
    );
  tx_td_mux0000_23_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N306,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(23),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(23),
      O => tx_td_mux0000(23)
    );
  tx_td_mux0000_22_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N308,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(22),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(22),
      O => tx_td_mux0000(22)
    );
  tx_td_mux0000_21_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N310,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(21),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(21),
      O => tx_td_mux0000(21)
    );
  tx_td_mux0000_20_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N312,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(20),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(20),
      O => tx_td_mux0000(20)
    );
  tx_td_mux0000_1_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N314,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(1),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(1),
      O => tx_td_mux0000(1)
    );
  tx_td_mux0000_19_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N316,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(19),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(19),
      O => tx_td_mux0000(19)
    );
  tx_td_mux0000_18_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N318,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(18),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(18),
      O => tx_td_mux0000(18)
    );
  tx_td_mux0000_17_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N320,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(17),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(17),
      O => tx_td_mux0000(17)
    );
  tx_td_mux0000_16_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N322,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(16),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(16),
      O => tx_td_mux0000(16)
    );
  tx_td_mux0000_15_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N324,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(15),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(15),
      O => tx_td_mux0000(15)
    );
  tx_td_mux0000_14_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N326,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(14),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(14),
      O => tx_td_mux0000(14)
    );
  tx_td_mux0000_13_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N328,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(13),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(13),
      O => tx_td_mux0000(13)
    );
  tx_td_mux0000_12_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N330,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(12),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(12),
      O => tx_td_mux0000(12)
    );
  tx_td_mux0000_11_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N332,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(11),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(11),
      O => tx_td_mux0000(11)
    );
  tx_td_mux0000_10_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N334,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(10),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(10),
      O => tx_td_mux0000(10)
    );
  tx_td_mux0000_0_Q : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N336,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_td(0),
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_td(0),
      O => tx_td_mux0000(0)
    );
  tx_sof_n_mux0000 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N338,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_sof_n,
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_sof_n_22636,
      O => tx_sof_n_mux0000_22926
    );
  tx_rem_n_bit_mux0000 : LUT6
    generic map(
      INIT => X"FFFF88F888F888F8"
    )
    port map (
      I0 => N340,
      I1 => N8,
      I2 => NlwRenamedSig_OI_tx_rem_n_bit,
      I3 => tx_td_or0000,
      I4 => N9,
      I5 => buf_rem_n_22634,
      O => tx_rem_n_bit_mux0000_22924
    );
  tx_td_or00001 : LUT6
    generic map(
      INIT => X"2228777D2228333C"
    )
    port map (
      I0 => NlwRenamedSig_OI_tx_src_rdy_n,
      I1 => N7,
      I2 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I3 => cfg_tx_src_rdy_n,
      I4 => tx_dst_rdy_n,
      I5 => buf_vld_22767,
      O => tx_td_or0000
    );
  cfg_tx_dst_rdy_n_or0000_SW0 : LUT5
    generic map(
      INIT => X"55545F5F"
    )
    port map (
      I0 => usr_in_pkt_23062,
      I1 => trn_tsrc_rdy_n,
      I2 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I3 => trn_tsof_n,
      I4 => trn_teof_n,
      O => N205
    );
  cfg_done1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => cfg_tx_eof_n,
      I1 => cfg_tx_src_rdy_n,
      I2 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      O => cfg_done
    );
  tx_src_rdy_n_mux00001 : LUT6
    generic map(
      INIT => X"3333222200300020"
    )
    port map (
      I0 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I1 => N9,
      I2 => trn_tsof_n,
      I3 => usr_in_pkt_23062,
      I4 => cfg_tx_src_rdy_n,
      I5 => N7,
      O => tx_src_rdy_n_mux0000
    );
  trn_tdst_rdy_n_or00011 : LUT6
    generic map(
      INIT => X"CAC8CAC8CAC8CACA"
    )
    port map (
      I0 => tx_dst_rdy_n,
      I1 => buf_vld_22767,
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => N12,
      I4 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I5 => trn_tsrc_rdy_n,
      O => trn_tdst_rdy_n_or0001
    );
  cfg_start1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => cfg_tx_sof_n,
      I1 => cfg_tx_src_rdy_n,
      I2 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      O => cfg_start
    );
  usr_done1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      I2 => trn_teof_n,
      O => usr_done
    );
  buf_td_not00011 : LUT6
    generic map(
      INIT => X"2000200020002020"
    )
    port map (
      I0 => rst_n,
      I1 => NlwRenamedSig_OI_tx_src_rdy_n,
      I2 => tx_dst_rdy_n,
      I3 => N12,
      I4 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I5 => trn_tsrc_rdy_n,
      O => buf_td_not0001
    );
  usr_start1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      I2 => trn_tsof_n,
      O => usr_start
    );
  tx_src_dsc_n_mux0000_SW0 : LUT5
    generic map(
      INIT => X"02FF0202"
    )
    port map (
      I0 => buf_vld_22767,
      I1 => NlwRenamedSig_OI_tx_src_rdy_n,
      I2 => tx_dst_rdy_n,
      I3 => tx_td_or0000,
      I4 => NlwRenamedSig_OI_tx_src_dsc_n,
      O => N0
    );
  cfg_tx_dst_rdy_n_or0000 : LUT6
    generic map(
      INIT => X"33332301FFFFFFFF"
    )
    port map (
      I0 => trn_tsrc_rdy_n,
      I1 => cfg_in_pkt_22771,
      I2 => N205,
      I3 => usr_in_pkt_23062,
      I4 => cfg_tx_src_rdy_n,
      I5 => rst_n,
      O => cfg_tx_dst_rdy_n_or0000_22774
    );
  buf_td_mux0000_9_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(9),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(9),
      O => buf_td_mux0000(9)
    );
  buf_td_mux0000_8_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(8),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(8),
      O => buf_td_mux0000(8)
    );
  buf_td_mux0000_7_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(7),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(7),
      O => buf_td_mux0000(7)
    );
  buf_td_mux0000_6_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(6),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(6),
      O => buf_td_mux0000(6)
    );
  buf_td_mux0000_63_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(63),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(63),
      O => buf_td_mux0000(63)
    );
  buf_td_mux0000_62_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(62),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(62),
      O => buf_td_mux0000(62)
    );
  buf_td_mux0000_61_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(61),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(61),
      O => buf_td_mux0000(61)
    );
  buf_td_mux0000_60_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(60),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(60),
      O => buf_td_mux0000(60)
    );
  buf_td_mux0000_5_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(5),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(5),
      O => buf_td_mux0000(5)
    );
  buf_td_mux0000_59_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(59),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(59),
      O => buf_td_mux0000(59)
    );
  buf_td_mux0000_58_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(58),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(58),
      O => buf_td_mux0000(58)
    );
  buf_td_mux0000_57_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(57),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(57),
      O => buf_td_mux0000(57)
    );
  buf_td_mux0000_56_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(56),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(56),
      O => buf_td_mux0000(56)
    );
  buf_td_mux0000_55_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(55),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(55),
      O => buf_td_mux0000(55)
    );
  buf_td_mux0000_54_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(54),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(54),
      O => buf_td_mux0000(54)
    );
  buf_td_mux0000_53_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(53),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(53),
      O => buf_td_mux0000(53)
    );
  buf_td_mux0000_52_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(52),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(52),
      O => buf_td_mux0000(52)
    );
  buf_td_mux0000_51_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(51),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(51),
      O => buf_td_mux0000(51)
    );
  buf_td_mux0000_50_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(50),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(50),
      O => buf_td_mux0000(50)
    );
  buf_td_mux0000_4_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(4),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(4),
      O => buf_td_mux0000(4)
    );
  buf_td_mux0000_49_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(49),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(49),
      O => buf_td_mux0000(49)
    );
  buf_td_mux0000_48_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(48),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(48),
      O => buf_td_mux0000(48)
    );
  buf_td_mux0000_47_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(47),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(47),
      O => buf_td_mux0000(47)
    );
  buf_td_mux0000_46_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(46),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(46),
      O => buf_td_mux0000(46)
    );
  buf_td_mux0000_45_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(45),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(45),
      O => buf_td_mux0000(45)
    );
  buf_td_mux0000_44_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(44),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(44),
      O => buf_td_mux0000(44)
    );
  buf_td_mux0000_43_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(43),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(43),
      O => buf_td_mux0000(43)
    );
  buf_td_mux0000_42_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(42),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(42),
      O => buf_td_mux0000(42)
    );
  buf_td_mux0000_41_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(41),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(41),
      O => buf_td_mux0000(41)
    );
  buf_td_mux0000_40_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(40),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(40),
      O => buf_td_mux0000(40)
    );
  buf_td_mux0000_3_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(3),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(3),
      O => buf_td_mux0000(3)
    );
  buf_td_mux0000_39_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(39),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(39),
      O => buf_td_mux0000(39)
    );
  buf_td_mux0000_38_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(38),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(38),
      O => buf_td_mux0000(38)
    );
  buf_td_mux0000_37_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(37),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(37),
      O => buf_td_mux0000(37)
    );
  buf_td_mux0000_36_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(36),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(36),
      O => buf_td_mux0000(36)
    );
  buf_td_mux0000_35_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(35),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(35),
      O => buf_td_mux0000(35)
    );
  buf_td_mux0000_34_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(34),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(34),
      O => buf_td_mux0000(34)
    );
  buf_td_mux0000_33_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(33),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(33),
      O => buf_td_mux0000(33)
    );
  buf_td_mux0000_32_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(32),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(32),
      O => buf_td_mux0000(32)
    );
  buf_td_mux0000_31_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(31),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(31),
      O => buf_td_mux0000(31)
    );
  buf_td_mux0000_30_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(30),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(30),
      O => buf_td_mux0000(30)
    );
  buf_td_mux0000_2_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(2),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(2),
      O => buf_td_mux0000(2)
    );
  buf_td_mux0000_29_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(29),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(29),
      O => buf_td_mux0000(29)
    );
  buf_td_mux0000_28_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(28),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(28),
      O => buf_td_mux0000(28)
    );
  buf_td_mux0000_27_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(27),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(27),
      O => buf_td_mux0000(27)
    );
  buf_td_mux0000_26_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(26),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(26),
      O => buf_td_mux0000(26)
    );
  buf_td_mux0000_25_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(25),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(25),
      O => buf_td_mux0000(25)
    );
  buf_td_mux0000_24_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(24),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(24),
      O => buf_td_mux0000(24)
    );
  buf_td_mux0000_23_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(23),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(23),
      O => buf_td_mux0000(23)
    );
  buf_td_mux0000_22_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(22),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(22),
      O => buf_td_mux0000(22)
    );
  buf_td_mux0000_21_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(21),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(21),
      O => buf_td_mux0000(21)
    );
  buf_td_mux0000_20_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(20),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(20),
      O => buf_td_mux0000(20)
    );
  buf_td_mux0000_1_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(1),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(1),
      O => buf_td_mux0000(1)
    );
  buf_td_mux0000_19_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(19),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(19),
      O => buf_td_mux0000(19)
    );
  buf_td_mux0000_18_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(18),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(18),
      O => buf_td_mux0000(18)
    );
  buf_td_mux0000_17_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(17),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(17),
      O => buf_td_mux0000(17)
    );
  buf_td_mux0000_16_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(16),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(16),
      O => buf_td_mux0000(16)
    );
  buf_td_mux0000_15_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(15),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(15),
      O => buf_td_mux0000(15)
    );
  buf_td_mux0000_14_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(14),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(14),
      O => buf_td_mux0000(14)
    );
  buf_td_mux0000_13_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(13),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(13),
      O => buf_td_mux0000(13)
    );
  buf_td_mux0000_12_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(12),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(12),
      O => buf_td_mux0000(12)
    );
  buf_td_mux0000_11_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(11),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(11),
      O => buf_td_mux0000(11)
    );
  buf_td_mux0000_10_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(10),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(10),
      O => buf_td_mux0000(10)
    );
  buf_td_mux0000_0_1 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_td(0),
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_td(0),
      O => buf_td_mux0000(0)
    );
  buf_sof_n_mux00001 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_sof_n,
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_tsof_n,
      O => buf_sof_n_mux0000
    );
  buf_rem_n_mux00001 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_rem_n,
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_trem_n(0),
      O => buf_rem_n_mux0000
    );
  buf_eof_n_mux00001 : LUT6
    generic map(
      INIT => X"CCCCCDCCCCCCC8CC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => cfg_tx_eof_n,
      I2 => NlwRenamedSig_OI_tx_src_rdy_n,
      I3 => tx_dst_rdy_n,
      I4 => trn_tsrc_rdy_n,
      I5 => trn_teof_n,
      O => buf_eof_n_mux0000
    );
  tx_src_rdy_n_not00011 : LUT6
    generic map(
      INIT => X"FFFF1011FFFFFFFF"
    )
    port map (
      I0 => trn_tsrc_rdy_n,
      I1 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I2 => usr_in_pkt_23062,
      I3 => trn_tsof_n,
      I4 => N12,
      I5 => tx_dst_rdy_n,
      O => tx_src_rdy_n_not0001
    );
  buf_vld_not00011 : LUT6
    generic map(
      INIT => X"3333222211130002"
    )
    port map (
      I0 => tx_dst_rdy_n,
      I1 => NlwRenamedSig_OI_tx_src_rdy_n,
      I2 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I3 => trn_tsrc_rdy_n,
      I4 => buf_vld_22767,
      I5 => N12,
      O => buf_vld_not0001
    );
  tx_src_dsc_n_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFF101010E0"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsrc_rdy_n,
      I2 => N8,
      I3 => cfg_tx_src_rdy_n,
      I4 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I5 => N0,
      O => tx_src_dsc_n_mux0000_22928
    );
  tx_td_mux0000_9_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(9),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(9),
      O => N210
    );
  tx_td_mux0000_8_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(8),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(8),
      O => N212
    );
  tx_td_mux0000_7_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(7),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(7),
      O => N214
    );
  tx_td_mux0000_6_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(6),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(6),
      O => N216
    );
  tx_td_mux0000_63_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(63),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(63),
      O => N218
    );
  tx_td_mux0000_62_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(62),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(62),
      O => N220
    );
  tx_td_mux0000_61_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(61),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(61),
      O => N222
    );
  tx_td_mux0000_60_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(60),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(60),
      O => N224
    );
  tx_td_mux0000_5_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(5),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(5),
      O => N226
    );
  tx_td_mux0000_59_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(59),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(59),
      O => N228
    );
  tx_td_mux0000_58_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(58),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(58),
      O => N230
    );
  tx_td_mux0000_57_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(57),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(57),
      O => N232
    );
  tx_td_mux0000_56_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(56),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(56),
      O => N234
    );
  tx_td_mux0000_55_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(55),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(55),
      O => N236
    );
  tx_td_mux0000_54_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(54),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(54),
      O => N238
    );
  tx_td_mux0000_53_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(53),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(53),
      O => N240
    );
  tx_td_mux0000_52_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(52),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(52),
      O => N242
    );
  tx_td_mux0000_51_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(51),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(51),
      O => N244
    );
  tx_td_mux0000_50_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(50),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(50),
      O => N246
    );
  tx_td_mux0000_4_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(4),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(4),
      O => N248
    );
  tx_td_mux0000_49_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(49),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(49),
      O => N250
    );
  tx_td_mux0000_48_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(48),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(48),
      O => N252
    );
  tx_td_mux0000_47_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(47),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(47),
      O => N254
    );
  tx_td_mux0000_46_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(46),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(46),
      O => N256
    );
  tx_td_mux0000_45_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(45),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(45),
      O => N258
    );
  tx_td_mux0000_44_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(44),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(44),
      O => N260
    );
  tx_td_mux0000_43_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(43),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(43),
      O => N262
    );
  tx_td_mux0000_42_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(42),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(42),
      O => N264
    );
  tx_td_mux0000_41_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(41),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(41),
      O => N266
    );
  tx_td_mux0000_40_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(40),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(40),
      O => N268
    );
  tx_td_mux0000_3_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(3),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(3),
      O => N270
    );
  tx_td_mux0000_39_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(39),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(39),
      O => N272
    );
  tx_td_mux0000_38_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(38),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(38),
      O => N274
    );
  tx_td_mux0000_37_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(37),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(37),
      O => N276
    );
  tx_td_mux0000_36_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(36),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(36),
      O => N278
    );
  tx_td_mux0000_35_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(35),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(35),
      O => N280
    );
  tx_td_mux0000_34_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(34),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(34),
      O => N282
    );
  tx_td_mux0000_33_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(33),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(33),
      O => N284
    );
  tx_td_mux0000_32_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(32),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(32),
      O => N286
    );
  tx_td_mux0000_31_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(31),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(31),
      O => N288
    );
  tx_td_mux0000_30_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(30),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(30),
      O => N290
    );
  tx_td_mux0000_2_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(2),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(2),
      O => N292
    );
  tx_td_mux0000_29_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(29),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(29),
      O => N294
    );
  tx_td_mux0000_28_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(28),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(28),
      O => N296
    );
  tx_td_mux0000_27_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(27),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(27),
      O => N298
    );
  tx_td_mux0000_26_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(26),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(26),
      O => N300
    );
  tx_td_mux0000_25_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(25),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(25),
      O => N302
    );
  tx_td_mux0000_24_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(24),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(24),
      O => N304
    );
  tx_td_mux0000_23_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(23),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(23),
      O => N306
    );
  tx_td_mux0000_22_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(22),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(22),
      O => N308
    );
  tx_td_mux0000_21_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(21),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(21),
      O => N310
    );
  tx_td_mux0000_20_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(20),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(20),
      O => N312
    );
  tx_td_mux0000_1_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(1),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(1),
      O => N314
    );
  tx_td_mux0000_19_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(19),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(19),
      O => N316
    );
  tx_td_mux0000_18_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(18),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(18),
      O => N318
    );
  tx_td_mux0000_17_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(17),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(17),
      O => N320
    );
  tx_td_mux0000_16_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(16),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(16),
      O => N322
    );
  tx_td_mux0000_15_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(15),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(15),
      O => N324
    );
  tx_td_mux0000_14_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(14),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(14),
      O => N326
    );
  tx_td_mux0000_13_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(13),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(13),
      O => N328
    );
  tx_td_mux0000_12_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(12),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(12),
      O => N330
    );
  tx_td_mux0000_11_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(11),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(11),
      O => N332
    );
  tx_td_mux0000_10_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(10),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(10),
      O => N334
    );
  tx_td_mux0000_0_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_td(0),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_td(0),
      O => N336
    );
  tx_sof_n_mux0000_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_tsof_n,
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_sof_n,
      O => N338
    );
  tx_rem_n_bit_mux0000_SW2 : LUT6
    generic map(
      INIT => X"040404FA04040400"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_tdst_rdy_n,
      I1 => trn_trem_n(0),
      I2 => trn_tsrc_rdy_n,
      I3 => NlwRenamedSig_OI_cfg_tx_dst_rdy_n,
      I4 => cfg_tx_src_rdy_n,
      I5 => cfg_tx_rem_n,
      O => N340
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  trn_tdst_rdy_n_or00001 : LUT5
    generic map(
      INIT => X"FFFF01FF"
    )
    port map (
      I0 => N7,
      I1 => cfg_tx_src_rdy_n,
      I2 => trn_teof_n,
      I3 => rst_n,
      I4 => cfg_in_pkt_22771,
      O => trn_tdst_rdy_n_or00001_22912
    );
  trn_tdst_rdy_n_or00002 : LUT6
    generic map(
      INIT => X"FFFF55FFFFFF45FF"
    )
    port map (
      I0 => cfg_tx_src_rdy_n,
      I1 => trn_tsof_n,
      I2 => trn_teof_n,
      I3 => rst_n,
      I4 => cfg_in_pkt_22771,
      I5 => N7,
      O => trn_tdst_rdy_n_or00002_22913
    );
  trn_tdst_rdy_n_or0000_f7 : MUXF7
    port map (
      I0 => trn_tdst_rdy_n_or00002_22913,
      I1 => trn_tdst_rdy_n_or00001_22912,
      S => usr_in_pkt_23062,
      O => trn_tdst_rdy_n_or0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_plus_ll_tx is
  port (
    clear_cpl_count : out STD_LOGIC; 
    llk_tx_src_rdy_n : out STD_LOGIC; 
    trn_terrfwd_n : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_tx_dst_rdy_n : out STD_LOGIC; 
    cfg_tx_eof_n : in STD_LOGIC := 'X'; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    trn_pfc_cplh_cl_upd : in STD_LOGIC := 'X'; 
    llk_tx_sop_n : out STD_LOGIC; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    cfg_tx_sof_n : in STD_LOGIC := 'X'; 
    llk_tx_src_dsc_n : out STD_LOGIC; 
    tx_err_wr_ep_n : out STD_LOGIC; 
    llk_tx_eof_n : out STD_LOGIC; 
    llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    npd_credit_limited : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    cfg_tx_rem_n : in STD_LOGIC := 'X'; 
    pd_credit_limited : in STD_LOGIC := 'X'; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    llk_tx_eop_n : out STD_LOGIC; 
    cd_credit_limited : in STD_LOGIC := 'X'; 
    llk_tx_sof_n : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    tx_pd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_cplh_cl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_npd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    tx_ch_credits_consumed : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_cd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_npd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_cd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_pd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end pcie_blk_plus_ll_tx;

architecture STRUCTURE of pcie_blk_plus_ll_tx is
  component pcie_blk_ll_tx_arb
    port (
      tx_src_rdy_n : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      tx_sof_n : out STD_LOGIC; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_tx_dst_rdy_n : out STD_LOGIC; 
      cfg_tx_eof_n : in STD_LOGIC := 'X'; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
      cfg_tx_sof_n : in STD_LOGIC := 'X'; 
      tx_src_dsc_n : out STD_LOGIC; 
      tx_dst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      cfg_tx_rem_n : in STD_LOGIC := 'X'; 
      tx_eof_n : out STD_LOGIC; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      tx_rem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  component pcie_blk_ll_tx
    port (
      clear_cpl_count : out STD_LOGIC; 
      llk_tx_src_rdy_n : out STD_LOGIC; 
      trn_terrfwd_n : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      trn_pfc_cplh_cl_upd : in STD_LOGIC := 'X'; 
      llk_tx_sop_n : out STD_LOGIC; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      llk_tx_src_dsc_n : out STD_LOGIC; 
      llk_tx_eof_n : out STD_LOGIC; 
      llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tbuf_av_cpl : out STD_LOGIC; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      npd_credit_limited : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      pd_credit_limited : in STD_LOGIC := 'X'; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      llk_tx_eop_n : out STD_LOGIC; 
      cd_credit_limited : in STD_LOGIC := 'X'; 
      llk_tx_sof_n : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      tx_pd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_cplh_cl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_npd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_ch_credits_consumed : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_cd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_npd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_cd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_pd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  signal N01 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal trn_tbuf_av_int_0_and0000_23959 : STD_LOGIC; 
  signal trn_tbuf_av_int_1_and0000_23961 : STD_LOGIC; 
  signal trn_tbuf_av_int_2_and0000_23963 : STD_LOGIC; 
  signal tx_dst_rdy_n : STD_LOGIC; 
  signal tx_eof_n : STD_LOGIC; 
  signal tx_err_wr_ep_n_not0001 : STD_LOGIC; 
  signal tx_sof_n : STD_LOGIC; 
  signal tx_src_dsc_n : STD_LOGIC; 
  signal tx_src_rdy_n : STD_LOGIC; 
  signal NLW_tx_bridge_trn_terrfwd_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_tx_bridge_trn_tdst_dsc_n_UNCONNECTED : STD_LOGIC; 
  signal trn_tbuf_av_int : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal tx_rem_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal tx_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  trn_tbuf_av(2) <= trn_tbuf_av_int(2);
  trn_tbuf_av(1) <= trn_tbuf_av_int(1);
  trn_tbuf_av(0) <= trn_tbuf_av_int(0);
  tx_err_wr_ep_n_12093 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => tx_err_wr_ep_n_not0001,
      Q => tx_err_wr_ep_n
    );
  trn_tbuf_av_int_0 : FDR
    port map (
      C => clk,
      D => trn_tbuf_av_int_0_and0000_23959,
      R => rst_n_inv,
      Q => trn_tbuf_av_int(0)
    );
  trn_tbuf_av_int_2 : FDR
    port map (
      C => clk,
      D => trn_tbuf_av_int_2_and0000_23963,
      R => rst_n_inv,
      Q => trn_tbuf_av_int(2)
    );
  trn_tbuf_av_int_1 : FDR
    port map (
      C => clk,
      D => trn_tbuf_av_int_1_and0000_23961,
      R => rst_n_inv,
      Q => trn_tbuf_av_int(1)
    );
  tx_arb : pcie_blk_ll_tx_arb
    port map (
      tx_src_rdy_n => tx_src_rdy_n,
      clk => clk,
      tx_sof_n => tx_sof_n,
      rst_n => rst_n,
      cfg_tx_dst_rdy_n => cfg_tx_dst_rdy_n,
      cfg_tx_eof_n => cfg_tx_eof_n,
      trn_tsrc_dsc_n => trn_tsrc_dsc_n,
      trn_tdst_rdy_n => trn_tdst_rdy_n,
      trn_teof_n => trn_teof_n,
      cfg_tx_src_rdy_n => cfg_tx_src_rdy_n,
      cfg_tx_sof_n => cfg_tx_sof_n,
      tx_src_dsc_n => tx_src_dsc_n,
      tx_dst_rdy_n => tx_dst_rdy_n,
      trn_tsrc_rdy_n => trn_tsrc_rdy_n,
      trn_tsof_n => trn_tsof_n,
      cfg_tx_rem_n => cfg_tx_rem_n,
      tx_eof_n => tx_eof_n,
      trn_tdst_dsc_n => trn_tdst_dsc_n,
      tx_rem_n(7) => tx_rem_n(7),
      tx_rem_n(6) => tx_rem_n(6),
      tx_rem_n(5) => tx_rem_n(5),
      tx_rem_n(4) => tx_rem_n(4),
      tx_rem_n(3) => tx_rem_n(3),
      tx_rem_n(2) => tx_rem_n(2),
      tx_rem_n(1) => tx_rem_n(1),
      tx_rem_n(0) => tx_rem_n(0),
      tx_td(63) => tx_td(63),
      tx_td(62) => tx_td(62),
      tx_td(61) => tx_td(61),
      tx_td(60) => tx_td(60),
      tx_td(59) => tx_td(59),
      tx_td(58) => tx_td(58),
      tx_td(57) => tx_td(57),
      tx_td(56) => tx_td(56),
      tx_td(55) => tx_td(55),
      tx_td(54) => tx_td(54),
      tx_td(53) => tx_td(53),
      tx_td(52) => tx_td(52),
      tx_td(51) => tx_td(51),
      tx_td(50) => tx_td(50),
      tx_td(49) => tx_td(49),
      tx_td(48) => tx_td(48),
      tx_td(47) => tx_td(47),
      tx_td(46) => tx_td(46),
      tx_td(45) => tx_td(45),
      tx_td(44) => tx_td(44),
      tx_td(43) => tx_td(43),
      tx_td(42) => tx_td(42),
      tx_td(41) => tx_td(41),
      tx_td(40) => tx_td(40),
      tx_td(39) => tx_td(39),
      tx_td(38) => tx_td(38),
      tx_td(37) => tx_td(37),
      tx_td(36) => tx_td(36),
      tx_td(35) => tx_td(35),
      tx_td(34) => tx_td(34),
      tx_td(33) => tx_td(33),
      tx_td(32) => tx_td(32),
      tx_td(31) => tx_td(31),
      tx_td(30) => tx_td(30),
      tx_td(29) => tx_td(29),
      tx_td(28) => tx_td(28),
      tx_td(27) => tx_td(27),
      tx_td(26) => tx_td(26),
      tx_td(25) => tx_td(25),
      tx_td(24) => tx_td(24),
      tx_td(23) => tx_td(23),
      tx_td(22) => tx_td(22),
      tx_td(21) => tx_td(21),
      tx_td(20) => tx_td(20),
      tx_td(19) => tx_td(19),
      tx_td(18) => tx_td(18),
      tx_td(17) => tx_td(17),
      tx_td(16) => tx_td(16),
      tx_td(15) => tx_td(15),
      tx_td(14) => tx_td(14),
      tx_td(13) => tx_td(13),
      tx_td(12) => tx_td(12),
      tx_td(11) => tx_td(11),
      tx_td(10) => tx_td(10),
      tx_td(9) => tx_td(9),
      tx_td(8) => tx_td(8),
      tx_td(7) => tx_td(7),
      tx_td(6) => tx_td(6),
      tx_td(5) => tx_td(5),
      tx_td(4) => tx_td(4),
      tx_td(3) => tx_td(3),
      tx_td(2) => tx_td(2),
      tx_td(1) => tx_td(1),
      tx_td(0) => tx_td(0),
      trn_td(63) => trn_td(63),
      trn_td(62) => trn_td(62),
      trn_td(61) => trn_td(61),
      trn_td(60) => trn_td(60),
      trn_td(59) => trn_td(59),
      trn_td(58) => trn_td(58),
      trn_td(57) => trn_td(57),
      trn_td(56) => trn_td(56),
      trn_td(55) => trn_td(55),
      trn_td(54) => trn_td(54),
      trn_td(53) => trn_td(53),
      trn_td(52) => trn_td(52),
      trn_td(51) => trn_td(51),
      trn_td(50) => trn_td(50),
      trn_td(49) => trn_td(49),
      trn_td(48) => trn_td(48),
      trn_td(47) => trn_td(47),
      trn_td(46) => trn_td(46),
      trn_td(45) => trn_td(45),
      trn_td(44) => trn_td(44),
      trn_td(43) => trn_td(43),
      trn_td(42) => trn_td(42),
      trn_td(41) => trn_td(41),
      trn_td(40) => trn_td(40),
      trn_td(39) => trn_td(39),
      trn_td(38) => trn_td(38),
      trn_td(37) => trn_td(37),
      trn_td(36) => trn_td(36),
      trn_td(35) => trn_td(35),
      trn_td(34) => trn_td(34),
      trn_td(33) => trn_td(33),
      trn_td(32) => trn_td(32),
      trn_td(31) => trn_td(31),
      trn_td(30) => trn_td(30),
      trn_td(29) => trn_td(29),
      trn_td(28) => trn_td(28),
      trn_td(27) => trn_td(27),
      trn_td(26) => trn_td(26),
      trn_td(25) => trn_td(25),
      trn_td(24) => trn_td(24),
      trn_td(23) => trn_td(23),
      trn_td(22) => trn_td(22),
      trn_td(21) => trn_td(21),
      trn_td(20) => trn_td(20),
      trn_td(19) => trn_td(19),
      trn_td(18) => trn_td(18),
      trn_td(17) => trn_td(17),
      trn_td(16) => trn_td(16),
      trn_td(15) => trn_td(15),
      trn_td(14) => trn_td(14),
      trn_td(13) => trn_td(13),
      trn_td(12) => trn_td(12),
      trn_td(11) => trn_td(11),
      trn_td(10) => trn_td(10),
      trn_td(9) => trn_td(9),
      trn_td(8) => trn_td(8),
      trn_td(7) => trn_td(7),
      trn_td(6) => trn_td(6),
      trn_td(5) => trn_td(5),
      trn_td(4) => trn_td(4),
      trn_td(3) => trn_td(3),
      trn_td(2) => trn_td(2),
      trn_td(1) => trn_td(1),
      trn_td(0) => trn_td(0),
      cfg_tx_td(63) => cfg_tx_td(63),
      cfg_tx_td(62) => cfg_tx_td(62),
      cfg_tx_td(61) => cfg_tx_td(61),
      cfg_tx_td(60) => cfg_tx_td(60),
      cfg_tx_td(59) => cfg_tx_td(59),
      cfg_tx_td(58) => cfg_tx_td(58),
      cfg_tx_td(57) => cfg_tx_td(57),
      cfg_tx_td(56) => cfg_tx_td(56),
      cfg_tx_td(55) => cfg_tx_td(55),
      cfg_tx_td(54) => cfg_tx_td(54),
      cfg_tx_td(53) => cfg_tx_td(53),
      cfg_tx_td(52) => cfg_tx_td(52),
      cfg_tx_td(51) => cfg_tx_td(51),
      cfg_tx_td(50) => cfg_tx_td(50),
      cfg_tx_td(49) => cfg_tx_td(49),
      cfg_tx_td(48) => cfg_tx_td(48),
      cfg_tx_td(47) => cfg_tx_td(47),
      cfg_tx_td(46) => cfg_tx_td(46),
      cfg_tx_td(45) => cfg_tx_td(45),
      cfg_tx_td(44) => cfg_tx_td(44),
      cfg_tx_td(43) => cfg_tx_td(43),
      cfg_tx_td(42) => cfg_tx_td(42),
      cfg_tx_td(41) => cfg_tx_td(41),
      cfg_tx_td(40) => cfg_tx_td(40),
      cfg_tx_td(39) => cfg_tx_td(39),
      cfg_tx_td(38) => cfg_tx_td(38),
      cfg_tx_td(37) => cfg_tx_td(37),
      cfg_tx_td(36) => cfg_tx_td(36),
      cfg_tx_td(35) => cfg_tx_td(35),
      cfg_tx_td(34) => cfg_tx_td(34),
      cfg_tx_td(33) => cfg_tx_td(33),
      cfg_tx_td(32) => cfg_tx_td(32),
      cfg_tx_td(31) => cfg_tx_td(31),
      cfg_tx_td(30) => cfg_tx_td(30),
      cfg_tx_td(29) => cfg_tx_td(29),
      cfg_tx_td(28) => cfg_tx_td(28),
      cfg_tx_td(27) => cfg_tx_td(27),
      cfg_tx_td(26) => cfg_tx_td(26),
      cfg_tx_td(25) => cfg_tx_td(25),
      cfg_tx_td(24) => cfg_tx_td(24),
      cfg_tx_td(23) => cfg_tx_td(23),
      cfg_tx_td(22) => cfg_tx_td(22),
      cfg_tx_td(21) => cfg_tx_td(21),
      cfg_tx_td(20) => cfg_tx_td(20),
      cfg_tx_td(19) => cfg_tx_td(19),
      cfg_tx_td(18) => cfg_tx_td(18),
      cfg_tx_td(17) => cfg_tx_td(17),
      cfg_tx_td(16) => cfg_tx_td(16),
      cfg_tx_td(15) => cfg_tx_td(15),
      cfg_tx_td(14) => cfg_tx_td(14),
      cfg_tx_td(13) => cfg_tx_td(13),
      cfg_tx_td(12) => cfg_tx_td(12),
      cfg_tx_td(11) => cfg_tx_td(11),
      cfg_tx_td(10) => cfg_tx_td(10),
      cfg_tx_td(9) => cfg_tx_td(9),
      cfg_tx_td(8) => cfg_tx_td(8),
      cfg_tx_td(7) => cfg_tx_td(7),
      cfg_tx_td(6) => cfg_tx_td(6),
      cfg_tx_td(5) => cfg_tx_td(5),
      cfg_tx_td(4) => cfg_tx_td(4),
      cfg_tx_td(3) => cfg_tx_td(3),
      cfg_tx_td(2) => cfg_tx_td(2),
      cfg_tx_td(1) => cfg_tx_td(1),
      cfg_tx_td(0) => cfg_tx_td(0),
      trn_trem_n(7) => trn_trem_n(7),
      trn_trem_n(6) => trn_trem_n(6),
      trn_trem_n(5) => trn_trem_n(5),
      trn_trem_n(4) => trn_trem_n(4),
      trn_trem_n(3) => trn_trem_n(3),
      trn_trem_n(2) => trn_trem_n(2),
      trn_trem_n(1) => trn_trem_n(1),
      trn_trem_n(0) => trn_trem_n(0)
    );
  tx_bridge : pcie_blk_ll_tx
    port map (
      clear_cpl_count => clear_cpl_count,
      llk_tx_src_rdy_n => llk_tx_src_rdy_n,
      trn_terrfwd_n => NLW_tx_bridge_trn_terrfwd_n_UNCONNECTED,
      clk => clk,
      rst_n => rst_n,
      trn_tsrc_dsc_n => tx_src_dsc_n,
      trn_pfc_cplh_cl_upd => trn_pfc_cplh_cl_upd,
      llk_tx_sop_n => llk_tx_sop_n,
      trn_tdst_rdy_n => tx_dst_rdy_n,
      trn_teof_n => tx_eof_n,
      l0_stats_cfg_transmitted => l0_stats_cfg_transmitted,
      llk_tx_src_dsc_n => llk_tx_src_dsc_n,
      llk_tx_eof_n => llk_tx_eof_n,
      llk_tx_dst_rdy_n => llk_tx_dst_rdy_n,
      trn_tbuf_av_cpl => trn_tbuf_av(3),
      trn_tsrc_rdy_n => tx_src_rdy_n,
      npd_credit_limited => npd_credit_limited,
      trn_tsof_n => tx_sof_n,
      pd_credit_limited => pd_credit_limited,
      trn_tdst_dsc_n => NLW_tx_bridge_trn_tdst_dsc_n_UNCONNECTED,
      llk_tx_eop_n => llk_tx_eop_n,
      cd_credit_limited => cd_credit_limited,
      llk_tx_sof_n => llk_tx_sof_n,
      trn_lnk_up_n => trn_lnk_up_n,
      llk_tx_ch_fifo(1) => llk_tx_ch_fifo(1),
      llk_tx_ch_fifo(0) => llk_tx_ch_fifo(0),
      llk_tx_ch_tc(2) => llk_tx_ch_tc(2),
      llk_tx_ch_tc(1) => llk_tx_ch_tc(1),
      llk_tx_ch_tc(0) => llk_tx_ch_tc(0),
      llk_tx_enable_n(1) => llk_tx_enable_n(1),
      llk_tx_enable_n(0) => llk_tx_enable_n(0),
      llk_tx_data(63) => llk_tx_data(63),
      llk_tx_data(62) => llk_tx_data(62),
      llk_tx_data(61) => llk_tx_data(61),
      llk_tx_data(60) => llk_tx_data(60),
      llk_tx_data(59) => llk_tx_data(59),
      llk_tx_data(58) => llk_tx_data(58),
      llk_tx_data(57) => llk_tx_data(57),
      llk_tx_data(56) => llk_tx_data(56),
      llk_tx_data(55) => llk_tx_data(55),
      llk_tx_data(54) => llk_tx_data(54),
      llk_tx_data(53) => llk_tx_data(53),
      llk_tx_data(52) => llk_tx_data(52),
      llk_tx_data(51) => llk_tx_data(51),
      llk_tx_data(50) => llk_tx_data(50),
      llk_tx_data(49) => llk_tx_data(49),
      llk_tx_data(48) => llk_tx_data(48),
      llk_tx_data(47) => llk_tx_data(47),
      llk_tx_data(46) => llk_tx_data(46),
      llk_tx_data(45) => llk_tx_data(45),
      llk_tx_data(44) => llk_tx_data(44),
      llk_tx_data(43) => llk_tx_data(43),
      llk_tx_data(42) => llk_tx_data(42),
      llk_tx_data(41) => llk_tx_data(41),
      llk_tx_data(40) => llk_tx_data(40),
      llk_tx_data(39) => llk_tx_data(39),
      llk_tx_data(38) => llk_tx_data(38),
      llk_tx_data(37) => llk_tx_data(37),
      llk_tx_data(36) => llk_tx_data(36),
      llk_tx_data(35) => llk_tx_data(35),
      llk_tx_data(34) => llk_tx_data(34),
      llk_tx_data(33) => llk_tx_data(33),
      llk_tx_data(32) => llk_tx_data(32),
      llk_tx_data(31) => llk_tx_data(31),
      llk_tx_data(30) => llk_tx_data(30),
      llk_tx_data(29) => llk_tx_data(29),
      llk_tx_data(28) => llk_tx_data(28),
      llk_tx_data(27) => llk_tx_data(27),
      llk_tx_data(26) => llk_tx_data(26),
      llk_tx_data(25) => llk_tx_data(25),
      llk_tx_data(24) => llk_tx_data(24),
      llk_tx_data(23) => llk_tx_data(23),
      llk_tx_data(22) => llk_tx_data(22),
      llk_tx_data(21) => llk_tx_data(21),
      llk_tx_data(20) => llk_tx_data(20),
      llk_tx_data(19) => llk_tx_data(19),
      llk_tx_data(18) => llk_tx_data(18),
      llk_tx_data(17) => llk_tx_data(17),
      llk_tx_data(16) => llk_tx_data(16),
      llk_tx_data(15) => llk_tx_data(15),
      llk_tx_data(14) => llk_tx_data(14),
      llk_tx_data(13) => llk_tx_data(13),
      llk_tx_data(12) => llk_tx_data(12),
      llk_tx_data(11) => llk_tx_data(11),
      llk_tx_data(10) => llk_tx_data(10),
      llk_tx_data(9) => llk_tx_data(9),
      llk_tx_data(8) => llk_tx_data(8),
      llk_tx_data(7) => llk_tx_data(7),
      llk_tx_data(6) => llk_tx_data(6),
      llk_tx_data(5) => llk_tx_data(5),
      llk_tx_data(4) => llk_tx_data(4),
      llk_tx_data(3) => llk_tx_data(3),
      llk_tx_data(2) => llk_tx_data(2),
      llk_tx_data(1) => llk_tx_data(1),
      llk_tx_data(0) => llk_tx_data(0),
      trn_td(63) => tx_td(63),
      trn_td(62) => tx_td(62),
      trn_td(61) => tx_td(61),
      trn_td(60) => tx_td(60),
      trn_td(59) => tx_td(59),
      trn_td(58) => tx_td(58),
      trn_td(57) => tx_td(57),
      trn_td(56) => tx_td(56),
      trn_td(55) => tx_td(55),
      trn_td(54) => tx_td(54),
      trn_td(53) => tx_td(53),
      trn_td(52) => tx_td(52),
      trn_td(51) => tx_td(51),
      trn_td(50) => tx_td(50),
      trn_td(49) => tx_td(49),
      trn_td(48) => tx_td(48),
      trn_td(47) => tx_td(47),
      trn_td(46) => tx_td(46),
      trn_td(45) => tx_td(45),
      trn_td(44) => tx_td(44),
      trn_td(43) => tx_td(43),
      trn_td(42) => tx_td(42),
      trn_td(41) => tx_td(41),
      trn_td(40) => tx_td(40),
      trn_td(39) => tx_td(39),
      trn_td(38) => tx_td(38),
      trn_td(37) => tx_td(37),
      trn_td(36) => tx_td(36),
      trn_td(35) => tx_td(35),
      trn_td(34) => tx_td(34),
      trn_td(33) => tx_td(33),
      trn_td(32) => tx_td(32),
      trn_td(31) => tx_td(31),
      trn_td(30) => tx_td(30),
      trn_td(29) => tx_td(29),
      trn_td(28) => tx_td(28),
      trn_td(27) => tx_td(27),
      trn_td(26) => tx_td(26),
      trn_td(25) => tx_td(25),
      trn_td(24) => tx_td(24),
      trn_td(23) => tx_td(23),
      trn_td(22) => tx_td(22),
      trn_td(21) => tx_td(21),
      trn_td(20) => tx_td(20),
      trn_td(19) => tx_td(19),
      trn_td(18) => tx_td(18),
      trn_td(17) => tx_td(17),
      trn_td(16) => tx_td(16),
      trn_td(15) => tx_td(15),
      trn_td(14) => tx_td(14),
      trn_td(13) => tx_td(13),
      trn_td(12) => tx_td(12),
      trn_td(11) => tx_td(11),
      trn_td(10) => tx_td(10),
      trn_td(9) => tx_td(9),
      trn_td(8) => tx_td(8),
      trn_td(7) => tx_td(7),
      trn_td(6) => tx_td(6),
      trn_td(5) => tx_td(5),
      trn_td(4) => tx_td(4),
      trn_td(3) => tx_td(3),
      trn_td(2) => tx_td(2),
      trn_td(1) => tx_td(1),
      trn_td(0) => tx_td(0),
      tx_pd_credits_consumed(11) => tx_pd_credits_consumed(11),
      tx_pd_credits_consumed(10) => tx_pd_credits_consumed(10),
      tx_pd_credits_consumed(9) => tx_pd_credits_consumed(9),
      tx_pd_credits_consumed(8) => tx_pd_credits_consumed(8),
      tx_pd_credits_consumed(7) => tx_pd_credits_consumed(7),
      tx_pd_credits_consumed(6) => tx_pd_credits_consumed(6),
      tx_pd_credits_consumed(5) => tx_pd_credits_consumed(5),
      tx_pd_credits_consumed(4) => tx_pd_credits_consumed(4),
      tx_pd_credits_consumed(3) => tx_pd_credits_consumed(3),
      tx_pd_credits_consumed(2) => tx_pd_credits_consumed(2),
      tx_pd_credits_consumed(1) => tx_pd_credits_consumed(1),
      tx_pd_credits_consumed(0) => tx_pd_credits_consumed(0),
      llk_tx_ch_non_posted_ready_n(7) => llk_tx_ch_non_posted_ready_n(7),
      llk_tx_ch_non_posted_ready_n(6) => llk_tx_ch_non_posted_ready_n(6),
      llk_tx_ch_non_posted_ready_n(5) => llk_tx_ch_non_posted_ready_n(5),
      llk_tx_ch_non_posted_ready_n(4) => llk_tx_ch_non_posted_ready_n(4),
      llk_tx_ch_non_posted_ready_n(3) => llk_tx_ch_non_posted_ready_n(3),
      llk_tx_ch_non_posted_ready_n(2) => llk_tx_ch_non_posted_ready_n(2),
      llk_tx_ch_non_posted_ready_n(1) => llk_tx_ch_non_posted_ready_n(1),
      llk_tx_ch_non_posted_ready_n(0) => llk_tx_ch_non_posted_ready_n(0),
      trn_pfc_cplh_cl(7) => trn_pfc_cplh_cl(7),
      trn_pfc_cplh_cl(6) => trn_pfc_cplh_cl(6),
      trn_pfc_cplh_cl(5) => trn_pfc_cplh_cl(5),
      trn_pfc_cplh_cl(4) => trn_pfc_cplh_cl(4),
      trn_pfc_cplh_cl(3) => trn_pfc_cplh_cl(3),
      trn_pfc_cplh_cl(2) => trn_pfc_cplh_cl(2),
      trn_pfc_cplh_cl(1) => trn_pfc_cplh_cl(1),
      trn_pfc_cplh_cl(0) => trn_pfc_cplh_cl(0),
      tx_npd_credits_consumed(11) => tx_npd_credits_consumed(11),
      tx_npd_credits_consumed(10) => tx_npd_credits_consumed(10),
      tx_npd_credits_consumed(9) => tx_npd_credits_consumed(9),
      tx_npd_credits_consumed(8) => tx_npd_credits_consumed(8),
      tx_npd_credits_consumed(7) => tx_npd_credits_consumed(7),
      tx_npd_credits_consumed(6) => tx_npd_credits_consumed(6),
      tx_npd_credits_consumed(5) => tx_npd_credits_consumed(5),
      tx_npd_credits_consumed(4) => tx_npd_credits_consumed(4),
      tx_npd_credits_consumed(3) => tx_npd_credits_consumed(3),
      tx_npd_credits_consumed(2) => tx_npd_credits_consumed(2),
      tx_npd_credits_consumed(1) => tx_npd_credits_consumed(1),
      tx_npd_credits_consumed(0) => tx_npd_credits_consumed(0),
      tx_ch_credits_consumed(7) => tx_ch_credits_consumed(7),
      tx_ch_credits_consumed(6) => tx_ch_credits_consumed(6),
      tx_ch_credits_consumed(5) => tx_ch_credits_consumed(5),
      tx_ch_credits_consumed(4) => tx_ch_credits_consumed(4),
      tx_ch_credits_consumed(3) => tx_ch_credits_consumed(3),
      tx_ch_credits_consumed(2) => tx_ch_credits_consumed(2),
      tx_ch_credits_consumed(1) => tx_ch_credits_consumed(1),
      tx_ch_credits_consumed(0) => tx_ch_credits_consumed(0),
      llk_tx_ch_posted_ready_n(7) => llk_tx_ch_posted_ready_n(7),
      llk_tx_ch_posted_ready_n(6) => llk_tx_ch_posted_ready_n(6),
      llk_tx_ch_posted_ready_n(5) => llk_tx_ch_posted_ready_n(5),
      llk_tx_ch_posted_ready_n(4) => llk_tx_ch_posted_ready_n(4),
      llk_tx_ch_posted_ready_n(3) => llk_tx_ch_posted_ready_n(3),
      llk_tx_ch_posted_ready_n(2) => llk_tx_ch_posted_ready_n(2),
      llk_tx_ch_posted_ready_n(1) => llk_tx_ch_posted_ready_n(1),
      llk_tx_ch_posted_ready_n(0) => llk_tx_ch_posted_ready_n(0),
      tx_cd_credits_consumed(11) => tx_cd_credits_consumed(11),
      tx_cd_credits_consumed(10) => tx_cd_credits_consumed(10),
      tx_cd_credits_consumed(9) => tx_cd_credits_consumed(9),
      tx_cd_credits_consumed(8) => tx_cd_credits_consumed(8),
      tx_cd_credits_consumed(7) => tx_cd_credits_consumed(7),
      tx_cd_credits_consumed(6) => tx_cd_credits_consumed(6),
      tx_cd_credits_consumed(5) => tx_cd_credits_consumed(5),
      tx_cd_credits_consumed(4) => tx_cd_credits_consumed(4),
      tx_cd_credits_consumed(3) => tx_cd_credits_consumed(3),
      tx_cd_credits_consumed(2) => tx_cd_credits_consumed(2),
      tx_cd_credits_consumed(1) => tx_cd_credits_consumed(1),
      tx_cd_credits_consumed(0) => tx_cd_credits_consumed(0),
      tx_npd_credits_available(11) => tx_npd_credits_available(11),
      tx_npd_credits_available(10) => tx_npd_credits_available(10),
      tx_npd_credits_available(9) => tx_npd_credits_available(9),
      tx_npd_credits_available(8) => tx_npd_credits_available(8),
      tx_npd_credits_available(7) => tx_npd_credits_available(7),
      tx_npd_credits_available(6) => tx_npd_credits_available(6),
      tx_npd_credits_available(5) => tx_npd_credits_available(5),
      tx_npd_credits_available(4) => tx_npd_credits_available(4),
      tx_npd_credits_available(3) => tx_npd_credits_available(3),
      tx_npd_credits_available(2) => tx_npd_credits_available(2),
      tx_npd_credits_available(1) => tx_npd_credits_available(1),
      tx_npd_credits_available(0) => tx_npd_credits_available(0),
      llk_tx_chan_space(9) => llk_tx_chan_space(9),
      llk_tx_chan_space(8) => llk_tx_chan_space(8),
      llk_tx_chan_space(7) => llk_tx_chan_space(7),
      llk_tx_chan_space(6) => llk_tx_chan_space(6),
      llk_tx_chan_space(5) => llk_tx_chan_space(5),
      llk_tx_chan_space(4) => llk_tx_chan_space(4),
      llk_tx_chan_space(3) => llk_tx_chan_space(3),
      llk_tx_chan_space(2) => llk_tx_chan_space(2),
      llk_tx_chan_space(1) => llk_tx_chan_space(1),
      llk_tx_chan_space(0) => llk_tx_chan_space(0),
      llk_tx_ch_completion_ready_n(7) => llk_tx_ch_completion_ready_n(7),
      llk_tx_ch_completion_ready_n(6) => llk_tx_ch_completion_ready_n(6),
      llk_tx_ch_completion_ready_n(5) => llk_tx_ch_completion_ready_n(5),
      llk_tx_ch_completion_ready_n(4) => llk_tx_ch_completion_ready_n(4),
      llk_tx_ch_completion_ready_n(3) => llk_tx_ch_completion_ready_n(3),
      llk_tx_ch_completion_ready_n(2) => llk_tx_ch_completion_ready_n(2),
      llk_tx_ch_completion_ready_n(1) => llk_tx_ch_completion_ready_n(1),
      llk_tx_ch_completion_ready_n(0) => llk_tx_ch_completion_ready_n(0),
      tx_cd_credits_available(11) => tx_cd_credits_available(11),
      tx_cd_credits_available(10) => tx_cd_credits_available(10),
      tx_cd_credits_available(9) => tx_cd_credits_available(9),
      tx_cd_credits_available(8) => tx_cd_credits_available(8),
      tx_cd_credits_available(7) => tx_cd_credits_available(7),
      tx_cd_credits_available(6) => tx_cd_credits_available(6),
      tx_cd_credits_available(5) => tx_cd_credits_available(5),
      tx_cd_credits_available(4) => tx_cd_credits_available(4),
      tx_cd_credits_available(3) => tx_cd_credits_available(3),
      tx_cd_credits_available(2) => tx_cd_credits_available(2),
      tx_cd_credits_available(1) => tx_cd_credits_available(1),
      tx_cd_credits_available(0) => tx_cd_credits_available(0),
      trn_trem_n(7) => tx_rem_n(7),
      trn_trem_n(6) => tx_rem_n(6),
      trn_trem_n(5) => tx_rem_n(5),
      trn_trem_n(4) => tx_rem_n(4),
      trn_trem_n(3) => tx_rem_n(3),
      trn_trem_n(2) => tx_rem_n(2),
      trn_trem_n(1) => tx_rem_n(1),
      trn_trem_n(0) => tx_rem_n(0),
      tx_pd_credits_available(11) => tx_pd_credits_available(11),
      tx_pd_credits_available(10) => tx_pd_credits_available(10),
      tx_pd_credits_available(9) => tx_pd_credits_available(9),
      tx_pd_credits_available(8) => tx_pd_credits_available(8),
      tx_pd_credits_available(7) => tx_pd_credits_available(7),
      tx_pd_credits_available(6) => tx_pd_credits_available(6),
      tx_pd_credits_available(5) => tx_pd_credits_available(5),
      tx_pd_credits_available(4) => tx_pd_credits_available(4),
      tx_pd_credits_available(3) => tx_pd_credits_available(3),
      tx_pd_credits_available(2) => tx_pd_credits_available(2),
      tx_pd_credits_available(1) => tx_pd_credits_available(1),
      tx_pd_credits_available(0) => tx_pd_credits_available(0)
    );
  tx_err_wr_ep_n_not00011 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => tx_sof_n,
      I1 => tx_dst_rdy_n,
      I2 => tx_td(46),
      I3 => tx_src_rdy_n,
      O => tx_err_wr_ep_n_not0001
    );
  trn_tbuf_av_int_0_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => llk_tx_ch_non_posted_ready_n(0),
      I1 => llk_tx_ch_non_posted_ready_n(3),
      I2 => llk_tx_ch_non_posted_ready_n(2),
      O => N01
    );
  trn_tbuf_av_int_0_and0000 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_tx_ch_non_posted_ready_n(5),
      I1 => llk_tx_ch_non_posted_ready_n(7),
      I2 => llk_tx_ch_non_posted_ready_n(6),
      I3 => llk_tx_ch_non_posted_ready_n(4),
      I4 => llk_tx_ch_non_posted_ready_n(1),
      I5 => N01,
      O => trn_tbuf_av_int_0_and0000_23959
    );
  trn_tbuf_av_int_1_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => llk_tx_ch_posted_ready_n(2),
      I1 => llk_tx_ch_posted_ready_n(1),
      I2 => llk_tx_ch_posted_ready_n(6),
      O => N2
    );
  trn_tbuf_av_int_1_and0000 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_tx_ch_posted_ready_n(7),
      I1 => llk_tx_ch_posted_ready_n(4),
      I2 => llk_tx_ch_posted_ready_n(5),
      I3 => llk_tx_ch_posted_ready_n(3),
      I4 => llk_tx_ch_posted_ready_n(0),
      I5 => N2,
      O => trn_tbuf_av_int_1_and0000_23961
    );
  trn_tbuf_av_int_2_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => llk_tx_ch_completion_ready_n(4),
      I1 => llk_tx_ch_completion_ready_n(3),
      I2 => llk_tx_ch_completion_ready_n(7),
      O => N4
    );
  trn_tbuf_av_int_2_and0000 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => llk_tx_ch_completion_ready_n(6),
      I1 => llk_tx_ch_completion_ready_n(5),
      I2 => llk_tx_ch_completion_ready_n(1),
      I3 => llk_tx_ch_completion_ready_n(2),
      I4 => llk_tx_ch_completion_ready_n(0),
      I5 => N4,
      O => trn_tbuf_av_int_2_and0000_23963
    );
  rst_n_inv1_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_17 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_17;

architecture STRUCTURE of my_SRL16E_17 is
  signal Mshreg_data_9_22294 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal RST_N_inv_shift1_22299 : STD_LOGIC; 
  signal RST_N_inv_shift2_22300 : STD_LOGIC; 
  signal RST_N_inv_shift3_22301 : STD_LOGIC; 
  signal data_0_Q : STD_LOGIC; 
  signal data_1_Q : STD_LOGIC; 
  signal data_10_Q : STD_LOGIC; 
  signal data_11_Q : STD_LOGIC; 
  signal data_2_Q : STD_LOGIC; 
  signal data_3_Q : STD_LOGIC; 
  signal data_4_Q : STD_LOGIC; 
  signal data_5_Q : STD_LOGIC; 
  signal data_9_Q : STD_LOGIC; 
  signal data_91_22311 : STD_LOGIC; 
  signal data_911_22312 : STD_LOGIC; 
  signal NLW_Mshreg_data_9_Q15_UNCONNECTED : STD_LOGIC; 
begin
  Q <= data_11_Q;
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data_0_Q
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_0_Q,
      R => RST_N_inv,
      Q => data_1_Q
    );
  data_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_1_Q,
      S => RST_N_inv,
      Q => data_2_Q
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_2_Q,
      R => RST_N_inv,
      Q => data_3_Q
    );
  data_4 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_3_Q,
      S => RST_N_inv,
      Q => data_4_Q
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_4_Q,
      R => RST_N_inv,
      Q => data_5_Q
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_9_Q,
      R => RST_N_inv,
      Q => data_10_Q
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_10_Q,
      R => RST_N_inv,
      Q => data_11_Q
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  Mshreg_data_9 : SRLC16E
    generic map(
      INIT => X"0003"
    )
    port map (
      A0 => N1,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      CE => CE,
      CLK => CLK,
      D => data_5_Q,
      Q => Mshreg_data_9_22294,
      Q15 => NLW_Mshreg_data_9_Q15_UNCONNECTED
    );
  data_91 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => Mshreg_data_9_22294,
      Q => data_91_22311
    );
  RST_N_inv_shift1 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => N0,
      S => RST_N_inv,
      Q => RST_N_inv_shift1_22299
    );
  RST_N_inv_shift2 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift1_22299,
      S => RST_N_inv,
      Q => RST_N_inv_shift2_22300
    );
  RST_N_inv_shift3 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift2_22300,
      S => RST_N_inv,
      Q => RST_N_inv_shift3_22301
    );
  data_911 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => data_91_22311,
      I1 => RST_N_inv_shift3_22301,
      O => data_911_22312
    );
  data_9 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_911_22312,
      S => RST_N_inv,
      Q => data_9_Q
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_16 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_16;

architecture STRUCTURE of my_SRL16E_16 is
  signal Mshreg_data_11_22272 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal RST_N_inv_shift1_22277 : STD_LOGIC; 
  signal RST_N_inv_shift2_22278 : STD_LOGIC; 
  signal RST_N_inv_shift3_22279 : STD_LOGIC; 
  signal data_0_Q : STD_LOGIC; 
  signal data_1_Q : STD_LOGIC; 
  signal data_11_Q : STD_LOGIC; 
  signal data_111_22283 : STD_LOGIC; 
  signal data_1111_22284 : STD_LOGIC; 
  signal data_2_Q : STD_LOGIC; 
  signal data_3_Q : STD_LOGIC; 
  signal data_4_Q : STD_LOGIC; 
  signal data_5_Q : STD_LOGIC; 
  signal data_6_Q : STD_LOGIC; 
  signal data_7_Q : STD_LOGIC; 
  signal NLW_Mshreg_data_11_Q15_UNCONNECTED : STD_LOGIC; 
begin
  Q <= data_11_Q;
  data_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      R => RST_N_inv,
      Q => data_0_Q
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_0_Q,
      R => RST_N_inv,
      Q => data_1_Q
    );
  data_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_1_Q,
      S => RST_N_inv,
      Q => data_2_Q
    );
  data_3 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_2_Q,
      S => RST_N_inv,
      Q => data_3_Q
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_3_Q,
      R => RST_N_inv,
      Q => data_4_Q
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_4_Q,
      R => RST_N_inv,
      Q => data_5_Q
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_5_Q,
      S => RST_N_inv,
      Q => data_6_Q
    );
  data_7 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_6_Q,
      S => RST_N_inv,
      Q => data_7_Q
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  Mshreg_data_11 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N1,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      CE => CE,
      CLK => CLK,
      D => data_7_Q,
      Q => Mshreg_data_11_22272,
      Q15 => NLW_Mshreg_data_11_Q15_UNCONNECTED
    );
  data_111 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => Mshreg_data_11_22272,
      Q => data_111_22283
    );
  RST_N_inv_shift1 : FDRE
    port map (
      C => CLK,
      CE => CE,
      D => N1,
      R => RST_N_inv,
      Q => RST_N_inv_shift1_22277
    );
  RST_N_inv_shift2 : FDRE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift1_22277,
      R => RST_N_inv,
      Q => RST_N_inv_shift2_22278
    );
  RST_N_inv_shift3 : FDRE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift2_22278,
      R => RST_N_inv,
      Q => RST_N_inv_shift3_22279
    );
  data_1111 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data_111_22283,
      I1 => RST_N_inv_shift3_22279,
      O => data_1111_22284
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_1111_22284,
      R => RST_N_inv,
      Q => data_11_Q
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_15 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_15;

architecture STRUCTURE of my_SRL16E_15 is
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 11 downto 0 ); 
begin
  Q <= data(11);
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      S => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      R => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      R => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_14 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_14;

architecture STRUCTURE of my_SRL16E_14 is
  signal Mshreg_data_6_22233 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal RST_N_inv_shift1_22238 : STD_LOGIC; 
  signal RST_N_inv_shift2_22239 : STD_LOGIC; 
  signal RST_N_inv_shift3_22240 : STD_LOGIC; 
  signal RST_N_inv_shift4_22241 : STD_LOGIC; 
  signal RST_N_inv_shift5_22242 : STD_LOGIC; 
  signal RST_N_inv_shift6_22243 : STD_LOGIC; 
  signal data_61_22247 : STD_LOGIC; 
  signal data_611_22248 : STD_LOGIC; 
  signal NLW_Mshreg_data_6_Q15_UNCONNECTED : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 11 downto 6 ); 
begin
  Q <= data(11);
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      S => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  Mshreg_data_6 : SRLC16E
    generic map(
      INIT => X"001F"
    )
    port map (
      A0 => N0,
      A1 => N0,
      A2 => N1,
      A3 => N0,
      CE => CE,
      CLK => CLK,
      D => D,
      Q => Mshreg_data_6_22233,
      Q15 => NLW_Mshreg_data_6_Q15_UNCONNECTED
    );
  data_61 : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => Mshreg_data_6_22233,
      Q => data_61_22247
    );
  RST_N_inv_shift1 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => N0,
      S => RST_N_inv,
      Q => RST_N_inv_shift1_22238
    );
  RST_N_inv_shift2 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift1_22238,
      S => RST_N_inv,
      Q => RST_N_inv_shift2_22239
    );
  RST_N_inv_shift3 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift2_22239,
      S => RST_N_inv,
      Q => RST_N_inv_shift3_22240
    );
  RST_N_inv_shift4 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift3_22240,
      S => RST_N_inv,
      Q => RST_N_inv_shift4_22241
    );
  RST_N_inv_shift5 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift4_22241,
      S => RST_N_inv,
      Q => RST_N_inv_shift5_22242
    );
  RST_N_inv_shift6 : FDSE
    port map (
      C => CLK,
      CE => CE,
      D => RST_N_inv_shift5_22242,
      S => RST_N_inv,
      Q => RST_N_inv_shift6_22243
    );
  data_611 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => data_61_22247,
      I1 => RST_N_inv_shift6_22243,
      O => data_611_22248
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data_611_22248,
      S => RST_N_inv,
      Q => data(6)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_13 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_13;

architecture STRUCTURE of my_SRL16E_13 is
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 11 downto 0 ); 
begin
  Q <= data(11);
  data_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      R => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      S => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      S => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      S => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      S => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      S => RST_N_inv,
      Q => data(11)
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_12 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_12;

architecture STRUCTURE of my_SRL16E_12 is
  signal Mmux_Q_5_f7_22188 : STD_LOGIC; 
  signal Mmux_Q_6_22189 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22190 : STD_LOGIC; 
  signal Mmux_Q_7_22191 : STD_LOGIC; 
  signal Mmux_Q_71_22192 : STD_LOGIC; 
  signal Mmux_Q_8_22193 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      S => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      S => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      S => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      R => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      R => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22193
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22192
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22191
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22189
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22188,
      I2 => Mmux_Q_6_f7_22190,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22193,
      I1 => Mmux_Q_71_22192,
      S => A2,
      O => Mmux_Q_6_f7_22190
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22191,
      I1 => Mmux_Q_6_22189,
      S => A2,
      O => Mmux_Q_5_f7_22188
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_11 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_11;

architecture STRUCTURE of my_SRL16E_11 is
  signal Mmux_Q_5_f7_22156 : STD_LOGIC; 
  signal Mmux_Q_6_22157 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22158 : STD_LOGIC; 
  signal Mmux_Q_7_22159 : STD_LOGIC; 
  signal Mmux_Q_71_22160 : STD_LOGIC; 
  signal Mmux_Q_8_22161 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      S => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      S => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      S => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      S => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      S => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      S => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      R => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      S => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      S => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      S => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      S => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      S => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      S => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      S => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22161
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22160
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22159
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22157
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22156,
      I2 => Mmux_Q_6_f7_22158,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22161,
      I1 => Mmux_Q_71_22160,
      S => A2,
      O => Mmux_Q_6_f7_22158
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22159,
      I1 => Mmux_Q_6_22157,
      S => A2,
      O => Mmux_Q_5_f7_22156
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_10 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_10;

architecture STRUCTURE of my_SRL16E_10 is
  signal Mmux_Q_5_f7_22124 : STD_LOGIC; 
  signal Mmux_Q_6_22125 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22126 : STD_LOGIC; 
  signal Mmux_Q_7_22127 : STD_LOGIC; 
  signal Mmux_Q_71_22128 : STD_LOGIC; 
  signal Mmux_Q_8_22129 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      S => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      R => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      R => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      R => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      R => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22129
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22128
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22127
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22125
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22124,
      I2 => Mmux_Q_6_f7_22126,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22129,
      I1 => Mmux_Q_71_22128,
      S => A2,
      O => Mmux_Q_6_f7_22126
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22127,
      I1 => Mmux_Q_6_22125,
      S => A2,
      O => Mmux_Q_5_f7_22124
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_9 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_9;

architecture STRUCTURE of my_SRL16E_9 is
  signal Mmux_Q_5_f7_22092 : STD_LOGIC; 
  signal Mmux_Q_6_22093 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22094 : STD_LOGIC; 
  signal Mmux_Q_7_22095 : STD_LOGIC; 
  signal Mmux_Q_71_22096 : STD_LOGIC; 
  signal Mmux_Q_8_22097 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      S => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      S => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      S => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      R => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      S => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      S => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      S => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      S => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      S => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      S => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22097
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22096
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22095
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22093
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22092,
      I2 => Mmux_Q_6_f7_22094,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22097,
      I1 => Mmux_Q_71_22096,
      S => A2,
      O => Mmux_Q_6_f7_22094
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22095,
      I1 => Mmux_Q_6_22093,
      S => A2,
      O => Mmux_Q_5_f7_22092
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_8 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_8;

architecture STRUCTURE of my_SRL16E_8 is
  signal Mmux_Q_5_f7_22060 : STD_LOGIC; 
  signal Mmux_Q_6_22061 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22062 : STD_LOGIC; 
  signal Mmux_Q_7_22063 : STD_LOGIC; 
  signal Mmux_Q_71_22064 : STD_LOGIC; 
  signal Mmux_Q_8_22065 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      S => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      S => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      S => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      R => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      S => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      R => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      S => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      S => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      R => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      S => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      S => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22065
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22064
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22063
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22061
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22060,
      I2 => Mmux_Q_6_f7_22062,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22065,
      I1 => Mmux_Q_71_22064,
      S => A2,
      O => Mmux_Q_6_f7_22062
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22063,
      I1 => Mmux_Q_6_22061,
      S => A2,
      O => Mmux_Q_5_f7_22060
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_7 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_7;

architecture STRUCTURE of my_SRL16E_7 is
  signal Mmux_Q_5_f7_22028 : STD_LOGIC; 
  signal Mmux_Q_6_22029 : STD_LOGIC; 
  signal Mmux_Q_6_f7_22030 : STD_LOGIC; 
  signal Mmux_Q_7_22031 : STD_LOGIC; 
  signal Mmux_Q_71_22032 : STD_LOGIC; 
  signal Mmux_Q_8_22033 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      S => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      R => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      R => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      R => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      R => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      R => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22033
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22032
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_22031
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_22029
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_22028,
      I2 => Mmux_Q_6_f7_22030,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22033,
      I1 => Mmux_Q_71_22032,
      S => A2,
      O => Mmux_Q_6_f7_22030
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_22031,
      I1 => Mmux_Q_6_22029,
      S => A2,
      O => Mmux_Q_5_f7_22028
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_6 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_6;

architecture STRUCTURE of my_SRL16E_6 is
  signal Mmux_Q_5_f7_21996 : STD_LOGIC; 
  signal Mmux_Q_6_21997 : STD_LOGIC; 
  signal Mmux_Q_6_f7_21998 : STD_LOGIC; 
  signal Mmux_Q_7_21999 : STD_LOGIC; 
  signal Mmux_Q_71_22000 : STD_LOGIC; 
  signal Mmux_Q_8_22001 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      R => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      S => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      S => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      S => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      S => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      R => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      R => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_22001
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_22000
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_21999
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_21997
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_21996,
      I2 => Mmux_Q_6_f7_21998,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_22001,
      I1 => Mmux_Q_71_22000,
      S => A2,
      O => Mmux_Q_6_f7_21998
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_21999,
      I1 => Mmux_Q_6_21997,
      S => A2,
      O => Mmux_Q_5_f7_21996
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_5 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_5;

architecture STRUCTURE of my_SRL16E_5 is
  signal Mmux_Q_5_f7_21964 : STD_LOGIC; 
  signal Mmux_Q_6_21965 : STD_LOGIC; 
  signal Mmux_Q_6_f7_21966 : STD_LOGIC; 
  signal Mmux_Q_7_21967 : STD_LOGIC; 
  signal Mmux_Q_71_21968 : STD_LOGIC; 
  signal Mmux_Q_8_21969 : STD_LOGIC; 
  signal RST_N_inv : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  data_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => D,
      R => RST_N_inv,
      Q => data(0)
    );
  data_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(0),
      R => RST_N_inv,
      Q => data(1)
    );
  data_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(1),
      R => RST_N_inv,
      Q => data(2)
    );
  data_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(2),
      R => RST_N_inv,
      Q => data(3)
    );
  data_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(3),
      R => RST_N_inv,
      Q => data(4)
    );
  data_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(4),
      R => RST_N_inv,
      Q => data(5)
    );
  data_6 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(5),
      S => RST_N_inv,
      Q => data(6)
    );
  data_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(6),
      R => RST_N_inv,
      Q => data(7)
    );
  data_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(7),
      R => RST_N_inv,
      Q => data(8)
    );
  data_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(8),
      R => RST_N_inv,
      Q => data(9)
    );
  data_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(9),
      R => RST_N_inv,
      Q => data(10)
    );
  data_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(10),
      R => RST_N_inv,
      Q => data(11)
    );
  data_12 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(11),
      S => RST_N_inv,
      Q => data(12)
    );
  data_13 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(12),
      R => RST_N_inv,
      Q => data(13)
    );
  data_14 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(13),
      R => RST_N_inv,
      Q => data(14)
    );
  data_15 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      CE => CE,
      D => data(14),
      R => RST_N_inv,
      Q => data(15)
    );
  Mmux_Q_8 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(10),
      I2 => A1,
      I3 => data(9),
      I4 => data(8),
      I5 => data(11),
      O => Mmux_Q_8_21969
    );
  Mmux_Q_71 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(14),
      I2 => A1,
      I3 => data(13),
      I4 => data(12),
      I5 => data(15),
      O => Mmux_Q_71_21968
    );
  Mmux_Q_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(2),
      I2 => A1,
      I3 => data(1),
      I4 => data(0),
      I5 => data(3),
      O => Mmux_Q_7_21967
    );
  Mmux_Q_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => A0,
      I1 => data(6),
      I2 => A1,
      I3 => data(5),
      I4 => data(4),
      I5 => data(7),
      O => Mmux_Q_6_21965
    );
  A31 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => A3,
      I1 => Mmux_Q_5_f7_21964,
      I2 => Mmux_Q_6_f7_21966,
      O => Q
    );
  Mmux_Q_6_f7 : MUXF7
    port map (
      I0 => Mmux_Q_8_21969,
      I1 => Mmux_Q_71_21968,
      S => A2,
      O => Mmux_Q_6_f7_21966
    );
  Mmux_Q_5_f7 : MUXF7
    port map (
      I0 => Mmux_Q_7_21967,
      I1 => Mmux_Q_6_21965,
      S => A2,
      O => Mmux_Q_5_f7_21964
    );
  RST_N_inv1_INV_0 : INV
    port map (
      I => RST_N,
      O => RST_N_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_4 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_4;

architecture STRUCTURE of my_SRL16E_4 is
  signal D1_21924 : STD_LOGIC; 
  signal data_0_1_21926 : STD_LOGIC; 
  signal data_10_1_21927 : STD_LOGIC; 
  signal data_11_1_21928 : STD_LOGIC; 
  signal data_12_1_21929 : STD_LOGIC; 
  signal data_13_1_21930 : STD_LOGIC; 
  signal data_14_1_21931 : STD_LOGIC; 
  signal data_1_1_21932 : STD_LOGIC; 
  signal data_2_1_21933 : STD_LOGIC; 
  signal data_3_1_21934 : STD_LOGIC; 
  signal data_4_1_21935 : STD_LOGIC; 
  signal data_5_1_21936 : STD_LOGIC; 
  signal data_6_1_21937 : STD_LOGIC; 
  signal data_7_1_21938 : STD_LOGIC; 
  signal data_8_1_21939 : STD_LOGIC; 
  signal data_9_1_21940 : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  Q <= data(15);
  data_0 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => D1_21924,
      Q => data(0)
    );
  data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_0_1_21926,
      Q => data(1)
    );
  data_2 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_1_1_21932,
      Q => data(2)
    );
  data_3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_2_1_21933,
      Q => data(3)
    );
  data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_3_1_21934,
      Q => data(4)
    );
  data_5 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_4_1_21935,
      Q => data(5)
    );
  data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_5_1_21936,
      Q => data(6)
    );
  data_7 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_6_1_21937,
      Q => data(7)
    );
  data_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_7_1_21938,
      Q => data(8)
    );
  data_9 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_8_1_21939,
      Q => data(9)
    );
  data_10 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_9_1_21940,
      Q => data(10)
    );
  data_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_10_1_21927,
      Q => data(11)
    );
  data_12 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_11_1_21928,
      Q => data(12)
    );
  data_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_12_1_21929,
      Q => data(13)
    );
  data_14 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_13_1_21930,
      Q => data(14)
    );
  data_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_14_1_21931,
      Q => data(15)
    );
  data_9_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(9),
      O => data_9_1_21940
    );
  data_8_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(8),
      O => data_8_1_21939
    );
  data_7_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(7),
      I1 => RST_N,
      O => data_7_1_21938
    );
  data_6_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(6),
      O => data_6_1_21937
    );
  data_5_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(5),
      I1 => RST_N,
      O => data_5_1_21936
    );
  data_4_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(4),
      O => data_4_1_21935
    );
  data_3_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(3),
      I1 => RST_N,
      O => data_3_1_21934
    );
  data_2_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(2),
      O => data_2_1_21933
    );
  data_1_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(1),
      O => data_1_1_21932
    );
  data_14_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(14),
      I1 => RST_N,
      O => data_14_1_21931
    );
  data_13_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(13),
      O => data_13_1_21930
    );
  data_12_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(12),
      I1 => RST_N,
      O => data_12_1_21929
    );
  data_11_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(11),
      O => data_11_1_21928
    );
  data_10_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(10),
      I1 => RST_N,
      O => data_10_1_21927
    );
  data_0_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(0),
      I1 => RST_N,
      O => data_0_1_21926
    );
  D1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => D,
      O => D1_21924
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_3 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_3;

architecture STRUCTURE of my_SRL16E_3 is
  signal D1_21889 : STD_LOGIC; 
  signal data_0_1_21891 : STD_LOGIC; 
  signal data_10_1_21892 : STD_LOGIC; 
  signal data_11_1_21893 : STD_LOGIC; 
  signal data_12_1_21894 : STD_LOGIC; 
  signal data_13_1_21895 : STD_LOGIC; 
  signal data_14_1_21896 : STD_LOGIC; 
  signal data_1_1_21897 : STD_LOGIC; 
  signal data_2_1_21898 : STD_LOGIC; 
  signal data_3_1_21899 : STD_LOGIC; 
  signal data_4_1_21900 : STD_LOGIC; 
  signal data_5_1_21901 : STD_LOGIC; 
  signal data_6_1_21902 : STD_LOGIC; 
  signal data_7_1_21903 : STD_LOGIC; 
  signal data_8_1_21904 : STD_LOGIC; 
  signal data_9_1_21905 : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  Q <= data(15);
  data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => D1_21889,
      Q => data(0)
    );
  data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_0_1_21891,
      Q => data(1)
    );
  data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_1_1_21897,
      Q => data(2)
    );
  data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_2_1_21898,
      Q => data(3)
    );
  data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_3_1_21899,
      Q => data(4)
    );
  data_5 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_4_1_21900,
      Q => data(5)
    );
  data_6 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_5_1_21901,
      Q => data(6)
    );
  data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_6_1_21902,
      Q => data(7)
    );
  data_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_7_1_21903,
      Q => data(8)
    );
  data_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_8_1_21904,
      Q => data(9)
    );
  data_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_9_1_21905,
      Q => data(10)
    );
  data_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_10_1_21892,
      Q => data(11)
    );
  data_12 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_11_1_21893,
      Q => data(12)
    );
  data_13 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_12_1_21894,
      Q => data(13)
    );
  data_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_13_1_21895,
      Q => data(14)
    );
  data_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_14_1_21896,
      Q => data(15)
    );
  data_9_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(9),
      I1 => RST_N,
      O => data_9_1_21905
    );
  data_8_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(8),
      I1 => RST_N,
      O => data_8_1_21904
    );
  data_7_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(7),
      I1 => RST_N,
      O => data_7_1_21903
    );
  data_6_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(6),
      I1 => RST_N,
      O => data_6_1_21902
    );
  data_5_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(5),
      O => data_5_1_21901
    );
  data_4_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(4),
      O => data_4_1_21900
    );
  data_3_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(3),
      I1 => RST_N,
      O => data_3_1_21899
    );
  data_2_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(2),
      I1 => RST_N,
      O => data_2_1_21898
    );
  data_1_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(1),
      I1 => RST_N,
      O => data_1_1_21897
    );
  data_14_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(14),
      I1 => RST_N,
      O => data_14_1_21896
    );
  data_13_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(13),
      I1 => RST_N,
      O => data_13_1_21895
    );
  data_12_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(12),
      O => data_12_1_21894
    );
  data_11_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(11),
      O => data_11_1_21893
    );
  data_10_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(10),
      I1 => RST_N,
      O => data_10_1_21892
    );
  data_0_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(0),
      I1 => RST_N,
      O => data_0_1_21891
    );
  D1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => D,
      I1 => RST_N,
      O => D1_21889
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_2 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_2;

architecture STRUCTURE of my_SRL16E_2 is
  signal D1_21854 : STD_LOGIC; 
  signal data_0_1_21856 : STD_LOGIC; 
  signal data_10_1_21857 : STD_LOGIC; 
  signal data_11_1_21858 : STD_LOGIC; 
  signal data_12_1_21859 : STD_LOGIC; 
  signal data_13_1_21860 : STD_LOGIC; 
  signal data_14_1_21861 : STD_LOGIC; 
  signal data_1_1_21862 : STD_LOGIC; 
  signal data_2_1_21863 : STD_LOGIC; 
  signal data_3_1_21864 : STD_LOGIC; 
  signal data_4_1_21865 : STD_LOGIC; 
  signal data_5_1_21866 : STD_LOGIC; 
  signal data_6_1_21867 : STD_LOGIC; 
  signal data_7_1_21868 : STD_LOGIC; 
  signal data_8_1_21869 : STD_LOGIC; 
  signal data_9_1_21870 : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  Q <= data(15);
  data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => D1_21854,
      Q => data(0)
    );
  data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_0_1_21856,
      Q => data(1)
    );
  data_2 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_1_1_21862,
      Q => data(2)
    );
  data_3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_2_1_21863,
      Q => data(3)
    );
  data_4 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_3_1_21864,
      Q => data(4)
    );
  data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_4_1_21865,
      Q => data(5)
    );
  data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_5_1_21866,
      Q => data(6)
    );
  data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_6_1_21867,
      Q => data(7)
    );
  data_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_7_1_21868,
      Q => data(8)
    );
  data_9 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_8_1_21869,
      Q => data(9)
    );
  data_10 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_9_1_21870,
      Q => data(10)
    );
  data_11 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_10_1_21857,
      Q => data(11)
    );
  data_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_11_1_21858,
      Q => data(12)
    );
  data_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_12_1_21859,
      Q => data(13)
    );
  data_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_13_1_21860,
      Q => data(14)
    );
  data_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_14_1_21861,
      Q => data(15)
    );
  data_9_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(9),
      O => data_9_1_21870
    );
  data_8_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(8),
      O => data_8_1_21869
    );
  data_7_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(7),
      I1 => RST_N,
      O => data_7_1_21868
    );
  data_6_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(6),
      I1 => RST_N,
      O => data_6_1_21867
    );
  data_5_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(5),
      I1 => RST_N,
      O => data_5_1_21866
    );
  data_4_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(4),
      I1 => RST_N,
      O => data_4_1_21865
    );
  data_3_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(3),
      O => data_3_1_21864
    );
  data_2_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(2),
      O => data_2_1_21863
    );
  data_1_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(1),
      O => data_1_1_21862
    );
  data_14_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(14),
      I1 => RST_N,
      O => data_14_1_21861
    );
  data_13_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(13),
      I1 => RST_N,
      O => data_13_1_21860
    );
  data_12_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(12),
      I1 => RST_N,
      O => data_12_1_21859
    );
  data_11_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(11),
      I1 => RST_N,
      O => data_11_1_21858
    );
  data_10_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(10),
      O => data_10_1_21857
    );
  data_0_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(0),
      I1 => RST_N,
      O => data_0_1_21856
    );
  D1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => D,
      I1 => RST_N,
      O => D1_21854
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity my_SRL16E_1 is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST_N : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC := 'X'; 
    Q : out STD_LOGIC; 
    A0 : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A2 : in STD_LOGIC := 'X'; 
    A3 : in STD_LOGIC := 'X' 
  );
end my_SRL16E_1;

architecture STRUCTURE of my_SRL16E_1 is
  signal D1_21819 : STD_LOGIC; 
  signal data_0_1_21821 : STD_LOGIC; 
  signal data_10_1_21822 : STD_LOGIC; 
  signal data_11_1_21823 : STD_LOGIC; 
  signal data_12_1_21824 : STD_LOGIC; 
  signal data_13_1_21825 : STD_LOGIC; 
  signal data_14_1_21826 : STD_LOGIC; 
  signal data_1_1_21827 : STD_LOGIC; 
  signal data_2_1_21828 : STD_LOGIC; 
  signal data_3_1_21829 : STD_LOGIC; 
  signal data_4_1_21830 : STD_LOGIC; 
  signal data_5_1_21831 : STD_LOGIC; 
  signal data_6_1_21832 : STD_LOGIC; 
  signal data_7_1_21833 : STD_LOGIC; 
  signal data_8_1_21834 : STD_LOGIC; 
  signal data_9_1_21835 : STD_LOGIC; 
  signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  Q <= data(15);
  data_0 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => D1_21819,
      Q => data(0)
    );
  data_1 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_0_1_21821,
      Q => data(1)
    );
  data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_1_1_21827,
      Q => data(2)
    );
  data_3 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_2_1_21828,
      Q => data(3)
    );
  data_4 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_3_1_21829,
      Q => data(4)
    );
  data_5 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_4_1_21830,
      Q => data(5)
    );
  data_6 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_5_1_21831,
      Q => data(6)
    );
  data_7 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_6_1_21832,
      Q => data(7)
    );
  data_8 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_7_1_21833,
      Q => data(8)
    );
  data_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => CLK,
      D => data_8_1_21834,
      Q => data(9)
    );
  data_10 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_9_1_21835,
      Q => data(10)
    );
  data_11 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_10_1_21822,
      Q => data(11)
    );
  data_12 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_11_1_21823,
      Q => data(12)
    );
  data_13 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_12_1_21824,
      Q => data(13)
    );
  data_14 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_13_1_21825,
      Q => data(14)
    );
  data_15 : FD
    generic map(
      INIT => '1'
    )
    port map (
      C => CLK,
      D => data_14_1_21826,
      Q => data(15)
    );
  data_9_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(9),
      O => data_9_1_21835
    );
  data_8_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(8),
      I1 => RST_N,
      O => data_8_1_21834
    );
  data_7_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(7),
      O => data_7_1_21833
    );
  data_6_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(6),
      O => data_6_1_21832
    );
  data_5_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(5),
      O => data_5_1_21831
    );
  data_4_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(4),
      O => data_4_1_21830
    );
  data_3_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(3),
      O => data_3_1_21829
    );
  data_2_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(2),
      O => data_2_1_21828
    );
  data_1_1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data(1),
      I1 => RST_N,
      O => data_1_1_21827
    );
  data_14_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(14),
      O => data_14_1_21826
    );
  data_13_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(13),
      O => data_13_1_21825
    );
  data_12_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(12),
      O => data_12_1_21824
    );
  data_11_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(11),
      O => data_11_1_21823
    );
  data_10_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(10),
      O => data_10_1_21822
    );
  data_0_1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => data(0),
      O => data_0_1_21821
    );
  D1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => RST_N,
      I1 => D,
      O => D1_21819
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll_credit is
  port (
    clear_cpl_count : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    trn_pfc_cplh_cl_upd : out STD_LOGIC; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    npd_credit_limited : out STD_LOGIC; 
    pd_credit_limited : out STD_LOGIC; 
    cd_credit_limited : out STD_LOGIC; 
    rx_ch_credits_received_inc : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    tx_pd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_pfc_cplh_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_npd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_npd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_ch_credits_consumed : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rx_ch_credits_received : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_cd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_pfc_cpld_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_pfc_ph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_npd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_pfc_nph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_cd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    mgmt_stats_credit_sel : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_pfc_pd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    tx_pd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    mgmt_stats_credit : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end pcie_blk_ll_credit;

architecture STRUCTURE of pcie_blk_ll_credit is
  component my_SRL16E_1
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_2
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_3
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_4
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_5
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_6
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_7
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_8
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_9
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_10
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_11
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_12
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_13
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_14
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_15
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_16
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  component my_SRL16E_17
    port (
      CLK : in STD_LOGIC := 'X'; 
      RST_N : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC := 'X'; 
      Q : out STD_LOGIC; 
      A0 : in STD_LOGIC := 'X'; 
      A1 : in STD_LOGIC := 'X'; 
      A2 : in STD_LOGIC := 'X'; 
      A3 : in STD_LOGIC := 'X' 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal Result_0_2 : STD_LOGIC; 
  signal Result_1_2 : STD_LOGIC; 
  signal Result_2_2 : STD_LOGIC; 
  signal Result_3_2 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Q_and0000 : STD_LOGIC; 
  signal Q_and0001 : STD_LOGIC; 
  signal cal_enable_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_cd_credit_limited : STD_LOGIC; 
  signal cd_credit_limited_and0000 : STD_LOGIC; 
  signal cd_credit_limited_cmp_lt0000 : STD_LOGIC; 
  signal cd_credit_limited_cmp_lt00002209_SW0 : STD_LOGIC; 
  signal cd_credit_limited_cmp_lt00002209_SW01_22376 : STD_LOGIC; 
  signal cd_credit_limited_cmp_lt0000233_22377 : STD_LOGIC; 
  signal cd_credit_limited_cmp_lt0000292_22378 : STD_LOGIC; 
  signal cd_credit_limited_upd_22379 : STD_LOGIC; 
  signal initial_header_read_22381 : STD_LOGIC; 
  signal initial_header_read_cntr_cmp_lt0000 : STD_LOGIC; 
  signal initial_header_read_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_5_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_stats_credit_sel_6_Q : STD_LOGIC; 
  signal mgmt_stats_credit_sel_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pd_credit_limited : STD_LOGIC; 
  signal pd_credit_limited_and0000 : STD_LOGIC; 
  signal pd_credit_limited_cmp_lt0000 : STD_LOGIC; 
  signal pd_credit_limited_cmp_lt00002209_SW0 : STD_LOGIC; 
  signal pd_credit_limited_cmp_lt00002209_SW01_22434 : STD_LOGIC; 
  signal pd_credit_limited_cmp_lt0000233_22435 : STD_LOGIC; 
  signal pd_credit_limited_cmp_lt0000292_22436 : STD_LOGIC; 
  signal pd_credit_limited_upd_22437 : STD_LOGIC; 
  signal rst_n_inv : STD_LOGIC; 
  signal service_rxrcd_ch_22444 : STD_LOGIC; 
  signal service_rxrcd_ch_cmp_eq0000 : STD_LOGIC; 
  signal service_txcon_ch_22446 : STD_LOGIC; 
  signal service_txcon_ch_cmp_eq0000 : STD_LOGIC; 
  signal service_txcon_pd_22448 : STD_LOGIC; 
  signal service_txcon_pd_cmp_eq0000 : STD_LOGIC; 
  signal service_txcon_pd_d_22450 : STD_LOGIC; 
  signal service_txlim_cd_22451 : STD_LOGIC; 
  signal service_txlim_cd_cmp_eq0000 : STD_LOGIC; 
  signal service_txlim_cd_d_22453 : STD_LOGIC; 
  signal service_txlim_ch_22454 : STD_LOGIC; 
  signal service_txlim_ch_cmp_eq0000 : STD_LOGIC; 
  signal service_txlim_ch_d_22456 : STD_LOGIC; 
  signal service_txlim_pd_22457 : STD_LOGIC; 
  signal service_txlim_pd_cmp_eq0000 : STD_LOGIC; 
  signal service_txlim_pd_d_22459 : STD_LOGIC; 
  signal service_txlim_ph_22460 : STD_LOGIC; 
  signal service_txlim_ph_cmp_eq0000 : STD_LOGIC; 
  signal service_txlim_ph_d_22462 : STD_LOGIC; 
  signal trn_pfc_cpld_cl_upd_22472 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_pfc_cplh_cl_upd : STD_LOGIC; 
  signal trn_pfc_pd_cl_cmp_eq000035_22494 : STD_LOGIC; 
  signal trn_pfc_pd_cl_cmp_eq000071_22495 : STD_LOGIC; 
  signal trn_pfc_pd_cl_upd_22508 : STD_LOGIC; 
  signal trn_pfc_ph_cl_upd_22517 : STD_LOGIC; 
  signal Msub_tx_pd_credits_available_sub0000_cy : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal Msub_tx_pd_credits_available_sub0000_lut : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cal_addr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cal_seq_init_out : STD_LOGIC_VECTOR ( 5 downto 2 ); 
  signal cal_seq_out : STD_LOGIC_VECTOR ( 7 downto 2 ); 
  signal cal_sub_seq_out : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal cal_tag_out : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal initial_header_read_cntr : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal mgmt_stats_credit_d : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal mgmt_stats_credit_sel_d : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal mgmt_stats_credit_sel_mux0000 : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal NlwRenamedSig_OI_trn_pfc_cpld_cl : STD_LOGIC_VECTOR ( 11 downto 4 ); 
  signal NlwRenamedSig_OI_trn_pfc_cplh_cl : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_trn_pfc_pd_cl : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal trn_pfc_pd_cl_mux0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal NlwRenamedSig_OI_trn_pfc_ph_cl : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal tx_pd_credits_available_sub0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
begin
  trn_pfc_cplh_cl_upd <= NlwRenamedSig_OI_trn_pfc_cplh_cl_upd;
  pd_credit_limited <= NlwRenamedSig_OI_pd_credit_limited;
  cd_credit_limited <= NlwRenamedSig_OI_cd_credit_limited;
  trn_pfc_cplh_cl(7) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(7);
  trn_pfc_cplh_cl(6) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(6);
  trn_pfc_cplh_cl(5) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(5);
  trn_pfc_cplh_cl(4) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(4);
  trn_pfc_cplh_cl(3) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(3);
  trn_pfc_cplh_cl(2) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(2);
  trn_pfc_cplh_cl(1) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(1);
  trn_pfc_cplh_cl(0) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(0);
  tx_npd_credits_consumed(11) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(10) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(9) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(8) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(7) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_consumed(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(7) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cplh_av(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_pfc_cpld_cl(11) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(11);
  trn_pfc_cpld_cl(10) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(10);
  trn_pfc_cpld_cl(9) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(9);
  trn_pfc_cpld_cl(8) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(8);
  trn_pfc_cpld_cl(7) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(7);
  trn_pfc_cpld_cl(6) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(6);
  trn_pfc_cpld_cl(5) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(5);
  trn_pfc_cpld_cl(4) <= NlwRenamedSig_OI_trn_pfc_cpld_cl(4);
  trn_pfc_ph_cl(7) <= NlwRenamedSig_OI_trn_pfc_ph_cl(7);
  trn_pfc_ph_cl(6) <= NlwRenamedSig_OI_trn_pfc_ph_cl(6);
  trn_pfc_ph_cl(5) <= NlwRenamedSig_OI_trn_pfc_ph_cl(5);
  trn_pfc_ph_cl(4) <= NlwRenamedSig_OI_trn_pfc_ph_cl(4);
  trn_pfc_ph_cl(3) <= NlwRenamedSig_OI_trn_pfc_ph_cl(3);
  trn_pfc_ph_cl(2) <= NlwRenamedSig_OI_trn_pfc_ph_cl(2);
  trn_pfc_ph_cl(1) <= NlwRenamedSig_OI_trn_pfc_ph_cl(1);
  trn_pfc_ph_cl(0) <= NlwRenamedSig_OI_trn_pfc_ph_cl(0);
  tx_npd_credits_available(11) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(10) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(9) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(8) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(7) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  tx_npd_credits_available(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(11) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(10) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(9) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(8) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(7) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_cpld_av(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(11) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(10) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(9) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(8) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(7) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_rfc_npd_av(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  mgmt_stats_credit_sel(6) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_6_Q;
  mgmt_stats_credit_sel(5) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_5_Q;
  mgmt_stats_credit_sel(4) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_4_Q;
  mgmt_stats_credit_sel(3) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_3_Q;
  mgmt_stats_credit_sel(2) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_2_Q;
  mgmt_stats_credit_sel(1) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  mgmt_stats_credit_sel(0) <= NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q;
  trn_pfc_pd_cl(11) <= NlwRenamedSig_OI_trn_pfc_pd_cl(11);
  trn_pfc_pd_cl(10) <= NlwRenamedSig_OI_trn_pfc_pd_cl(10);
  trn_pfc_pd_cl(9) <= NlwRenamedSig_OI_trn_pfc_pd_cl(9);
  trn_pfc_pd_cl(8) <= NlwRenamedSig_OI_trn_pfc_pd_cl(8);
  trn_pfc_pd_cl(7) <= NlwRenamedSig_OI_trn_pfc_pd_cl(7);
  trn_pfc_pd_cl(6) <= NlwRenamedSig_OI_trn_pfc_pd_cl(6);
  trn_pfc_pd_cl(5) <= NlwRenamedSig_OI_trn_pfc_pd_cl(5);
  trn_pfc_pd_cl(4) <= NlwRenamedSig_OI_trn_pfc_pd_cl(4);
  trn_pfc_pd_cl(3) <= NlwRenamedSig_OI_trn_pfc_pd_cl(3);
  trn_pfc_pd_cl(2) <= NlwRenamedSig_OI_trn_pfc_pd_cl(2);
  trn_pfc_pd_cl(1) <= NlwRenamedSig_OI_trn_pfc_pd_cl(1);
  trn_pfc_pd_cl(0) <= NlwRenamedSig_OI_trn_pfc_pd_cl(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  initial_header_read : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      S => initial_header_read_or0000,
      Q => initial_header_read_22381
    );
  mgmt_stats_credit_sel_2 : FDR
    port map (
      C => clk,
      D => mgmt_stats_credit_sel_mux0000(2),
      R => mgmt_stats_credit_sel_or0000,
      Q => NlwRenamedSig_OI_mgmt_stats_credit_sel_2_Q
    );
  mgmt_stats_credit_sel_3 : FDR
    port map (
      C => clk,
      D => mgmt_stats_credit_sel_mux0000(3),
      R => mgmt_stats_credit_sel_or0000,
      Q => NlwRenamedSig_OI_mgmt_stats_credit_sel_3_Q
    );
  mgmt_stats_credit_sel_4 : FDR
    port map (
      C => clk,
      D => mgmt_stats_credit_sel_mux0000(4),
      R => mgmt_stats_credit_sel_or0000,
      Q => NlwRenamedSig_OI_mgmt_stats_credit_sel_4_Q
    );
  mgmt_stats_credit_sel_5 : FDR
    port map (
      C => clk,
      D => mgmt_stats_credit_sel_mux0000(5),
      R => mgmt_stats_credit_sel_or0000,
      Q => NlwRenamedSig_OI_mgmt_stats_credit_sel_5_Q
    );
  mgmt_stats_credit_sel_6 : FDR
    port map (
      C => clk,
      D => mgmt_stats_credit_sel_mux0000(6),
      R => mgmt_stats_credit_sel_or0000,
      Q => NlwRenamedSig_OI_mgmt_stats_credit_sel_6_Q
    );
  service_rxrcd_ch : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_rxrcd_ch_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_rxrcd_ch_22444
    );
  service_txcon_ch : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txcon_ch_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txcon_ch_22446
    );
  service_txcon_pd : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txcon_pd_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txcon_pd_22448
    );
  service_txlim_ch : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_ch_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txlim_ch_22454
    );
  service_txlim_ph : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_ph_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txlim_ph_22460
    );
  service_txlim_cd : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_cd_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txlim_cd_22451
    );
  service_txlim_pd : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_pd_cmp_eq0000,
      R => mgmt_stats_credit_sel_or0000,
      Q => service_txlim_pd_22457
    );
  mgmt_stats_credit_d_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(0),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(0)
    );
  mgmt_stats_credit_d_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(1),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(1)
    );
  mgmt_stats_credit_d_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(2),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(2)
    );
  mgmt_stats_credit_d_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(3),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(3)
    );
  mgmt_stats_credit_d_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(4),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(4)
    );
  mgmt_stats_credit_d_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(5),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(5)
    );
  mgmt_stats_credit_d_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(6),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(6)
    );
  mgmt_stats_credit_d_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(7),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(7)
    );
  mgmt_stats_credit_d_8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(8),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(8)
    );
  mgmt_stats_credit_d_9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(9),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(9)
    );
  mgmt_stats_credit_d_10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(10),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(10)
    );
  mgmt_stats_credit_d_11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => mgmt_stats_credit(11),
      R => rst_n_inv,
      Q => mgmt_stats_credit_d(11)
    );
  pd_credit_limited_upd : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => pd_credit_limited_and0000,
      D => N1,
      R => rst_n_inv,
      Q => pd_credit_limited_upd_22437
    );
  cd_credit_limited_upd : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => cd_credit_limited_and0000,
      D => N1,
      R => rst_n_inv,
      Q => cd_credit_limited_upd_22379
    );
  mgmt_stats_credit_sel_d_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_2_Q,
      R => mgmt_stats_credit_sel_or0000,
      Q => mgmt_stats_credit_sel_d(2)
    );
  mgmt_stats_credit_sel_d_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_3_Q,
      R => mgmt_stats_credit_sel_or0000,
      Q => mgmt_stats_credit_sel_d(3)
    );
  mgmt_stats_credit_sel_d_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_4_Q,
      R => mgmt_stats_credit_sel_or0000,
      Q => mgmt_stats_credit_sel_d(4)
    );
  mgmt_stats_credit_sel_d_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_5_Q,
      R => mgmt_stats_credit_sel_or0000,
      Q => mgmt_stats_credit_sel_d(5)
    );
  mgmt_stats_credit_sel_d_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => NlwRenamedSig_OI_mgmt_stats_credit_sel_6_Q,
      R => mgmt_stats_credit_sel_or0000,
      Q => mgmt_stats_credit_sel_d(6)
    );
  tx_ch_credits_consumed_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_ch_22446,
      D => mgmt_stats_credit(0),
      R => rst_n_inv,
      Q => tx_ch_credits_consumed(0)
    );
  tx_ch_credits_consumed_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_ch_22446,
      D => mgmt_stats_credit(1),
      R => rst_n_inv,
      Q => tx_ch_credits_consumed(1)
    );
  tx_ch_credits_consumed_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_ch_22446,
      D => mgmt_stats_credit(2),
      R => rst_n_inv,
      Q => tx_ch_credits_consumed(2)
    );
  tx_ch_credits_consumed_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_ch_22446,
      D => mgmt_stats_credit(3),
      R => rst_n_inv,
      Q => tx_ch_credits_consumed(3)
    );
  tx_ch_credits_consumed_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_ch_22446,
      D => mgmt_stats_credit(4),
      R => rst_n_inv,
      Q => tx_ch_credits_consumed(4)
    );
  rx_ch_credits_received_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_rxrcd_ch_22444,
      D => mgmt_stats_credit(0),
      R => rst_n_inv,
      Q => rx_ch_credits_received(0)
    );
  rx_ch_credits_received_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_rxrcd_ch_22444,
      D => mgmt_stats_credit(1),
      R => rst_n_inv,
      Q => rx_ch_credits_received(1)
    );
  rx_ch_credits_received_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_rxrcd_ch_22444,
      D => mgmt_stats_credit(2),
      R => rst_n_inv,
      Q => rx_ch_credits_received(2)
    );
  rx_ch_credits_received_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_rxrcd_ch_22444,
      D => mgmt_stats_credit(3),
      R => rst_n_inv,
      Q => rx_ch_credits_received(3)
    );
  service_txcon_pd_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txcon_pd_22448,
      R => rst_n_inv,
      Q => service_txcon_pd_d_22450
    );
  service_txlim_ch_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_ch_22454,
      R => rst_n_inv,
      Q => service_txlim_ch_d_22456
    );
  service_txlim_ph_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_ph_22460,
      R => rst_n_inv,
      Q => service_txlim_ph_d_22462
    );
  service_txlim_cd_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_cd_22451,
      R => rst_n_inv,
      Q => service_txlim_cd_d_22453
    );
  service_txlim_pd_d : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => service_txlim_pd_22457,
      R => rst_n_inv,
      Q => service_txlim_pd_d_22459
    );
  tx_pd_credits_consumed_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(0),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(0)
    );
  tx_pd_credits_consumed_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(1),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(1)
    );
  tx_pd_credits_consumed_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(2),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(2)
    );
  tx_pd_credits_consumed_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(3),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(3)
    );
  tx_pd_credits_consumed_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(4),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(4)
    );
  tx_pd_credits_consumed_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(5),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(5)
    );
  tx_pd_credits_consumed_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(6),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(6)
    );
  tx_pd_credits_consumed_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(7),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(7)
    );
  tx_pd_credits_consumed_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(8),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(8)
    );
  tx_pd_credits_consumed_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(9),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(9)
    );
  tx_pd_credits_consumed_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(10),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(10)
    );
  tx_pd_credits_consumed_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => mgmt_stats_credit_d(11),
      R => rst_n_inv,
      Q => tx_pd_credits_consumed(11)
    );
  trn_pfc_cplh_cl_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(0),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(0)
    );
  trn_pfc_cplh_cl_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(1),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(1)
    );
  trn_pfc_cplh_cl_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(2),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(2)
    );
  trn_pfc_cplh_cl_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(3),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(3)
    );
  trn_pfc_cplh_cl_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(4),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(4)
    );
  trn_pfc_cplh_cl_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(5),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(5)
    );
  trn_pfc_cplh_cl_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(6),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(6)
    );
  trn_pfc_cplh_cl_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => mgmt_stats_credit_d(7),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl(7)
    );
  trn_pfc_ph_cl_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(0),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(0)
    );
  trn_pfc_ph_cl_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(1),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(1)
    );
  trn_pfc_ph_cl_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(2),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(2)
    );
  trn_pfc_ph_cl_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(3),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(3)
    );
  trn_pfc_ph_cl_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(4),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(4)
    );
  trn_pfc_ph_cl_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(5),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(5)
    );
  trn_pfc_ph_cl_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(6),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(6)
    );
  trn_pfc_ph_cl_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => mgmt_stats_credit_d(7),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_ph_cl(7)
    );
  trn_pfc_pd_cl_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(11),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(0)
    );
  trn_pfc_pd_cl_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(10),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(1)
    );
  trn_pfc_pd_cl_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(9),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(2)
    );
  trn_pfc_pd_cl_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(8),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(3)
    );
  trn_pfc_pd_cl_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(7),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(4)
    );
  trn_pfc_pd_cl_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(6),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(5)
    );
  trn_pfc_pd_cl_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(5),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(6)
    );
  trn_pfc_pd_cl_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(4),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(7)
    );
  trn_pfc_pd_cl_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(3),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(8)
    );
  trn_pfc_pd_cl_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(2),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(9)
    );
  trn_pfc_pd_cl_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(1),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(10)
    );
  trn_pfc_pd_cl_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => trn_pfc_pd_cl_mux0000(0),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_pd_cl(11)
    );
  trn_pfc_cpld_cl_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(4),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(4)
    );
  trn_pfc_cpld_cl_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(5),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(5)
    );
  trn_pfc_cpld_cl_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(6),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(6)
    );
  trn_pfc_cpld_cl_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(7),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(7)
    );
  trn_pfc_cpld_cl_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(8),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(8)
    );
  trn_pfc_cpld_cl_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(9),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(9)
    );
  trn_pfc_cpld_cl_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(10),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(10)
    );
  trn_pfc_cpld_cl_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => mgmt_stats_credit_d(11),
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cpld_cl(11)
    );
  trn_pfc_ph_cl_upd : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ph_d_22462,
      D => N1,
      R => rst_n_inv,
      Q => trn_pfc_ph_cl_upd_22517
    );
  trn_pfc_pd_cl_upd : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_pd_d_22459,
      D => N1,
      R => rst_n_inv,
      Q => trn_pfc_pd_cl_upd_22508
    );
  trn_pfc_cplh_cl_upd_11559 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_ch_d_22456,
      D => N1,
      R => rst_n_inv,
      Q => NlwRenamedSig_OI_trn_pfc_cplh_cl_upd
    );
  trn_pfc_cpld_cl_upd : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txlim_cd_d_22453,
      D => N1,
      R => rst_n_inv,
      Q => trn_pfc_cpld_cl_upd_22472
    );
  tx_pd_credits_available_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(0),
      R => rst_n_inv,
      Q => tx_pd_credits_available(0)
    );
  tx_pd_credits_available_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(1),
      R => rst_n_inv,
      Q => tx_pd_credits_available(1)
    );
  tx_pd_credits_available_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(2),
      R => rst_n_inv,
      Q => tx_pd_credits_available(2)
    );
  tx_pd_credits_available_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(3),
      R => rst_n_inv,
      Q => tx_pd_credits_available(3)
    );
  tx_pd_credits_available_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(4),
      R => rst_n_inv,
      Q => tx_pd_credits_available(4)
    );
  tx_pd_credits_available_5 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(5),
      R => rst_n_inv,
      Q => tx_pd_credits_available(5)
    );
  tx_pd_credits_available_6 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(6),
      R => rst_n_inv,
      Q => tx_pd_credits_available(6)
    );
  tx_pd_credits_available_7 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(7),
      R => rst_n_inv,
      Q => tx_pd_credits_available(7)
    );
  tx_pd_credits_available_8 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(8),
      R => rst_n_inv,
      Q => tx_pd_credits_available(8)
    );
  tx_pd_credits_available_9 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(9),
      R => rst_n_inv,
      Q => tx_pd_credits_available(9)
    );
  tx_pd_credits_available_10 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(10),
      R => rst_n_inv,
      Q => tx_pd_credits_available(10)
    );
  tx_pd_credits_available_11 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => service_txcon_pd_d_22450,
      D => tx_pd_credits_available_sub0000(11),
      R => rst_n_inv,
      Q => tx_pd_credits_available(11)
    );
  pd_credit_limited_11573 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => pd_credit_limited_and0000,
      D => pd_credit_limited_cmp_lt0000,
      S => rst_n_inv,
      Q => NlwRenamedSig_OI_pd_credit_limited
    );
  cd_credit_limited_11574 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cd_credit_limited_and0000,
      D => cd_credit_limited_cmp_lt0000,
      S => rst_n_inv,
      Q => NlwRenamedSig_OI_cd_credit_limited
    );
  cal_addr_0 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cal_enable_inv,
      D => Result(0),
      S => rst_n_inv,
      Q => cal_addr(0)
    );
  cal_addr_1 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cal_enable_inv,
      D => Result(1),
      S => rst_n_inv,
      Q => cal_addr(1)
    );
  cal_addr_2 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cal_enable_inv,
      D => Result(2),
      S => rst_n_inv,
      Q => cal_addr(2)
    );
  cal_addr_3 : FDSE
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      CE => cal_enable_inv,
      D => Result(3),
      S => rst_n_inv,
      Q => cal_addr(3)
    );
  initial_header_read_cntr_0 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => initial_header_read_cntr_cmp_lt0000,
      D => Result_0_2,
      R => rst_n_inv,
      Q => initial_header_read_cntr(0)
    );
  initial_header_read_cntr_1 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => initial_header_read_cntr_cmp_lt0000,
      D => Result_1_2,
      R => rst_n_inv,
      Q => initial_header_read_cntr(1)
    );
  initial_header_read_cntr_2 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => initial_header_read_cntr_cmp_lt0000,
      D => Result_2_2,
      R => rst_n_inv,
      Q => initial_header_read_cntr(2)
    );
  initial_header_read_cntr_3 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => initial_header_read_cntr_cmp_lt0000,
      D => Result_3_2,
      R => rst_n_inv,
      Q => initial_header_read_cntr(3)
    );
  initial_header_read_cntr_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => initial_header_read_cntr_cmp_lt0000,
      D => Result_4_1,
      R => rst_n_inv,
      Q => initial_header_read_cntr(4)
    );
  Msub_tx_pd_credits_available_sub0000_lut_0_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(0),
      I1 => mgmt_stats_credit_d(0),
      O => Msub_tx_pd_credits_available_sub0000_lut(0)
    );
  Msub_tx_pd_credits_available_sub0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(0),
      S => Msub_tx_pd_credits_available_sub0000_lut(0),
      O => Msub_tx_pd_credits_available_sub0000_cy(0)
    );
  Msub_tx_pd_credits_available_sub0000_xor_0_Q : XORCY
    port map (
      CI => N1,
      LI => Msub_tx_pd_credits_available_sub0000_lut(0),
      O => tx_pd_credits_available_sub0000(0)
    );
  Msub_tx_pd_credits_available_sub0000_lut_1_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(1),
      I1 => mgmt_stats_credit_d(1),
      O => Msub_tx_pd_credits_available_sub0000_lut(1)
    );
  Msub_tx_pd_credits_available_sub0000_cy_1_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(0),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(1),
      S => Msub_tx_pd_credits_available_sub0000_lut(1),
      O => Msub_tx_pd_credits_available_sub0000_cy(1)
    );
  Msub_tx_pd_credits_available_sub0000_xor_1_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(0),
      LI => Msub_tx_pd_credits_available_sub0000_lut(1),
      O => tx_pd_credits_available_sub0000(1)
    );
  Msub_tx_pd_credits_available_sub0000_lut_2_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(2),
      I1 => mgmt_stats_credit_d(2),
      O => Msub_tx_pd_credits_available_sub0000_lut(2)
    );
  Msub_tx_pd_credits_available_sub0000_cy_2_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(1),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(2),
      S => Msub_tx_pd_credits_available_sub0000_lut(2),
      O => Msub_tx_pd_credits_available_sub0000_cy(2)
    );
  Msub_tx_pd_credits_available_sub0000_xor_2_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(1),
      LI => Msub_tx_pd_credits_available_sub0000_lut(2),
      O => tx_pd_credits_available_sub0000(2)
    );
  Msub_tx_pd_credits_available_sub0000_lut_3_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(3),
      I1 => mgmt_stats_credit_d(3),
      O => Msub_tx_pd_credits_available_sub0000_lut(3)
    );
  Msub_tx_pd_credits_available_sub0000_cy_3_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(2),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(3),
      S => Msub_tx_pd_credits_available_sub0000_lut(3),
      O => Msub_tx_pd_credits_available_sub0000_cy(3)
    );
  Msub_tx_pd_credits_available_sub0000_xor_3_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(2),
      LI => Msub_tx_pd_credits_available_sub0000_lut(3),
      O => tx_pd_credits_available_sub0000(3)
    );
  Msub_tx_pd_credits_available_sub0000_lut_4_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(4),
      I1 => mgmt_stats_credit_d(4),
      O => Msub_tx_pd_credits_available_sub0000_lut(4)
    );
  Msub_tx_pd_credits_available_sub0000_cy_4_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(3),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(4),
      S => Msub_tx_pd_credits_available_sub0000_lut(4),
      O => Msub_tx_pd_credits_available_sub0000_cy(4)
    );
  Msub_tx_pd_credits_available_sub0000_xor_4_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(3),
      LI => Msub_tx_pd_credits_available_sub0000_lut(4),
      O => tx_pd_credits_available_sub0000(4)
    );
  Msub_tx_pd_credits_available_sub0000_lut_5_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(5),
      I1 => mgmt_stats_credit_d(5),
      O => Msub_tx_pd_credits_available_sub0000_lut(5)
    );
  Msub_tx_pd_credits_available_sub0000_cy_5_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(4),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(5),
      S => Msub_tx_pd_credits_available_sub0000_lut(5),
      O => Msub_tx_pd_credits_available_sub0000_cy(5)
    );
  Msub_tx_pd_credits_available_sub0000_xor_5_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(4),
      LI => Msub_tx_pd_credits_available_sub0000_lut(5),
      O => tx_pd_credits_available_sub0000(5)
    );
  Msub_tx_pd_credits_available_sub0000_lut_6_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(6),
      I1 => mgmt_stats_credit_d(6),
      O => Msub_tx_pd_credits_available_sub0000_lut(6)
    );
  Msub_tx_pd_credits_available_sub0000_cy_6_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(5),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(6),
      S => Msub_tx_pd_credits_available_sub0000_lut(6),
      O => Msub_tx_pd_credits_available_sub0000_cy(6)
    );
  Msub_tx_pd_credits_available_sub0000_xor_6_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(5),
      LI => Msub_tx_pd_credits_available_sub0000_lut(6),
      O => tx_pd_credits_available_sub0000(6)
    );
  Msub_tx_pd_credits_available_sub0000_lut_7_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(7),
      I1 => mgmt_stats_credit_d(7),
      O => Msub_tx_pd_credits_available_sub0000_lut(7)
    );
  Msub_tx_pd_credits_available_sub0000_cy_7_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(6),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(7),
      S => Msub_tx_pd_credits_available_sub0000_lut(7),
      O => Msub_tx_pd_credits_available_sub0000_cy(7)
    );
  Msub_tx_pd_credits_available_sub0000_xor_7_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(6),
      LI => Msub_tx_pd_credits_available_sub0000_lut(7),
      O => tx_pd_credits_available_sub0000(7)
    );
  Msub_tx_pd_credits_available_sub0000_lut_8_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(8),
      I1 => mgmt_stats_credit_d(8),
      O => Msub_tx_pd_credits_available_sub0000_lut(8)
    );
  Msub_tx_pd_credits_available_sub0000_cy_8_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(7),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(8),
      S => Msub_tx_pd_credits_available_sub0000_lut(8),
      O => Msub_tx_pd_credits_available_sub0000_cy(8)
    );
  Msub_tx_pd_credits_available_sub0000_xor_8_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(7),
      LI => Msub_tx_pd_credits_available_sub0000_lut(8),
      O => tx_pd_credits_available_sub0000(8)
    );
  Msub_tx_pd_credits_available_sub0000_lut_9_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(9),
      I1 => mgmt_stats_credit_d(9),
      O => Msub_tx_pd_credits_available_sub0000_lut(9)
    );
  Msub_tx_pd_credits_available_sub0000_cy_9_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(8),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(9),
      S => Msub_tx_pd_credits_available_sub0000_lut(9),
      O => Msub_tx_pd_credits_available_sub0000_cy(9)
    );
  Msub_tx_pd_credits_available_sub0000_xor_9_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(8),
      LI => Msub_tx_pd_credits_available_sub0000_lut(9),
      O => tx_pd_credits_available_sub0000(9)
    );
  Msub_tx_pd_credits_available_sub0000_lut_10_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(10),
      I1 => mgmt_stats_credit_d(10),
      O => Msub_tx_pd_credits_available_sub0000_lut(10)
    );
  Msub_tx_pd_credits_available_sub0000_cy_10_Q : MUXCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(9),
      DI => NlwRenamedSig_OI_trn_pfc_pd_cl(10),
      S => Msub_tx_pd_credits_available_sub0000_lut(10),
      O => Msub_tx_pd_credits_available_sub0000_cy(10)
    );
  Msub_tx_pd_credits_available_sub0000_xor_10_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(9),
      LI => Msub_tx_pd_credits_available_sub0000_lut(10),
      O => tx_pd_credits_available_sub0000(10)
    );
  Msub_tx_pd_credits_available_sub0000_lut_11_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_pd_cl(11),
      I1 => mgmt_stats_credit_d(11),
      O => Msub_tx_pd_credits_available_sub0000_lut(11)
    );
  Msub_tx_pd_credits_available_sub0000_xor_11_Q : XORCY
    port map (
      CI => Msub_tx_pd_credits_available_sub0000_cy(10),
      LI => Msub_tx_pd_credits_available_sub0000_lut(11),
      O => tx_pd_credits_available_sub0000(11)
    );
  srl_init_cal5 : my_SRL16E_1
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => N1,
      D => cal_seq_init_out(5),
      Q => cal_seq_init_out(5),
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1
    );
  srl_init_cal4 : my_SRL16E_2
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => N1,
      D => cal_seq_init_out(4),
      Q => cal_seq_init_out(4),
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1
    );
  srl_init_cal3 : my_SRL16E_3
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => N1,
      D => cal_seq_init_out(3),
      Q => cal_seq_init_out(3),
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1
    );
  srl_init_cal2 : my_SRL16E_4
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => N1,
      D => cal_seq_init_out(2),
      Q => cal_seq_init_out(2),
      A0 => N1,
      A1 => N1,
      A2 => N1,
      A3 => N1
    );
  srl_gen_0_srl_cal_tag1 : my_SRL16E_5
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_tag_out(1),
      Q => cal_tag_out(1),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal_tag0 : my_SRL16E_6
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_tag_out(0),
      Q => cal_tag_out(0),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal7 : my_SRL16E_7
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(7),
      Q => cal_seq_out(7),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal6 : my_SRL16E_8
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(6),
      Q => cal_seq_out(6),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal5 : my_SRL16E_9
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(5),
      Q => cal_seq_out(5),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal4 : my_SRL16E_10
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(4),
      Q => cal_seq_out(4),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal3 : my_SRL16E_11
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(3),
      Q => cal_seq_out(3),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  srl_gen_0_srl_cal2 : my_SRL16E_12
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0000,
      D => cal_seq_out(2),
      Q => cal_seq_out(2),
      A0 => cal_addr(0),
      A1 => cal_addr(1),
      A2 => cal_addr(2),
      A3 => cal_addr(3)
    );
  sub_srl_gen_0_srl_sub_cal6 : my_SRL16E_13
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0001,
      D => cal_sub_seq_out(6),
      Q => cal_sub_seq_out(6),
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      A3 => N1
    );
  sub_srl_gen_0_srl_sub_cal5 : my_SRL16E_14
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0001,
      D => cal_sub_seq_out(5),
      Q => cal_sub_seq_out(5),
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      A3 => N1
    );
  sub_srl_gen_0_srl_sub_cal4 : my_SRL16E_15
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0001,
      D => cal_sub_seq_out(4),
      Q => cal_sub_seq_out(4),
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      A3 => N1
    );
  sub_srl_gen_0_srl_sub_cal3 : my_SRL16E_16
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0001,
      D => cal_sub_seq_out(3),
      Q => cal_sub_seq_out(3),
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      A3 => N1
    );
  sub_srl_gen_0_srl_sub_cal2 : my_SRL16E_17
    port map (
      CLK => clk,
      RST_N => rst_n,
      CE => Q_and0001,
      D => cal_sub_seq_out(2),
      Q => cal_sub_seq_out(2),
      A0 => N1,
      A1 => N1,
      A2 => NlwRenamedSig_OI_mgmt_stats_credit_sel_0_Q,
      A3 => N1
    );
  Mcount_initial_header_read_cntr_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => initial_header_read_cntr(1),
      I1 => initial_header_read_cntr(0),
      O => Result_1_2
    );
  Mcount_cal_addr_xor_1_11 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cal_addr(1),
      I1 => cal_addr(0),
      O => Result(1)
    );
  Mcount_initial_header_read_cntr_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => initial_header_read_cntr(0),
      I1 => initial_header_read_cntr(2),
      I2 => initial_header_read_cntr(1),
      O => Result_2_2
    );
  Mcount_cal_addr_xor_2_11 : LUT3
    generic map(
      INIT => X"C9"
    )
    port map (
      I0 => cal_addr(1),
      I1 => cal_addr(2),
      I2 => cal_addr(0),
      O => Result(2)
    );
  Mcount_initial_header_read_cntr_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => initial_header_read_cntr(0),
      I1 => initial_header_read_cntr(3),
      I2 => initial_header_read_cntr(1),
      I3 => initial_header_read_cntr(2),
      O => Result_3_2
    );
  Mcount_cal_addr_xor_3_11 : LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      I0 => cal_addr(3),
      I1 => cal_addr(1),
      I2 => cal_addr(2),
      I3 => cal_addr(0),
      O => Result(3)
    );
  service_txlim_ph_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(5),
      I1 => mgmt_stats_credit_sel_d(2),
      I2 => mgmt_stats_credit_sel_d(3),
      I3 => mgmt_stats_credit_sel_d(6),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_txlim_ph_cmp_eq0000
    );
  service_txlim_pd_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(5),
      I1 => mgmt_stats_credit_sel_d(3),
      I2 => mgmt_stats_credit_sel_d(2),
      I3 => mgmt_stats_credit_sel_d(6),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_txlim_pd_cmp_eq0000
    );
  service_txlim_ch_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(3),
      I1 => mgmt_stats_credit_sel_d(5),
      I2 => mgmt_stats_credit_sel_d(2),
      I3 => mgmt_stats_credit_sel_d(6),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_txlim_ch_cmp_eq0000
    );
  service_txlim_cd_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(5),
      I1 => mgmt_stats_credit_sel_d(4),
      I2 => mgmt_stats_credit_sel_d(2),
      I3 => mgmt_stats_credit_sel_d(3),
      I4 => mgmt_stats_credit_sel_d(6),
      O => service_txlim_cd_cmp_eq0000
    );
  service_txcon_pd_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(3),
      I1 => mgmt_stats_credit_sel_d(2),
      I2 => mgmt_stats_credit_sel_d(6),
      I3 => mgmt_stats_credit_sel_d(5),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_txcon_pd_cmp_eq0000
    );
  service_txcon_ch_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(3),
      I1 => mgmt_stats_credit_sel_d(2),
      I2 => mgmt_stats_credit_sel_d(6),
      I3 => mgmt_stats_credit_sel_d(5),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_txcon_ch_cmp_eq0000
    );
  service_rxrcd_ch_cmp_eq00001 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => mgmt_stats_credit_sel_d(5),
      I1 => mgmt_stats_credit_sel_d(3),
      I2 => mgmt_stats_credit_sel_d(6),
      I3 => mgmt_stats_credit_sel_d(2),
      I4 => mgmt_stats_credit_sel_d(4),
      O => service_rxrcd_ch_cmp_eq0000
    );
  Mcount_initial_header_read_cntr_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => initial_header_read_cntr(0),
      I1 => initial_header_read_cntr(4),
      I2 => initial_header_read_cntr(1),
      I3 => initial_header_read_cntr(2),
      I4 => initial_header_read_cntr(3),
      O => Result_4_1
    );
  pd_credit_limited_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => trn_pfc_pd_cl_upd_22508,
      I1 => trn_pfc_ph_cl_upd_22517,
      I2 => pd_credit_limited_upd_22437,
      O => pd_credit_limited_and0000
    );
  cd_credit_limited_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => trn_pfc_cpld_cl_upd_22472,
      I1 => NlwRenamedSig_OI_trn_pfc_cplh_cl_upd,
      I2 => cd_credit_limited_upd_22379,
      O => cd_credit_limited_and0000
    );
  initial_header_read_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => rst_n,
      I1 => initial_header_read_cntr(4),
      O => initial_header_read_or0000
    );
  mgmt_stats_credit_sel_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => rst_n,
      I1 => trn_lnk_up_n,
      O => mgmt_stats_credit_sel_or0000
    );
  trn_pfc_pd_cl_cmp_eq000035 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => mgmt_stats_credit_d(4),
      I1 => mgmt_stats_credit_d(5),
      I2 => mgmt_stats_credit_d(3),
      I3 => mgmt_stats_credit_d(2),
      I4 => mgmt_stats_credit_d(1),
      I5 => mgmt_stats_credit_d(0),
      O => trn_pfc_pd_cl_cmp_eq000035_22494
    );
  trn_pfc_pd_cl_cmp_eq000071 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => mgmt_stats_credit_d(10),
      I1 => mgmt_stats_credit_d(11),
      I2 => mgmt_stats_credit_d(9),
      I3 => mgmt_stats_credit_d(8),
      I4 => mgmt_stats_credit_d(7),
      I5 => mgmt_stats_credit_d(6),
      O => trn_pfc_pd_cl_cmp_eq000071_22495
    );
  mgmt_stats_credit_sel_mux0000_6_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => cal_seq_out(6),
      I2 => initial_header_read_22381,
      I3 => cal_sub_seq_out(6),
      O => mgmt_stats_credit_sel_mux0000(6)
    );
  mgmt_stats_credit_sel_mux0000_5_1 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => initial_header_read_22381,
      I2 => cal_sub_seq_out(5),
      I3 => cal_seq_out(5),
      I4 => cal_seq_init_out(5),
      O => mgmt_stats_credit_sel_mux0000(5)
    );
  mgmt_stats_credit_sel_mux0000_4_1 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => initial_header_read_22381,
      I2 => cal_sub_seq_out(4),
      I3 => cal_seq_out(4),
      I4 => cal_seq_init_out(4),
      O => mgmt_stats_credit_sel_mux0000(4)
    );
  mgmt_stats_credit_sel_mux0000_3_1 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => initial_header_read_22381,
      I2 => cal_sub_seq_out(3),
      I3 => cal_seq_out(3),
      I4 => cal_seq_init_out(3),
      O => mgmt_stats_credit_sel_mux0000(3)
    );
  mgmt_stats_credit_sel_mux0000_2_1 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => initial_header_read_22381,
      I2 => cal_sub_seq_out(2),
      I3 => cal_seq_out(2),
      I4 => cal_seq_init_out(2),
      O => mgmt_stats_credit_sel_mux0000(2)
    );
  Q_and00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => cal_seq_out(7),
      I1 => rst_n,
      O => Q_and0001
    );
  cal_enable_inv1 : LUT4
    generic map(
      INIT => X"028A"
    )
    port map (
      I0 => cal_tag_out(0),
      I1 => cal_tag_out(1),
      I2 => NlwRenamedSig_OI_cd_credit_limited,
      I3 => NlwRenamedSig_OI_pd_credit_limited,
      O => cal_enable_inv
    );
  Q_and00001 : LUT5
    generic map(
      INIT => X"CCC44C44"
    )
    port map (
      I0 => cal_tag_out(0),
      I1 => rst_n,
      I2 => cal_tag_out(1),
      I3 => NlwRenamedSig_OI_cd_credit_limited,
      I4 => NlwRenamedSig_OI_pd_credit_limited,
      O => Q_and0000
    );
  pd_credit_limited_cmp_lt0000233 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_ph_cl(5),
      I1 => NlwRenamedSig_OI_trn_pfc_ph_cl(4),
      I2 => NlwRenamedSig_OI_trn_pfc_pd_cl(8),
      I3 => NlwRenamedSig_OI_trn_pfc_pd_cl(9),
      O => pd_credit_limited_cmp_lt0000233_22435
    );
  pd_credit_limited_cmp_lt0000292 : LUT6
    generic map(
      INIT => X"08088A08AEAEEFAE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_ph_cl(2),
      I1 => NlwRenamedSig_OI_trn_pfc_ph_cl(1),
      I2 => NlwRenamedSig_OI_trn_pfc_pd_cl(5),
      I3 => NlwRenamedSig_OI_trn_pfc_ph_cl(0),
      I4 => NlwRenamedSig_OI_trn_pfc_pd_cl(4),
      I5 => NlwRenamedSig_OI_trn_pfc_pd_cl(6),
      O => pd_credit_limited_cmp_lt0000292_22436
    );
  cd_credit_limited_cmp_lt0000233 : LUT4
    generic map(
      INIT => X"08AE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_cplh_cl(5),
      I1 => NlwRenamedSig_OI_trn_pfc_cplh_cl(4),
      I2 => NlwRenamedSig_OI_trn_pfc_cpld_cl(8),
      I3 => NlwRenamedSig_OI_trn_pfc_cpld_cl(9),
      O => cd_credit_limited_cmp_lt0000233_22377
    );
  cd_credit_limited_cmp_lt0000292 : LUT6
    generic map(
      INIT => X"08088A08AEAEEFAE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_cplh_cl(2),
      I1 => NlwRenamedSig_OI_trn_pfc_cplh_cl(1),
      I2 => NlwRenamedSig_OI_trn_pfc_cpld_cl(5),
      I3 => NlwRenamedSig_OI_trn_pfc_cplh_cl(0),
      I4 => NlwRenamedSig_OI_trn_pfc_cpld_cl(4),
      I5 => NlwRenamedSig_OI_trn_pfc_cpld_cl(6),
      O => cd_credit_limited_cmp_lt0000292_22378
    );
  pd_credit_limited_cmp_lt00002209 : LUT6
    generic map(
      INIT => X"8A8A8A08EFEFEFAE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_ph_cl(7),
      I1 => NlwRenamedSig_OI_trn_pfc_ph_cl(6),
      I2 => NlwRenamedSig_OI_trn_pfc_pd_cl(10),
      I3 => N0,
      I4 => pd_credit_limited_cmp_lt0000233_22435,
      I5 => NlwRenamedSig_OI_trn_pfc_pd_cl(11),
      O => pd_credit_limited_cmp_lt0000
    );
  cd_credit_limited_cmp_lt00002209 : LUT6
    generic map(
      INIT => X"8A8A8A08EFEFEFAE"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_cplh_cl(7),
      I1 => NlwRenamedSig_OI_trn_pfc_cplh_cl(6),
      I2 => NlwRenamedSig_OI_trn_pfc_cpld_cl(10),
      I3 => N2,
      I4 => cd_credit_limited_cmp_lt0000233_22377,
      I5 => NlwRenamedSig_OI_trn_pfc_cpld_cl(11),
      O => cd_credit_limited_cmp_lt0000
    );
  trn_pfc_pd_cl_mux0000_9_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(2),
      O => trn_pfc_pd_cl_mux0000(9)
    );
  trn_pfc_pd_cl_mux0000_8_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(3),
      O => trn_pfc_pd_cl_mux0000(8)
    );
  trn_pfc_pd_cl_mux0000_7_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(4),
      O => trn_pfc_pd_cl_mux0000(7)
    );
  trn_pfc_pd_cl_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(5),
      O => trn_pfc_pd_cl_mux0000(6)
    );
  trn_pfc_pd_cl_mux0000_5_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(6),
      O => trn_pfc_pd_cl_mux0000(5)
    );
  trn_pfc_pd_cl_mux0000_4_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(7),
      O => trn_pfc_pd_cl_mux0000(4)
    );
  trn_pfc_pd_cl_mux0000_3_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(8),
      O => trn_pfc_pd_cl_mux0000(3)
    );
  trn_pfc_pd_cl_mux0000_2_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(9),
      O => trn_pfc_pd_cl_mux0000(2)
    );
  trn_pfc_pd_cl_mux0000_1_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(10),
      O => trn_pfc_pd_cl_mux0000(1)
    );
  trn_pfc_pd_cl_mux0000_11_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(0),
      O => trn_pfc_pd_cl_mux0000(11)
    );
  trn_pfc_pd_cl_mux0000_10_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(1),
      O => trn_pfc_pd_cl_mux0000(10)
    );
  trn_pfc_pd_cl_mux0000_0_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => trn_pfc_pd_cl_cmp_eq000035_22494,
      I1 => trn_pfc_pd_cl_cmp_eq000071_22495,
      I2 => mgmt_stats_credit_d(11),
      O => trn_pfc_pd_cl_mux0000(0)
    );
  Mcount_initial_header_read_cntr_xor_0_11_INV_0 : INV
    port map (
      I => initial_header_read_cntr(0),
      O => Result_0_2
    );
  Mcount_cal_addr_xor_0_11_INV_0 : INV
    port map (
      I => cal_addr(0),
      O => Result(0)
    );
  initial_header_read_cntr_cmp_lt00001_INV_0 : INV
    port map (
      I => initial_header_read_cntr(4),
      O => initial_header_read_cntr_cmp_lt0000
    );
  rst_n_inv521_INV_0 : INV
    port map (
      I => rst_n,
      O => rst_n_inv
    );
  pd_credit_limited_cmp_lt00002209_SW01 : LUT5
    generic map(
      INIT => X"80A8C0FC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_ph_cl(4),
      I1 => pd_credit_limited_cmp_lt0000292_22436,
      I2 => NlwRenamedSig_OI_trn_pfc_ph_cl(3),
      I3 => NlwRenamedSig_OI_trn_pfc_pd_cl(7),
      I4 => NlwRenamedSig_OI_trn_pfc_pd_cl(8),
      O => pd_credit_limited_cmp_lt00002209_SW0
    );
  pd_credit_limited_cmp_lt00002209_SW02 : LUT6
    generic map(
      INIT => X"2202020033030300"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_ph_cl(4),
      I1 => NlwRenamedSig_OI_trn_pfc_pd_cl(9),
      I2 => NlwRenamedSig_OI_trn_pfc_pd_cl(7),
      I3 => NlwRenamedSig_OI_trn_pfc_ph_cl(3),
      I4 => pd_credit_limited_cmp_lt0000292_22436,
      I5 => NlwRenamedSig_OI_trn_pfc_pd_cl(8),
      O => pd_credit_limited_cmp_lt00002209_SW01_22434
    );
  pd_credit_limited_cmp_lt00002209_SW0_f7 : MUXF7
    port map (
      I0 => pd_credit_limited_cmp_lt00002209_SW01_22434,
      I1 => pd_credit_limited_cmp_lt00002209_SW0,
      S => NlwRenamedSig_OI_trn_pfc_ph_cl(5),
      O => N0
    );
  cd_credit_limited_cmp_lt00002209_SW01 : LUT5
    generic map(
      INIT => X"80A8C0FC"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_cplh_cl(4),
      I1 => cd_credit_limited_cmp_lt0000292_22378,
      I2 => NlwRenamedSig_OI_trn_pfc_cplh_cl(3),
      I3 => NlwRenamedSig_OI_trn_pfc_cpld_cl(7),
      I4 => NlwRenamedSig_OI_trn_pfc_cpld_cl(8),
      O => cd_credit_limited_cmp_lt00002209_SW0
    );
  cd_credit_limited_cmp_lt00002209_SW02 : LUT6
    generic map(
      INIT => X"2202020033030300"
    )
    port map (
      I0 => NlwRenamedSig_OI_trn_pfc_cplh_cl(4),
      I1 => NlwRenamedSig_OI_trn_pfc_cpld_cl(9),
      I2 => NlwRenamedSig_OI_trn_pfc_cpld_cl(7),
      I3 => NlwRenamedSig_OI_trn_pfc_cplh_cl(3),
      I4 => cd_credit_limited_cmp_lt0000292_22378,
      I5 => NlwRenamedSig_OI_trn_pfc_cpld_cl(8),
      O => cd_credit_limited_cmp_lt00002209_SW01_22376
    );
  cd_credit_limited_cmp_lt00002209_SW0_f7 : MUXF7
    port map (
      I0 => cd_credit_limited_cmp_lt00002209_SW01_22376,
      I1 => cd_credit_limited_cmp_lt00002209_SW0,
      S => NlwRenamedSig_OI_trn_pfc_cplh_cl(5),
      O => N2
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_blk_ll is
  port (
    rx_err_cpl_ur_n : out STD_LOGIC; 
    llk_tx_src_rdy_n : out STD_LOGIC; 
    trn_rsrc_rdy_n : out STD_LOGIC; 
    l0_stats_tlp_received : in STD_LOGIC := 'X'; 
    trn_terrfwd_n : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    llk_rx_eof_n : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    cfg_tx_dst_rdy_n : out STD_LOGIC; 
    llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
    trn_rerrfwd_n : out STD_LOGIC; 
    llk_rx_dst_cont_req_n : out STD_LOGIC; 
    cfg_tx_eof_n : in STD_LOGIC := 'X'; 
    trn_rnp_ok_n : in STD_LOGIC := 'X'; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    err_tlp_malformed : out STD_LOGIC; 
    llk_tx_sop_n : out STD_LOGIC; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    err_tlp_ur_lock : out STD_LOGIC; 
    trn_rsof_n : out STD_LOGIC; 
    io_space_enable : in STD_LOGIC := 'X'; 
    llk_rx_dst_req_n : out STD_LOGIC; 
    llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    llk_rx_sof_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_ep_n : out STD_LOGIC; 
    cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
    err_tlp_uc : out STD_LOGIC; 
    cfg_tx_sof_n : in STD_LOGIC := 'X'; 
    llk_tx_src_dsc_n : out STD_LOGIC; 
    trn_rsrc_dsc_n : out STD_LOGIC; 
    err_tlp_ur : out STD_LOGIC; 
    tx_err_wr_ep_n : out STD_LOGIC; 
    llk_rx_src_dsc_n : in STD_LOGIC := 'X'; 
    llk_tx_eof_n : out STD_LOGIC; 
    llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
    trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    cfg_tx_rem_n : in STD_LOGIC := 'X'; 
    rx_err_cpl_abort_n : out STD_LOGIC; 
    err_tlp_p : out STD_LOGIC; 
    mem_space_enable : in STD_LOGIC := 'X'; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    rx_err_ep_n : out STD_LOGIC; 
    llk_tx_eop_n : out STD_LOGIC; 
    trn_reof_n : out STD_LOGIC; 
    llk_tx_sof_n : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    trn_pfc_cplh_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_npd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    err_tlp_cpl_header : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
    trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_cpld_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_pfc_ph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    llk_rx_data_d : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_pfc_nph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    mgmt_stats_credit_sel : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_pfc_pd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
    llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_valid_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_rx_xrom : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    mgmt_stats_credit : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_rx_bar0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    cfg_rx_bar5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    llk_rx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end pcie_blk_ll;

architecture STRUCTURE of pcie_blk_ll is
  component pcie_blk_ll_credit
    port (
      clear_cpl_count : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      trn_pfc_cplh_cl_upd : out STD_LOGIC; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      npd_credit_limited : out STD_LOGIC; 
      pd_credit_limited : out STD_LOGIC; 
      cd_credit_limited : out STD_LOGIC; 
      rx_ch_credits_received_inc : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      tx_pd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_pfc_cplh_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_npd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_npd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_ch_credits_consumed : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rx_ch_credits_received : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_cd_credits_consumed : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_pfc_cpld_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_pfc_ph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_npd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_pfc_nph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_cd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      mgmt_stats_credit_sel : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_pfc_pd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_pd_credits_available : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      mgmt_stats_credit : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  component pcie_blk_plus_ll_tx
    port (
      clear_cpl_count : out STD_LOGIC; 
      llk_tx_src_rdy_n : out STD_LOGIC; 
      trn_terrfwd_n : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_tx_dst_rdy_n : out STD_LOGIC; 
      cfg_tx_eof_n : in STD_LOGIC := 'X'; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      trn_pfc_cplh_cl_upd : in STD_LOGIC := 'X'; 
      llk_tx_sop_n : out STD_LOGIC; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      cfg_tx_sof_n : in STD_LOGIC := 'X'; 
      llk_tx_src_dsc_n : out STD_LOGIC; 
      tx_err_wr_ep_n : out STD_LOGIC; 
      llk_tx_eof_n : out STD_LOGIC; 
      llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      npd_credit_limited : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      cfg_tx_rem_n : in STD_LOGIC := 'X'; 
      pd_credit_limited : in STD_LOGIC := 'X'; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      llk_tx_eop_n : out STD_LOGIC; 
      cd_credit_limited : in STD_LOGIC := 'X'; 
      llk_tx_sof_n : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      tx_pd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_cplh_cl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_npd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      tx_ch_credits_consumed : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_cd_credits_consumed : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      tx_npd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_cd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_pd_credits_available : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  component pcie_blk_plus_ll_rx
    port (
      rx_err_cpl_ur_n : out STD_LOGIC; 
      trn_rsrc_rdy_n : out STD_LOGIC; 
      l0_stats_tlp_received : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      llk_rx_eof_n : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
      trn_rerrfwd_n : out STD_LOGIC; 
      llk_rx_dst_cont_req_n : out STD_LOGIC; 
      trn_rnp_ok_n : in STD_LOGIC := 'X'; 
      err_tlp_malformed : out STD_LOGIC; 
      err_tlp_ur_lock : out STD_LOGIC; 
      trn_rsof_n : out STD_LOGIC; 
      io_space_enable : in STD_LOGIC := 'X'; 
      llk_rx_dst_req_n : out STD_LOGIC; 
      llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      llk_rx_sof_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_ep_n : out STD_LOGIC; 
      err_tlp_uc : out STD_LOGIC; 
      trn_rsrc_dsc_n : out STD_LOGIC; 
      err_tlp_ur : out STD_LOGIC; 
      llk_rx_src_dsc_n : in STD_LOGIC := 'X'; 
      trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_abort_n : out STD_LOGIC; 
      err_tlp_p : out STD_LOGIC; 
      mem_space_enable : in STD_LOGIC := 'X'; 
      rx_err_ep_n : out STD_LOGIC; 
      rx_ch_credits_received_inc : in STD_LOGIC := 'X'; 
      trn_reof_n : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      err_tlp_cpl_header : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
      trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_data_d : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
      llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_valid_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rx_ch_credits_received : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_rx_xrom : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_rx_bar0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      llk_rx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal cd_credit_limited : STD_LOGIC; 
  signal clear_cpl_count : STD_LOGIC; 
  signal npd_credit_limited : STD_LOGIC; 
  signal pd_credit_limited : STD_LOGIC; 
  signal rx_ch_credits_received_inc : STD_LOGIC; 
  signal trn_pfc_cplh_cl_upd : STD_LOGIC; 
  signal NLW_rx_bridge_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_rx_bridge_llk_rx_src_dsc_n_UNCONNECTED : STD_LOGIC; 
  signal rx_ch_credits_received : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_trn_pfc_cplh_cl : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal tx_cd_credits_available : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tx_cd_credits_consumed : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tx_ch_credits_consumed : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal tx_npd_credits_available : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tx_npd_credits_consumed : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tx_pd_credits_available : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal tx_pd_credits_consumed : STD_LOGIC_VECTOR ( 11 downto 0 ); 
begin
  trn_pfc_cplh_cl(7) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(7);
  trn_pfc_cplh_cl(6) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(6);
  trn_pfc_cplh_cl(5) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(5);
  trn_pfc_cplh_cl(4) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(4);
  trn_pfc_cplh_cl(3) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(3);
  trn_pfc_cplh_cl(2) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(2);
  trn_pfc_cplh_cl(1) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(1);
  trn_pfc_cplh_cl(0) <= NlwRenamedSig_OI_trn_pfc_cplh_cl(0);
  ll_credit : pcie_blk_ll_credit
    port map (
      clear_cpl_count => clear_cpl_count,
      clk => clk,
      rst_n => rst_n,
      trn_pfc_cplh_cl_upd => trn_pfc_cplh_cl_upd,
      trn_rcpl_streaming_n => trn_rcpl_streaming_n,
      l0_stats_cfg_transmitted => l0_stats_cfg_transmitted,
      npd_credit_limited => npd_credit_limited,
      pd_credit_limited => pd_credit_limited,
      cd_credit_limited => cd_credit_limited,
      rx_ch_credits_received_inc => rx_ch_credits_received_inc,
      trn_lnk_up_n => trn_lnk_up_n,
      tx_pd_credits_consumed(11) => tx_pd_credits_consumed(11),
      tx_pd_credits_consumed(10) => tx_pd_credits_consumed(10),
      tx_pd_credits_consumed(9) => tx_pd_credits_consumed(9),
      tx_pd_credits_consumed(8) => tx_pd_credits_consumed(8),
      tx_pd_credits_consumed(7) => tx_pd_credits_consumed(7),
      tx_pd_credits_consumed(6) => tx_pd_credits_consumed(6),
      tx_pd_credits_consumed(5) => tx_pd_credits_consumed(5),
      tx_pd_credits_consumed(4) => tx_pd_credits_consumed(4),
      tx_pd_credits_consumed(3) => tx_pd_credits_consumed(3),
      tx_pd_credits_consumed(2) => tx_pd_credits_consumed(2),
      tx_pd_credits_consumed(1) => tx_pd_credits_consumed(1),
      tx_pd_credits_consumed(0) => tx_pd_credits_consumed(0),
      trn_pfc_cplh_cl(7) => NlwRenamedSig_OI_trn_pfc_cplh_cl(7),
      trn_pfc_cplh_cl(6) => NlwRenamedSig_OI_trn_pfc_cplh_cl(6),
      trn_pfc_cplh_cl(5) => NlwRenamedSig_OI_trn_pfc_cplh_cl(5),
      trn_pfc_cplh_cl(4) => NlwRenamedSig_OI_trn_pfc_cplh_cl(4),
      trn_pfc_cplh_cl(3) => NlwRenamedSig_OI_trn_pfc_cplh_cl(3),
      trn_pfc_cplh_cl(2) => NlwRenamedSig_OI_trn_pfc_cplh_cl(2),
      trn_pfc_cplh_cl(1) => NlwRenamedSig_OI_trn_pfc_cplh_cl(1),
      trn_pfc_cplh_cl(0) => NlwRenamedSig_OI_trn_pfc_cplh_cl(0),
      trn_pfc_npd_cl(11) => trn_pfc_npd_cl(11),
      trn_pfc_npd_cl(10) => trn_pfc_npd_cl(10),
      trn_pfc_npd_cl(9) => trn_pfc_npd_cl(9),
      trn_pfc_npd_cl(8) => trn_pfc_npd_cl(8),
      trn_pfc_npd_cl(7) => trn_pfc_npd_cl(7),
      trn_pfc_npd_cl(6) => trn_pfc_npd_cl(6),
      trn_pfc_npd_cl(5) => trn_pfc_npd_cl(5),
      trn_pfc_npd_cl(4) => trn_pfc_npd_cl(4),
      trn_pfc_npd_cl(3) => trn_pfc_npd_cl(3),
      trn_pfc_npd_cl(2) => trn_pfc_npd_cl(2),
      trn_pfc_npd_cl(1) => trn_pfc_npd_cl(1),
      trn_pfc_npd_cl(0) => trn_pfc_npd_cl(0),
      tx_npd_credits_consumed(11) => tx_npd_credits_consumed(11),
      tx_npd_credits_consumed(10) => tx_npd_credits_consumed(10),
      tx_npd_credits_consumed(9) => tx_npd_credits_consumed(9),
      tx_npd_credits_consumed(8) => tx_npd_credits_consumed(8),
      tx_npd_credits_consumed(7) => tx_npd_credits_consumed(7),
      tx_npd_credits_consumed(6) => tx_npd_credits_consumed(6),
      tx_npd_credits_consumed(5) => tx_npd_credits_consumed(5),
      tx_npd_credits_consumed(4) => tx_npd_credits_consumed(4),
      tx_npd_credits_consumed(3) => tx_npd_credits_consumed(3),
      tx_npd_credits_consumed(2) => tx_npd_credits_consumed(2),
      tx_npd_credits_consumed(1) => tx_npd_credits_consumed(1),
      tx_npd_credits_consumed(0) => tx_npd_credits_consumed(0),
      tx_ch_credits_consumed(7) => tx_ch_credits_consumed(7),
      tx_ch_credits_consumed(6) => tx_ch_credits_consumed(6),
      tx_ch_credits_consumed(5) => tx_ch_credits_consumed(5),
      tx_ch_credits_consumed(4) => tx_ch_credits_consumed(4),
      tx_ch_credits_consumed(3) => tx_ch_credits_consumed(3),
      tx_ch_credits_consumed(2) => tx_ch_credits_consumed(2),
      tx_ch_credits_consumed(1) => tx_ch_credits_consumed(1),
      tx_ch_credits_consumed(0) => tx_ch_credits_consumed(0),
      trn_rfc_cplh_av(7) => trn_rfc_cplh_av(7),
      trn_rfc_cplh_av(6) => trn_rfc_cplh_av(6),
      trn_rfc_cplh_av(5) => trn_rfc_cplh_av(5),
      trn_rfc_cplh_av(4) => trn_rfc_cplh_av(4),
      trn_rfc_cplh_av(3) => trn_rfc_cplh_av(3),
      trn_rfc_cplh_av(2) => trn_rfc_cplh_av(2),
      trn_rfc_cplh_av(1) => trn_rfc_cplh_av(1),
      trn_rfc_cplh_av(0) => trn_rfc_cplh_av(0),
      rx_ch_credits_received(7) => rx_ch_credits_received(7),
      rx_ch_credits_received(6) => rx_ch_credits_received(6),
      rx_ch_credits_received(5) => rx_ch_credits_received(5),
      rx_ch_credits_received(4) => rx_ch_credits_received(4),
      rx_ch_credits_received(3) => rx_ch_credits_received(3),
      rx_ch_credits_received(2) => rx_ch_credits_received(2),
      rx_ch_credits_received(1) => rx_ch_credits_received(1),
      rx_ch_credits_received(0) => rx_ch_credits_received(0),
      trn_rfc_nph_av(7) => trn_rfc_nph_av(7),
      trn_rfc_nph_av(6) => trn_rfc_nph_av(6),
      trn_rfc_nph_av(5) => trn_rfc_nph_av(5),
      trn_rfc_nph_av(4) => trn_rfc_nph_av(4),
      trn_rfc_nph_av(3) => trn_rfc_nph_av(3),
      trn_rfc_nph_av(2) => trn_rfc_nph_av(2),
      trn_rfc_nph_av(1) => trn_rfc_nph_av(1),
      trn_rfc_nph_av(0) => trn_rfc_nph_av(0),
      trn_rfc_ph_av(7) => trn_rfc_ph_av(7),
      trn_rfc_ph_av(6) => trn_rfc_ph_av(6),
      trn_rfc_ph_av(5) => trn_rfc_ph_av(5),
      trn_rfc_ph_av(4) => trn_rfc_ph_av(4),
      trn_rfc_ph_av(3) => trn_rfc_ph_av(3),
      trn_rfc_ph_av(2) => trn_rfc_ph_av(2),
      trn_rfc_ph_av(1) => trn_rfc_ph_av(1),
      trn_rfc_ph_av(0) => trn_rfc_ph_av(0),
      tx_cd_credits_consumed(11) => tx_cd_credits_consumed(11),
      tx_cd_credits_consumed(10) => tx_cd_credits_consumed(10),
      tx_cd_credits_consumed(9) => tx_cd_credits_consumed(9),
      tx_cd_credits_consumed(8) => tx_cd_credits_consumed(8),
      tx_cd_credits_consumed(7) => tx_cd_credits_consumed(7),
      tx_cd_credits_consumed(6) => tx_cd_credits_consumed(6),
      tx_cd_credits_consumed(5) => tx_cd_credits_consumed(5),
      tx_cd_credits_consumed(4) => tx_cd_credits_consumed(4),
      tx_cd_credits_consumed(3) => tx_cd_credits_consumed(3),
      tx_cd_credits_consumed(2) => tx_cd_credits_consumed(2),
      tx_cd_credits_consumed(1) => tx_cd_credits_consumed(1),
      tx_cd_credits_consumed(0) => tx_cd_credits_consumed(0),
      trn_pfc_cpld_cl(11) => trn_pfc_cpld_cl(11),
      trn_pfc_cpld_cl(10) => trn_pfc_cpld_cl(10),
      trn_pfc_cpld_cl(9) => trn_pfc_cpld_cl(9),
      trn_pfc_cpld_cl(8) => trn_pfc_cpld_cl(8),
      trn_pfc_cpld_cl(7) => trn_pfc_cpld_cl(7),
      trn_pfc_cpld_cl(6) => trn_pfc_cpld_cl(6),
      trn_pfc_cpld_cl(5) => trn_pfc_cpld_cl(5),
      trn_pfc_cpld_cl(4) => trn_pfc_cpld_cl(4),
      trn_pfc_cpld_cl(3) => trn_pfc_cpld_cl(3),
      trn_pfc_cpld_cl(2) => trn_pfc_cpld_cl(2),
      trn_pfc_cpld_cl(1) => trn_pfc_cpld_cl(1),
      trn_pfc_cpld_cl(0) => trn_pfc_cpld_cl(0),
      trn_pfc_ph_cl(7) => trn_pfc_ph_cl(7),
      trn_pfc_ph_cl(6) => trn_pfc_ph_cl(6),
      trn_pfc_ph_cl(5) => trn_pfc_ph_cl(5),
      trn_pfc_ph_cl(4) => trn_pfc_ph_cl(4),
      trn_pfc_ph_cl(3) => trn_pfc_ph_cl(3),
      trn_pfc_ph_cl(2) => trn_pfc_ph_cl(2),
      trn_pfc_ph_cl(1) => trn_pfc_ph_cl(1),
      trn_pfc_ph_cl(0) => trn_pfc_ph_cl(0),
      tx_npd_credits_available(11) => tx_npd_credits_available(11),
      tx_npd_credits_available(10) => tx_npd_credits_available(10),
      tx_npd_credits_available(9) => tx_npd_credits_available(9),
      tx_npd_credits_available(8) => tx_npd_credits_available(8),
      tx_npd_credits_available(7) => tx_npd_credits_available(7),
      tx_npd_credits_available(6) => tx_npd_credits_available(6),
      tx_npd_credits_available(5) => tx_npd_credits_available(5),
      tx_npd_credits_available(4) => tx_npd_credits_available(4),
      tx_npd_credits_available(3) => tx_npd_credits_available(3),
      tx_npd_credits_available(2) => tx_npd_credits_available(2),
      tx_npd_credits_available(1) => tx_npd_credits_available(1),
      tx_npd_credits_available(0) => tx_npd_credits_available(0),
      trn_rfc_cpld_av(11) => trn_rfc_cpld_av(11),
      trn_rfc_cpld_av(10) => trn_rfc_cpld_av(10),
      trn_rfc_cpld_av(9) => trn_rfc_cpld_av(9),
      trn_rfc_cpld_av(8) => trn_rfc_cpld_av(8),
      trn_rfc_cpld_av(7) => trn_rfc_cpld_av(7),
      trn_rfc_cpld_av(6) => trn_rfc_cpld_av(6),
      trn_rfc_cpld_av(5) => trn_rfc_cpld_av(5),
      trn_rfc_cpld_av(4) => trn_rfc_cpld_av(4),
      trn_rfc_cpld_av(3) => trn_rfc_cpld_av(3),
      trn_rfc_cpld_av(2) => trn_rfc_cpld_av(2),
      trn_rfc_cpld_av(1) => trn_rfc_cpld_av(1),
      trn_rfc_cpld_av(0) => trn_rfc_cpld_av(0),
      trn_pfc_nph_cl(7) => trn_pfc_nph_cl(7),
      trn_pfc_nph_cl(6) => trn_pfc_nph_cl(6),
      trn_pfc_nph_cl(5) => trn_pfc_nph_cl(5),
      trn_pfc_nph_cl(4) => trn_pfc_nph_cl(4),
      trn_pfc_nph_cl(3) => trn_pfc_nph_cl(3),
      trn_pfc_nph_cl(2) => trn_pfc_nph_cl(2),
      trn_pfc_nph_cl(1) => trn_pfc_nph_cl(1),
      trn_pfc_nph_cl(0) => trn_pfc_nph_cl(0),
      trn_rfc_npd_av(11) => trn_rfc_npd_av(11),
      trn_rfc_npd_av(10) => trn_rfc_npd_av(10),
      trn_rfc_npd_av(9) => trn_rfc_npd_av(9),
      trn_rfc_npd_av(8) => trn_rfc_npd_av(8),
      trn_rfc_npd_av(7) => trn_rfc_npd_av(7),
      trn_rfc_npd_av(6) => trn_rfc_npd_av(6),
      trn_rfc_npd_av(5) => trn_rfc_npd_av(5),
      trn_rfc_npd_av(4) => trn_rfc_npd_av(4),
      trn_rfc_npd_av(3) => trn_rfc_npd_av(3),
      trn_rfc_npd_av(2) => trn_rfc_npd_av(2),
      trn_rfc_npd_av(1) => trn_rfc_npd_av(1),
      trn_rfc_npd_av(0) => trn_rfc_npd_av(0),
      tx_cd_credits_available(11) => tx_cd_credits_available(11),
      tx_cd_credits_available(10) => tx_cd_credits_available(10),
      tx_cd_credits_available(9) => tx_cd_credits_available(9),
      tx_cd_credits_available(8) => tx_cd_credits_available(8),
      tx_cd_credits_available(7) => tx_cd_credits_available(7),
      tx_cd_credits_available(6) => tx_cd_credits_available(6),
      tx_cd_credits_available(5) => tx_cd_credits_available(5),
      tx_cd_credits_available(4) => tx_cd_credits_available(4),
      tx_cd_credits_available(3) => tx_cd_credits_available(3),
      tx_cd_credits_available(2) => tx_cd_credits_available(2),
      tx_cd_credits_available(1) => tx_cd_credits_available(1),
      tx_cd_credits_available(0) => tx_cd_credits_available(0),
      trn_rfc_pd_av(11) => trn_rfc_pd_av(11),
      trn_rfc_pd_av(10) => trn_rfc_pd_av(10),
      trn_rfc_pd_av(9) => trn_rfc_pd_av(9),
      trn_rfc_pd_av(8) => trn_rfc_pd_av(8),
      trn_rfc_pd_av(7) => trn_rfc_pd_av(7),
      trn_rfc_pd_av(6) => trn_rfc_pd_av(6),
      trn_rfc_pd_av(5) => trn_rfc_pd_av(5),
      trn_rfc_pd_av(4) => trn_rfc_pd_av(4),
      trn_rfc_pd_av(3) => trn_rfc_pd_av(3),
      trn_rfc_pd_av(2) => trn_rfc_pd_av(2),
      trn_rfc_pd_av(1) => trn_rfc_pd_av(1),
      trn_rfc_pd_av(0) => trn_rfc_pd_av(0),
      mgmt_stats_credit_sel(6) => mgmt_stats_credit_sel(6),
      mgmt_stats_credit_sel(5) => mgmt_stats_credit_sel(5),
      mgmt_stats_credit_sel(4) => mgmt_stats_credit_sel(4),
      mgmt_stats_credit_sel(3) => mgmt_stats_credit_sel(3),
      mgmt_stats_credit_sel(2) => mgmt_stats_credit_sel(2),
      mgmt_stats_credit_sel(1) => mgmt_stats_credit_sel(1),
      mgmt_stats_credit_sel(0) => mgmt_stats_credit_sel(0),
      trn_pfc_pd_cl(11) => trn_pfc_pd_cl(11),
      trn_pfc_pd_cl(10) => trn_pfc_pd_cl(10),
      trn_pfc_pd_cl(9) => trn_pfc_pd_cl(9),
      trn_pfc_pd_cl(8) => trn_pfc_pd_cl(8),
      trn_pfc_pd_cl(7) => trn_pfc_pd_cl(7),
      trn_pfc_pd_cl(6) => trn_pfc_pd_cl(6),
      trn_pfc_pd_cl(5) => trn_pfc_pd_cl(5),
      trn_pfc_pd_cl(4) => trn_pfc_pd_cl(4),
      trn_pfc_pd_cl(3) => trn_pfc_pd_cl(3),
      trn_pfc_pd_cl(2) => trn_pfc_pd_cl(2),
      trn_pfc_pd_cl(1) => trn_pfc_pd_cl(1),
      trn_pfc_pd_cl(0) => trn_pfc_pd_cl(0),
      tx_pd_credits_available(11) => tx_pd_credits_available(11),
      tx_pd_credits_available(10) => tx_pd_credits_available(10),
      tx_pd_credits_available(9) => tx_pd_credits_available(9),
      tx_pd_credits_available(8) => tx_pd_credits_available(8),
      tx_pd_credits_available(7) => tx_pd_credits_available(7),
      tx_pd_credits_available(6) => tx_pd_credits_available(6),
      tx_pd_credits_available(5) => tx_pd_credits_available(5),
      tx_pd_credits_available(4) => tx_pd_credits_available(4),
      tx_pd_credits_available(3) => tx_pd_credits_available(3),
      tx_pd_credits_available(2) => tx_pd_credits_available(2),
      tx_pd_credits_available(1) => tx_pd_credits_available(1),
      tx_pd_credits_available(0) => tx_pd_credits_available(0),
      mgmt_stats_credit(11) => mgmt_stats_credit(11),
      mgmt_stats_credit(10) => mgmt_stats_credit(10),
      mgmt_stats_credit(9) => mgmt_stats_credit(9),
      mgmt_stats_credit(8) => mgmt_stats_credit(8),
      mgmt_stats_credit(7) => mgmt_stats_credit(7),
      mgmt_stats_credit(6) => mgmt_stats_credit(6),
      mgmt_stats_credit(5) => mgmt_stats_credit(5),
      mgmt_stats_credit(4) => mgmt_stats_credit(4),
      mgmt_stats_credit(3) => mgmt_stats_credit(3),
      mgmt_stats_credit(2) => mgmt_stats_credit(2),
      mgmt_stats_credit(1) => mgmt_stats_credit(1),
      mgmt_stats_credit(0) => mgmt_stats_credit(0)
    );
  tx_bridge : pcie_blk_plus_ll_tx
    port map (
      clear_cpl_count => clear_cpl_count,
      llk_tx_src_rdy_n => llk_tx_src_rdy_n,
      trn_terrfwd_n => trn_terrfwd_n,
      clk => clk,
      rst_n => rst_n,
      cfg_tx_dst_rdy_n => cfg_tx_dst_rdy_n,
      cfg_tx_eof_n => cfg_tx_eof_n,
      trn_tsrc_dsc_n => trn_tsrc_dsc_n,
      trn_pfc_cplh_cl_upd => trn_pfc_cplh_cl_upd,
      llk_tx_sop_n => llk_tx_sop_n,
      trn_tdst_rdy_n => trn_tdst_rdy_n,
      trn_teof_n => trn_teof_n,
      cfg_tx_src_rdy_n => cfg_tx_src_rdy_n,
      l0_stats_cfg_transmitted => l0_stats_cfg_transmitted,
      cfg_tx_sof_n => cfg_tx_sof_n,
      llk_tx_src_dsc_n => llk_tx_src_dsc_n,
      tx_err_wr_ep_n => tx_err_wr_ep_n,
      llk_tx_eof_n => llk_tx_eof_n,
      llk_tx_dst_rdy_n => llk_tx_dst_rdy_n,
      trn_tsrc_rdy_n => trn_tsrc_rdy_n,
      npd_credit_limited => npd_credit_limited,
      trn_tsof_n => trn_tsof_n,
      cfg_tx_rem_n => cfg_tx_rem_n,
      pd_credit_limited => pd_credit_limited,
      trn_tdst_dsc_n => trn_tdst_dsc_n,
      llk_tx_eop_n => llk_tx_eop_n,
      cd_credit_limited => cd_credit_limited,
      llk_tx_sof_n => llk_tx_sof_n,
      trn_lnk_up_n => trn_lnk_up_n,
      llk_tx_ch_fifo(1) => llk_tx_ch_fifo(1),
      llk_tx_ch_fifo(0) => llk_tx_ch_fifo(0),
      llk_tx_ch_tc(2) => llk_tx_ch_tc(2),
      llk_tx_ch_tc(1) => llk_tx_ch_tc(1),
      llk_tx_ch_tc(0) => llk_tx_ch_tc(0),
      trn_tbuf_av(3) => trn_tbuf_av(3),
      trn_tbuf_av(2) => trn_tbuf_av(2),
      trn_tbuf_av(1) => trn_tbuf_av(1),
      trn_tbuf_av(0) => trn_tbuf_av(0),
      llk_tx_enable_n(1) => llk_tx_enable_n(1),
      llk_tx_enable_n(0) => llk_tx_enable_n(0),
      llk_tx_data(63) => llk_tx_data(63),
      llk_tx_data(62) => llk_tx_data(62),
      llk_tx_data(61) => llk_tx_data(61),
      llk_tx_data(60) => llk_tx_data(60),
      llk_tx_data(59) => llk_tx_data(59),
      llk_tx_data(58) => llk_tx_data(58),
      llk_tx_data(57) => llk_tx_data(57),
      llk_tx_data(56) => llk_tx_data(56),
      llk_tx_data(55) => llk_tx_data(55),
      llk_tx_data(54) => llk_tx_data(54),
      llk_tx_data(53) => llk_tx_data(53),
      llk_tx_data(52) => llk_tx_data(52),
      llk_tx_data(51) => llk_tx_data(51),
      llk_tx_data(50) => llk_tx_data(50),
      llk_tx_data(49) => llk_tx_data(49),
      llk_tx_data(48) => llk_tx_data(48),
      llk_tx_data(47) => llk_tx_data(47),
      llk_tx_data(46) => llk_tx_data(46),
      llk_tx_data(45) => llk_tx_data(45),
      llk_tx_data(44) => llk_tx_data(44),
      llk_tx_data(43) => llk_tx_data(43),
      llk_tx_data(42) => llk_tx_data(42),
      llk_tx_data(41) => llk_tx_data(41),
      llk_tx_data(40) => llk_tx_data(40),
      llk_tx_data(39) => llk_tx_data(39),
      llk_tx_data(38) => llk_tx_data(38),
      llk_tx_data(37) => llk_tx_data(37),
      llk_tx_data(36) => llk_tx_data(36),
      llk_tx_data(35) => llk_tx_data(35),
      llk_tx_data(34) => llk_tx_data(34),
      llk_tx_data(33) => llk_tx_data(33),
      llk_tx_data(32) => llk_tx_data(32),
      llk_tx_data(31) => llk_tx_data(31),
      llk_tx_data(30) => llk_tx_data(30),
      llk_tx_data(29) => llk_tx_data(29),
      llk_tx_data(28) => llk_tx_data(28),
      llk_tx_data(27) => llk_tx_data(27),
      llk_tx_data(26) => llk_tx_data(26),
      llk_tx_data(25) => llk_tx_data(25),
      llk_tx_data(24) => llk_tx_data(24),
      llk_tx_data(23) => llk_tx_data(23),
      llk_tx_data(22) => llk_tx_data(22),
      llk_tx_data(21) => llk_tx_data(21),
      llk_tx_data(20) => llk_tx_data(20),
      llk_tx_data(19) => llk_tx_data(19),
      llk_tx_data(18) => llk_tx_data(18),
      llk_tx_data(17) => llk_tx_data(17),
      llk_tx_data(16) => llk_tx_data(16),
      llk_tx_data(15) => llk_tx_data(15),
      llk_tx_data(14) => llk_tx_data(14),
      llk_tx_data(13) => llk_tx_data(13),
      llk_tx_data(12) => llk_tx_data(12),
      llk_tx_data(11) => llk_tx_data(11),
      llk_tx_data(10) => llk_tx_data(10),
      llk_tx_data(9) => llk_tx_data(9),
      llk_tx_data(8) => llk_tx_data(8),
      llk_tx_data(7) => llk_tx_data(7),
      llk_tx_data(6) => llk_tx_data(6),
      llk_tx_data(5) => llk_tx_data(5),
      llk_tx_data(4) => llk_tx_data(4),
      llk_tx_data(3) => llk_tx_data(3),
      llk_tx_data(2) => llk_tx_data(2),
      llk_tx_data(1) => llk_tx_data(1),
      llk_tx_data(0) => llk_tx_data(0),
      trn_td(63) => trn_td(63),
      trn_td(62) => trn_td(62),
      trn_td(61) => trn_td(61),
      trn_td(60) => trn_td(60),
      trn_td(59) => trn_td(59),
      trn_td(58) => trn_td(58),
      trn_td(57) => trn_td(57),
      trn_td(56) => trn_td(56),
      trn_td(55) => trn_td(55),
      trn_td(54) => trn_td(54),
      trn_td(53) => trn_td(53),
      trn_td(52) => trn_td(52),
      trn_td(51) => trn_td(51),
      trn_td(50) => trn_td(50),
      trn_td(49) => trn_td(49),
      trn_td(48) => trn_td(48),
      trn_td(47) => trn_td(47),
      trn_td(46) => trn_td(46),
      trn_td(45) => trn_td(45),
      trn_td(44) => trn_td(44),
      trn_td(43) => trn_td(43),
      trn_td(42) => trn_td(42),
      trn_td(41) => trn_td(41),
      trn_td(40) => trn_td(40),
      trn_td(39) => trn_td(39),
      trn_td(38) => trn_td(38),
      trn_td(37) => trn_td(37),
      trn_td(36) => trn_td(36),
      trn_td(35) => trn_td(35),
      trn_td(34) => trn_td(34),
      trn_td(33) => trn_td(33),
      trn_td(32) => trn_td(32),
      trn_td(31) => trn_td(31),
      trn_td(30) => trn_td(30),
      trn_td(29) => trn_td(29),
      trn_td(28) => trn_td(28),
      trn_td(27) => trn_td(27),
      trn_td(26) => trn_td(26),
      trn_td(25) => trn_td(25),
      trn_td(24) => trn_td(24),
      trn_td(23) => trn_td(23),
      trn_td(22) => trn_td(22),
      trn_td(21) => trn_td(21),
      trn_td(20) => trn_td(20),
      trn_td(19) => trn_td(19),
      trn_td(18) => trn_td(18),
      trn_td(17) => trn_td(17),
      trn_td(16) => trn_td(16),
      trn_td(15) => trn_td(15),
      trn_td(14) => trn_td(14),
      trn_td(13) => trn_td(13),
      trn_td(12) => trn_td(12),
      trn_td(11) => trn_td(11),
      trn_td(10) => trn_td(10),
      trn_td(9) => trn_td(9),
      trn_td(8) => trn_td(8),
      trn_td(7) => trn_td(7),
      trn_td(6) => trn_td(6),
      trn_td(5) => trn_td(5),
      trn_td(4) => trn_td(4),
      trn_td(3) => trn_td(3),
      trn_td(2) => trn_td(2),
      trn_td(1) => trn_td(1),
      trn_td(0) => trn_td(0),
      tx_pd_credits_consumed(11) => tx_pd_credits_consumed(11),
      tx_pd_credits_consumed(10) => tx_pd_credits_consumed(10),
      tx_pd_credits_consumed(9) => tx_pd_credits_consumed(9),
      tx_pd_credits_consumed(8) => tx_pd_credits_consumed(8),
      tx_pd_credits_consumed(7) => tx_pd_credits_consumed(7),
      tx_pd_credits_consumed(6) => tx_pd_credits_consumed(6),
      tx_pd_credits_consumed(5) => tx_pd_credits_consumed(5),
      tx_pd_credits_consumed(4) => tx_pd_credits_consumed(4),
      tx_pd_credits_consumed(3) => tx_pd_credits_consumed(3),
      tx_pd_credits_consumed(2) => tx_pd_credits_consumed(2),
      tx_pd_credits_consumed(1) => tx_pd_credits_consumed(1),
      tx_pd_credits_consumed(0) => tx_pd_credits_consumed(0),
      llk_tx_ch_non_posted_ready_n(7) => llk_tx_ch_non_posted_ready_n(7),
      llk_tx_ch_non_posted_ready_n(6) => llk_tx_ch_non_posted_ready_n(6),
      llk_tx_ch_non_posted_ready_n(5) => llk_tx_ch_non_posted_ready_n(5),
      llk_tx_ch_non_posted_ready_n(4) => llk_tx_ch_non_posted_ready_n(4),
      llk_tx_ch_non_posted_ready_n(3) => llk_tx_ch_non_posted_ready_n(3),
      llk_tx_ch_non_posted_ready_n(2) => llk_tx_ch_non_posted_ready_n(2),
      llk_tx_ch_non_posted_ready_n(1) => llk_tx_ch_non_posted_ready_n(1),
      llk_tx_ch_non_posted_ready_n(0) => llk_tx_ch_non_posted_ready_n(0),
      trn_pfc_cplh_cl(7) => NlwRenamedSig_OI_trn_pfc_cplh_cl(7),
      trn_pfc_cplh_cl(6) => NlwRenamedSig_OI_trn_pfc_cplh_cl(6),
      trn_pfc_cplh_cl(5) => NlwRenamedSig_OI_trn_pfc_cplh_cl(5),
      trn_pfc_cplh_cl(4) => NlwRenamedSig_OI_trn_pfc_cplh_cl(4),
      trn_pfc_cplh_cl(3) => NlwRenamedSig_OI_trn_pfc_cplh_cl(3),
      trn_pfc_cplh_cl(2) => NlwRenamedSig_OI_trn_pfc_cplh_cl(2),
      trn_pfc_cplh_cl(1) => NlwRenamedSig_OI_trn_pfc_cplh_cl(1),
      trn_pfc_cplh_cl(0) => NlwRenamedSig_OI_trn_pfc_cplh_cl(0),
      tx_npd_credits_consumed(11) => tx_npd_credits_consumed(11),
      tx_npd_credits_consumed(10) => tx_npd_credits_consumed(10),
      tx_npd_credits_consumed(9) => tx_npd_credits_consumed(9),
      tx_npd_credits_consumed(8) => tx_npd_credits_consumed(8),
      tx_npd_credits_consumed(7) => tx_npd_credits_consumed(7),
      tx_npd_credits_consumed(6) => tx_npd_credits_consumed(6),
      tx_npd_credits_consumed(5) => tx_npd_credits_consumed(5),
      tx_npd_credits_consumed(4) => tx_npd_credits_consumed(4),
      tx_npd_credits_consumed(3) => tx_npd_credits_consumed(3),
      tx_npd_credits_consumed(2) => tx_npd_credits_consumed(2),
      tx_npd_credits_consumed(1) => tx_npd_credits_consumed(1),
      tx_npd_credits_consumed(0) => tx_npd_credits_consumed(0),
      cfg_tx_td(63) => cfg_tx_td(63),
      cfg_tx_td(62) => cfg_tx_td(62),
      cfg_tx_td(61) => cfg_tx_td(61),
      cfg_tx_td(60) => cfg_tx_td(60),
      cfg_tx_td(59) => cfg_tx_td(59),
      cfg_tx_td(58) => cfg_tx_td(58),
      cfg_tx_td(57) => cfg_tx_td(57),
      cfg_tx_td(56) => cfg_tx_td(56),
      cfg_tx_td(55) => cfg_tx_td(55),
      cfg_tx_td(54) => cfg_tx_td(54),
      cfg_tx_td(53) => cfg_tx_td(53),
      cfg_tx_td(52) => cfg_tx_td(52),
      cfg_tx_td(51) => cfg_tx_td(51),
      cfg_tx_td(50) => cfg_tx_td(50),
      cfg_tx_td(49) => cfg_tx_td(49),
      cfg_tx_td(48) => cfg_tx_td(48),
      cfg_tx_td(47) => cfg_tx_td(47),
      cfg_tx_td(46) => cfg_tx_td(46),
      cfg_tx_td(45) => cfg_tx_td(45),
      cfg_tx_td(44) => cfg_tx_td(44),
      cfg_tx_td(43) => cfg_tx_td(43),
      cfg_tx_td(42) => cfg_tx_td(42),
      cfg_tx_td(41) => cfg_tx_td(41),
      cfg_tx_td(40) => cfg_tx_td(40),
      cfg_tx_td(39) => cfg_tx_td(39),
      cfg_tx_td(38) => cfg_tx_td(38),
      cfg_tx_td(37) => cfg_tx_td(37),
      cfg_tx_td(36) => cfg_tx_td(36),
      cfg_tx_td(35) => cfg_tx_td(35),
      cfg_tx_td(34) => cfg_tx_td(34),
      cfg_tx_td(33) => cfg_tx_td(33),
      cfg_tx_td(32) => cfg_tx_td(32),
      cfg_tx_td(31) => cfg_tx_td(31),
      cfg_tx_td(30) => cfg_tx_td(30),
      cfg_tx_td(29) => cfg_tx_td(29),
      cfg_tx_td(28) => cfg_tx_td(28),
      cfg_tx_td(27) => cfg_tx_td(27),
      cfg_tx_td(26) => cfg_tx_td(26),
      cfg_tx_td(25) => cfg_tx_td(25),
      cfg_tx_td(24) => cfg_tx_td(24),
      cfg_tx_td(23) => cfg_tx_td(23),
      cfg_tx_td(22) => cfg_tx_td(22),
      cfg_tx_td(21) => cfg_tx_td(21),
      cfg_tx_td(20) => cfg_tx_td(20),
      cfg_tx_td(19) => cfg_tx_td(19),
      cfg_tx_td(18) => cfg_tx_td(18),
      cfg_tx_td(17) => cfg_tx_td(17),
      cfg_tx_td(16) => cfg_tx_td(16),
      cfg_tx_td(15) => cfg_tx_td(15),
      cfg_tx_td(14) => cfg_tx_td(14),
      cfg_tx_td(13) => cfg_tx_td(13),
      cfg_tx_td(12) => cfg_tx_td(12),
      cfg_tx_td(11) => cfg_tx_td(11),
      cfg_tx_td(10) => cfg_tx_td(10),
      cfg_tx_td(9) => cfg_tx_td(9),
      cfg_tx_td(8) => cfg_tx_td(8),
      cfg_tx_td(7) => cfg_tx_td(7),
      cfg_tx_td(6) => cfg_tx_td(6),
      cfg_tx_td(5) => cfg_tx_td(5),
      cfg_tx_td(4) => cfg_tx_td(4),
      cfg_tx_td(3) => cfg_tx_td(3),
      cfg_tx_td(2) => cfg_tx_td(2),
      cfg_tx_td(1) => cfg_tx_td(1),
      cfg_tx_td(0) => cfg_tx_td(0),
      tx_ch_credits_consumed(7) => tx_ch_credits_consumed(7),
      tx_ch_credits_consumed(6) => tx_ch_credits_consumed(6),
      tx_ch_credits_consumed(5) => tx_ch_credits_consumed(5),
      tx_ch_credits_consumed(4) => tx_ch_credits_consumed(4),
      tx_ch_credits_consumed(3) => tx_ch_credits_consumed(3),
      tx_ch_credits_consumed(2) => tx_ch_credits_consumed(2),
      tx_ch_credits_consumed(1) => tx_ch_credits_consumed(1),
      tx_ch_credits_consumed(0) => tx_ch_credits_consumed(0),
      llk_tx_ch_posted_ready_n(7) => llk_tx_ch_posted_ready_n(7),
      llk_tx_ch_posted_ready_n(6) => llk_tx_ch_posted_ready_n(6),
      llk_tx_ch_posted_ready_n(5) => llk_tx_ch_posted_ready_n(5),
      llk_tx_ch_posted_ready_n(4) => llk_tx_ch_posted_ready_n(4),
      llk_tx_ch_posted_ready_n(3) => llk_tx_ch_posted_ready_n(3),
      llk_tx_ch_posted_ready_n(2) => llk_tx_ch_posted_ready_n(2),
      llk_tx_ch_posted_ready_n(1) => llk_tx_ch_posted_ready_n(1),
      llk_tx_ch_posted_ready_n(0) => llk_tx_ch_posted_ready_n(0),
      tx_cd_credits_consumed(11) => tx_cd_credits_consumed(11),
      tx_cd_credits_consumed(10) => tx_cd_credits_consumed(10),
      tx_cd_credits_consumed(9) => tx_cd_credits_consumed(9),
      tx_cd_credits_consumed(8) => tx_cd_credits_consumed(8),
      tx_cd_credits_consumed(7) => tx_cd_credits_consumed(7),
      tx_cd_credits_consumed(6) => tx_cd_credits_consumed(6),
      tx_cd_credits_consumed(5) => tx_cd_credits_consumed(5),
      tx_cd_credits_consumed(4) => tx_cd_credits_consumed(4),
      tx_cd_credits_consumed(3) => tx_cd_credits_consumed(3),
      tx_cd_credits_consumed(2) => tx_cd_credits_consumed(2),
      tx_cd_credits_consumed(1) => tx_cd_credits_consumed(1),
      tx_cd_credits_consumed(0) => tx_cd_credits_consumed(0),
      tx_npd_credits_available(11) => tx_npd_credits_available(11),
      tx_npd_credits_available(10) => tx_npd_credits_available(10),
      tx_npd_credits_available(9) => tx_npd_credits_available(9),
      tx_npd_credits_available(8) => tx_npd_credits_available(8),
      tx_npd_credits_available(7) => tx_npd_credits_available(7),
      tx_npd_credits_available(6) => tx_npd_credits_available(6),
      tx_npd_credits_available(5) => tx_npd_credits_available(5),
      tx_npd_credits_available(4) => tx_npd_credits_available(4),
      tx_npd_credits_available(3) => tx_npd_credits_available(3),
      tx_npd_credits_available(2) => tx_npd_credits_available(2),
      tx_npd_credits_available(1) => tx_npd_credits_available(1),
      tx_npd_credits_available(0) => tx_npd_credits_available(0),
      llk_tx_chan_space(9) => llk_tx_chan_space(9),
      llk_tx_chan_space(8) => llk_tx_chan_space(8),
      llk_tx_chan_space(7) => llk_tx_chan_space(7),
      llk_tx_chan_space(6) => llk_tx_chan_space(6),
      llk_tx_chan_space(5) => llk_tx_chan_space(5),
      llk_tx_chan_space(4) => llk_tx_chan_space(4),
      llk_tx_chan_space(3) => llk_tx_chan_space(3),
      llk_tx_chan_space(2) => llk_tx_chan_space(2),
      llk_tx_chan_space(1) => llk_tx_chan_space(1),
      llk_tx_chan_space(0) => llk_tx_chan_space(0),
      llk_tx_ch_completion_ready_n(7) => llk_tx_ch_completion_ready_n(7),
      llk_tx_ch_completion_ready_n(6) => llk_tx_ch_completion_ready_n(6),
      llk_tx_ch_completion_ready_n(5) => llk_tx_ch_completion_ready_n(5),
      llk_tx_ch_completion_ready_n(4) => llk_tx_ch_completion_ready_n(4),
      llk_tx_ch_completion_ready_n(3) => llk_tx_ch_completion_ready_n(3),
      llk_tx_ch_completion_ready_n(2) => llk_tx_ch_completion_ready_n(2),
      llk_tx_ch_completion_ready_n(1) => llk_tx_ch_completion_ready_n(1),
      llk_tx_ch_completion_ready_n(0) => llk_tx_ch_completion_ready_n(0),
      tx_cd_credits_available(11) => tx_cd_credits_available(11),
      tx_cd_credits_available(10) => tx_cd_credits_available(10),
      tx_cd_credits_available(9) => tx_cd_credits_available(9),
      tx_cd_credits_available(8) => tx_cd_credits_available(8),
      tx_cd_credits_available(7) => tx_cd_credits_available(7),
      tx_cd_credits_available(6) => tx_cd_credits_available(6),
      tx_cd_credits_available(5) => tx_cd_credits_available(5),
      tx_cd_credits_available(4) => tx_cd_credits_available(4),
      tx_cd_credits_available(3) => tx_cd_credits_available(3),
      tx_cd_credits_available(2) => tx_cd_credits_available(2),
      tx_cd_credits_available(1) => tx_cd_credits_available(1),
      tx_cd_credits_available(0) => tx_cd_credits_available(0),
      trn_trem_n(7) => trn_trem_n(7),
      trn_trem_n(6) => trn_trem_n(6),
      trn_trem_n(5) => trn_trem_n(5),
      trn_trem_n(4) => trn_trem_n(4),
      trn_trem_n(3) => trn_trem_n(3),
      trn_trem_n(2) => trn_trem_n(2),
      trn_trem_n(1) => trn_trem_n(1),
      trn_trem_n(0) => trn_trem_n(0),
      tx_pd_credits_available(11) => tx_pd_credits_available(11),
      tx_pd_credits_available(10) => tx_pd_credits_available(10),
      tx_pd_credits_available(9) => tx_pd_credits_available(9),
      tx_pd_credits_available(8) => tx_pd_credits_available(8),
      tx_pd_credits_available(7) => tx_pd_credits_available(7),
      tx_pd_credits_available(6) => tx_pd_credits_available(6),
      tx_pd_credits_available(5) => tx_pd_credits_available(5),
      tx_pd_credits_available(4) => tx_pd_credits_available(4),
      tx_pd_credits_available(3) => tx_pd_credits_available(3),
      tx_pd_credits_available(2) => tx_pd_credits_available(2),
      tx_pd_credits_available(1) => tx_pd_credits_available(1),
      tx_pd_credits_available(0) => tx_pd_credits_available(0)
    );
  rx_bridge : pcie_blk_plus_ll_rx
    port map (
      rx_err_cpl_ur_n => rx_err_cpl_ur_n,
      trn_rsrc_rdy_n => trn_rsrc_rdy_n,
      l0_stats_tlp_received => l0_stats_tlp_received,
      clk => clk,
      llk_rx_eof_n => llk_rx_eof_n,
      rst_n => rst_n,
      llk_rx_src_rdy_n => llk_rx_src_rdy_n,
      trn_rerrfwd_n => trn_rerrfwd_n,
      llk_rx_dst_cont_req_n => llk_rx_dst_cont_req_n,
      trn_rnp_ok_n => NLW_rx_bridge_trn_rnp_ok_n_UNCONNECTED,
      err_tlp_malformed => err_tlp_malformed,
      err_tlp_ur_lock => err_tlp_ur_lock,
      trn_rsof_n => trn_rsof_n,
      io_space_enable => io_space_enable,
      llk_rx_dst_req_n => llk_rx_dst_req_n,
      llk_rx_src_last_req_n => llk_rx_src_last_req_n,
      trn_rcpl_streaming_n => trn_rcpl_streaming_n,
      llk_rx_sof_n => llk_rx_sof_n,
      rx_err_cpl_ep_n => rx_err_cpl_ep_n,
      err_tlp_uc => err_tlp_uc,
      trn_rsrc_dsc_n => trn_rsrc_dsc_n,
      err_tlp_ur => err_tlp_ur,
      llk_rx_src_dsc_n => NLW_rx_bridge_llk_rx_src_dsc_n_UNCONNECTED,
      trn_rdst_rdy_n => trn_rdst_rdy_n,
      rx_err_cpl_abort_n => rx_err_cpl_abort_n,
      err_tlp_p => err_tlp_p,
      mem_space_enable => mem_space_enable,
      rx_err_ep_n => rx_err_ep_n,
      rx_ch_credits_received_inc => rx_ch_credits_received_inc,
      trn_reof_n => trn_reof_n,
      trn_lnk_up_n => trn_lnk_up_n,
      err_tlp_cpl_header(47) => err_tlp_cpl_header(47),
      err_tlp_cpl_header(46) => err_tlp_cpl_header(46),
      err_tlp_cpl_header(45) => err_tlp_cpl_header(45),
      err_tlp_cpl_header(44) => err_tlp_cpl_header(44),
      err_tlp_cpl_header(43) => err_tlp_cpl_header(43),
      err_tlp_cpl_header(42) => err_tlp_cpl_header(42),
      err_tlp_cpl_header(41) => err_tlp_cpl_header(41),
      err_tlp_cpl_header(40) => err_tlp_cpl_header(40),
      err_tlp_cpl_header(39) => err_tlp_cpl_header(39),
      err_tlp_cpl_header(38) => err_tlp_cpl_header(38),
      err_tlp_cpl_header(37) => err_tlp_cpl_header(37),
      err_tlp_cpl_header(36) => err_tlp_cpl_header(36),
      err_tlp_cpl_header(35) => err_tlp_cpl_header(35),
      err_tlp_cpl_header(34) => err_tlp_cpl_header(34),
      err_tlp_cpl_header(33) => err_tlp_cpl_header(33),
      err_tlp_cpl_header(32) => err_tlp_cpl_header(32),
      err_tlp_cpl_header(31) => err_tlp_cpl_header(31),
      err_tlp_cpl_header(30) => err_tlp_cpl_header(30),
      err_tlp_cpl_header(29) => err_tlp_cpl_header(29),
      err_tlp_cpl_header(28) => err_tlp_cpl_header(28),
      err_tlp_cpl_header(27) => err_tlp_cpl_header(27),
      err_tlp_cpl_header(26) => err_tlp_cpl_header(26),
      err_tlp_cpl_header(25) => err_tlp_cpl_header(25),
      err_tlp_cpl_header(24) => err_tlp_cpl_header(24),
      err_tlp_cpl_header(23) => err_tlp_cpl_header(23),
      err_tlp_cpl_header(22) => err_tlp_cpl_header(22),
      err_tlp_cpl_header(21) => err_tlp_cpl_header(21),
      err_tlp_cpl_header(20) => err_tlp_cpl_header(20),
      err_tlp_cpl_header(19) => err_tlp_cpl_header(19),
      err_tlp_cpl_header(18) => err_tlp_cpl_header(18),
      err_tlp_cpl_header(17) => err_tlp_cpl_header(17),
      err_tlp_cpl_header(16) => err_tlp_cpl_header(16),
      err_tlp_cpl_header(15) => err_tlp_cpl_header(15),
      err_tlp_cpl_header(14) => err_tlp_cpl_header(14),
      err_tlp_cpl_header(13) => err_tlp_cpl_header(13),
      err_tlp_cpl_header(12) => err_tlp_cpl_header(12),
      err_tlp_cpl_header(11) => err_tlp_cpl_header(11),
      err_tlp_cpl_header(10) => err_tlp_cpl_header(10),
      err_tlp_cpl_header(9) => err_tlp_cpl_header(9),
      err_tlp_cpl_header(8) => err_tlp_cpl_header(8),
      err_tlp_cpl_header(7) => err_tlp_cpl_header(7),
      err_tlp_cpl_header(6) => err_tlp_cpl_header(6),
      err_tlp_cpl_header(5) => err_tlp_cpl_header(5),
      err_tlp_cpl_header(4) => err_tlp_cpl_header(4),
      err_tlp_cpl_header(3) => err_tlp_cpl_header(3),
      err_tlp_cpl_header(2) => err_tlp_cpl_header(2),
      err_tlp_cpl_header(1) => err_tlp_cpl_header(1),
      err_tlp_cpl_header(0) => err_tlp_cpl_header(0),
      trn_rrem_n(7) => trn_rrem_n(7),
      trn_rrem_n(6) => trn_rrem_n(6),
      trn_rrem_n(5) => trn_rrem_n(5),
      trn_rrem_n(4) => trn_rrem_n(4),
      trn_rrem_n(3) => trn_rrem_n(3),
      trn_rrem_n(2) => trn_rrem_n(2),
      trn_rrem_n(1) => trn_rrem_n(1),
      trn_rrem_n(0) => trn_rrem_n(0),
      llk_rx_data_d(63) => llk_rx_data_d(63),
      llk_rx_data_d(62) => llk_rx_data_d(62),
      llk_rx_data_d(61) => llk_rx_data_d(61),
      llk_rx_data_d(60) => llk_rx_data_d(60),
      llk_rx_data_d(59) => llk_rx_data_d(59),
      llk_rx_data_d(58) => llk_rx_data_d(58),
      llk_rx_data_d(57) => llk_rx_data_d(57),
      llk_rx_data_d(56) => llk_rx_data_d(56),
      llk_rx_data_d(55) => llk_rx_data_d(55),
      llk_rx_data_d(54) => llk_rx_data_d(54),
      llk_rx_data_d(53) => llk_rx_data_d(53),
      llk_rx_data_d(52) => llk_rx_data_d(52),
      llk_rx_data_d(51) => llk_rx_data_d(51),
      llk_rx_data_d(50) => llk_rx_data_d(50),
      llk_rx_data_d(49) => llk_rx_data_d(49),
      llk_rx_data_d(48) => llk_rx_data_d(48),
      llk_rx_data_d(47) => llk_rx_data_d(47),
      llk_rx_data_d(46) => llk_rx_data_d(46),
      llk_rx_data_d(45) => llk_rx_data_d(45),
      llk_rx_data_d(44) => llk_rx_data_d(44),
      llk_rx_data_d(43) => llk_rx_data_d(43),
      llk_rx_data_d(42) => llk_rx_data_d(42),
      llk_rx_data_d(41) => llk_rx_data_d(41),
      llk_rx_data_d(40) => llk_rx_data_d(40),
      llk_rx_data_d(39) => llk_rx_data_d(39),
      llk_rx_data_d(38) => llk_rx_data_d(38),
      llk_rx_data_d(37) => llk_rx_data_d(37),
      llk_rx_data_d(36) => llk_rx_data_d(36),
      llk_rx_data_d(35) => llk_rx_data_d(35),
      llk_rx_data_d(34) => llk_rx_data_d(34),
      llk_rx_data_d(33) => llk_rx_data_d(33),
      llk_rx_data_d(32) => llk_rx_data_d(32),
      llk_rx_data_d(31) => llk_rx_data_d(31),
      llk_rx_data_d(30) => llk_rx_data_d(30),
      llk_rx_data_d(29) => llk_rx_data_d(29),
      llk_rx_data_d(28) => llk_rx_data_d(28),
      llk_rx_data_d(27) => llk_rx_data_d(27),
      llk_rx_data_d(26) => llk_rx_data_d(26),
      llk_rx_data_d(25) => llk_rx_data_d(25),
      llk_rx_data_d(24) => llk_rx_data_d(24),
      llk_rx_data_d(23) => llk_rx_data_d(23),
      llk_rx_data_d(22) => llk_rx_data_d(22),
      llk_rx_data_d(21) => llk_rx_data_d(21),
      llk_rx_data_d(20) => llk_rx_data_d(20),
      llk_rx_data_d(19) => llk_rx_data_d(19),
      llk_rx_data_d(18) => llk_rx_data_d(18),
      llk_rx_data_d(17) => llk_rx_data_d(17),
      llk_rx_data_d(16) => llk_rx_data_d(16),
      llk_rx_data_d(15) => llk_rx_data_d(15),
      llk_rx_data_d(14) => llk_rx_data_d(14),
      llk_rx_data_d(13) => llk_rx_data_d(13),
      llk_rx_data_d(12) => llk_rx_data_d(12),
      llk_rx_data_d(11) => llk_rx_data_d(11),
      llk_rx_data_d(10) => llk_rx_data_d(10),
      llk_rx_data_d(9) => llk_rx_data_d(9),
      llk_rx_data_d(8) => llk_rx_data_d(8),
      llk_rx_data_d(7) => llk_rx_data_d(7),
      llk_rx_data_d(6) => llk_rx_data_d(6),
      llk_rx_data_d(5) => llk_rx_data_d(5),
      llk_rx_data_d(4) => llk_rx_data_d(4),
      llk_rx_data_d(3) => llk_rx_data_d(3),
      llk_rx_data_d(2) => llk_rx_data_d(2),
      llk_rx_data_d(1) => llk_rx_data_d(1),
      llk_rx_data_d(0) => llk_rx_data_d(0),
      trn_rbar_hit_n(6) => trn_rbar_hit_n(6),
      trn_rbar_hit_n(5) => trn_rbar_hit_n(5),
      trn_rbar_hit_n(4) => trn_rbar_hit_n(4),
      trn_rbar_hit_n(3) => trn_rbar_hit_n(3),
      trn_rbar_hit_n(2) => trn_rbar_hit_n(2),
      trn_rbar_hit_n(1) => trn_rbar_hit_n(1),
      trn_rbar_hit_n(0) => trn_rbar_hit_n(0),
      llk_rx_ch_fifo(1) => llk_rx_ch_fifo(1),
      llk_rx_ch_fifo(0) => llk_rx_ch_fifo(0),
      llk_rx_ch_tc(2) => llk_rx_ch_tc(2),
      llk_rx_ch_tc(1) => llk_rx_ch_tc(1),
      llk_rx_ch_tc(0) => llk_rx_ch_tc(0),
      trn_rd(63) => trn_rd(63),
      trn_rd(62) => trn_rd(62),
      trn_rd(61) => trn_rd(61),
      trn_rd(60) => trn_rd(60),
      trn_rd(59) => trn_rd(59),
      trn_rd(58) => trn_rd(58),
      trn_rd(57) => trn_rd(57),
      trn_rd(56) => trn_rd(56),
      trn_rd(55) => trn_rd(55),
      trn_rd(54) => trn_rd(54),
      trn_rd(53) => trn_rd(53),
      trn_rd(52) => trn_rd(52),
      trn_rd(51) => trn_rd(51),
      trn_rd(50) => trn_rd(50),
      trn_rd(49) => trn_rd(49),
      trn_rd(48) => trn_rd(48),
      trn_rd(47) => trn_rd(47),
      trn_rd(46) => trn_rd(46),
      trn_rd(45) => trn_rd(45),
      trn_rd(44) => trn_rd(44),
      trn_rd(43) => trn_rd(43),
      trn_rd(42) => trn_rd(42),
      trn_rd(41) => trn_rd(41),
      trn_rd(40) => trn_rd(40),
      trn_rd(39) => trn_rd(39),
      trn_rd(38) => trn_rd(38),
      trn_rd(37) => trn_rd(37),
      trn_rd(36) => trn_rd(36),
      trn_rd(35) => trn_rd(35),
      trn_rd(34) => trn_rd(34),
      trn_rd(33) => trn_rd(33),
      trn_rd(32) => trn_rd(32),
      trn_rd(31) => trn_rd(31),
      trn_rd(30) => trn_rd(30),
      trn_rd(29) => trn_rd(29),
      trn_rd(28) => trn_rd(28),
      trn_rd(27) => trn_rd(27),
      trn_rd(26) => trn_rd(26),
      trn_rd(25) => trn_rd(25),
      trn_rd(24) => trn_rd(24),
      trn_rd(23) => trn_rd(23),
      trn_rd(22) => trn_rd(22),
      trn_rd(21) => trn_rd(21),
      trn_rd(20) => trn_rd(20),
      trn_rd(19) => trn_rd(19),
      trn_rd(18) => trn_rd(18),
      trn_rd(17) => trn_rd(17),
      trn_rd(16) => trn_rd(16),
      trn_rd(15) => trn_rd(15),
      trn_rd(14) => trn_rd(14),
      trn_rd(13) => trn_rd(13),
      trn_rd(12) => trn_rd(12),
      trn_rd(11) => trn_rd(11),
      trn_rd(10) => trn_rd(10),
      trn_rd(9) => trn_rd(9),
      trn_rd(8) => trn_rd(8),
      trn_rd(7) => trn_rd(7),
      trn_rd(6) => trn_rd(6),
      trn_rd(5) => trn_rd(5),
      trn_rd(4) => trn_rd(4),
      trn_rd(3) => trn_rd(3),
      trn_rd(2) => trn_rd(2),
      trn_rd(1) => trn_rd(1),
      trn_rd(0) => trn_rd(0),
      llk_rx_ch_posted_available_n(7) => llk_rx_ch_posted_available_n(7),
      llk_rx_ch_posted_available_n(6) => llk_rx_ch_posted_available_n(6),
      llk_rx_ch_posted_available_n(5) => llk_rx_ch_posted_available_n(5),
      llk_rx_ch_posted_available_n(4) => llk_rx_ch_posted_available_n(4),
      llk_rx_ch_posted_available_n(3) => llk_rx_ch_posted_available_n(3),
      llk_rx_ch_posted_available_n(2) => llk_rx_ch_posted_available_n(2),
      llk_rx_ch_posted_available_n(1) => llk_rx_ch_posted_available_n(1),
      llk_rx_ch_posted_available_n(0) => llk_rx_ch_posted_available_n(0),
      cfg_device_number(4) => cfg_device_number(4),
      cfg_device_number(3) => cfg_device_number(3),
      cfg_device_number(2) => cfg_device_number(2),
      cfg_device_number(1) => cfg_device_number(1),
      cfg_device_number(0) => cfg_device_number(0),
      llk_rx_ch_non_posted_available_n(7) => llk_rx_ch_non_posted_available_n(7),
      llk_rx_ch_non_posted_available_n(6) => llk_rx_ch_non_posted_available_n(6),
      llk_rx_ch_non_posted_available_n(5) => llk_rx_ch_non_posted_available_n(5),
      llk_rx_ch_non_posted_available_n(4) => llk_rx_ch_non_posted_available_n(4),
      llk_rx_ch_non_posted_available_n(3) => llk_rx_ch_non_posted_available_n(3),
      llk_rx_ch_non_posted_available_n(2) => llk_rx_ch_non_posted_available_n(2),
      llk_rx_ch_non_posted_available_n(1) => llk_rx_ch_non_posted_available_n(1),
      llk_rx_ch_non_posted_available_n(0) => llk_rx_ch_non_posted_available_n(0),
      llk_rx_ch_completion_available_n(7) => llk_rx_ch_completion_available_n(7),
      llk_rx_ch_completion_available_n(6) => llk_rx_ch_completion_available_n(6),
      llk_rx_ch_completion_available_n(5) => llk_rx_ch_completion_available_n(5),
      llk_rx_ch_completion_available_n(4) => llk_rx_ch_completion_available_n(4),
      llk_rx_ch_completion_available_n(3) => llk_rx_ch_completion_available_n(3),
      llk_rx_ch_completion_available_n(2) => llk_rx_ch_completion_available_n(2),
      llk_rx_ch_completion_available_n(1) => llk_rx_ch_completion_available_n(1),
      llk_rx_ch_completion_available_n(0) => llk_rx_ch_completion_available_n(0),
      llk_rx_valid_n(1) => llk_rx_valid_n(1),
      llk_rx_valid_n(0) => llk_rx_valid_n(0),
      llk_rx_preferred_type(15) => llk_rx_preferred_type(15),
      llk_rx_preferred_type(14) => llk_rx_preferred_type(14),
      llk_rx_preferred_type(13) => llk_rx_preferred_type(13),
      llk_rx_preferred_type(12) => llk_rx_preferred_type(12),
      llk_rx_preferred_type(11) => llk_rx_preferred_type(11),
      llk_rx_preferred_type(10) => llk_rx_preferred_type(10),
      llk_rx_preferred_type(9) => llk_rx_preferred_type(9),
      llk_rx_preferred_type(8) => llk_rx_preferred_type(8),
      llk_rx_preferred_type(7) => llk_rx_preferred_type(7),
      llk_rx_preferred_type(6) => llk_rx_preferred_type(6),
      llk_rx_preferred_type(5) => llk_rx_preferred_type(5),
      llk_rx_preferred_type(4) => llk_rx_preferred_type(4),
      llk_rx_preferred_type(3) => llk_rx_preferred_type(3),
      llk_rx_preferred_type(2) => llk_rx_preferred_type(2),
      llk_rx_preferred_type(1) => llk_rx_preferred_type(1),
      llk_rx_preferred_type(0) => llk_rx_preferred_type(0),
      llk_tc_status(7) => llk_tc_status(7),
      llk_tc_status(6) => llk_tc_status(6),
      llk_tc_status(5) => llk_tc_status(5),
      llk_tc_status(4) => llk_tc_status(4),
      llk_tc_status(3) => llk_tc_status(3),
      llk_tc_status(2) => llk_tc_status(2),
      llk_tc_status(1) => llk_tc_status(1),
      llk_tc_status(0) => llk_tc_status(0),
      rx_ch_credits_received(7) => rx_ch_credits_received(7),
      rx_ch_credits_received(6) => rx_ch_credits_received(6),
      rx_ch_credits_received(5) => rx_ch_credits_received(5),
      rx_ch_credits_received(4) => rx_ch_credits_received(4),
      rx_ch_credits_received(3) => rx_ch_credits_received(3),
      rx_ch_credits_received(2) => rx_ch_credits_received(2),
      rx_ch_credits_received(1) => rx_ch_credits_received(1),
      rx_ch_credits_received(0) => rx_ch_credits_received(0),
      cfg_rx_xrom(31) => cfg_rx_xrom(31),
      cfg_rx_xrom(30) => cfg_rx_xrom(30),
      cfg_rx_xrom(29) => cfg_rx_xrom(29),
      cfg_rx_xrom(28) => cfg_rx_xrom(28),
      cfg_rx_xrom(27) => cfg_rx_xrom(27),
      cfg_rx_xrom(26) => cfg_rx_xrom(26),
      cfg_rx_xrom(25) => cfg_rx_xrom(25),
      cfg_rx_xrom(24) => cfg_rx_xrom(24),
      cfg_rx_xrom(23) => cfg_rx_xrom(23),
      cfg_rx_xrom(22) => cfg_rx_xrom(22),
      cfg_rx_xrom(21) => cfg_rx_xrom(21),
      cfg_rx_xrom(20) => cfg_rx_xrom(20),
      cfg_rx_xrom(19) => cfg_rx_xrom(19),
      cfg_rx_xrom(18) => cfg_rx_xrom(18),
      cfg_rx_xrom(17) => cfg_rx_xrom(17),
      cfg_rx_xrom(16) => cfg_rx_xrom(16),
      cfg_rx_xrom(15) => cfg_rx_xrom(15),
      cfg_rx_xrom(14) => cfg_rx_xrom(14),
      cfg_rx_xrom(13) => cfg_rx_xrom(13),
      cfg_rx_xrom(12) => cfg_rx_xrom(12),
      cfg_rx_xrom(11) => cfg_rx_xrom(11),
      cfg_rx_xrom(10) => cfg_rx_xrom(10),
      cfg_rx_xrom(9) => cfg_rx_xrom(9),
      cfg_rx_xrom(8) => cfg_rx_xrom(8),
      cfg_rx_xrom(7) => cfg_rx_xrom(7),
      cfg_rx_xrom(6) => cfg_rx_xrom(6),
      cfg_rx_xrom(5) => cfg_rx_xrom(5),
      cfg_rx_xrom(4) => cfg_rx_xrom(4),
      cfg_rx_xrom(3) => cfg_rx_xrom(3),
      cfg_rx_xrom(2) => cfg_rx_xrom(2),
      cfg_rx_xrom(1) => cfg_rx_xrom(1),
      cfg_rx_xrom(0) => cfg_rx_xrom(0),
      max_payload_size(2) => max_payload_size(2),
      max_payload_size(1) => max_payload_size(1),
      max_payload_size(0) => max_payload_size(0),
      cfg_bus_number(7) => cfg_bus_number(7),
      cfg_bus_number(6) => cfg_bus_number(6),
      cfg_bus_number(5) => cfg_bus_number(5),
      cfg_bus_number(4) => cfg_bus_number(4),
      cfg_bus_number(3) => cfg_bus_number(3),
      cfg_bus_number(2) => cfg_bus_number(2),
      cfg_bus_number(1) => cfg_bus_number(1),
      cfg_bus_number(0) => cfg_bus_number(0),
      cfg_pmcsr(15) => cfg_pmcsr(15),
      cfg_pmcsr(14) => cfg_pmcsr(14),
      cfg_pmcsr(13) => cfg_pmcsr(13),
      cfg_pmcsr(12) => cfg_pmcsr(12),
      cfg_pmcsr(11) => cfg_pmcsr(11),
      cfg_pmcsr(10) => cfg_pmcsr(10),
      cfg_pmcsr(9) => cfg_pmcsr(9),
      cfg_pmcsr(8) => cfg_pmcsr(8),
      cfg_pmcsr(7) => cfg_pmcsr(7),
      cfg_pmcsr(6) => cfg_pmcsr(6),
      cfg_pmcsr(5) => cfg_pmcsr(5),
      cfg_pmcsr(4) => cfg_pmcsr(4),
      cfg_pmcsr(3) => cfg_pmcsr(3),
      cfg_pmcsr(2) => cfg_pmcsr(2),
      cfg_pmcsr(1) => cfg_pmcsr(1),
      cfg_pmcsr(0) => cfg_pmcsr(0),
      cfg_dcommand(15) => cfg_dcommand(15),
      cfg_dcommand(14) => cfg_dcommand(14),
      cfg_dcommand(13) => cfg_dcommand(13),
      cfg_dcommand(12) => cfg_dcommand(12),
      cfg_dcommand(11) => cfg_dcommand(11),
      cfg_dcommand(10) => cfg_dcommand(10),
      cfg_dcommand(9) => cfg_dcommand(9),
      cfg_dcommand(8) => cfg_dcommand(8),
      cfg_dcommand(7) => cfg_dcommand(7),
      cfg_dcommand(6) => cfg_dcommand(6),
      cfg_dcommand(5) => cfg_dcommand(5),
      cfg_dcommand(4) => cfg_dcommand(4),
      cfg_dcommand(3) => cfg_dcommand(3),
      cfg_dcommand(2) => cfg_dcommand(2),
      cfg_dcommand(1) => cfg_dcommand(1),
      cfg_dcommand(0) => cfg_dcommand(0),
      cfg_function_number(2) => cfg_function_number(2),
      cfg_function_number(1) => cfg_function_number(1),
      cfg_function_number(0) => cfg_function_number(0),
      cfg_rx_bar0(31) => cfg_rx_bar0(31),
      cfg_rx_bar0(30) => cfg_rx_bar0(30),
      cfg_rx_bar0(29) => cfg_rx_bar0(29),
      cfg_rx_bar0(28) => cfg_rx_bar0(28),
      cfg_rx_bar0(27) => cfg_rx_bar0(27),
      cfg_rx_bar0(26) => cfg_rx_bar0(26),
      cfg_rx_bar0(25) => cfg_rx_bar0(25),
      cfg_rx_bar0(24) => cfg_rx_bar0(24),
      cfg_rx_bar0(23) => cfg_rx_bar0(23),
      cfg_rx_bar0(22) => cfg_rx_bar0(22),
      cfg_rx_bar0(21) => cfg_rx_bar0(21),
      cfg_rx_bar0(20) => cfg_rx_bar0(20),
      cfg_rx_bar0(19) => cfg_rx_bar0(19),
      cfg_rx_bar0(18) => cfg_rx_bar0(18),
      cfg_rx_bar0(17) => cfg_rx_bar0(17),
      cfg_rx_bar0(16) => cfg_rx_bar0(16),
      cfg_rx_bar0(15) => cfg_rx_bar0(15),
      cfg_rx_bar0(14) => cfg_rx_bar0(14),
      cfg_rx_bar0(13) => cfg_rx_bar0(13),
      cfg_rx_bar0(12) => cfg_rx_bar0(12),
      cfg_rx_bar0(11) => cfg_rx_bar0(11),
      cfg_rx_bar0(10) => cfg_rx_bar0(10),
      cfg_rx_bar0(9) => cfg_rx_bar0(9),
      cfg_rx_bar0(8) => cfg_rx_bar0(8),
      cfg_rx_bar0(7) => cfg_rx_bar0(7),
      cfg_rx_bar0(6) => cfg_rx_bar0(6),
      cfg_rx_bar0(5) => cfg_rx_bar0(5),
      cfg_rx_bar0(4) => cfg_rx_bar0(4),
      cfg_rx_bar0(3) => cfg_rx_bar0(3),
      cfg_rx_bar0(2) => cfg_rx_bar0(2),
      cfg_rx_bar0(1) => cfg_rx_bar0(1),
      cfg_rx_bar0(0) => cfg_rx_bar0(0),
      cfg_rx_bar1(31) => cfg_rx_bar1(31),
      cfg_rx_bar1(30) => cfg_rx_bar1(30),
      cfg_rx_bar1(29) => cfg_rx_bar1(29),
      cfg_rx_bar1(28) => cfg_rx_bar1(28),
      cfg_rx_bar1(27) => cfg_rx_bar1(27),
      cfg_rx_bar1(26) => cfg_rx_bar1(26),
      cfg_rx_bar1(25) => cfg_rx_bar1(25),
      cfg_rx_bar1(24) => cfg_rx_bar1(24),
      cfg_rx_bar1(23) => cfg_rx_bar1(23),
      cfg_rx_bar1(22) => cfg_rx_bar1(22),
      cfg_rx_bar1(21) => cfg_rx_bar1(21),
      cfg_rx_bar1(20) => cfg_rx_bar1(20),
      cfg_rx_bar1(19) => cfg_rx_bar1(19),
      cfg_rx_bar1(18) => cfg_rx_bar1(18),
      cfg_rx_bar1(17) => cfg_rx_bar1(17),
      cfg_rx_bar1(16) => cfg_rx_bar1(16),
      cfg_rx_bar1(15) => cfg_rx_bar1(15),
      cfg_rx_bar1(14) => cfg_rx_bar1(14),
      cfg_rx_bar1(13) => cfg_rx_bar1(13),
      cfg_rx_bar1(12) => cfg_rx_bar1(12),
      cfg_rx_bar1(11) => cfg_rx_bar1(11),
      cfg_rx_bar1(10) => cfg_rx_bar1(10),
      cfg_rx_bar1(9) => cfg_rx_bar1(9),
      cfg_rx_bar1(8) => cfg_rx_bar1(8),
      cfg_rx_bar1(7) => cfg_rx_bar1(7),
      cfg_rx_bar1(6) => cfg_rx_bar1(6),
      cfg_rx_bar1(5) => cfg_rx_bar1(5),
      cfg_rx_bar1(4) => cfg_rx_bar1(4),
      cfg_rx_bar1(3) => cfg_rx_bar1(3),
      cfg_rx_bar1(2) => cfg_rx_bar1(2),
      cfg_rx_bar1(1) => cfg_rx_bar1(1),
      cfg_rx_bar1(0) => cfg_rx_bar1(0),
      cfg_rx_bar2(31) => cfg_rx_bar2(31),
      cfg_rx_bar2(30) => cfg_rx_bar2(30),
      cfg_rx_bar2(29) => cfg_rx_bar2(29),
      cfg_rx_bar2(28) => cfg_rx_bar2(28),
      cfg_rx_bar2(27) => cfg_rx_bar2(27),
      cfg_rx_bar2(26) => cfg_rx_bar2(26),
      cfg_rx_bar2(25) => cfg_rx_bar2(25),
      cfg_rx_bar2(24) => cfg_rx_bar2(24),
      cfg_rx_bar2(23) => cfg_rx_bar2(23),
      cfg_rx_bar2(22) => cfg_rx_bar2(22),
      cfg_rx_bar2(21) => cfg_rx_bar2(21),
      cfg_rx_bar2(20) => cfg_rx_bar2(20),
      cfg_rx_bar2(19) => cfg_rx_bar2(19),
      cfg_rx_bar2(18) => cfg_rx_bar2(18),
      cfg_rx_bar2(17) => cfg_rx_bar2(17),
      cfg_rx_bar2(16) => cfg_rx_bar2(16),
      cfg_rx_bar2(15) => cfg_rx_bar2(15),
      cfg_rx_bar2(14) => cfg_rx_bar2(14),
      cfg_rx_bar2(13) => cfg_rx_bar2(13),
      cfg_rx_bar2(12) => cfg_rx_bar2(12),
      cfg_rx_bar2(11) => cfg_rx_bar2(11),
      cfg_rx_bar2(10) => cfg_rx_bar2(10),
      cfg_rx_bar2(9) => cfg_rx_bar2(9),
      cfg_rx_bar2(8) => cfg_rx_bar2(8),
      cfg_rx_bar2(7) => cfg_rx_bar2(7),
      cfg_rx_bar2(6) => cfg_rx_bar2(6),
      cfg_rx_bar2(5) => cfg_rx_bar2(5),
      cfg_rx_bar2(4) => cfg_rx_bar2(4),
      cfg_rx_bar2(3) => cfg_rx_bar2(3),
      cfg_rx_bar2(2) => cfg_rx_bar2(2),
      cfg_rx_bar2(1) => cfg_rx_bar2(1),
      cfg_rx_bar2(0) => cfg_rx_bar2(0),
      cfg_rx_bar3(31) => cfg_rx_bar3(31),
      cfg_rx_bar3(30) => cfg_rx_bar3(30),
      cfg_rx_bar3(29) => cfg_rx_bar3(29),
      cfg_rx_bar3(28) => cfg_rx_bar3(28),
      cfg_rx_bar3(27) => cfg_rx_bar3(27),
      cfg_rx_bar3(26) => cfg_rx_bar3(26),
      cfg_rx_bar3(25) => cfg_rx_bar3(25),
      cfg_rx_bar3(24) => cfg_rx_bar3(24),
      cfg_rx_bar3(23) => cfg_rx_bar3(23),
      cfg_rx_bar3(22) => cfg_rx_bar3(22),
      cfg_rx_bar3(21) => cfg_rx_bar3(21),
      cfg_rx_bar3(20) => cfg_rx_bar3(20),
      cfg_rx_bar3(19) => cfg_rx_bar3(19),
      cfg_rx_bar3(18) => cfg_rx_bar3(18),
      cfg_rx_bar3(17) => cfg_rx_bar3(17),
      cfg_rx_bar3(16) => cfg_rx_bar3(16),
      cfg_rx_bar3(15) => cfg_rx_bar3(15),
      cfg_rx_bar3(14) => cfg_rx_bar3(14),
      cfg_rx_bar3(13) => cfg_rx_bar3(13),
      cfg_rx_bar3(12) => cfg_rx_bar3(12),
      cfg_rx_bar3(11) => cfg_rx_bar3(11),
      cfg_rx_bar3(10) => cfg_rx_bar3(10),
      cfg_rx_bar3(9) => cfg_rx_bar3(9),
      cfg_rx_bar3(8) => cfg_rx_bar3(8),
      cfg_rx_bar3(7) => cfg_rx_bar3(7),
      cfg_rx_bar3(6) => cfg_rx_bar3(6),
      cfg_rx_bar3(5) => cfg_rx_bar3(5),
      cfg_rx_bar3(4) => cfg_rx_bar3(4),
      cfg_rx_bar3(3) => cfg_rx_bar3(3),
      cfg_rx_bar3(2) => cfg_rx_bar3(2),
      cfg_rx_bar3(1) => cfg_rx_bar3(1),
      cfg_rx_bar3(0) => cfg_rx_bar3(0),
      cfg_rx_bar4(31) => cfg_rx_bar4(31),
      cfg_rx_bar4(30) => cfg_rx_bar4(30),
      cfg_rx_bar4(29) => cfg_rx_bar4(29),
      cfg_rx_bar4(28) => cfg_rx_bar4(28),
      cfg_rx_bar4(27) => cfg_rx_bar4(27),
      cfg_rx_bar4(26) => cfg_rx_bar4(26),
      cfg_rx_bar4(25) => cfg_rx_bar4(25),
      cfg_rx_bar4(24) => cfg_rx_bar4(24),
      cfg_rx_bar4(23) => cfg_rx_bar4(23),
      cfg_rx_bar4(22) => cfg_rx_bar4(22),
      cfg_rx_bar4(21) => cfg_rx_bar4(21),
      cfg_rx_bar4(20) => cfg_rx_bar4(20),
      cfg_rx_bar4(19) => cfg_rx_bar4(19),
      cfg_rx_bar4(18) => cfg_rx_bar4(18),
      cfg_rx_bar4(17) => cfg_rx_bar4(17),
      cfg_rx_bar4(16) => cfg_rx_bar4(16),
      cfg_rx_bar4(15) => cfg_rx_bar4(15),
      cfg_rx_bar4(14) => cfg_rx_bar4(14),
      cfg_rx_bar4(13) => cfg_rx_bar4(13),
      cfg_rx_bar4(12) => cfg_rx_bar4(12),
      cfg_rx_bar4(11) => cfg_rx_bar4(11),
      cfg_rx_bar4(10) => cfg_rx_bar4(10),
      cfg_rx_bar4(9) => cfg_rx_bar4(9),
      cfg_rx_bar4(8) => cfg_rx_bar4(8),
      cfg_rx_bar4(7) => cfg_rx_bar4(7),
      cfg_rx_bar4(6) => cfg_rx_bar4(6),
      cfg_rx_bar4(5) => cfg_rx_bar4(5),
      cfg_rx_bar4(4) => cfg_rx_bar4(4),
      cfg_rx_bar4(3) => cfg_rx_bar4(3),
      cfg_rx_bar4(2) => cfg_rx_bar4(2),
      cfg_rx_bar4(1) => cfg_rx_bar4(1),
      cfg_rx_bar4(0) => cfg_rx_bar4(0),
      cfg_rx_bar5(31) => cfg_rx_bar5(31),
      cfg_rx_bar5(30) => cfg_rx_bar5(30),
      cfg_rx_bar5(29) => cfg_rx_bar5(29),
      cfg_rx_bar5(28) => cfg_rx_bar5(28),
      cfg_rx_bar5(27) => cfg_rx_bar5(27),
      cfg_rx_bar5(26) => cfg_rx_bar5(26),
      cfg_rx_bar5(25) => cfg_rx_bar5(25),
      cfg_rx_bar5(24) => cfg_rx_bar5(24),
      cfg_rx_bar5(23) => cfg_rx_bar5(23),
      cfg_rx_bar5(22) => cfg_rx_bar5(22),
      cfg_rx_bar5(21) => cfg_rx_bar5(21),
      cfg_rx_bar5(20) => cfg_rx_bar5(20),
      cfg_rx_bar5(19) => cfg_rx_bar5(19),
      cfg_rx_bar5(18) => cfg_rx_bar5(18),
      cfg_rx_bar5(17) => cfg_rx_bar5(17),
      cfg_rx_bar5(16) => cfg_rx_bar5(16),
      cfg_rx_bar5(15) => cfg_rx_bar5(15),
      cfg_rx_bar5(14) => cfg_rx_bar5(14),
      cfg_rx_bar5(13) => cfg_rx_bar5(13),
      cfg_rx_bar5(12) => cfg_rx_bar5(12),
      cfg_rx_bar5(11) => cfg_rx_bar5(11),
      cfg_rx_bar5(10) => cfg_rx_bar5(10),
      cfg_rx_bar5(9) => cfg_rx_bar5(9),
      cfg_rx_bar5(8) => cfg_rx_bar5(8),
      cfg_rx_bar5(7) => cfg_rx_bar5(7),
      cfg_rx_bar5(6) => cfg_rx_bar5(6),
      cfg_rx_bar5(5) => cfg_rx_bar5(5),
      cfg_rx_bar5(4) => cfg_rx_bar5(4),
      cfg_rx_bar5(3) => cfg_rx_bar5(3),
      cfg_rx_bar5(2) => cfg_rx_bar5(2),
      cfg_rx_bar5(1) => cfg_rx_bar5(1),
      cfg_rx_bar5(0) => cfg_rx_bar5(0),
      llk_rx_data(63) => llk_rx_data(63),
      llk_rx_data(62) => llk_rx_data(62),
      llk_rx_data(61) => llk_rx_data(61),
      llk_rx_data(60) => llk_rx_data(60),
      llk_rx_data(59) => llk_rx_data(59),
      llk_rx_data(58) => llk_rx_data(58),
      llk_rx_data(57) => llk_rx_data(57),
      llk_rx_data(56) => llk_rx_data(56),
      llk_rx_data(55) => llk_rx_data(55),
      llk_rx_data(54) => llk_rx_data(54),
      llk_rx_data(53) => llk_rx_data(53),
      llk_rx_data(52) => llk_rx_data(52),
      llk_rx_data(51) => llk_rx_data(51),
      llk_rx_data(50) => llk_rx_data(50),
      llk_rx_data(49) => llk_rx_data(49),
      llk_rx_data(48) => llk_rx_data(48),
      llk_rx_data(47) => llk_rx_data(47),
      llk_rx_data(46) => llk_rx_data(46),
      llk_rx_data(45) => llk_rx_data(45),
      llk_rx_data(44) => llk_rx_data(44),
      llk_rx_data(43) => llk_rx_data(43),
      llk_rx_data(42) => llk_rx_data(42),
      llk_rx_data(41) => llk_rx_data(41),
      llk_rx_data(40) => llk_rx_data(40),
      llk_rx_data(39) => llk_rx_data(39),
      llk_rx_data(38) => llk_rx_data(38),
      llk_rx_data(37) => llk_rx_data(37),
      llk_rx_data(36) => llk_rx_data(36),
      llk_rx_data(35) => llk_rx_data(35),
      llk_rx_data(34) => llk_rx_data(34),
      llk_rx_data(33) => llk_rx_data(33),
      llk_rx_data(32) => llk_rx_data(32),
      llk_rx_data(31) => llk_rx_data(31),
      llk_rx_data(30) => llk_rx_data(30),
      llk_rx_data(29) => llk_rx_data(29),
      llk_rx_data(28) => llk_rx_data(28),
      llk_rx_data(27) => llk_rx_data(27),
      llk_rx_data(26) => llk_rx_data(26),
      llk_rx_data(25) => llk_rx_data(25),
      llk_rx_data(24) => llk_rx_data(24),
      llk_rx_data(23) => llk_rx_data(23),
      llk_rx_data(22) => llk_rx_data(22),
      llk_rx_data(21) => llk_rx_data(21),
      llk_rx_data(20) => llk_rx_data(20),
      llk_rx_data(19) => llk_rx_data(19),
      llk_rx_data(18) => llk_rx_data(18),
      llk_rx_data(17) => llk_rx_data(17),
      llk_rx_data(16) => llk_rx_data(16),
      llk_rx_data(15) => llk_rx_data(15),
      llk_rx_data(14) => llk_rx_data(14),
      llk_rx_data(13) => llk_rx_data(13),
      llk_rx_data(12) => llk_rx_data(12),
      llk_rx_data(11) => llk_rx_data(11),
      llk_rx_data(10) => llk_rx_data(10),
      llk_rx_data(9) => llk_rx_data(9),
      llk_rx_data(8) => llk_rx_data(8),
      llk_rx_data(7) => llk_rx_data(7),
      llk_rx_data(6) => llk_rx_data(6),
      llk_rx_data(5) => llk_rx_data(5),
      llk_rx_data(4) => llk_rx_data(4),
      llk_rx_data(3) => llk_rx_data(3),
      llk_rx_data(2) => llk_rx_data(2),
      llk_rx_data(1) => llk_rx_data(1),
      llk_rx_data(0) => llk_rx_data(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity TX_SYNC_GTP is
  port (
    RESET : in STD_LOGIC := 'X'; 
    USER_CLK : in STD_LOGIC := 'X'; 
    TXENPMAPHASEALIGN : out STD_LOGIC; 
    SYNC_DONE : out STD_LOGIC; 
    TXPMASETPHASE : out STD_LOGIC 
  );
end TX_SYNC_GTP;

architecture STRUCTURE of TX_SYNC_GTP is
  signal Mcount_sync_counter_r_cy_10_rt_15315 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_11_rt_15317 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_1_rt_15319 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_2_rt_15321 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_3_rt_15323 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_4_rt_15325 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_5_rt_15327 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_6_rt_15329 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_7_rt_15331 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_8_rt_15333 : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy_9_rt_15335 : STD_LOGIC; 
  signal Mcount_sync_counter_r_xor_12_rt_15337 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_1_rt_15340 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_2_rt_15342 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_3_rt_15344 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_4_rt_15346 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_5_rt_15348 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_6_rt_15350 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_7_rt_15352 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_cy_8_rt_15354 : STD_LOGIC; 
  signal Mcount_wait_before_sync_r_xor_9_rt_15356 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal RESET_inv : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal Result_8_1 : STD_LOGIC; 
  signal Result_9_1 : STD_LOGIC; 
  signal begin_r_15386 : STD_LOGIC; 
  signal next_phase_align_c : STD_LOGIC; 
  signal next_ready_c : STD_LOGIC; 
  signal next_wait_stable_c : STD_LOGIC; 
  signal NlwRenamedSig_OI_phase_align_r : STD_LOGIC; 
  signal phase_align_r_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_ready_r : STD_LOGIC; 
  signal wait_stable_r_15416 : STD_LOGIC; 
  signal wait_stable_r_inv : STD_LOGIC; 
  signal Mcount_sync_counter_r_cy : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Mcount_sync_counter_r_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_wait_before_sync_r_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_wait_before_sync_r_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal sync_counter_r : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal wait_before_sync_r : STD_LOGIC_VECTOR ( 9 downto 0 ); 
begin
  SYNC_DONE <= NlwRenamedSig_OI_ready_r;
  TXPMASETPHASE <= NlwRenamedSig_OI_phase_align_r;
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  wait_stable_r : FDR
    port map (
      C => USER_CLK,
      D => next_wait_stable_c,
      R => RESET,
      Q => wait_stable_r_15416
    );
  ready_r : FDR
    port map (
      C => USER_CLK,
      D => next_ready_c,
      R => RESET,
      Q => NlwRenamedSig_OI_ready_r
    );
  phase_align_r : FDR
    port map (
      C => USER_CLK,
      D => next_phase_align_c,
      R => RESET,
      Q => NlwRenamedSig_OI_phase_align_r
    );
  begin_r : FDR
    port map (
      C => USER_CLK,
      D => N1,
      R => RESET_inv,
      Q => begin_r_15386
    );
  wait_before_sync_r_0 : FDR
    port map (
      C => USER_CLK,
      D => Result(0),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(0)
    );
  wait_before_sync_r_1 : FDR
    port map (
      C => USER_CLK,
      D => Result(1),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(1)
    );
  wait_before_sync_r_2 : FDR
    port map (
      C => USER_CLK,
      D => Result(2),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(2)
    );
  wait_before_sync_r_3 : FDR
    port map (
      C => USER_CLK,
      D => Result(3),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(3)
    );
  wait_before_sync_r_4 : FDR
    port map (
      C => USER_CLK,
      D => Result(4),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(4)
    );
  wait_before_sync_r_5 : FDR
    port map (
      C => USER_CLK,
      D => Result(5),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(5)
    );
  wait_before_sync_r_6 : FDR
    port map (
      C => USER_CLK,
      D => Result(6),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(6)
    );
  wait_before_sync_r_7 : FDR
    port map (
      C => USER_CLK,
      D => Result(7),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(7)
    );
  wait_before_sync_r_8 : FDR
    port map (
      C => USER_CLK,
      D => Result(8),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(8)
    );
  wait_before_sync_r_9 : FDR
    port map (
      C => USER_CLK,
      D => Result(9),
      R => wait_stable_r_inv,
      Q => wait_before_sync_r(9)
    );
  sync_counter_r_0 : FDR
    port map (
      C => USER_CLK,
      D => Result_0_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(0)
    );
  sync_counter_r_1 : FDR
    port map (
      C => USER_CLK,
      D => Result_1_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(1)
    );
  sync_counter_r_2 : FDR
    port map (
      C => USER_CLK,
      D => Result_2_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(2)
    );
  sync_counter_r_3 : FDR
    port map (
      C => USER_CLK,
      D => Result_3_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(3)
    );
  sync_counter_r_4 : FDR
    port map (
      C => USER_CLK,
      D => Result_4_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(4)
    );
  sync_counter_r_5 : FDR
    port map (
      C => USER_CLK,
      D => Result_5_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(5)
    );
  sync_counter_r_6 : FDR
    port map (
      C => USER_CLK,
      D => Result_6_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(6)
    );
  sync_counter_r_7 : FDR
    port map (
      C => USER_CLK,
      D => Result_7_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(7)
    );
  sync_counter_r_8 : FDR
    port map (
      C => USER_CLK,
      D => Result_8_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(8)
    );
  sync_counter_r_9 : FDR
    port map (
      C => USER_CLK,
      D => Result_9_1,
      R => phase_align_r_inv,
      Q => sync_counter_r(9)
    );
  sync_counter_r_10 : FDR
    port map (
      C => USER_CLK,
      D => Result(10),
      R => phase_align_r_inv,
      Q => sync_counter_r(10)
    );
  sync_counter_r_11 : FDR
    port map (
      C => USER_CLK,
      D => Result(11),
      R => phase_align_r_inv,
      Q => sync_counter_r(11)
    );
  sync_counter_r_12 : FDR
    port map (
      C => USER_CLK,
      D => Result(12),
      R => phase_align_r_inv,
      Q => sync_counter_r(12)
    );
  Mcount_wait_before_sync_r_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_wait_before_sync_r_lut(0),
      O => Mcount_wait_before_sync_r_cy(0)
    );
  Mcount_wait_before_sync_r_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_wait_before_sync_r_lut(0),
      O => Result(0)
    );
  Mcount_wait_before_sync_r_cy_1_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(0),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_1_rt_15340,
      O => Mcount_wait_before_sync_r_cy(1)
    );
  Mcount_wait_before_sync_r_xor_1_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(0),
      LI => Mcount_wait_before_sync_r_cy_1_rt_15340,
      O => Result(1)
    );
  Mcount_wait_before_sync_r_cy_2_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(1),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_2_rt_15342,
      O => Mcount_wait_before_sync_r_cy(2)
    );
  Mcount_wait_before_sync_r_xor_2_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(1),
      LI => Mcount_wait_before_sync_r_cy_2_rt_15342,
      O => Result(2)
    );
  Mcount_wait_before_sync_r_cy_3_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(2),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_3_rt_15344,
      O => Mcount_wait_before_sync_r_cy(3)
    );
  Mcount_wait_before_sync_r_xor_3_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(2),
      LI => Mcount_wait_before_sync_r_cy_3_rt_15344,
      O => Result(3)
    );
  Mcount_wait_before_sync_r_cy_4_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(3),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_4_rt_15346,
      O => Mcount_wait_before_sync_r_cy(4)
    );
  Mcount_wait_before_sync_r_xor_4_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(3),
      LI => Mcount_wait_before_sync_r_cy_4_rt_15346,
      O => Result(4)
    );
  Mcount_wait_before_sync_r_cy_5_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(4),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_5_rt_15348,
      O => Mcount_wait_before_sync_r_cy(5)
    );
  Mcount_wait_before_sync_r_xor_5_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(4),
      LI => Mcount_wait_before_sync_r_cy_5_rt_15348,
      O => Result(5)
    );
  Mcount_wait_before_sync_r_cy_6_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(5),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_6_rt_15350,
      O => Mcount_wait_before_sync_r_cy(6)
    );
  Mcount_wait_before_sync_r_xor_6_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(5),
      LI => Mcount_wait_before_sync_r_cy_6_rt_15350,
      O => Result(6)
    );
  Mcount_wait_before_sync_r_cy_7_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(6),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_7_rt_15352,
      O => Mcount_wait_before_sync_r_cy(7)
    );
  Mcount_wait_before_sync_r_xor_7_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(6),
      LI => Mcount_wait_before_sync_r_cy_7_rt_15352,
      O => Result(7)
    );
  Mcount_wait_before_sync_r_cy_8_Q : MUXCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(7),
      DI => N0,
      S => Mcount_wait_before_sync_r_cy_8_rt_15354,
      O => Mcount_wait_before_sync_r_cy(8)
    );
  Mcount_wait_before_sync_r_xor_8_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(7),
      LI => Mcount_wait_before_sync_r_cy_8_rt_15354,
      O => Result(8)
    );
  Mcount_wait_before_sync_r_xor_9_Q : XORCY
    port map (
      CI => Mcount_wait_before_sync_r_cy(8),
      LI => Mcount_wait_before_sync_r_xor_9_rt_15356,
      O => Result(9)
    );
  Mcount_sync_counter_r_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_sync_counter_r_lut(0),
      O => Mcount_sync_counter_r_cy(0)
    );
  Mcount_sync_counter_r_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_sync_counter_r_lut(0),
      O => Result_0_1
    );
  Mcount_sync_counter_r_cy_1_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(0),
      DI => N0,
      S => Mcount_sync_counter_r_cy_1_rt_15319,
      O => Mcount_sync_counter_r_cy(1)
    );
  Mcount_sync_counter_r_xor_1_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(0),
      LI => Mcount_sync_counter_r_cy_1_rt_15319,
      O => Result_1_1
    );
  Mcount_sync_counter_r_cy_2_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(1),
      DI => N0,
      S => Mcount_sync_counter_r_cy_2_rt_15321,
      O => Mcount_sync_counter_r_cy(2)
    );
  Mcount_sync_counter_r_xor_2_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(1),
      LI => Mcount_sync_counter_r_cy_2_rt_15321,
      O => Result_2_1
    );
  Mcount_sync_counter_r_cy_3_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(2),
      DI => N0,
      S => Mcount_sync_counter_r_cy_3_rt_15323,
      O => Mcount_sync_counter_r_cy(3)
    );
  Mcount_sync_counter_r_xor_3_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(2),
      LI => Mcount_sync_counter_r_cy_3_rt_15323,
      O => Result_3_1
    );
  Mcount_sync_counter_r_cy_4_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(3),
      DI => N0,
      S => Mcount_sync_counter_r_cy_4_rt_15325,
      O => Mcount_sync_counter_r_cy(4)
    );
  Mcount_sync_counter_r_xor_4_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(3),
      LI => Mcount_sync_counter_r_cy_4_rt_15325,
      O => Result_4_1
    );
  Mcount_sync_counter_r_cy_5_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(4),
      DI => N0,
      S => Mcount_sync_counter_r_cy_5_rt_15327,
      O => Mcount_sync_counter_r_cy(5)
    );
  Mcount_sync_counter_r_xor_5_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(4),
      LI => Mcount_sync_counter_r_cy_5_rt_15327,
      O => Result_5_1
    );
  Mcount_sync_counter_r_cy_6_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(5),
      DI => N0,
      S => Mcount_sync_counter_r_cy_6_rt_15329,
      O => Mcount_sync_counter_r_cy(6)
    );
  Mcount_sync_counter_r_xor_6_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(5),
      LI => Mcount_sync_counter_r_cy_6_rt_15329,
      O => Result_6_1
    );
  Mcount_sync_counter_r_cy_7_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(6),
      DI => N0,
      S => Mcount_sync_counter_r_cy_7_rt_15331,
      O => Mcount_sync_counter_r_cy(7)
    );
  Mcount_sync_counter_r_xor_7_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(6),
      LI => Mcount_sync_counter_r_cy_7_rt_15331,
      O => Result_7_1
    );
  Mcount_sync_counter_r_cy_8_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(7),
      DI => N0,
      S => Mcount_sync_counter_r_cy_8_rt_15333,
      O => Mcount_sync_counter_r_cy(8)
    );
  Mcount_sync_counter_r_xor_8_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(7),
      LI => Mcount_sync_counter_r_cy_8_rt_15333,
      O => Result_8_1
    );
  Mcount_sync_counter_r_cy_9_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(8),
      DI => N0,
      S => Mcount_sync_counter_r_cy_9_rt_15335,
      O => Mcount_sync_counter_r_cy(9)
    );
  Mcount_sync_counter_r_xor_9_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(8),
      LI => Mcount_sync_counter_r_cy_9_rt_15335,
      O => Result_9_1
    );
  Mcount_sync_counter_r_cy_10_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(9),
      DI => N0,
      S => Mcount_sync_counter_r_cy_10_rt_15315,
      O => Mcount_sync_counter_r_cy(10)
    );
  Mcount_sync_counter_r_xor_10_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(9),
      LI => Mcount_sync_counter_r_cy_10_rt_15315,
      O => Result(10)
    );
  Mcount_sync_counter_r_cy_11_Q : MUXCY
    port map (
      CI => Mcount_sync_counter_r_cy(10),
      DI => N0,
      S => Mcount_sync_counter_r_cy_11_rt_15317,
      O => Mcount_sync_counter_r_cy(11)
    );
  Mcount_sync_counter_r_xor_11_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(10),
      LI => Mcount_sync_counter_r_cy_11_rt_15317,
      O => Result(11)
    );
  Mcount_sync_counter_r_xor_12_Q : XORCY
    port map (
      CI => Mcount_sync_counter_r_cy(11),
      LI => Mcount_sync_counter_r_xor_12_rt_15337,
      O => Result(12)
    );
  next_wait_stable_c1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => begin_r_15386,
      I1 => wait_before_sync_r(9),
      I2 => wait_stable_r_15416,
      O => next_wait_stable_c
    );
  next_ready_c1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => NlwRenamedSig_OI_phase_align_r,
      I1 => sync_counter_r(12),
      I2 => NlwRenamedSig_OI_ready_r,
      O => next_ready_c
    );
  next_phase_align_c1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => wait_before_sync_r(9),
      I1 => wait_stable_r_15416,
      I2 => sync_counter_r(12),
      I3 => NlwRenamedSig_OI_phase_align_r,
      O => next_phase_align_c
    );
  Mcount_wait_before_sync_r_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(1),
      O => Mcount_wait_before_sync_r_cy_1_rt_15340
    );
  Mcount_wait_before_sync_r_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(2),
      O => Mcount_wait_before_sync_r_cy_2_rt_15342
    );
  Mcount_wait_before_sync_r_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(3),
      O => Mcount_wait_before_sync_r_cy_3_rt_15344
    );
  Mcount_wait_before_sync_r_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(4),
      O => Mcount_wait_before_sync_r_cy_4_rt_15346
    );
  Mcount_wait_before_sync_r_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(5),
      O => Mcount_wait_before_sync_r_cy_5_rt_15348
    );
  Mcount_wait_before_sync_r_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(6),
      O => Mcount_wait_before_sync_r_cy_6_rt_15350
    );
  Mcount_wait_before_sync_r_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(7),
      O => Mcount_wait_before_sync_r_cy_7_rt_15352
    );
  Mcount_wait_before_sync_r_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(8),
      O => Mcount_wait_before_sync_r_cy_8_rt_15354
    );
  Mcount_sync_counter_r_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(1),
      O => Mcount_sync_counter_r_cy_1_rt_15319
    );
  Mcount_sync_counter_r_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(2),
      O => Mcount_sync_counter_r_cy_2_rt_15321
    );
  Mcount_sync_counter_r_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(3),
      O => Mcount_sync_counter_r_cy_3_rt_15323
    );
  Mcount_sync_counter_r_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(4),
      O => Mcount_sync_counter_r_cy_4_rt_15325
    );
  Mcount_sync_counter_r_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(5),
      O => Mcount_sync_counter_r_cy_5_rt_15327
    );
  Mcount_sync_counter_r_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(6),
      O => Mcount_sync_counter_r_cy_6_rt_15329
    );
  Mcount_sync_counter_r_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(7),
      O => Mcount_sync_counter_r_cy_7_rt_15331
    );
  Mcount_sync_counter_r_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(8),
      O => Mcount_sync_counter_r_cy_8_rt_15333
    );
  Mcount_sync_counter_r_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(9),
      O => Mcount_sync_counter_r_cy_9_rt_15335
    );
  Mcount_sync_counter_r_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(10),
      O => Mcount_sync_counter_r_cy_10_rt_15315
    );
  Mcount_sync_counter_r_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(11),
      O => Mcount_sync_counter_r_cy_11_rt_15317
    );
  Mcount_wait_before_sync_r_xor_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wait_before_sync_r(9),
      O => Mcount_wait_before_sync_r_xor_9_rt_15356
    );
  Mcount_sync_counter_r_xor_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => sync_counter_r(12),
      O => Mcount_sync_counter_r_xor_12_rt_15337
    );
  Mcount_wait_before_sync_r_lut_0_INV_0 : INV
    port map (
      I => wait_before_sync_r(0),
      O => Mcount_wait_before_sync_r_lut(0)
    );
  Mcount_sync_counter_r_lut_0_INV_0 : INV
    port map (
      I => sync_counter_r(0),
      O => Mcount_sync_counter_r_lut(0)
    );
  TXENPMAPHASEALIGN1_INV_0 : INV
    port map (
      I => begin_r_15386,
      O => TXENPMAPHASEALIGN
    );
  wait_stable_r_inv1_INV_0 : INV
    port map (
      I => wait_stable_r_15416,
      O => wait_stable_r_inv
    );
  phase_align_r_inv1_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_phase_align_r,
      O => phase_align_r_inv
    );
  RESET_inv1_INV_0 : INV
    port map (
      I => RESET,
      O => RESET_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_gt_wrapper is
  port (
    gtclk_bufg : out STD_LOGIC; 
    gt_usrclk : in STD_LOGIC := 'X'; 
    refclkout_bufg : out STD_LOGIC; 
    gtreset : in STD_LOGIC := 'X'; 
    pcie_reset : out STD_LOGIC; 
    refclk : in STD_LOGIC := 'X'; 
    clock_lock : in STD_LOGIC := 'X'; 
    gt_dclk : in STD_LOGIC := 'X'; 
    gt_rx_chanisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_elec_idle : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxchanbondseq : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    resetdone : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_valid : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_data_k : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxbyteisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_tx_p : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_status : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
    plllkdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
    gt_rx_phy_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_elec_idle : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_p : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_deskew_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
    gt_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_tx_compliance : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_pipe_reset : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_detect_rx_loopback : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
    gt_power_down : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    gt_rx_polarity : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end pcie_gt_wrapper;

architecture STRUCTURE of pcie_gt_wrapper is
  component TX_SYNC_GTP
    port (
      RESET : in STD_LOGIC := 'X'; 
      USER_CLK : in STD_LOGIC := 'X'; 
      TXENPMAPHASEALIGN : out STD_LOGIC; 
      SYNC_DONE : out STD_LOGIC; 
      TXPMASETPHASE : out STD_LOGIC 
    );
  end component;
  signal N1 : STD_LOGIC; 
  signal TXENPMAPHASEALIGN : STD_LOGIC; 
  signal TXPMASETPHASE : STD_LOGIC; 
  signal Q_and0000 : STD_LOGIC; 
  signal Q_and0001 : STD_LOGIC; 
  signal Q_and0002 : STD_LOGIC; 
  signal Q_and0003 : STD_LOGIC; 
  signal Q_and0004 : STD_LOGIC; 
  signal Q_and0005 : STD_LOGIC; 
  signal Q_and0006 : STD_LOGIC; 
  signal Q_and0007 : STD_LOGIC; 
  signal Q_and0008 : STD_LOGIC; 
  signal Q_and0009 : STD_LOGIC; 
  signal cdrreset_0_and0000 : STD_LOGIC; 
  signal cdrreset_1_and0000 : STD_LOGIC; 
  signal cdrreset_2_and0000 : STD_LOGIC; 
  signal cdrreset_3_and0000 : STD_LOGIC; 
  signal cdrreset_4_and0000 : STD_LOGIC; 
  signal cdrreset_5_and0000 : STD_LOGIC; 
  signal cdrreset_6_and0000 : STD_LOGIC; 
  signal cdrreset_7_and0000 : STD_LOGIC; 
  signal delayed_elec_idle_reset_15450 : STD_LOGIC; 
  signal flop_0_tx_elec_idle_not0000 : STD_LOGIC; 
  signal m1_delayed_elec_idle_reset_16238 : STD_LOGIC; 
  signal m2_delayed_elec_idle_reset_16239 : STD_LOGIC; 
  signal mgt_txreset_16240 : STD_LOGIC; 
  signal mgt_txreset_cnt_cmp_lt0000 : STD_LOGIC; 
  signal mgt_txreset_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_rst_pcie : STD_LOGIC; 
  signal rxreset_16276 : STD_LOGIC; 
  signal rxreset_and0000 : STD_LOGIC; 
  signal sync_done : STD_LOGIC; 
  signal sync_done_inv : STD_LOGIC; 
  signal tx_sync_reset : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRECCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRECCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXOUTCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCOMMADET0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBYTEREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHANREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCOMMADET1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBYTEREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHANREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXPRBSERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXPRBSERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXOVERSAMPLEERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXOVERSAMPLEERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXNOTINTABLE0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXNOTINTABLE0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDISPERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDISPERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISK0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISCOMMA0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISCOMMA0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDATA1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXNOTINTABLE1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXNOTINTABLE1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDISPERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXDISPERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISK1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISCOMMA1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCHARISCOMMA1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXKERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXKERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXKERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXKERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_TXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_0_GT_i_RXCLKCORCNT1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_REFCLKOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRECCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXOUTCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRECCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXOUTCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCOMMADET0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBYTEREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHANREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCOMMADET1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBYTEREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHANREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXPRBSERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXPRBSERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXOVERSAMPLEERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXOVERSAMPLEERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXNOTINTABLE0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXNOTINTABLE0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDISPERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDISPERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISK0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISCOMMA0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISCOMMA0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDATA1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXNOTINTABLE1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXNOTINTABLE1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDISPERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXDISPERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISK1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISCOMMA1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCHARISCOMMA1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXKERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXKERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXKERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXKERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_TXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_2_GT_i_RXCLKCORCNT1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_REFCLKOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRECCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXOUTCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRECCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXOUTCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCOMMADET0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBYTEREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHANREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCOMMADET1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBYTEREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHANREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXPRBSERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXPRBSERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXOVERSAMPLEERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXOVERSAMPLEERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXNOTINTABLE0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXNOTINTABLE0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDISPERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDISPERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISK0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISCOMMA0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISCOMMA0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDATA1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXNOTINTABLE1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXNOTINTABLE1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDISPERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXDISPERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISK1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISCOMMA1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCHARISCOMMA1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXKERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXKERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXKERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXKERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_TXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_4_GT_i_RXCLKCORCNT1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_REFCLKOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRECCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXOUTCLK0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRECCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXOUTCLK1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCOMMADET0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBYTEREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHANREALIGN0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCOMMADET1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBYTEREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHANREALIGN1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXPRBSERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXPRBSERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXOVERSAMPLEERR0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXOVERSAMPLEERR1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXNOTINTABLE0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXNOTINTABLE0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDISPERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDISPERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISK0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISCOMMA0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISCOMMA0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDATA1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXNOTINTABLE1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXNOTINTABLE1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDISPERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXDISPERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISK1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISCOMMA1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHARISCOMMA1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXKERR0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXKERR0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXRUNDISP0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXRUNDISP0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXKERR1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXKERR1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXRUNDISP1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXRUNDISP1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_TXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHBONDO1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHBONDO1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCHBONDO1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXBUFSTATUS1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_GTD_6_GT_i_RXCLKCORCNT1_0_UNCONNECTED : STD_LOGIC; 
  signal Result : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal cdrreset : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_clk : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSig_OI_gt_do : STD_LOGIC_VECTOR ( 16 downto 16 ); 
  signal gt_pipe_reset_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_refclk_out : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal gt_rx_chanisaligned_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_rx_chbond_o : STD_LOGIC_VECTOR2 ( 6 downto 0 , 2 downto 0 ); 
  signal gt_rx_data_k_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_rx_data_reg : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal gt_rx_elec_idle_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_rx_en_elec_idle_resetb : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal gt_rx_phy_status_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_rx_polarity_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_rx_power_down_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal gt_rx_status_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal gt_rx_valid_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_tx_compliance_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_tx_data_k_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_tx_data_reg : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal gt_tx_detect_rx_loopback_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_tx_elec_idle_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal gt_tx_power_down_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal icdrreset : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal mgt_txreset_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_resetdone : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  pcie_reset <= NlwRenamedSig_OI_rst_pcie;
  resetdone(7) <= NlwRenamedSig_OI_resetdone(7);
  resetdone(6) <= NlwRenamedSig_OI_resetdone(6);
  resetdone(5) <= NlwRenamedSig_OI_resetdone(5);
  resetdone(4) <= NlwRenamedSig_OI_resetdone(4);
  resetdone(3) <= NlwRenamedSig_OI_resetdone(3);
  resetdone(2) <= NlwRenamedSig_OI_resetdone(2);
  resetdone(1) <= NlwRenamedSig_OI_resetdone(1);
  resetdone(0) <= NlwRenamedSig_OI_resetdone(0);
  gt_drdy(7) <= NlwRenamedSig_OI_gt_do(16);
  gt_drdy(5) <= NlwRenamedSig_OI_gt_do(16);
  gt_drdy(3) <= NlwRenamedSig_OI_gt_do(16);
  gt_drdy(1) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(127) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(126) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(125) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(124) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(123) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(122) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(121) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(120) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(119) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(118) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(117) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(116) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(115) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(114) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(113) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(112) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(95) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(94) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(93) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(92) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(91) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(90) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(89) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(88) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(87) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(86) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(85) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(84) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(83) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(82) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(81) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(80) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(63) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(62) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(61) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(60) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(59) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(58) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(57) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(56) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(55) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(54) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(53) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(52) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(51) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(50) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(49) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(48) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(31) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(30) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(29) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(28) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(27) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(26) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(25) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(24) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(23) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(22) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(21) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(20) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(19) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(18) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(17) <= NlwRenamedSig_OI_gt_do(16);
  gt_do(16) <= NlwRenamedSig_OI_gt_do(16);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_gt_do(16)
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  mgt_txreset : FDR
    port map (
      C => gt_usrclk,
      D => N1,
      R => mgt_txreset_or0000,
      Q => mgt_txreset_16240
    );
  rst_pcie : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      D => sync_done_inv,
      PRE => gtreset,
      Q => NlwRenamedSig_OI_rst_pcie
    );
  m1_delayed_elec_idle_reset : FDC
    port map (
      C => gt_usrclk,
      CLR => gt_pipe_reset_reg(0),
      D => cdrreset(0),
      Q => m1_delayed_elec_idle_reset_16238
    );
  rxreset : FDC
    port map (
      C => gt_usrclk,
      CLR => gt_pipe_reset_reg(0),
      D => rxreset_and0000,
      Q => rxreset_16276
    );
  m2_delayed_elec_idle_reset : FDC
    port map (
      C => gt_usrclk,
      CLR => gt_pipe_reset_reg(0),
      D => m1_delayed_elec_idle_reset_16238,
      Q => m2_delayed_elec_idle_reset_16239
    );
  delayed_elec_idle_reset : FDC
    port map (
      C => gt_usrclk,
      CLR => gt_pipe_reset_reg(0),
      D => m2_delayed_elec_idle_reset_16239,
      Q => delayed_elec_idle_reset_15450
    );
  flop_0_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(0),
      Q => gt_tx_data_reg(0)
    );
  flop_0_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(1),
      Q => gt_tx_data_reg(1)
    );
  flop_0_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(2),
      Q => gt_tx_data_reg(2)
    );
  flop_0_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(3),
      Q => gt_tx_data_reg(3)
    );
  flop_0_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(4),
      Q => gt_tx_data_reg(4)
    );
  flop_0_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(5),
      Q => gt_tx_data_reg(5)
    );
  flop_0_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(6),
      Q => gt_tx_data_reg(6)
    );
  flop_0_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(7),
      Q => gt_tx_data_reg(7)
    );
  flop_0_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(0),
      Q => gt_tx_data_k_reg(0)
    );
  flop_0_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(0)
    );
  flop_0_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(0),
      Q => gt_tx_compliance_reg(0)
    );
  flop_0_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(0),
      Q => gt_tx_detect_rx_loopback_reg(0)
    );
  flop_0_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(0)
    );
  flop_0_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(1),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(1)
    );
  flop_0_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(0)
    );
  flop_0_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(1),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(1)
    );
  flop_0_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(0),
      Q => gt_rx_polarity_reg(0)
    );
  flop_0_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(0)
    );
  flop_0_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(0),
      Q => gt_rx_data(0)
    );
  flop_0_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(1),
      Q => gt_rx_data(1)
    );
  flop_0_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(2),
      Q => gt_rx_data(2)
    );
  flop_0_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(3),
      Q => gt_rx_data(3)
    );
  flop_0_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(4),
      Q => gt_rx_data(4)
    );
  flop_0_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(5),
      Q => gt_rx_data(5)
    );
  flop_0_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(6),
      Q => gt_rx_data(6)
    );
  flop_0_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(7),
      Q => gt_rx_data(7)
    );
  flop_0_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(0),
      Q => gt_rx_data_k(0)
    );
  flop_0_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(0)
    );
  flop_0_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(0),
      Q => gt_rx_valid(0)
    );
  flop_0_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(0),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(0)
    );
  flop_0_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(0),
      Q => gt_rx_chanisaligned(0)
    );
  flop_0_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(0),
      Q => gt_rx_status(0)
    );
  flop_0_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(1),
      Q => gt_rx_status(1)
    );
  flop_0_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(2),
      Q => gt_rx_status(2)
    );
  flop_1_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(8),
      Q => gt_tx_data_reg(8)
    );
  flop_1_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(9),
      Q => gt_tx_data_reg(9)
    );
  flop_1_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(10),
      Q => gt_tx_data_reg(10)
    );
  flop_1_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(11),
      Q => gt_tx_data_reg(11)
    );
  flop_1_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(12),
      Q => gt_tx_data_reg(12)
    );
  flop_1_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(13),
      Q => gt_tx_data_reg(13)
    );
  flop_1_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(14),
      Q => gt_tx_data_reg(14)
    );
  flop_1_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(15),
      Q => gt_tx_data_reg(15)
    );
  flop_1_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(1),
      Q => gt_tx_data_k_reg(1)
    );
  flop_1_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(1),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(1)
    );
  flop_1_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(1),
      Q => gt_tx_compliance_reg(1)
    );
  flop_1_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(1),
      Q => gt_tx_detect_rx_loopback_reg(1)
    );
  flop_1_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(2)
    );
  flop_1_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(3),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(3)
    );
  flop_1_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(2)
    );
  flop_1_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(3),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(3)
    );
  flop_1_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(1),
      Q => gt_rx_polarity_reg(1)
    );
  flop_1_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(1),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(1)
    );
  flop_1_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(8),
      Q => gt_rx_data(8)
    );
  flop_1_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(9),
      Q => gt_rx_data(9)
    );
  flop_1_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(10),
      Q => gt_rx_data(10)
    );
  flop_1_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(11),
      Q => gt_rx_data(11)
    );
  flop_1_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(12),
      Q => gt_rx_data(12)
    );
  flop_1_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(13),
      Q => gt_rx_data(13)
    );
  flop_1_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(14),
      Q => gt_rx_data(14)
    );
  flop_1_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(15),
      Q => gt_rx_data(15)
    );
  flop_1_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(1),
      Q => gt_rx_data_k(1)
    );
  flop_1_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(1),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(1)
    );
  flop_1_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(1),
      Q => gt_rx_valid(1)
    );
  flop_1_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(1),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(1)
    );
  flop_1_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(1),
      Q => gt_rx_chanisaligned(1)
    );
  flop_1_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(3),
      Q => gt_rx_status(3)
    );
  flop_1_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(4),
      Q => gt_rx_status(4)
    );
  flop_1_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(5),
      Q => gt_rx_status(5)
    );
  flop_2_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(16),
      Q => gt_tx_data_reg(16)
    );
  flop_2_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(17),
      Q => gt_tx_data_reg(17)
    );
  flop_2_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(18),
      Q => gt_tx_data_reg(18)
    );
  flop_2_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(19),
      Q => gt_tx_data_reg(19)
    );
  flop_2_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(20),
      Q => gt_tx_data_reg(20)
    );
  flop_2_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(21),
      Q => gt_tx_data_reg(21)
    );
  flop_2_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(22),
      Q => gt_tx_data_reg(22)
    );
  flop_2_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(23),
      Q => gt_tx_data_reg(23)
    );
  flop_2_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(2),
      Q => gt_tx_data_k_reg(2)
    );
  flop_2_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(2)
    );
  flop_2_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(2),
      Q => gt_tx_compliance_reg(2)
    );
  flop_2_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(2),
      Q => gt_tx_detect_rx_loopback_reg(2)
    );
  flop_2_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(4)
    );
  flop_2_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(5),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(5)
    );
  flop_2_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(4)
    );
  flop_2_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(5),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(5)
    );
  flop_2_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(2),
      Q => gt_rx_polarity_reg(2)
    );
  flop_2_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(2)
    );
  flop_2_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(16),
      Q => gt_rx_data(16)
    );
  flop_2_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(17),
      Q => gt_rx_data(17)
    );
  flop_2_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(18),
      Q => gt_rx_data(18)
    );
  flop_2_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(19),
      Q => gt_rx_data(19)
    );
  flop_2_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(20),
      Q => gt_rx_data(20)
    );
  flop_2_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(21),
      Q => gt_rx_data(21)
    );
  flop_2_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(22),
      Q => gt_rx_data(22)
    );
  flop_2_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(23),
      Q => gt_rx_data(23)
    );
  flop_2_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(2),
      Q => gt_rx_data_k(2)
    );
  flop_2_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(2)
    );
  flop_2_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(2),
      Q => gt_rx_valid(2)
    );
  flop_2_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(2),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(2)
    );
  flop_2_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(2),
      Q => gt_rx_chanisaligned(2)
    );
  flop_2_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(6),
      Q => gt_rx_status(6)
    );
  flop_2_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(7),
      Q => gt_rx_status(7)
    );
  flop_2_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(8),
      Q => gt_rx_status(8)
    );
  flop_3_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(24),
      Q => gt_tx_data_reg(24)
    );
  flop_3_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(25),
      Q => gt_tx_data_reg(25)
    );
  flop_3_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(26),
      Q => gt_tx_data_reg(26)
    );
  flop_3_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(27),
      Q => gt_tx_data_reg(27)
    );
  flop_3_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(28),
      Q => gt_tx_data_reg(28)
    );
  flop_3_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(29),
      Q => gt_tx_data_reg(29)
    );
  flop_3_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(30),
      Q => gt_tx_data_reg(30)
    );
  flop_3_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(31),
      Q => gt_tx_data_reg(31)
    );
  flop_3_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(3),
      Q => gt_tx_data_k_reg(3)
    );
  flop_3_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(3),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(3)
    );
  flop_3_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(3),
      Q => gt_tx_compliance_reg(3)
    );
  flop_3_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(3),
      Q => gt_tx_detect_rx_loopback_reg(3)
    );
  flop_3_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(6)
    );
  flop_3_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(7),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(7)
    );
  flop_3_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(6)
    );
  flop_3_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(7),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(7)
    );
  flop_3_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(3),
      Q => gt_rx_polarity_reg(3)
    );
  flop_3_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(3),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(3)
    );
  flop_3_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(24),
      Q => gt_rx_data(24)
    );
  flop_3_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(25),
      Q => gt_rx_data(25)
    );
  flop_3_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(26),
      Q => gt_rx_data(26)
    );
  flop_3_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(27),
      Q => gt_rx_data(27)
    );
  flop_3_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(28),
      Q => gt_rx_data(28)
    );
  flop_3_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(29),
      Q => gt_rx_data(29)
    );
  flop_3_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(30),
      Q => gt_rx_data(30)
    );
  flop_3_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(31),
      Q => gt_rx_data(31)
    );
  flop_3_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(3),
      Q => gt_rx_data_k(3)
    );
  flop_3_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(3),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(3)
    );
  flop_3_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(3),
      Q => gt_rx_valid(3)
    );
  flop_3_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(3),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(3)
    );
  flop_3_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(3),
      Q => gt_rx_chanisaligned(3)
    );
  flop_3_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(9),
      Q => gt_rx_status(9)
    );
  flop_3_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(10),
      Q => gt_rx_status(10)
    );
  flop_3_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(11),
      Q => gt_rx_status(11)
    );
  flop_4_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(32),
      Q => gt_tx_data_reg(32)
    );
  flop_4_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(33),
      Q => gt_tx_data_reg(33)
    );
  flop_4_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(34),
      Q => gt_tx_data_reg(34)
    );
  flop_4_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(35),
      Q => gt_tx_data_reg(35)
    );
  flop_4_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(36),
      Q => gt_tx_data_reg(36)
    );
  flop_4_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(37),
      Q => gt_tx_data_reg(37)
    );
  flop_4_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(38),
      Q => gt_tx_data_reg(38)
    );
  flop_4_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(39),
      Q => gt_tx_data_reg(39)
    );
  flop_4_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(4),
      Q => gt_tx_data_k_reg(4)
    );
  flop_4_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(4)
    );
  flop_4_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(4),
      Q => gt_tx_compliance_reg(4)
    );
  flop_4_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(4),
      Q => gt_tx_detect_rx_loopback_reg(4)
    );
  flop_4_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(8),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(8)
    );
  flop_4_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(9),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(9)
    );
  flop_4_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(8),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(8)
    );
  flop_4_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(9),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(9)
    );
  flop_4_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(4),
      Q => gt_rx_polarity_reg(4)
    );
  flop_4_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(4)
    );
  flop_4_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(32),
      Q => gt_rx_data(32)
    );
  flop_4_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(33),
      Q => gt_rx_data(33)
    );
  flop_4_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(34),
      Q => gt_rx_data(34)
    );
  flop_4_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(35),
      Q => gt_rx_data(35)
    );
  flop_4_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(36),
      Q => gt_rx_data(36)
    );
  flop_4_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(37),
      Q => gt_rx_data(37)
    );
  flop_4_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(38),
      Q => gt_rx_data(38)
    );
  flop_4_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(39),
      Q => gt_rx_data(39)
    );
  flop_4_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(4),
      Q => gt_rx_data_k(4)
    );
  flop_4_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(4)
    );
  flop_4_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(4),
      Q => gt_rx_valid(4)
    );
  flop_4_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(4),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(4)
    );
  flop_4_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(4),
      Q => gt_rx_chanisaligned(4)
    );
  flop_4_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(12),
      Q => gt_rx_status(12)
    );
  flop_4_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(13),
      Q => gt_rx_status(13)
    );
  flop_4_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(14),
      Q => gt_rx_status(14)
    );
  flop_5_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(40),
      Q => gt_tx_data_reg(40)
    );
  flop_5_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(41),
      Q => gt_tx_data_reg(41)
    );
  flop_5_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(42),
      Q => gt_tx_data_reg(42)
    );
  flop_5_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(43),
      Q => gt_tx_data_reg(43)
    );
  flop_5_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(44),
      Q => gt_tx_data_reg(44)
    );
  flop_5_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(45),
      Q => gt_tx_data_reg(45)
    );
  flop_5_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(46),
      Q => gt_tx_data_reg(46)
    );
  flop_5_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(47),
      Q => gt_tx_data_reg(47)
    );
  flop_5_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(5),
      Q => gt_tx_data_k_reg(5)
    );
  flop_5_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(5),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(5)
    );
  flop_5_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(5),
      Q => gt_tx_compliance_reg(5)
    );
  flop_5_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(5),
      Q => gt_tx_detect_rx_loopback_reg(5)
    );
  flop_5_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(10),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(10)
    );
  flop_5_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(11),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(11)
    );
  flop_5_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(10),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(10)
    );
  flop_5_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(11),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(11)
    );
  flop_5_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(5),
      Q => gt_rx_polarity_reg(5)
    );
  flop_5_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(5),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(5)
    );
  flop_5_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(40),
      Q => gt_rx_data(40)
    );
  flop_5_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(41),
      Q => gt_rx_data(41)
    );
  flop_5_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(42),
      Q => gt_rx_data(42)
    );
  flop_5_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(43),
      Q => gt_rx_data(43)
    );
  flop_5_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(44),
      Q => gt_rx_data(44)
    );
  flop_5_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(45),
      Q => gt_rx_data(45)
    );
  flop_5_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(46),
      Q => gt_rx_data(46)
    );
  flop_5_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(47),
      Q => gt_rx_data(47)
    );
  flop_5_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(5),
      Q => gt_rx_data_k(5)
    );
  flop_5_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(5),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(5)
    );
  flop_5_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(5),
      Q => gt_rx_valid(5)
    );
  flop_5_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(5),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(5)
    );
  flop_5_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(5),
      Q => gt_rx_chanisaligned(5)
    );
  flop_5_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(15),
      Q => gt_rx_status(15)
    );
  flop_5_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(16),
      Q => gt_rx_status(16)
    );
  flop_5_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(17),
      Q => gt_rx_status(17)
    );
  flop_6_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(48),
      Q => gt_tx_data_reg(48)
    );
  flop_6_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(49),
      Q => gt_tx_data_reg(49)
    );
  flop_6_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(50),
      Q => gt_tx_data_reg(50)
    );
  flop_6_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(51),
      Q => gt_tx_data_reg(51)
    );
  flop_6_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(52),
      Q => gt_tx_data_reg(52)
    );
  flop_6_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(53),
      Q => gt_tx_data_reg(53)
    );
  flop_6_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(54),
      Q => gt_tx_data_reg(54)
    );
  flop_6_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(55),
      Q => gt_tx_data_reg(55)
    );
  flop_6_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(6),
      Q => gt_tx_data_k_reg(6)
    );
  flop_6_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(6)
    );
  flop_6_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(6),
      Q => gt_tx_compliance_reg(6)
    );
  flop_6_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(6),
      Q => gt_tx_detect_rx_loopback_reg(6)
    );
  flop_6_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(12),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(12)
    );
  flop_6_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(13),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(13)
    );
  flop_6_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(12),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(12)
    );
  flop_6_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(13),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(13)
    );
  flop_6_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(6),
      Q => gt_rx_polarity_reg(6)
    );
  flop_6_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(6)
    );
  flop_6_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(48),
      Q => gt_rx_data(48)
    );
  flop_6_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(49),
      Q => gt_rx_data(49)
    );
  flop_6_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(50),
      Q => gt_rx_data(50)
    );
  flop_6_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(51),
      Q => gt_rx_data(51)
    );
  flop_6_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(52),
      Q => gt_rx_data(52)
    );
  flop_6_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(53),
      Q => gt_rx_data(53)
    );
  flop_6_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(54),
      Q => gt_rx_data(54)
    );
  flop_6_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(55),
      Q => gt_rx_data(55)
    );
  flop_6_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(6),
      Q => gt_rx_data_k(6)
    );
  flop_6_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(6)
    );
  flop_6_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(6),
      Q => gt_rx_valid(6)
    );
  flop_6_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(6),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(6)
    );
  flop_6_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(6),
      Q => gt_rx_chanisaligned(6)
    );
  flop_6_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(18),
      Q => gt_rx_status(18)
    );
  flop_6_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(19),
      Q => gt_rx_status(19)
    );
  flop_6_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(20),
      Q => gt_rx_status(20)
    );
  flop_7_tx_data0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(56),
      Q => gt_tx_data_reg(56)
    );
  flop_7_tx_data1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(57),
      Q => gt_tx_data_reg(57)
    );
  flop_7_tx_data2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(58),
      Q => gt_tx_data_reg(58)
    );
  flop_7_tx_data3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(59),
      Q => gt_tx_data_reg(59)
    );
  flop_7_tx_data4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(60),
      Q => gt_tx_data_reg(60)
    );
  flop_7_tx_data5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(61),
      Q => gt_tx_data_reg(61)
    );
  flop_7_tx_data6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(62),
      Q => gt_tx_data_reg(62)
    );
  flop_7_tx_data7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data(63),
      Q => gt_tx_data_reg(63)
    );
  flop_7_tx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_data_k(7),
      Q => gt_tx_data_k_reg(7)
    );
  flop_7_tx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_tx_elec_idle(7),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_elec_idle_reg(7)
    );
  flop_7_tx_compliance : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_compliance(7),
      Q => gt_tx_compliance_reg(7)
    );
  flop_7_tx_detect_rx_loopback : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_tx_detect_rx_loopback(7),
      Q => gt_tx_detect_rx_loopback_reg(7)
    );
  flop_7_tx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(14),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_tx_power_down_reg(14)
    );
  flop_7_tx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(15),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_tx_power_down_reg(15)
    );
  flop_7_rx_power_down0 : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_power_down(14),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_power_down_reg(14)
    );
  flop_7_rx_power_down1 : FDCP
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      CLR => flop_0_tx_elec_idle_not0000,
      D => gt_power_down(15),
      PRE => NlwRenamedSig_OI_gt_do(16),
      Q => gt_rx_power_down_reg(15)
    );
  flop_7_rx_polarity : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_polarity(7),
      Q => gt_rx_polarity_reg(7)
    );
  flop_7_reset : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_pipe_reset(7),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_pipe_reset_reg(7)
    );
  flop_7_rx_data_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(56),
      Q => gt_rx_data(56)
    );
  flop_7_rx_data_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(57),
      Q => gt_rx_data(57)
    );
  flop_7_rx_data_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(58),
      Q => gt_rx_data(58)
    );
  flop_7_rx_data_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(59),
      Q => gt_rx_data(59)
    );
  flop_7_rx_data_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(60),
      Q => gt_rx_data(60)
    );
  flop_7_rx_data_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(61),
      Q => gt_rx_data(61)
    );
  flop_7_rx_data_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(62),
      Q => gt_rx_data(62)
    );
  flop_7_rx_data_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_reg(63),
      Q => gt_rx_data(63)
    );
  flop_7_rx_data_k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_data_k_reg(7),
      Q => gt_rx_data_k(7)
    );
  flop_7_rx_elec_idle : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_elec_idle_reg(7),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_elec_idle(7)
    );
  flop_7_rx_valid : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_valid_reg(7),
      Q => gt_rx_valid(7)
    );
  flop_7_rx_phy_status : FDCP
    generic map(
      INIT => '1'
    )
    port map (
      C => gt_usrclk,
      CLR => NlwRenamedSig_OI_gt_do(16),
      D => gt_rx_phy_status_reg(7),
      PRE => flop_0_tx_elec_idle_not0000,
      Q => gt_rx_phy_status(7)
    );
  flop_7_rx_chanisaligned : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_chanisaligned_reg(7),
      Q => gt_rx_chanisaligned(7)
    );
  flop_7_rx_status_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(21),
      Q => gt_rx_status(21)
    );
  flop_7_rx_status_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(22),
      Q => gt_rx_status(22)
    );
  flop_7_rx_status_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => gt_usrclk,
      D => gt_rx_status_reg(23),
      Q => gt_rx_status(23)
    );
  mgt_txreset_cnt_0 : FDRE
    port map (
      C => gt_usrclk,
      CE => mgt_txreset_cnt_cmp_lt0000,
      D => Result(0),
      R => sync_done_inv,
      Q => mgt_txreset_cnt(0)
    );
  mgt_txreset_cnt_1 : FDRE
    port map (
      C => gt_usrclk,
      CE => mgt_txreset_cnt_cmp_lt0000,
      D => Result(1),
      R => sync_done_inv,
      Q => mgt_txreset_cnt(1)
    );
  bufg1 : BUFG
    port map (
      I => gt_clk(0),
      O => gtclk_bufg
    );
  bufg2 : BUFG
    port map (
      I => gt_refclk_out(0),
      O => refclkout_bufg
    );
  GTD_0_GT_i : GTP_DUAL
    generic map(
      AC_CAP_DIS_0 => FALSE,
      AC_CAP_DIS_1 => FALSE,
      ALIGN_COMMA_WORD_0 => 1,
      ALIGN_COMMA_WORD_1 => 1,
      CHAN_BOND_1_MAX_SKEW_0 => 7,
      CHAN_BOND_1_MAX_SKEW_1 => 7,
      CHAN_BOND_2_MAX_SKEW_0 => 7,
      CHAN_BOND_2_MAX_SKEW_1 => 7,
      CHAN_BOND_LEVEL_0 => 7,
      CHAN_BOND_LEVEL_1 => 6,
      CHAN_BOND_MODE_0 => "MASTER",
      CHAN_BOND_MODE_1 => "SLAVE",
      CLK_COR_SEQ_1_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_1_ENABLE_0 => "1111",
      CLK_COR_SEQ_2_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_2_ENABLE_0 => "1111",
      CHAN_BOND_SEQ_1_1_0 => "0001001010",
      CHAN_BOND_SEQ_1_1_1 => "0001001010",
      CHAN_BOND_SEQ_1_2_0 => "0001001010",
      CHAN_BOND_SEQ_1_2_1 => "0001001010",
      CHAN_BOND_SEQ_2_3_0 => "0110111100",
      CHAN_BOND_SEQ_2_3_1 => "0110111100",
      CHAN_BOND_SEQ_1_3_0 => "0001001010",
      CHAN_BOND_SEQ_1_3_1 => "0001001010",
      CHAN_BOND_SEQ_1_4_0 => "0110111100",
      CHAN_BOND_SEQ_1_4_1 => "0110111100",
      CHAN_BOND_SEQ_2_1_0 => "0100111100",
      CHAN_BOND_SEQ_2_1_1 => "0100111100",
      CHAN_BOND_SEQ_2_2_0 => "0100111100",
      CHAN_BOND_SEQ_2_2_1 => "0100111100",
      CHAN_BOND_SEQ_2_4_0 => "0100011100",
      CHAN_BOND_SEQ_2_4_1 => "0100011100",
      CHAN_BOND_SEQ_2_USE_0 => TRUE,
      CHAN_BOND_SEQ_2_USE_1 => TRUE,
      CHAN_BOND_SEQ_LEN_0 => 4,
      CHAN_BOND_SEQ_LEN_1 => 4,
      CLK25_DIVIDER => 10,
      CLKINDC_B => TRUE,
      CLK_CORRECT_USE_0 => TRUE,
      CLK_CORRECT_USE_1 => TRUE,
      CLK_COR_ADJ_LEN_0 => 1,
      CLK_COR_ADJ_LEN_1 => 1,
      CLK_COR_DET_LEN_0 => 1,
      CLK_COR_DET_LEN_1 => 1,
      CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
      CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
      CLK_COR_KEEP_IDLE_0 => FALSE,
      CLK_COR_KEEP_IDLE_1 => FALSE,
      CLK_COR_MAX_LAT_0 => 18,
      CLK_COR_MAX_LAT_1 => 18,
      CLK_COR_MIN_LAT_0 => 16,
      CLK_COR_MIN_LAT_1 => 16,
      CLK_COR_PRECEDENCE_0 => TRUE,
      CLK_COR_PRECEDENCE_1 => TRUE,
      CLK_COR_REPEAT_WAIT_0 => 5,
      CLK_COR_REPEAT_WAIT_1 => 5,
      MCOMMA_10B_VALUE_1 => "1010000011",
      CLK_COR_SEQ_1_ENABLE_0 => "1111",
      COMMA_10B_ENABLE_1 => "1111111111",
      CLK_COR_SEQ_2_ENABLE_0 => "1111",
      CLK_COR_SEQ_1_1_0 => "0100011100",
      CLK_COR_SEQ_1_1_1 => "0100011100",
      CLK_COR_SEQ_1_2_0 => "0000000000",
      CLK_COR_SEQ_1_2_1 => "0000000000",
      CLK_COR_SEQ_2_3_0 => "0000000000",
      CLK_COR_SEQ_2_3_1 => "0000000000",
      CLK_COR_SEQ_1_3_0 => "0000000000",
      CLK_COR_SEQ_1_3_1 => "0000000000",
      CLK_COR_SEQ_1_4_0 => "0000000000",
      CLK_COR_SEQ_1_4_1 => "0000000000",
      CLK_COR_SEQ_2_1_0 => "0000000000",
      CLK_COR_SEQ_2_1_1 => "0000000000",
      CLK_COR_SEQ_2_2_0 => "0000000000",
      CLK_COR_SEQ_2_2_1 => "0000000000",
      CLK_COR_SEQ_2_4_0 => "0000000000",
      CLK_COR_SEQ_2_4_1 => "0000000000",
      CLK_COR_SEQ_2_USE_0 => FALSE,
      CLK_COR_SEQ_2_USE_1 => FALSE,
      PCOMMA_10B_VALUE_0 => "0101111100",
      PCOMMA_10B_VALUE_1 => "0101111100",
      COMMA_DOUBLE_0 => FALSE,
      COMMA_DOUBLE_1 => FALSE,
      SATA_BURST_VAL_0 => "100",
      SATA_BURST_VAL_1 => "100",
      DEC_MCOMMA_DETECT_0 => TRUE,
      DEC_MCOMMA_DETECT_1 => TRUE,
      DEC_PCOMMA_DETECT_0 => TRUE,
      DEC_PCOMMA_DETECT_1 => TRUE,
      DEC_VALID_COMMA_ONLY_0 => TRUE,
      DEC_VALID_COMMA_ONLY_1 => TRUE,
      TXRX_INVERT_1 => "00000",
      COMMA_10B_ENABLE_0 => "1111111111",
      MCOMMA_DETECT_0 => TRUE,
      MCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_0 => "011",
      PCS_COM_CFG => X"1680A07",
      OOB_CLK_DIVIDER => 4,
      OVERSAMPLE_MODE => FALSE,
      PCI_EXPRESS_MODE_0 => TRUE,
      PCI_EXPRESS_MODE_1 => TRUE,
      TXRX_INVERT_0 => "00000",
      MCOMMA_10B_VALUE_0 => "1010000011",
      PCOMMA_DETECT_0 => TRUE,
      PCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_1 => "011",
      PLL_DIVSEL_FB => 1,
      PLL_DIVSEL_REF => 1,
      PLL_RXDIVSEL_OUT_0 => 1,
      PLL_RXDIVSEL_OUT_1 => 1,
      PLL_SATA_0 => FALSE,
      PLL_SATA_1 => FALSE,
      PLL_TXDIVSEL_COMM_OUT => 1,
      PLL_TXDIVSEL_OUT_0 => 1,
      PLL_TXDIVSEL_OUT_1 => 1,
      OOBDETECT_THRESHOLD_0 => "010",
      OOBDETECT_THRESHOLD_1 => "010",
      PMA_CDR_SCAN_0 => X"6C07640",
      PMA_CDR_SCAN_1 => X"6C07640",
      TRANS_TIME_NON_P2_1 => X"0019",
      TRANS_TIME_TO_P2_1 => X"0064",
      RCV_TERM_GND_0 => TRUE,
      RCV_TERM_GND_1 => TRUE,
      RCV_TERM_MID_0 => TRUE,
      RCV_TERM_MID_1 => TRUE,
      RCV_TERM_VTTRX_0 => FALSE,
      RCV_TERM_VTTRX_1 => FALSE,
      RX_BUFFER_USE_0 => TRUE,
      RX_BUFFER_USE_1 => TRUE,
      RX_DECODE_SEQ_MATCH_0 => TRUE,
      RX_DECODE_SEQ_MATCH_1 => TRUE,
      RX_LOSS_OF_SYNC_FSM_0 => FALSE,
      RX_LOSS_OF_SYNC_FSM_1 => FALSE,
      RX_LOS_INVALID_INCR_0 => 8,
      RX_LOS_INVALID_INCR_1 => 8,
      RX_LOS_THRESHOLD_0 => 128,
      RX_LOS_THRESHOLD_1 => 128,
      RX_SLIDE_MODE_0 => "PCS",
      RX_SLIDE_MODE_1 => "PCS",
      RX_STATUS_FMT_0 => "PCIE",
      RX_STATUS_FMT_1 => "PCIE",
      RX_XCLK_SEL_0 => "RXREC",
      RX_XCLK_SEL_1 => "RXREC",
      PRBS_ERR_THRESHOLD_1 => X"00000001",
      COM_BURST_VAL_0 => "1111",
      SATA_MAX_BURST_0 => 7,
      SATA_MAX_BURST_1 => 7,
      SATA_MAX_INIT_0 => 22,
      SATA_MAX_INIT_1 => 22,
      SATA_MAX_WAKE_0 => 7,
      SATA_MAX_WAKE_1 => 7,
      SATA_MIN_BURST_0 => 4,
      SATA_MIN_BURST_1 => 4,
      SATA_MIN_INIT_0 => 12,
      SATA_MIN_INIT_1 => 12,
      SATA_MIN_WAKE_0 => 4,
      SATA_MIN_WAKE_1 => 4,
      SIM_GTPRESET_SPEEDUP => 1,
      SIM_MODE => "FAST",
      COM_BURST_VAL_1 => "1111",
      SIM_RECEIVER_DETECT_PASS0 => TRUE,
      SIM_RECEIVER_DETECT_PASS1 => TRUE,
      PMA_RX_CFG_1 => X"09F0089",
      TERMINATION_IMP_0 => 50,
      TERMINATION_IMP_1 => 50,
      TERMINATION_OVRD => FALSE,
      CHAN_BOND_SEQ_1_ENABLE_1 => "1111",
      TRANS_TIME_NON_P2_0 => X"0019",
      CHAN_BOND_SEQ_2_ENABLE_1 => "1111",
      TRANS_TIME_TO_P2_0 => X"0064",
      TRANS_TIME_FROM_P2_0 => X"003C",
      TRANS_TIME_FROM_P2_1 => X"003C",
      TERMINATION_CTRL => "10100",
      TX_BUFFER_USE_0 => TRUE,
      TX_BUFFER_USE_1 => TRUE,
      TX_DIFF_BOOST_0 => TRUE,
      TX_DIFF_BOOST_1 => TRUE,
      TX_SYNC_FILTERB => 1,
      TX_XCLK_SEL_0 => "TXOUT",
      TX_XCLK_SEL_1 => "TXOUT",
      PMA_RX_CFG_0 => X"09F0089",
      PRBS_ERR_THRESHOLD_0 => X"00000001",
      SIM_PLL_PERDIV2 => X"190"
    )
    port map (
      CLKIN => refclk,
      REFCLKOUT => gt_refclk_out(0),
      RXRECCLK0 => NLW_GTD_0_GT_i_RXRECCLK0_UNCONNECTED,
      TXOUTCLK0 => gt_clk(0),
      TXUSRCLK0 => gt_usrclk,
      TXUSRCLK20 => gt_usrclk,
      RXUSRCLK0 => gt_usrclk,
      RXUSRCLK20 => gt_usrclk,
      RXRECCLK1 => NLW_GTD_0_GT_i_RXRECCLK1_UNCONNECTED,
      TXOUTCLK1 => NLW_GTD_0_GT_i_TXOUTCLK1_UNCONNECTED,
      TXUSRCLK1 => gt_usrclk,
      TXUSRCLK21 => gt_usrclk,
      RXUSRCLK1 => gt_usrclk,
      RXUSRCLK21 => gt_usrclk,
      TXP0 => gt_tx_p(0),
      TXN0 => gt_tx_n(0),
      RXP0 => gt_rx_p(0),
      RXN0 => gt_rx_n(0),
      TXP1 => gt_tx_p(1),
      TXN1 => gt_tx_n(1),
      RXP1 => gt_rx_p(1),
      RXN1 => gt_rx_n(1),
      RXVALID0 => gt_rx_valid_reg(0),
      RXVALID1 => gt_rx_valid_reg(1),
      GTPRESET => gtreset,
      RXCDRRESET0 => Q_and0000,
      TXRESET0 => Q_and0003,
      RXRESET0 => Q_and0002,
      RXBUFRESET0 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE0 => NlwRenamedSig_OI_resetdone(0),
      RXCDRRESET1 => Q_and0001,
      TXRESET1 => Q_and0003,
      RXRESET1 => Q_and0002,
      RXBUFRESET1 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE1 => NlwRenamedSig_OI_resetdone(1),
      PLLPOWERDOWN => NlwRenamedSig_OI_gt_do(16),
      REFCLKPWRDNB => N1,
      RXENEQB0 => N1,
      RXENEQB1 => N1,
      INTDATAWIDTH => N1,
      TXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      TXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXENPMAPHASEALIGN => TXENPMAPHASEALIGN,
      TXPMASETPHASE => TXPMASETPHASE,
      RXPMASETPHASE0 => NlwRenamedSig_OI_gt_do(16),
      RXPMASETPHASE1 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE0 => N1,
      TXPOLARITY0 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT0 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE1 => N1,
      TXPOLARITY1 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT1 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY0 => gt_rx_polarity_reg(0),
      RXENPCOMMAALIGN0 => N1,
      RXENMCOMMAALIGN0 => N1,
      RXSLIDE0 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE0 => N1,
      RXCOMMADET0 => NLW_GTD_0_GT_i_RXCOMMADET0_UNCONNECTED,
      RXBYTEREALIGN0 => NLW_GTD_0_GT_i_RXBYTEREALIGN0_UNCONNECTED,
      RXBYTEISALIGNED0 => rxbyteisaligned(0),
      RXDEC8B10BUSE0 => N1,
      RXENCHANSYNC0 => N1,
      RXCHANBONDSEQ0 => rxchanbondseq(0),
      RXCHANREALIGN0 => NLW_GTD_0_GT_i_RXCHANREALIGN0_UNCONNECTED,
      RXCHANISALIGNED0 => gt_rx_chanisaligned_reg(0),
      RXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY1 => gt_rx_polarity_reg(1),
      RXENPCOMMAALIGN1 => N1,
      RXENMCOMMAALIGN1 => N1,
      RXSLIDE1 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE1 => N1,
      RXCOMMADET1 => NLW_GTD_0_GT_i_RXCOMMADET1_UNCONNECTED,
      RXBYTEREALIGN1 => NLW_GTD_0_GT_i_RXBYTEREALIGN1_UNCONNECTED,
      RXBYTEISALIGNED1 => rxbyteisaligned(1),
      RXDEC8B10BUSE1 => N1,
      RXENCHANSYNC1 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ1 => rxchanbondseq(1),
      RXCHANREALIGN1 => NLW_GTD_0_GT_i_RXCHANREALIGN1_UNCONNECTED,
      RXCHANISALIGNED1 => gt_rx_chanisaligned_reg(1),
      RXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXELECIDLE0 => gt_tx_elec_idle_reg(0),
      TXDETECTRX0 => gt_tx_detect_rx_loopback_reg(0),
      TXELECIDLE1 => gt_tx_elec_idle_reg(1),
      TXDETECTRX1 => gt_tx_detect_rx_loopback_reg(1),
      PHYSTATUS0 => gt_rx_phy_status_reg(0),
      PHYSTATUS1 => gt_rx_phy_status_reg(1),
      RXELECIDLE0 => gt_rx_elec_idle_reg(0),
      RXELECIDLE1 => gt_rx_elec_idle_reg(1),
      TXCOMSTART0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMSTART1 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE1 => NlwRenamedSig_OI_gt_do(16),
      PLLLKDET => plllkdet_out(0),
      PLLLKDETEN => N1,
      PRBSCNTRESET0 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR0 => NLW_GTD_0_GT_i_RXPRBSERR0_UNCONNECTED,
      PRBSCNTRESET1 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR1 => NLW_GTD_0_GT_i_RXPRBSERR1_UNCONNECTED,
      DCLK => gt_dclk,
      DEN => gt_den(0),
      DWE => gt_dwen(0),
      DRDY => gt_drdy(0),
      RXENSAMPLEALIGN0 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR0 => NLW_GTD_0_GT_i_RXOVERSAMPLEERR0_UNCONNECTED,
      RXENSAMPLEALIGN1 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR1 => NLW_GTD_0_GT_i_RXOVERSAMPLEERR1_UNCONNECTED,
      RXELECIDLERESET0 => cdrreset(0),
      RXELECIDLERESET1 => cdrreset(1),
      RXENELECIDLERESETB => gt_rx_en_elec_idle_resetb(0),
      TXDATA0(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(7) => gt_tx_data_reg(7),
      TXDATA0(6) => gt_tx_data_reg(6),
      TXDATA0(5) => gt_tx_data_reg(5),
      TXDATA0(4) => gt_tx_data_reg(4),
      TXDATA0(3) => gt_tx_data_reg(3),
      TXDATA0(2) => gt_tx_data_reg(2),
      TXDATA0(1) => gt_tx_data_reg(1),
      TXDATA0(0) => gt_tx_data_reg(0),
      TXBYPASS8B10B0(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B0(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(0) => gt_tx_data_k_reg(0),
      TXCHARDISPMODE0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE0(0) => gt_tx_compliance_reg(0),
      TXCHARDISPVAL0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL0(0) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(7) => gt_tx_data_reg(15),
      TXDATA1(6) => gt_tx_data_reg(14),
      TXDATA1(5) => gt_tx_data_reg(13),
      TXDATA1(4) => gt_tx_data_reg(12),
      TXDATA1(3) => gt_tx_data_reg(11),
      TXDATA1(2) => gt_tx_data_reg(10),
      TXDATA1(1) => gt_tx_data_reg(9),
      TXDATA1(0) => gt_tx_data_reg(8),
      TXBYPASS8B10B1(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B1(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(0) => gt_tx_data_k_reg(1),
      TXCHARDISPMODE1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE1(0) => gt_tx_compliance_reg(1),
      TXCHARDISPVAL1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL1(0) => NlwRenamedSig_OI_gt_do(16),
      RXDATA0(15) => NLW_GTD_0_GT_i_RXDATA0_15_UNCONNECTED,
      RXDATA0(14) => NLW_GTD_0_GT_i_RXDATA0_14_UNCONNECTED,
      RXDATA0(13) => NLW_GTD_0_GT_i_RXDATA0_13_UNCONNECTED,
      RXDATA0(12) => NLW_GTD_0_GT_i_RXDATA0_12_UNCONNECTED,
      RXDATA0(11) => NLW_GTD_0_GT_i_RXDATA0_11_UNCONNECTED,
      RXDATA0(10) => NLW_GTD_0_GT_i_RXDATA0_10_UNCONNECTED,
      RXDATA0(9) => NLW_GTD_0_GT_i_RXDATA0_9_UNCONNECTED,
      RXDATA0(8) => NLW_GTD_0_GT_i_RXDATA0_8_UNCONNECTED,
      RXDATA0(7) => gt_rx_data_reg(7),
      RXDATA0(6) => gt_rx_data_reg(6),
      RXDATA0(5) => gt_rx_data_reg(5),
      RXDATA0(4) => gt_rx_data_reg(4),
      RXDATA0(3) => gt_rx_data_reg(3),
      RXDATA0(2) => gt_rx_data_reg(2),
      RXDATA0(1) => gt_rx_data_reg(1),
      RXDATA0(0) => gt_rx_data_reg(0),
      RXNOTINTABLE0(1) => NLW_GTD_0_GT_i_RXNOTINTABLE0_1_UNCONNECTED,
      RXNOTINTABLE0(0) => NLW_GTD_0_GT_i_RXNOTINTABLE0_0_UNCONNECTED,
      RXDISPERR0(1) => NLW_GTD_0_GT_i_RXDISPERR0_1_UNCONNECTED,
      RXDISPERR0(0) => NLW_GTD_0_GT_i_RXDISPERR0_0_UNCONNECTED,
      RXCHARISK0(1) => NLW_GTD_0_GT_i_RXCHARISK0_1_UNCONNECTED,
      RXCHARISK0(0) => gt_rx_data_k_reg(0),
      RXRUNDISP0(1) => NLW_GTD_0_GT_i_RXRUNDISP0_1_UNCONNECTED,
      RXRUNDISP0(0) => NLW_GTD_0_GT_i_RXRUNDISP0_0_UNCONNECTED,
      RXCHARISCOMMA0(1) => NLW_GTD_0_GT_i_RXCHARISCOMMA0_1_UNCONNECTED,
      RXCHARISCOMMA0(0) => NLW_GTD_0_GT_i_RXCHARISCOMMA0_0_UNCONNECTED,
      RXDATA1(15) => NLW_GTD_0_GT_i_RXDATA1_15_UNCONNECTED,
      RXDATA1(14) => NLW_GTD_0_GT_i_RXDATA1_14_UNCONNECTED,
      RXDATA1(13) => NLW_GTD_0_GT_i_RXDATA1_13_UNCONNECTED,
      RXDATA1(12) => NLW_GTD_0_GT_i_RXDATA1_12_UNCONNECTED,
      RXDATA1(11) => NLW_GTD_0_GT_i_RXDATA1_11_UNCONNECTED,
      RXDATA1(10) => NLW_GTD_0_GT_i_RXDATA1_10_UNCONNECTED,
      RXDATA1(9) => NLW_GTD_0_GT_i_RXDATA1_9_UNCONNECTED,
      RXDATA1(8) => NLW_GTD_0_GT_i_RXDATA1_8_UNCONNECTED,
      RXDATA1(7) => gt_rx_data_reg(15),
      RXDATA1(6) => gt_rx_data_reg(14),
      RXDATA1(5) => gt_rx_data_reg(13),
      RXDATA1(4) => gt_rx_data_reg(12),
      RXDATA1(3) => gt_rx_data_reg(11),
      RXDATA1(2) => gt_rx_data_reg(10),
      RXDATA1(1) => gt_rx_data_reg(9),
      RXDATA1(0) => gt_rx_data_reg(8),
      RXNOTINTABLE1(1) => NLW_GTD_0_GT_i_RXNOTINTABLE1_1_UNCONNECTED,
      RXNOTINTABLE1(0) => NLW_GTD_0_GT_i_RXNOTINTABLE1_0_UNCONNECTED,
      RXDISPERR1(1) => NLW_GTD_0_GT_i_RXDISPERR1_1_UNCONNECTED,
      RXDISPERR1(0) => NLW_GTD_0_GT_i_RXDISPERR1_0_UNCONNECTED,
      RXCHARISK1(1) => NLW_GTD_0_GT_i_RXCHARISK1_1_UNCONNECTED,
      RXCHARISK1(0) => gt_rx_data_k_reg(1),
      RXRUNDISP1(1) => NLW_GTD_0_GT_i_RXRUNDISP1_1_UNCONNECTED,
      RXRUNDISP1(0) => NLW_GTD_0_GT_i_RXRUNDISP1_0_UNCONNECTED,
      RXCHARISCOMMA1(1) => NLW_GTD_0_GT_i_RXCHARISCOMMA1_1_UNCONNECTED,
      RXCHARISCOMMA1(0) => NLW_GTD_0_GT_i_RXCHARISCOMMA1_0_UNCONNECTED,
      TXPOWERDOWN0(1) => gt_tx_power_down_reg(1),
      TXPOWERDOWN0(0) => gt_tx_power_down_reg(0),
      RXPOWERDOWN0(1) => gt_rx_power_down_reg(1),
      RXPOWERDOWN0(0) => gt_rx_power_down_reg(0),
      TXPOWERDOWN1(1) => gt_tx_power_down_reg(3),
      TXPOWERDOWN1(0) => gt_tx_power_down_reg(2),
      RXPOWERDOWN1(1) => gt_rx_power_down_reg(3),
      RXPOWERDOWN1(0) => gt_rx_power_down_reg(2),
      LOOPBACK0(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(0) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(0) => NlwRenamedSig_OI_gt_do(16),
      TXDIFFCTRL0(2) => gt_txdiffctrl_0(2),
      TXDIFFCTRL0(1) => gt_txdiffctrl_0(1),
      TXDIFFCTRL0(0) => gt_txdiffctrl_0(0),
      TXBUFDIFFCTRL0(2) => gt_txbuffctrl_0(2),
      TXBUFDIFFCTRL0(1) => gt_txbuffctrl_0(1),
      TXBUFDIFFCTRL0(0) => gt_txbuffctrl_0(0),
      TXPREEMPHASIS0(2) => gt_txpreemphesis_0(2),
      TXPREEMPHASIS0(1) => gt_txpreemphesis_0(1),
      TXPREEMPHASIS0(0) => gt_txpreemphesis_0(0),
      TXDIFFCTRL1(2) => gt_txdiffctrl_1(2),
      TXDIFFCTRL1(1) => gt_txdiffctrl_1(1),
      TXDIFFCTRL1(0) => gt_txdiffctrl_1(0),
      TXBUFDIFFCTRL1(2) => gt_txbuffctrl_1(2),
      TXBUFDIFFCTRL1(1) => gt_txbuffctrl_1(1),
      TXBUFDIFFCTRL1(0) => gt_txbuffctrl_1(0),
      TXPREEMPHASIS1(2) => gt_txpreemphesis_1(2),
      TXPREEMPHASIS1(1) => gt_txpreemphesis_1(1),
      TXPREEMPHASIS1(0) => gt_txpreemphesis_1(0),
      RXEQMIX0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX0(0) => N1,
      RXEQPOLE0(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(0) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(0) => N1,
      RXEQPOLE1(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(0) => NlwRenamedSig_OI_gt_do(16),
      TXKERR0(1) => NLW_GTD_0_GT_i_TXKERR0_1_UNCONNECTED,
      TXKERR0(0) => NLW_GTD_0_GT_i_TXKERR0_0_UNCONNECTED,
      TXRUNDISP0(1) => NLW_GTD_0_GT_i_TXRUNDISP0_1_UNCONNECTED,
      TXRUNDISP0(0) => NLW_GTD_0_GT_i_TXRUNDISP0_0_UNCONNECTED,
      TXBUFSTATUS0(1) => NLW_GTD_0_GT_i_TXBUFSTATUS0_1_UNCONNECTED,
      TXBUFSTATUS0(0) => NLW_GTD_0_GT_i_TXBUFSTATUS0_0_UNCONNECTED,
      TXKERR1(1) => NLW_GTD_0_GT_i_TXKERR1_1_UNCONNECTED,
      TXKERR1(0) => NLW_GTD_0_GT_i_TXKERR1_0_UNCONNECTED,
      TXRUNDISP1(1) => NLW_GTD_0_GT_i_TXRUNDISP1_1_UNCONNECTED,
      TXRUNDISP1(0) => NLW_GTD_0_GT_i_TXRUNDISP1_0_UNCONNECTED,
      TXBUFSTATUS1(1) => NLW_GTD_0_GT_i_TXBUFSTATUS1_1_UNCONNECTED,
      TXBUFSTATUS1(0) => NLW_GTD_0_GT_i_TXBUFSTATUS1_0_UNCONNECTED,
      RXLOSSOFSYNC0(1) => NLW_GTD_0_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED,
      RXLOSSOFSYNC0(0) => NLW_GTD_0_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED,
      RXCHBONDI0(2) => NlwRenamedSig_OI_gt_do(16),
      RXCHBONDI0(1) => NlwRenamedSig_OI_gt_do(16),
      RXCHBONDI0(0) => NlwRenamedSig_OI_gt_do(16),
      RXCHBONDO0(2) => gt_rx_chbond_o(0, 2),
      RXCHBONDO0(1) => gt_rx_chbond_o(0, 1),
      RXCHBONDO0(0) => gt_rx_chbond_o(0, 0),
      RXBUFSTATUS0(2) => NLW_GTD_0_GT_i_RXBUFSTATUS0_2_UNCONNECTED,
      RXBUFSTATUS0(1) => NLW_GTD_0_GT_i_RXBUFSTATUS0_1_UNCONNECTED,
      RXBUFSTATUS0(0) => NLW_GTD_0_GT_i_RXBUFSTATUS0_0_UNCONNECTED,
      RXLOSSOFSYNC1(1) => NLW_GTD_0_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED,
      RXLOSSOFSYNC1(0) => NLW_GTD_0_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED,
      RXCHBONDI1(2) => gt_rx_chbond_o(0, 2),
      RXCHBONDI1(1) => gt_rx_chbond_o(0, 1),
      RXCHBONDI1(0) => gt_rx_chbond_o(0, 0),
      RXCHBONDO1(2) => gt_rx_chbond_o(1, 2),
      RXCHBONDO1(1) => gt_rx_chbond_o(1, 1),
      RXCHBONDO1(0) => gt_rx_chbond_o(1, 0),
      RXBUFSTATUS1(2) => NLW_GTD_0_GT_i_RXBUFSTATUS1_2_UNCONNECTED,
      RXBUFSTATUS1(1) => NLW_GTD_0_GT_i_RXBUFSTATUS1_1_UNCONNECTED,
      RXBUFSTATUS1(0) => NLW_GTD_0_GT_i_RXBUFSTATUS1_0_UNCONNECTED,
      RXSTATUS0(2) => gt_rx_status_reg(2),
      RXSTATUS0(1) => gt_rx_status_reg(1),
      RXSTATUS0(0) => gt_rx_status_reg(0),
      RXCLKCORCNT0(2) => NLW_GTD_0_GT_i_RXCLKCORCNT0_2_UNCONNECTED,
      RXCLKCORCNT0(1) => NLW_GTD_0_GT_i_RXCLKCORCNT0_1_UNCONNECTED,
      RXCLKCORCNT0(0) => NLW_GTD_0_GT_i_RXCLKCORCNT0_0_UNCONNECTED,
      RXSTATUS1(2) => gt_rx_status_reg(5),
      RXSTATUS1(1) => gt_rx_status_reg(4),
      RXSTATUS1(0) => gt_rx_status_reg(3),
      RXCLKCORCNT1(2) => NLW_GTD_0_GT_i_RXCLKCORCNT1_2_UNCONNECTED,
      RXCLKCORCNT1(1) => NLW_GTD_0_GT_i_RXCLKCORCNT1_1_UNCONNECTED,
      RXCLKCORCNT1(0) => NLW_GTD_0_GT_i_RXCLKCORCNT1_0_UNCONNECTED,
      TXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      DADDR(6) => gt_daddr(6),
      DADDR(5) => gt_daddr(5),
      DADDR(4) => gt_daddr(4),
      DADDR(3) => gt_daddr(3),
      DADDR(2) => gt_daddr(2),
      DADDR(1) => gt_daddr(1),
      DADDR(0) => gt_daddr(0),
      DI(15) => gt_di(15),
      DI(14) => gt_di(14),
      DI(13) => gt_di(13),
      DI(12) => gt_di(12),
      DI(11) => gt_di(11),
      DI(10) => gt_di(10),
      DI(9) => gt_di(9),
      DI(8) => gt_di(8),
      DI(7) => gt_di(7),
      DI(6) => gt_di(6),
      DI(5) => gt_di(5),
      DI(4) => gt_di(4),
      DI(3) => gt_di(3),
      DI(2) => gt_di(2),
      DI(1) => gt_di(1),
      DI(0) => gt_di(0),
      DO(15) => gt_do(15),
      DO(14) => gt_do(14),
      DO(13) => gt_do(13),
      DO(12) => gt_do(12),
      DO(11) => gt_do(11),
      DO(10) => gt_do(10),
      DO(9) => gt_do(9),
      DO(8) => gt_do(8),
      DO(7) => gt_do(7),
      DO(6) => gt_do(6),
      DO(5) => gt_do(5),
      DO(4) => gt_do(4),
      DO(3) => gt_do(3),
      DO(2) => gt_do(2),
      DO(1) => gt_do(1),
      DO(0) => gt_do(0),
      GTPTEST(3) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(2) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(1) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(0) => NlwRenamedSig_OI_gt_do(16)
    );
  GTD_2_GT_i : GTP_DUAL
    generic map(
      AC_CAP_DIS_0 => FALSE,
      AC_CAP_DIS_1 => FALSE,
      ALIGN_COMMA_WORD_0 => 1,
      ALIGN_COMMA_WORD_1 => 1,
      CHAN_BOND_1_MAX_SKEW_0 => 7,
      CHAN_BOND_1_MAX_SKEW_1 => 7,
      CHAN_BOND_2_MAX_SKEW_0 => 7,
      CHAN_BOND_2_MAX_SKEW_1 => 7,
      CHAN_BOND_LEVEL_0 => 5,
      CHAN_BOND_LEVEL_1 => 4,
      CHAN_BOND_MODE_0 => "SLAVE",
      CHAN_BOND_MODE_1 => "SLAVE",
      CLK_COR_SEQ_1_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_1_ENABLE_0 => "1111",
      CLK_COR_SEQ_2_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_2_ENABLE_0 => "1111",
      CHAN_BOND_SEQ_1_1_0 => "0001001010",
      CHAN_BOND_SEQ_1_1_1 => "0001001010",
      CHAN_BOND_SEQ_1_2_0 => "0001001010",
      CHAN_BOND_SEQ_1_2_1 => "0001001010",
      CHAN_BOND_SEQ_2_3_0 => "0110111100",
      CHAN_BOND_SEQ_2_3_1 => "0110111100",
      CHAN_BOND_SEQ_1_3_0 => "0001001010",
      CHAN_BOND_SEQ_1_3_1 => "0001001010",
      CHAN_BOND_SEQ_1_4_0 => "0110111100",
      CHAN_BOND_SEQ_1_4_1 => "0110111100",
      CHAN_BOND_SEQ_2_1_0 => "0100111100",
      CHAN_BOND_SEQ_2_1_1 => "0100111100",
      CHAN_BOND_SEQ_2_2_0 => "0100111100",
      CHAN_BOND_SEQ_2_2_1 => "0100111100",
      CHAN_BOND_SEQ_2_4_0 => "0100011100",
      CHAN_BOND_SEQ_2_4_1 => "0100011100",
      CHAN_BOND_SEQ_2_USE_0 => TRUE,
      CHAN_BOND_SEQ_2_USE_1 => TRUE,
      CHAN_BOND_SEQ_LEN_0 => 4,
      CHAN_BOND_SEQ_LEN_1 => 4,
      CLK25_DIVIDER => 10,
      CLKINDC_B => TRUE,
      CLK_CORRECT_USE_0 => TRUE,
      CLK_CORRECT_USE_1 => TRUE,
      CLK_COR_ADJ_LEN_0 => 1,
      CLK_COR_ADJ_LEN_1 => 1,
      CLK_COR_DET_LEN_0 => 1,
      CLK_COR_DET_LEN_1 => 1,
      CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
      CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
      CLK_COR_KEEP_IDLE_0 => FALSE,
      CLK_COR_KEEP_IDLE_1 => FALSE,
      CLK_COR_MAX_LAT_0 => 18,
      CLK_COR_MAX_LAT_1 => 18,
      CLK_COR_MIN_LAT_0 => 16,
      CLK_COR_MIN_LAT_1 => 16,
      CLK_COR_PRECEDENCE_0 => TRUE,
      CLK_COR_PRECEDENCE_1 => TRUE,
      CLK_COR_REPEAT_WAIT_0 => 5,
      CLK_COR_REPEAT_WAIT_1 => 5,
      MCOMMA_10B_VALUE_1 => "1010000011",
      CLK_COR_SEQ_1_ENABLE_0 => "1111",
      COMMA_10B_ENABLE_1 => "1111111111",
      CLK_COR_SEQ_2_ENABLE_0 => "1111",
      CLK_COR_SEQ_1_1_0 => "0100011100",
      CLK_COR_SEQ_1_1_1 => "0100011100",
      CLK_COR_SEQ_1_2_0 => "0000000000",
      CLK_COR_SEQ_1_2_1 => "0000000000",
      CLK_COR_SEQ_2_3_0 => "0000000000",
      CLK_COR_SEQ_2_3_1 => "0000000000",
      CLK_COR_SEQ_1_3_0 => "0000000000",
      CLK_COR_SEQ_1_3_1 => "0000000000",
      CLK_COR_SEQ_1_4_0 => "0000000000",
      CLK_COR_SEQ_1_4_1 => "0000000000",
      CLK_COR_SEQ_2_1_0 => "0000000000",
      CLK_COR_SEQ_2_1_1 => "0000000000",
      CLK_COR_SEQ_2_2_0 => "0000000000",
      CLK_COR_SEQ_2_2_1 => "0000000000",
      CLK_COR_SEQ_2_4_0 => "0000000000",
      CLK_COR_SEQ_2_4_1 => "0000000000",
      CLK_COR_SEQ_2_USE_0 => FALSE,
      CLK_COR_SEQ_2_USE_1 => FALSE,
      PCOMMA_10B_VALUE_0 => "0101111100",
      PCOMMA_10B_VALUE_1 => "0101111100",
      COMMA_DOUBLE_0 => FALSE,
      COMMA_DOUBLE_1 => FALSE,
      SATA_BURST_VAL_0 => "100",
      SATA_BURST_VAL_1 => "100",
      DEC_MCOMMA_DETECT_0 => TRUE,
      DEC_MCOMMA_DETECT_1 => TRUE,
      DEC_PCOMMA_DETECT_0 => TRUE,
      DEC_PCOMMA_DETECT_1 => TRUE,
      DEC_VALID_COMMA_ONLY_0 => TRUE,
      DEC_VALID_COMMA_ONLY_1 => TRUE,
      TXRX_INVERT_1 => "00000",
      COMMA_10B_ENABLE_0 => "1111111111",
      MCOMMA_DETECT_0 => TRUE,
      MCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_0 => "011",
      PCS_COM_CFG => X"1680A07",
      OOB_CLK_DIVIDER => 4,
      OVERSAMPLE_MODE => FALSE,
      PCI_EXPRESS_MODE_0 => TRUE,
      PCI_EXPRESS_MODE_1 => TRUE,
      TXRX_INVERT_0 => "00000",
      MCOMMA_10B_VALUE_0 => "1010000011",
      PCOMMA_DETECT_0 => TRUE,
      PCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_1 => "011",
      PLL_DIVSEL_FB => 1,
      PLL_DIVSEL_REF => 1,
      PLL_RXDIVSEL_OUT_0 => 1,
      PLL_RXDIVSEL_OUT_1 => 1,
      PLL_SATA_0 => FALSE,
      PLL_SATA_1 => FALSE,
      PLL_TXDIVSEL_COMM_OUT => 1,
      PLL_TXDIVSEL_OUT_0 => 1,
      PLL_TXDIVSEL_OUT_1 => 1,
      OOBDETECT_THRESHOLD_0 => "010",
      OOBDETECT_THRESHOLD_1 => "010",
      PMA_CDR_SCAN_0 => X"6C07640",
      PMA_CDR_SCAN_1 => X"6C07640",
      TRANS_TIME_NON_P2_1 => X"0019",
      TRANS_TIME_TO_P2_1 => X"0064",
      RCV_TERM_GND_0 => TRUE,
      RCV_TERM_GND_1 => TRUE,
      RCV_TERM_MID_0 => TRUE,
      RCV_TERM_MID_1 => TRUE,
      RCV_TERM_VTTRX_0 => FALSE,
      RCV_TERM_VTTRX_1 => FALSE,
      RX_BUFFER_USE_0 => TRUE,
      RX_BUFFER_USE_1 => TRUE,
      RX_DECODE_SEQ_MATCH_0 => TRUE,
      RX_DECODE_SEQ_MATCH_1 => TRUE,
      RX_LOSS_OF_SYNC_FSM_0 => FALSE,
      RX_LOSS_OF_SYNC_FSM_1 => FALSE,
      RX_LOS_INVALID_INCR_0 => 8,
      RX_LOS_INVALID_INCR_1 => 8,
      RX_LOS_THRESHOLD_0 => 128,
      RX_LOS_THRESHOLD_1 => 128,
      RX_SLIDE_MODE_0 => "PCS",
      RX_SLIDE_MODE_1 => "PCS",
      RX_STATUS_FMT_0 => "PCIE",
      RX_STATUS_FMT_1 => "PCIE",
      RX_XCLK_SEL_0 => "RXREC",
      RX_XCLK_SEL_1 => "RXREC",
      PRBS_ERR_THRESHOLD_1 => X"00000001",
      COM_BURST_VAL_0 => "1111",
      SATA_MAX_BURST_0 => 7,
      SATA_MAX_BURST_1 => 7,
      SATA_MAX_INIT_0 => 22,
      SATA_MAX_INIT_1 => 22,
      SATA_MAX_WAKE_0 => 7,
      SATA_MAX_WAKE_1 => 7,
      SATA_MIN_BURST_0 => 4,
      SATA_MIN_BURST_1 => 4,
      SATA_MIN_INIT_0 => 12,
      SATA_MIN_INIT_1 => 12,
      SATA_MIN_WAKE_0 => 4,
      SATA_MIN_WAKE_1 => 4,
      SIM_GTPRESET_SPEEDUP => 1,
      SIM_MODE => "FAST",
      COM_BURST_VAL_1 => "1111",
      SIM_RECEIVER_DETECT_PASS0 => TRUE,
      SIM_RECEIVER_DETECT_PASS1 => TRUE,
      PMA_RX_CFG_1 => X"09F0089",
      TERMINATION_IMP_0 => 50,
      TERMINATION_IMP_1 => 50,
      TERMINATION_OVRD => FALSE,
      CHAN_BOND_SEQ_1_ENABLE_1 => "1111",
      TRANS_TIME_NON_P2_0 => X"0019",
      CHAN_BOND_SEQ_2_ENABLE_1 => "1111",
      TRANS_TIME_TO_P2_0 => X"0064",
      TRANS_TIME_FROM_P2_0 => X"003C",
      TRANS_TIME_FROM_P2_1 => X"003C",
      TERMINATION_CTRL => "10100",
      TX_BUFFER_USE_0 => TRUE,
      TX_BUFFER_USE_1 => TRUE,
      TX_DIFF_BOOST_0 => TRUE,
      TX_DIFF_BOOST_1 => TRUE,
      TX_SYNC_FILTERB => 1,
      TX_XCLK_SEL_0 => "TXOUT",
      TX_XCLK_SEL_1 => "TXOUT",
      PMA_RX_CFG_0 => X"09F0089",
      PRBS_ERR_THRESHOLD_0 => X"00000001",
      SIM_PLL_PERDIV2 => X"190"
    )
    port map (
      CLKIN => refclk,
      REFCLKOUT => NLW_GTD_2_GT_i_REFCLKOUT_UNCONNECTED,
      RXRECCLK0 => NLW_GTD_2_GT_i_RXRECCLK0_UNCONNECTED,
      TXOUTCLK0 => NLW_GTD_2_GT_i_TXOUTCLK0_UNCONNECTED,
      TXUSRCLK0 => gt_usrclk,
      TXUSRCLK20 => gt_usrclk,
      RXUSRCLK0 => gt_usrclk,
      RXUSRCLK20 => gt_usrclk,
      RXRECCLK1 => NLW_GTD_2_GT_i_RXRECCLK1_UNCONNECTED,
      TXOUTCLK1 => NLW_GTD_2_GT_i_TXOUTCLK1_UNCONNECTED,
      TXUSRCLK1 => gt_usrclk,
      TXUSRCLK21 => gt_usrclk,
      RXUSRCLK1 => gt_usrclk,
      RXUSRCLK21 => gt_usrclk,
      TXP0 => gt_tx_p(2),
      TXN0 => gt_tx_n(2),
      RXP0 => gt_rx_p(2),
      RXN0 => gt_rx_n(2),
      TXP1 => gt_tx_p(3),
      TXN1 => gt_tx_n(3),
      RXP1 => gt_rx_p(3),
      RXN1 => gt_rx_n(3),
      RXVALID0 => gt_rx_valid_reg(2),
      RXVALID1 => gt_rx_valid_reg(3),
      GTPRESET => gtreset,
      RXCDRRESET0 => Q_and0004,
      TXRESET0 => Q_and0003,
      RXRESET0 => Q_and0002,
      RXBUFRESET0 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE0 => NlwRenamedSig_OI_resetdone(2),
      RXCDRRESET1 => Q_and0005,
      TXRESET1 => Q_and0003,
      RXRESET1 => Q_and0002,
      RXBUFRESET1 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE1 => NlwRenamedSig_OI_resetdone(3),
      PLLPOWERDOWN => NlwRenamedSig_OI_gt_do(16),
      REFCLKPWRDNB => N1,
      RXENEQB0 => N1,
      RXENEQB1 => N1,
      INTDATAWIDTH => N1,
      TXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      TXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXENPMAPHASEALIGN => TXENPMAPHASEALIGN,
      TXPMASETPHASE => TXPMASETPHASE,
      RXPMASETPHASE0 => NlwRenamedSig_OI_gt_do(16),
      RXPMASETPHASE1 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE0 => N1,
      TXPOLARITY0 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT0 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE1 => N1,
      TXPOLARITY1 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT1 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY0 => gt_rx_polarity_reg(2),
      RXENPCOMMAALIGN0 => N1,
      RXENMCOMMAALIGN0 => N1,
      RXSLIDE0 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE0 => N1,
      RXCOMMADET0 => NLW_GTD_2_GT_i_RXCOMMADET0_UNCONNECTED,
      RXBYTEREALIGN0 => NLW_GTD_2_GT_i_RXBYTEREALIGN0_UNCONNECTED,
      RXBYTEISALIGNED0 => rxbyteisaligned(2),
      RXDEC8B10BUSE0 => N1,
      RXENCHANSYNC0 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ0 => rxchanbondseq(2),
      RXCHANREALIGN0 => NLW_GTD_2_GT_i_RXCHANREALIGN0_UNCONNECTED,
      RXCHANISALIGNED0 => gt_rx_chanisaligned_reg(2),
      RXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY1 => gt_rx_polarity_reg(3),
      RXENPCOMMAALIGN1 => N1,
      RXENMCOMMAALIGN1 => N1,
      RXSLIDE1 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE1 => N1,
      RXCOMMADET1 => NLW_GTD_2_GT_i_RXCOMMADET1_UNCONNECTED,
      RXBYTEREALIGN1 => NLW_GTD_2_GT_i_RXBYTEREALIGN1_UNCONNECTED,
      RXBYTEISALIGNED1 => rxbyteisaligned(3),
      RXDEC8B10BUSE1 => N1,
      RXENCHANSYNC1 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ1 => rxchanbondseq(3),
      RXCHANREALIGN1 => NLW_GTD_2_GT_i_RXCHANREALIGN1_UNCONNECTED,
      RXCHANISALIGNED1 => gt_rx_chanisaligned_reg(3),
      RXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXELECIDLE0 => gt_tx_elec_idle_reg(2),
      TXDETECTRX0 => gt_tx_detect_rx_loopback_reg(2),
      TXELECIDLE1 => gt_tx_elec_idle_reg(3),
      TXDETECTRX1 => gt_tx_detect_rx_loopback_reg(3),
      PHYSTATUS0 => gt_rx_phy_status_reg(2),
      PHYSTATUS1 => gt_rx_phy_status_reg(3),
      RXELECIDLE0 => gt_rx_elec_idle_reg(2),
      RXELECIDLE1 => gt_rx_elec_idle_reg(3),
      TXCOMSTART0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMSTART1 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE1 => NlwRenamedSig_OI_gt_do(16),
      PLLLKDET => plllkdet_out(1),
      PLLLKDETEN => N1,
      PRBSCNTRESET0 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR0 => NLW_GTD_2_GT_i_RXPRBSERR0_UNCONNECTED,
      PRBSCNTRESET1 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR1 => NLW_GTD_2_GT_i_RXPRBSERR1_UNCONNECTED,
      DCLK => gt_dclk,
      DEN => gt_den(2),
      DWE => gt_dwen(2),
      DRDY => gt_drdy(2),
      RXENSAMPLEALIGN0 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR0 => NLW_GTD_2_GT_i_RXOVERSAMPLEERR0_UNCONNECTED,
      RXENSAMPLEALIGN1 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR1 => NLW_GTD_2_GT_i_RXOVERSAMPLEERR1_UNCONNECTED,
      RXELECIDLERESET0 => cdrreset(2),
      RXELECIDLERESET1 => cdrreset(3),
      RXENELECIDLERESETB => gt_rx_en_elec_idle_resetb(1),
      TXDATA0(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(7) => gt_tx_data_reg(23),
      TXDATA0(6) => gt_tx_data_reg(22),
      TXDATA0(5) => gt_tx_data_reg(21),
      TXDATA0(4) => gt_tx_data_reg(20),
      TXDATA0(3) => gt_tx_data_reg(19),
      TXDATA0(2) => gt_tx_data_reg(18),
      TXDATA0(1) => gt_tx_data_reg(17),
      TXDATA0(0) => gt_tx_data_reg(16),
      TXBYPASS8B10B0(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B0(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(0) => gt_tx_data_k_reg(2),
      TXCHARDISPMODE0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE0(0) => gt_tx_compliance_reg(2),
      TXCHARDISPVAL0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL0(0) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(7) => gt_tx_data_reg(31),
      TXDATA1(6) => gt_tx_data_reg(30),
      TXDATA1(5) => gt_tx_data_reg(29),
      TXDATA1(4) => gt_tx_data_reg(28),
      TXDATA1(3) => gt_tx_data_reg(27),
      TXDATA1(2) => gt_tx_data_reg(26),
      TXDATA1(1) => gt_tx_data_reg(25),
      TXDATA1(0) => gt_tx_data_reg(24),
      TXBYPASS8B10B1(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B1(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(0) => gt_tx_data_k_reg(3),
      TXCHARDISPMODE1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE1(0) => gt_tx_compliance_reg(3),
      TXCHARDISPVAL1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL1(0) => NlwRenamedSig_OI_gt_do(16),
      RXDATA0(15) => NLW_GTD_2_GT_i_RXDATA0_15_UNCONNECTED,
      RXDATA0(14) => NLW_GTD_2_GT_i_RXDATA0_14_UNCONNECTED,
      RXDATA0(13) => NLW_GTD_2_GT_i_RXDATA0_13_UNCONNECTED,
      RXDATA0(12) => NLW_GTD_2_GT_i_RXDATA0_12_UNCONNECTED,
      RXDATA0(11) => NLW_GTD_2_GT_i_RXDATA0_11_UNCONNECTED,
      RXDATA0(10) => NLW_GTD_2_GT_i_RXDATA0_10_UNCONNECTED,
      RXDATA0(9) => NLW_GTD_2_GT_i_RXDATA0_9_UNCONNECTED,
      RXDATA0(8) => NLW_GTD_2_GT_i_RXDATA0_8_UNCONNECTED,
      RXDATA0(7) => gt_rx_data_reg(23),
      RXDATA0(6) => gt_rx_data_reg(22),
      RXDATA0(5) => gt_rx_data_reg(21),
      RXDATA0(4) => gt_rx_data_reg(20),
      RXDATA0(3) => gt_rx_data_reg(19),
      RXDATA0(2) => gt_rx_data_reg(18),
      RXDATA0(1) => gt_rx_data_reg(17),
      RXDATA0(0) => gt_rx_data_reg(16),
      RXNOTINTABLE0(1) => NLW_GTD_2_GT_i_RXNOTINTABLE0_1_UNCONNECTED,
      RXNOTINTABLE0(0) => NLW_GTD_2_GT_i_RXNOTINTABLE0_0_UNCONNECTED,
      RXDISPERR0(1) => NLW_GTD_2_GT_i_RXDISPERR0_1_UNCONNECTED,
      RXDISPERR0(0) => NLW_GTD_2_GT_i_RXDISPERR0_0_UNCONNECTED,
      RXCHARISK0(1) => NLW_GTD_2_GT_i_RXCHARISK0_1_UNCONNECTED,
      RXCHARISK0(0) => gt_rx_data_k_reg(2),
      RXRUNDISP0(1) => NLW_GTD_2_GT_i_RXRUNDISP0_1_UNCONNECTED,
      RXRUNDISP0(0) => NLW_GTD_2_GT_i_RXRUNDISP0_0_UNCONNECTED,
      RXCHARISCOMMA0(1) => NLW_GTD_2_GT_i_RXCHARISCOMMA0_1_UNCONNECTED,
      RXCHARISCOMMA0(0) => NLW_GTD_2_GT_i_RXCHARISCOMMA0_0_UNCONNECTED,
      RXDATA1(15) => NLW_GTD_2_GT_i_RXDATA1_15_UNCONNECTED,
      RXDATA1(14) => NLW_GTD_2_GT_i_RXDATA1_14_UNCONNECTED,
      RXDATA1(13) => NLW_GTD_2_GT_i_RXDATA1_13_UNCONNECTED,
      RXDATA1(12) => NLW_GTD_2_GT_i_RXDATA1_12_UNCONNECTED,
      RXDATA1(11) => NLW_GTD_2_GT_i_RXDATA1_11_UNCONNECTED,
      RXDATA1(10) => NLW_GTD_2_GT_i_RXDATA1_10_UNCONNECTED,
      RXDATA1(9) => NLW_GTD_2_GT_i_RXDATA1_9_UNCONNECTED,
      RXDATA1(8) => NLW_GTD_2_GT_i_RXDATA1_8_UNCONNECTED,
      RXDATA1(7) => gt_rx_data_reg(31),
      RXDATA1(6) => gt_rx_data_reg(30),
      RXDATA1(5) => gt_rx_data_reg(29),
      RXDATA1(4) => gt_rx_data_reg(28),
      RXDATA1(3) => gt_rx_data_reg(27),
      RXDATA1(2) => gt_rx_data_reg(26),
      RXDATA1(1) => gt_rx_data_reg(25),
      RXDATA1(0) => gt_rx_data_reg(24),
      RXNOTINTABLE1(1) => NLW_GTD_2_GT_i_RXNOTINTABLE1_1_UNCONNECTED,
      RXNOTINTABLE1(0) => NLW_GTD_2_GT_i_RXNOTINTABLE1_0_UNCONNECTED,
      RXDISPERR1(1) => NLW_GTD_2_GT_i_RXDISPERR1_1_UNCONNECTED,
      RXDISPERR1(0) => NLW_GTD_2_GT_i_RXDISPERR1_0_UNCONNECTED,
      RXCHARISK1(1) => NLW_GTD_2_GT_i_RXCHARISK1_1_UNCONNECTED,
      RXCHARISK1(0) => gt_rx_data_k_reg(3),
      RXRUNDISP1(1) => NLW_GTD_2_GT_i_RXRUNDISP1_1_UNCONNECTED,
      RXRUNDISP1(0) => NLW_GTD_2_GT_i_RXRUNDISP1_0_UNCONNECTED,
      RXCHARISCOMMA1(1) => NLW_GTD_2_GT_i_RXCHARISCOMMA1_1_UNCONNECTED,
      RXCHARISCOMMA1(0) => NLW_GTD_2_GT_i_RXCHARISCOMMA1_0_UNCONNECTED,
      TXPOWERDOWN0(1) => gt_tx_power_down_reg(5),
      TXPOWERDOWN0(0) => gt_tx_power_down_reg(4),
      RXPOWERDOWN0(1) => gt_rx_power_down_reg(5),
      RXPOWERDOWN0(0) => gt_rx_power_down_reg(4),
      TXPOWERDOWN1(1) => gt_tx_power_down_reg(7),
      TXPOWERDOWN1(0) => gt_tx_power_down_reg(6),
      RXPOWERDOWN1(1) => gt_rx_power_down_reg(7),
      RXPOWERDOWN1(0) => gt_rx_power_down_reg(6),
      LOOPBACK0(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(0) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(0) => NlwRenamedSig_OI_gt_do(16),
      TXDIFFCTRL0(2) => gt_txdiffctrl_0(2),
      TXDIFFCTRL0(1) => gt_txdiffctrl_0(1),
      TXDIFFCTRL0(0) => gt_txdiffctrl_0(0),
      TXBUFDIFFCTRL0(2) => gt_txbuffctrl_0(2),
      TXBUFDIFFCTRL0(1) => gt_txbuffctrl_0(1),
      TXBUFDIFFCTRL0(0) => gt_txbuffctrl_0(0),
      TXPREEMPHASIS0(2) => gt_txpreemphesis_0(2),
      TXPREEMPHASIS0(1) => gt_txpreemphesis_0(1),
      TXPREEMPHASIS0(0) => gt_txpreemphesis_0(0),
      TXDIFFCTRL1(2) => gt_txdiffctrl_1(2),
      TXDIFFCTRL1(1) => gt_txdiffctrl_1(1),
      TXDIFFCTRL1(0) => gt_txdiffctrl_1(0),
      TXBUFDIFFCTRL1(2) => gt_txbuffctrl_1(2),
      TXBUFDIFFCTRL1(1) => gt_txbuffctrl_1(1),
      TXBUFDIFFCTRL1(0) => gt_txbuffctrl_1(0),
      TXPREEMPHASIS1(2) => gt_txpreemphesis_1(2),
      TXPREEMPHASIS1(1) => gt_txpreemphesis_1(1),
      TXPREEMPHASIS1(0) => gt_txpreemphesis_1(0),
      RXEQMIX0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX0(0) => N1,
      RXEQPOLE0(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(0) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(0) => N1,
      RXEQPOLE1(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(0) => NlwRenamedSig_OI_gt_do(16),
      TXKERR0(1) => NLW_GTD_2_GT_i_TXKERR0_1_UNCONNECTED,
      TXKERR0(0) => NLW_GTD_2_GT_i_TXKERR0_0_UNCONNECTED,
      TXRUNDISP0(1) => NLW_GTD_2_GT_i_TXRUNDISP0_1_UNCONNECTED,
      TXRUNDISP0(0) => NLW_GTD_2_GT_i_TXRUNDISP0_0_UNCONNECTED,
      TXBUFSTATUS0(1) => NLW_GTD_2_GT_i_TXBUFSTATUS0_1_UNCONNECTED,
      TXBUFSTATUS0(0) => NLW_GTD_2_GT_i_TXBUFSTATUS0_0_UNCONNECTED,
      TXKERR1(1) => NLW_GTD_2_GT_i_TXKERR1_1_UNCONNECTED,
      TXKERR1(0) => NLW_GTD_2_GT_i_TXKERR1_0_UNCONNECTED,
      TXRUNDISP1(1) => NLW_GTD_2_GT_i_TXRUNDISP1_1_UNCONNECTED,
      TXRUNDISP1(0) => NLW_GTD_2_GT_i_TXRUNDISP1_0_UNCONNECTED,
      TXBUFSTATUS1(1) => NLW_GTD_2_GT_i_TXBUFSTATUS1_1_UNCONNECTED,
      TXBUFSTATUS1(0) => NLW_GTD_2_GT_i_TXBUFSTATUS1_0_UNCONNECTED,
      RXLOSSOFSYNC0(1) => NLW_GTD_2_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED,
      RXLOSSOFSYNC0(0) => NLW_GTD_2_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED,
      RXCHBONDI0(2) => gt_rx_chbond_o(1, 2),
      RXCHBONDI0(1) => gt_rx_chbond_o(1, 1),
      RXCHBONDI0(0) => gt_rx_chbond_o(1, 0),
      RXCHBONDO0(2) => gt_rx_chbond_o(2, 2),
      RXCHBONDO0(1) => gt_rx_chbond_o(2, 1),
      RXCHBONDO0(0) => gt_rx_chbond_o(2, 0),
      RXBUFSTATUS0(2) => NLW_GTD_2_GT_i_RXBUFSTATUS0_2_UNCONNECTED,
      RXBUFSTATUS0(1) => NLW_GTD_2_GT_i_RXBUFSTATUS0_1_UNCONNECTED,
      RXBUFSTATUS0(0) => NLW_GTD_2_GT_i_RXBUFSTATUS0_0_UNCONNECTED,
      RXLOSSOFSYNC1(1) => NLW_GTD_2_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED,
      RXLOSSOFSYNC1(0) => NLW_GTD_2_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED,
      RXCHBONDI1(2) => gt_rx_chbond_o(2, 2),
      RXCHBONDI1(1) => gt_rx_chbond_o(2, 1),
      RXCHBONDI1(0) => gt_rx_chbond_o(2, 0),
      RXCHBONDO1(2) => gt_rx_chbond_o(3, 2),
      RXCHBONDO1(1) => gt_rx_chbond_o(3, 1),
      RXCHBONDO1(0) => gt_rx_chbond_o(3, 0),
      RXBUFSTATUS1(2) => NLW_GTD_2_GT_i_RXBUFSTATUS1_2_UNCONNECTED,
      RXBUFSTATUS1(1) => NLW_GTD_2_GT_i_RXBUFSTATUS1_1_UNCONNECTED,
      RXBUFSTATUS1(0) => NLW_GTD_2_GT_i_RXBUFSTATUS1_0_UNCONNECTED,
      RXSTATUS0(2) => gt_rx_status_reg(8),
      RXSTATUS0(1) => gt_rx_status_reg(7),
      RXSTATUS0(0) => gt_rx_status_reg(6),
      RXCLKCORCNT0(2) => NLW_GTD_2_GT_i_RXCLKCORCNT0_2_UNCONNECTED,
      RXCLKCORCNT0(1) => NLW_GTD_2_GT_i_RXCLKCORCNT0_1_UNCONNECTED,
      RXCLKCORCNT0(0) => NLW_GTD_2_GT_i_RXCLKCORCNT0_0_UNCONNECTED,
      RXSTATUS1(2) => gt_rx_status_reg(11),
      RXSTATUS1(1) => gt_rx_status_reg(10),
      RXSTATUS1(0) => gt_rx_status_reg(9),
      RXCLKCORCNT1(2) => NLW_GTD_2_GT_i_RXCLKCORCNT1_2_UNCONNECTED,
      RXCLKCORCNT1(1) => NLW_GTD_2_GT_i_RXCLKCORCNT1_1_UNCONNECTED,
      RXCLKCORCNT1(0) => NLW_GTD_2_GT_i_RXCLKCORCNT1_0_UNCONNECTED,
      TXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      DADDR(6) => gt_daddr(20),
      DADDR(5) => gt_daddr(19),
      DADDR(4) => gt_daddr(18),
      DADDR(3) => gt_daddr(17),
      DADDR(2) => gt_daddr(16),
      DADDR(1) => gt_daddr(15),
      DADDR(0) => gt_daddr(14),
      DI(15) => gt_di(47),
      DI(14) => gt_di(46),
      DI(13) => gt_di(45),
      DI(12) => gt_di(44),
      DI(11) => gt_di(43),
      DI(10) => gt_di(42),
      DI(9) => gt_di(41),
      DI(8) => gt_di(40),
      DI(7) => gt_di(39),
      DI(6) => gt_di(38),
      DI(5) => gt_di(37),
      DI(4) => gt_di(36),
      DI(3) => gt_di(35),
      DI(2) => gt_di(34),
      DI(1) => gt_di(33),
      DI(0) => gt_di(32),
      DO(15) => gt_do(47),
      DO(14) => gt_do(46),
      DO(13) => gt_do(45),
      DO(12) => gt_do(44),
      DO(11) => gt_do(43),
      DO(10) => gt_do(42),
      DO(9) => gt_do(41),
      DO(8) => gt_do(40),
      DO(7) => gt_do(39),
      DO(6) => gt_do(38),
      DO(5) => gt_do(37),
      DO(4) => gt_do(36),
      DO(3) => gt_do(35),
      DO(2) => gt_do(34),
      DO(1) => gt_do(33),
      DO(0) => gt_do(32),
      GTPTEST(3) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(2) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(1) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(0) => NlwRenamedSig_OI_gt_do(16)
    );
  GTD_4_GT_i : GTP_DUAL
    generic map(
      AC_CAP_DIS_0 => FALSE,
      AC_CAP_DIS_1 => FALSE,
      ALIGN_COMMA_WORD_0 => 1,
      ALIGN_COMMA_WORD_1 => 1,
      CHAN_BOND_1_MAX_SKEW_0 => 7,
      CHAN_BOND_1_MAX_SKEW_1 => 7,
      CHAN_BOND_2_MAX_SKEW_0 => 7,
      CHAN_BOND_2_MAX_SKEW_1 => 7,
      CHAN_BOND_LEVEL_0 => 3,
      CHAN_BOND_LEVEL_1 => 2,
      CHAN_BOND_MODE_0 => "SLAVE",
      CHAN_BOND_MODE_1 => "SLAVE",
      CLK_COR_SEQ_1_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_1_ENABLE_0 => "1111",
      CLK_COR_SEQ_2_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_2_ENABLE_0 => "1111",
      CHAN_BOND_SEQ_1_1_0 => "0001001010",
      CHAN_BOND_SEQ_1_1_1 => "0001001010",
      CHAN_BOND_SEQ_1_2_0 => "0001001010",
      CHAN_BOND_SEQ_1_2_1 => "0001001010",
      CHAN_BOND_SEQ_2_3_0 => "0110111100",
      CHAN_BOND_SEQ_2_3_1 => "0110111100",
      CHAN_BOND_SEQ_1_3_0 => "0001001010",
      CHAN_BOND_SEQ_1_3_1 => "0001001010",
      CHAN_BOND_SEQ_1_4_0 => "0110111100",
      CHAN_BOND_SEQ_1_4_1 => "0110111100",
      CHAN_BOND_SEQ_2_1_0 => "0100111100",
      CHAN_BOND_SEQ_2_1_1 => "0100111100",
      CHAN_BOND_SEQ_2_2_0 => "0100111100",
      CHAN_BOND_SEQ_2_2_1 => "0100111100",
      CHAN_BOND_SEQ_2_4_0 => "0100011100",
      CHAN_BOND_SEQ_2_4_1 => "0100011100",
      CHAN_BOND_SEQ_2_USE_0 => TRUE,
      CHAN_BOND_SEQ_2_USE_1 => TRUE,
      CHAN_BOND_SEQ_LEN_0 => 4,
      CHAN_BOND_SEQ_LEN_1 => 4,
      CLK25_DIVIDER => 10,
      CLKINDC_B => TRUE,
      CLK_CORRECT_USE_0 => TRUE,
      CLK_CORRECT_USE_1 => TRUE,
      CLK_COR_ADJ_LEN_0 => 1,
      CLK_COR_ADJ_LEN_1 => 1,
      CLK_COR_DET_LEN_0 => 1,
      CLK_COR_DET_LEN_1 => 1,
      CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
      CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
      CLK_COR_KEEP_IDLE_0 => FALSE,
      CLK_COR_KEEP_IDLE_1 => FALSE,
      CLK_COR_MAX_LAT_0 => 18,
      CLK_COR_MAX_LAT_1 => 18,
      CLK_COR_MIN_LAT_0 => 16,
      CLK_COR_MIN_LAT_1 => 16,
      CLK_COR_PRECEDENCE_0 => TRUE,
      CLK_COR_PRECEDENCE_1 => TRUE,
      CLK_COR_REPEAT_WAIT_0 => 5,
      CLK_COR_REPEAT_WAIT_1 => 5,
      MCOMMA_10B_VALUE_1 => "1010000011",
      CLK_COR_SEQ_1_ENABLE_0 => "1111",
      COMMA_10B_ENABLE_1 => "1111111111",
      CLK_COR_SEQ_2_ENABLE_0 => "1111",
      CLK_COR_SEQ_1_1_0 => "0100011100",
      CLK_COR_SEQ_1_1_1 => "0100011100",
      CLK_COR_SEQ_1_2_0 => "0000000000",
      CLK_COR_SEQ_1_2_1 => "0000000000",
      CLK_COR_SEQ_2_3_0 => "0000000000",
      CLK_COR_SEQ_2_3_1 => "0000000000",
      CLK_COR_SEQ_1_3_0 => "0000000000",
      CLK_COR_SEQ_1_3_1 => "0000000000",
      CLK_COR_SEQ_1_4_0 => "0000000000",
      CLK_COR_SEQ_1_4_1 => "0000000000",
      CLK_COR_SEQ_2_1_0 => "0000000000",
      CLK_COR_SEQ_2_1_1 => "0000000000",
      CLK_COR_SEQ_2_2_0 => "0000000000",
      CLK_COR_SEQ_2_2_1 => "0000000000",
      CLK_COR_SEQ_2_4_0 => "0000000000",
      CLK_COR_SEQ_2_4_1 => "0000000000",
      CLK_COR_SEQ_2_USE_0 => FALSE,
      CLK_COR_SEQ_2_USE_1 => FALSE,
      PCOMMA_10B_VALUE_0 => "0101111100",
      PCOMMA_10B_VALUE_1 => "0101111100",
      COMMA_DOUBLE_0 => FALSE,
      COMMA_DOUBLE_1 => FALSE,
      SATA_BURST_VAL_0 => "100",
      SATA_BURST_VAL_1 => "100",
      DEC_MCOMMA_DETECT_0 => TRUE,
      DEC_MCOMMA_DETECT_1 => TRUE,
      DEC_PCOMMA_DETECT_0 => TRUE,
      DEC_PCOMMA_DETECT_1 => TRUE,
      DEC_VALID_COMMA_ONLY_0 => TRUE,
      DEC_VALID_COMMA_ONLY_1 => TRUE,
      TXRX_INVERT_1 => "00000",
      COMMA_10B_ENABLE_0 => "1111111111",
      MCOMMA_DETECT_0 => TRUE,
      MCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_0 => "011",
      PCS_COM_CFG => X"1680A07",
      OOB_CLK_DIVIDER => 4,
      OVERSAMPLE_MODE => FALSE,
      PCI_EXPRESS_MODE_0 => TRUE,
      PCI_EXPRESS_MODE_1 => TRUE,
      TXRX_INVERT_0 => "00000",
      MCOMMA_10B_VALUE_0 => "1010000011",
      PCOMMA_DETECT_0 => TRUE,
      PCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_1 => "011",
      PLL_DIVSEL_FB => 1,
      PLL_DIVSEL_REF => 1,
      PLL_RXDIVSEL_OUT_0 => 1,
      PLL_RXDIVSEL_OUT_1 => 1,
      PLL_SATA_0 => FALSE,
      PLL_SATA_1 => FALSE,
      PLL_TXDIVSEL_COMM_OUT => 1,
      PLL_TXDIVSEL_OUT_0 => 1,
      PLL_TXDIVSEL_OUT_1 => 1,
      OOBDETECT_THRESHOLD_0 => "010",
      OOBDETECT_THRESHOLD_1 => "010",
      PMA_CDR_SCAN_0 => X"6C07640",
      PMA_CDR_SCAN_1 => X"6C07640",
      TRANS_TIME_NON_P2_1 => X"0019",
      TRANS_TIME_TO_P2_1 => X"0064",
      RCV_TERM_GND_0 => TRUE,
      RCV_TERM_GND_1 => TRUE,
      RCV_TERM_MID_0 => TRUE,
      RCV_TERM_MID_1 => TRUE,
      RCV_TERM_VTTRX_0 => FALSE,
      RCV_TERM_VTTRX_1 => FALSE,
      RX_BUFFER_USE_0 => TRUE,
      RX_BUFFER_USE_1 => TRUE,
      RX_DECODE_SEQ_MATCH_0 => TRUE,
      RX_DECODE_SEQ_MATCH_1 => TRUE,
      RX_LOSS_OF_SYNC_FSM_0 => FALSE,
      RX_LOSS_OF_SYNC_FSM_1 => FALSE,
      RX_LOS_INVALID_INCR_0 => 8,
      RX_LOS_INVALID_INCR_1 => 8,
      RX_LOS_THRESHOLD_0 => 128,
      RX_LOS_THRESHOLD_1 => 128,
      RX_SLIDE_MODE_0 => "PCS",
      RX_SLIDE_MODE_1 => "PCS",
      RX_STATUS_FMT_0 => "PCIE",
      RX_STATUS_FMT_1 => "PCIE",
      RX_XCLK_SEL_0 => "RXREC",
      RX_XCLK_SEL_1 => "RXREC",
      PRBS_ERR_THRESHOLD_1 => X"00000001",
      COM_BURST_VAL_0 => "1111",
      SATA_MAX_BURST_0 => 7,
      SATA_MAX_BURST_1 => 7,
      SATA_MAX_INIT_0 => 22,
      SATA_MAX_INIT_1 => 22,
      SATA_MAX_WAKE_0 => 7,
      SATA_MAX_WAKE_1 => 7,
      SATA_MIN_BURST_0 => 4,
      SATA_MIN_BURST_1 => 4,
      SATA_MIN_INIT_0 => 12,
      SATA_MIN_INIT_1 => 12,
      SATA_MIN_WAKE_0 => 4,
      SATA_MIN_WAKE_1 => 4,
      SIM_GTPRESET_SPEEDUP => 1,
      SIM_MODE => "FAST",
      COM_BURST_VAL_1 => "1111",
      SIM_RECEIVER_DETECT_PASS0 => TRUE,
      SIM_RECEIVER_DETECT_PASS1 => TRUE,
      PMA_RX_CFG_1 => X"09F0089",
      TERMINATION_IMP_0 => 50,
      TERMINATION_IMP_1 => 50,
      TERMINATION_OVRD => FALSE,
      CHAN_BOND_SEQ_1_ENABLE_1 => "1111",
      TRANS_TIME_NON_P2_0 => X"0019",
      CHAN_BOND_SEQ_2_ENABLE_1 => "1111",
      TRANS_TIME_TO_P2_0 => X"0064",
      TRANS_TIME_FROM_P2_0 => X"003C",
      TRANS_TIME_FROM_P2_1 => X"003C",
      TERMINATION_CTRL => "10100",
      TX_BUFFER_USE_0 => TRUE,
      TX_BUFFER_USE_1 => TRUE,
      TX_DIFF_BOOST_0 => TRUE,
      TX_DIFF_BOOST_1 => TRUE,
      TX_SYNC_FILTERB => 1,
      TX_XCLK_SEL_0 => "TXOUT",
      TX_XCLK_SEL_1 => "TXOUT",
      PMA_RX_CFG_0 => X"09F0089",
      PRBS_ERR_THRESHOLD_0 => X"00000001",
      SIM_PLL_PERDIV2 => X"190"
    )
    port map (
      CLKIN => refclk,
      REFCLKOUT => NLW_GTD_4_GT_i_REFCLKOUT_UNCONNECTED,
      RXRECCLK0 => NLW_GTD_4_GT_i_RXRECCLK0_UNCONNECTED,
      TXOUTCLK0 => NLW_GTD_4_GT_i_TXOUTCLK0_UNCONNECTED,
      TXUSRCLK0 => gt_usrclk,
      TXUSRCLK20 => gt_usrclk,
      RXUSRCLK0 => gt_usrclk,
      RXUSRCLK20 => gt_usrclk,
      RXRECCLK1 => NLW_GTD_4_GT_i_RXRECCLK1_UNCONNECTED,
      TXOUTCLK1 => NLW_GTD_4_GT_i_TXOUTCLK1_UNCONNECTED,
      TXUSRCLK1 => gt_usrclk,
      TXUSRCLK21 => gt_usrclk,
      RXUSRCLK1 => gt_usrclk,
      RXUSRCLK21 => gt_usrclk,
      TXP0 => gt_tx_p(4),
      TXN0 => gt_tx_n(4),
      RXP0 => gt_rx_p(4),
      RXN0 => gt_rx_n(4),
      TXP1 => gt_tx_p(5),
      TXN1 => gt_tx_n(5),
      RXP1 => gt_rx_p(5),
      RXN1 => gt_rx_n(5),
      RXVALID0 => gt_rx_valid_reg(4),
      RXVALID1 => gt_rx_valid_reg(5),
      GTPRESET => gtreset,
      RXCDRRESET0 => Q_and0006,
      TXRESET0 => Q_and0003,
      RXRESET0 => Q_and0002,
      RXBUFRESET0 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE0 => NlwRenamedSig_OI_resetdone(4),
      RXCDRRESET1 => Q_and0007,
      TXRESET1 => Q_and0003,
      RXRESET1 => Q_and0002,
      RXBUFRESET1 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE1 => NlwRenamedSig_OI_resetdone(5),
      PLLPOWERDOWN => NlwRenamedSig_OI_gt_do(16),
      REFCLKPWRDNB => N1,
      RXENEQB0 => N1,
      RXENEQB1 => N1,
      INTDATAWIDTH => N1,
      TXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      TXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXENPMAPHASEALIGN => TXENPMAPHASEALIGN,
      TXPMASETPHASE => TXPMASETPHASE,
      RXPMASETPHASE0 => NlwRenamedSig_OI_gt_do(16),
      RXPMASETPHASE1 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE0 => N1,
      TXPOLARITY0 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT0 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE1 => N1,
      TXPOLARITY1 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT1 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY0 => gt_rx_polarity_reg(4),
      RXENPCOMMAALIGN0 => N1,
      RXENMCOMMAALIGN0 => N1,
      RXSLIDE0 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE0 => N1,
      RXCOMMADET0 => NLW_GTD_4_GT_i_RXCOMMADET0_UNCONNECTED,
      RXBYTEREALIGN0 => NLW_GTD_4_GT_i_RXBYTEREALIGN0_UNCONNECTED,
      RXBYTEISALIGNED0 => rxbyteisaligned(4),
      RXDEC8B10BUSE0 => N1,
      RXENCHANSYNC0 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ0 => rxchanbondseq(4),
      RXCHANREALIGN0 => NLW_GTD_4_GT_i_RXCHANREALIGN0_UNCONNECTED,
      RXCHANISALIGNED0 => gt_rx_chanisaligned_reg(4),
      RXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY1 => gt_rx_polarity_reg(5),
      RXENPCOMMAALIGN1 => N1,
      RXENMCOMMAALIGN1 => N1,
      RXSLIDE1 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE1 => N1,
      RXCOMMADET1 => NLW_GTD_4_GT_i_RXCOMMADET1_UNCONNECTED,
      RXBYTEREALIGN1 => NLW_GTD_4_GT_i_RXBYTEREALIGN1_UNCONNECTED,
      RXBYTEISALIGNED1 => rxbyteisaligned(5),
      RXDEC8B10BUSE1 => N1,
      RXENCHANSYNC1 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ1 => rxchanbondseq(5),
      RXCHANREALIGN1 => NLW_GTD_4_GT_i_RXCHANREALIGN1_UNCONNECTED,
      RXCHANISALIGNED1 => gt_rx_chanisaligned_reg(5),
      RXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXELECIDLE0 => gt_tx_elec_idle_reg(4),
      TXDETECTRX0 => gt_tx_detect_rx_loopback_reg(4),
      TXELECIDLE1 => gt_tx_elec_idle_reg(5),
      TXDETECTRX1 => gt_tx_detect_rx_loopback_reg(5),
      PHYSTATUS0 => gt_rx_phy_status_reg(4),
      PHYSTATUS1 => gt_rx_phy_status_reg(5),
      RXELECIDLE0 => gt_rx_elec_idle_reg(4),
      RXELECIDLE1 => gt_rx_elec_idle_reg(5),
      TXCOMSTART0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMSTART1 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE1 => NlwRenamedSig_OI_gt_do(16),
      PLLLKDET => plllkdet_out(2),
      PLLLKDETEN => N1,
      PRBSCNTRESET0 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR0 => NLW_GTD_4_GT_i_RXPRBSERR0_UNCONNECTED,
      PRBSCNTRESET1 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR1 => NLW_GTD_4_GT_i_RXPRBSERR1_UNCONNECTED,
      DCLK => gt_dclk,
      DEN => gt_den(4),
      DWE => gt_dwen(4),
      DRDY => gt_drdy(4),
      RXENSAMPLEALIGN0 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR0 => NLW_GTD_4_GT_i_RXOVERSAMPLEERR0_UNCONNECTED,
      RXENSAMPLEALIGN1 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR1 => NLW_GTD_4_GT_i_RXOVERSAMPLEERR1_UNCONNECTED,
      RXELECIDLERESET0 => cdrreset(4),
      RXELECIDLERESET1 => cdrreset(5),
      RXENELECIDLERESETB => gt_rx_en_elec_idle_resetb(2),
      TXDATA0(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(7) => gt_tx_data_reg(39),
      TXDATA0(6) => gt_tx_data_reg(38),
      TXDATA0(5) => gt_tx_data_reg(37),
      TXDATA0(4) => gt_tx_data_reg(36),
      TXDATA0(3) => gt_tx_data_reg(35),
      TXDATA0(2) => gt_tx_data_reg(34),
      TXDATA0(1) => gt_tx_data_reg(33),
      TXDATA0(0) => gt_tx_data_reg(32),
      TXBYPASS8B10B0(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B0(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(0) => gt_tx_data_k_reg(4),
      TXCHARDISPMODE0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE0(0) => gt_tx_compliance_reg(4),
      TXCHARDISPVAL0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL0(0) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(7) => gt_tx_data_reg(47),
      TXDATA1(6) => gt_tx_data_reg(46),
      TXDATA1(5) => gt_tx_data_reg(45),
      TXDATA1(4) => gt_tx_data_reg(44),
      TXDATA1(3) => gt_tx_data_reg(43),
      TXDATA1(2) => gt_tx_data_reg(42),
      TXDATA1(1) => gt_tx_data_reg(41),
      TXDATA1(0) => gt_tx_data_reg(40),
      TXBYPASS8B10B1(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B1(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(0) => gt_tx_data_k_reg(5),
      TXCHARDISPMODE1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE1(0) => gt_tx_compliance_reg(5),
      TXCHARDISPVAL1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL1(0) => NlwRenamedSig_OI_gt_do(16),
      RXDATA0(15) => NLW_GTD_4_GT_i_RXDATA0_15_UNCONNECTED,
      RXDATA0(14) => NLW_GTD_4_GT_i_RXDATA0_14_UNCONNECTED,
      RXDATA0(13) => NLW_GTD_4_GT_i_RXDATA0_13_UNCONNECTED,
      RXDATA0(12) => NLW_GTD_4_GT_i_RXDATA0_12_UNCONNECTED,
      RXDATA0(11) => NLW_GTD_4_GT_i_RXDATA0_11_UNCONNECTED,
      RXDATA0(10) => NLW_GTD_4_GT_i_RXDATA0_10_UNCONNECTED,
      RXDATA0(9) => NLW_GTD_4_GT_i_RXDATA0_9_UNCONNECTED,
      RXDATA0(8) => NLW_GTD_4_GT_i_RXDATA0_8_UNCONNECTED,
      RXDATA0(7) => gt_rx_data_reg(39),
      RXDATA0(6) => gt_rx_data_reg(38),
      RXDATA0(5) => gt_rx_data_reg(37),
      RXDATA0(4) => gt_rx_data_reg(36),
      RXDATA0(3) => gt_rx_data_reg(35),
      RXDATA0(2) => gt_rx_data_reg(34),
      RXDATA0(1) => gt_rx_data_reg(33),
      RXDATA0(0) => gt_rx_data_reg(32),
      RXNOTINTABLE0(1) => NLW_GTD_4_GT_i_RXNOTINTABLE0_1_UNCONNECTED,
      RXNOTINTABLE0(0) => NLW_GTD_4_GT_i_RXNOTINTABLE0_0_UNCONNECTED,
      RXDISPERR0(1) => NLW_GTD_4_GT_i_RXDISPERR0_1_UNCONNECTED,
      RXDISPERR0(0) => NLW_GTD_4_GT_i_RXDISPERR0_0_UNCONNECTED,
      RXCHARISK0(1) => NLW_GTD_4_GT_i_RXCHARISK0_1_UNCONNECTED,
      RXCHARISK0(0) => gt_rx_data_k_reg(4),
      RXRUNDISP0(1) => NLW_GTD_4_GT_i_RXRUNDISP0_1_UNCONNECTED,
      RXRUNDISP0(0) => NLW_GTD_4_GT_i_RXRUNDISP0_0_UNCONNECTED,
      RXCHARISCOMMA0(1) => NLW_GTD_4_GT_i_RXCHARISCOMMA0_1_UNCONNECTED,
      RXCHARISCOMMA0(0) => NLW_GTD_4_GT_i_RXCHARISCOMMA0_0_UNCONNECTED,
      RXDATA1(15) => NLW_GTD_4_GT_i_RXDATA1_15_UNCONNECTED,
      RXDATA1(14) => NLW_GTD_4_GT_i_RXDATA1_14_UNCONNECTED,
      RXDATA1(13) => NLW_GTD_4_GT_i_RXDATA1_13_UNCONNECTED,
      RXDATA1(12) => NLW_GTD_4_GT_i_RXDATA1_12_UNCONNECTED,
      RXDATA1(11) => NLW_GTD_4_GT_i_RXDATA1_11_UNCONNECTED,
      RXDATA1(10) => NLW_GTD_4_GT_i_RXDATA1_10_UNCONNECTED,
      RXDATA1(9) => NLW_GTD_4_GT_i_RXDATA1_9_UNCONNECTED,
      RXDATA1(8) => NLW_GTD_4_GT_i_RXDATA1_8_UNCONNECTED,
      RXDATA1(7) => gt_rx_data_reg(47),
      RXDATA1(6) => gt_rx_data_reg(46),
      RXDATA1(5) => gt_rx_data_reg(45),
      RXDATA1(4) => gt_rx_data_reg(44),
      RXDATA1(3) => gt_rx_data_reg(43),
      RXDATA1(2) => gt_rx_data_reg(42),
      RXDATA1(1) => gt_rx_data_reg(41),
      RXDATA1(0) => gt_rx_data_reg(40),
      RXNOTINTABLE1(1) => NLW_GTD_4_GT_i_RXNOTINTABLE1_1_UNCONNECTED,
      RXNOTINTABLE1(0) => NLW_GTD_4_GT_i_RXNOTINTABLE1_0_UNCONNECTED,
      RXDISPERR1(1) => NLW_GTD_4_GT_i_RXDISPERR1_1_UNCONNECTED,
      RXDISPERR1(0) => NLW_GTD_4_GT_i_RXDISPERR1_0_UNCONNECTED,
      RXCHARISK1(1) => NLW_GTD_4_GT_i_RXCHARISK1_1_UNCONNECTED,
      RXCHARISK1(0) => gt_rx_data_k_reg(5),
      RXRUNDISP1(1) => NLW_GTD_4_GT_i_RXRUNDISP1_1_UNCONNECTED,
      RXRUNDISP1(0) => NLW_GTD_4_GT_i_RXRUNDISP1_0_UNCONNECTED,
      RXCHARISCOMMA1(1) => NLW_GTD_4_GT_i_RXCHARISCOMMA1_1_UNCONNECTED,
      RXCHARISCOMMA1(0) => NLW_GTD_4_GT_i_RXCHARISCOMMA1_0_UNCONNECTED,
      TXPOWERDOWN0(1) => gt_tx_power_down_reg(9),
      TXPOWERDOWN0(0) => gt_tx_power_down_reg(8),
      RXPOWERDOWN0(1) => gt_rx_power_down_reg(9),
      RXPOWERDOWN0(0) => gt_rx_power_down_reg(8),
      TXPOWERDOWN1(1) => gt_tx_power_down_reg(11),
      TXPOWERDOWN1(0) => gt_tx_power_down_reg(10),
      RXPOWERDOWN1(1) => gt_rx_power_down_reg(11),
      RXPOWERDOWN1(0) => gt_rx_power_down_reg(10),
      LOOPBACK0(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(0) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(0) => NlwRenamedSig_OI_gt_do(16),
      TXDIFFCTRL0(2) => gt_txdiffctrl_0(2),
      TXDIFFCTRL0(1) => gt_txdiffctrl_0(1),
      TXDIFFCTRL0(0) => gt_txdiffctrl_0(0),
      TXBUFDIFFCTRL0(2) => gt_txbuffctrl_0(2),
      TXBUFDIFFCTRL0(1) => gt_txbuffctrl_0(1),
      TXBUFDIFFCTRL0(0) => gt_txbuffctrl_0(0),
      TXPREEMPHASIS0(2) => gt_txpreemphesis_0(2),
      TXPREEMPHASIS0(1) => gt_txpreemphesis_0(1),
      TXPREEMPHASIS0(0) => gt_txpreemphesis_0(0),
      TXDIFFCTRL1(2) => gt_txdiffctrl_1(2),
      TXDIFFCTRL1(1) => gt_txdiffctrl_1(1),
      TXDIFFCTRL1(0) => gt_txdiffctrl_1(0),
      TXBUFDIFFCTRL1(2) => gt_txbuffctrl_1(2),
      TXBUFDIFFCTRL1(1) => gt_txbuffctrl_1(1),
      TXBUFDIFFCTRL1(0) => gt_txbuffctrl_1(0),
      TXPREEMPHASIS1(2) => gt_txpreemphesis_1(2),
      TXPREEMPHASIS1(1) => gt_txpreemphesis_1(1),
      TXPREEMPHASIS1(0) => gt_txpreemphesis_1(0),
      RXEQMIX0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX0(0) => N1,
      RXEQPOLE0(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(0) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(0) => N1,
      RXEQPOLE1(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(0) => NlwRenamedSig_OI_gt_do(16),
      TXKERR0(1) => NLW_GTD_4_GT_i_TXKERR0_1_UNCONNECTED,
      TXKERR0(0) => NLW_GTD_4_GT_i_TXKERR0_0_UNCONNECTED,
      TXRUNDISP0(1) => NLW_GTD_4_GT_i_TXRUNDISP0_1_UNCONNECTED,
      TXRUNDISP0(0) => NLW_GTD_4_GT_i_TXRUNDISP0_0_UNCONNECTED,
      TXBUFSTATUS0(1) => NLW_GTD_4_GT_i_TXBUFSTATUS0_1_UNCONNECTED,
      TXBUFSTATUS0(0) => NLW_GTD_4_GT_i_TXBUFSTATUS0_0_UNCONNECTED,
      TXKERR1(1) => NLW_GTD_4_GT_i_TXKERR1_1_UNCONNECTED,
      TXKERR1(0) => NLW_GTD_4_GT_i_TXKERR1_0_UNCONNECTED,
      TXRUNDISP1(1) => NLW_GTD_4_GT_i_TXRUNDISP1_1_UNCONNECTED,
      TXRUNDISP1(0) => NLW_GTD_4_GT_i_TXRUNDISP1_0_UNCONNECTED,
      TXBUFSTATUS1(1) => NLW_GTD_4_GT_i_TXBUFSTATUS1_1_UNCONNECTED,
      TXBUFSTATUS1(0) => NLW_GTD_4_GT_i_TXBUFSTATUS1_0_UNCONNECTED,
      RXLOSSOFSYNC0(1) => NLW_GTD_4_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED,
      RXLOSSOFSYNC0(0) => NLW_GTD_4_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED,
      RXCHBONDI0(2) => gt_rx_chbond_o(3, 2),
      RXCHBONDI0(1) => gt_rx_chbond_o(3, 1),
      RXCHBONDI0(0) => gt_rx_chbond_o(3, 0),
      RXCHBONDO0(2) => gt_rx_chbond_o(4, 2),
      RXCHBONDO0(1) => gt_rx_chbond_o(4, 1),
      RXCHBONDO0(0) => gt_rx_chbond_o(4, 0),
      RXBUFSTATUS0(2) => NLW_GTD_4_GT_i_RXBUFSTATUS0_2_UNCONNECTED,
      RXBUFSTATUS0(1) => NLW_GTD_4_GT_i_RXBUFSTATUS0_1_UNCONNECTED,
      RXBUFSTATUS0(0) => NLW_GTD_4_GT_i_RXBUFSTATUS0_0_UNCONNECTED,
      RXLOSSOFSYNC1(1) => NLW_GTD_4_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED,
      RXLOSSOFSYNC1(0) => NLW_GTD_4_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED,
      RXCHBONDI1(2) => gt_rx_chbond_o(4, 2),
      RXCHBONDI1(1) => gt_rx_chbond_o(4, 1),
      RXCHBONDI1(0) => gt_rx_chbond_o(4, 0),
      RXCHBONDO1(2) => gt_rx_chbond_o(5, 2),
      RXCHBONDO1(1) => gt_rx_chbond_o(5, 1),
      RXCHBONDO1(0) => gt_rx_chbond_o(5, 0),
      RXBUFSTATUS1(2) => NLW_GTD_4_GT_i_RXBUFSTATUS1_2_UNCONNECTED,
      RXBUFSTATUS1(1) => NLW_GTD_4_GT_i_RXBUFSTATUS1_1_UNCONNECTED,
      RXBUFSTATUS1(0) => NLW_GTD_4_GT_i_RXBUFSTATUS1_0_UNCONNECTED,
      RXSTATUS0(2) => gt_rx_status_reg(14),
      RXSTATUS0(1) => gt_rx_status_reg(13),
      RXSTATUS0(0) => gt_rx_status_reg(12),
      RXCLKCORCNT0(2) => NLW_GTD_4_GT_i_RXCLKCORCNT0_2_UNCONNECTED,
      RXCLKCORCNT0(1) => NLW_GTD_4_GT_i_RXCLKCORCNT0_1_UNCONNECTED,
      RXCLKCORCNT0(0) => NLW_GTD_4_GT_i_RXCLKCORCNT0_0_UNCONNECTED,
      RXSTATUS1(2) => gt_rx_status_reg(17),
      RXSTATUS1(1) => gt_rx_status_reg(16),
      RXSTATUS1(0) => gt_rx_status_reg(15),
      RXCLKCORCNT1(2) => NLW_GTD_4_GT_i_RXCLKCORCNT1_2_UNCONNECTED,
      RXCLKCORCNT1(1) => NLW_GTD_4_GT_i_RXCLKCORCNT1_1_UNCONNECTED,
      RXCLKCORCNT1(0) => NLW_GTD_4_GT_i_RXCLKCORCNT1_0_UNCONNECTED,
      TXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      DADDR(6) => gt_daddr(34),
      DADDR(5) => gt_daddr(33),
      DADDR(4) => gt_daddr(32),
      DADDR(3) => gt_daddr(31),
      DADDR(2) => gt_daddr(30),
      DADDR(1) => gt_daddr(29),
      DADDR(0) => gt_daddr(28),
      DI(15) => gt_di(79),
      DI(14) => gt_di(78),
      DI(13) => gt_di(77),
      DI(12) => gt_di(76),
      DI(11) => gt_di(75),
      DI(10) => gt_di(74),
      DI(9) => gt_di(73),
      DI(8) => gt_di(72),
      DI(7) => gt_di(71),
      DI(6) => gt_di(70),
      DI(5) => gt_di(69),
      DI(4) => gt_di(68),
      DI(3) => gt_di(67),
      DI(2) => gt_di(66),
      DI(1) => gt_di(65),
      DI(0) => gt_di(64),
      DO(15) => gt_do(79),
      DO(14) => gt_do(78),
      DO(13) => gt_do(77),
      DO(12) => gt_do(76),
      DO(11) => gt_do(75),
      DO(10) => gt_do(74),
      DO(9) => gt_do(73),
      DO(8) => gt_do(72),
      DO(7) => gt_do(71),
      DO(6) => gt_do(70),
      DO(5) => gt_do(69),
      DO(4) => gt_do(68),
      DO(3) => gt_do(67),
      DO(2) => gt_do(66),
      DO(1) => gt_do(65),
      DO(0) => gt_do(64),
      GTPTEST(3) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(2) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(1) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(0) => NlwRenamedSig_OI_gt_do(16)
    );
  GTD_6_GT_i : GTP_DUAL
    generic map(
      AC_CAP_DIS_0 => FALSE,
      AC_CAP_DIS_1 => FALSE,
      ALIGN_COMMA_WORD_0 => 1,
      ALIGN_COMMA_WORD_1 => 1,
      CHAN_BOND_1_MAX_SKEW_0 => 7,
      CHAN_BOND_1_MAX_SKEW_1 => 7,
      CHAN_BOND_2_MAX_SKEW_0 => 7,
      CHAN_BOND_2_MAX_SKEW_1 => 7,
      CHAN_BOND_LEVEL_0 => 1,
      CHAN_BOND_LEVEL_1 => 0,
      CHAN_BOND_MODE_0 => "SLAVE",
      CHAN_BOND_MODE_1 => "SLAVE",
      CLK_COR_SEQ_1_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_1_ENABLE_0 => "1111",
      CLK_COR_SEQ_2_ENABLE_1 => "1111",
      CHAN_BOND_SEQ_2_ENABLE_0 => "1111",
      CHAN_BOND_SEQ_1_1_0 => "0001001010",
      CHAN_BOND_SEQ_1_1_1 => "0001001010",
      CHAN_BOND_SEQ_1_2_0 => "0001001010",
      CHAN_BOND_SEQ_1_2_1 => "0001001010",
      CHAN_BOND_SEQ_2_3_0 => "0110111100",
      CHAN_BOND_SEQ_2_3_1 => "0110111100",
      CHAN_BOND_SEQ_1_3_0 => "0001001010",
      CHAN_BOND_SEQ_1_3_1 => "0001001010",
      CHAN_BOND_SEQ_1_4_0 => "0110111100",
      CHAN_BOND_SEQ_1_4_1 => "0110111100",
      CHAN_BOND_SEQ_2_1_0 => "0100111100",
      CHAN_BOND_SEQ_2_1_1 => "0100111100",
      CHAN_BOND_SEQ_2_2_0 => "0100111100",
      CHAN_BOND_SEQ_2_2_1 => "0100111100",
      CHAN_BOND_SEQ_2_4_0 => "0100011100",
      CHAN_BOND_SEQ_2_4_1 => "0100011100",
      CHAN_BOND_SEQ_2_USE_0 => TRUE,
      CHAN_BOND_SEQ_2_USE_1 => TRUE,
      CHAN_BOND_SEQ_LEN_0 => 4,
      CHAN_BOND_SEQ_LEN_1 => 4,
      CLK25_DIVIDER => 10,
      CLKINDC_B => TRUE,
      CLK_CORRECT_USE_0 => TRUE,
      CLK_CORRECT_USE_1 => TRUE,
      CLK_COR_ADJ_LEN_0 => 1,
      CLK_COR_ADJ_LEN_1 => 1,
      CLK_COR_DET_LEN_0 => 1,
      CLK_COR_DET_LEN_1 => 1,
      CLK_COR_INSERT_IDLE_FLAG_0 => FALSE,
      CLK_COR_INSERT_IDLE_FLAG_1 => FALSE,
      CLK_COR_KEEP_IDLE_0 => FALSE,
      CLK_COR_KEEP_IDLE_1 => FALSE,
      CLK_COR_MAX_LAT_0 => 18,
      CLK_COR_MAX_LAT_1 => 18,
      CLK_COR_MIN_LAT_0 => 16,
      CLK_COR_MIN_LAT_1 => 16,
      CLK_COR_PRECEDENCE_0 => TRUE,
      CLK_COR_PRECEDENCE_1 => TRUE,
      CLK_COR_REPEAT_WAIT_0 => 5,
      CLK_COR_REPEAT_WAIT_1 => 5,
      MCOMMA_10B_VALUE_1 => "1010000011",
      CLK_COR_SEQ_1_ENABLE_0 => "1111",
      COMMA_10B_ENABLE_1 => "1111111111",
      CLK_COR_SEQ_2_ENABLE_0 => "1111",
      CLK_COR_SEQ_1_1_0 => "0100011100",
      CLK_COR_SEQ_1_1_1 => "0100011100",
      CLK_COR_SEQ_1_2_0 => "0000000000",
      CLK_COR_SEQ_1_2_1 => "0000000000",
      CLK_COR_SEQ_2_3_0 => "0000000000",
      CLK_COR_SEQ_2_3_1 => "0000000000",
      CLK_COR_SEQ_1_3_0 => "0000000000",
      CLK_COR_SEQ_1_3_1 => "0000000000",
      CLK_COR_SEQ_1_4_0 => "0000000000",
      CLK_COR_SEQ_1_4_1 => "0000000000",
      CLK_COR_SEQ_2_1_0 => "0000000000",
      CLK_COR_SEQ_2_1_1 => "0000000000",
      CLK_COR_SEQ_2_2_0 => "0000000000",
      CLK_COR_SEQ_2_2_1 => "0000000000",
      CLK_COR_SEQ_2_4_0 => "0000000000",
      CLK_COR_SEQ_2_4_1 => "0000000000",
      CLK_COR_SEQ_2_USE_0 => FALSE,
      CLK_COR_SEQ_2_USE_1 => FALSE,
      PCOMMA_10B_VALUE_0 => "0101111100",
      PCOMMA_10B_VALUE_1 => "0101111100",
      COMMA_DOUBLE_0 => FALSE,
      COMMA_DOUBLE_1 => FALSE,
      SATA_BURST_VAL_0 => "100",
      SATA_BURST_VAL_1 => "100",
      DEC_MCOMMA_DETECT_0 => TRUE,
      DEC_MCOMMA_DETECT_1 => TRUE,
      DEC_PCOMMA_DETECT_0 => TRUE,
      DEC_PCOMMA_DETECT_1 => TRUE,
      DEC_VALID_COMMA_ONLY_0 => TRUE,
      DEC_VALID_COMMA_ONLY_1 => TRUE,
      TXRX_INVERT_1 => "00000",
      COMMA_10B_ENABLE_0 => "1111111111",
      MCOMMA_DETECT_0 => TRUE,
      MCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_0 => "011",
      PCS_COM_CFG => X"1680A07",
      OOB_CLK_DIVIDER => 4,
      OVERSAMPLE_MODE => FALSE,
      PCI_EXPRESS_MODE_0 => TRUE,
      PCI_EXPRESS_MODE_1 => TRUE,
      TXRX_INVERT_0 => "00000",
      MCOMMA_10B_VALUE_0 => "1010000011",
      PCOMMA_DETECT_0 => TRUE,
      PCOMMA_DETECT_1 => TRUE,
      SATA_IDLE_VAL_1 => "011",
      PLL_DIVSEL_FB => 1,
      PLL_DIVSEL_REF => 1,
      PLL_RXDIVSEL_OUT_0 => 1,
      PLL_RXDIVSEL_OUT_1 => 1,
      PLL_SATA_0 => FALSE,
      PLL_SATA_1 => FALSE,
      PLL_TXDIVSEL_COMM_OUT => 1,
      PLL_TXDIVSEL_OUT_0 => 1,
      PLL_TXDIVSEL_OUT_1 => 1,
      OOBDETECT_THRESHOLD_0 => "010",
      OOBDETECT_THRESHOLD_1 => "010",
      PMA_CDR_SCAN_0 => X"6C07640",
      PMA_CDR_SCAN_1 => X"6C07640",
      TRANS_TIME_NON_P2_1 => X"0019",
      TRANS_TIME_TO_P2_1 => X"0064",
      RCV_TERM_GND_0 => TRUE,
      RCV_TERM_GND_1 => TRUE,
      RCV_TERM_MID_0 => TRUE,
      RCV_TERM_MID_1 => TRUE,
      RCV_TERM_VTTRX_0 => FALSE,
      RCV_TERM_VTTRX_1 => FALSE,
      RX_BUFFER_USE_0 => TRUE,
      RX_BUFFER_USE_1 => TRUE,
      RX_DECODE_SEQ_MATCH_0 => TRUE,
      RX_DECODE_SEQ_MATCH_1 => TRUE,
      RX_LOSS_OF_SYNC_FSM_0 => FALSE,
      RX_LOSS_OF_SYNC_FSM_1 => FALSE,
      RX_LOS_INVALID_INCR_0 => 8,
      RX_LOS_INVALID_INCR_1 => 8,
      RX_LOS_THRESHOLD_0 => 128,
      RX_LOS_THRESHOLD_1 => 128,
      RX_SLIDE_MODE_0 => "PCS",
      RX_SLIDE_MODE_1 => "PCS",
      RX_STATUS_FMT_0 => "PCIE",
      RX_STATUS_FMT_1 => "PCIE",
      RX_XCLK_SEL_0 => "RXREC",
      RX_XCLK_SEL_1 => "RXREC",
      PRBS_ERR_THRESHOLD_1 => X"00000001",
      COM_BURST_VAL_0 => "1111",
      SATA_MAX_BURST_0 => 7,
      SATA_MAX_BURST_1 => 7,
      SATA_MAX_INIT_0 => 22,
      SATA_MAX_INIT_1 => 22,
      SATA_MAX_WAKE_0 => 7,
      SATA_MAX_WAKE_1 => 7,
      SATA_MIN_BURST_0 => 4,
      SATA_MIN_BURST_1 => 4,
      SATA_MIN_INIT_0 => 12,
      SATA_MIN_INIT_1 => 12,
      SATA_MIN_WAKE_0 => 4,
      SATA_MIN_WAKE_1 => 4,
      SIM_GTPRESET_SPEEDUP => 1,
      SIM_MODE => "FAST",
      COM_BURST_VAL_1 => "1111",
      SIM_RECEIVER_DETECT_PASS0 => TRUE,
      SIM_RECEIVER_DETECT_PASS1 => TRUE,
      PMA_RX_CFG_1 => X"09F0089",
      TERMINATION_IMP_0 => 50,
      TERMINATION_IMP_1 => 50,
      TERMINATION_OVRD => FALSE,
      CHAN_BOND_SEQ_1_ENABLE_1 => "1111",
      TRANS_TIME_NON_P2_0 => X"0019",
      CHAN_BOND_SEQ_2_ENABLE_1 => "1111",
      TRANS_TIME_TO_P2_0 => X"0064",
      TRANS_TIME_FROM_P2_0 => X"003C",
      TRANS_TIME_FROM_P2_1 => X"003C",
      TERMINATION_CTRL => "10100",
      TX_BUFFER_USE_0 => TRUE,
      TX_BUFFER_USE_1 => TRUE,
      TX_DIFF_BOOST_0 => TRUE,
      TX_DIFF_BOOST_1 => TRUE,
      TX_SYNC_FILTERB => 1,
      TX_XCLK_SEL_0 => "TXOUT",
      TX_XCLK_SEL_1 => "TXOUT",
      PMA_RX_CFG_0 => X"09F0089",
      PRBS_ERR_THRESHOLD_0 => X"00000001",
      SIM_PLL_PERDIV2 => X"190"
    )
    port map (
      CLKIN => refclk,
      REFCLKOUT => NLW_GTD_6_GT_i_REFCLKOUT_UNCONNECTED,
      RXRECCLK0 => NLW_GTD_6_GT_i_RXRECCLK0_UNCONNECTED,
      TXOUTCLK0 => NLW_GTD_6_GT_i_TXOUTCLK0_UNCONNECTED,
      TXUSRCLK0 => gt_usrclk,
      TXUSRCLK20 => gt_usrclk,
      RXUSRCLK0 => gt_usrclk,
      RXUSRCLK20 => gt_usrclk,
      RXRECCLK1 => NLW_GTD_6_GT_i_RXRECCLK1_UNCONNECTED,
      TXOUTCLK1 => NLW_GTD_6_GT_i_TXOUTCLK1_UNCONNECTED,
      TXUSRCLK1 => gt_usrclk,
      TXUSRCLK21 => gt_usrclk,
      RXUSRCLK1 => gt_usrclk,
      RXUSRCLK21 => gt_usrclk,
      TXP0 => gt_tx_p(6),
      TXN0 => gt_tx_n(6),
      RXP0 => gt_rx_p(6),
      RXN0 => gt_rx_n(6),
      TXP1 => gt_tx_p(7),
      TXN1 => gt_tx_n(7),
      RXP1 => gt_rx_p(7),
      RXN1 => gt_rx_n(7),
      RXVALID0 => gt_rx_valid_reg(6),
      RXVALID1 => gt_rx_valid_reg(7),
      GTPRESET => gtreset,
      RXCDRRESET0 => Q_and0008,
      TXRESET0 => Q_and0003,
      RXRESET0 => Q_and0002,
      RXBUFRESET0 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE0 => NlwRenamedSig_OI_resetdone(6),
      RXCDRRESET1 => Q_and0009,
      TXRESET1 => Q_and0003,
      RXRESET1 => Q_and0002,
      RXBUFRESET1 => NlwRenamedSig_OI_gt_do(16),
      RESETDONE1 => NlwRenamedSig_OI_resetdone(7),
      PLLPOWERDOWN => NlwRenamedSig_OI_gt_do(16),
      REFCLKPWRDNB => N1,
      RXENEQB0 => N1,
      RXENEQB1 => N1,
      INTDATAWIDTH => N1,
      TXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      TXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXENPMAPHASEALIGN => TXENPMAPHASEALIGN,
      TXPMASETPHASE => TXPMASETPHASE,
      RXPMASETPHASE0 => NlwRenamedSig_OI_gt_do(16),
      RXPMASETPHASE1 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE0 => N1,
      TXPOLARITY0 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT0 => NlwRenamedSig_OI_gt_do(16),
      TXENC8B10BUSE1 => N1,
      TXPOLARITY1 => NlwRenamedSig_OI_gt_do(16),
      TXINHIBIT1 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY0 => gt_rx_polarity_reg(6),
      RXENPCOMMAALIGN0 => N1,
      RXENMCOMMAALIGN0 => N1,
      RXSLIDE0 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE0 => N1,
      RXCOMMADET0 => NLW_GTD_6_GT_i_RXCOMMADET0_UNCONNECTED,
      RXBYTEREALIGN0 => NLW_GTD_6_GT_i_RXBYTEREALIGN0_UNCONNECTED,
      RXBYTEISALIGNED0 => rxbyteisaligned(6),
      RXDEC8B10BUSE0 => N1,
      RXENCHANSYNC0 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ0 => rxchanbondseq(6),
      RXCHANREALIGN0 => NLW_GTD_6_GT_i_RXCHANREALIGN0_UNCONNECTED,
      RXCHANISALIGNED0 => gt_rx_chanisaligned_reg(6),
      RXDATAWIDTH0 => NlwRenamedSig_OI_gt_do(16),
      RXPOLARITY1 => gt_rx_polarity_reg(7),
      RXENPCOMMAALIGN1 => N1,
      RXENMCOMMAALIGN1 => N1,
      RXSLIDE1 => NlwRenamedSig_OI_gt_do(16),
      RXCOMMADETUSE1 => N1,
      RXCOMMADET1 => NLW_GTD_6_GT_i_RXCOMMADET1_UNCONNECTED,
      RXBYTEREALIGN1 => NLW_GTD_6_GT_i_RXBYTEREALIGN1_UNCONNECTED,
      RXBYTEISALIGNED1 => rxbyteisaligned(7),
      RXDEC8B10BUSE1 => N1,
      RXENCHANSYNC1 => NlwRenamedSig_OI_gt_do(16),
      RXCHANBONDSEQ1 => rxchanbondseq(7),
      RXCHANREALIGN1 => NLW_GTD_6_GT_i_RXCHANREALIGN1_UNCONNECTED,
      RXCHANISALIGNED1 => gt_rx_chanisaligned_reg(7),
      RXDATAWIDTH1 => NlwRenamedSig_OI_gt_do(16),
      TXELECIDLE0 => gt_tx_elec_idle_reg(6),
      TXDETECTRX0 => gt_tx_detect_rx_loopback_reg(6),
      TXELECIDLE1 => gt_tx_elec_idle_reg(7),
      TXDETECTRX1 => gt_tx_detect_rx_loopback_reg(7),
      PHYSTATUS0 => gt_rx_phy_status_reg(6),
      PHYSTATUS1 => gt_rx_phy_status_reg(7),
      RXELECIDLE0 => gt_rx_elec_idle_reg(6),
      RXELECIDLE1 => gt_rx_elec_idle_reg(7),
      TXCOMSTART0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE0 => NlwRenamedSig_OI_gt_do(16),
      TXCOMSTART1 => NlwRenamedSig_OI_gt_do(16),
      TXCOMTYPE1 => NlwRenamedSig_OI_gt_do(16),
      PLLLKDET => plllkdet_out(3),
      PLLLKDETEN => N1,
      PRBSCNTRESET0 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR0 => NLW_GTD_6_GT_i_RXPRBSERR0_UNCONNECTED,
      PRBSCNTRESET1 => NlwRenamedSig_OI_gt_do(16),
      RXPRBSERR1 => NLW_GTD_6_GT_i_RXPRBSERR1_UNCONNECTED,
      DCLK => gt_dclk,
      DEN => gt_den(6),
      DWE => gt_dwen(6),
      DRDY => gt_drdy(6),
      RXENSAMPLEALIGN0 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR0 => NLW_GTD_6_GT_i_RXOVERSAMPLEERR0_UNCONNECTED,
      RXENSAMPLEALIGN1 => NlwRenamedSig_OI_gt_do(16),
      RXOVERSAMPLEERR1 => NLW_GTD_6_GT_i_RXOVERSAMPLEERR1_UNCONNECTED,
      RXELECIDLERESET0 => cdrreset(6),
      RXELECIDLERESET1 => cdrreset(7),
      RXENELECIDLERESETB => gt_rx_en_elec_idle_resetb(3),
      TXDATA0(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA0(7) => gt_tx_data_reg(55),
      TXDATA0(6) => gt_tx_data_reg(54),
      TXDATA0(5) => gt_tx_data_reg(53),
      TXDATA0(4) => gt_tx_data_reg(52),
      TXDATA0(3) => gt_tx_data_reg(51),
      TXDATA0(2) => gt_tx_data_reg(50),
      TXDATA0(1) => gt_tx_data_reg(49),
      TXDATA0(0) => gt_tx_data_reg(48),
      TXBYPASS8B10B0(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B0(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK0(0) => gt_tx_data_k_reg(6),
      TXCHARDISPMODE0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE0(0) => gt_tx_compliance_reg(6),
      TXCHARDISPVAL0(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL0(0) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(15) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(14) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(13) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(12) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(11) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(10) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(9) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(8) => NlwRenamedSig_OI_gt_do(16),
      TXDATA1(7) => gt_tx_data_reg(63),
      TXDATA1(6) => gt_tx_data_reg(62),
      TXDATA1(5) => gt_tx_data_reg(61),
      TXDATA1(4) => gt_tx_data_reg(60),
      TXDATA1(3) => gt_tx_data_reg(59),
      TXDATA1(2) => gt_tx_data_reg(58),
      TXDATA1(1) => gt_tx_data_reg(57),
      TXDATA1(0) => gt_tx_data_reg(56),
      TXBYPASS8B10B1(1) => NlwRenamedSig_OI_gt_do(16),
      TXBYPASS8B10B1(0) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARISK1(0) => gt_tx_data_k_reg(7),
      TXCHARDISPMODE1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPMODE1(0) => gt_tx_compliance_reg(7),
      TXCHARDISPVAL1(1) => NlwRenamedSig_OI_gt_do(16),
      TXCHARDISPVAL1(0) => NlwRenamedSig_OI_gt_do(16),
      RXDATA0(15) => NLW_GTD_6_GT_i_RXDATA0_15_UNCONNECTED,
      RXDATA0(14) => NLW_GTD_6_GT_i_RXDATA0_14_UNCONNECTED,
      RXDATA0(13) => NLW_GTD_6_GT_i_RXDATA0_13_UNCONNECTED,
      RXDATA0(12) => NLW_GTD_6_GT_i_RXDATA0_12_UNCONNECTED,
      RXDATA0(11) => NLW_GTD_6_GT_i_RXDATA0_11_UNCONNECTED,
      RXDATA0(10) => NLW_GTD_6_GT_i_RXDATA0_10_UNCONNECTED,
      RXDATA0(9) => NLW_GTD_6_GT_i_RXDATA0_9_UNCONNECTED,
      RXDATA0(8) => NLW_GTD_6_GT_i_RXDATA0_8_UNCONNECTED,
      RXDATA0(7) => gt_rx_data_reg(55),
      RXDATA0(6) => gt_rx_data_reg(54),
      RXDATA0(5) => gt_rx_data_reg(53),
      RXDATA0(4) => gt_rx_data_reg(52),
      RXDATA0(3) => gt_rx_data_reg(51),
      RXDATA0(2) => gt_rx_data_reg(50),
      RXDATA0(1) => gt_rx_data_reg(49),
      RXDATA0(0) => gt_rx_data_reg(48),
      RXNOTINTABLE0(1) => NLW_GTD_6_GT_i_RXNOTINTABLE0_1_UNCONNECTED,
      RXNOTINTABLE0(0) => NLW_GTD_6_GT_i_RXNOTINTABLE0_0_UNCONNECTED,
      RXDISPERR0(1) => NLW_GTD_6_GT_i_RXDISPERR0_1_UNCONNECTED,
      RXDISPERR0(0) => NLW_GTD_6_GT_i_RXDISPERR0_0_UNCONNECTED,
      RXCHARISK0(1) => NLW_GTD_6_GT_i_RXCHARISK0_1_UNCONNECTED,
      RXCHARISK0(0) => gt_rx_data_k_reg(6),
      RXRUNDISP0(1) => NLW_GTD_6_GT_i_RXRUNDISP0_1_UNCONNECTED,
      RXRUNDISP0(0) => NLW_GTD_6_GT_i_RXRUNDISP0_0_UNCONNECTED,
      RXCHARISCOMMA0(1) => NLW_GTD_6_GT_i_RXCHARISCOMMA0_1_UNCONNECTED,
      RXCHARISCOMMA0(0) => NLW_GTD_6_GT_i_RXCHARISCOMMA0_0_UNCONNECTED,
      RXDATA1(15) => NLW_GTD_6_GT_i_RXDATA1_15_UNCONNECTED,
      RXDATA1(14) => NLW_GTD_6_GT_i_RXDATA1_14_UNCONNECTED,
      RXDATA1(13) => NLW_GTD_6_GT_i_RXDATA1_13_UNCONNECTED,
      RXDATA1(12) => NLW_GTD_6_GT_i_RXDATA1_12_UNCONNECTED,
      RXDATA1(11) => NLW_GTD_6_GT_i_RXDATA1_11_UNCONNECTED,
      RXDATA1(10) => NLW_GTD_6_GT_i_RXDATA1_10_UNCONNECTED,
      RXDATA1(9) => NLW_GTD_6_GT_i_RXDATA1_9_UNCONNECTED,
      RXDATA1(8) => NLW_GTD_6_GT_i_RXDATA1_8_UNCONNECTED,
      RXDATA1(7) => gt_rx_data_reg(63),
      RXDATA1(6) => gt_rx_data_reg(62),
      RXDATA1(5) => gt_rx_data_reg(61),
      RXDATA1(4) => gt_rx_data_reg(60),
      RXDATA1(3) => gt_rx_data_reg(59),
      RXDATA1(2) => gt_rx_data_reg(58),
      RXDATA1(1) => gt_rx_data_reg(57),
      RXDATA1(0) => gt_rx_data_reg(56),
      RXNOTINTABLE1(1) => NLW_GTD_6_GT_i_RXNOTINTABLE1_1_UNCONNECTED,
      RXNOTINTABLE1(0) => NLW_GTD_6_GT_i_RXNOTINTABLE1_0_UNCONNECTED,
      RXDISPERR1(1) => NLW_GTD_6_GT_i_RXDISPERR1_1_UNCONNECTED,
      RXDISPERR1(0) => NLW_GTD_6_GT_i_RXDISPERR1_0_UNCONNECTED,
      RXCHARISK1(1) => NLW_GTD_6_GT_i_RXCHARISK1_1_UNCONNECTED,
      RXCHARISK1(0) => gt_rx_data_k_reg(7),
      RXRUNDISP1(1) => NLW_GTD_6_GT_i_RXRUNDISP1_1_UNCONNECTED,
      RXRUNDISP1(0) => NLW_GTD_6_GT_i_RXRUNDISP1_0_UNCONNECTED,
      RXCHARISCOMMA1(1) => NLW_GTD_6_GT_i_RXCHARISCOMMA1_1_UNCONNECTED,
      RXCHARISCOMMA1(0) => NLW_GTD_6_GT_i_RXCHARISCOMMA1_0_UNCONNECTED,
      TXPOWERDOWN0(1) => gt_tx_power_down_reg(13),
      TXPOWERDOWN0(0) => gt_tx_power_down_reg(12),
      RXPOWERDOWN0(1) => gt_rx_power_down_reg(13),
      RXPOWERDOWN0(0) => gt_rx_power_down_reg(12),
      TXPOWERDOWN1(1) => gt_tx_power_down_reg(15),
      TXPOWERDOWN1(0) => gt_tx_power_down_reg(14),
      RXPOWERDOWN1(1) => gt_rx_power_down_reg(15),
      RXPOWERDOWN1(0) => gt_rx_power_down_reg(14),
      LOOPBACK0(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK0(0) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(2) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(1) => NlwRenamedSig_OI_gt_do(16),
      LOOPBACK1(0) => NlwRenamedSig_OI_gt_do(16),
      TXDIFFCTRL0(2) => gt_txdiffctrl_0(2),
      TXDIFFCTRL0(1) => gt_txdiffctrl_0(1),
      TXDIFFCTRL0(0) => gt_txdiffctrl_0(0),
      TXBUFDIFFCTRL0(2) => gt_txbuffctrl_0(2),
      TXBUFDIFFCTRL0(1) => gt_txbuffctrl_0(1),
      TXBUFDIFFCTRL0(0) => gt_txbuffctrl_0(0),
      TXPREEMPHASIS0(2) => gt_txpreemphesis_0(2),
      TXPREEMPHASIS0(1) => gt_txpreemphesis_0(1),
      TXPREEMPHASIS0(0) => gt_txpreemphesis_0(0),
      TXDIFFCTRL1(2) => gt_txdiffctrl_1(2),
      TXDIFFCTRL1(1) => gt_txdiffctrl_1(1),
      TXDIFFCTRL1(0) => gt_txdiffctrl_1(0),
      TXBUFDIFFCTRL1(2) => gt_txbuffctrl_1(2),
      TXBUFDIFFCTRL1(1) => gt_txbuffctrl_1(1),
      TXBUFDIFFCTRL1(0) => gt_txbuffctrl_1(0),
      TXPREEMPHASIS1(2) => gt_txpreemphesis_1(2),
      TXPREEMPHASIS1(1) => gt_txpreemphesis_1(1),
      TXPREEMPHASIS1(0) => gt_txpreemphesis_1(0),
      RXEQMIX0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX0(0) => N1,
      RXEQPOLE0(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE0(0) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQMIX1(0) => N1,
      RXEQPOLE1(3) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(2) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(1) => NlwRenamedSig_OI_gt_do(16),
      RXEQPOLE1(0) => NlwRenamedSig_OI_gt_do(16),
      TXKERR0(1) => NLW_GTD_6_GT_i_TXKERR0_1_UNCONNECTED,
      TXKERR0(0) => NLW_GTD_6_GT_i_TXKERR0_0_UNCONNECTED,
      TXRUNDISP0(1) => NLW_GTD_6_GT_i_TXRUNDISP0_1_UNCONNECTED,
      TXRUNDISP0(0) => NLW_GTD_6_GT_i_TXRUNDISP0_0_UNCONNECTED,
      TXBUFSTATUS0(1) => NLW_GTD_6_GT_i_TXBUFSTATUS0_1_UNCONNECTED,
      TXBUFSTATUS0(0) => NLW_GTD_6_GT_i_TXBUFSTATUS0_0_UNCONNECTED,
      TXKERR1(1) => NLW_GTD_6_GT_i_TXKERR1_1_UNCONNECTED,
      TXKERR1(0) => NLW_GTD_6_GT_i_TXKERR1_0_UNCONNECTED,
      TXRUNDISP1(1) => NLW_GTD_6_GT_i_TXRUNDISP1_1_UNCONNECTED,
      TXRUNDISP1(0) => NLW_GTD_6_GT_i_TXRUNDISP1_0_UNCONNECTED,
      TXBUFSTATUS1(1) => NLW_GTD_6_GT_i_TXBUFSTATUS1_1_UNCONNECTED,
      TXBUFSTATUS1(0) => NLW_GTD_6_GT_i_TXBUFSTATUS1_0_UNCONNECTED,
      RXLOSSOFSYNC0(1) => NLW_GTD_6_GT_i_RXLOSSOFSYNC0_1_UNCONNECTED,
      RXLOSSOFSYNC0(0) => NLW_GTD_6_GT_i_RXLOSSOFSYNC0_0_UNCONNECTED,
      RXCHBONDI0(2) => gt_rx_chbond_o(5, 2),
      RXCHBONDI0(1) => gt_rx_chbond_o(5, 1),
      RXCHBONDI0(0) => gt_rx_chbond_o(5, 0),
      RXCHBONDO0(2) => gt_rx_chbond_o(6, 2),
      RXCHBONDO0(1) => gt_rx_chbond_o(6, 1),
      RXCHBONDO0(0) => gt_rx_chbond_o(6, 0),
      RXBUFSTATUS0(2) => NLW_GTD_6_GT_i_RXBUFSTATUS0_2_UNCONNECTED,
      RXBUFSTATUS0(1) => NLW_GTD_6_GT_i_RXBUFSTATUS0_1_UNCONNECTED,
      RXBUFSTATUS0(0) => NLW_GTD_6_GT_i_RXBUFSTATUS0_0_UNCONNECTED,
      RXLOSSOFSYNC1(1) => NLW_GTD_6_GT_i_RXLOSSOFSYNC1_1_UNCONNECTED,
      RXLOSSOFSYNC1(0) => NLW_GTD_6_GT_i_RXLOSSOFSYNC1_0_UNCONNECTED,
      RXCHBONDI1(2) => gt_rx_chbond_o(6, 2),
      RXCHBONDI1(1) => gt_rx_chbond_o(6, 1),
      RXCHBONDI1(0) => gt_rx_chbond_o(6, 0),
      RXCHBONDO1(2) => NLW_GTD_6_GT_i_RXCHBONDO1_2_UNCONNECTED,
      RXCHBONDO1(1) => NLW_GTD_6_GT_i_RXCHBONDO1_1_UNCONNECTED,
      RXCHBONDO1(0) => NLW_GTD_6_GT_i_RXCHBONDO1_0_UNCONNECTED,
      RXBUFSTATUS1(2) => NLW_GTD_6_GT_i_RXBUFSTATUS1_2_UNCONNECTED,
      RXBUFSTATUS1(1) => NLW_GTD_6_GT_i_RXBUFSTATUS1_1_UNCONNECTED,
      RXBUFSTATUS1(0) => NLW_GTD_6_GT_i_RXBUFSTATUS1_0_UNCONNECTED,
      RXSTATUS0(2) => gt_rx_status_reg(20),
      RXSTATUS0(1) => gt_rx_status_reg(19),
      RXSTATUS0(0) => gt_rx_status_reg(18),
      RXCLKCORCNT0(2) => NLW_GTD_6_GT_i_RXCLKCORCNT0_2_UNCONNECTED,
      RXCLKCORCNT0(1) => NLW_GTD_6_GT_i_RXCLKCORCNT0_1_UNCONNECTED,
      RXCLKCORCNT0(0) => NLW_GTD_6_GT_i_RXCLKCORCNT0_0_UNCONNECTED,
      RXSTATUS1(2) => gt_rx_status_reg(23),
      RXSTATUS1(1) => gt_rx_status_reg(22),
      RXSTATUS1(0) => gt_rx_status_reg(21),
      RXCLKCORCNT1(2) => NLW_GTD_6_GT_i_RXCLKCORCNT1_2_UNCONNECTED,
      RXCLKCORCNT1(1) => NLW_GTD_6_GT_i_RXCLKCORCNT1_1_UNCONNECTED,
      RXCLKCORCNT1(0) => NLW_GTD_6_GT_i_RXCLKCORCNT1_0_UNCONNECTED,
      TXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST0(0) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      TXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(1) => NlwRenamedSig_OI_gt_do(16),
      RXENPRBSTST1(0) => NlwRenamedSig_OI_gt_do(16),
      DADDR(6) => gt_daddr(48),
      DADDR(5) => gt_daddr(47),
      DADDR(4) => gt_daddr(46),
      DADDR(3) => gt_daddr(45),
      DADDR(2) => gt_daddr(44),
      DADDR(1) => gt_daddr(43),
      DADDR(0) => gt_daddr(42),
      DI(15) => gt_di(111),
      DI(14) => gt_di(110),
      DI(13) => gt_di(109),
      DI(12) => gt_di(108),
      DI(11) => gt_di(107),
      DI(10) => gt_di(106),
      DI(9) => gt_di(105),
      DI(8) => gt_di(104),
      DI(7) => gt_di(103),
      DI(6) => gt_di(102),
      DI(5) => gt_di(101),
      DI(4) => gt_di(100),
      DI(3) => gt_di(99),
      DI(2) => gt_di(98),
      DI(1) => gt_di(97),
      DI(0) => gt_di(96),
      DO(15) => gt_do(111),
      DO(14) => gt_do(110),
      DO(13) => gt_do(109),
      DO(12) => gt_do(108),
      DO(11) => gt_do(107),
      DO(10) => gt_do(106),
      DO(9) => gt_do(105),
      DO(8) => gt_do(104),
      DO(7) => gt_do(103),
      DO(6) => gt_do(102),
      DO(5) => gt_do(101),
      DO(4) => gt_do(100),
      DO(3) => gt_do(99),
      DO(2) => gt_do(98),
      DO(1) => gt_do(97),
      DO(0) => gt_do(96),
      GTPTEST(3) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(2) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(1) => NlwRenamedSig_OI_gt_do(16),
      GTPTEST(0) => NlwRenamedSig_OI_gt_do(16)
    );
  cdrreset_7 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(7),
      PRE => cdrreset_7_and0000,
      Q => cdrreset(7)
    );
  cdrreset_6 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(6),
      PRE => cdrreset_6_and0000,
      Q => cdrreset(6)
    );
  cdrreset_5 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(5),
      PRE => cdrreset_5_and0000,
      Q => cdrreset(5)
    );
  cdrreset_4 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(4),
      PRE => cdrreset_4_and0000,
      Q => cdrreset(4)
    );
  cdrreset_3 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(3),
      PRE => cdrreset_3_and0000,
      Q => cdrreset(3)
    );
  cdrreset_2 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(2),
      PRE => cdrreset_2_and0000,
      Q => cdrreset(2)
    );
  cdrreset_1 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(1),
      PRE => cdrreset_1_and0000,
      Q => cdrreset(1)
    );
  cdrreset_0 : LDP_1
    generic map(
      INIT => '0'
    )
    port map (
      D => NlwRenamedSig_OI_gt_do(16),
      G => icdrreset(0),
      PRE => cdrreset_0_and0000,
      Q => cdrreset(0)
    );
  tile0_txsync_i : TX_SYNC_GTP
    port map (
      RESET => tx_sync_reset,
      USER_CLK => gt_usrclk,
      TXENPMAPHASEALIGN => TXENPMAPHASEALIGN,
      SYNC_DONE => sync_done,
      TXPMASETPHASE => TXPMASETPHASE
    );
  icdrreset_7_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(7),
      I1 => gt_rx_elec_idle_reg(7),
      O => icdrreset(7)
    );
  icdrreset_6_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(6),
      I1 => gt_rx_elec_idle_reg(6),
      O => icdrreset(6)
    );
  icdrreset_5_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(5),
      I1 => gt_rx_elec_idle_reg(5),
      O => icdrreset(5)
    );
  icdrreset_4_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(4),
      I1 => gt_rx_elec_idle_reg(4),
      O => icdrreset(4)
    );
  icdrreset_3_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(3),
      I1 => gt_rx_elec_idle_reg(3),
      O => icdrreset(3)
    );
  icdrreset_2_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(2),
      I1 => gt_rx_elec_idle_reg(2),
      O => icdrreset(2)
    );
  icdrreset_1_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(1),
      I1 => gt_rx_elec_idle_reg(1),
      O => icdrreset(1)
    );
  icdrreset_0_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_resetdone(0),
      I1 => gt_rx_elec_idle_reg(0),
      O => icdrreset(0)
    );
  gt_rx_en_elec_idle_resetb_3_not00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => cdrreset(6),
      I1 => cdrreset(7),
      O => gt_rx_en_elec_idle_resetb(3)
    );
  gt_rx_en_elec_idle_resetb_2_not00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => cdrreset(4),
      I1 => cdrreset(5),
      O => gt_rx_en_elec_idle_resetb(2)
    );
  gt_rx_en_elec_idle_resetb_1_not00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => cdrreset(2),
      I1 => cdrreset(3),
      O => gt_rx_en_elec_idle_resetb(1)
    );
  gt_rx_en_elec_idle_resetb_0_not00001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => cdrreset(0),
      I1 => cdrreset(1),
      O => gt_rx_en_elec_idle_resetb(0)
    );
  Q_and00091 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(7),
      O => Q_and0009
    );
  Q_and00081 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(6),
      O => Q_and0008
    );
  Q_and00071 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(5),
      O => Q_and0007
    );
  Q_and00061 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(4),
      O => Q_and0006
    );
  Q_and00051 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(3),
      O => Q_and0005
    );
  Q_and00041 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(2),
      O => Q_and0004
    );
  Q_and00031 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => mgt_txreset_16240,
      O => Q_and0003
    );
  Q_and00021 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => rxreset_16276,
      O => Q_and0002
    );
  Q_and00011 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(1),
      O => Q_and0001
    );
  Q_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_rst_pcie,
      I1 => gt_pipe_reset_reg(0),
      O => Q_and0000
    );
  cdrreset_7_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(7),
      I1 => NlwRenamedSig_OI_resetdone(7),
      I2 => gt_rx_valid_reg(7),
      O => cdrreset_7_and0000
    );
  cdrreset_6_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(6),
      I1 => NlwRenamedSig_OI_resetdone(6),
      I2 => gt_rx_valid_reg(6),
      O => cdrreset_6_and0000
    );
  cdrreset_5_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(5),
      I1 => NlwRenamedSig_OI_resetdone(5),
      I2 => gt_rx_valid_reg(5),
      O => cdrreset_5_and0000
    );
  cdrreset_4_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(4),
      I1 => NlwRenamedSig_OI_resetdone(4),
      I2 => gt_rx_valid_reg(4),
      O => cdrreset_4_and0000
    );
  cdrreset_3_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(3),
      I1 => NlwRenamedSig_OI_resetdone(3),
      I2 => gt_rx_valid_reg(3),
      O => cdrreset_3_and0000
    );
  cdrreset_2_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(2),
      I1 => NlwRenamedSig_OI_resetdone(2),
      I2 => gt_rx_valid_reg(2),
      O => cdrreset_2_and0000
    );
  cdrreset_1_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(1),
      I1 => NlwRenamedSig_OI_resetdone(1),
      I2 => gt_rx_valid_reg(1),
      O => cdrreset_1_and0000
    );
  cdrreset_0_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => gt_rx_elec_idle_reg(0),
      I1 => NlwRenamedSig_OI_resetdone(0),
      I2 => gt_rx_valid_reg(0),
      O => cdrreset_0_and0000
    );
  rxreset_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => m2_delayed_elec_idle_reset_16239,
      I1 => delayed_elec_idle_reset_15450,
      O => rxreset_and0000
    );
  Mcount_mgt_txreset_cnt_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => mgt_txreset_cnt(1),
      I1 => mgt_txreset_cnt(0),
      O => Result(1)
    );
  mgt_txreset_cnt_cmp_lt00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => mgt_txreset_cnt(0),
      I1 => mgt_txreset_cnt(1),
      O => mgt_txreset_cnt_cmp_lt0000
    );
  mgt_txreset_or00001 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => sync_done,
      I1 => mgt_txreset_cnt(1),
      I2 => mgt_txreset_cnt(0),
      O => mgt_txreset_or0000
    );
  tx_sync_reset1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => clock_lock,
      I1 => NlwRenamedSig_OI_rst_pcie,
      O => tx_sync_reset
    );
  flop_0_tx_elec_idle_not00001_INV_0 : INV
    port map (
      I => clock_lock,
      O => flop_0_tx_elec_idle_not0000
    );
  Mcount_mgt_txreset_cnt_xor_0_11_INV_0 : INV
    port map (
      I => mgt_txreset_cnt(0),
      O => Result(0)
    );
  sync_done_inv1_INV_0 : INV
    port map (
      I => sync_done,
      O => sync_done_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_gt_wrapper_top is
  port (
    gtclk_bufg : out STD_LOGIC; 
    txsync_clk : in STD_LOGIC := 'X'; 
    gt_usrclk : in STD_LOGIC := 'X'; 
    refclkout_bufg : out STD_LOGIC; 
    gtreset : in STD_LOGIC := 'X'; 
    pcie_reset : out STD_LOGIC; 
    refclk : in STD_LOGIC := 'X'; 
    clock_lock : in STD_LOGIC := 'X'; 
    gt_usrclk2 : in STD_LOGIC := 'X'; 
    gt_dclk : in STD_LOGIC := 'X'; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    gt_rx_chanisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_elec_idle : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxchanbondseq : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    resetdone : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_valid : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_data_k : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxbyteisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_tx_p : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_status : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
    plllkdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
    gt_rx_phy_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_elec_idle : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_rx_p : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_deskew_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
    gt_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_tx_compliance : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_pipe_reset : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_tx_detect_rx_loopback : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
    gt_power_down : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    gt_rx_polarity : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end pcie_gt_wrapper_top;

architecture STRUCTURE of pcie_gt_wrapper_top is
  component pcie_gt_wrapper
    port (
      gtclk_bufg : out STD_LOGIC; 
      gt_usrclk : in STD_LOGIC := 'X'; 
      refclkout_bufg : out STD_LOGIC; 
      gtreset : in STD_LOGIC := 'X'; 
      pcie_reset : out STD_LOGIC; 
      refclk : in STD_LOGIC := 'X'; 
      clock_lock : in STD_LOGIC := 'X'; 
      gt_dclk : in STD_LOGIC := 'X'; 
      gt_rx_chanisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_elec_idle : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxchanbondseq : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      resetdone : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_valid : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_data_k : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxbyteisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_tx_p : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_status : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
      plllkdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
      gt_rx_phy_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_elec_idle : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_p : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_deskew_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
      gt_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_tx_compliance : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_pipe_reset : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_detect_rx_loopback : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
      gt_power_down : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      gt_rx_polarity : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  Q_pcie_gt_wrapper_i : pcie_gt_wrapper
    port map (
      gtclk_bufg => gtclk_bufg,
      gt_usrclk => gt_usrclk2,
      refclkout_bufg => refclkout_bufg,
      gtreset => gtreset,
      pcie_reset => pcie_reset,
      refclk => refclk,
      clock_lock => clock_lock,
      gt_dclk => N0,
      gt_rx_chanisaligned(7) => gt_rx_chanisaligned(7),
      gt_rx_chanisaligned(6) => gt_rx_chanisaligned(6),
      gt_rx_chanisaligned(5) => gt_rx_chanisaligned(5),
      gt_rx_chanisaligned(4) => gt_rx_chanisaligned(4),
      gt_rx_chanisaligned(3) => gt_rx_chanisaligned(3),
      gt_rx_chanisaligned(2) => gt_rx_chanisaligned(2),
      gt_rx_chanisaligned(1) => gt_rx_chanisaligned(1),
      gt_rx_chanisaligned(0) => gt_rx_chanisaligned(0),
      gt_rx_elec_idle(7) => gt_rx_elec_idle(7),
      gt_rx_elec_idle(6) => gt_rx_elec_idle(6),
      gt_rx_elec_idle(5) => gt_rx_elec_idle(5),
      gt_rx_elec_idle(4) => gt_rx_elec_idle(4),
      gt_rx_elec_idle(3) => gt_rx_elec_idle(3),
      gt_rx_elec_idle(2) => gt_rx_elec_idle(2),
      gt_rx_elec_idle(1) => gt_rx_elec_idle(1),
      gt_rx_elec_idle(0) => gt_rx_elec_idle(0),
      rxchanbondseq(7) => rxchanbondseq(7),
      rxchanbondseq(6) => rxchanbondseq(6),
      rxchanbondseq(5) => rxchanbondseq(5),
      rxchanbondseq(4) => rxchanbondseq(4),
      rxchanbondseq(3) => rxchanbondseq(3),
      rxchanbondseq(2) => rxchanbondseq(2),
      rxchanbondseq(1) => rxchanbondseq(1),
      rxchanbondseq(0) => rxchanbondseq(0),
      resetdone(7) => resetdone(7),
      resetdone(6) => resetdone(6),
      resetdone(5) => resetdone(5),
      resetdone(4) => resetdone(4),
      resetdone(3) => resetdone(3),
      resetdone(2) => resetdone(2),
      resetdone(1) => resetdone(1),
      resetdone(0) => resetdone(0),
      gt_rx_valid(7) => gt_rx_valid(7),
      gt_rx_valid(6) => gt_rx_valid(6),
      gt_rx_valid(5) => gt_rx_valid(5),
      gt_rx_valid(4) => gt_rx_valid(4),
      gt_rx_valid(3) => gt_rx_valid(3),
      gt_rx_valid(2) => gt_rx_valid(2),
      gt_rx_valid(1) => gt_rx_valid(1),
      gt_rx_valid(0) => gt_rx_valid(0),
      gt_rx_data_k(7) => gt_rx_data_k(7),
      gt_rx_data_k(6) => gt_rx_data_k(6),
      gt_rx_data_k(5) => gt_rx_data_k(5),
      gt_rx_data_k(4) => gt_rx_data_k(4),
      gt_rx_data_k(3) => gt_rx_data_k(3),
      gt_rx_data_k(2) => gt_rx_data_k(2),
      gt_rx_data_k(1) => gt_rx_data_k(1),
      gt_rx_data_k(0) => gt_rx_data_k(0),
      rxbyteisaligned(7) => rxbyteisaligned(7),
      rxbyteisaligned(6) => rxbyteisaligned(6),
      rxbyteisaligned(5) => rxbyteisaligned(5),
      rxbyteisaligned(4) => rxbyteisaligned(4),
      rxbyteisaligned(3) => rxbyteisaligned(3),
      rxbyteisaligned(2) => rxbyteisaligned(2),
      rxbyteisaligned(1) => rxbyteisaligned(1),
      rxbyteisaligned(0) => rxbyteisaligned(0),
      gt_tx_n(7) => gt_tx_n(7),
      gt_tx_n(6) => gt_tx_n(6),
      gt_tx_n(5) => gt_tx_n(5),
      gt_tx_n(4) => gt_tx_n(4),
      gt_tx_n(3) => gt_tx_n(3),
      gt_tx_n(2) => gt_tx_n(2),
      gt_tx_n(1) => gt_tx_n(1),
      gt_tx_n(0) => gt_tx_n(0),
      gt_rx_data(63) => gt_rx_data(63),
      gt_rx_data(62) => gt_rx_data(62),
      gt_rx_data(61) => gt_rx_data(61),
      gt_rx_data(60) => gt_rx_data(60),
      gt_rx_data(59) => gt_rx_data(59),
      gt_rx_data(58) => gt_rx_data(58),
      gt_rx_data(57) => gt_rx_data(57),
      gt_rx_data(56) => gt_rx_data(56),
      gt_rx_data(55) => gt_rx_data(55),
      gt_rx_data(54) => gt_rx_data(54),
      gt_rx_data(53) => gt_rx_data(53),
      gt_rx_data(52) => gt_rx_data(52),
      gt_rx_data(51) => gt_rx_data(51),
      gt_rx_data(50) => gt_rx_data(50),
      gt_rx_data(49) => gt_rx_data(49),
      gt_rx_data(48) => gt_rx_data(48),
      gt_rx_data(47) => gt_rx_data(47),
      gt_rx_data(46) => gt_rx_data(46),
      gt_rx_data(45) => gt_rx_data(45),
      gt_rx_data(44) => gt_rx_data(44),
      gt_rx_data(43) => gt_rx_data(43),
      gt_rx_data(42) => gt_rx_data(42),
      gt_rx_data(41) => gt_rx_data(41),
      gt_rx_data(40) => gt_rx_data(40),
      gt_rx_data(39) => gt_rx_data(39),
      gt_rx_data(38) => gt_rx_data(38),
      gt_rx_data(37) => gt_rx_data(37),
      gt_rx_data(36) => gt_rx_data(36),
      gt_rx_data(35) => gt_rx_data(35),
      gt_rx_data(34) => gt_rx_data(34),
      gt_rx_data(33) => gt_rx_data(33),
      gt_rx_data(32) => gt_rx_data(32),
      gt_rx_data(31) => gt_rx_data(31),
      gt_rx_data(30) => gt_rx_data(30),
      gt_rx_data(29) => gt_rx_data(29),
      gt_rx_data(28) => gt_rx_data(28),
      gt_rx_data(27) => gt_rx_data(27),
      gt_rx_data(26) => gt_rx_data(26),
      gt_rx_data(25) => gt_rx_data(25),
      gt_rx_data(24) => gt_rx_data(24),
      gt_rx_data(23) => gt_rx_data(23),
      gt_rx_data(22) => gt_rx_data(22),
      gt_rx_data(21) => gt_rx_data(21),
      gt_rx_data(20) => gt_rx_data(20),
      gt_rx_data(19) => gt_rx_data(19),
      gt_rx_data(18) => gt_rx_data(18),
      gt_rx_data(17) => gt_rx_data(17),
      gt_rx_data(16) => gt_rx_data(16),
      gt_rx_data(15) => gt_rx_data(15),
      gt_rx_data(14) => gt_rx_data(14),
      gt_rx_data(13) => gt_rx_data(13),
      gt_rx_data(12) => gt_rx_data(12),
      gt_rx_data(11) => gt_rx_data(11),
      gt_rx_data(10) => gt_rx_data(10),
      gt_rx_data(9) => gt_rx_data(9),
      gt_rx_data(8) => gt_rx_data(8),
      gt_rx_data(7) => gt_rx_data(7),
      gt_rx_data(6) => gt_rx_data(6),
      gt_rx_data(5) => gt_rx_data(5),
      gt_rx_data(4) => gt_rx_data(4),
      gt_rx_data(3) => gt_rx_data(3),
      gt_rx_data(2) => gt_rx_data(2),
      gt_rx_data(1) => gt_rx_data(1),
      gt_rx_data(0) => gt_rx_data(0),
      gt_tx_p(7) => gt_tx_p(7),
      gt_tx_p(6) => gt_tx_p(6),
      gt_tx_p(5) => gt_tx_p(5),
      gt_tx_p(4) => gt_tx_p(4),
      gt_tx_p(3) => gt_tx_p(3),
      gt_tx_p(2) => gt_tx_p(2),
      gt_tx_p(1) => gt_tx_p(1),
      gt_tx_p(0) => gt_tx_p(0),
      gt_rx_status(23) => gt_rx_status(23),
      gt_rx_status(22) => gt_rx_status(22),
      gt_rx_status(21) => gt_rx_status(21),
      gt_rx_status(20) => gt_rx_status(20),
      gt_rx_status(19) => gt_rx_status(19),
      gt_rx_status(18) => gt_rx_status(18),
      gt_rx_status(17) => gt_rx_status(17),
      gt_rx_status(16) => gt_rx_status(16),
      gt_rx_status(15) => gt_rx_status(15),
      gt_rx_status(14) => gt_rx_status(14),
      gt_rx_status(13) => gt_rx_status(13),
      gt_rx_status(12) => gt_rx_status(12),
      gt_rx_status(11) => gt_rx_status(11),
      gt_rx_status(10) => gt_rx_status(10),
      gt_rx_status(9) => gt_rx_status(9),
      gt_rx_status(8) => gt_rx_status(8),
      gt_rx_status(7) => gt_rx_status(7),
      gt_rx_status(6) => gt_rx_status(6),
      gt_rx_status(5) => gt_rx_status(5),
      gt_rx_status(4) => gt_rx_status(4),
      gt_rx_status(3) => gt_rx_status(3),
      gt_rx_status(2) => gt_rx_status(2),
      gt_rx_status(1) => gt_rx_status(1),
      gt_rx_status(0) => gt_rx_status(0),
      plllkdet_out(3) => plllkdet_out(3),
      plllkdet_out(2) => plllkdet_out(2),
      plllkdet_out(1) => plllkdet_out(1),
      plllkdet_out(0) => plllkdet_out(0),
      gt_drdy(7) => gt_drdy(7),
      gt_drdy(6) => gt_drdy(6),
      gt_drdy(5) => gt_drdy(5),
      gt_drdy(4) => gt_drdy(4),
      gt_drdy(3) => gt_drdy(3),
      gt_drdy(2) => gt_drdy(2),
      gt_drdy(1) => gt_drdy(1),
      gt_drdy(0) => gt_drdy(0),
      gt_do(127) => gt_do(127),
      gt_do(126) => gt_do(126),
      gt_do(125) => gt_do(125),
      gt_do(124) => gt_do(124),
      gt_do(123) => gt_do(123),
      gt_do(122) => gt_do(122),
      gt_do(121) => gt_do(121),
      gt_do(120) => gt_do(120),
      gt_do(119) => gt_do(119),
      gt_do(118) => gt_do(118),
      gt_do(117) => gt_do(117),
      gt_do(116) => gt_do(116),
      gt_do(115) => gt_do(115),
      gt_do(114) => gt_do(114),
      gt_do(113) => gt_do(113),
      gt_do(112) => gt_do(112),
      gt_do(111) => gt_do(111),
      gt_do(110) => gt_do(110),
      gt_do(109) => gt_do(109),
      gt_do(108) => gt_do(108),
      gt_do(107) => gt_do(107),
      gt_do(106) => gt_do(106),
      gt_do(105) => gt_do(105),
      gt_do(104) => gt_do(104),
      gt_do(103) => gt_do(103),
      gt_do(102) => gt_do(102),
      gt_do(101) => gt_do(101),
      gt_do(100) => gt_do(100),
      gt_do(99) => gt_do(99),
      gt_do(98) => gt_do(98),
      gt_do(97) => gt_do(97),
      gt_do(96) => gt_do(96),
      gt_do(95) => gt_do(95),
      gt_do(94) => gt_do(94),
      gt_do(93) => gt_do(93),
      gt_do(92) => gt_do(92),
      gt_do(91) => gt_do(91),
      gt_do(90) => gt_do(90),
      gt_do(89) => gt_do(89),
      gt_do(88) => gt_do(88),
      gt_do(87) => gt_do(87),
      gt_do(86) => gt_do(86),
      gt_do(85) => gt_do(85),
      gt_do(84) => gt_do(84),
      gt_do(83) => gt_do(83),
      gt_do(82) => gt_do(82),
      gt_do(81) => gt_do(81),
      gt_do(80) => gt_do(80),
      gt_do(79) => gt_do(79),
      gt_do(78) => gt_do(78),
      gt_do(77) => gt_do(77),
      gt_do(76) => gt_do(76),
      gt_do(75) => gt_do(75),
      gt_do(74) => gt_do(74),
      gt_do(73) => gt_do(73),
      gt_do(72) => gt_do(72),
      gt_do(71) => gt_do(71),
      gt_do(70) => gt_do(70),
      gt_do(69) => gt_do(69),
      gt_do(68) => gt_do(68),
      gt_do(67) => gt_do(67),
      gt_do(66) => gt_do(66),
      gt_do(65) => gt_do(65),
      gt_do(64) => gt_do(64),
      gt_do(63) => gt_do(63),
      gt_do(62) => gt_do(62),
      gt_do(61) => gt_do(61),
      gt_do(60) => gt_do(60),
      gt_do(59) => gt_do(59),
      gt_do(58) => gt_do(58),
      gt_do(57) => gt_do(57),
      gt_do(56) => gt_do(56),
      gt_do(55) => gt_do(55),
      gt_do(54) => gt_do(54),
      gt_do(53) => gt_do(53),
      gt_do(52) => gt_do(52),
      gt_do(51) => gt_do(51),
      gt_do(50) => gt_do(50),
      gt_do(49) => gt_do(49),
      gt_do(48) => gt_do(48),
      gt_do(47) => gt_do(47),
      gt_do(46) => gt_do(46),
      gt_do(45) => gt_do(45),
      gt_do(44) => gt_do(44),
      gt_do(43) => gt_do(43),
      gt_do(42) => gt_do(42),
      gt_do(41) => gt_do(41),
      gt_do(40) => gt_do(40),
      gt_do(39) => gt_do(39),
      gt_do(38) => gt_do(38),
      gt_do(37) => gt_do(37),
      gt_do(36) => gt_do(36),
      gt_do(35) => gt_do(35),
      gt_do(34) => gt_do(34),
      gt_do(33) => gt_do(33),
      gt_do(32) => gt_do(32),
      gt_do(31) => gt_do(31),
      gt_do(30) => gt_do(30),
      gt_do(29) => gt_do(29),
      gt_do(28) => gt_do(28),
      gt_do(27) => gt_do(27),
      gt_do(26) => gt_do(26),
      gt_do(25) => gt_do(25),
      gt_do(24) => gt_do(24),
      gt_do(23) => gt_do(23),
      gt_do(22) => gt_do(22),
      gt_do(21) => gt_do(21),
      gt_do(20) => gt_do(20),
      gt_do(19) => gt_do(19),
      gt_do(18) => gt_do(18),
      gt_do(17) => gt_do(17),
      gt_do(16) => gt_do(16),
      gt_do(15) => gt_do(15),
      gt_do(14) => gt_do(14),
      gt_do(13) => gt_do(13),
      gt_do(12) => gt_do(12),
      gt_do(11) => gt_do(11),
      gt_do(10) => gt_do(10),
      gt_do(9) => gt_do(9),
      gt_do(8) => gt_do(8),
      gt_do(7) => gt_do(7),
      gt_do(6) => gt_do(6),
      gt_do(5) => gt_do(5),
      gt_do(4) => gt_do(4),
      gt_do(3) => gt_do(3),
      gt_do(2) => gt_do(2),
      gt_do(1) => gt_do(1),
      gt_do(0) => gt_do(0),
      gt_rx_phy_status(7) => gt_rx_phy_status(7),
      gt_rx_phy_status(6) => gt_rx_phy_status(6),
      gt_rx_phy_status(5) => gt_rx_phy_status(5),
      gt_rx_phy_status(4) => gt_rx_phy_status(4),
      gt_rx_phy_status(3) => gt_rx_phy_status(3),
      gt_rx_phy_status(2) => gt_rx_phy_status(2),
      gt_rx_phy_status(1) => gt_rx_phy_status(1),
      gt_rx_phy_status(0) => gt_rx_phy_status(0),
      gt_tx_elec_idle(7) => gt_tx_elec_idle(7),
      gt_tx_elec_idle(6) => gt_tx_elec_idle(6),
      gt_tx_elec_idle(5) => gt_tx_elec_idle(5),
      gt_tx_elec_idle(4) => gt_tx_elec_idle(4),
      gt_tx_elec_idle(3) => gt_tx_elec_idle(3),
      gt_tx_elec_idle(2) => gt_tx_elec_idle(2),
      gt_tx_elec_idle(1) => gt_tx_elec_idle(1),
      gt_tx_elec_idle(0) => gt_tx_elec_idle(0),
      gt_rx_present(7) => N1,
      gt_rx_present(6) => N1,
      gt_rx_present(5) => N1,
      gt_rx_present(4) => N1,
      gt_rx_present(3) => N1,
      gt_rx_present(2) => N1,
      gt_rx_present(1) => N1,
      gt_rx_present(0) => N1,
      gt_tx_data_k(7) => gt_tx_data_k(7),
      gt_tx_data_k(6) => gt_tx_data_k(6),
      gt_tx_data_k(5) => gt_tx_data_k(5),
      gt_tx_data_k(4) => gt_tx_data_k(4),
      gt_tx_data_k(3) => gt_tx_data_k(3),
      gt_tx_data_k(2) => gt_tx_data_k(2),
      gt_tx_data_k(1) => gt_tx_data_k(1),
      gt_tx_data_k(0) => gt_tx_data_k(0),
      gt_den(7) => N0,
      gt_den(6) => N0,
      gt_den(5) => N0,
      gt_den(4) => N0,
      gt_den(3) => N0,
      gt_den(2) => N0,
      gt_den(1) => N0,
      gt_den(0) => N0,
      gt_rx_n(7) => gt_rx_n(7),
      gt_rx_n(6) => gt_rx_n(6),
      gt_rx_n(5) => gt_rx_n(5),
      gt_rx_n(4) => gt_rx_n(4),
      gt_rx_n(3) => gt_rx_n(3),
      gt_rx_n(2) => gt_rx_n(2),
      gt_rx_n(1) => gt_rx_n(1),
      gt_rx_n(0) => gt_rx_n(0),
      gt_rx_p(7) => gt_rx_p(7),
      gt_rx_p(6) => gt_rx_p(6),
      gt_rx_p(5) => gt_rx_p(5),
      gt_rx_p(4) => gt_rx_p(4),
      gt_rx_p(3) => gt_rx_p(3),
      gt_rx_p(2) => gt_rx_p(2),
      gt_rx_p(1) => gt_rx_p(1),
      gt_rx_p(0) => gt_rx_p(0),
      gt_deskew_lanes(7) => gt_deskew_lanes(7),
      gt_deskew_lanes(6) => gt_deskew_lanes(6),
      gt_deskew_lanes(5) => gt_deskew_lanes(5),
      gt_deskew_lanes(4) => gt_deskew_lanes(4),
      gt_deskew_lanes(3) => gt_deskew_lanes(3),
      gt_deskew_lanes(2) => gt_deskew_lanes(2),
      gt_deskew_lanes(1) => gt_deskew_lanes(1),
      gt_deskew_lanes(0) => gt_deskew_lanes(0),
      gt_dwen(7) => N0,
      gt_dwen(6) => N0,
      gt_dwen(5) => N0,
      gt_dwen(4) => N0,
      gt_dwen(3) => N0,
      gt_dwen(2) => N0,
      gt_dwen(1) => N0,
      gt_dwen(0) => N0,
      gt_daddr(55) => gt_daddr(55),
      gt_daddr(54) => gt_daddr(54),
      gt_daddr(53) => gt_daddr(53),
      gt_daddr(52) => gt_daddr(52),
      gt_daddr(51) => gt_daddr(51),
      gt_daddr(50) => gt_daddr(50),
      gt_daddr(49) => gt_daddr(49),
      gt_daddr(48) => gt_daddr(48),
      gt_daddr(47) => gt_daddr(47),
      gt_daddr(46) => gt_daddr(46),
      gt_daddr(45) => gt_daddr(45),
      gt_daddr(44) => gt_daddr(44),
      gt_daddr(43) => gt_daddr(43),
      gt_daddr(42) => gt_daddr(42),
      gt_daddr(41) => gt_daddr(41),
      gt_daddr(40) => gt_daddr(40),
      gt_daddr(39) => gt_daddr(39),
      gt_daddr(38) => gt_daddr(38),
      gt_daddr(37) => gt_daddr(37),
      gt_daddr(36) => gt_daddr(36),
      gt_daddr(35) => gt_daddr(35),
      gt_daddr(34) => gt_daddr(34),
      gt_daddr(33) => gt_daddr(33),
      gt_daddr(32) => gt_daddr(32),
      gt_daddr(31) => gt_daddr(31),
      gt_daddr(30) => gt_daddr(30),
      gt_daddr(29) => gt_daddr(29),
      gt_daddr(28) => gt_daddr(28),
      gt_daddr(27) => gt_daddr(27),
      gt_daddr(26) => gt_daddr(26),
      gt_daddr(25) => gt_daddr(25),
      gt_daddr(24) => gt_daddr(24),
      gt_daddr(23) => gt_daddr(23),
      gt_daddr(22) => gt_daddr(22),
      gt_daddr(21) => gt_daddr(21),
      gt_daddr(20) => gt_daddr(20),
      gt_daddr(19) => gt_daddr(19),
      gt_daddr(18) => gt_daddr(18),
      gt_daddr(17) => gt_daddr(17),
      gt_daddr(16) => gt_daddr(16),
      gt_daddr(15) => gt_daddr(15),
      gt_daddr(14) => gt_daddr(14),
      gt_daddr(13) => gt_daddr(13),
      gt_daddr(12) => gt_daddr(12),
      gt_daddr(11) => gt_daddr(11),
      gt_daddr(10) => gt_daddr(10),
      gt_daddr(9) => gt_daddr(9),
      gt_daddr(8) => gt_daddr(8),
      gt_daddr(7) => gt_daddr(7),
      gt_daddr(6) => gt_daddr(6),
      gt_daddr(5) => gt_daddr(5),
      gt_daddr(4) => gt_daddr(4),
      gt_daddr(3) => gt_daddr(3),
      gt_daddr(2) => gt_daddr(2),
      gt_daddr(1) => gt_daddr(1),
      gt_daddr(0) => gt_daddr(0),
      gt_tx_data(63) => gt_tx_data(63),
      gt_tx_data(62) => gt_tx_data(62),
      gt_tx_data(61) => gt_tx_data(61),
      gt_tx_data(60) => gt_tx_data(60),
      gt_tx_data(59) => gt_tx_data(59),
      gt_tx_data(58) => gt_tx_data(58),
      gt_tx_data(57) => gt_tx_data(57),
      gt_tx_data(56) => gt_tx_data(56),
      gt_tx_data(55) => gt_tx_data(55),
      gt_tx_data(54) => gt_tx_data(54),
      gt_tx_data(53) => gt_tx_data(53),
      gt_tx_data(52) => gt_tx_data(52),
      gt_tx_data(51) => gt_tx_data(51),
      gt_tx_data(50) => gt_tx_data(50),
      gt_tx_data(49) => gt_tx_data(49),
      gt_tx_data(48) => gt_tx_data(48),
      gt_tx_data(47) => gt_tx_data(47),
      gt_tx_data(46) => gt_tx_data(46),
      gt_tx_data(45) => gt_tx_data(45),
      gt_tx_data(44) => gt_tx_data(44),
      gt_tx_data(43) => gt_tx_data(43),
      gt_tx_data(42) => gt_tx_data(42),
      gt_tx_data(41) => gt_tx_data(41),
      gt_tx_data(40) => gt_tx_data(40),
      gt_tx_data(39) => gt_tx_data(39),
      gt_tx_data(38) => gt_tx_data(38),
      gt_tx_data(37) => gt_tx_data(37),
      gt_tx_data(36) => gt_tx_data(36),
      gt_tx_data(35) => gt_tx_data(35),
      gt_tx_data(34) => gt_tx_data(34),
      gt_tx_data(33) => gt_tx_data(33),
      gt_tx_data(32) => gt_tx_data(32),
      gt_tx_data(31) => gt_tx_data(31),
      gt_tx_data(30) => gt_tx_data(30),
      gt_tx_data(29) => gt_tx_data(29),
      gt_tx_data(28) => gt_tx_data(28),
      gt_tx_data(27) => gt_tx_data(27),
      gt_tx_data(26) => gt_tx_data(26),
      gt_tx_data(25) => gt_tx_data(25),
      gt_tx_data(24) => gt_tx_data(24),
      gt_tx_data(23) => gt_tx_data(23),
      gt_tx_data(22) => gt_tx_data(22),
      gt_tx_data(21) => gt_tx_data(21),
      gt_tx_data(20) => gt_tx_data(20),
      gt_tx_data(19) => gt_tx_data(19),
      gt_tx_data(18) => gt_tx_data(18),
      gt_tx_data(17) => gt_tx_data(17),
      gt_tx_data(16) => gt_tx_data(16),
      gt_tx_data(15) => gt_tx_data(15),
      gt_tx_data(14) => gt_tx_data(14),
      gt_tx_data(13) => gt_tx_data(13),
      gt_tx_data(12) => gt_tx_data(12),
      gt_tx_data(11) => gt_tx_data(11),
      gt_tx_data(10) => gt_tx_data(10),
      gt_tx_data(9) => gt_tx_data(9),
      gt_tx_data(8) => gt_tx_data(8),
      gt_tx_data(7) => gt_tx_data(7),
      gt_tx_data(6) => gt_tx_data(6),
      gt_tx_data(5) => gt_tx_data(5),
      gt_tx_data(4) => gt_tx_data(4),
      gt_tx_data(3) => gt_tx_data(3),
      gt_tx_data(2) => gt_tx_data(2),
      gt_tx_data(1) => gt_tx_data(1),
      gt_tx_data(0) => gt_tx_data(0),
      gt_txbuffctrl_0(2) => N1,
      gt_txbuffctrl_0(1) => N0,
      gt_txbuffctrl_0(0) => N0,
      gt_txbuffctrl_1(2) => N1,
      gt_txbuffctrl_1(1) => N0,
      gt_txbuffctrl_1(0) => N0,
      gt_tx_compliance(7) => gt_tx_compliance(7),
      gt_tx_compliance(6) => gt_tx_compliance(6),
      gt_tx_compliance(5) => gt_tx_compliance(5),
      gt_tx_compliance(4) => gt_tx_compliance(4),
      gt_tx_compliance(3) => gt_tx_compliance(3),
      gt_tx_compliance(2) => gt_tx_compliance(2),
      gt_tx_compliance(1) => gt_tx_compliance(1),
      gt_tx_compliance(0) => gt_tx_compliance(0),
      gt_txdiffctrl_0(2) => N1,
      gt_txdiffctrl_0(1) => N0,
      gt_txdiffctrl_0(0) => N0,
      gt_txdiffctrl_1(2) => N1,
      gt_txdiffctrl_1(1) => N0,
      gt_txdiffctrl_1(0) => N0,
      gt_pipe_reset(7) => gt_pipe_reset(7),
      gt_pipe_reset(6) => gt_pipe_reset(6),
      gt_pipe_reset(5) => gt_pipe_reset(5),
      gt_pipe_reset(4) => gt_pipe_reset(4),
      gt_pipe_reset(3) => gt_pipe_reset(3),
      gt_pipe_reset(2) => gt_pipe_reset(2),
      gt_pipe_reset(1) => gt_pipe_reset(1),
      gt_pipe_reset(0) => gt_pipe_reset(0),
      gt_tx_detect_rx_loopback(7) => gt_tx_detect_rx_loopback(7),
      gt_tx_detect_rx_loopback(6) => gt_tx_detect_rx_loopback(6),
      gt_tx_detect_rx_loopback(5) => gt_tx_detect_rx_loopback(5),
      gt_tx_detect_rx_loopback(4) => gt_tx_detect_rx_loopback(4),
      gt_tx_detect_rx_loopback(3) => gt_tx_detect_rx_loopback(3),
      gt_tx_detect_rx_loopback(2) => gt_tx_detect_rx_loopback(2),
      gt_tx_detect_rx_loopback(1) => gt_tx_detect_rx_loopback(1),
      gt_tx_detect_rx_loopback(0) => gt_tx_detect_rx_loopback(0),
      gt_txpreemphesis_0(2) => N1,
      gt_txpreemphesis_0(1) => N1,
      gt_txpreemphesis_0(0) => N1,
      gt_txpreemphesis_1(2) => N1,
      gt_txpreemphesis_1(1) => N1,
      gt_txpreemphesis_1(0) => N1,
      gt_di(127) => gt_di(127),
      gt_di(126) => gt_di(126),
      gt_di(125) => gt_di(125),
      gt_di(124) => gt_di(124),
      gt_di(123) => gt_di(123),
      gt_di(122) => gt_di(122),
      gt_di(121) => gt_di(121),
      gt_di(120) => gt_di(120),
      gt_di(119) => gt_di(119),
      gt_di(118) => gt_di(118),
      gt_di(117) => gt_di(117),
      gt_di(116) => gt_di(116),
      gt_di(115) => gt_di(115),
      gt_di(114) => gt_di(114),
      gt_di(113) => gt_di(113),
      gt_di(112) => gt_di(112),
      gt_di(111) => gt_di(111),
      gt_di(110) => gt_di(110),
      gt_di(109) => gt_di(109),
      gt_di(108) => gt_di(108),
      gt_di(107) => gt_di(107),
      gt_di(106) => gt_di(106),
      gt_di(105) => gt_di(105),
      gt_di(104) => gt_di(104),
      gt_di(103) => gt_di(103),
      gt_di(102) => gt_di(102),
      gt_di(101) => gt_di(101),
      gt_di(100) => gt_di(100),
      gt_di(99) => gt_di(99),
      gt_di(98) => gt_di(98),
      gt_di(97) => gt_di(97),
      gt_di(96) => gt_di(96),
      gt_di(95) => gt_di(95),
      gt_di(94) => gt_di(94),
      gt_di(93) => gt_di(93),
      gt_di(92) => gt_di(92),
      gt_di(91) => gt_di(91),
      gt_di(90) => gt_di(90),
      gt_di(89) => gt_di(89),
      gt_di(88) => gt_di(88),
      gt_di(87) => gt_di(87),
      gt_di(86) => gt_di(86),
      gt_di(85) => gt_di(85),
      gt_di(84) => gt_di(84),
      gt_di(83) => gt_di(83),
      gt_di(82) => gt_di(82),
      gt_di(81) => gt_di(81),
      gt_di(80) => gt_di(80),
      gt_di(79) => gt_di(79),
      gt_di(78) => gt_di(78),
      gt_di(77) => gt_di(77),
      gt_di(76) => gt_di(76),
      gt_di(75) => gt_di(75),
      gt_di(74) => gt_di(74),
      gt_di(73) => gt_di(73),
      gt_di(72) => gt_di(72),
      gt_di(71) => gt_di(71),
      gt_di(70) => gt_di(70),
      gt_di(69) => gt_di(69),
      gt_di(68) => gt_di(68),
      gt_di(67) => gt_di(67),
      gt_di(66) => gt_di(66),
      gt_di(65) => gt_di(65),
      gt_di(64) => gt_di(64),
      gt_di(63) => gt_di(63),
      gt_di(62) => gt_di(62),
      gt_di(61) => gt_di(61),
      gt_di(60) => gt_di(60),
      gt_di(59) => gt_di(59),
      gt_di(58) => gt_di(58),
      gt_di(57) => gt_di(57),
      gt_di(56) => gt_di(56),
      gt_di(55) => gt_di(55),
      gt_di(54) => gt_di(54),
      gt_di(53) => gt_di(53),
      gt_di(52) => gt_di(52),
      gt_di(51) => gt_di(51),
      gt_di(50) => gt_di(50),
      gt_di(49) => gt_di(49),
      gt_di(48) => gt_di(48),
      gt_di(47) => gt_di(47),
      gt_di(46) => gt_di(46),
      gt_di(45) => gt_di(45),
      gt_di(44) => gt_di(44),
      gt_di(43) => gt_di(43),
      gt_di(42) => gt_di(42),
      gt_di(41) => gt_di(41),
      gt_di(40) => gt_di(40),
      gt_di(39) => gt_di(39),
      gt_di(38) => gt_di(38),
      gt_di(37) => gt_di(37),
      gt_di(36) => gt_di(36),
      gt_di(35) => gt_di(35),
      gt_di(34) => gt_di(34),
      gt_di(33) => gt_di(33),
      gt_di(32) => gt_di(32),
      gt_di(31) => gt_di(31),
      gt_di(30) => gt_di(30),
      gt_di(29) => gt_di(29),
      gt_di(28) => gt_di(28),
      gt_di(27) => gt_di(27),
      gt_di(26) => gt_di(26),
      gt_di(25) => gt_di(25),
      gt_di(24) => gt_di(24),
      gt_di(23) => gt_di(23),
      gt_di(22) => gt_di(22),
      gt_di(21) => gt_di(21),
      gt_di(20) => gt_di(20),
      gt_di(19) => gt_di(19),
      gt_di(18) => gt_di(18),
      gt_di(17) => gt_di(17),
      gt_di(16) => gt_di(16),
      gt_di(15) => gt_di(15),
      gt_di(14) => gt_di(14),
      gt_di(13) => gt_di(13),
      gt_di(12) => gt_di(12),
      gt_di(11) => gt_di(11),
      gt_di(10) => gt_di(10),
      gt_di(9) => gt_di(9),
      gt_di(8) => gt_di(8),
      gt_di(7) => gt_di(7),
      gt_di(6) => gt_di(6),
      gt_di(5) => gt_di(5),
      gt_di(4) => gt_di(4),
      gt_di(3) => gt_di(3),
      gt_di(2) => gt_di(2),
      gt_di(1) => gt_di(1),
      gt_di(0) => gt_di(0),
      gt_power_down(15) => gt_power_down(15),
      gt_power_down(14) => gt_power_down(14),
      gt_power_down(13) => gt_power_down(13),
      gt_power_down(12) => gt_power_down(12),
      gt_power_down(11) => gt_power_down(11),
      gt_power_down(10) => gt_power_down(10),
      gt_power_down(9) => gt_power_down(9),
      gt_power_down(8) => gt_power_down(8),
      gt_power_down(7) => gt_power_down(7),
      gt_power_down(6) => gt_power_down(6),
      gt_power_down(5) => gt_power_down(5),
      gt_power_down(4) => gt_power_down(4),
      gt_power_down(3) => gt_power_down(3),
      gt_power_down(2) => gt_power_down(2),
      gt_power_down(1) => gt_power_down(1),
      gt_power_down(0) => gt_power_down(0),
      gt_rx_polarity(7) => gt_rx_polarity(7),
      gt_rx_polarity(6) => gt_rx_polarity(6),
      gt_rx_polarity(5) => gt_rx_polarity(5),
      gt_rx_polarity(4) => gt_rx_polarity(4),
      gt_rx_polarity(3) => gt_rx_polarity(3),
      gt_rx_polarity(2) => gt_rx_polarity(2),
      gt_rx_polarity(1) => gt_rx_polarity(1),
      gt_rx_polarity(0) => gt_rx_polarity(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity bram_common_2_INST_1 is
  port (
    ena : in STD_LOGIC := 'X'; 
    enb : in STD_LOGIC := 'X'; 
    clka : in STD_LOGIC := 'X'; 
    clkb : in STD_LOGIC := 'X'; 
    wena : in STD_LOGIC := 'X'; 
    wenb : in STD_LOGIC := 'X'; 
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end bram_common_2_INST_1;

architecture STRUCTURE of bram_common_2_INST_1 is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_0_UNCONNECTED : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  generate_tdp2_0_ram_tdp2_inst : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      SIM_COLLISION_CHECK => "ALL",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ENAU => ena,
      ENAL => ena,
      ENBU => enb,
      ENBL => enb,
      SSRAU => N0,
      SSRAL => N0,
      SSRBU => N0,
      SSRBL => N0,
      CLKAU => clka,
      CLKAL => clka,
      CLKBU => clkb,
      CLKBL => clkb,
      REGCLKAU => clka,
      REGCLKAL => clka,
      REGCLKBU => clkb,
      REGCLKBL => clkb,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED,
      CASCADEINLATB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED,
      CASCADEINREGA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED,
      CASCADEINREGB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED,
      CASCADEOUTLATA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => dina(31),
      DIA(30) => dina(30),
      DIA(29) => dina(29),
      DIA(28) => dina(28),
      DIA(27) => dina(27),
      DIA(26) => dina(26),
      DIA(25) => dina(25),
      DIA(24) => dina(24),
      DIA(23) => dina(23),
      DIA(22) => dina(22),
      DIA(21) => dina(21),
      DIA(20) => dina(20),
      DIA(19) => dina(19),
      DIA(18) => dina(18),
      DIA(17) => dina(17),
      DIA(16) => dina(16),
      DIA(15) => dina(15),
      DIA(14) => dina(14),
      DIA(13) => dina(13),
      DIA(12) => dina(12),
      DIA(11) => dina(11),
      DIA(10) => dina(10),
      DIA(9) => dina(9),
      DIA(8) => dina(8),
      DIA(7) => dina(7),
      DIA(6) => dina(6),
      DIA(5) => dina(5),
      DIA(4) => dina(4),
      DIA(3) => dina(3),
      DIA(2) => dina(2),
      DIA(1) => dina(1),
      DIA(0) => dina(0),
      DIPA(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_1_UNCONNECTED,
      DIPA(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_0_UNCONNECTED,
      DIB(31) => dinb(31),
      DIB(30) => dinb(30),
      DIB(29) => dinb(29),
      DIB(28) => dinb(28),
      DIB(27) => dinb(27),
      DIB(26) => dinb(26),
      DIB(25) => dinb(25),
      DIB(24) => dinb(24),
      DIB(23) => dinb(23),
      DIB(22) => dinb(22),
      DIB(21) => dinb(21),
      DIB(20) => dinb(20),
      DIB(19) => dinb(19),
      DIB(18) => dinb(18),
      DIB(17) => dinb(17),
      DIB(16) => dinb(16),
      DIB(15) => dinb(15),
      DIB(14) => dinb(14),
      DIB(13) => dinb(13),
      DIB(12) => dinb(12),
      DIB(11) => dinb(11),
      DIB(10) => dinb(10),
      DIB(9) => dinb(9),
      DIB(8) => dinb(8),
      DIB(7) => dinb(7),
      DIB(6) => dinb(6),
      DIB(5) => dinb(5),
      DIB(4) => dinb(4),
      DIB(3) => dinb(3),
      DIB(2) => dinb(2),
      DIB(1) => dinb(1),
      DIB(0) => dinb(0),
      DIPB(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_1_UNCONNECTED,
      DIPB(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_0_UNCONNECTED,
      ADDRAL(15) => N0,
      ADDRAL(14) => addra(9),
      ADDRAL(13) => addra(8),
      ADDRAL(12) => addra(7),
      ADDRAL(11) => addra(6),
      ADDRAL(10) => addra(5),
      ADDRAL(9) => addra(4),
      ADDRAL(8) => addra(3),
      ADDRAL(7) => addra(2),
      ADDRAL(6) => addra(1),
      ADDRAL(5) => addra(0),
      ADDRAL(4) => N0,
      ADDRAL(3) => N0,
      ADDRAL(2) => N0,
      ADDRAL(1) => N0,
      ADDRAL(0) => N0,
      ADDRAU(14) => addra(9),
      ADDRAU(13) => addra(8),
      ADDRAU(12) => addra(7),
      ADDRAU(11) => addra(6),
      ADDRAU(10) => addra(5),
      ADDRAU(9) => addra(4),
      ADDRAU(8) => addra(3),
      ADDRAU(7) => addra(2),
      ADDRAU(6) => addra(1),
      ADDRAU(5) => addra(0),
      ADDRAU(4) => N0,
      ADDRAU(3) => N0,
      ADDRAU(2) => N0,
      ADDRAU(1) => N0,
      ADDRAU(0) => N0,
      ADDRBL(15) => N0,
      ADDRBL(14) => addrb(9),
      ADDRBL(13) => addrb(8),
      ADDRBL(12) => addrb(7),
      ADDRBL(11) => addrb(6),
      ADDRBL(10) => addrb(5),
      ADDRBL(9) => addrb(4),
      ADDRBL(8) => addrb(3),
      ADDRBL(7) => addrb(2),
      ADDRBL(6) => addrb(1),
      ADDRBL(5) => addrb(0),
      ADDRBL(4) => N0,
      ADDRBL(3) => N0,
      ADDRBL(2) => N0,
      ADDRBL(1) => N0,
      ADDRBL(0) => N0,
      ADDRBU(14) => addrb(9),
      ADDRBU(13) => addrb(8),
      ADDRBU(12) => addrb(7),
      ADDRBU(11) => addrb(6),
      ADDRBU(10) => addrb(5),
      ADDRBU(9) => addrb(4),
      ADDRBU(8) => addrb(3),
      ADDRBU(7) => addrb(2),
      ADDRBU(6) => addrb(1),
      ADDRBU(5) => addrb(0),
      ADDRBU(4) => N0,
      ADDRBU(3) => N0,
      ADDRBU(2) => N0,
      ADDRBU(1) => N0,
      ADDRBU(0) => N0,
      WEAU(3) => wena,
      WEAU(2) => wena,
      WEAU(1) => wena,
      WEAU(0) => wena,
      WEAL(3) => wena,
      WEAL(2) => wena,
      WEAL(1) => wena,
      WEAL(0) => wena,
      WEBU(7) => N0,
      WEBU(6) => N0,
      WEBU(5) => N0,
      WEBU(4) => N0,
      WEBU(3) => N0,
      WEBU(2) => N0,
      WEBU(1) => N0,
      WEBU(0) => N0,
      WEBL(7) => N0,
      WEBL(6) => N0,
      WEBL(5) => N0,
      WEBL(4) => N0,
      WEBL(3) => N0,
      WEBL(2) => N0,
      WEBL(1) => N0,
      WEBL(0) => N0,
      DOA(31) => douta(31),
      DOA(30) => douta(30),
      DOA(29) => douta(29),
      DOA(28) => douta(28),
      DOA(27) => douta(27),
      DOA(26) => douta(26),
      DOA(25) => douta(25),
      DOA(24) => douta(24),
      DOA(23) => douta(23),
      DOA(22) => douta(22),
      DOA(21) => douta(21),
      DOA(20) => douta(20),
      DOA(19) => douta(19),
      DOA(18) => douta(18),
      DOA(17) => douta(17),
      DOA(16) => douta(16),
      DOA(15) => douta(15),
      DOA(14) => douta(14),
      DOA(13) => douta(13),
      DOA(12) => douta(12),
      DOA(11) => douta(11),
      DOA(10) => douta(10),
      DOA(9) => douta(9),
      DOA(8) => douta(8),
      DOA(7) => douta(7),
      DOA(6) => douta(6),
      DOA(5) => douta(5),
      DOA(4) => douta(4),
      DOA(3) => douta(3),
      DOA(2) => douta(2),
      DOA(1) => douta(1),
      DOA(0) => douta(0),
      DOPA(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_0_UNCONNECTED,
      DOB(31) => doutb(31),
      DOB(30) => doutb(30),
      DOB(29) => doutb(29),
      DOB(28) => doutb(28),
      DOB(27) => doutb(27),
      DOB(26) => doutb(26),
      DOB(25) => doutb(25),
      DOB(24) => doutb(24),
      DOB(23) => doutb(23),
      DOB(22) => doutb(22),
      DOB(21) => doutb(21),
      DOB(20) => doutb(20),
      DOB(19) => doutb(19),
      DOB(18) => doutb(18),
      DOB(17) => doutb(17),
      DOB(16) => doutb(16),
      DOB(15) => doutb(15),
      DOB(14) => doutb(14),
      DOB(13) => doutb(13),
      DOB(12) => doutb(12),
      DOB(11) => doutb(11),
      DOB(10) => doutb(10),
      DOB(9) => doutb(9),
      DOB(8) => doutb(8),
      DOB(7) => doutb(7),
      DOB(6) => doutb(6),
      DOB(5) => doutb(5),
      DOB(4) => doutb(4),
      DOB(3) => doutb(3),
      DOB(2) => doutb(2),
      DOB(1) => doutb(1),
      DOB(0) => doutb(0),
      DOPB(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_0_UNCONNECTED
    );
  generate_tdp2_1_ram_tdp2_inst : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      SIM_COLLISION_CHECK => "ALL",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ENAU => ena,
      ENAL => ena,
      ENBU => enb,
      ENBL => enb,
      SSRAU => N0,
      SSRAL => N0,
      SSRBU => N0,
      SSRBL => N0,
      CLKAU => clka,
      CLKAL => clka,
      CLKBU => clkb,
      CLKBL => clkb,
      REGCLKAU => clka,
      REGCLKAL => clka,
      REGCLKBU => clkb,
      REGCLKBL => clkb,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED,
      CASCADEINLATB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED,
      CASCADEINREGA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED,
      CASCADEINREGB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED,
      CASCADEOUTLATA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => dina(63),
      DIA(30) => dina(62),
      DIA(29) => dina(61),
      DIA(28) => dina(60),
      DIA(27) => dina(59),
      DIA(26) => dina(58),
      DIA(25) => dina(57),
      DIA(24) => dina(56),
      DIA(23) => dina(55),
      DIA(22) => dina(54),
      DIA(21) => dina(53),
      DIA(20) => dina(52),
      DIA(19) => dina(51),
      DIA(18) => dina(50),
      DIA(17) => dina(49),
      DIA(16) => dina(48),
      DIA(15) => dina(47),
      DIA(14) => dina(46),
      DIA(13) => dina(45),
      DIA(12) => dina(44),
      DIA(11) => dina(43),
      DIA(10) => dina(42),
      DIA(9) => dina(41),
      DIA(8) => dina(40),
      DIA(7) => dina(39),
      DIA(6) => dina(38),
      DIA(5) => dina(37),
      DIA(4) => dina(36),
      DIA(3) => dina(35),
      DIA(2) => dina(34),
      DIA(1) => dina(33),
      DIA(0) => dina(32),
      DIPA(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_1_UNCONNECTED,
      DIPA(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_0_UNCONNECTED,
      DIB(31) => dinb(63),
      DIB(30) => dinb(62),
      DIB(29) => dinb(61),
      DIB(28) => dinb(60),
      DIB(27) => dinb(59),
      DIB(26) => dinb(58),
      DIB(25) => dinb(57),
      DIB(24) => dinb(56),
      DIB(23) => dinb(55),
      DIB(22) => dinb(54),
      DIB(21) => dinb(53),
      DIB(20) => dinb(52),
      DIB(19) => dinb(51),
      DIB(18) => dinb(50),
      DIB(17) => dinb(49),
      DIB(16) => dinb(48),
      DIB(15) => dinb(47),
      DIB(14) => dinb(46),
      DIB(13) => dinb(45),
      DIB(12) => dinb(44),
      DIB(11) => dinb(43),
      DIB(10) => dinb(42),
      DIB(9) => dinb(41),
      DIB(8) => dinb(40),
      DIB(7) => dinb(39),
      DIB(6) => dinb(38),
      DIB(5) => dinb(37),
      DIB(4) => dinb(36),
      DIB(3) => dinb(35),
      DIB(2) => dinb(34),
      DIB(1) => dinb(33),
      DIB(0) => dinb(32),
      DIPB(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_1_UNCONNECTED,
      DIPB(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_0_UNCONNECTED,
      ADDRAL(15) => N0,
      ADDRAL(14) => addra(9),
      ADDRAL(13) => addra(8),
      ADDRAL(12) => addra(7),
      ADDRAL(11) => addra(6),
      ADDRAL(10) => addra(5),
      ADDRAL(9) => addra(4),
      ADDRAL(8) => addra(3),
      ADDRAL(7) => addra(2),
      ADDRAL(6) => addra(1),
      ADDRAL(5) => addra(0),
      ADDRAL(4) => N0,
      ADDRAL(3) => N0,
      ADDRAL(2) => N0,
      ADDRAL(1) => N0,
      ADDRAL(0) => N0,
      ADDRAU(14) => addra(9),
      ADDRAU(13) => addra(8),
      ADDRAU(12) => addra(7),
      ADDRAU(11) => addra(6),
      ADDRAU(10) => addra(5),
      ADDRAU(9) => addra(4),
      ADDRAU(8) => addra(3),
      ADDRAU(7) => addra(2),
      ADDRAU(6) => addra(1),
      ADDRAU(5) => addra(0),
      ADDRAU(4) => N0,
      ADDRAU(3) => N0,
      ADDRAU(2) => N0,
      ADDRAU(1) => N0,
      ADDRAU(0) => N0,
      ADDRBL(15) => N0,
      ADDRBL(14) => addrb(9),
      ADDRBL(13) => addrb(8),
      ADDRBL(12) => addrb(7),
      ADDRBL(11) => addrb(6),
      ADDRBL(10) => addrb(5),
      ADDRBL(9) => addrb(4),
      ADDRBL(8) => addrb(3),
      ADDRBL(7) => addrb(2),
      ADDRBL(6) => addrb(1),
      ADDRBL(5) => addrb(0),
      ADDRBL(4) => N0,
      ADDRBL(3) => N0,
      ADDRBL(2) => N0,
      ADDRBL(1) => N0,
      ADDRBL(0) => N0,
      ADDRBU(14) => addrb(9),
      ADDRBU(13) => addrb(8),
      ADDRBU(12) => addrb(7),
      ADDRBU(11) => addrb(6),
      ADDRBU(10) => addrb(5),
      ADDRBU(9) => addrb(4),
      ADDRBU(8) => addrb(3),
      ADDRBU(7) => addrb(2),
      ADDRBU(6) => addrb(1),
      ADDRBU(5) => addrb(0),
      ADDRBU(4) => N0,
      ADDRBU(3) => N0,
      ADDRBU(2) => N0,
      ADDRBU(1) => N0,
      ADDRBU(0) => N0,
      WEAU(3) => wena,
      WEAU(2) => wena,
      WEAU(1) => wena,
      WEAU(0) => wena,
      WEAL(3) => wena,
      WEAL(2) => wena,
      WEAL(1) => wena,
      WEAL(0) => wena,
      WEBU(7) => N0,
      WEBU(6) => N0,
      WEBU(5) => N0,
      WEBU(4) => N0,
      WEBU(3) => N0,
      WEBU(2) => N0,
      WEBU(1) => N0,
      WEBU(0) => N0,
      WEBL(7) => N0,
      WEBL(6) => N0,
      WEBL(5) => N0,
      WEBL(4) => N0,
      WEBL(3) => N0,
      WEBL(2) => N0,
      WEBL(1) => N0,
      WEBL(0) => N0,
      DOA(31) => douta(63),
      DOA(30) => douta(62),
      DOA(29) => douta(61),
      DOA(28) => douta(60),
      DOA(27) => douta(59),
      DOA(26) => douta(58),
      DOA(25) => douta(57),
      DOA(24) => douta(56),
      DOA(23) => douta(55),
      DOA(22) => douta(54),
      DOA(21) => douta(53),
      DOA(20) => douta(52),
      DOA(19) => douta(51),
      DOA(18) => douta(50),
      DOA(17) => douta(49),
      DOA(16) => douta(48),
      DOA(15) => douta(47),
      DOA(14) => douta(46),
      DOA(13) => douta(45),
      DOA(12) => douta(44),
      DOA(11) => douta(43),
      DOA(10) => douta(42),
      DOA(9) => douta(41),
      DOA(8) => douta(40),
      DOA(7) => douta(39),
      DOA(6) => douta(38),
      DOA(5) => douta(37),
      DOA(4) => douta(36),
      DOA(3) => douta(35),
      DOA(2) => douta(34),
      DOA(1) => douta(33),
      DOA(0) => douta(32),
      DOPA(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_0_UNCONNECTED,
      DOB(31) => doutb(63),
      DOB(30) => doutb(62),
      DOB(29) => doutb(61),
      DOB(28) => doutb(60),
      DOB(27) => doutb(59),
      DOB(26) => doutb(58),
      DOB(25) => doutb(57),
      DOB(24) => doutb(56),
      DOB(23) => doutb(55),
      DOB(22) => doutb(54),
      DOB(21) => doutb(53),
      DOB(20) => doutb(52),
      DOB(19) => doutb(51),
      DOB(18) => doutb(50),
      DOB(17) => doutb(49),
      DOB(16) => doutb(48),
      DOB(15) => doutb(47),
      DOB(14) => doutb(46),
      DOB(13) => doutb(45),
      DOB(12) => doutb(44),
      DOB(11) => doutb(43),
      DOB(10) => doutb(42),
      DOB(9) => doutb(41),
      DOB(8) => doutb(40),
      DOB(7) => doutb(39),
      DOB(6) => doutb(38),
      DOB(5) => doutb(37),
      DOB(4) => doutb(36),
      DOB(3) => doutb(35),
      DOB(2) => doutb(34),
      DOB(1) => doutb(33),
      DOB(0) => doutb(32),
      DOPB(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity bram_common_2 is
  port (
    ena : in STD_LOGIC := 'X'; 
    enb : in STD_LOGIC := 'X'; 
    clka : in STD_LOGIC := 'X'; 
    clkb : in STD_LOGIC := 'X'; 
    wena : in STD_LOGIC := 'X'; 
    wenb : in STD_LOGIC := 'X'; 
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end bram_common_2;

architecture STRUCTURE of bram_common_2 is
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_0_UNCONNECTED : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  generate_tdp2_0_ram_tdp2_inst : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      SIM_COLLISION_CHECK => "ALL",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ENAU => ena,
      ENAL => ena,
      ENBU => enb,
      ENBL => enb,
      SSRAU => N0,
      SSRAL => N0,
      SSRBU => N0,
      SSRBL => N0,
      CLKAU => clka,
      CLKAL => clka,
      CLKBU => clkb,
      CLKBL => clkb,
      REGCLKAU => clka,
      REGCLKAL => clka,
      REGCLKBU => clkb,
      REGCLKBL => clkb,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED,
      CASCADEINLATB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED,
      CASCADEINREGA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED,
      CASCADEINREGB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED,
      CASCADEOUTLATA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_generate_tdp2_0_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => dina(31),
      DIA(30) => dina(30),
      DIA(29) => dina(29),
      DIA(28) => dina(28),
      DIA(27) => dina(27),
      DIA(26) => dina(26),
      DIA(25) => dina(25),
      DIA(24) => dina(24),
      DIA(23) => dina(23),
      DIA(22) => dina(22),
      DIA(21) => dina(21),
      DIA(20) => dina(20),
      DIA(19) => dina(19),
      DIA(18) => dina(18),
      DIA(17) => dina(17),
      DIA(16) => dina(16),
      DIA(15) => dina(15),
      DIA(14) => dina(14),
      DIA(13) => dina(13),
      DIA(12) => dina(12),
      DIA(11) => dina(11),
      DIA(10) => dina(10),
      DIA(9) => dina(9),
      DIA(8) => dina(8),
      DIA(7) => dina(7),
      DIA(6) => dina(6),
      DIA(5) => dina(5),
      DIA(4) => dina(4),
      DIA(3) => dina(3),
      DIA(2) => dina(2),
      DIA(1) => dina(1),
      DIA(0) => dina(0),
      DIPA(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_1_UNCONNECTED,
      DIPA(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPA_0_UNCONNECTED,
      DIB(31) => dinb(31),
      DIB(30) => dinb(30),
      DIB(29) => dinb(29),
      DIB(28) => dinb(28),
      DIB(27) => dinb(27),
      DIB(26) => dinb(26),
      DIB(25) => dinb(25),
      DIB(24) => dinb(24),
      DIB(23) => dinb(23),
      DIB(22) => dinb(22),
      DIB(21) => dinb(21),
      DIB(20) => dinb(20),
      DIB(19) => dinb(19),
      DIB(18) => dinb(18),
      DIB(17) => dinb(17),
      DIB(16) => dinb(16),
      DIB(15) => dinb(15),
      DIB(14) => dinb(14),
      DIB(13) => dinb(13),
      DIB(12) => dinb(12),
      DIB(11) => dinb(11),
      DIB(10) => dinb(10),
      DIB(9) => dinb(9),
      DIB(8) => dinb(8),
      DIB(7) => dinb(7),
      DIB(6) => dinb(6),
      DIB(5) => dinb(5),
      DIB(4) => dinb(4),
      DIB(3) => dinb(3),
      DIB(2) => dinb(2),
      DIB(1) => dinb(1),
      DIB(0) => dinb(0),
      DIPB(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_1_UNCONNECTED,
      DIPB(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DIPB_0_UNCONNECTED,
      ADDRAL(15) => N0,
      ADDRAL(14) => addra(9),
      ADDRAL(13) => addra(8),
      ADDRAL(12) => addra(7),
      ADDRAL(11) => addra(6),
      ADDRAL(10) => addra(5),
      ADDRAL(9) => addra(4),
      ADDRAL(8) => addra(3),
      ADDRAL(7) => addra(2),
      ADDRAL(6) => addra(1),
      ADDRAL(5) => addra(0),
      ADDRAL(4) => N0,
      ADDRAL(3) => N0,
      ADDRAL(2) => N0,
      ADDRAL(1) => N0,
      ADDRAL(0) => N0,
      ADDRAU(14) => addra(9),
      ADDRAU(13) => addra(8),
      ADDRAU(12) => addra(7),
      ADDRAU(11) => addra(6),
      ADDRAU(10) => addra(5),
      ADDRAU(9) => addra(4),
      ADDRAU(8) => addra(3),
      ADDRAU(7) => addra(2),
      ADDRAU(6) => addra(1),
      ADDRAU(5) => addra(0),
      ADDRAU(4) => N0,
      ADDRAU(3) => N0,
      ADDRAU(2) => N0,
      ADDRAU(1) => N0,
      ADDRAU(0) => N0,
      ADDRBL(15) => N0,
      ADDRBL(14) => addrb(9),
      ADDRBL(13) => addrb(8),
      ADDRBL(12) => addrb(7),
      ADDRBL(11) => addrb(6),
      ADDRBL(10) => addrb(5),
      ADDRBL(9) => addrb(4),
      ADDRBL(8) => addrb(3),
      ADDRBL(7) => addrb(2),
      ADDRBL(6) => addrb(1),
      ADDRBL(5) => addrb(0),
      ADDRBL(4) => N0,
      ADDRBL(3) => N0,
      ADDRBL(2) => N0,
      ADDRBL(1) => N0,
      ADDRBL(0) => N0,
      ADDRBU(14) => addrb(9),
      ADDRBU(13) => addrb(8),
      ADDRBU(12) => addrb(7),
      ADDRBU(11) => addrb(6),
      ADDRBU(10) => addrb(5),
      ADDRBU(9) => addrb(4),
      ADDRBU(8) => addrb(3),
      ADDRBU(7) => addrb(2),
      ADDRBU(6) => addrb(1),
      ADDRBU(5) => addrb(0),
      ADDRBU(4) => N0,
      ADDRBU(3) => N0,
      ADDRBU(2) => N0,
      ADDRBU(1) => N0,
      ADDRBU(0) => N0,
      WEAU(3) => wena,
      WEAU(2) => wena,
      WEAU(1) => wena,
      WEAU(0) => wena,
      WEAL(3) => wena,
      WEAL(2) => wena,
      WEAL(1) => wena,
      WEAL(0) => wena,
      WEBU(7) => N0,
      WEBU(6) => N0,
      WEBU(5) => N0,
      WEBU(4) => N0,
      WEBU(3) => N0,
      WEBU(2) => N0,
      WEBU(1) => N0,
      WEBU(0) => N0,
      WEBL(7) => N0,
      WEBL(6) => N0,
      WEBL(5) => N0,
      WEBL(4) => N0,
      WEBL(3) => N0,
      WEBL(2) => N0,
      WEBL(1) => N0,
      WEBL(0) => N0,
      DOA(31) => douta(31),
      DOA(30) => douta(30),
      DOA(29) => douta(29),
      DOA(28) => douta(28),
      DOA(27) => douta(27),
      DOA(26) => douta(26),
      DOA(25) => douta(25),
      DOA(24) => douta(24),
      DOA(23) => douta(23),
      DOA(22) => douta(22),
      DOA(21) => douta(21),
      DOA(20) => douta(20),
      DOA(19) => douta(19),
      DOA(18) => douta(18),
      DOA(17) => douta(17),
      DOA(16) => douta(16),
      DOA(15) => douta(15),
      DOA(14) => douta(14),
      DOA(13) => douta(13),
      DOA(12) => douta(12),
      DOA(11) => douta(11),
      DOA(10) => douta(10),
      DOA(9) => douta(9),
      DOA(8) => douta(8),
      DOA(7) => douta(7),
      DOA(6) => douta(6),
      DOA(5) => douta(5),
      DOA(4) => douta(4),
      DOA(3) => douta(3),
      DOA(2) => douta(2),
      DOA(1) => douta(1),
      DOA(0) => douta(0),
      DOPA(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPA_0_UNCONNECTED,
      DOB(31) => doutb(31),
      DOB(30) => doutb(30),
      DOB(29) => doutb(29),
      DOB(28) => doutb(28),
      DOB(27) => doutb(27),
      DOB(26) => doutb(26),
      DOB(25) => doutb(25),
      DOB(24) => doutb(24),
      DOB(23) => doutb(23),
      DOB(22) => doutb(22),
      DOB(21) => doutb(21),
      DOB(20) => doutb(20),
      DOB(19) => doutb(19),
      DOB(18) => doutb(18),
      DOB(17) => doutb(17),
      DOB(16) => doutb(16),
      DOB(15) => doutb(15),
      DOB(14) => doutb(14),
      DOB(13) => doutb(13),
      DOB(12) => doutb(12),
      DOB(11) => doutb(11),
      DOB(10) => doutb(10),
      DOB(9) => doutb(9),
      DOB(8) => doutb(8),
      DOB(7) => doutb(7),
      DOB(6) => doutb(6),
      DOB(5) => doutb(5),
      DOB(4) => doutb(4),
      DOB(3) => doutb(3),
      DOB(2) => doutb(2),
      DOB(1) => doutb(1),
      DOB(0) => doutb(0),
      DOPB(3) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_generate_tdp2_0_ram_tdp2_inst_DOPB_0_UNCONNECTED
    );
  generate_tdp2_1_ram_tdp2_inst : RAMB36_EXP
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      SIM_COLLISION_CHECK => "ALL",
      SIM_MODE => "SAFE",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      WRITE_MODE_A => "READ_FIRST",
      WRITE_MODE_B => "READ_FIRST",
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      ENAU => ena,
      ENAL => ena,
      ENBU => enb,
      ENBL => enb,
      SSRAU => N0,
      SSRAL => N0,
      SSRBU => N0,
      SSRBL => N0,
      CLKAU => clka,
      CLKAL => clka,
      CLKBU => clkb,
      CLKBL => clkb,
      REGCLKAU => clka,
      REGCLKAL => clka,
      REGCLKBU => clkb,
      REGCLKBL => clkb,
      REGCEAU => N1,
      REGCEAL => N1,
      REGCEBU => N1,
      REGCEBL => N1,
      CASCADEINLATA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATA_UNCONNECTED,
      CASCADEINLATB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINLATB_UNCONNECTED,
      CASCADEINREGA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGA_UNCONNECTED,
      CASCADEINREGB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEINREGB_UNCONNECTED,
      CASCADEOUTLATA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATA_UNCONNECTED,
      CASCADEOUTLATB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTLATB_UNCONNECTED,
      CASCADEOUTREGA => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGA_UNCONNECTED,
      CASCADEOUTREGB => NLW_generate_tdp2_1_ram_tdp2_inst_CASCADEOUTREGB_UNCONNECTED,
      DIA(31) => dina(63),
      DIA(30) => dina(62),
      DIA(29) => dina(61),
      DIA(28) => dina(60),
      DIA(27) => dina(59),
      DIA(26) => dina(58),
      DIA(25) => dina(57),
      DIA(24) => dina(56),
      DIA(23) => dina(55),
      DIA(22) => dina(54),
      DIA(21) => dina(53),
      DIA(20) => dina(52),
      DIA(19) => dina(51),
      DIA(18) => dina(50),
      DIA(17) => dina(49),
      DIA(16) => dina(48),
      DIA(15) => dina(47),
      DIA(14) => dina(46),
      DIA(13) => dina(45),
      DIA(12) => dina(44),
      DIA(11) => dina(43),
      DIA(10) => dina(42),
      DIA(9) => dina(41),
      DIA(8) => dina(40),
      DIA(7) => dina(39),
      DIA(6) => dina(38),
      DIA(5) => dina(37),
      DIA(4) => dina(36),
      DIA(3) => dina(35),
      DIA(2) => dina(34),
      DIA(1) => dina(33),
      DIA(0) => dina(32),
      DIPA(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_1_UNCONNECTED,
      DIPA(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPA_0_UNCONNECTED,
      DIB(31) => dinb(63),
      DIB(30) => dinb(62),
      DIB(29) => dinb(61),
      DIB(28) => dinb(60),
      DIB(27) => dinb(59),
      DIB(26) => dinb(58),
      DIB(25) => dinb(57),
      DIB(24) => dinb(56),
      DIB(23) => dinb(55),
      DIB(22) => dinb(54),
      DIB(21) => dinb(53),
      DIB(20) => dinb(52),
      DIB(19) => dinb(51),
      DIB(18) => dinb(50),
      DIB(17) => dinb(49),
      DIB(16) => dinb(48),
      DIB(15) => dinb(47),
      DIB(14) => dinb(46),
      DIB(13) => dinb(45),
      DIB(12) => dinb(44),
      DIB(11) => dinb(43),
      DIB(10) => dinb(42),
      DIB(9) => dinb(41),
      DIB(8) => dinb(40),
      DIB(7) => dinb(39),
      DIB(6) => dinb(38),
      DIB(5) => dinb(37),
      DIB(4) => dinb(36),
      DIB(3) => dinb(35),
      DIB(2) => dinb(34),
      DIB(1) => dinb(33),
      DIB(0) => dinb(32),
      DIPB(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_1_UNCONNECTED,
      DIPB(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DIPB_0_UNCONNECTED,
      ADDRAL(15) => N0,
      ADDRAL(14) => addra(9),
      ADDRAL(13) => addra(8),
      ADDRAL(12) => addra(7),
      ADDRAL(11) => addra(6),
      ADDRAL(10) => addra(5),
      ADDRAL(9) => addra(4),
      ADDRAL(8) => addra(3),
      ADDRAL(7) => addra(2),
      ADDRAL(6) => addra(1),
      ADDRAL(5) => addra(0),
      ADDRAL(4) => N0,
      ADDRAL(3) => N0,
      ADDRAL(2) => N0,
      ADDRAL(1) => N0,
      ADDRAL(0) => N0,
      ADDRAU(14) => addra(9),
      ADDRAU(13) => addra(8),
      ADDRAU(12) => addra(7),
      ADDRAU(11) => addra(6),
      ADDRAU(10) => addra(5),
      ADDRAU(9) => addra(4),
      ADDRAU(8) => addra(3),
      ADDRAU(7) => addra(2),
      ADDRAU(6) => addra(1),
      ADDRAU(5) => addra(0),
      ADDRAU(4) => N0,
      ADDRAU(3) => N0,
      ADDRAU(2) => N0,
      ADDRAU(1) => N0,
      ADDRAU(0) => N0,
      ADDRBL(15) => N0,
      ADDRBL(14) => addrb(9),
      ADDRBL(13) => addrb(8),
      ADDRBL(12) => addrb(7),
      ADDRBL(11) => addrb(6),
      ADDRBL(10) => addrb(5),
      ADDRBL(9) => addrb(4),
      ADDRBL(8) => addrb(3),
      ADDRBL(7) => addrb(2),
      ADDRBL(6) => addrb(1),
      ADDRBL(5) => addrb(0),
      ADDRBL(4) => N0,
      ADDRBL(3) => N0,
      ADDRBL(2) => N0,
      ADDRBL(1) => N0,
      ADDRBL(0) => N0,
      ADDRBU(14) => addrb(9),
      ADDRBU(13) => addrb(8),
      ADDRBU(12) => addrb(7),
      ADDRBU(11) => addrb(6),
      ADDRBU(10) => addrb(5),
      ADDRBU(9) => addrb(4),
      ADDRBU(8) => addrb(3),
      ADDRBU(7) => addrb(2),
      ADDRBU(6) => addrb(1),
      ADDRBU(5) => addrb(0),
      ADDRBU(4) => N0,
      ADDRBU(3) => N0,
      ADDRBU(2) => N0,
      ADDRBU(1) => N0,
      ADDRBU(0) => N0,
      WEAU(3) => wena,
      WEAU(2) => wena,
      WEAU(1) => wena,
      WEAU(0) => wena,
      WEAL(3) => wena,
      WEAL(2) => wena,
      WEAL(1) => wena,
      WEAL(0) => wena,
      WEBU(7) => N0,
      WEBU(6) => N0,
      WEBU(5) => N0,
      WEBU(4) => N0,
      WEBU(3) => N0,
      WEBU(2) => N0,
      WEBU(1) => N0,
      WEBU(0) => N0,
      WEBL(7) => N0,
      WEBL(6) => N0,
      WEBL(5) => N0,
      WEBL(4) => N0,
      WEBL(3) => N0,
      WEBL(2) => N0,
      WEBL(1) => N0,
      WEBL(0) => N0,
      DOA(31) => douta(63),
      DOA(30) => douta(62),
      DOA(29) => douta(61),
      DOA(28) => douta(60),
      DOA(27) => douta(59),
      DOA(26) => douta(58),
      DOA(25) => douta(57),
      DOA(24) => douta(56),
      DOA(23) => douta(55),
      DOA(22) => douta(54),
      DOA(21) => douta(53),
      DOA(20) => douta(52),
      DOA(19) => douta(51),
      DOA(18) => douta(50),
      DOA(17) => douta(49),
      DOA(16) => douta(48),
      DOA(15) => douta(47),
      DOA(14) => douta(46),
      DOA(13) => douta(45),
      DOA(12) => douta(44),
      DOA(11) => douta(43),
      DOA(10) => douta(42),
      DOA(9) => douta(41),
      DOA(8) => douta(40),
      DOA(7) => douta(39),
      DOA(6) => douta(38),
      DOA(5) => douta(37),
      DOA(4) => douta(36),
      DOA(3) => douta(35),
      DOA(2) => douta(34),
      DOA(1) => douta(33),
      DOA(0) => douta(32),
      DOPA(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPA_0_UNCONNECTED,
      DOB(31) => doutb(63),
      DOB(30) => doutb(62),
      DOB(29) => doutb(61),
      DOB(28) => doutb(60),
      DOB(27) => doutb(59),
      DOB(26) => doutb(58),
      DOB(25) => doutb(57),
      DOB(24) => doutb(56),
      DOB(23) => doutb(55),
      DOB(22) => doutb(54),
      DOB(21) => doutb(53),
      DOB(20) => doutb(52),
      DOB(19) => doutb(51),
      DOB(18) => doutb(50),
      DOB(17) => doutb(49),
      DOB(16) => doutb(48),
      DOB(15) => doutb(47),
      DOB(14) => doutb(46),
      DOB(13) => doutb(45),
      DOB(12) => doutb(44),
      DOB(11) => doutb(43),
      DOB(10) => doutb(42),
      DOB(9) => doutb(41),
      DOB(8) => doutb(40),
      DOB(7) => doutb(39),
      DOB(6) => doutb(38),
      DOB(5) => doutb(37),
      DOB(4) => doutb(36),
      DOB(3) => doutb(35),
      DOB(2) => doutb(34),
      DOB(1) => doutb(33),
      DOB(0) => doutb(32),
      DOPB(3) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_generate_tdp2_1_ram_tdp2_inst_DOPB_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity bram_common_1 is
  port (
    ena : in STD_LOGIC := 'X'; 
    enb : in STD_LOGIC := 'X'; 
    clka : in STD_LOGIC := 'X'; 
    clkb : in STD_LOGIC := 'X'; 
    wena : in STD_LOGIC := 'X'; 
    wenb : in STD_LOGIC := 'X'; 
    douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end bram_common_1;

architecture STRUCTURE of bram_common_1 is
  signal N1 : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_SBITERR_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DBITERR_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_RDADDRU_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_WRADDRU_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_DOP_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_generate_sdp_ram_sdp_inst_ECCPARITY_0_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSig_OI_douta : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  douta(63) <= NlwRenamedSig_OI_douta(0);
  douta(62) <= NlwRenamedSig_OI_douta(0);
  douta(61) <= NlwRenamedSig_OI_douta(0);
  douta(60) <= NlwRenamedSig_OI_douta(0);
  douta(59) <= NlwRenamedSig_OI_douta(0);
  douta(58) <= NlwRenamedSig_OI_douta(0);
  douta(57) <= NlwRenamedSig_OI_douta(0);
  douta(56) <= NlwRenamedSig_OI_douta(0);
  douta(55) <= NlwRenamedSig_OI_douta(0);
  douta(54) <= NlwRenamedSig_OI_douta(0);
  douta(53) <= NlwRenamedSig_OI_douta(0);
  douta(52) <= NlwRenamedSig_OI_douta(0);
  douta(51) <= NlwRenamedSig_OI_douta(0);
  douta(50) <= NlwRenamedSig_OI_douta(0);
  douta(49) <= NlwRenamedSig_OI_douta(0);
  douta(48) <= NlwRenamedSig_OI_douta(0);
  douta(47) <= NlwRenamedSig_OI_douta(0);
  douta(46) <= NlwRenamedSig_OI_douta(0);
  douta(45) <= NlwRenamedSig_OI_douta(0);
  douta(44) <= NlwRenamedSig_OI_douta(0);
  douta(43) <= NlwRenamedSig_OI_douta(0);
  douta(42) <= NlwRenamedSig_OI_douta(0);
  douta(41) <= NlwRenamedSig_OI_douta(0);
  douta(40) <= NlwRenamedSig_OI_douta(0);
  douta(39) <= NlwRenamedSig_OI_douta(0);
  douta(38) <= NlwRenamedSig_OI_douta(0);
  douta(37) <= NlwRenamedSig_OI_douta(0);
  douta(36) <= NlwRenamedSig_OI_douta(0);
  douta(35) <= NlwRenamedSig_OI_douta(0);
  douta(34) <= NlwRenamedSig_OI_douta(0);
  douta(33) <= NlwRenamedSig_OI_douta(0);
  douta(32) <= NlwRenamedSig_OI_douta(0);
  douta(31) <= NlwRenamedSig_OI_douta(0);
  douta(30) <= NlwRenamedSig_OI_douta(0);
  douta(29) <= NlwRenamedSig_OI_douta(0);
  douta(28) <= NlwRenamedSig_OI_douta(0);
  douta(27) <= NlwRenamedSig_OI_douta(0);
  douta(26) <= NlwRenamedSig_OI_douta(0);
  douta(25) <= NlwRenamedSig_OI_douta(0);
  douta(24) <= NlwRenamedSig_OI_douta(0);
  douta(23) <= NlwRenamedSig_OI_douta(0);
  douta(22) <= NlwRenamedSig_OI_douta(0);
  douta(21) <= NlwRenamedSig_OI_douta(0);
  douta(20) <= NlwRenamedSig_OI_douta(0);
  douta(19) <= NlwRenamedSig_OI_douta(0);
  douta(18) <= NlwRenamedSig_OI_douta(0);
  douta(17) <= NlwRenamedSig_OI_douta(0);
  douta(16) <= NlwRenamedSig_OI_douta(0);
  douta(15) <= NlwRenamedSig_OI_douta(0);
  douta(14) <= NlwRenamedSig_OI_douta(0);
  douta(13) <= NlwRenamedSig_OI_douta(0);
  douta(12) <= NlwRenamedSig_OI_douta(0);
  douta(11) <= NlwRenamedSig_OI_douta(0);
  douta(10) <= NlwRenamedSig_OI_douta(0);
  douta(9) <= NlwRenamedSig_OI_douta(0);
  douta(8) <= NlwRenamedSig_OI_douta(0);
  douta(7) <= NlwRenamedSig_OI_douta(0);
  douta(6) <= NlwRenamedSig_OI_douta(0);
  douta(5) <= NlwRenamedSig_OI_douta(0);
  douta(4) <= NlwRenamedSig_OI_douta(0);
  douta(3) <= NlwRenamedSig_OI_douta(0);
  douta(2) <= NlwRenamedSig_OI_douta(0);
  douta(1) <= NlwRenamedSig_OI_douta(0);
  douta(0) <= NlwRenamedSig_OI_douta(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_douta(0)
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  generate_sdp_ram_sdp_inst : RAMB36SDP_EXP
    generic map(
      DO_REG => 1,
      EN_ECC_READ => FALSE,
      EN_ECC_SCRUB => FALSE,
      EN_ECC_WRITE => FALSE,
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT => X"000000000000000000",
      SRVAL => X"000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_FILE => "NONE",
      SIM_COLLISION_CHECK => "ALL",
      SIM_MODE => "SAFE",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
    )
    port map (
      RDENU => enb,
      RDENL => enb,
      WRENU => ena,
      WRENL => ena,
      SSRU => NlwRenamedSig_OI_douta(0),
      SSRL => NlwRenamedSig_OI_douta(0),
      RDCLKU => clkb,
      RDCLKL => clkb,
      WRCLKU => clka,
      WRCLKL => clka,
      RDRCLKU => clkb,
      RDRCLKL => clkb,
      REGCEU => N1,
      REGCEL => N1,
      SBITERR => NLW_generate_sdp_ram_sdp_inst_SBITERR_UNCONNECTED,
      DBITERR => NLW_generate_sdp_ram_sdp_inst_DBITERR_UNCONNECTED,
      DI(63) => dina(63),
      DI(62) => dina(62),
      DI(61) => dina(61),
      DI(60) => dina(60),
      DI(59) => dina(59),
      DI(58) => dina(58),
      DI(57) => dina(57),
      DI(56) => dina(56),
      DI(55) => dina(55),
      DI(54) => dina(54),
      DI(53) => dina(53),
      DI(52) => dina(52),
      DI(51) => dina(51),
      DI(50) => dina(50),
      DI(49) => dina(49),
      DI(48) => dina(48),
      DI(47) => dina(47),
      DI(46) => dina(46),
      DI(45) => dina(45),
      DI(44) => dina(44),
      DI(43) => dina(43),
      DI(42) => dina(42),
      DI(41) => dina(41),
      DI(40) => dina(40),
      DI(39) => dina(39),
      DI(38) => dina(38),
      DI(37) => dina(37),
      DI(36) => dina(36),
      DI(35) => dina(35),
      DI(34) => dina(34),
      DI(33) => dina(33),
      DI(32) => dina(32),
      DI(31) => dina(31),
      DI(30) => dina(30),
      DI(29) => dina(29),
      DI(28) => dina(28),
      DI(27) => dina(27),
      DI(26) => dina(26),
      DI(25) => dina(25),
      DI(24) => dina(24),
      DI(23) => dina(23),
      DI(22) => dina(22),
      DI(21) => dina(21),
      DI(20) => dina(20),
      DI(19) => dina(19),
      DI(18) => dina(18),
      DI(17) => dina(17),
      DI(16) => dina(16),
      DI(15) => dina(15),
      DI(14) => dina(14),
      DI(13) => dina(13),
      DI(12) => dina(12),
      DI(11) => dina(11),
      DI(10) => dina(10),
      DI(9) => dina(9),
      DI(8) => dina(8),
      DI(7) => dina(7),
      DI(6) => dina(6),
      DI(5) => dina(5),
      DI(4) => dina(4),
      DI(3) => dina(3),
      DI(2) => dina(2),
      DI(1) => dina(1),
      DI(0) => dina(0),
      DIP(7) => NlwRenamedSig_OI_douta(0),
      DIP(6) => NlwRenamedSig_OI_douta(0),
      DIP(5) => NlwRenamedSig_OI_douta(0),
      DIP(4) => NlwRenamedSig_OI_douta(0),
      DIP(3) => NlwRenamedSig_OI_douta(0),
      DIP(2) => NlwRenamedSig_OI_douta(0),
      DIP(1) => NlwRenamedSig_OI_douta(0),
      DIP(0) => NlwRenamedSig_OI_douta(0),
      RDADDRL(15) => N1,
      RDADDRL(14) => addrb(8),
      RDADDRL(13) => addrb(7),
      RDADDRL(12) => addrb(6),
      RDADDRL(11) => addrb(5),
      RDADDRL(10) => addrb(4),
      RDADDRL(9) => addrb(3),
      RDADDRL(8) => addrb(2),
      RDADDRL(7) => addrb(1),
      RDADDRL(6) => addrb(0),
      RDADDRL(5) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_5_UNCONNECTED,
      RDADDRL(4) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_4_UNCONNECTED,
      RDADDRL(3) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_3_UNCONNECTED,
      RDADDRL(2) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_2_UNCONNECTED,
      RDADDRL(1) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_1_UNCONNECTED,
      RDADDRL(0) => NLW_generate_sdp_ram_sdp_inst_RDADDRL_0_UNCONNECTED,
      RDADDRU(14) => addrb(8),
      RDADDRU(13) => addrb(7),
      RDADDRU(12) => addrb(6),
      RDADDRU(11) => addrb(5),
      RDADDRU(10) => addrb(4),
      RDADDRU(9) => addrb(3),
      RDADDRU(8) => addrb(2),
      RDADDRU(7) => addrb(1),
      RDADDRU(6) => addrb(0),
      RDADDRU(5) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_5_UNCONNECTED,
      RDADDRU(4) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_4_UNCONNECTED,
      RDADDRU(3) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_3_UNCONNECTED,
      RDADDRU(2) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_2_UNCONNECTED,
      RDADDRU(1) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_1_UNCONNECTED,
      RDADDRU(0) => NLW_generate_sdp_ram_sdp_inst_RDADDRU_0_UNCONNECTED,
      WRADDRL(15) => N1,
      WRADDRL(14) => addra(8),
      WRADDRL(13) => addra(7),
      WRADDRL(12) => addra(6),
      WRADDRL(11) => addra(5),
      WRADDRL(10) => addra(4),
      WRADDRL(9) => addra(3),
      WRADDRL(8) => addra(2),
      WRADDRL(7) => addra(1),
      WRADDRL(6) => addra(0),
      WRADDRL(5) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_5_UNCONNECTED,
      WRADDRL(4) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_4_UNCONNECTED,
      WRADDRL(3) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_3_UNCONNECTED,
      WRADDRL(2) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_2_UNCONNECTED,
      WRADDRL(1) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_1_UNCONNECTED,
      WRADDRL(0) => NLW_generate_sdp_ram_sdp_inst_WRADDRL_0_UNCONNECTED,
      WRADDRU(14) => addra(8),
      WRADDRU(13) => addra(7),
      WRADDRU(12) => addra(6),
      WRADDRU(11) => addra(5),
      WRADDRU(10) => addra(4),
      WRADDRU(9) => addra(3),
      WRADDRU(8) => addra(2),
      WRADDRU(7) => addra(1),
      WRADDRU(6) => addra(0),
      WRADDRU(5) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_5_UNCONNECTED,
      WRADDRU(4) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_4_UNCONNECTED,
      WRADDRU(3) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_3_UNCONNECTED,
      WRADDRU(2) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_2_UNCONNECTED,
      WRADDRU(1) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_1_UNCONNECTED,
      WRADDRU(0) => NLW_generate_sdp_ram_sdp_inst_WRADDRU_0_UNCONNECTED,
      WEU(7) => wena,
      WEU(6) => wena,
      WEU(5) => wena,
      WEU(4) => wena,
      WEU(3) => wena,
      WEU(2) => wena,
      WEU(1) => wena,
      WEU(0) => wena,
      WEL(7) => wena,
      WEL(6) => wena,
      WEL(5) => wena,
      WEL(4) => wena,
      WEL(3) => wena,
      WEL(2) => wena,
      WEL(1) => wena,
      WEL(0) => wena,
      DO(63) => doutb(63),
      DO(62) => doutb(62),
      DO(61) => doutb(61),
      DO(60) => doutb(60),
      DO(59) => doutb(59),
      DO(58) => doutb(58),
      DO(57) => doutb(57),
      DO(56) => doutb(56),
      DO(55) => doutb(55),
      DO(54) => doutb(54),
      DO(53) => doutb(53),
      DO(52) => doutb(52),
      DO(51) => doutb(51),
      DO(50) => doutb(50),
      DO(49) => doutb(49),
      DO(48) => doutb(48),
      DO(47) => doutb(47),
      DO(46) => doutb(46),
      DO(45) => doutb(45),
      DO(44) => doutb(44),
      DO(43) => doutb(43),
      DO(42) => doutb(42),
      DO(41) => doutb(41),
      DO(40) => doutb(40),
      DO(39) => doutb(39),
      DO(38) => doutb(38),
      DO(37) => doutb(37),
      DO(36) => doutb(36),
      DO(35) => doutb(35),
      DO(34) => doutb(34),
      DO(33) => doutb(33),
      DO(32) => doutb(32),
      DO(31) => doutb(31),
      DO(30) => doutb(30),
      DO(29) => doutb(29),
      DO(28) => doutb(28),
      DO(27) => doutb(27),
      DO(26) => doutb(26),
      DO(25) => doutb(25),
      DO(24) => doutb(24),
      DO(23) => doutb(23),
      DO(22) => doutb(22),
      DO(21) => doutb(21),
      DO(20) => doutb(20),
      DO(19) => doutb(19),
      DO(18) => doutb(18),
      DO(17) => doutb(17),
      DO(16) => doutb(16),
      DO(15) => doutb(15),
      DO(14) => doutb(14),
      DO(13) => doutb(13),
      DO(12) => doutb(12),
      DO(11) => doutb(11),
      DO(10) => doutb(10),
      DO(9) => doutb(9),
      DO(8) => doutb(8),
      DO(7) => doutb(7),
      DO(6) => doutb(6),
      DO(5) => doutb(5),
      DO(4) => doutb(4),
      DO(3) => doutb(3),
      DO(2) => doutb(2),
      DO(1) => doutb(1),
      DO(0) => doutb(0),
      DOP(7) => NLW_generate_sdp_ram_sdp_inst_DOP_7_UNCONNECTED,
      DOP(6) => NLW_generate_sdp_ram_sdp_inst_DOP_6_UNCONNECTED,
      DOP(5) => NLW_generate_sdp_ram_sdp_inst_DOP_5_UNCONNECTED,
      DOP(4) => NLW_generate_sdp_ram_sdp_inst_DOP_4_UNCONNECTED,
      DOP(3) => NLW_generate_sdp_ram_sdp_inst_DOP_3_UNCONNECTED,
      DOP(2) => NLW_generate_sdp_ram_sdp_inst_DOP_2_UNCONNECTED,
      DOP(1) => NLW_generate_sdp_ram_sdp_inst_DOP_1_UNCONNECTED,
      DOP(0) => NLW_generate_sdp_ram_sdp_inst_DOP_0_UNCONNECTED,
      ECCPARITY(7) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_7_UNCONNECTED,
      ECCPARITY(6) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_6_UNCONNECTED,
      ECCPARITY(5) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_5_UNCONNECTED,
      ECCPARITY(4) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_4_UNCONNECTED,
      ECCPARITY(3) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_3_UNCONNECTED,
      ECCPARITY(2) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_2_UNCONNECTED,
      ECCPARITY(1) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_1_UNCONNECTED,
      ECCPARITY(0) => NLW_generate_sdp_ram_sdp_inst_ECCPARITY_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_mim_wrapper is
  port (
    mim_tx_bwclk : in STD_LOGIC := 'X'; 
    mim_tx_bren : in STD_LOGIC := 'X'; 
    mim_rx_bren : in STD_LOGIC := 'X'; 
    mim_rx_brclk : in STD_LOGIC := 'X'; 
    mim_dll_bren : in STD_LOGIC := 'X'; 
    mim_rx_bwclk : in STD_LOGIC := 'X'; 
    mim_dll_bclk : in STD_LOGIC := 'X'; 
    mim_tx_bwen : in STD_LOGIC := 'X'; 
    mim_tx_brclk : in STD_LOGIC := 'X'; 
    mim_rx_bwen : in STD_LOGIC := 'X'; 
    mim_dll_bwen : in STD_LOGIC := 'X'; 
    mim_tx_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_rx_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_dll_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_dll_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_dll_bwadd : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    mim_tx_bradd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    mim_tx_bwadd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    mim_rx_bradd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    mim_tx_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_rx_bwadd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
    mim_rx_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mim_dll_bradd : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end pcie_mim_wrapper;

architecture STRUCTURE of pcie_mim_wrapper is
  component bram_common_1
    port (
      ena : in STD_LOGIC := 'X'; 
      enb : in STD_LOGIC := 'X'; 
      clka : in STD_LOGIC := 'X'; 
      clkb : in STD_LOGIC := 'X'; 
      wena : in STD_LOGIC := 'X'; 
      wenb : in STD_LOGIC := 'X'; 
      douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      addra : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component bram_common_2
    port (
      ena : in STD_LOGIC := 'X'; 
      enb : in STD_LOGIC := 'X'; 
      clka : in STD_LOGIC := 'X'; 
      clkb : in STD_LOGIC := 'X'; 
      wena : in STD_LOGIC := 'X'; 
      wenb : in STD_LOGIC := 'X'; 
      douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component bram_common_2_INST_1
    port (
      ena : in STD_LOGIC := 'X'; 
      enb : in STD_LOGIC := 'X'; 
      clka : in STD_LOGIC := 'X'; 
      clkb : in STD_LOGIC := 'X'; 
      wena : in STD_LOGIC := 'X'; 
      wenb : in STD_LOGIC := 'X'; 
      douta : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      doutb : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      addra : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      addrb : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      dina : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      dinb : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal NLW_bram_tl_tx_wenb_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_tx_douta_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_wenb_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_tl_rx_douta_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_wenb_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_bram_retry_douta_0_UNCONNECTED : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  bram_retry : bram_common_1
    port map (
      ena => mim_dll_bwen,
      enb => mim_dll_bren,
      clka => mim_dll_bclk,
      clkb => mim_dll_bclk,
      wena => mim_dll_bwen,
      wenb => NLW_bram_retry_wenb_UNCONNECTED,
      douta(63) => NLW_bram_retry_douta_63_UNCONNECTED,
      douta(62) => NLW_bram_retry_douta_62_UNCONNECTED,
      douta(61) => NLW_bram_retry_douta_61_UNCONNECTED,
      douta(60) => NLW_bram_retry_douta_60_UNCONNECTED,
      douta(59) => NLW_bram_retry_douta_59_UNCONNECTED,
      douta(58) => NLW_bram_retry_douta_58_UNCONNECTED,
      douta(57) => NLW_bram_retry_douta_57_UNCONNECTED,
      douta(56) => NLW_bram_retry_douta_56_UNCONNECTED,
      douta(55) => NLW_bram_retry_douta_55_UNCONNECTED,
      douta(54) => NLW_bram_retry_douta_54_UNCONNECTED,
      douta(53) => NLW_bram_retry_douta_53_UNCONNECTED,
      douta(52) => NLW_bram_retry_douta_52_UNCONNECTED,
      douta(51) => NLW_bram_retry_douta_51_UNCONNECTED,
      douta(50) => NLW_bram_retry_douta_50_UNCONNECTED,
      douta(49) => NLW_bram_retry_douta_49_UNCONNECTED,
      douta(48) => NLW_bram_retry_douta_48_UNCONNECTED,
      douta(47) => NLW_bram_retry_douta_47_UNCONNECTED,
      douta(46) => NLW_bram_retry_douta_46_UNCONNECTED,
      douta(45) => NLW_bram_retry_douta_45_UNCONNECTED,
      douta(44) => NLW_bram_retry_douta_44_UNCONNECTED,
      douta(43) => NLW_bram_retry_douta_43_UNCONNECTED,
      douta(42) => NLW_bram_retry_douta_42_UNCONNECTED,
      douta(41) => NLW_bram_retry_douta_41_UNCONNECTED,
      douta(40) => NLW_bram_retry_douta_40_UNCONNECTED,
      douta(39) => NLW_bram_retry_douta_39_UNCONNECTED,
      douta(38) => NLW_bram_retry_douta_38_UNCONNECTED,
      douta(37) => NLW_bram_retry_douta_37_UNCONNECTED,
      douta(36) => NLW_bram_retry_douta_36_UNCONNECTED,
      douta(35) => NLW_bram_retry_douta_35_UNCONNECTED,
      douta(34) => NLW_bram_retry_douta_34_UNCONNECTED,
      douta(33) => NLW_bram_retry_douta_33_UNCONNECTED,
      douta(32) => NLW_bram_retry_douta_32_UNCONNECTED,
      douta(31) => NLW_bram_retry_douta_31_UNCONNECTED,
      douta(30) => NLW_bram_retry_douta_30_UNCONNECTED,
      douta(29) => NLW_bram_retry_douta_29_UNCONNECTED,
      douta(28) => NLW_bram_retry_douta_28_UNCONNECTED,
      douta(27) => NLW_bram_retry_douta_27_UNCONNECTED,
      douta(26) => NLW_bram_retry_douta_26_UNCONNECTED,
      douta(25) => NLW_bram_retry_douta_25_UNCONNECTED,
      douta(24) => NLW_bram_retry_douta_24_UNCONNECTED,
      douta(23) => NLW_bram_retry_douta_23_UNCONNECTED,
      douta(22) => NLW_bram_retry_douta_22_UNCONNECTED,
      douta(21) => NLW_bram_retry_douta_21_UNCONNECTED,
      douta(20) => NLW_bram_retry_douta_20_UNCONNECTED,
      douta(19) => NLW_bram_retry_douta_19_UNCONNECTED,
      douta(18) => NLW_bram_retry_douta_18_UNCONNECTED,
      douta(17) => NLW_bram_retry_douta_17_UNCONNECTED,
      douta(16) => NLW_bram_retry_douta_16_UNCONNECTED,
      douta(15) => NLW_bram_retry_douta_15_UNCONNECTED,
      douta(14) => NLW_bram_retry_douta_14_UNCONNECTED,
      douta(13) => NLW_bram_retry_douta_13_UNCONNECTED,
      douta(12) => NLW_bram_retry_douta_12_UNCONNECTED,
      douta(11) => NLW_bram_retry_douta_11_UNCONNECTED,
      douta(10) => NLW_bram_retry_douta_10_UNCONNECTED,
      douta(9) => NLW_bram_retry_douta_9_UNCONNECTED,
      douta(8) => NLW_bram_retry_douta_8_UNCONNECTED,
      douta(7) => NLW_bram_retry_douta_7_UNCONNECTED,
      douta(6) => NLW_bram_retry_douta_6_UNCONNECTED,
      douta(5) => NLW_bram_retry_douta_5_UNCONNECTED,
      douta(4) => NLW_bram_retry_douta_4_UNCONNECTED,
      douta(3) => NLW_bram_retry_douta_3_UNCONNECTED,
      douta(2) => NLW_bram_retry_douta_2_UNCONNECTED,
      douta(1) => NLW_bram_retry_douta_1_UNCONNECTED,
      douta(0) => NLW_bram_retry_douta_0_UNCONNECTED,
      doutb(63) => mim_dll_brdata(63),
      doutb(62) => mim_dll_brdata(62),
      doutb(61) => mim_dll_brdata(61),
      doutb(60) => mim_dll_brdata(60),
      doutb(59) => mim_dll_brdata(59),
      doutb(58) => mim_dll_brdata(58),
      doutb(57) => mim_dll_brdata(57),
      doutb(56) => mim_dll_brdata(56),
      doutb(55) => mim_dll_brdata(55),
      doutb(54) => mim_dll_brdata(54),
      doutb(53) => mim_dll_brdata(53),
      doutb(52) => mim_dll_brdata(52),
      doutb(51) => mim_dll_brdata(51),
      doutb(50) => mim_dll_brdata(50),
      doutb(49) => mim_dll_brdata(49),
      doutb(48) => mim_dll_brdata(48),
      doutb(47) => mim_dll_brdata(47),
      doutb(46) => mim_dll_brdata(46),
      doutb(45) => mim_dll_brdata(45),
      doutb(44) => mim_dll_brdata(44),
      doutb(43) => mim_dll_brdata(43),
      doutb(42) => mim_dll_brdata(42),
      doutb(41) => mim_dll_brdata(41),
      doutb(40) => mim_dll_brdata(40),
      doutb(39) => mim_dll_brdata(39),
      doutb(38) => mim_dll_brdata(38),
      doutb(37) => mim_dll_brdata(37),
      doutb(36) => mim_dll_brdata(36),
      doutb(35) => mim_dll_brdata(35),
      doutb(34) => mim_dll_brdata(34),
      doutb(33) => mim_dll_brdata(33),
      doutb(32) => mim_dll_brdata(32),
      doutb(31) => mim_dll_brdata(31),
      doutb(30) => mim_dll_brdata(30),
      doutb(29) => mim_dll_brdata(29),
      doutb(28) => mim_dll_brdata(28),
      doutb(27) => mim_dll_brdata(27),
      doutb(26) => mim_dll_brdata(26),
      doutb(25) => mim_dll_brdata(25),
      doutb(24) => mim_dll_brdata(24),
      doutb(23) => mim_dll_brdata(23),
      doutb(22) => mim_dll_brdata(22),
      doutb(21) => mim_dll_brdata(21),
      doutb(20) => mim_dll_brdata(20),
      doutb(19) => mim_dll_brdata(19),
      doutb(18) => mim_dll_brdata(18),
      doutb(17) => mim_dll_brdata(17),
      doutb(16) => mim_dll_brdata(16),
      doutb(15) => mim_dll_brdata(15),
      doutb(14) => mim_dll_brdata(14),
      doutb(13) => mim_dll_brdata(13),
      doutb(12) => mim_dll_brdata(12),
      doutb(11) => mim_dll_brdata(11),
      doutb(10) => mim_dll_brdata(10),
      doutb(9) => mim_dll_brdata(9),
      doutb(8) => mim_dll_brdata(8),
      doutb(7) => mim_dll_brdata(7),
      doutb(6) => mim_dll_brdata(6),
      doutb(5) => mim_dll_brdata(5),
      doutb(4) => mim_dll_brdata(4),
      doutb(3) => mim_dll_brdata(3),
      doutb(2) => mim_dll_brdata(2),
      doutb(1) => mim_dll_brdata(1),
      doutb(0) => mim_dll_brdata(0),
      addra(11) => mim_dll_bwadd(11),
      addra(10) => mim_dll_bwadd(10),
      addra(9) => mim_dll_bwadd(9),
      addra(8) => mim_dll_bwadd(8),
      addra(7) => mim_dll_bwadd(7),
      addra(6) => mim_dll_bwadd(6),
      addra(5) => mim_dll_bwadd(5),
      addra(4) => mim_dll_bwadd(4),
      addra(3) => mim_dll_bwadd(3),
      addra(2) => mim_dll_bwadd(2),
      addra(1) => mim_dll_bwadd(1),
      addra(0) => mim_dll_bwadd(0),
      addrb(11) => mim_dll_bradd(11),
      addrb(10) => mim_dll_bradd(10),
      addrb(9) => mim_dll_bradd(9),
      addrb(8) => mim_dll_bradd(8),
      addrb(7) => mim_dll_bradd(7),
      addrb(6) => mim_dll_bradd(6),
      addrb(5) => mim_dll_bradd(5),
      addrb(4) => mim_dll_bradd(4),
      addrb(3) => mim_dll_bradd(3),
      addrb(2) => mim_dll_bradd(2),
      addrb(1) => mim_dll_bradd(1),
      addrb(0) => mim_dll_bradd(0),
      dina(63) => mim_dll_bwdata(63),
      dina(62) => mim_dll_bwdata(62),
      dina(61) => mim_dll_bwdata(61),
      dina(60) => mim_dll_bwdata(60),
      dina(59) => mim_dll_bwdata(59),
      dina(58) => mim_dll_bwdata(58),
      dina(57) => mim_dll_bwdata(57),
      dina(56) => mim_dll_bwdata(56),
      dina(55) => mim_dll_bwdata(55),
      dina(54) => mim_dll_bwdata(54),
      dina(53) => mim_dll_bwdata(53),
      dina(52) => mim_dll_bwdata(52),
      dina(51) => mim_dll_bwdata(51),
      dina(50) => mim_dll_bwdata(50),
      dina(49) => mim_dll_bwdata(49),
      dina(48) => mim_dll_bwdata(48),
      dina(47) => mim_dll_bwdata(47),
      dina(46) => mim_dll_bwdata(46),
      dina(45) => mim_dll_bwdata(45),
      dina(44) => mim_dll_bwdata(44),
      dina(43) => mim_dll_bwdata(43),
      dina(42) => mim_dll_bwdata(42),
      dina(41) => mim_dll_bwdata(41),
      dina(40) => mim_dll_bwdata(40),
      dina(39) => mim_dll_bwdata(39),
      dina(38) => mim_dll_bwdata(38),
      dina(37) => mim_dll_bwdata(37),
      dina(36) => mim_dll_bwdata(36),
      dina(35) => mim_dll_bwdata(35),
      dina(34) => mim_dll_bwdata(34),
      dina(33) => mim_dll_bwdata(33),
      dina(32) => mim_dll_bwdata(32),
      dina(31) => mim_dll_bwdata(31),
      dina(30) => mim_dll_bwdata(30),
      dina(29) => mim_dll_bwdata(29),
      dina(28) => mim_dll_bwdata(28),
      dina(27) => mim_dll_bwdata(27),
      dina(26) => mim_dll_bwdata(26),
      dina(25) => mim_dll_bwdata(25),
      dina(24) => mim_dll_bwdata(24),
      dina(23) => mim_dll_bwdata(23),
      dina(22) => mim_dll_bwdata(22),
      dina(21) => mim_dll_bwdata(21),
      dina(20) => mim_dll_bwdata(20),
      dina(19) => mim_dll_bwdata(19),
      dina(18) => mim_dll_bwdata(18),
      dina(17) => mim_dll_bwdata(17),
      dina(16) => mim_dll_bwdata(16),
      dina(15) => mim_dll_bwdata(15),
      dina(14) => mim_dll_bwdata(14),
      dina(13) => mim_dll_bwdata(13),
      dina(12) => mim_dll_bwdata(12),
      dina(11) => mim_dll_bwdata(11),
      dina(10) => mim_dll_bwdata(10),
      dina(9) => mim_dll_bwdata(9),
      dina(8) => mim_dll_bwdata(8),
      dina(7) => mim_dll_bwdata(7),
      dina(6) => mim_dll_bwdata(6),
      dina(5) => mim_dll_bwdata(5),
      dina(4) => mim_dll_bwdata(4),
      dina(3) => mim_dll_bwdata(3),
      dina(2) => mim_dll_bwdata(2),
      dina(1) => mim_dll_bwdata(1),
      dina(0) => mim_dll_bwdata(0),
      dinb(63) => N0,
      dinb(62) => N0,
      dinb(61) => N0,
      dinb(60) => N0,
      dinb(59) => N0,
      dinb(58) => N0,
      dinb(57) => N0,
      dinb(56) => N0,
      dinb(55) => N0,
      dinb(54) => N0,
      dinb(53) => N0,
      dinb(52) => N0,
      dinb(51) => N0,
      dinb(50) => N0,
      dinb(49) => N0,
      dinb(48) => N0,
      dinb(47) => N0,
      dinb(46) => N0,
      dinb(45) => N0,
      dinb(44) => N0,
      dinb(43) => N0,
      dinb(42) => N0,
      dinb(41) => N0,
      dinb(40) => N0,
      dinb(39) => N0,
      dinb(38) => N0,
      dinb(37) => N0,
      dinb(36) => N0,
      dinb(35) => N0,
      dinb(34) => N0,
      dinb(33) => N0,
      dinb(32) => N0,
      dinb(31) => N0,
      dinb(30) => N0,
      dinb(29) => N0,
      dinb(28) => N0,
      dinb(27) => N0,
      dinb(26) => N0,
      dinb(25) => N0,
      dinb(24) => N0,
      dinb(23) => N0,
      dinb(22) => N0,
      dinb(21) => N0,
      dinb(20) => N0,
      dinb(19) => N0,
      dinb(18) => N0,
      dinb(17) => N0,
      dinb(16) => N0,
      dinb(15) => N0,
      dinb(14) => N0,
      dinb(13) => N0,
      dinb(12) => N0,
      dinb(11) => N0,
      dinb(10) => N0,
      dinb(9) => N0,
      dinb(8) => N0,
      dinb(7) => N0,
      dinb(6) => N0,
      dinb(5) => N0,
      dinb(4) => N0,
      dinb(3) => N0,
      dinb(2) => N0,
      dinb(1) => N0,
      dinb(0) => N0
    );
  bram_tl_rx : bram_common_2
    port map (
      ena => mim_rx_bwen,
      enb => mim_rx_bren,
      clka => mim_rx_bwclk,
      clkb => mim_rx_brclk,
      wena => mim_rx_bwen,
      wenb => NLW_bram_tl_rx_wenb_UNCONNECTED,
      douta(63) => NLW_bram_tl_rx_douta_63_UNCONNECTED,
      douta(62) => NLW_bram_tl_rx_douta_62_UNCONNECTED,
      douta(61) => NLW_bram_tl_rx_douta_61_UNCONNECTED,
      douta(60) => NLW_bram_tl_rx_douta_60_UNCONNECTED,
      douta(59) => NLW_bram_tl_rx_douta_59_UNCONNECTED,
      douta(58) => NLW_bram_tl_rx_douta_58_UNCONNECTED,
      douta(57) => NLW_bram_tl_rx_douta_57_UNCONNECTED,
      douta(56) => NLW_bram_tl_rx_douta_56_UNCONNECTED,
      douta(55) => NLW_bram_tl_rx_douta_55_UNCONNECTED,
      douta(54) => NLW_bram_tl_rx_douta_54_UNCONNECTED,
      douta(53) => NLW_bram_tl_rx_douta_53_UNCONNECTED,
      douta(52) => NLW_bram_tl_rx_douta_52_UNCONNECTED,
      douta(51) => NLW_bram_tl_rx_douta_51_UNCONNECTED,
      douta(50) => NLW_bram_tl_rx_douta_50_UNCONNECTED,
      douta(49) => NLW_bram_tl_rx_douta_49_UNCONNECTED,
      douta(48) => NLW_bram_tl_rx_douta_48_UNCONNECTED,
      douta(47) => NLW_bram_tl_rx_douta_47_UNCONNECTED,
      douta(46) => NLW_bram_tl_rx_douta_46_UNCONNECTED,
      douta(45) => NLW_bram_tl_rx_douta_45_UNCONNECTED,
      douta(44) => NLW_bram_tl_rx_douta_44_UNCONNECTED,
      douta(43) => NLW_bram_tl_rx_douta_43_UNCONNECTED,
      douta(42) => NLW_bram_tl_rx_douta_42_UNCONNECTED,
      douta(41) => NLW_bram_tl_rx_douta_41_UNCONNECTED,
      douta(40) => NLW_bram_tl_rx_douta_40_UNCONNECTED,
      douta(39) => NLW_bram_tl_rx_douta_39_UNCONNECTED,
      douta(38) => NLW_bram_tl_rx_douta_38_UNCONNECTED,
      douta(37) => NLW_bram_tl_rx_douta_37_UNCONNECTED,
      douta(36) => NLW_bram_tl_rx_douta_36_UNCONNECTED,
      douta(35) => NLW_bram_tl_rx_douta_35_UNCONNECTED,
      douta(34) => NLW_bram_tl_rx_douta_34_UNCONNECTED,
      douta(33) => NLW_bram_tl_rx_douta_33_UNCONNECTED,
      douta(32) => NLW_bram_tl_rx_douta_32_UNCONNECTED,
      douta(31) => NLW_bram_tl_rx_douta_31_UNCONNECTED,
      douta(30) => NLW_bram_tl_rx_douta_30_UNCONNECTED,
      douta(29) => NLW_bram_tl_rx_douta_29_UNCONNECTED,
      douta(28) => NLW_bram_tl_rx_douta_28_UNCONNECTED,
      douta(27) => NLW_bram_tl_rx_douta_27_UNCONNECTED,
      douta(26) => NLW_bram_tl_rx_douta_26_UNCONNECTED,
      douta(25) => NLW_bram_tl_rx_douta_25_UNCONNECTED,
      douta(24) => NLW_bram_tl_rx_douta_24_UNCONNECTED,
      douta(23) => NLW_bram_tl_rx_douta_23_UNCONNECTED,
      douta(22) => NLW_bram_tl_rx_douta_22_UNCONNECTED,
      douta(21) => NLW_bram_tl_rx_douta_21_UNCONNECTED,
      douta(20) => NLW_bram_tl_rx_douta_20_UNCONNECTED,
      douta(19) => NLW_bram_tl_rx_douta_19_UNCONNECTED,
      douta(18) => NLW_bram_tl_rx_douta_18_UNCONNECTED,
      douta(17) => NLW_bram_tl_rx_douta_17_UNCONNECTED,
      douta(16) => NLW_bram_tl_rx_douta_16_UNCONNECTED,
      douta(15) => NLW_bram_tl_rx_douta_15_UNCONNECTED,
      douta(14) => NLW_bram_tl_rx_douta_14_UNCONNECTED,
      douta(13) => NLW_bram_tl_rx_douta_13_UNCONNECTED,
      douta(12) => NLW_bram_tl_rx_douta_12_UNCONNECTED,
      douta(11) => NLW_bram_tl_rx_douta_11_UNCONNECTED,
      douta(10) => NLW_bram_tl_rx_douta_10_UNCONNECTED,
      douta(9) => NLW_bram_tl_rx_douta_9_UNCONNECTED,
      douta(8) => NLW_bram_tl_rx_douta_8_UNCONNECTED,
      douta(7) => NLW_bram_tl_rx_douta_7_UNCONNECTED,
      douta(6) => NLW_bram_tl_rx_douta_6_UNCONNECTED,
      douta(5) => NLW_bram_tl_rx_douta_5_UNCONNECTED,
      douta(4) => NLW_bram_tl_rx_douta_4_UNCONNECTED,
      douta(3) => NLW_bram_tl_rx_douta_3_UNCONNECTED,
      douta(2) => NLW_bram_tl_rx_douta_2_UNCONNECTED,
      douta(1) => NLW_bram_tl_rx_douta_1_UNCONNECTED,
      douta(0) => NLW_bram_tl_rx_douta_0_UNCONNECTED,
      doutb(63) => mim_rx_brdata(63),
      doutb(62) => mim_rx_brdata(62),
      doutb(61) => mim_rx_brdata(61),
      doutb(60) => mim_rx_brdata(60),
      doutb(59) => mim_rx_brdata(59),
      doutb(58) => mim_rx_brdata(58),
      doutb(57) => mim_rx_brdata(57),
      doutb(56) => mim_rx_brdata(56),
      doutb(55) => mim_rx_brdata(55),
      doutb(54) => mim_rx_brdata(54),
      doutb(53) => mim_rx_brdata(53),
      doutb(52) => mim_rx_brdata(52),
      doutb(51) => mim_rx_brdata(51),
      doutb(50) => mim_rx_brdata(50),
      doutb(49) => mim_rx_brdata(49),
      doutb(48) => mim_rx_brdata(48),
      doutb(47) => mim_rx_brdata(47),
      doutb(46) => mim_rx_brdata(46),
      doutb(45) => mim_rx_brdata(45),
      doutb(44) => mim_rx_brdata(44),
      doutb(43) => mim_rx_brdata(43),
      doutb(42) => mim_rx_brdata(42),
      doutb(41) => mim_rx_brdata(41),
      doutb(40) => mim_rx_brdata(40),
      doutb(39) => mim_rx_brdata(39),
      doutb(38) => mim_rx_brdata(38),
      doutb(37) => mim_rx_brdata(37),
      doutb(36) => mim_rx_brdata(36),
      doutb(35) => mim_rx_brdata(35),
      doutb(34) => mim_rx_brdata(34),
      doutb(33) => mim_rx_brdata(33),
      doutb(32) => mim_rx_brdata(32),
      doutb(31) => mim_rx_brdata(31),
      doutb(30) => mim_rx_brdata(30),
      doutb(29) => mim_rx_brdata(29),
      doutb(28) => mim_rx_brdata(28),
      doutb(27) => mim_rx_brdata(27),
      doutb(26) => mim_rx_brdata(26),
      doutb(25) => mim_rx_brdata(25),
      doutb(24) => mim_rx_brdata(24),
      doutb(23) => mim_rx_brdata(23),
      doutb(22) => mim_rx_brdata(22),
      doutb(21) => mim_rx_brdata(21),
      doutb(20) => mim_rx_brdata(20),
      doutb(19) => mim_rx_brdata(19),
      doutb(18) => mim_rx_brdata(18),
      doutb(17) => mim_rx_brdata(17),
      doutb(16) => mim_rx_brdata(16),
      doutb(15) => mim_rx_brdata(15),
      doutb(14) => mim_rx_brdata(14),
      doutb(13) => mim_rx_brdata(13),
      doutb(12) => mim_rx_brdata(12),
      doutb(11) => mim_rx_brdata(11),
      doutb(10) => mim_rx_brdata(10),
      doutb(9) => mim_rx_brdata(9),
      doutb(8) => mim_rx_brdata(8),
      doutb(7) => mim_rx_brdata(7),
      doutb(6) => mim_rx_brdata(6),
      doutb(5) => mim_rx_brdata(5),
      doutb(4) => mim_rx_brdata(4),
      doutb(3) => mim_rx_brdata(3),
      doutb(2) => mim_rx_brdata(2),
      doutb(1) => mim_rx_brdata(1),
      doutb(0) => mim_rx_brdata(0),
      addra(12) => mim_rx_bwadd(12),
      addra(11) => mim_rx_bwadd(11),
      addra(10) => mim_rx_bwadd(10),
      addra(9) => mim_rx_bwadd(9),
      addra(8) => mim_rx_bwadd(8),
      addra(7) => mim_rx_bwadd(7),
      addra(6) => mim_rx_bwadd(6),
      addra(5) => mim_rx_bwadd(5),
      addra(4) => mim_rx_bwadd(4),
      addra(3) => mim_rx_bwadd(3),
      addra(2) => mim_rx_bwadd(2),
      addra(1) => mim_rx_bwadd(1),
      addra(0) => mim_rx_bwadd(0),
      addrb(12) => mim_rx_bradd(12),
      addrb(11) => mim_rx_bradd(11),
      addrb(10) => mim_rx_bradd(10),
      addrb(9) => mim_rx_bradd(9),
      addrb(8) => mim_rx_bradd(8),
      addrb(7) => mim_rx_bradd(7),
      addrb(6) => mim_rx_bradd(6),
      addrb(5) => mim_rx_bradd(5),
      addrb(4) => mim_rx_bradd(4),
      addrb(3) => mim_rx_bradd(3),
      addrb(2) => mim_rx_bradd(2),
      addrb(1) => mim_rx_bradd(1),
      addrb(0) => mim_rx_bradd(0),
      dina(63) => mim_rx_bwdata(63),
      dina(62) => mim_rx_bwdata(62),
      dina(61) => mim_rx_bwdata(61),
      dina(60) => mim_rx_bwdata(60),
      dina(59) => mim_rx_bwdata(59),
      dina(58) => mim_rx_bwdata(58),
      dina(57) => mim_rx_bwdata(57),
      dina(56) => mim_rx_bwdata(56),
      dina(55) => mim_rx_bwdata(55),
      dina(54) => mim_rx_bwdata(54),
      dina(53) => mim_rx_bwdata(53),
      dina(52) => mim_rx_bwdata(52),
      dina(51) => mim_rx_bwdata(51),
      dina(50) => mim_rx_bwdata(50),
      dina(49) => mim_rx_bwdata(49),
      dina(48) => mim_rx_bwdata(48),
      dina(47) => mim_rx_bwdata(47),
      dina(46) => mim_rx_bwdata(46),
      dina(45) => mim_rx_bwdata(45),
      dina(44) => mim_rx_bwdata(44),
      dina(43) => mim_rx_bwdata(43),
      dina(42) => mim_rx_bwdata(42),
      dina(41) => mim_rx_bwdata(41),
      dina(40) => mim_rx_bwdata(40),
      dina(39) => mim_rx_bwdata(39),
      dina(38) => mim_rx_bwdata(38),
      dina(37) => mim_rx_bwdata(37),
      dina(36) => mim_rx_bwdata(36),
      dina(35) => mim_rx_bwdata(35),
      dina(34) => mim_rx_bwdata(34),
      dina(33) => mim_rx_bwdata(33),
      dina(32) => mim_rx_bwdata(32),
      dina(31) => mim_rx_bwdata(31),
      dina(30) => mim_rx_bwdata(30),
      dina(29) => mim_rx_bwdata(29),
      dina(28) => mim_rx_bwdata(28),
      dina(27) => mim_rx_bwdata(27),
      dina(26) => mim_rx_bwdata(26),
      dina(25) => mim_rx_bwdata(25),
      dina(24) => mim_rx_bwdata(24),
      dina(23) => mim_rx_bwdata(23),
      dina(22) => mim_rx_bwdata(22),
      dina(21) => mim_rx_bwdata(21),
      dina(20) => mim_rx_bwdata(20),
      dina(19) => mim_rx_bwdata(19),
      dina(18) => mim_rx_bwdata(18),
      dina(17) => mim_rx_bwdata(17),
      dina(16) => mim_rx_bwdata(16),
      dina(15) => mim_rx_bwdata(15),
      dina(14) => mim_rx_bwdata(14),
      dina(13) => mim_rx_bwdata(13),
      dina(12) => mim_rx_bwdata(12),
      dina(11) => mim_rx_bwdata(11),
      dina(10) => mim_rx_bwdata(10),
      dina(9) => mim_rx_bwdata(9),
      dina(8) => mim_rx_bwdata(8),
      dina(7) => mim_rx_bwdata(7),
      dina(6) => mim_rx_bwdata(6),
      dina(5) => mim_rx_bwdata(5),
      dina(4) => mim_rx_bwdata(4),
      dina(3) => mim_rx_bwdata(3),
      dina(2) => mim_rx_bwdata(2),
      dina(1) => mim_rx_bwdata(1),
      dina(0) => mim_rx_bwdata(0),
      dinb(63) => N0,
      dinb(62) => N0,
      dinb(61) => N0,
      dinb(60) => N0,
      dinb(59) => N0,
      dinb(58) => N0,
      dinb(57) => N0,
      dinb(56) => N0,
      dinb(55) => N0,
      dinb(54) => N0,
      dinb(53) => N0,
      dinb(52) => N0,
      dinb(51) => N0,
      dinb(50) => N0,
      dinb(49) => N0,
      dinb(48) => N0,
      dinb(47) => N0,
      dinb(46) => N0,
      dinb(45) => N0,
      dinb(44) => N0,
      dinb(43) => N0,
      dinb(42) => N0,
      dinb(41) => N0,
      dinb(40) => N0,
      dinb(39) => N0,
      dinb(38) => N0,
      dinb(37) => N0,
      dinb(36) => N0,
      dinb(35) => N0,
      dinb(34) => N0,
      dinb(33) => N0,
      dinb(32) => N0,
      dinb(31) => N0,
      dinb(30) => N0,
      dinb(29) => N0,
      dinb(28) => N0,
      dinb(27) => N0,
      dinb(26) => N0,
      dinb(25) => N0,
      dinb(24) => N0,
      dinb(23) => N0,
      dinb(22) => N0,
      dinb(21) => N0,
      dinb(20) => N0,
      dinb(19) => N0,
      dinb(18) => N0,
      dinb(17) => N0,
      dinb(16) => N0,
      dinb(15) => N0,
      dinb(14) => N0,
      dinb(13) => N0,
      dinb(12) => N0,
      dinb(11) => N0,
      dinb(10) => N0,
      dinb(9) => N0,
      dinb(8) => N0,
      dinb(7) => N0,
      dinb(6) => N0,
      dinb(5) => N0,
      dinb(4) => N0,
      dinb(3) => N0,
      dinb(2) => N0,
      dinb(1) => N0,
      dinb(0) => N0
    );
  bram_tl_tx : bram_common_2_INST_1
    port map (
      ena => mim_tx_bwen,
      enb => mim_tx_bren,
      clka => mim_tx_bwclk,
      clkb => mim_tx_brclk,
      wena => mim_tx_bwen,
      wenb => NLW_bram_tl_tx_wenb_UNCONNECTED,
      douta(63) => NLW_bram_tl_tx_douta_63_UNCONNECTED,
      douta(62) => NLW_bram_tl_tx_douta_62_UNCONNECTED,
      douta(61) => NLW_bram_tl_tx_douta_61_UNCONNECTED,
      douta(60) => NLW_bram_tl_tx_douta_60_UNCONNECTED,
      douta(59) => NLW_bram_tl_tx_douta_59_UNCONNECTED,
      douta(58) => NLW_bram_tl_tx_douta_58_UNCONNECTED,
      douta(57) => NLW_bram_tl_tx_douta_57_UNCONNECTED,
      douta(56) => NLW_bram_tl_tx_douta_56_UNCONNECTED,
      douta(55) => NLW_bram_tl_tx_douta_55_UNCONNECTED,
      douta(54) => NLW_bram_tl_tx_douta_54_UNCONNECTED,
      douta(53) => NLW_bram_tl_tx_douta_53_UNCONNECTED,
      douta(52) => NLW_bram_tl_tx_douta_52_UNCONNECTED,
      douta(51) => NLW_bram_tl_tx_douta_51_UNCONNECTED,
      douta(50) => NLW_bram_tl_tx_douta_50_UNCONNECTED,
      douta(49) => NLW_bram_tl_tx_douta_49_UNCONNECTED,
      douta(48) => NLW_bram_tl_tx_douta_48_UNCONNECTED,
      douta(47) => NLW_bram_tl_tx_douta_47_UNCONNECTED,
      douta(46) => NLW_bram_tl_tx_douta_46_UNCONNECTED,
      douta(45) => NLW_bram_tl_tx_douta_45_UNCONNECTED,
      douta(44) => NLW_bram_tl_tx_douta_44_UNCONNECTED,
      douta(43) => NLW_bram_tl_tx_douta_43_UNCONNECTED,
      douta(42) => NLW_bram_tl_tx_douta_42_UNCONNECTED,
      douta(41) => NLW_bram_tl_tx_douta_41_UNCONNECTED,
      douta(40) => NLW_bram_tl_tx_douta_40_UNCONNECTED,
      douta(39) => NLW_bram_tl_tx_douta_39_UNCONNECTED,
      douta(38) => NLW_bram_tl_tx_douta_38_UNCONNECTED,
      douta(37) => NLW_bram_tl_tx_douta_37_UNCONNECTED,
      douta(36) => NLW_bram_tl_tx_douta_36_UNCONNECTED,
      douta(35) => NLW_bram_tl_tx_douta_35_UNCONNECTED,
      douta(34) => NLW_bram_tl_tx_douta_34_UNCONNECTED,
      douta(33) => NLW_bram_tl_tx_douta_33_UNCONNECTED,
      douta(32) => NLW_bram_tl_tx_douta_32_UNCONNECTED,
      douta(31) => NLW_bram_tl_tx_douta_31_UNCONNECTED,
      douta(30) => NLW_bram_tl_tx_douta_30_UNCONNECTED,
      douta(29) => NLW_bram_tl_tx_douta_29_UNCONNECTED,
      douta(28) => NLW_bram_tl_tx_douta_28_UNCONNECTED,
      douta(27) => NLW_bram_tl_tx_douta_27_UNCONNECTED,
      douta(26) => NLW_bram_tl_tx_douta_26_UNCONNECTED,
      douta(25) => NLW_bram_tl_tx_douta_25_UNCONNECTED,
      douta(24) => NLW_bram_tl_tx_douta_24_UNCONNECTED,
      douta(23) => NLW_bram_tl_tx_douta_23_UNCONNECTED,
      douta(22) => NLW_bram_tl_tx_douta_22_UNCONNECTED,
      douta(21) => NLW_bram_tl_tx_douta_21_UNCONNECTED,
      douta(20) => NLW_bram_tl_tx_douta_20_UNCONNECTED,
      douta(19) => NLW_bram_tl_tx_douta_19_UNCONNECTED,
      douta(18) => NLW_bram_tl_tx_douta_18_UNCONNECTED,
      douta(17) => NLW_bram_tl_tx_douta_17_UNCONNECTED,
      douta(16) => NLW_bram_tl_tx_douta_16_UNCONNECTED,
      douta(15) => NLW_bram_tl_tx_douta_15_UNCONNECTED,
      douta(14) => NLW_bram_tl_tx_douta_14_UNCONNECTED,
      douta(13) => NLW_bram_tl_tx_douta_13_UNCONNECTED,
      douta(12) => NLW_bram_tl_tx_douta_12_UNCONNECTED,
      douta(11) => NLW_bram_tl_tx_douta_11_UNCONNECTED,
      douta(10) => NLW_bram_tl_tx_douta_10_UNCONNECTED,
      douta(9) => NLW_bram_tl_tx_douta_9_UNCONNECTED,
      douta(8) => NLW_bram_tl_tx_douta_8_UNCONNECTED,
      douta(7) => NLW_bram_tl_tx_douta_7_UNCONNECTED,
      douta(6) => NLW_bram_tl_tx_douta_6_UNCONNECTED,
      douta(5) => NLW_bram_tl_tx_douta_5_UNCONNECTED,
      douta(4) => NLW_bram_tl_tx_douta_4_UNCONNECTED,
      douta(3) => NLW_bram_tl_tx_douta_3_UNCONNECTED,
      douta(2) => NLW_bram_tl_tx_douta_2_UNCONNECTED,
      douta(1) => NLW_bram_tl_tx_douta_1_UNCONNECTED,
      douta(0) => NLW_bram_tl_tx_douta_0_UNCONNECTED,
      doutb(63) => mim_tx_brdata(63),
      doutb(62) => mim_tx_brdata(62),
      doutb(61) => mim_tx_brdata(61),
      doutb(60) => mim_tx_brdata(60),
      doutb(59) => mim_tx_brdata(59),
      doutb(58) => mim_tx_brdata(58),
      doutb(57) => mim_tx_brdata(57),
      doutb(56) => mim_tx_brdata(56),
      doutb(55) => mim_tx_brdata(55),
      doutb(54) => mim_tx_brdata(54),
      doutb(53) => mim_tx_brdata(53),
      doutb(52) => mim_tx_brdata(52),
      doutb(51) => mim_tx_brdata(51),
      doutb(50) => mim_tx_brdata(50),
      doutb(49) => mim_tx_brdata(49),
      doutb(48) => mim_tx_brdata(48),
      doutb(47) => mim_tx_brdata(47),
      doutb(46) => mim_tx_brdata(46),
      doutb(45) => mim_tx_brdata(45),
      doutb(44) => mim_tx_brdata(44),
      doutb(43) => mim_tx_brdata(43),
      doutb(42) => mim_tx_brdata(42),
      doutb(41) => mim_tx_brdata(41),
      doutb(40) => mim_tx_brdata(40),
      doutb(39) => mim_tx_brdata(39),
      doutb(38) => mim_tx_brdata(38),
      doutb(37) => mim_tx_brdata(37),
      doutb(36) => mim_tx_brdata(36),
      doutb(35) => mim_tx_brdata(35),
      doutb(34) => mim_tx_brdata(34),
      doutb(33) => mim_tx_brdata(33),
      doutb(32) => mim_tx_brdata(32),
      doutb(31) => mim_tx_brdata(31),
      doutb(30) => mim_tx_brdata(30),
      doutb(29) => mim_tx_brdata(29),
      doutb(28) => mim_tx_brdata(28),
      doutb(27) => mim_tx_brdata(27),
      doutb(26) => mim_tx_brdata(26),
      doutb(25) => mim_tx_brdata(25),
      doutb(24) => mim_tx_brdata(24),
      doutb(23) => mim_tx_brdata(23),
      doutb(22) => mim_tx_brdata(22),
      doutb(21) => mim_tx_brdata(21),
      doutb(20) => mim_tx_brdata(20),
      doutb(19) => mim_tx_brdata(19),
      doutb(18) => mim_tx_brdata(18),
      doutb(17) => mim_tx_brdata(17),
      doutb(16) => mim_tx_brdata(16),
      doutb(15) => mim_tx_brdata(15),
      doutb(14) => mim_tx_brdata(14),
      doutb(13) => mim_tx_brdata(13),
      doutb(12) => mim_tx_brdata(12),
      doutb(11) => mim_tx_brdata(11),
      doutb(10) => mim_tx_brdata(10),
      doutb(9) => mim_tx_brdata(9),
      doutb(8) => mim_tx_brdata(8),
      doutb(7) => mim_tx_brdata(7),
      doutb(6) => mim_tx_brdata(6),
      doutb(5) => mim_tx_brdata(5),
      doutb(4) => mim_tx_brdata(4),
      doutb(3) => mim_tx_brdata(3),
      doutb(2) => mim_tx_brdata(2),
      doutb(1) => mim_tx_brdata(1),
      doutb(0) => mim_tx_brdata(0),
      addra(12) => mim_tx_bwadd(12),
      addra(11) => mim_tx_bwadd(11),
      addra(10) => mim_tx_bwadd(10),
      addra(9) => mim_tx_bwadd(9),
      addra(8) => mim_tx_bwadd(8),
      addra(7) => mim_tx_bwadd(7),
      addra(6) => mim_tx_bwadd(6),
      addra(5) => mim_tx_bwadd(5),
      addra(4) => mim_tx_bwadd(4),
      addra(3) => mim_tx_bwadd(3),
      addra(2) => mim_tx_bwadd(2),
      addra(1) => mim_tx_bwadd(1),
      addra(0) => mim_tx_bwadd(0),
      addrb(12) => mim_tx_bradd(12),
      addrb(11) => mim_tx_bradd(11),
      addrb(10) => mim_tx_bradd(10),
      addrb(9) => mim_tx_bradd(9),
      addrb(8) => mim_tx_bradd(8),
      addrb(7) => mim_tx_bradd(7),
      addrb(6) => mim_tx_bradd(6),
      addrb(5) => mim_tx_bradd(5),
      addrb(4) => mim_tx_bradd(4),
      addrb(3) => mim_tx_bradd(3),
      addrb(2) => mim_tx_bradd(2),
      addrb(1) => mim_tx_bradd(1),
      addrb(0) => mim_tx_bradd(0),
      dina(63) => mim_tx_bwdata(63),
      dina(62) => mim_tx_bwdata(62),
      dina(61) => mim_tx_bwdata(61),
      dina(60) => mim_tx_bwdata(60),
      dina(59) => mim_tx_bwdata(59),
      dina(58) => mim_tx_bwdata(58),
      dina(57) => mim_tx_bwdata(57),
      dina(56) => mim_tx_bwdata(56),
      dina(55) => mim_tx_bwdata(55),
      dina(54) => mim_tx_bwdata(54),
      dina(53) => mim_tx_bwdata(53),
      dina(52) => mim_tx_bwdata(52),
      dina(51) => mim_tx_bwdata(51),
      dina(50) => mim_tx_bwdata(50),
      dina(49) => mim_tx_bwdata(49),
      dina(48) => mim_tx_bwdata(48),
      dina(47) => mim_tx_bwdata(47),
      dina(46) => mim_tx_bwdata(46),
      dina(45) => mim_tx_bwdata(45),
      dina(44) => mim_tx_bwdata(44),
      dina(43) => mim_tx_bwdata(43),
      dina(42) => mim_tx_bwdata(42),
      dina(41) => mim_tx_bwdata(41),
      dina(40) => mim_tx_bwdata(40),
      dina(39) => mim_tx_bwdata(39),
      dina(38) => mim_tx_bwdata(38),
      dina(37) => mim_tx_bwdata(37),
      dina(36) => mim_tx_bwdata(36),
      dina(35) => mim_tx_bwdata(35),
      dina(34) => mim_tx_bwdata(34),
      dina(33) => mim_tx_bwdata(33),
      dina(32) => mim_tx_bwdata(32),
      dina(31) => mim_tx_bwdata(31),
      dina(30) => mim_tx_bwdata(30),
      dina(29) => mim_tx_bwdata(29),
      dina(28) => mim_tx_bwdata(28),
      dina(27) => mim_tx_bwdata(27),
      dina(26) => mim_tx_bwdata(26),
      dina(25) => mim_tx_bwdata(25),
      dina(24) => mim_tx_bwdata(24),
      dina(23) => mim_tx_bwdata(23),
      dina(22) => mim_tx_bwdata(22),
      dina(21) => mim_tx_bwdata(21),
      dina(20) => mim_tx_bwdata(20),
      dina(19) => mim_tx_bwdata(19),
      dina(18) => mim_tx_bwdata(18),
      dina(17) => mim_tx_bwdata(17),
      dina(16) => mim_tx_bwdata(16),
      dina(15) => mim_tx_bwdata(15),
      dina(14) => mim_tx_bwdata(14),
      dina(13) => mim_tx_bwdata(13),
      dina(12) => mim_tx_bwdata(12),
      dina(11) => mim_tx_bwdata(11),
      dina(10) => mim_tx_bwdata(10),
      dina(9) => mim_tx_bwdata(9),
      dina(8) => mim_tx_bwdata(8),
      dina(7) => mim_tx_bwdata(7),
      dina(6) => mim_tx_bwdata(6),
      dina(5) => mim_tx_bwdata(5),
      dina(4) => mim_tx_bwdata(4),
      dina(3) => mim_tx_bwdata(3),
      dina(2) => mim_tx_bwdata(2),
      dina(1) => mim_tx_bwdata(1),
      dina(0) => mim_tx_bwdata(0),
      dinb(63) => N0,
      dinb(62) => N0,
      dinb(61) => N0,
      dinb(60) => N0,
      dinb(59) => N0,
      dinb(58) => N0,
      dinb(57) => N0,
      dinb(56) => N0,
      dinb(55) => N0,
      dinb(54) => N0,
      dinb(53) => N0,
      dinb(52) => N0,
      dinb(51) => N0,
      dinb(50) => N0,
      dinb(49) => N0,
      dinb(48) => N0,
      dinb(47) => N0,
      dinb(46) => N0,
      dinb(45) => N0,
      dinb(44) => N0,
      dinb(43) => N0,
      dinb(42) => N0,
      dinb(41) => N0,
      dinb(40) => N0,
      dinb(39) => N0,
      dinb(38) => N0,
      dinb(37) => N0,
      dinb(36) => N0,
      dinb(35) => N0,
      dinb(34) => N0,
      dinb(33) => N0,
      dinb(32) => N0,
      dinb(31) => N0,
      dinb(30) => N0,
      dinb(29) => N0,
      dinb(28) => N0,
      dinb(27) => N0,
      dinb(26) => N0,
      dinb(25) => N0,
      dinb(24) => N0,
      dinb(23) => N0,
      dinb(22) => N0,
      dinb(21) => N0,
      dinb(20) => N0,
      dinb(19) => N0,
      dinb(18) => N0,
      dinb(17) => N0,
      dinb(16) => N0,
      dinb(15) => N0,
      dinb(14) => N0,
      dinb(13) => N0,
      dinb(12) => N0,
      dinb(11) => N0,
      dinb(10) => N0,
      dinb(9) => N0,
      dinb(8) => N0,
      dinb(7) => N0,
      dinb(6) => N0,
      dinb(5) => N0,
      dinb(4) => N0,
      dinb(3) => N0,
      dinb(2) => N0,
      dinb(1) => N0,
      dinb(0) => N0
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_clocking is
  port (
    gtx_usrclk : out STD_LOGIC; 
    txsync_clk : out STD_LOGIC; 
    rst : in STD_LOGIC := 'X'; 
    clkin_pll : in STD_LOGIC := 'X'; 
    fast_train_simulation_only : in STD_LOGIC := 'X'; 
    coreclk : out STD_LOGIC; 
    locked : out STD_LOGIC; 
    clkin_dcm : in STD_LOGIC := 'X'; 
    userclk : out STD_LOGIC 
  );
end pcie_clocking;

architecture STRUCTURE of pcie_clocking is
  signal Mcount_lock_wait_cntr_15_8_cy_1_rt_14039 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy_2_rt_14041 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy_3_rt_14043 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy_4_rt_14045 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy_5_rt_14047 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy_6_rt_14049 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_xor_7_rt_14051 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_1_rt_14054 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_2_rt_14056 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_3_rt_14058 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_4_rt_14060 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_5_rt_14062 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_cy_6_rt_14064 : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_7_0_xor_7_rt_14066 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal clkfbout : STD_LOGIC; 
  signal clkout0 : STD_LOGIC; 
  signal clkout2 : STD_LOGIC; 
  signal lock_wait_cntr_15_8_not0001_14102 : STD_LOGIC; 
  signal lock_wait_cntr_7_0_not0001 : STD_LOGIC; 
  signal pll_locked_out_r_14112 : STD_LOGIC; 
  signal pll_locked_out_r_2d_14113 : STD_LOGIC; 
  signal pll_locked_out_r_d_14114 : STD_LOGIC; 
  signal pll_locked_out_r_or0000_14115 : STD_LOGIC; 
  signal time_elapsed_14117 : STD_LOGIC; 
  signal txsync_clkout : STD_LOGIC; 
  signal use_pll_pll_lk_out : STD_LOGIC; 
  signal NlwRenamedSig_OI_userclk : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKIN2_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DWE_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DEN_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DCLK_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_REL_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUT1_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUT4_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUT5_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM0_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM1_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM2_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM3_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM4_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKOUTDCM5_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_CLKFBDCM_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DRDY_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DADDR_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DADDR_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DADDR_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DADDR_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DADDR_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DI_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_use_pll_pll_adv_i_DO_0_UNCONNECTED : STD_LOGIC; 
  signal Mcount_lock_wait_cntr_15_8_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcount_lock_wait_cntr_15_8_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_lock_wait_cntr_7_0_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcount_lock_wait_cntr_7_0_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal lock_wait_cntr_15_8 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal lock_wait_cntr_7_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  coreclk <= NlwRenamedSig_OI_userclk;
  locked <= pll_locked_out_r_2d_14113;
  userclk <= NlwRenamedSig_OI_userclk;
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  time_elapsed : FDCE
    port map (
      C => clkin_pll,
      CE => pll_locked_out_r_or0000_14115,
      CLR => rst,
      D => N1,
      Q => time_elapsed_14117
    );
  pll_locked_out_r : FDCE
    port map (
      C => clkin_pll,
      CE => pll_locked_out_r_or0000_14115,
      CLR => rst,
      D => use_pll_pll_lk_out,
      Q => pll_locked_out_r_14112
    );
  pll_locked_out_r_d : FDC
    port map (
      C => NlwRenamedSig_OI_userclk,
      CLR => rst,
      D => pll_locked_out_r_14112,
      Q => pll_locked_out_r_d_14114
    );
  pll_locked_out_r_2d : FDC
    port map (
      C => NlwRenamedSig_OI_userclk,
      CLR => rst,
      D => pll_locked_out_r_d_14114,
      Q => pll_locked_out_r_2d_14113
    );
  lock_wait_cntr_15_8_0 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(0),
      Q => lock_wait_cntr_15_8(0)
    );
  lock_wait_cntr_15_8_1 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(1),
      Q => lock_wait_cntr_15_8(1)
    );
  lock_wait_cntr_15_8_2 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(2),
      Q => lock_wait_cntr_15_8(2)
    );
  lock_wait_cntr_15_8_3 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(3),
      Q => lock_wait_cntr_15_8(3)
    );
  lock_wait_cntr_15_8_4 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(4),
      Q => lock_wait_cntr_15_8(4)
    );
  lock_wait_cntr_15_8_5 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(5),
      Q => lock_wait_cntr_15_8(5)
    );
  lock_wait_cntr_15_8_6 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(6),
      Q => lock_wait_cntr_15_8(6)
    );
  lock_wait_cntr_15_8_7 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_15_8_not0001_14102,
      CLR => rst,
      D => Result(7),
      Q => lock_wait_cntr_15_8(7)
    );
  lock_wait_cntr_7_0_0 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_0_1,
      Q => lock_wait_cntr_7_0(0)
    );
  lock_wait_cntr_7_0_1 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_1_1,
      Q => lock_wait_cntr_7_0(1)
    );
  lock_wait_cntr_7_0_2 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_2_1,
      Q => lock_wait_cntr_7_0(2)
    );
  lock_wait_cntr_7_0_3 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_3_1,
      Q => lock_wait_cntr_7_0(3)
    );
  lock_wait_cntr_7_0_4 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_4_1,
      Q => lock_wait_cntr_7_0(4)
    );
  lock_wait_cntr_7_0_5 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_5_1,
      Q => lock_wait_cntr_7_0(5)
    );
  lock_wait_cntr_7_0_6 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_6_1,
      Q => lock_wait_cntr_7_0(6)
    );
  lock_wait_cntr_7_0_7 : FDCE
    port map (
      C => clkin_pll,
      CE => lock_wait_cntr_7_0_not0001,
      CLR => rst,
      D => Result_7_1,
      Q => lock_wait_cntr_7_0(7)
    );
  Mcount_lock_wait_cntr_7_0_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_lock_wait_cntr_7_0_lut(0),
      O => Mcount_lock_wait_cntr_7_0_cy(0)
    );
  Mcount_lock_wait_cntr_7_0_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_lock_wait_cntr_7_0_lut(0),
      O => Result_0_1
    );
  Mcount_lock_wait_cntr_7_0_cy_1_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(0),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_1_rt_14054,
      O => Mcount_lock_wait_cntr_7_0_cy(1)
    );
  Mcount_lock_wait_cntr_7_0_xor_1_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(0),
      LI => Mcount_lock_wait_cntr_7_0_cy_1_rt_14054,
      O => Result_1_1
    );
  Mcount_lock_wait_cntr_7_0_cy_2_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(1),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_2_rt_14056,
      O => Mcount_lock_wait_cntr_7_0_cy(2)
    );
  Mcount_lock_wait_cntr_7_0_xor_2_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(1),
      LI => Mcount_lock_wait_cntr_7_0_cy_2_rt_14056,
      O => Result_2_1
    );
  Mcount_lock_wait_cntr_7_0_cy_3_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(2),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_3_rt_14058,
      O => Mcount_lock_wait_cntr_7_0_cy(3)
    );
  Mcount_lock_wait_cntr_7_0_xor_3_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(2),
      LI => Mcount_lock_wait_cntr_7_0_cy_3_rt_14058,
      O => Result_3_1
    );
  Mcount_lock_wait_cntr_7_0_cy_4_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(3),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_4_rt_14060,
      O => Mcount_lock_wait_cntr_7_0_cy(4)
    );
  Mcount_lock_wait_cntr_7_0_xor_4_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(3),
      LI => Mcount_lock_wait_cntr_7_0_cy_4_rt_14060,
      O => Result_4_1
    );
  Mcount_lock_wait_cntr_7_0_cy_5_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(4),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_5_rt_14062,
      O => Mcount_lock_wait_cntr_7_0_cy(5)
    );
  Mcount_lock_wait_cntr_7_0_xor_5_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(4),
      LI => Mcount_lock_wait_cntr_7_0_cy_5_rt_14062,
      O => Result_5_1
    );
  Mcount_lock_wait_cntr_7_0_cy_6_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(5),
      DI => N0,
      S => Mcount_lock_wait_cntr_7_0_cy_6_rt_14064,
      O => Mcount_lock_wait_cntr_7_0_cy(6)
    );
  Mcount_lock_wait_cntr_7_0_xor_6_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(5),
      LI => Mcount_lock_wait_cntr_7_0_cy_6_rt_14064,
      O => Result_6_1
    );
  Mcount_lock_wait_cntr_7_0_xor_7_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_7_0_cy(6),
      LI => Mcount_lock_wait_cntr_7_0_xor_7_rt_14066,
      O => Result_7_1
    );
  Mcount_lock_wait_cntr_15_8_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_lock_wait_cntr_15_8_lut(0),
      O => Mcount_lock_wait_cntr_15_8_cy(0)
    );
  Mcount_lock_wait_cntr_15_8_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_lock_wait_cntr_15_8_lut(0),
      O => Result(0)
    );
  Mcount_lock_wait_cntr_15_8_cy_1_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(0),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_1_rt_14039,
      O => Mcount_lock_wait_cntr_15_8_cy(1)
    );
  Mcount_lock_wait_cntr_15_8_xor_1_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(0),
      LI => Mcount_lock_wait_cntr_15_8_cy_1_rt_14039,
      O => Result(1)
    );
  Mcount_lock_wait_cntr_15_8_cy_2_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(1),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_2_rt_14041,
      O => Mcount_lock_wait_cntr_15_8_cy(2)
    );
  Mcount_lock_wait_cntr_15_8_xor_2_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(1),
      LI => Mcount_lock_wait_cntr_15_8_cy_2_rt_14041,
      O => Result(2)
    );
  Mcount_lock_wait_cntr_15_8_cy_3_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(2),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_3_rt_14043,
      O => Mcount_lock_wait_cntr_15_8_cy(3)
    );
  Mcount_lock_wait_cntr_15_8_xor_3_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(2),
      LI => Mcount_lock_wait_cntr_15_8_cy_3_rt_14043,
      O => Result(3)
    );
  Mcount_lock_wait_cntr_15_8_cy_4_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(3),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_4_rt_14045,
      O => Mcount_lock_wait_cntr_15_8_cy(4)
    );
  Mcount_lock_wait_cntr_15_8_xor_4_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(3),
      LI => Mcount_lock_wait_cntr_15_8_cy_4_rt_14045,
      O => Result(4)
    );
  Mcount_lock_wait_cntr_15_8_cy_5_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(4),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_5_rt_14047,
      O => Mcount_lock_wait_cntr_15_8_cy(5)
    );
  Mcount_lock_wait_cntr_15_8_xor_5_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(4),
      LI => Mcount_lock_wait_cntr_15_8_cy_5_rt_14047,
      O => Result(5)
    );
  Mcount_lock_wait_cntr_15_8_cy_6_Q : MUXCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(5),
      DI => N0,
      S => Mcount_lock_wait_cntr_15_8_cy_6_rt_14049,
      O => Mcount_lock_wait_cntr_15_8_cy(6)
    );
  Mcount_lock_wait_cntr_15_8_xor_6_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(5),
      LI => Mcount_lock_wait_cntr_15_8_cy_6_rt_14049,
      O => Result(6)
    );
  Mcount_lock_wait_cntr_15_8_xor_7_Q : XORCY
    port map (
      CI => Mcount_lock_wait_cntr_15_8_cy(6),
      LI => Mcount_lock_wait_cntr_15_8_xor_7_rt_14051,
      O => Result(7)
    );
  use_pll_pll_adv_i : PLL_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_DESKEW_ADJUST => "NONE",
      CLKFBOUT_MULT => 2,
      CLKFBOUT_PHASE => 0.000000,
      CLKIN1_PERIOD => 4.000000,
      CLKIN2_PERIOD => 4.000000,
      CLKOUT0_DESKEW_ADJUST => "NONE",
      CLKOUT0_DIVIDE => 2,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT1_DESKEW_ADJUST => "NONE",
      CLKOUT1_DIVIDE => 2,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT2_DESKEW_ADJUST => "NONE",
      CLKOUT2_DIVIDE => 4,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT3_DESKEW_ADJUST => "NONE",
      CLKOUT3_DIVIDE => 4,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT4_DESKEW_ADJUST => "NONE",
      CLKOUT4_DIVIDE => 1,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT5_DESKEW_ADJUST => "NONE",
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLK_FEEDBACK => "CLKFBOUT",
      COMPENSATION => "SYSTEM_SYNCHRONOUS",
      DIVCLK_DIVIDE => 1,
      EN_REL => FALSE,
      PLL_PMCD_MODE => FALSE,
      REF_JITTER => 0.100000,
      RESET_ON_LOSS_OF_LOCK => FALSE,
      RST_DEASSERT_CLK => "CLKIN1",
      SIM_DEVICE => "VIRTEX5"
    )
    port map (
      CLKIN1 => clkin_pll,
      CLKIN2 => NLW_use_pll_pll_adv_i_CLKIN2_UNCONNECTED,
      CLKFBIN => clkfbout,
      RST => rst,
      CLKINSEL => N1,
      DWE => NLW_use_pll_pll_adv_i_DWE_UNCONNECTED,
      DEN => NLW_use_pll_pll_adv_i_DEN_UNCONNECTED,
      DCLK => NLW_use_pll_pll_adv_i_DCLK_UNCONNECTED,
      REL => NLW_use_pll_pll_adv_i_REL_UNCONNECTED,
      CLKOUT0 => clkout0,
      CLKOUT1 => NLW_use_pll_pll_adv_i_CLKOUT1_UNCONNECTED,
      CLKOUT2 => clkout2,
      CLKOUT3 => txsync_clkout,
      CLKOUT4 => NLW_use_pll_pll_adv_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_use_pll_pll_adv_i_CLKOUT5_UNCONNECTED,
      CLKFBOUT => clkfbout,
      CLKOUTDCM0 => NLW_use_pll_pll_adv_i_CLKOUTDCM0_UNCONNECTED,
      CLKOUTDCM1 => NLW_use_pll_pll_adv_i_CLKOUTDCM1_UNCONNECTED,
      CLKOUTDCM2 => NLW_use_pll_pll_adv_i_CLKOUTDCM2_UNCONNECTED,
      CLKOUTDCM3 => NLW_use_pll_pll_adv_i_CLKOUTDCM3_UNCONNECTED,
      CLKOUTDCM4 => NLW_use_pll_pll_adv_i_CLKOUTDCM4_UNCONNECTED,
      CLKOUTDCM5 => NLW_use_pll_pll_adv_i_CLKOUTDCM5_UNCONNECTED,
      CLKFBDCM => NLW_use_pll_pll_adv_i_CLKFBDCM_UNCONNECTED,
      LOCKED => use_pll_pll_lk_out,
      DRDY => NLW_use_pll_pll_adv_i_DRDY_UNCONNECTED,
      DADDR(4) => NLW_use_pll_pll_adv_i_DADDR_4_UNCONNECTED,
      DADDR(3) => NLW_use_pll_pll_adv_i_DADDR_3_UNCONNECTED,
      DADDR(2) => NLW_use_pll_pll_adv_i_DADDR_2_UNCONNECTED,
      DADDR(1) => NLW_use_pll_pll_adv_i_DADDR_1_UNCONNECTED,
      DADDR(0) => NLW_use_pll_pll_adv_i_DADDR_0_UNCONNECTED,
      DI(15) => NLW_use_pll_pll_adv_i_DI_15_UNCONNECTED,
      DI(14) => NLW_use_pll_pll_adv_i_DI_14_UNCONNECTED,
      DI(13) => NLW_use_pll_pll_adv_i_DI_13_UNCONNECTED,
      DI(12) => NLW_use_pll_pll_adv_i_DI_12_UNCONNECTED,
      DI(11) => NLW_use_pll_pll_adv_i_DI_11_UNCONNECTED,
      DI(10) => NLW_use_pll_pll_adv_i_DI_10_UNCONNECTED,
      DI(9) => NLW_use_pll_pll_adv_i_DI_9_UNCONNECTED,
      DI(8) => NLW_use_pll_pll_adv_i_DI_8_UNCONNECTED,
      DI(7) => NLW_use_pll_pll_adv_i_DI_7_UNCONNECTED,
      DI(6) => NLW_use_pll_pll_adv_i_DI_6_UNCONNECTED,
      DI(5) => NLW_use_pll_pll_adv_i_DI_5_UNCONNECTED,
      DI(4) => NLW_use_pll_pll_adv_i_DI_4_UNCONNECTED,
      DI(3) => NLW_use_pll_pll_adv_i_DI_3_UNCONNECTED,
      DI(2) => NLW_use_pll_pll_adv_i_DI_2_UNCONNECTED,
      DI(1) => NLW_use_pll_pll_adv_i_DI_1_UNCONNECTED,
      DI(0) => NLW_use_pll_pll_adv_i_DI_0_UNCONNECTED,
      DO(15) => NLW_use_pll_pll_adv_i_DO_15_UNCONNECTED,
      DO(14) => NLW_use_pll_pll_adv_i_DO_14_UNCONNECTED,
      DO(13) => NLW_use_pll_pll_adv_i_DO_13_UNCONNECTED,
      DO(12) => NLW_use_pll_pll_adv_i_DO_12_UNCONNECTED,
      DO(11) => NLW_use_pll_pll_adv_i_DO_11_UNCONNECTED,
      DO(10) => NLW_use_pll_pll_adv_i_DO_10_UNCONNECTED,
      DO(9) => NLW_use_pll_pll_adv_i_DO_9_UNCONNECTED,
      DO(8) => NLW_use_pll_pll_adv_i_DO_8_UNCONNECTED,
      DO(7) => NLW_use_pll_pll_adv_i_DO_7_UNCONNECTED,
      DO(6) => NLW_use_pll_pll_adv_i_DO_6_UNCONNECTED,
      DO(5) => NLW_use_pll_pll_adv_i_DO_5_UNCONNECTED,
      DO(4) => NLW_use_pll_pll_adv_i_DO_4_UNCONNECTED,
      DO(3) => NLW_use_pll_pll_adv_i_DO_3_UNCONNECTED,
      DO(2) => NLW_use_pll_pll_adv_i_DO_2_UNCONNECTED,
      DO(1) => NLW_use_pll_pll_adv_i_DO_1_UNCONNECTED,
      DO(0) => NLW_use_pll_pll_adv_i_DO_0_UNCONNECTED
    );
  use_pll_coreclk_pll_bufg : BUFG
    port map (
      I => clkout0,
      O => NlwRenamedSig_OI_userclk
    );
  use_pll_gtxclk_pll_bufg : BUFG
    port map (
      I => clkout2,
      O => gtx_usrclk
    );
  use_pll_txsync_clk_pll_bufg : BUFG
    port map (
      I => txsync_clkout,
      O => txsync_clk
    );
  pll_locked_out_r_or0000_SW0 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => lock_wait_cntr_15_8(5),
      I1 => lock_wait_cntr_15_8(4),
      I2 => lock_wait_cntr_15_8(3),
      I3 => lock_wait_cntr_15_8(0),
      O => N02
    );
  pll_locked_out_r_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFF00020000"
    )
    port map (
      I0 => lock_wait_cntr_15_8(7),
      I1 => lock_wait_cntr_15_8(6),
      I2 => lock_wait_cntr_15_8(2),
      I3 => lock_wait_cntr_15_8(1),
      I4 => N02,
      I5 => time_elapsed_14117,
      O => pll_locked_out_r_or0000_14115
    );
  lock_wait_cntr_15_8_not0001_SW0 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => lock_wait_cntr_7_0(7),
      I1 => lock_wait_cntr_7_0(6),
      I2 => lock_wait_cntr_7_0(5),
      I3 => time_elapsed_14117,
      I4 => lock_wait_cntr_7_0(4),
      O => N2
    );
  lock_wait_cntr_15_8_not0001 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => lock_wait_cntr_7_0(1),
      I1 => lock_wait_cntr_7_0(3),
      I2 => lock_wait_cntr_7_0(2),
      I3 => N2,
      I4 => lock_wait_cntr_7_0(0),
      I5 => N01,
      O => lock_wait_cntr_15_8_not0001_14102
    );
  lock_wait_cntr_7_0_not00011 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => time_elapsed_14117,
      I1 => N01,
      O => lock_wait_cntr_7_0_not0001
    );
  lock_wait_cntr_15_8_not00011_SW0 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => lock_wait_cntr_15_8(1),
      I1 => lock_wait_cntr_15_8(7),
      I2 => lock_wait_cntr_15_8(2),
      O => N4
    );
  lock_wait_cntr_15_8_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => lock_wait_cntr_15_8(6),
      I1 => lock_wait_cntr_15_8(3),
      I2 => lock_wait_cntr_15_8(5),
      I3 => lock_wait_cntr_15_8(4),
      I4 => lock_wait_cntr_15_8(0),
      I5 => N4,
      O => N01
    );
  Mcount_lock_wait_cntr_7_0_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(1),
      O => Mcount_lock_wait_cntr_7_0_cy_1_rt_14054
    );
  Mcount_lock_wait_cntr_7_0_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(2),
      O => Mcount_lock_wait_cntr_7_0_cy_2_rt_14056
    );
  Mcount_lock_wait_cntr_7_0_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(3),
      O => Mcount_lock_wait_cntr_7_0_cy_3_rt_14058
    );
  Mcount_lock_wait_cntr_7_0_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(4),
      O => Mcount_lock_wait_cntr_7_0_cy_4_rt_14060
    );
  Mcount_lock_wait_cntr_7_0_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(5),
      O => Mcount_lock_wait_cntr_7_0_cy_5_rt_14062
    );
  Mcount_lock_wait_cntr_7_0_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(6),
      O => Mcount_lock_wait_cntr_7_0_cy_6_rt_14064
    );
  Mcount_lock_wait_cntr_15_8_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(1),
      O => Mcount_lock_wait_cntr_15_8_cy_1_rt_14039
    );
  Mcount_lock_wait_cntr_15_8_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(2),
      O => Mcount_lock_wait_cntr_15_8_cy_2_rt_14041
    );
  Mcount_lock_wait_cntr_15_8_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(3),
      O => Mcount_lock_wait_cntr_15_8_cy_3_rt_14043
    );
  Mcount_lock_wait_cntr_15_8_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(4),
      O => Mcount_lock_wait_cntr_15_8_cy_4_rt_14045
    );
  Mcount_lock_wait_cntr_15_8_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(5),
      O => Mcount_lock_wait_cntr_15_8_cy_5_rt_14047
    );
  Mcount_lock_wait_cntr_15_8_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(6),
      O => Mcount_lock_wait_cntr_15_8_cy_6_rt_14049
    );
  Mcount_lock_wait_cntr_7_0_xor_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_7_0(7),
      O => Mcount_lock_wait_cntr_7_0_xor_7_rt_14066
    );
  Mcount_lock_wait_cntr_15_8_xor_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lock_wait_cntr_15_8(7),
      O => Mcount_lock_wait_cntr_15_8_xor_7_rt_14051
    );
  Mcount_lock_wait_cntr_7_0_lut_0_INV_0 : INV
    port map (
      I => lock_wait_cntr_7_0(0),
      O => Mcount_lock_wait_cntr_7_0_lut(0)
    );
  Mcount_lock_wait_cntr_15_8_lut_0_INV_0 : INV
    port map (
      I => lock_wait_cntr_15_8(0),
      O => Mcount_lock_wait_cntr_15_8_lut(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity reset_logic is
  port (
    CRMPWRSOFTRESETN : in STD_LOGIC := 'X'; 
    CRMLINKRSTN : out STD_LOGIC; 
    CRMUSERCFGRSTN : out STD_LOGIC; 
    CRMURSTN : out STD_LOGIC; 
    user_master_reset_n : in STD_LOGIC := 'X'; 
    L0STATSCFGTRANSMITTED : in STD_LOGIC := 'X'; 
    CRMNVRSTN : out STD_LOGIC; 
    L0DLUPDOWN : in STD_LOGIC := 'X'; 
    CRMCORECLK : in STD_LOGIC := 'X'; 
    CRMMACRSTN : out STD_LOGIC; 
    clock_ready : in STD_LOGIC := 'X'; 
    CRMDOHOTRESETN : in STD_LOGIC := 'X'; 
    CRMMGMTRSTN : out STD_LOGIC; 
    USERCLK : in STD_LOGIC := 'X'; 
    L0LTSSMSTATE : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end reset_logic;

architecture STRUCTURE of reset_logic is
  signal NlwRenamedSignal_CRMMACRSTN : STD_LOGIC; 
  signal NlwRenamedSignal_CRMURSTN : STD_LOGIC; 
  signal crm_pwr_soft_reset_n_aftersentcpl_14021 : STD_LOGIC; 
  signal crm_pwr_soft_reset_n_aftersentcpl_not0001 : STD_LOGIC; 
  signal crmpwrsoftresetn_d_14023 : STD_LOGIC; 
  signal dl_down_1_14024 : STD_LOGIC; 
  signal dl_down_2_14025 : STD_LOGIC; 
  signal dl_down_reset_1_n_14026 : STD_LOGIC; 
  signal dl_down_reset_1_n_not0001 : STD_LOGIC; 
  signal dl_down_reset_2_n_14028 : STD_LOGIC; 
  signal dl_down_reset_n_14029 : STD_LOGIC; 
  signal dl_down_reset_n_and0000 : STD_LOGIC; 
  signal l0statscfgtransmitted_d_14031 : STD_LOGIC; 
  signal softreset_wait_for_cpl_14032 : STD_LOGIC; 
  signal softreset_wait_for_cpl_and0000 : STD_LOGIC; 
  signal softreset_wait_for_cpl_not0001 : STD_LOGIC; 
  signal user_master_reset_n_inv : STD_LOGIC; 
begin
  CRMLINKRSTN <= NlwRenamedSignal_CRMURSTN;
  CRMURSTN <= NlwRenamedSignal_CRMURSTN;
  CRMNVRSTN <= NlwRenamedSignal_CRMMACRSTN;
  CRMMACRSTN <= NlwRenamedSignal_CRMMACRSTN;
  XST_VCC : VCC
    port map (
      P => NlwRenamedSignal_CRMMACRSTN
    );
  dl_down_reset_1_n : FDP
    port map (
      C => CRMCORECLK,
      D => dl_down_reset_1_n_not0001,
      PRE => user_master_reset_n_inv,
      Q => dl_down_reset_1_n_14026
    );
  dl_down_1 : FDP
    port map (
      C => CRMCORECLK,
      D => L0DLUPDOWN,
      PRE => user_master_reset_n_inv,
      Q => dl_down_1_14024
    );
  dl_down_reset_n : FDP
    port map (
      C => CRMCORECLK,
      D => dl_down_reset_n_and0000,
      PRE => user_master_reset_n_inv,
      Q => dl_down_reset_n_14029
    );
  softreset_wait_for_cpl : FDCE
    port map (
      C => USERCLK,
      CE => softreset_wait_for_cpl_not0001,
      CLR => user_master_reset_n_inv,
      D => softreset_wait_for_cpl_and0000,
      Q => softreset_wait_for_cpl_14032
    );
  crm_pwr_soft_reset_n_aftersentcpl : FDP
    port map (
      C => USERCLK,
      D => crm_pwr_soft_reset_n_aftersentcpl_not0001,
      PRE => user_master_reset_n_inv,
      Q => crm_pwr_soft_reset_n_aftersentcpl_14021
    );
  crmpwrsoftresetn_d : FDP
    port map (
      C => USERCLK,
      D => CRMPWRSOFTRESETN,
      PRE => user_master_reset_n_inv,
      Q => crmpwrsoftresetn_d_14023
    );
  l0statscfgtransmitted_d : FDC
    port map (
      C => USERCLK,
      CLR => user_master_reset_n_inv,
      D => L0STATSCFGTRANSMITTED,
      Q => l0statscfgtransmitted_d_14031
    );
  dl_down_2 : FDP
    port map (
      C => CRMCORECLK,
      D => dl_down_1_14024,
      PRE => user_master_reset_n_inv,
      Q => dl_down_2_14025
    );
  dl_down_reset_2_n : FDP
    port map (
      C => CRMCORECLK,
      D => dl_down_reset_1_n_14026,
      PRE => user_master_reset_n_inv,
      Q => dl_down_reset_2_n_14028
    );
  CRMURSTN1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dl_down_reset_n_14029,
      I1 => CRMDOHOTRESETN,
      O => NlwRenamedSignal_CRMURSTN
    );
  CRMUSERCFGRSTN1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => dl_down_reset_n_14029,
      I1 => CRMDOHOTRESETN,
      I2 => crm_pwr_soft_reset_n_aftersentcpl_14021,
      O => CRMUSERCFGRSTN
    );
  dl_down_reset_n_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dl_down_reset_1_n_14026,
      I1 => dl_down_reset_2_n_14028,
      O => dl_down_reset_n_and0000
    );
  dl_down_reset_1_n_not00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => dl_down_2_14025,
      I1 => dl_down_1_14024,
      O => dl_down_reset_1_n_not0001
    );
  crm_pwr_soft_reset_n_aftersentcpl_not00011 : LUT4
    generic map(
      INIT => X"4C5D"
    )
    port map (
      I0 => L0STATSCFGTRANSMITTED,
      I1 => CRMPWRSOFTRESETN,
      I2 => softreset_wait_for_cpl_14032,
      I3 => l0statscfgtransmitted_d_14031,
      O => crm_pwr_soft_reset_n_aftersentcpl_not0001
    );
  softreset_wait_for_cpl_and00001 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => L0STATSCFGTRANSMITTED,
      I1 => l0statscfgtransmitted_d_14031,
      I2 => CRMPWRSOFTRESETN,
      I3 => crmpwrsoftresetn_d_14023,
      O => softreset_wait_for_cpl_and0000
    );
  CRMMGMTRSTN1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => clock_ready,
      I1 => user_master_reset_n,
      O => CRMMGMTRSTN
    );
  softreset_wait_for_cpl_not00011 : LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      I0 => L0STATSCFGTRANSMITTED,
      I1 => l0statscfgtransmitted_d_14031,
      I2 => crmpwrsoftresetn_d_14023,
      I3 => CRMPWRSOFTRESETN,
      O => softreset_wait_for_cpl_not0001
    );
  user_master_reset_n_inv1_INV_0 : INV
    port map (
      I => user_master_reset_n,
      O => user_master_reset_n_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity prod_fixes is
  port (
    clk : in STD_LOGIC := 'X'; 
    chan_bond_done : in STD_LOGIC := 'X'; 
    bit_reset_n : in STD_LOGIC := 'X'; 
    upcfgcap_cycle : out STD_LOGIC; 
    masking_ack : out STD_LOGIC; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    pipe_rx_data_l2_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_k_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l7_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l3_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l4_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l5_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_valid_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l6_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    negotiated_link_width : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    pipe_rx_data_l0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_l6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    l0_ltssm_state : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    pipe_rx_data_l7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_valid : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pipe_rx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end prod_fixes;

architecture STRUCTURE of prod_fixes is
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N161 : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N211 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N301 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal N46 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal bit_reset_n_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_curr_state_l0_FSM_FFd1 : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd2_13656 : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd3_13657 : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd4_13659 : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd5_13661 : STD_LOGIC; 
  signal curr_state_l0_FSM_FFd5_In_13662 : STD_LOGIC; 
  signal curr_state_l0_cmp_eq0004_13663 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd1_13664 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd2_13665 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd3_13666 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd4_13668 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd4_In1_13670 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd5_13671 : STD_LOGIC; 
  signal curr_state_l1_FSM_FFd5_In_13672 : STD_LOGIC; 
  signal curr_state_l1_cmp_eq0001 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd1_13674 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd2_13675 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd3_13676 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd4_13678 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd4_In1_13680 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd5_13681 : STD_LOGIC; 
  signal curr_state_l2_FSM_FFd5_In_13682 : STD_LOGIC; 
  signal curr_state_l2_cmp_eq0001 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd1_13684 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd2_13685 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd3_13686 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd4_13688 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd5_13690 : STD_LOGIC; 
  signal curr_state_l3_FSM_FFd5_In_13691 : STD_LOGIC; 
  signal curr_state_l3_cmp_eq0001_13692 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd1_13693 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd2_13694 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd3_13695 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd4_13697 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd5_13699 : STD_LOGIC; 
  signal curr_state_l4_FSM_FFd5_In_13700 : STD_LOGIC; 
  signal curr_state_l4_cmp_eq0001_13701 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd1_13702 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd2_13703 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd3_13704 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd4_13706 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd4_In1_13708 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd5_13709 : STD_LOGIC; 
  signal curr_state_l5_FSM_FFd5_In_13710 : STD_LOGIC; 
  signal curr_state_l5_cmp_eq0001 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd1_13712 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd2_13713 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd3_13714 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd4_13716 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd4_In1_13718 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd5_13719 : STD_LOGIC; 
  signal curr_state_l6_FSM_FFd5_In_13720 : STD_LOGIC; 
  signal curr_state_l6_cmp_eq0001 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd1_13722 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd2_13723 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd3_13724 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd3_In : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd4_13726 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd4_In : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd5_13728 : STD_LOGIC; 
  signal curr_state_l7_FSM_FFd5_In_13729 : STD_LOGIC; 
  signal curr_state_l7_cmp_eq0001_13730 : STD_LOGIC; 
  signal dllp_ack_l0 : STD_LOGIC; 
  signal dllp_ack_l0_cmp_eq0001 : STD_LOGIC; 
  signal dllp_ack_l0_cmp_eq00018126_13733 : STD_LOGIC; 
  signal dllp_ack_l0_cmp_eq0001849_13734 : STD_LOGIC; 
  signal dllp_ack_l0_r_13735 : STD_LOGIC; 
  signal dllp_ack_l3_reverse : STD_LOGIC; 
  signal dllp_ack_l3_reverse_r_13737 : STD_LOGIC; 
  signal dllp_ack_l3_reverse_rr_13738 : STD_LOGIC; 
  signal dllp_ack_l3_reverse_rr_and0000 : STD_LOGIC; 
  signal dllp_ack_l4 : STD_LOGIC; 
  signal dllp_ack_l4_cmp_eq0001 : STD_LOGIC; 
  signal dllp_ack_l4_cmp_eq00018126_13742 : STD_LOGIC; 
  signal dllp_ack_l4_cmp_eq0001849_13743 : STD_LOGIC; 
  signal dllp_ack_l4_r_13744 : STD_LOGIC; 
  signal dllp_ack_l4_rr_13745 : STD_LOGIC; 
  signal dllp_ack_l4_rr_and0000 : STD_LOGIC; 
  signal dllp_ack_l7_reverse : STD_LOGIC; 
  signal dllp_ack_l7_reverse_r_13748 : STD_LOGIC; 
  signal pipe_rx_data_l0_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l1_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l2_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l3_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l4_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l5_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l6_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l7_out_not0001 : STD_LOGIC; 
  signal pipe_rx_data_l7_out_or0001_13983 : STD_LOGIC; 
  signal trn_lnk_up_n_d_14009 : STD_LOGIC; 
  signal l0_ltssm_state_d : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal negotiated_link_width_d : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal pipe_rx_data_k_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l0_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l1_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l2_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l3_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l4_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l5_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l6_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l7_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_valid_out_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  upcfgcap_cycle <= NlwRenamedSig_OI_curr_state_l0_FSM_FFd1;
  l0_ltssm_state_d_0 : FDR
    port map (
      C => clk,
      D => l0_ltssm_state(0),
      R => bit_reset_n_inv,
      Q => l0_ltssm_state_d(0)
    );
  l0_ltssm_state_d_1 : FDR
    port map (
      C => clk,
      D => l0_ltssm_state(1),
      R => bit_reset_n_inv,
      Q => l0_ltssm_state_d(1)
    );
  l0_ltssm_state_d_2 : FDR
    port map (
      C => clk,
      D => l0_ltssm_state(2),
      R => bit_reset_n_inv,
      Q => l0_ltssm_state_d(2)
    );
  l0_ltssm_state_d_3 : FDR
    port map (
      C => clk,
      D => l0_ltssm_state(3),
      R => bit_reset_n_inv,
      Q => l0_ltssm_state_d(3)
    );
  trn_lnk_up_n_d : FDS
    port map (
      C => clk,
      D => trn_lnk_up_n,
      S => bit_reset_n_inv,
      Q => trn_lnk_up_n_d_14009
    );
  negotiated_link_width_d_3 : FD
    port map (
      C => clk,
      D => negotiated_link_width(3),
      Q => negotiated_link_width_d(3)
    );
  dllp_ack_l0_r : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l0,
      Q => dllp_ack_l0_r_13735
    );
  dllp_ack_l7_reverse_r : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l7_reverse,
      Q => dllp_ack_l7_reverse_r_13748
    );
  dllp_ack_l4_r : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l4,
      Q => dllp_ack_l4_r_13744
    );
  dllp_ack_l4_rr : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l4_rr_and0000,
      Q => dllp_ack_l4_rr_13745
    );
  dllp_ack_l3_reverse_r : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l3_reverse,
      Q => dllp_ack_l3_reverse_r_13737
    );
  dllp_ack_l3_reverse_rr : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => dllp_ack_l3_reverse_rr_and0000,
      Q => dllp_ack_l3_reverse_rr_13738
    );
  pipe_rx_data_l7_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(7),
      Q => pipe_rx_data_l7_out(0)
    );
  pipe_rx_data_l7_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(6),
      Q => pipe_rx_data_l7_out(1)
    );
  pipe_rx_data_l7_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(5),
      Q => pipe_rx_data_l7_out(2)
    );
  pipe_rx_data_l7_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(4),
      Q => pipe_rx_data_l7_out(3)
    );
  pipe_rx_data_l7_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(3),
      Q => pipe_rx_data_l7_out(4)
    );
  pipe_rx_data_l7_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(2),
      Q => pipe_rx_data_l7_out(5)
    );
  pipe_rx_data_l7_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(1),
      Q => pipe_rx_data_l7_out(6)
    );
  pipe_rx_data_l7_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l7_out_not0001,
      D => pipe_rx_data_l7_out_mux0000(0),
      Q => pipe_rx_data_l7_out(7)
    );
  pipe_rx_data_l6_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(7),
      Q => pipe_rx_data_l6_out(0)
    );
  pipe_rx_data_l6_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(6),
      Q => pipe_rx_data_l6_out(1)
    );
  pipe_rx_data_l6_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(5),
      Q => pipe_rx_data_l6_out(2)
    );
  pipe_rx_data_l6_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(4),
      Q => pipe_rx_data_l6_out(3)
    );
  pipe_rx_data_l6_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(3),
      Q => pipe_rx_data_l6_out(4)
    );
  pipe_rx_data_l6_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(2),
      Q => pipe_rx_data_l6_out(5)
    );
  pipe_rx_data_l6_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(1),
      Q => pipe_rx_data_l6_out(6)
    );
  pipe_rx_data_l6_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l6_out_not0001,
      D => pipe_rx_data_l6_out_mux0000(0),
      Q => pipe_rx_data_l6_out(7)
    );
  pipe_rx_data_l3_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(7),
      Q => pipe_rx_data_l3_out(0)
    );
  pipe_rx_data_l3_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(6),
      Q => pipe_rx_data_l3_out(1)
    );
  pipe_rx_data_l3_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(5),
      Q => pipe_rx_data_l3_out(2)
    );
  pipe_rx_data_l3_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(4),
      Q => pipe_rx_data_l3_out(3)
    );
  pipe_rx_data_l3_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(3),
      Q => pipe_rx_data_l3_out(4)
    );
  pipe_rx_data_l3_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(2),
      Q => pipe_rx_data_l3_out(5)
    );
  pipe_rx_data_l3_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(1),
      Q => pipe_rx_data_l3_out(6)
    );
  pipe_rx_data_l3_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l3_out_not0001,
      D => pipe_rx_data_l3_out_mux0000(0),
      Q => pipe_rx_data_l3_out(7)
    );
  pipe_rx_data_l5_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(7),
      Q => pipe_rx_data_l5_out(0)
    );
  pipe_rx_data_l5_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(6),
      Q => pipe_rx_data_l5_out(1)
    );
  pipe_rx_data_l5_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(5),
      Q => pipe_rx_data_l5_out(2)
    );
  pipe_rx_data_l5_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(4),
      Q => pipe_rx_data_l5_out(3)
    );
  pipe_rx_data_l5_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(3),
      Q => pipe_rx_data_l5_out(4)
    );
  pipe_rx_data_l5_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(2),
      Q => pipe_rx_data_l5_out(5)
    );
  pipe_rx_data_l5_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(1),
      Q => pipe_rx_data_l5_out(6)
    );
  pipe_rx_data_l5_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l5_out_not0001,
      D => pipe_rx_data_l5_out_mux0000(0),
      Q => pipe_rx_data_l5_out(7)
    );
  pipe_rx_data_l4_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(7),
      Q => pipe_rx_data_l4_out(0)
    );
  pipe_rx_data_l4_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(6),
      Q => pipe_rx_data_l4_out(1)
    );
  pipe_rx_data_l4_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(5),
      Q => pipe_rx_data_l4_out(2)
    );
  pipe_rx_data_l4_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(4),
      Q => pipe_rx_data_l4_out(3)
    );
  pipe_rx_data_l4_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(3),
      Q => pipe_rx_data_l4_out(4)
    );
  pipe_rx_data_l4_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(2),
      Q => pipe_rx_data_l4_out(5)
    );
  pipe_rx_data_l4_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(1),
      Q => pipe_rx_data_l4_out(6)
    );
  pipe_rx_data_l4_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l4_out_not0001,
      D => pipe_rx_data_l4_out_mux0000(0),
      Q => pipe_rx_data_l4_out(7)
    );
  pipe_rx_data_l2_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(7),
      Q => pipe_rx_data_l2_out(0)
    );
  pipe_rx_data_l2_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(6),
      Q => pipe_rx_data_l2_out(1)
    );
  pipe_rx_data_l2_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(5),
      Q => pipe_rx_data_l2_out(2)
    );
  pipe_rx_data_l2_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(4),
      Q => pipe_rx_data_l2_out(3)
    );
  pipe_rx_data_l2_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(3),
      Q => pipe_rx_data_l2_out(4)
    );
  pipe_rx_data_l2_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(2),
      Q => pipe_rx_data_l2_out(5)
    );
  pipe_rx_data_l2_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(1),
      Q => pipe_rx_data_l2_out(6)
    );
  pipe_rx_data_l2_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l2_out_not0001,
      D => pipe_rx_data_l2_out_mux0000(0),
      Q => pipe_rx_data_l2_out(7)
    );
  pipe_rx_data_l1_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(7),
      Q => pipe_rx_data_l1_out(0)
    );
  pipe_rx_data_l1_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(6),
      Q => pipe_rx_data_l1_out(1)
    );
  pipe_rx_data_l1_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(5),
      Q => pipe_rx_data_l1_out(2)
    );
  pipe_rx_data_l1_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(4),
      Q => pipe_rx_data_l1_out(3)
    );
  pipe_rx_data_l1_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(3),
      Q => pipe_rx_data_l1_out(4)
    );
  pipe_rx_data_l1_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(2),
      Q => pipe_rx_data_l1_out(5)
    );
  pipe_rx_data_l1_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(1),
      Q => pipe_rx_data_l1_out(6)
    );
  pipe_rx_data_l1_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l1_out_not0001,
      D => pipe_rx_data_l1_out_mux0000(0),
      Q => pipe_rx_data_l1_out(7)
    );
  pipe_rx_data_l0_out_0 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(7),
      Q => pipe_rx_data_l0_out(0)
    );
  pipe_rx_data_l0_out_1 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(6),
      Q => pipe_rx_data_l0_out(1)
    );
  pipe_rx_data_l0_out_2 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(5),
      Q => pipe_rx_data_l0_out(2)
    );
  pipe_rx_data_l0_out_3 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(4),
      Q => pipe_rx_data_l0_out(3)
    );
  pipe_rx_data_l0_out_4 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(3),
      Q => pipe_rx_data_l0_out(4)
    );
  pipe_rx_data_l0_out_5 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(2),
      Q => pipe_rx_data_l0_out(5)
    );
  pipe_rx_data_l0_out_6 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(1),
      Q => pipe_rx_data_l0_out(6)
    );
  pipe_rx_data_l0_out_7 : FDE
    port map (
      C => clk,
      CE => pipe_rx_data_l0_out_not0001,
      D => pipe_rx_data_l0_out_mux0000(0),
      Q => pipe_rx_data_l0_out(7)
    );
  pipe_rx_data_k_out_0 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(0),
      Q => pipe_rx_data_k_out(0)
    );
  pipe_rx_data_k_out_1 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(1),
      Q => pipe_rx_data_k_out(1)
    );
  pipe_rx_data_k_out_2 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(2),
      Q => pipe_rx_data_k_out(2)
    );
  pipe_rx_data_k_out_3 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(3),
      Q => pipe_rx_data_k_out(3)
    );
  pipe_rx_data_k_out_4 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(4),
      Q => pipe_rx_data_k_out(4)
    );
  pipe_rx_data_k_out_5 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(5),
      Q => pipe_rx_data_k_out(5)
    );
  pipe_rx_data_k_out_6 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(6),
      Q => pipe_rx_data_k_out(6)
    );
  pipe_rx_data_k_out_7 : FD
    port map (
      C => clk,
      D => pipe_rx_data_k_out_mux0000(7),
      Q => pipe_rx_data_k_out(7)
    );
  pipe_rx_valid_out_0 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(0),
      Q => pipe_rx_valid_out(0)
    );
  pipe_rx_valid_out_1 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(1),
      Q => pipe_rx_valid_out(1)
    );
  pipe_rx_valid_out_2 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(2),
      Q => pipe_rx_valid_out(2)
    );
  pipe_rx_valid_out_3 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(3),
      Q => pipe_rx_valid_out(3)
    );
  pipe_rx_valid_out_4 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(4),
      Q => pipe_rx_valid_out(4)
    );
  pipe_rx_valid_out_5 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(5),
      Q => pipe_rx_valid_out(5)
    );
  pipe_rx_valid_out_6 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(6),
      Q => pipe_rx_valid_out(6)
    );
  pipe_rx_valid_out_7 : FD
    port map (
      C => clk,
      D => pipe_rx_valid_out_mux0000(7),
      Q => pipe_rx_valid_out(7)
    );
  curr_state_l7_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l7_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l7_FSM_FFd3_13724
    );
  curr_state_l7_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l7_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l7_FSM_FFd4_13726
    );
  curr_state_l7_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l7_FSM_FFd5_In_13729,
      S => bit_reset_n_inv,
      Q => curr_state_l7_FSM_FFd5_13728
    );
  curr_state_l7_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l7_FSM_FFd3_13724,
      R => bit_reset_n_inv,
      Q => curr_state_l7_FSM_FFd2_13723
    );
  curr_state_l7_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l7_FSM_FFd2_13723,
      R => bit_reset_n_inv,
      Q => curr_state_l7_FSM_FFd1_13722
    );
  curr_state_l6_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l6_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l6_FSM_FFd3_13714
    );
  curr_state_l6_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l6_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l6_FSM_FFd4_13716
    );
  curr_state_l6_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l6_FSM_FFd5_In_13720,
      S => bit_reset_n_inv,
      Q => curr_state_l6_FSM_FFd5_13719
    );
  curr_state_l6_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l6_FSM_FFd3_13714,
      R => bit_reset_n_inv,
      Q => curr_state_l6_FSM_FFd2_13713
    );
  curr_state_l6_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l6_FSM_FFd2_13713,
      R => bit_reset_n_inv,
      Q => curr_state_l6_FSM_FFd1_13712
    );
  curr_state_l5_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l5_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l5_FSM_FFd3_13704
    );
  curr_state_l5_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l5_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l5_FSM_FFd4_13706
    );
  curr_state_l5_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l5_FSM_FFd5_In_13710,
      S => bit_reset_n_inv,
      Q => curr_state_l5_FSM_FFd5_13709
    );
  curr_state_l5_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l5_FSM_FFd3_13704,
      R => bit_reset_n_inv,
      Q => curr_state_l5_FSM_FFd2_13703
    );
  curr_state_l5_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l5_FSM_FFd2_13703,
      R => bit_reset_n_inv,
      Q => curr_state_l5_FSM_FFd1_13702
    );
  curr_state_l4_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l4_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l4_FSM_FFd3_13695
    );
  curr_state_l4_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l4_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l4_FSM_FFd4_13697
    );
  curr_state_l4_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l4_FSM_FFd5_In_13700,
      S => bit_reset_n_inv,
      Q => curr_state_l4_FSM_FFd5_13699
    );
  curr_state_l4_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l4_FSM_FFd3_13695,
      R => bit_reset_n_inv,
      Q => curr_state_l4_FSM_FFd2_13694
    );
  curr_state_l4_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l4_FSM_FFd2_13694,
      R => bit_reset_n_inv,
      Q => curr_state_l4_FSM_FFd1_13693
    );
  curr_state_l3_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l3_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l3_FSM_FFd3_13686
    );
  curr_state_l3_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l3_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l3_FSM_FFd4_13688
    );
  curr_state_l3_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l3_FSM_FFd5_In_13691,
      S => bit_reset_n_inv,
      Q => curr_state_l3_FSM_FFd5_13690
    );
  curr_state_l3_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l3_FSM_FFd3_13686,
      R => bit_reset_n_inv,
      Q => curr_state_l3_FSM_FFd2_13685
    );
  curr_state_l3_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l3_FSM_FFd2_13685,
      R => bit_reset_n_inv,
      Q => curr_state_l3_FSM_FFd1_13684
    );
  curr_state_l2_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l2_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l2_FSM_FFd3_13676
    );
  curr_state_l2_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l2_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l2_FSM_FFd4_13678
    );
  curr_state_l2_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l2_FSM_FFd5_In_13682,
      S => bit_reset_n_inv,
      Q => curr_state_l2_FSM_FFd5_13681
    );
  curr_state_l2_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l2_FSM_FFd3_13676,
      R => bit_reset_n_inv,
      Q => curr_state_l2_FSM_FFd2_13675
    );
  curr_state_l2_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l2_FSM_FFd2_13675,
      R => bit_reset_n_inv,
      Q => curr_state_l2_FSM_FFd1_13674
    );
  curr_state_l1_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l1_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l1_FSM_FFd3_13666
    );
  curr_state_l1_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l1_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l1_FSM_FFd4_13668
    );
  curr_state_l1_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l1_FSM_FFd5_In_13672,
      S => bit_reset_n_inv,
      Q => curr_state_l1_FSM_FFd5_13671
    );
  curr_state_l1_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l1_FSM_FFd3_13666,
      R => bit_reset_n_inv,
      Q => curr_state_l1_FSM_FFd2_13665
    );
  curr_state_l1_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l1_FSM_FFd2_13665,
      R => bit_reset_n_inv,
      Q => curr_state_l1_FSM_FFd1_13664
    );
  curr_state_l0_FSM_FFd3 : FDR
    port map (
      C => clk,
      D => curr_state_l0_FSM_FFd3_In,
      R => bit_reset_n_inv,
      Q => curr_state_l0_FSM_FFd3_13657
    );
  curr_state_l0_FSM_FFd4 : FDR
    port map (
      C => clk,
      D => curr_state_l0_FSM_FFd4_In,
      R => bit_reset_n_inv,
      Q => curr_state_l0_FSM_FFd4_13659
    );
  curr_state_l0_FSM_FFd5 : FDS
    port map (
      C => clk,
      D => curr_state_l0_FSM_FFd5_In_13662,
      S => bit_reset_n_inv,
      Q => curr_state_l0_FSM_FFd5_13661
    );
  curr_state_l0_FSM_FFd2 : FDR
    port map (
      C => clk,
      D => curr_state_l0_FSM_FFd3_13657,
      R => bit_reset_n_inv,
      Q => curr_state_l0_FSM_FFd2_13656
    );
  curr_state_l0_FSM_FFd1 : FDR
    port map (
      C => clk,
      D => curr_state_l0_FSM_FFd2_13656,
      R => bit_reset_n_inv,
      Q => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1
    );
  curr_state_l7_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => curr_state_l7_FSM_FFd5_13728,
      I1 => N11,
      I2 => pipe_rx_data_l7(5),
      I3 => pipe_rx_data_l7(6),
      I4 => pipe_rx_data_l7(7),
      I5 => N16,
      O => curr_state_l7_FSM_FFd4_In
    );
  curr_state_l4_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => curr_state_l4_FSM_FFd5_13699,
      I1 => N11,
      I2 => pipe_rx_data_l4(5),
      I3 => pipe_rx_data_l4(6),
      I4 => pipe_rx_data_l4(7),
      I5 => N18,
      O => curr_state_l4_FSM_FFd4_In
    );
  curr_state_l3_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => curr_state_l3_FSM_FFd5_13690,
      I1 => N11,
      I2 => pipe_rx_data_l3(5),
      I3 => pipe_rx_data_l3(6),
      I4 => pipe_rx_data_l3(7),
      I5 => N17,
      O => curr_state_l3_FSM_FFd4_In
    );
  curr_state_l0_FSM_FFd4_In2 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => curr_state_l0_FSM_FFd5_13661,
      I1 => N11,
      I2 => pipe_rx_data_l0(5),
      I3 => pipe_rx_data_l0(6),
      I4 => pipe_rx_data_l0(7),
      I5 => N19,
      O => curr_state_l0_FSM_FFd4_In
    );
  pipe_rx_data_l4_out_not000111 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => curr_state_l3_FSM_FFd1_13684,
      I1 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I2 => curr_state_l1_FSM_FFd1_13664,
      I3 => curr_state_l2_FSM_FFd1_13674,
      O => N6
    );
  pipe_rx_data_l0_out_not000111 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => curr_state_l6_FSM_FFd1_13712,
      I1 => curr_state_l4_FSM_FFd1_13693,
      I2 => curr_state_l5_FSM_FFd1_13702,
      I3 => curr_state_l7_FSM_FFd1_13722,
      O => N7
    );
  pipe_rx_data_l7_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l7_FSM_FFd1_13722,
      I1 => curr_state_l5_FSM_FFd1_13702,
      I2 => curr_state_l4_FSM_FFd1_13693,
      I3 => curr_state_l6_FSM_FFd1_13712,
      I4 => N6,
      O => pipe_rx_data_l7_out_not0001
    );
  pipe_rx_data_l6_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l6_FSM_FFd1_13712,
      I1 => curr_state_l4_FSM_FFd1_13693,
      I2 => curr_state_l5_FSM_FFd1_13702,
      I3 => curr_state_l7_FSM_FFd1_13722,
      I4 => N6,
      O => pipe_rx_data_l6_out_not0001
    );
  pipe_rx_data_l5_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l5_FSM_FFd1_13702,
      I1 => curr_state_l7_FSM_FFd1_13722,
      I2 => curr_state_l4_FSM_FFd1_13693,
      I3 => curr_state_l6_FSM_FFd1_13712,
      I4 => N6,
      O => pipe_rx_data_l5_out_not0001
    );
  pipe_rx_data_l4_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l4_FSM_FFd1_13693,
      I1 => curr_state_l5_FSM_FFd1_13702,
      I2 => curr_state_l6_FSM_FFd1_13712,
      I3 => curr_state_l7_FSM_FFd1_13722,
      I4 => N6,
      O => pipe_rx_data_l4_out_not0001
    );
  pipe_rx_data_l3_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l3_FSM_FFd1_13684,
      I1 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I2 => curr_state_l1_FSM_FFd1_13664,
      I3 => curr_state_l2_FSM_FFd1_13674,
      I4 => N7,
      O => pipe_rx_data_l3_out_not0001
    );
  pipe_rx_data_l2_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l2_FSM_FFd1_13674,
      I1 => curr_state_l1_FSM_FFd1_13664,
      I2 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I3 => curr_state_l3_FSM_FFd1_13684,
      I4 => N7,
      O => pipe_rx_data_l2_out_not0001
    );
  pipe_rx_data_l1_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => curr_state_l1_FSM_FFd1_13664,
      I1 => curr_state_l2_FSM_FFd1_13674,
      I2 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I3 => curr_state_l3_FSM_FFd1_13684,
      I4 => N7,
      O => pipe_rx_data_l1_out_not0001
    );
  pipe_rx_data_l0_out_not00011 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I1 => curr_state_l1_FSM_FFd1_13664,
      I2 => curr_state_l2_FSM_FFd1_13674,
      I3 => curr_state_l3_FSM_FFd1_13684,
      I4 => N7,
      O => pipe_rx_data_l0_out_not0001
    );
  curr_state_l7_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l7_FSM_FFd4_13726,
      I1 => pipe_rx_data_k(7),
      I2 => curr_state_l7_cmp_eq0001_13730,
      O => curr_state_l7_FSM_FFd3_In
    );
  curr_state_l6_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l6_FSM_FFd4_13716,
      I1 => pipe_rx_data_k(6),
      I2 => curr_state_l6_cmp_eq0001,
      O => curr_state_l6_FSM_FFd3_In
    );
  curr_state_l5_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l5_FSM_FFd4_13706,
      I1 => pipe_rx_data_k(5),
      I2 => curr_state_l5_cmp_eq0001,
      O => curr_state_l5_FSM_FFd3_In
    );
  curr_state_l4_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l4_FSM_FFd4_13697,
      I1 => pipe_rx_data_k(4),
      I2 => curr_state_l4_cmp_eq0001_13701,
      O => curr_state_l4_FSM_FFd3_In
    );
  curr_state_l3_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l3_FSM_FFd4_13688,
      I1 => pipe_rx_data_k(3),
      I2 => curr_state_l3_cmp_eq0001_13692,
      O => curr_state_l3_FSM_FFd3_In
    );
  curr_state_l2_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l2_FSM_FFd4_13678,
      I1 => pipe_rx_data_k(2),
      I2 => curr_state_l2_cmp_eq0001,
      O => curr_state_l2_FSM_FFd3_In
    );
  curr_state_l1_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l1_FSM_FFd4_13668,
      I1 => pipe_rx_data_k(1),
      I2 => curr_state_l1_cmp_eq0001,
      O => curr_state_l1_FSM_FFd3_In
    );
  curr_state_l0_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => curr_state_l0_FSM_FFd4_13659,
      I1 => pipe_rx_data_k(0),
      I2 => curr_state_l0_cmp_eq0004_13663,
      O => curr_state_l0_FSM_FFd3_In
    );
  curr_state_l0_FSM_FFd4_In11 : LUT4
    generic map(
      INIT => X"0242"
    )
    port map (
      I0 => l0_ltssm_state_d(1),
      I1 => l0_ltssm_state_d(2),
      I2 => l0_ltssm_state_d(3),
      I3 => l0_ltssm_state_d(0),
      O => N11
    );
  curr_state_l7_cmp_eq0001_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => pipe_rx_data_l7(2),
      I1 => pipe_rx_data_l7(1),
      I2 => pipe_rx_data_l7(0),
      I3 => pipe_rx_data_k(7),
      O => N8
    );
  curr_state_l7_cmp_eq0001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l7(7),
      I1 => pipe_rx_data_l7(6),
      I2 => pipe_rx_data_l7(5),
      I3 => pipe_rx_data_l7(4),
      I4 => pipe_rx_data_l7(3),
      I5 => N8,
      O => curr_state_l7_cmp_eq0001_13730
    );
  curr_state_l4_cmp_eq0001_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => pipe_rx_data_l4(2),
      I1 => pipe_rx_data_l4(1),
      I2 => pipe_rx_data_l4(0),
      I3 => pipe_rx_data_k(4),
      O => N10
    );
  curr_state_l4_cmp_eq0001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l4(7),
      I1 => pipe_rx_data_l4(6),
      I2 => pipe_rx_data_l4(5),
      I3 => pipe_rx_data_l4(4),
      I4 => pipe_rx_data_l4(3),
      I5 => N10,
      O => curr_state_l4_cmp_eq0001_13701
    );
  curr_state_l3_cmp_eq0001_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => pipe_rx_data_l3(2),
      I1 => pipe_rx_data_l3(1),
      I2 => pipe_rx_data_l3(0),
      I3 => pipe_rx_data_k(3),
      O => N12
    );
  curr_state_l3_cmp_eq0001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l3(7),
      I1 => pipe_rx_data_l3(6),
      I2 => pipe_rx_data_l3(5),
      I3 => pipe_rx_data_l3(4),
      I4 => pipe_rx_data_l3(3),
      I5 => N12,
      O => curr_state_l3_cmp_eq0001_13692
    );
  curr_state_l0_cmp_eq0004_SW0 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => pipe_rx_data_l0(2),
      I1 => pipe_rx_data_l0(1),
      I2 => pipe_rx_data_l0(0),
      I3 => pipe_rx_data_k(0),
      O => N14
    );
  curr_state_l0_cmp_eq0004 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l0(7),
      I1 => pipe_rx_data_l0(6),
      I2 => pipe_rx_data_l0(5),
      I3 => pipe_rx_data_l0(4),
      I4 => pipe_rx_data_l0(3),
      I5 => N14,
      O => curr_state_l0_cmp_eq0004_13663
    );
  curr_state_l6_cmp_eq00011 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => pipe_rx_data_l6(0),
      I1 => pipe_rx_data_l6(1),
      I2 => pipe_rx_data_l6(3),
      I3 => pipe_rx_data_l6(6),
      I4 => N20,
      O => curr_state_l6_cmp_eq0001
    );
  curr_state_l6_cmp_eq000011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => pipe_rx_data_k(6),
      I1 => pipe_rx_data_l6(7),
      I2 => pipe_rx_data_l6(5),
      I3 => pipe_rx_data_l6(4),
      I4 => pipe_rx_data_l6(2),
      O => N20
    );
  curr_state_l5_cmp_eq00011 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => pipe_rx_data_l5(0),
      I1 => pipe_rx_data_l5(1),
      I2 => pipe_rx_data_l5(3),
      I3 => pipe_rx_data_l5(6),
      I4 => N211,
      O => curr_state_l5_cmp_eq0001
    );
  curr_state_l5_cmp_eq000011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => pipe_rx_data_k(5),
      I1 => pipe_rx_data_l5(7),
      I2 => pipe_rx_data_l5(5),
      I3 => pipe_rx_data_l5(4),
      I4 => pipe_rx_data_l5(2),
      O => N211
    );
  curr_state_l2_cmp_eq00011 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => pipe_rx_data_l2(0),
      I1 => pipe_rx_data_l2(1),
      I2 => pipe_rx_data_l2(3),
      I3 => pipe_rx_data_l2(6),
      I4 => N22,
      O => curr_state_l2_cmp_eq0001
    );
  curr_state_l2_cmp_eq000011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => pipe_rx_data_k(2),
      I1 => pipe_rx_data_l2(7),
      I2 => pipe_rx_data_l2(4),
      I3 => pipe_rx_data_l2(5),
      I4 => pipe_rx_data_l2(2),
      O => N22
    );
  curr_state_l1_cmp_eq00011 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => pipe_rx_data_l1(0),
      I1 => pipe_rx_data_l1(1),
      I2 => pipe_rx_data_l1(3),
      I3 => pipe_rx_data_l1(6),
      I4 => N23,
      O => curr_state_l1_cmp_eq0001
    );
  curr_state_l1_cmp_eq000011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => pipe_rx_data_k(1),
      I1 => pipe_rx_data_l1(7),
      I2 => pipe_rx_data_l1(5),
      I3 => pipe_rx_data_l1(4),
      I4 => pipe_rx_data_l1(2),
      O => N23
    );
  pipe_rx_data_l7_out_or0001_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      I1 => curr_state_l3_FSM_FFd1_13684,
      I2 => curr_state_l2_FSM_FFd1_13674,
      O => N161
    );
  pipe_rx_data_l7_out_or0001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => curr_state_l7_FSM_FFd1_13722,
      I1 => curr_state_l6_FSM_FFd1_13712,
      I2 => curr_state_l5_FSM_FFd1_13702,
      I3 => curr_state_l4_FSM_FFd1_13693,
      I4 => curr_state_l1_FSM_FFd1_13664,
      I5 => N161,
      O => pipe_rx_data_l7_out_or0001_13983
    );
  curr_state_l6_FSM_FFd5_In_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => pipe_rx_data_l6(3),
      I1 => pipe_rx_data_l6(0),
      I2 => pipe_rx_data_l6(6),
      I3 => N20,
      I4 => N11,
      I5 => pipe_rx_data_l6(1),
      O => N301
    );
  curr_state_l6_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => curr_state_l6_FSM_FFd4_13716,
      I1 => pipe_rx_data_k(6),
      I2 => curr_state_l6_cmp_eq0001,
      I3 => curr_state_l6_FSM_FFd5_13719,
      I4 => N301,
      I5 => curr_state_l6_FSM_FFd1_13712,
      O => curr_state_l6_FSM_FFd5_In_13720
    );
  curr_state_l5_FSM_FFd5_In_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => pipe_rx_data_l5(3),
      I1 => pipe_rx_data_l5(0),
      I2 => pipe_rx_data_l5(6),
      I3 => N211,
      I4 => N11,
      I5 => pipe_rx_data_l5(1),
      O => N32
    );
  curr_state_l5_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => curr_state_l5_FSM_FFd4_13706,
      I1 => pipe_rx_data_k(5),
      I2 => curr_state_l5_cmp_eq0001,
      I3 => curr_state_l5_FSM_FFd5_13709,
      I4 => N32,
      I5 => curr_state_l5_FSM_FFd1_13702,
      O => curr_state_l5_FSM_FFd5_In_13710
    );
  curr_state_l2_FSM_FFd5_In_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => pipe_rx_data_l2(3),
      I1 => pipe_rx_data_l2(0),
      I2 => pipe_rx_data_l2(6),
      I3 => N22,
      I4 => N11,
      I5 => pipe_rx_data_l2(1),
      O => N34
    );
  curr_state_l2_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => curr_state_l2_FSM_FFd4_13678,
      I1 => pipe_rx_data_k(2),
      I2 => curr_state_l2_cmp_eq0001,
      I3 => curr_state_l2_FSM_FFd5_13681,
      I4 => N34,
      I5 => curr_state_l2_FSM_FFd1_13674,
      O => curr_state_l2_FSM_FFd5_In_13682
    );
  curr_state_l1_FSM_FFd5_In_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => pipe_rx_data_l1(3),
      I1 => pipe_rx_data_l1(0),
      I2 => pipe_rx_data_l1(6),
      I3 => N23,
      I4 => N11,
      I5 => pipe_rx_data_l1(1),
      O => N36
    );
  curr_state_l1_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => curr_state_l1_FSM_FFd4_13668,
      I1 => pipe_rx_data_k(1),
      I2 => curr_state_l1_cmp_eq0001,
      I3 => curr_state_l1_FSM_FFd5_13671,
      I4 => N36,
      I5 => curr_state_l1_FSM_FFd1_13664,
      O => curr_state_l1_FSM_FFd5_In_13672
    );
  dllp_ack_l7_reverse_and000011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l7(4),
      I1 => pipe_rx_data_l7(2),
      I2 => pipe_rx_data_l7(3),
      I3 => pipe_rx_data_k(7),
      I4 => pipe_rx_data_l7(0),
      I5 => pipe_rx_data_l7(1),
      O => N16
    );
  dllp_ack_l0_and000011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l0(4),
      I1 => pipe_rx_data_l0(2),
      I2 => pipe_rx_data_l0(3),
      I3 => pipe_rx_data_k(0),
      I4 => pipe_rx_data_l0(0),
      I5 => pipe_rx_data_l0(1),
      O => N19
    );
  dllp_ack_l0_and000021 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => trn_lnk_up_n_d_14009,
      I1 => negotiated_link_width_d(3),
      O => N30
    );
  pipe_rx_valid_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(7),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(7)
    );
  pipe_rx_valid_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(6),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(6)
    );
  pipe_rx_valid_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(5),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(5)
    );
  pipe_rx_valid_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(4),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(4)
    );
  pipe_rx_data_l7_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l7(1),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(6)
    );
  pipe_rx_data_l6_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l6(1),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(6)
    );
  pipe_rx_data_l5_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l5(1),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(6)
    );
  pipe_rx_data_l4_out_mux0000_6_2 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l4(1),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(6)
    );
  pipe_rx_data_k_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(7),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(7)
    );
  pipe_rx_data_k_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(6),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(6)
    );
  pipe_rx_data_k_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(5),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(5)
    );
  pipe_rx_data_k_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(4),
      I1 => N28,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(4)
    );
  dllp_ack_l4_and000011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l4(4),
      I1 => pipe_rx_data_l4(2),
      I2 => pipe_rx_data_l4(3),
      I3 => pipe_rx_data_k(4),
      I4 => pipe_rx_data_l4(0),
      I5 => pipe_rx_data_l4(1),
      O => N18
    );
  dllp_ack_l3_reverse_and000011 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l3(4),
      I1 => pipe_rx_data_l3(2),
      I2 => pipe_rx_data_l3(3),
      I3 => pipe_rx_data_k(3),
      I4 => pipe_rx_data_l3(0),
      I5 => pipe_rx_data_l3(1),
      O => N17
    );
  pipe_rx_valid_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(3),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(3)
    );
  pipe_rx_valid_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(2),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(2)
    );
  pipe_rx_valid_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(1)
    );
  pipe_rx_valid_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_valid(0),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_valid_out_mux0000(0)
    );
  pipe_rx_data_l3_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l3(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(6)
    );
  pipe_rx_data_l2_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l2(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(6)
    );
  pipe_rx_data_l1_out_mux0000_6_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l1(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(6)
    );
  pipe_rx_data_l0_out_mux0000_6_2 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => pipe_rx_data_l0(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(6)
    );
  pipe_rx_data_k_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(3),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(3)
    );
  pipe_rx_data_k_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(2),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(2)
    );
  pipe_rx_data_k_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(1),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(1)
    );
  pipe_rx_data_k_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pipe_rx_data_k(0),
      I1 => N29,
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_k_out_mux0000(0)
    );
  dllp_ack_l7_reverse_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => N16,
      I1 => N30,
      I2 => dllp_ack_l4_cmp_eq0001,
      I3 => pipe_rx_data_l7(6),
      I4 => pipe_rx_data_l7(5),
      I5 => pipe_rx_data_l7(7),
      O => dllp_ack_l7_reverse
    );
  dllp_ack_l0_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => N19,
      I1 => N30,
      I2 => dllp_ack_l0_cmp_eq0001,
      I3 => pipe_rx_data_l0(6),
      I4 => pipe_rx_data_l0(5),
      I5 => pipe_rx_data_l0(7),
      O => dllp_ack_l0
    );
  pipe_rx_data_l4_out_mux0000_6_11 : LUT6
    generic map(
      INIT => X"0001001101011111"
    )
    port map (
      I0 => dllp_ack_l3_reverse_rr_13738,
      I1 => dllp_ack_l4_rr_and0000,
      I2 => dllp_ack_l0_r_13735,
      I3 => dllp_ack_l7_reverse_r_13748,
      I4 => dllp_ack_l0,
      I5 => dllp_ack_l7_reverse,
      O => N28
    );
  dllp_ack_l4_rr_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dllp_ack_l4,
      I1 => dllp_ack_l4_r_13744,
      O => dllp_ack_l4_rr_and0000
    );
  dllp_ack_l3_reverse_rr_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dllp_ack_l3_reverse,
      I1 => dllp_ack_l3_reverse_r_13737,
      O => dllp_ack_l3_reverse_rr_and0000
    );
  dllp_ack_l4_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => N18,
      I1 => N30,
      I2 => dllp_ack_l4_cmp_eq0001,
      I3 => pipe_rx_data_l4(6),
      I4 => pipe_rx_data_l4(5),
      I5 => pipe_rx_data_l4(7),
      O => dllp_ack_l4
    );
  dllp_ack_l3_reverse_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => N17,
      I1 => N30,
      I2 => dllp_ack_l0_cmp_eq0001,
      I3 => pipe_rx_data_l3(6),
      I4 => pipe_rx_data_l3(5),
      I5 => pipe_rx_data_l3(7),
      O => dllp_ack_l3_reverse
    );
  pipe_rx_data_l0_out_mux0000_6_1 : LUT6
    generic map(
      INIT => X"115533FF0105030F"
    )
    port map (
      I0 => dllp_ack_l7_reverse_r_13748,
      I1 => dllp_ack_l0_r_13735,
      I2 => N38,
      I3 => dllp_ack_l0,
      I4 => dllp_ack_l7_reverse,
      I5 => dllp_ack_l3_reverse_rr_13738,
      O => N29
    );
  dllp_ack_l4_cmp_eq0001849 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => pipe_rx_data_l5(2),
      I1 => pipe_rx_data_l6(2),
      I2 => pipe_rx_data_l5(3),
      I3 => pipe_rx_data_l6(3),
      I4 => pipe_rx_data_l5(4),
      I5 => pipe_rx_data_l6(4),
      O => dllp_ack_l4_cmp_eq0001849_13743
    );
  dllp_ack_l4_cmp_eq00018126 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => pipe_rx_data_l5(7),
      I1 => pipe_rx_data_l6(7),
      I2 => pipe_rx_data_l5(0),
      I3 => pipe_rx_data_l6(0),
      I4 => pipe_rx_data_l5(1),
      I5 => pipe_rx_data_l6(1),
      O => dllp_ack_l4_cmp_eq00018126_13742
    );
  dllp_ack_l0_cmp_eq0001849 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => pipe_rx_data_l1(2),
      I1 => pipe_rx_data_l2(2),
      I2 => pipe_rx_data_l1(3),
      I3 => pipe_rx_data_l2(3),
      I4 => pipe_rx_data_l1(4),
      I5 => pipe_rx_data_l2(4),
      O => dllp_ack_l0_cmp_eq0001849_13734
    );
  dllp_ack_l0_cmp_eq00018126 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => pipe_rx_data_l1(7),
      I1 => pipe_rx_data_l2(7),
      I2 => pipe_rx_data_l1(0),
      I3 => pipe_rx_data_l2(0),
      I4 => pipe_rx_data_l1(1),
      I5 => pipe_rx_data_l2(1),
      O => dllp_ack_l0_cmp_eq00018126_13733
    );
  dllp_ack_l4_cmp_eq00018141 : LUT6
    generic map(
      INIT => X"9009000000000000"
    )
    port map (
      I0 => pipe_rx_data_l5(5),
      I1 => pipe_rx_data_l6(5),
      I2 => pipe_rx_data_l5(6),
      I3 => pipe_rx_data_l6(6),
      I4 => dllp_ack_l4_cmp_eq0001849_13743,
      I5 => dllp_ack_l4_cmp_eq00018126_13742,
      O => dllp_ack_l4_cmp_eq0001
    );
  dllp_ack_l0_cmp_eq00018141 : LUT6
    generic map(
      INIT => X"9009000000000000"
    )
    port map (
      I0 => pipe_rx_data_l1(5),
      I1 => pipe_rx_data_l2(5),
      I2 => pipe_rx_data_l1(6),
      I3 => pipe_rx_data_l2(6),
      I4 => dllp_ack_l0_cmp_eq0001849_13734,
      I5 => dllp_ack_l0_cmp_eq00018126_13733,
      O => dllp_ack_l0_cmp_eq0001
    );
  curr_state_l7_FSM_FFd5_In_SW2 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => N11,
      I1 => N16,
      I2 => pipe_rx_data_l7(5),
      I3 => pipe_rx_data_l7(6),
      I4 => pipe_rx_data_l7(7),
      O => N40
    );
  curr_state_l7_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => pipe_rx_data_k(7),
      I1 => curr_state_l7_FSM_FFd4_13726,
      I2 => curr_state_l7_cmp_eq0001_13730,
      I3 => N40,
      I4 => curr_state_l7_FSM_FFd5_13728,
      I5 => curr_state_l7_FSM_FFd1_13722,
      O => curr_state_l7_FSM_FFd5_In_13729
    );
  curr_state_l4_FSM_FFd5_In_SW2 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => N11,
      I1 => N18,
      I2 => pipe_rx_data_l4(5),
      I3 => pipe_rx_data_l4(6),
      I4 => pipe_rx_data_l4(7),
      O => N42
    );
  curr_state_l4_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => pipe_rx_data_k(4),
      I1 => curr_state_l4_FSM_FFd4_13697,
      I2 => curr_state_l4_cmp_eq0001_13701,
      I3 => N42,
      I4 => curr_state_l4_FSM_FFd5_13699,
      I5 => curr_state_l4_FSM_FFd1_13693,
      O => curr_state_l4_FSM_FFd5_In_13700
    );
  curr_state_l3_FSM_FFd5_In_SW2 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => N11,
      I1 => N17,
      I2 => pipe_rx_data_l3(5),
      I3 => pipe_rx_data_l3(6),
      I4 => pipe_rx_data_l3(7),
      O => N44
    );
  curr_state_l3_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => pipe_rx_data_k(3),
      I1 => curr_state_l3_FSM_FFd4_13688,
      I2 => curr_state_l3_cmp_eq0001_13692,
      I3 => N44,
      I4 => curr_state_l3_FSM_FFd5_13690,
      I5 => curr_state_l3_FSM_FFd1_13684,
      O => curr_state_l3_FSM_FFd5_In_13691
    );
  curr_state_l0_FSM_FFd5_In_SW2 : LUT5
    generic map(
      INIT => X"FF7FFFFF"
    )
    port map (
      I0 => N11,
      I1 => N19,
      I2 => pipe_rx_data_l0(5),
      I3 => pipe_rx_data_l0(6),
      I4 => pipe_rx_data_l0(7),
      O => N46
    );
  curr_state_l0_FSM_FFd5_In : LUT6
    generic map(
      INIT => X"FFFFFFFFFF080808"
    )
    port map (
      I0 => pipe_rx_data_k(0),
      I1 => curr_state_l0_FSM_FFd4_13659,
      I2 => curr_state_l0_cmp_eq0004_13663,
      I3 => N46,
      I4 => curr_state_l0_FSM_FFd5_13661,
      I5 => NlwRenamedSig_OI_curr_state_l0_FSM_FFd1,
      O => curr_state_l0_FSM_FFd5_In_13662
    );
  pipe_rx_data_l7_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(7)
    );
  pipe_rx_data_l7_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(5)
    );
  pipe_rx_data_l7_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(4)
    );
  pipe_rx_data_l7_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(3)
    );
  pipe_rx_data_l7_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(2)
    );
  pipe_rx_data_l7_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(1)
    );
  pipe_rx_data_l7_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l7(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l7_out_mux0000(0)
    );
  pipe_rx_data_l6_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(7)
    );
  pipe_rx_data_l6_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(5)
    );
  pipe_rx_data_l6_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(4)
    );
  pipe_rx_data_l6_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(3)
    );
  pipe_rx_data_l6_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(2)
    );
  pipe_rx_data_l6_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(1)
    );
  pipe_rx_data_l6_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l6(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l6_out_mux0000(0)
    );
  pipe_rx_data_l5_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(7)
    );
  pipe_rx_data_l5_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(5)
    );
  pipe_rx_data_l5_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(4)
    );
  pipe_rx_data_l5_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(3)
    );
  pipe_rx_data_l5_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(2)
    );
  pipe_rx_data_l5_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(1)
    );
  pipe_rx_data_l5_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l5(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l5_out_mux0000(0)
    );
  pipe_rx_data_l4_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(7)
    );
  pipe_rx_data_l4_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(5)
    );
  pipe_rx_data_l4_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(4)
    );
  pipe_rx_data_l4_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(3)
    );
  pipe_rx_data_l4_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(2)
    );
  pipe_rx_data_l4_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(1)
    );
  pipe_rx_data_l4_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N28,
      I1 => pipe_rx_data_l4(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l4_out_mux0000(0)
    );
  pipe_rx_data_l3_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(7)
    );
  pipe_rx_data_l3_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(5)
    );
  pipe_rx_data_l3_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(4)
    );
  pipe_rx_data_l3_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(3)
    );
  pipe_rx_data_l3_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(2)
    );
  pipe_rx_data_l3_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(1)
    );
  pipe_rx_data_l3_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l3(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l3_out_mux0000(0)
    );
  pipe_rx_data_l2_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(7)
    );
  pipe_rx_data_l2_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(5)
    );
  pipe_rx_data_l2_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(4)
    );
  pipe_rx_data_l2_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(3)
    );
  pipe_rx_data_l2_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(2)
    );
  pipe_rx_data_l2_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(1)
    );
  pipe_rx_data_l2_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l2(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l2_out_mux0000(0)
    );
  pipe_rx_data_l1_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(7)
    );
  pipe_rx_data_l1_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(5)
    );
  pipe_rx_data_l1_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(4)
    );
  pipe_rx_data_l1_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(3)
    );
  pipe_rx_data_l1_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(2)
    );
  pipe_rx_data_l1_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(1)
    );
  pipe_rx_data_l1_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l1(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l1_out_mux0000(0)
    );
  pipe_rx_data_l0_out_mux0000_7_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(0),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(7)
    );
  pipe_rx_data_l0_out_mux0000_5_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(2),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(5)
    );
  pipe_rx_data_l0_out_mux0000_4_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(3),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(4)
    );
  pipe_rx_data_l0_out_mux0000_3_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(4),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(3)
    );
  pipe_rx_data_l0_out_mux0000_2_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(5),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(2)
    );
  pipe_rx_data_l0_out_mux0000_1_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(6),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(1)
    );
  pipe_rx_data_l0_out_mux0000_0_1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N29,
      I1 => pipe_rx_data_l0(7),
      I2 => pipe_rx_data_l7_out_or0001_13983,
      O => pipe_rx_data_l0_out_mux0000(0)
    );
  pipe_rx_data_l0_out_mux0000_6_1_SW0 : LUT5
    generic map(
      INIT => X"3F2A2A2A"
    )
    port map (
      I0 => dllp_ack_l4_rr_13745,
      I1 => dllp_ack_l4,
      I2 => dllp_ack_l4_r_13744,
      I3 => dllp_ack_l3_reverse,
      I4 => dllp_ack_l3_reverse_r_13737,
      O => N38
    );
  bit_reset_n_inv1_INV_0 : INV
    port map (
      I => bit_reset_n,
      O => bit_reset_n_inv
    );
  XST_GND : GND
    port map (
      G => N49
    );
  curr_state_l6_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l6(3),
      I1 => N11,
      I2 => curr_state_l6_FSM_FFd5_13719,
      I3 => N20,
      I4 => pipe_rx_data_l6(1),
      I5 => pipe_rx_data_l6(0),
      O => curr_state_l6_FSM_FFd4_In1_13718
    );
  curr_state_l6_FSM_FFd4_In_f7 : MUXF7
    port map (
      I0 => curr_state_l6_FSM_FFd4_In1_13718,
      I1 => N49,
      S => pipe_rx_data_l6(6),
      O => curr_state_l6_FSM_FFd4_In
    );
  curr_state_l5_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l5(3),
      I1 => N11,
      I2 => curr_state_l5_FSM_FFd5_13709,
      I3 => N211,
      I4 => pipe_rx_data_l5(1),
      I5 => pipe_rx_data_l5(0),
      O => curr_state_l5_FSM_FFd4_In1_13708
    );
  curr_state_l5_FSM_FFd4_In_f7 : MUXF7
    port map (
      I0 => curr_state_l5_FSM_FFd4_In1_13708,
      I1 => N49,
      S => pipe_rx_data_l5(6),
      O => curr_state_l5_FSM_FFd4_In
    );
  curr_state_l2_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l2(3),
      I1 => N11,
      I2 => curr_state_l2_FSM_FFd5_13681,
      I3 => N22,
      I4 => pipe_rx_data_l2(1),
      I5 => pipe_rx_data_l2(0),
      O => curr_state_l2_FSM_FFd4_In1_13680
    );
  curr_state_l2_FSM_FFd4_In_f7 : MUXF7
    port map (
      I0 => curr_state_l2_FSM_FFd4_In1_13680,
      I1 => N49,
      S => pipe_rx_data_l2(6),
      O => curr_state_l2_FSM_FFd4_In
    );
  curr_state_l1_FSM_FFd4_In1 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => pipe_rx_data_l1(3),
      I1 => N11,
      I2 => curr_state_l1_FSM_FFd5_13671,
      I3 => N23,
      I4 => pipe_rx_data_l1(1),
      I5 => pipe_rx_data_l1(0),
      O => curr_state_l1_FSM_FFd4_In1_13670
    );
  curr_state_l1_FSM_FFd4_In_f7 : MUXF7
    port map (
      I0 => curr_state_l1_FSM_FFd4_In1_13670,
      I1 => N49,
      S => pipe_rx_data_l1(6),
      O => curr_state_l1_FSM_FFd4_In
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_top_wrapper is
  port (
    llk_tx_src_rdy_n : in STD_LOGIC := 'X'; 
    l0_stats_tlp_received : out STD_LOGIC; 
    l0_set_user_system_error : in STD_LOGIC := 'X'; 
    l0_stats_os_transmitted : out STD_LOGIC; 
    llk_rx_eof_n : out STD_LOGIC; 
    l0_set_unexpected_completion_uncorr_error : in STD_LOGIC := 'X'; 
    l0_set_user_received_master_abort : in STD_LOGIC := 'X'; 
    llk_rx_src_rdy_n : out STD_LOGIC; 
    l0_set_detected_nonfatal_error : in STD_LOGIC := 'X'; 
    serr_enable : out STD_LOGIC; 
    llk_rx_dst_cont_req_n : in STD_LOGIC := 'X'; 
    l0_mac_rx_l0s_state : out STD_LOGIC; 
    l0_set_completer_abort_error : in STD_LOGIC := 'X'; 
    l0_mac_entered_l0 : out STD_LOGIC; 
    mgmt_rden : in STD_LOGIC := 'X'; 
    crm_link_rst_n : in STD_LOGIC := 'X'; 
    l0_cfg_loopback_master : in STD_LOGIC := 'X'; 
    l0_set_detected_corr_error : in STD_LOGIC := 'X'; 
    crm_nvrst_n : in STD_LOGIC := 'X'; 
    crm_do_hot_reset_n : out STD_LOGIC; 
    mgmt_wren : in STD_LOGIC := 'X'; 
    bus_master_enable : out STD_LOGIC; 
    l0_msi_enable0 : out STD_LOGIC; 
    llk_tx_sop_n : in STD_LOGIC := 'X'; 
    mgmt_rdy : out STD_LOGIC; 
    user_clk : out STD_LOGIC; 
    io_space_enable : out STD_LOGIC; 
    l0_pwr_turn_off_req : out STD_LOGIC; 
    parity_error_response : out STD_LOGIC; 
    llk_rx_dst_req_n : in STD_LOGIC := 'X'; 
    crm_urst_n : in STD_LOGIC := 'X'; 
    llk_rx_eop_n : out STD_LOGIC; 
    llk_rx_src_last_req_n : out STD_LOGIC; 
    l0_pme_req_in : in STD_LOGIC := 'X'; 
    GTPRESET : in STD_LOGIC := 'X'; 
    REFCLKOUT_bufg : out STD_LOGIC; 
    l0_stats_cfg_other_received : out STD_LOGIC; 
    interrupt_disable : out STD_LOGIC; 
    llk_rx_sof_n : out STD_LOGIC; 
    crm_mac_rst_n : in STD_LOGIC := 'X'; 
    GTPCLK_bufg : out STD_LOGIC; 
    l0_mac_link_training : out STD_LOGIC; 
    l0_set_user_master_data_parity : in STD_LOGIC := 'X'; 
    l0_stats_cfg_transmitted : out STD_LOGIC; 
    l0_mac_link_up : out STD_LOGIC; 
    crm_user_cfg_rst_n : in STD_LOGIC := 'X'; 
    l0_set_user_signalled_target_abort : in STD_LOGIC := 'X'; 
    l0_set_user_detected_parity_error : in STD_LOGIC := 'X'; 
    ur_reporting_enable : out STD_LOGIC; 
    l0_set_detected_fatal_error : in STD_LOGIC := 'X'; 
    l0_cfg_loopback_ack : out STD_LOGIC; 
    llk_tx_src_dsc_n : in STD_LOGIC := 'X'; 
    l0_set_completion_timeout_corr_error : in STD_LOGIC := 'X'; 
    REFCLK : in STD_LOGIC := 'X'; 
    clock_lock : out STD_LOGIC; 
    l0_transactions_pending : in STD_LOGIC := 'X'; 
    l0_stats_os_received : out STD_LOGIC; 
    l0_stats_dllp_transmitted : out STD_LOGIC; 
    l0_legacy_int_funct0 : in STD_LOGIC := 'X'; 
    l0_first_cfg_write_occurred : out STD_LOGIC; 
    core_clk : out STD_LOGIC; 
    fast_train_simulation_only : in STD_LOGIC := 'X'; 
    llk_tx_eof_n : in STD_LOGIC := 'X'; 
    llk_tx_dst_rdy_n : out STD_LOGIC; 
    llk_rx_sop_n : out STD_LOGIC; 
    user_reset_n : in STD_LOGIC := 'X'; 
    l0_stats_dllp_received : out STD_LOGIC; 
    l0_stats_cfg_received : out STD_LOGIC; 
    l0_stats_tlp_transmitted : out STD_LOGIC; 
    l0_pme_ack : out STD_LOGIC; 
    crm_pwr_soft_reset_n : out STD_LOGIC; 
    l0_pwr_tx_l0s_state : out STD_LOGIC; 
    l0_set_unexpected_completion_corr_error : in STD_LOGIC := 'X'; 
    mem_space_enable : out STD_LOGIC; 
    l0_pwr_l23_ready_state : out STD_LOGIC; 
    mgmt_reset_delay_n : in STD_LOGIC := 'X'; 
    l0_set_unsupported_request_other_error : in STD_LOGIC := 'X'; 
    l0_set_unsupported_request_nonposted_error : in STD_LOGIC := 'X'; 
    l0_set_completion_timeout_uncorr_error : in STD_LOGIC := 'X'; 
    gt_dclk : in STD_LOGIC := 'X'; 
    crm_mgmt_rst_n : in STD_LOGIC := 'X'; 
    l0_set_user_received_target_abort : in STD_LOGIC := 'X'; 
    l0_stats_cfg_other_transmitted : out STD_LOGIC; 
    llk_tx_eop_n : in STD_LOGIC := 'X'; 
    compliance_avoid : in STD_LOGIC := 'X'; 
    l0_mac_new_state_ack : out STD_LOGIC; 
    llk_tx_sof_n : in STD_LOGIC := 'X'; 
    trn_lnk_up_n : in STD_LOGIC := 'X'; 
    l0_pwr_state0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_rx_ch_posted_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tx_ch_non_posted_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    DEBUG : out STD_LOGIC_VECTOR ( 338 downto 0 ); 
    llk_rx_ch_non_posted_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    l0_ltssm_state : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    llk_rx_ch_completion_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_valid_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    RESETDONE : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_rx_preferred_type : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    l0_dl_up_down : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    llk_tc_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    mgmt_pso : out STD_LOGIC_VECTOR ( 16 downto 0 ); 
    l0_dll_error_vector : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    llk_tx_ch_posted_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    l0_rx_mac_link_error : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    max_payload_size : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    TXN : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    TXP : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    PLLLKDET_OUT : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    llk_tx_chan_space : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    mgmt_stats_credit : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    l0_multi_msg_en0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    mgmt_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    llk_tx_ch_completion_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    max_read_request_size : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
    l0_mac_negotiated_link_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    l0_completer_id : out STD_LOGIC_VECTOR ( 12 downto 0 ); 
    llk_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    mgmt_bwren : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    mgmt_addr : in STD_LOGIC_VECTOR ( 10 downto 0 ); 
    gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    l0_msi_request0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    RXN : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    RXP : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
    llk_tx_ch_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    llk_tx_ch_fifo : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
    llk_tx_enable_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    llk_rx_ch_fifo : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    mgmt_stats_credit_sel : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    llk_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    llk_rx_ch_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    mgmt_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end pcie_top_wrapper;

architecture STRUCTURE of pcie_top_wrapper is
  component prod_fixes
    port (
      clk : in STD_LOGIC := 'X'; 
      chan_bond_done : in STD_LOGIC := 'X'; 
      bit_reset_n : in STD_LOGIC := 'X'; 
      upcfgcap_cycle : out STD_LOGIC; 
      masking_ack : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      pipe_rx_data_l2_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_k_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l7_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l3_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l4_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l0_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l5_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l1_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_valid_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l6_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      negotiated_link_width : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      pipe_rx_data_l0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_l6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      l0_ltssm_state : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      pipe_rx_data_l7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_valid : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pipe_rx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  component reset_logic
    port (
      CRMPWRSOFTRESETN : in STD_LOGIC := 'X'; 
      CRMLINKRSTN : out STD_LOGIC; 
      CRMUSERCFGRSTN : out STD_LOGIC; 
      CRMURSTN : out STD_LOGIC; 
      user_master_reset_n : in STD_LOGIC := 'X'; 
      L0STATSCFGTRANSMITTED : in STD_LOGIC := 'X'; 
      CRMNVRSTN : out STD_LOGIC; 
      L0DLUPDOWN : in STD_LOGIC := 'X'; 
      CRMCORECLK : in STD_LOGIC := 'X'; 
      CRMMACRSTN : out STD_LOGIC; 
      clock_ready : in STD_LOGIC := 'X'; 
      CRMDOHOTRESETN : in STD_LOGIC := 'X'; 
      CRMMGMTRSTN : out STD_LOGIC; 
      USERCLK : in STD_LOGIC := 'X'; 
      L0LTSSMSTATE : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
    );
  end component;
  component pcie_clocking
    port (
      gtx_usrclk : out STD_LOGIC; 
      txsync_clk : out STD_LOGIC; 
      rst : in STD_LOGIC := 'X'; 
      clkin_pll : in STD_LOGIC := 'X'; 
      fast_train_simulation_only : in STD_LOGIC := 'X'; 
      coreclk : out STD_LOGIC; 
      locked : out STD_LOGIC; 
      clkin_dcm : in STD_LOGIC := 'X'; 
      userclk : out STD_LOGIC 
    );
  end component;
  component pcie_mim_wrapper
    port (
      mim_tx_bwclk : in STD_LOGIC := 'X'; 
      mim_tx_bren : in STD_LOGIC := 'X'; 
      mim_rx_bren : in STD_LOGIC := 'X'; 
      mim_rx_brclk : in STD_LOGIC := 'X'; 
      mim_dll_bren : in STD_LOGIC := 'X'; 
      mim_rx_bwclk : in STD_LOGIC := 'X'; 
      mim_dll_bclk : in STD_LOGIC := 'X'; 
      mim_tx_bwen : in STD_LOGIC := 'X'; 
      mim_tx_brclk : in STD_LOGIC := 'X'; 
      mim_rx_bwen : in STD_LOGIC := 'X'; 
      mim_dll_bwen : in STD_LOGIC := 'X'; 
      mim_tx_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_rx_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_dll_brdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_dll_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_dll_bwadd : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      mim_tx_bradd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      mim_tx_bwadd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      mim_rx_bradd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      mim_tx_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_rx_bwadd : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      mim_rx_bwdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mim_dll_bradd : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  component pcie_gt_wrapper_top
    port (
      gtclk_bufg : out STD_LOGIC; 
      txsync_clk : in STD_LOGIC := 'X'; 
      gt_usrclk : in STD_LOGIC := 'X'; 
      refclkout_bufg : out STD_LOGIC; 
      gtreset : in STD_LOGIC := 'X'; 
      pcie_reset : out STD_LOGIC; 
      refclk : in STD_LOGIC := 'X'; 
      clock_lock : in STD_LOGIC := 'X'; 
      gt_usrclk2 : in STD_LOGIC := 'X'; 
      gt_dclk : in STD_LOGIC := 'X'; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      gt_rx_chanisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_elec_idle : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxchanbondseq : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      resetdone : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_valid : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_data_k : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxbyteisaligned : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_tx_p : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_status : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
      plllkdet_out : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
      gt_rx_phy_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_elec_idle : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_data_k : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_rx_p : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_deskew_lanes : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
      gt_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_tx_compliance : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_pipe_reset : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_tx_detect_rx_loopback : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
      gt_power_down : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      gt_rx_polarity : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_GTPCLK_bufg : STD_LOGIC; 
  signal NlwRenamedSig_OI_REFCLKOUT_bufg : STD_LOGIC; 
  signal NlwRenamedSig_OI_clock_lock : STD_LOGIC; 
  signal clocking_i_not0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_core_clk : STD_LOGIC; 
  signal NlwRenamedSig_OI_crm_do_hot_reset_n : STD_LOGIC; 
  signal NlwRenamedSig_OI_crm_pwr_soft_reset_n : STD_LOGIC; 
  signal d_user_reset_n_inv : STD_LOGIC; 
  signal gt_usrclk : STD_LOGIC; 
  signal NlwRenamedSig_OI_l0_stats_cfg_transmitted : STD_LOGIC; 
  signal NlwRenamedSig_OI_mgmt_rdy : STD_LOGIC; 
  signal pcie_reset : STD_LOGIC; 
  signal pipe_deskew_lanes_l0 : STD_LOGIC; 
  signal pipe_deskew_lanes_l1 : STD_LOGIC; 
  signal pipe_deskew_lanes_l2 : STD_LOGIC; 
  signal pipe_deskew_lanes_l3 : STD_LOGIC; 
  signal pipe_deskew_lanes_l4 : STD_LOGIC; 
  signal pipe_deskew_lanes_l5 : STD_LOGIC; 
  signal pipe_deskew_lanes_l6 : STD_LOGIC; 
  signal pipe_deskew_lanes_l7 : STD_LOGIC; 
  signal pipe_reset_l0 : STD_LOGIC; 
  signal pipe_reset_l1 : STD_LOGIC; 
  signal pipe_reset_l2 : STD_LOGIC; 
  signal pipe_reset_l3 : STD_LOGIC; 
  signal pipe_reset_l4 : STD_LOGIC; 
  signal pipe_reset_l5 : STD_LOGIC; 
  signal pipe_reset_l6 : STD_LOGIC; 
  signal pipe_reset_l7 : STD_LOGIC; 
  signal pipe_rx_polarity_l0 : STD_LOGIC; 
  signal pipe_rx_polarity_l1 : STD_LOGIC; 
  signal pipe_rx_polarity_l2 : STD_LOGIC; 
  signal pipe_rx_polarity_l3 : STD_LOGIC; 
  signal pipe_rx_polarity_l4 : STD_LOGIC; 
  signal pipe_rx_polarity_l5 : STD_LOGIC; 
  signal pipe_rx_polarity_l6 : STD_LOGIC; 
  signal pipe_rx_polarity_l7 : STD_LOGIC; 
  signal pipe_tx_compliance_l0 : STD_LOGIC; 
  signal pipe_tx_compliance_l1 : STD_LOGIC; 
  signal pipe_tx_compliance_l2 : STD_LOGIC; 
  signal pipe_tx_compliance_l3 : STD_LOGIC; 
  signal pipe_tx_compliance_l4 : STD_LOGIC; 
  signal pipe_tx_compliance_l5 : STD_LOGIC; 
  signal pipe_tx_compliance_l6 : STD_LOGIC; 
  signal pipe_tx_compliance_l7 : STD_LOGIC; 
  signal pipe_tx_data_k_l0 : STD_LOGIC; 
  signal pipe_tx_data_k_l1 : STD_LOGIC; 
  signal pipe_tx_data_k_l2 : STD_LOGIC; 
  signal pipe_tx_data_k_l3 : STD_LOGIC; 
  signal pipe_tx_data_k_l4 : STD_LOGIC; 
  signal pipe_tx_data_k_l5 : STD_LOGIC; 
  signal pipe_tx_data_k_l6 : STD_LOGIC; 
  signal pipe_tx_data_k_l7 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l0 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l1 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l2 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l3 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l4 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l5 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l6 : STD_LOGIC; 
  signal pipe_tx_detect_rx_loopback_l7 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l0 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l1 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l2 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l3 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l4 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l5 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l6 : STD_LOGIC; 
  signal pipe_tx_elec_idle_l7 : STD_LOGIC; 
  signal rb_crm_link_rst_n : STD_LOGIC; 
  signal rb_crm_mac_rst_n : STD_LOGIC; 
  signal rb_crm_nvrst_n : STD_LOGIC; 
  signal rb_crm_urst_n : STD_LOGIC; 
  signal rb_crm_user_cfg_rst_n : STD_LOGIC; 
  signal reg_enable_ltssm_reset_18589 : STD_LOGIC; 
  signal reg_enable_ltssm_reset_mux0000 : STD_LOGIC; 
  signal reg_enable_ltssm_reset_not0001 : STD_LOGIC; 
  signal reg_ltssm_reset_and0000 : STD_LOGIC; 
  signal trn_reset_n : STD_LOGIC; 
  signal txsync_clk : STD_LOGIC; 
  signal NlwRenamedSig_OI_user_clk : STD_LOGIC; 
  signal user_reset_workaround_n : STD_LOGIC; 
  signal usrclk : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxchanbondseq_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_SIO_rxbyteisaligned_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_prod_fixes_I_chan_bond_done_UNCONNECTED : STD_LOGIC; 
  signal NLW_prod_fixes_I_upcfgcap_cycle_UNCONNECTED : STD_LOGIC; 
  signal NLW_prod_fixes_I_masking_ack_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_CRMRXHOTRESETN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKTXCONFIGREADYN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXSRCDSCN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCONFIGAVAILABLEN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCONFIGPARTIALN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRX4DWHEADERN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXECRCBADN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLTLPECRCOK_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_DLLTXPMDLLPOUTSTANDING_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0MACUPSTREAMDOWNSTREAM_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLASTXSTATE_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ASAUTONOMOUSINITCOMPLETED_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UNLOCKRECEIVED_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0CORRERRMSGRCVD_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0FATALERRMSGRCVD_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0NONFATALERRMSGRCVD_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0FWDCORRERROUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0FWDFATALERROUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0FWDNONFATALERROUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDASSERTINTALEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDASSERTINTBLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDASSERTINTCLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDASSERTINTDLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDDEASSERTINTALEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDDEASSERTINTBLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDDEASSERTINTCLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RECEIVEDDEASSERTINTDLEGACYINT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0POWERCONTROLLERCONTROL_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TOGGLEELECTROMECHANICALINTERLOCK_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXBEACON_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0PMEREQOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0PMEEN_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0PWRINHIBITTRANSFERS_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0PWRL1STATE_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0PWRL23READYDEVICE_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLPM_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLPMUPDATED_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLRXACKOUTSTANDING_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLTXOUTSTANDING_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLTXNONFCOUTSTANDING_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLSBFCUPDATED_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCUPDATE_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLVCSTATUS_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLASRXSTATE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0DLLASRXSTATE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ERRMSGREQID_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ATTENTIONINDICATORCONTROL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0ATTENTIONINDICATORCONTROL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0POWERINDICATORCONTROL_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0POWERINDICATORCONTROL_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLPMTYPE_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLPMTYPE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLPMTYPE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLTLPEND_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLTLPEND_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLSBFCDATA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCBYPFOUND_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCBYPFOUND_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCBYPFOUND_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCBYPFOUND_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCORDFOUND_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCORDFOUND_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCORDFOUND_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0UCORDFOUND_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0MCFOUND_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0MCFOUND_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0MCFOUND_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TRANSFORMEDVC_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TRANSFORMEDVC_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep_L0TRANSFORMEDVC_0_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSig_OI_DEBUG : STD_LOGIC_VECTOR ( 338 downto 0 ); 
  signal NlwRenamedSig_OI_PLLLKDET_OUT : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_l0_dl_up_down : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSig_OI_l0_ltssm_state : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_l0_mac_negotiated_link_width : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal mim_rx_brdata : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal mim_tx_brdata : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pipe_power_down_l0 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l3 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l4 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l5 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l6 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_power_down_l7 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pipe_rx_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pipe_rx_data_k : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_k_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l0_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l1_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l2_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l3_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l4_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l5_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l6_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_data_l7_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_elec_idle : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_phy_status : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_status : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal pipe_rx_valid : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rx_valid_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_rxchanisaligned : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l4 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l5 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l6 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal pipe_tx_data_l7 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal reg_l0_ltssm_state_internal : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal reg_ltssm_reset : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  crm_do_hot_reset_n <= NlwRenamedSig_OI_crm_do_hot_reset_n;
  mgmt_rdy <= NlwRenamedSig_OI_mgmt_rdy;
  user_clk <= NlwRenamedSig_OI_user_clk;
  REFCLKOUT_bufg <= NlwRenamedSig_OI_REFCLKOUT_bufg;
  GTPCLK_bufg <= NlwRenamedSig_OI_GTPCLK_bufg;
  l0_stats_cfg_transmitted <= NlwRenamedSig_OI_l0_stats_cfg_transmitted;
  clock_lock <= NlwRenamedSig_OI_clock_lock;
  core_clk <= NlwRenamedSig_OI_core_clk;
  crm_pwr_soft_reset_n <= NlwRenamedSig_OI_crm_pwr_soft_reset_n;
  DEBUG(338) <= NlwRenamedSig_OI_DEBUG(338);
  DEBUG(337) <= NlwRenamedSig_OI_DEBUG(337);
  DEBUG(336) <= NlwRenamedSig_OI_DEBUG(336);
  DEBUG(335) <= NlwRenamedSig_OI_DEBUG(335);
  DEBUG(334) <= NlwRenamedSig_OI_DEBUG(334);
  DEBUG(333) <= NlwRenamedSig_OI_DEBUG(333);
  DEBUG(332) <= NlwRenamedSig_OI_DEBUG(332);
  DEBUG(331) <= NlwRenamedSig_OI_DEBUG(331);
  DEBUG(330) <= NlwRenamedSig_OI_DEBUG(330);
  DEBUG(329) <= NlwRenamedSig_OI_DEBUG(329);
  DEBUG(328) <= NlwRenamedSig_OI_DEBUG(328);
  DEBUG(327) <= NlwRenamedSig_OI_DEBUG(327);
  DEBUG(326) <= NlwRenamedSig_OI_DEBUG(326);
  DEBUG(325) <= NlwRenamedSig_OI_DEBUG(325);
  DEBUG(324) <= NlwRenamedSig_OI_DEBUG(324);
  DEBUG(323) <= NlwRenamedSig_OI_DEBUG(323);
  DEBUG(322) <= NlwRenamedSig_OI_DEBUG(322);
  DEBUG(321) <= NlwRenamedSig_OI_DEBUG(321);
  DEBUG(320) <= NlwRenamedSig_OI_DEBUG(320);
  DEBUG(319) <= NlwRenamedSig_OI_DEBUG(319);
  DEBUG(318) <= NlwRenamedSig_OI_DEBUG(318);
  DEBUG(317) <= NlwRenamedSig_OI_DEBUG(317);
  DEBUG(316) <= NlwRenamedSig_OI_DEBUG(316);
  DEBUG(315) <= NlwRenamedSig_OI_DEBUG(315);
  DEBUG(314) <= NlwRenamedSig_OI_DEBUG(314);
  DEBUG(313) <= NlwRenamedSig_OI_DEBUG(313);
  DEBUG(312) <= NlwRenamedSig_OI_DEBUG(312);
  DEBUG(311) <= NlwRenamedSig_OI_DEBUG(311);
  DEBUG(310) <= NlwRenamedSig_OI_DEBUG(310);
  DEBUG(309) <= NlwRenamedSig_OI_DEBUG(309);
  DEBUG(308) <= NlwRenamedSig_OI_DEBUG(308);
  DEBUG(307) <= NlwRenamedSig_OI_DEBUG(307);
  DEBUG(306) <= NlwRenamedSig_OI_DEBUG(306);
  DEBUG(305) <= NlwRenamedSig_OI_DEBUG(305);
  DEBUG(304) <= NlwRenamedSig_OI_DEBUG(304);
  DEBUG(303) <= NlwRenamedSig_OI_DEBUG(303);
  DEBUG(302) <= NlwRenamedSig_OI_DEBUG(302);
  DEBUG(301) <= NlwRenamedSig_OI_DEBUG(301);
  DEBUG(300) <= NlwRenamedSig_OI_DEBUG(300);
  DEBUG(299) <= NlwRenamedSig_OI_DEBUG(299);
  DEBUG(298) <= NlwRenamedSig_OI_DEBUG(298);
  DEBUG(297) <= NlwRenamedSig_OI_DEBUG(297);
  DEBUG(296) <= NlwRenamedSig_OI_DEBUG(296);
  DEBUG(295) <= NlwRenamedSig_OI_DEBUG(295);
  DEBUG(294) <= NlwRenamedSig_OI_DEBUG(294);
  DEBUG(293) <= NlwRenamedSig_OI_DEBUG(293);
  DEBUG(292) <= NlwRenamedSig_OI_DEBUG(292);
  DEBUG(291) <= NlwRenamedSig_OI_DEBUG(291);
  DEBUG(290) <= NlwRenamedSig_OI_DEBUG(290);
  DEBUG(289) <= NlwRenamedSig_OI_DEBUG(289);
  DEBUG(288) <= NlwRenamedSig_OI_DEBUG(288);
  DEBUG(287) <= NlwRenamedSig_OI_DEBUG(287);
  DEBUG(286) <= NlwRenamedSig_OI_DEBUG(286);
  DEBUG(285) <= NlwRenamedSig_OI_DEBUG(285);
  DEBUG(284) <= NlwRenamedSig_OI_DEBUG(284);
  DEBUG(283) <= NlwRenamedSig_OI_DEBUG(283);
  DEBUG(282) <= NlwRenamedSig_OI_DEBUG(282);
  DEBUG(281) <= NlwRenamedSig_OI_DEBUG(281);
  DEBUG(280) <= NlwRenamedSig_OI_DEBUG(280);
  DEBUG(279) <= NlwRenamedSig_OI_DEBUG(279);
  DEBUG(278) <= NlwRenamedSig_OI_DEBUG(278);
  DEBUG(277) <= NlwRenamedSig_OI_DEBUG(277);
  DEBUG(276) <= NlwRenamedSig_OI_DEBUG(276);
  DEBUG(275) <= NlwRenamedSig_OI_DEBUG(275);
  DEBUG(274) <= NlwRenamedSig_OI_DEBUG(274);
  DEBUG(273) <= NlwRenamedSig_OI_DEBUG(273);
  DEBUG(272) <= NlwRenamedSig_OI_DEBUG(272);
  DEBUG(271) <= NlwRenamedSig_OI_DEBUG(271);
  DEBUG(270) <= NlwRenamedSig_OI_DEBUG(270);
  DEBUG(269) <= NlwRenamedSig_OI_DEBUG(269);
  DEBUG(268) <= NlwRenamedSig_OI_DEBUG(268);
  DEBUG(267) <= NlwRenamedSig_OI_DEBUG(267);
  DEBUG(266) <= NlwRenamedSig_OI_DEBUG(266);
  DEBUG(265) <= NlwRenamedSig_OI_DEBUG(265);
  DEBUG(264) <= NlwRenamedSig_OI_DEBUG(264);
  DEBUG(263) <= NlwRenamedSig_OI_DEBUG(263);
  DEBUG(262) <= NlwRenamedSig_OI_DEBUG(262);
  DEBUG(261) <= NlwRenamedSig_OI_DEBUG(261);
  DEBUG(260) <= NlwRenamedSig_OI_DEBUG(260);
  DEBUG(259) <= NlwRenamedSig_OI_DEBUG(259);
  DEBUG(258) <= NlwRenamedSig_OI_DEBUG(258);
  DEBUG(257) <= NlwRenamedSig_OI_DEBUG(257);
  DEBUG(256) <= NlwRenamedSig_OI_DEBUG(256);
  DEBUG(255) <= NlwRenamedSig_OI_DEBUG(255);
  DEBUG(254) <= NlwRenamedSig_OI_DEBUG(254);
  DEBUG(253) <= NlwRenamedSig_OI_DEBUG(253);
  DEBUG(252) <= NlwRenamedSig_OI_DEBUG(252);
  DEBUG(251) <= NlwRenamedSig_OI_DEBUG(251);
  DEBUG(250) <= NlwRenamedSig_OI_DEBUG(250);
  DEBUG(249) <= NlwRenamedSig_OI_DEBUG(249);
  DEBUG(248) <= NlwRenamedSig_OI_DEBUG(248);
  DEBUG(247) <= NlwRenamedSig_OI_DEBUG(247);
  DEBUG(246) <= NlwRenamedSig_OI_DEBUG(246);
  DEBUG(245) <= NlwRenamedSig_OI_DEBUG(245);
  DEBUG(244) <= NlwRenamedSig_OI_DEBUG(244);
  DEBUG(243) <= NlwRenamedSig_OI_DEBUG(243);
  DEBUG(242) <= NlwRenamedSig_OI_DEBUG(242);
  DEBUG(241) <= NlwRenamedSig_OI_DEBUG(241);
  DEBUG(240) <= NlwRenamedSig_OI_DEBUG(240);
  DEBUG(239) <= NlwRenamedSig_OI_DEBUG(239);
  DEBUG(238) <= NlwRenamedSig_OI_DEBUG(238);
  DEBUG(237) <= NlwRenamedSig_OI_DEBUG(237);
  DEBUG(236) <= NlwRenamedSig_OI_DEBUG(236);
  DEBUG(235) <= NlwRenamedSig_OI_DEBUG(235);
  DEBUG(234) <= NlwRenamedSig_OI_DEBUG(234);
  DEBUG(233) <= NlwRenamedSig_OI_DEBUG(233);
  DEBUG(232) <= NlwRenamedSig_OI_DEBUG(232);
  DEBUG(231) <= NlwRenamedSig_OI_DEBUG(231);
  DEBUG(230) <= NlwRenamedSig_OI_DEBUG(230);
  DEBUG(229) <= NlwRenamedSig_OI_DEBUG(229);
  DEBUG(228) <= NlwRenamedSig_OI_DEBUG(228);
  DEBUG(227) <= NlwRenamedSig_OI_DEBUG(227);
  DEBUG(226) <= NlwRenamedSig_OI_DEBUG(226);
  DEBUG(225) <= NlwRenamedSig_OI_DEBUG(225);
  DEBUG(224) <= NlwRenamedSig_OI_DEBUG(224);
  DEBUG(223) <= NlwRenamedSig_OI_DEBUG(223);
  DEBUG(222) <= NlwRenamedSig_OI_DEBUG(222);
  DEBUG(221) <= NlwRenamedSig_OI_DEBUG(221);
  DEBUG(220) <= NlwRenamedSig_OI_DEBUG(220);
  DEBUG(219) <= NlwRenamedSig_OI_DEBUG(219);
  DEBUG(218) <= NlwRenamedSig_OI_DEBUG(218);
  DEBUG(217) <= NlwRenamedSig_OI_DEBUG(217);
  DEBUG(216) <= NlwRenamedSig_OI_DEBUG(216);
  DEBUG(215) <= NlwRenamedSig_OI_DEBUG(215);
  DEBUG(214) <= NlwRenamedSig_OI_DEBUG(214);
  DEBUG(213) <= NlwRenamedSig_OI_DEBUG(213);
  DEBUG(212) <= NlwRenamedSig_OI_DEBUG(212);
  DEBUG(211) <= NlwRenamedSig_OI_DEBUG(211);
  DEBUG(210) <= NlwRenamedSig_OI_DEBUG(210);
  DEBUG(209) <= NlwRenamedSig_OI_DEBUG(209);
  DEBUG(208) <= NlwRenamedSig_OI_DEBUG(208);
  DEBUG(207) <= NlwRenamedSig_OI_DEBUG(207);
  DEBUG(206) <= NlwRenamedSig_OI_DEBUG(206);
  DEBUG(205) <= NlwRenamedSig_OI_DEBUG(205);
  DEBUG(204) <= NlwRenamedSig_OI_DEBUG(204);
  DEBUG(203) <= NlwRenamedSig_OI_DEBUG(203);
  DEBUG(202) <= NlwRenamedSig_OI_DEBUG(202);
  DEBUG(201) <= NlwRenamedSig_OI_DEBUG(201);
  DEBUG(200) <= NlwRenamedSig_OI_DEBUG(200);
  DEBUG(199) <= NlwRenamedSig_OI_DEBUG(199);
  DEBUG(198) <= NlwRenamedSig_OI_DEBUG(198);
  DEBUG(197) <= NlwRenamedSig_OI_DEBUG(197);
  DEBUG(196) <= NlwRenamedSig_OI_DEBUG(196);
  DEBUG(195) <= NlwRenamedSig_OI_DEBUG(195);
  DEBUG(194) <= NlwRenamedSig_OI_DEBUG(194);
  DEBUG(193) <= NlwRenamedSig_OI_DEBUG(193);
  DEBUG(192) <= NlwRenamedSig_OI_DEBUG(192);
  DEBUG(191) <= NlwRenamedSig_OI_DEBUG(191);
  DEBUG(190) <= NlwRenamedSig_OI_DEBUG(190);
  DEBUG(189) <= NlwRenamedSig_OI_DEBUG(189);
  DEBUG(188) <= NlwRenamedSig_OI_DEBUG(188);
  DEBUG(187) <= NlwRenamedSig_OI_DEBUG(187);
  DEBUG(186) <= NlwRenamedSig_OI_DEBUG(186);
  DEBUG(185) <= NlwRenamedSig_OI_DEBUG(185);
  DEBUG(184) <= NlwRenamedSig_OI_DEBUG(184);
  DEBUG(183) <= NlwRenamedSig_OI_DEBUG(183);
  DEBUG(182) <= NlwRenamedSig_OI_DEBUG(182);
  DEBUG(181) <= NlwRenamedSig_OI_DEBUG(181);
  DEBUG(180) <= NlwRenamedSig_OI_DEBUG(180);
  DEBUG(179) <= NlwRenamedSig_OI_DEBUG(179);
  DEBUG(178) <= NlwRenamedSig_OI_DEBUG(178);
  DEBUG(177) <= NlwRenamedSig_OI_DEBUG(177);
  DEBUG(176) <= NlwRenamedSig_OI_DEBUG(176);
  DEBUG(175) <= NlwRenamedSig_OI_DEBUG(175);
  DEBUG(174) <= NlwRenamedSig_OI_DEBUG(174);
  DEBUG(173) <= NlwRenamedSig_OI_DEBUG(173);
  DEBUG(172) <= NlwRenamedSig_OI_DEBUG(172);
  DEBUG(171) <= NlwRenamedSig_OI_DEBUG(171);
  DEBUG(170) <= NlwRenamedSig_OI_DEBUG(170);
  DEBUG(169) <= NlwRenamedSig_OI_DEBUG(169);
  DEBUG(168) <= NlwRenamedSig_OI_DEBUG(168);
  DEBUG(167) <= NlwRenamedSig_OI_DEBUG(167);
  DEBUG(166) <= NlwRenamedSig_OI_DEBUG(166);
  DEBUG(165) <= NlwRenamedSig_OI_DEBUG(165);
  DEBUG(164) <= NlwRenamedSig_OI_DEBUG(164);
  DEBUG(163) <= NlwRenamedSig_OI_DEBUG(163);
  DEBUG(162) <= NlwRenamedSig_OI_DEBUG(162);
  DEBUG(161) <= NlwRenamedSig_OI_DEBUG(161);
  DEBUG(160) <= NlwRenamedSig_OI_DEBUG(160);
  DEBUG(159) <= NlwRenamedSig_OI_DEBUG(159);
  DEBUG(158) <= NlwRenamedSig_OI_DEBUG(158);
  DEBUG(157) <= NlwRenamedSig_OI_DEBUG(157);
  DEBUG(156) <= NlwRenamedSig_OI_DEBUG(156);
  DEBUG(155) <= NlwRenamedSig_OI_DEBUG(155);
  DEBUG(154) <= NlwRenamedSig_OI_DEBUG(154);
  DEBUG(153) <= NlwRenamedSig_OI_DEBUG(153);
  DEBUG(152) <= NlwRenamedSig_OI_DEBUG(152);
  DEBUG(151) <= NlwRenamedSig_OI_DEBUG(151);
  DEBUG(150) <= NlwRenamedSig_OI_DEBUG(150);
  DEBUG(149) <= NlwRenamedSig_OI_DEBUG(149);
  DEBUG(148) <= NlwRenamedSig_OI_DEBUG(148);
  DEBUG(147) <= NlwRenamedSig_OI_DEBUG(147);
  DEBUG(146) <= NlwRenamedSig_OI_DEBUG(146);
  DEBUG(145) <= NlwRenamedSig_OI_DEBUG(145);
  DEBUG(144) <= NlwRenamedSig_OI_DEBUG(144);
  DEBUG(143) <= NlwRenamedSig_OI_DEBUG(143);
  DEBUG(142) <= NlwRenamedSig_OI_DEBUG(142);
  DEBUG(141) <= NlwRenamedSig_OI_DEBUG(141);
  DEBUG(140) <= NlwRenamedSig_OI_DEBUG(140);
  DEBUG(139) <= NlwRenamedSig_OI_DEBUG(139);
  DEBUG(138) <= NlwRenamedSig_OI_DEBUG(138);
  DEBUG(137) <= NlwRenamedSig_OI_DEBUG(137);
  DEBUG(136) <= NlwRenamedSig_OI_DEBUG(136);
  DEBUG(135) <= NlwRenamedSig_OI_DEBUG(135);
  DEBUG(134) <= NlwRenamedSig_OI_DEBUG(134);
  DEBUG(133) <= NlwRenamedSig_OI_DEBUG(133);
  DEBUG(132) <= NlwRenamedSig_OI_DEBUG(132);
  DEBUG(131) <= NlwRenamedSig_OI_DEBUG(131);
  DEBUG(130) <= NlwRenamedSig_OI_DEBUG(130);
  DEBUG(129) <= NlwRenamedSig_OI_DEBUG(129);
  DEBUG(128) <= NlwRenamedSig_OI_DEBUG(128);
  DEBUG(127) <= NlwRenamedSig_OI_DEBUG(127);
  DEBUG(126) <= NlwRenamedSig_OI_DEBUG(126);
  DEBUG(125) <= NlwRenamedSig_OI_DEBUG(125);
  DEBUG(124) <= NlwRenamedSig_OI_DEBUG(124);
  DEBUG(123) <= NlwRenamedSig_OI_DEBUG(123);
  DEBUG(122) <= NlwRenamedSig_OI_DEBUG(122);
  DEBUG(121) <= NlwRenamedSig_OI_DEBUG(121);
  DEBUG(120) <= NlwRenamedSig_OI_DEBUG(120);
  DEBUG(119) <= NlwRenamedSig_OI_DEBUG(119);
  DEBUG(118) <= NlwRenamedSig_OI_DEBUG(118);
  DEBUG(117) <= NlwRenamedSig_OI_DEBUG(117);
  DEBUG(116) <= NlwRenamedSig_OI_DEBUG(116);
  DEBUG(115) <= NlwRenamedSig_OI_DEBUG(115);
  DEBUG(114) <= NlwRenamedSig_OI_DEBUG(114);
  DEBUG(113) <= NlwRenamedSig_OI_DEBUG(113);
  DEBUG(112) <= NlwRenamedSig_OI_DEBUG(112);
  DEBUG(111) <= NlwRenamedSig_OI_DEBUG(111);
  DEBUG(110) <= NlwRenamedSig_OI_DEBUG(110);
  DEBUG(109) <= NlwRenamedSig_OI_DEBUG(109);
  DEBUG(108) <= NlwRenamedSig_OI_DEBUG(108);
  DEBUG(107) <= NlwRenamedSig_OI_DEBUG(107);
  DEBUG(106) <= NlwRenamedSig_OI_DEBUG(106);
  DEBUG(105) <= NlwRenamedSig_OI_DEBUG(105);
  DEBUG(104) <= NlwRenamedSig_OI_DEBUG(104);
  DEBUG(103) <= NlwRenamedSig_OI_DEBUG(103);
  DEBUG(102) <= NlwRenamedSig_OI_DEBUG(102);
  DEBUG(101) <= NlwRenamedSig_OI_DEBUG(101);
  DEBUG(100) <= NlwRenamedSig_OI_DEBUG(100);
  DEBUG(99) <= NlwRenamedSig_OI_DEBUG(99);
  DEBUG(98) <= NlwRenamedSig_OI_DEBUG(98);
  DEBUG(97) <= NlwRenamedSig_OI_DEBUG(97);
  DEBUG(96) <= NlwRenamedSig_OI_DEBUG(96);
  DEBUG(95) <= NlwRenamedSig_OI_DEBUG(95);
  DEBUG(94) <= NlwRenamedSig_OI_DEBUG(94);
  DEBUG(93) <= NlwRenamedSig_OI_DEBUG(93);
  DEBUG(92) <= NlwRenamedSig_OI_DEBUG(92);
  DEBUG(91) <= NlwRenamedSig_OI_DEBUG(91);
  DEBUG(90) <= NlwRenamedSig_OI_DEBUG(90);
  DEBUG(89) <= NlwRenamedSig_OI_DEBUG(89);
  DEBUG(88) <= NlwRenamedSig_OI_DEBUG(88);
  DEBUG(87) <= NlwRenamedSig_OI_DEBUG(87);
  DEBUG(86) <= NlwRenamedSig_OI_DEBUG(86);
  DEBUG(85) <= NlwRenamedSig_OI_DEBUG(85);
  DEBUG(84) <= NlwRenamedSig_OI_DEBUG(84);
  DEBUG(83) <= NlwRenamedSig_OI_DEBUG(83);
  DEBUG(82) <= NlwRenamedSig_OI_DEBUG(82);
  DEBUG(81) <= NlwRenamedSig_OI_DEBUG(81);
  DEBUG(80) <= NlwRenamedSig_OI_DEBUG(80);
  DEBUG(79) <= NlwRenamedSig_OI_DEBUG(79);
  DEBUG(78) <= NlwRenamedSig_OI_DEBUG(78);
  DEBUG(77) <= NlwRenamedSig_OI_DEBUG(77);
  DEBUG(76) <= NlwRenamedSig_OI_DEBUG(76);
  DEBUG(75) <= NlwRenamedSig_OI_DEBUG(75);
  DEBUG(74) <= NlwRenamedSig_OI_DEBUG(74);
  DEBUG(73) <= NlwRenamedSig_OI_DEBUG(73);
  DEBUG(72) <= NlwRenamedSig_OI_DEBUG(72);
  DEBUG(71) <= NlwRenamedSig_OI_DEBUG(71);
  DEBUG(70) <= NlwRenamedSig_OI_DEBUG(70);
  DEBUG(69) <= NlwRenamedSig_OI_DEBUG(69);
  DEBUG(68) <= NlwRenamedSig_OI_DEBUG(68);
  DEBUG(67) <= NlwRenamedSig_OI_DEBUG(67);
  DEBUG(66) <= NlwRenamedSig_OI_DEBUG(66);
  DEBUG(65) <= NlwRenamedSig_OI_DEBUG(65);
  DEBUG(64) <= NlwRenamedSig_OI_DEBUG(64);
  DEBUG(63) <= NlwRenamedSig_OI_DEBUG(63);
  DEBUG(62) <= NlwRenamedSig_OI_DEBUG(62);
  DEBUG(61) <= NlwRenamedSig_OI_DEBUG(61);
  DEBUG(60) <= NlwRenamedSig_OI_DEBUG(60);
  DEBUG(59) <= NlwRenamedSig_OI_DEBUG(59);
  DEBUG(58) <= NlwRenamedSig_OI_DEBUG(58);
  DEBUG(57) <= NlwRenamedSig_OI_DEBUG(57);
  DEBUG(56) <= NlwRenamedSig_OI_DEBUG(56);
  DEBUG(55) <= NlwRenamedSig_OI_DEBUG(55);
  DEBUG(54) <= NlwRenamedSig_OI_DEBUG(54);
  DEBUG(53) <= NlwRenamedSig_OI_DEBUG(53);
  DEBUG(52) <= NlwRenamedSig_OI_DEBUG(52);
  DEBUG(51) <= NlwRenamedSig_OI_DEBUG(51);
  DEBUG(50) <= NlwRenamedSig_OI_DEBUG(50);
  DEBUG(49) <= NlwRenamedSig_OI_DEBUG(49);
  DEBUG(48) <= NlwRenamedSig_OI_DEBUG(48);
  DEBUG(47) <= NlwRenamedSig_OI_DEBUG(47);
  DEBUG(46) <= NlwRenamedSig_OI_DEBUG(46);
  DEBUG(45) <= NlwRenamedSig_OI_DEBUG(45);
  DEBUG(44) <= NlwRenamedSig_OI_DEBUG(44);
  DEBUG(43) <= NlwRenamedSig_OI_DEBUG(43);
  DEBUG(42) <= NlwRenamedSig_OI_DEBUG(42);
  DEBUG(41) <= NlwRenamedSig_OI_DEBUG(41);
  DEBUG(40) <= NlwRenamedSig_OI_DEBUG(40);
  DEBUG(39) <= NlwRenamedSig_OI_DEBUG(39);
  DEBUG(38) <= NlwRenamedSig_OI_DEBUG(38);
  DEBUG(37) <= NlwRenamedSig_OI_DEBUG(37);
  DEBUG(36) <= NlwRenamedSig_OI_DEBUG(36);
  DEBUG(35) <= NlwRenamedSig_OI_DEBUG(35);
  DEBUG(34) <= NlwRenamedSig_OI_DEBUG(34);
  DEBUG(33) <= NlwRenamedSig_OI_DEBUG(33);
  DEBUG(32) <= NlwRenamedSig_OI_DEBUG(32);
  DEBUG(31) <= NlwRenamedSig_OI_DEBUG(31);
  DEBUG(30) <= NlwRenamedSig_OI_DEBUG(30);
  DEBUG(29) <= NlwRenamedSig_OI_DEBUG(29);
  DEBUG(28) <= NlwRenamedSig_OI_DEBUG(28);
  DEBUG(27) <= NlwRenamedSig_OI_DEBUG(27);
  DEBUG(26) <= NlwRenamedSig_OI_DEBUG(26);
  DEBUG(25) <= NlwRenamedSig_OI_DEBUG(25);
  DEBUG(24) <= NlwRenamedSig_OI_DEBUG(24);
  DEBUG(23) <= NlwRenamedSig_OI_DEBUG(23);
  DEBUG(22) <= NlwRenamedSig_OI_DEBUG(22);
  DEBUG(21) <= NlwRenamedSig_OI_DEBUG(21);
  DEBUG(20) <= NlwRenamedSig_OI_DEBUG(20);
  DEBUG(19) <= NlwRenamedSig_OI_DEBUG(19);
  DEBUG(18) <= NlwRenamedSig_OI_DEBUG(18);
  DEBUG(17) <= NlwRenamedSig_OI_DEBUG(17);
  DEBUG(16) <= NlwRenamedSig_OI_DEBUG(16);
  DEBUG(15) <= NlwRenamedSig_OI_DEBUG(15);
  DEBUG(14) <= NlwRenamedSig_OI_DEBUG(14);
  DEBUG(13) <= NlwRenamedSig_OI_DEBUG(13);
  DEBUG(12) <= NlwRenamedSig_OI_DEBUG(12);
  DEBUG(11) <= NlwRenamedSig_OI_DEBUG(11);
  DEBUG(10) <= NlwRenamedSig_OI_DEBUG(10);
  DEBUG(9) <= NlwRenamedSig_OI_DEBUG(9);
  DEBUG(8) <= NlwRenamedSig_OI_DEBUG(8);
  DEBUG(7) <= NlwRenamedSig_OI_DEBUG(7);
  DEBUG(6) <= NlwRenamedSig_OI_DEBUG(6);
  DEBUG(5) <= NlwRenamedSig_OI_DEBUG(5);
  DEBUG(4) <= NlwRenamedSig_OI_DEBUG(4);
  DEBUG(3) <= NlwRenamedSig_OI_DEBUG(3);
  DEBUG(2) <= NlwRenamedSig_OI_DEBUG(2);
  DEBUG(1) <= NlwRenamedSig_OI_DEBUG(1);
  DEBUG(0) <= NlwRenamedSig_OI_DEBUG(0);
  l0_ltssm_state(3) <= NlwRenamedSig_OI_l0_ltssm_state(3);
  l0_ltssm_state(2) <= NlwRenamedSig_OI_l0_ltssm_state(2);
  l0_ltssm_state(1) <= NlwRenamedSig_OI_l0_ltssm_state(1);
  l0_ltssm_state(0) <= NlwRenamedSig_OI_l0_ltssm_state(0);
  l0_dl_up_down(0) <= NlwRenamedSig_OI_l0_dl_up_down(0);
  PLLLKDET_OUT(0) <= NlwRenamedSig_OI_PLLLKDET_OUT(0);
  l0_mac_negotiated_link_width(3) <= NlwRenamedSig_OI_l0_mac_negotiated_link_width(3);
  l0_mac_negotiated_link_width(2) <= NlwRenamedSig_OI_l0_mac_negotiated_link_width(2);
  l0_mac_negotiated_link_width(1) <= NlwRenamedSig_OI_l0_mac_negotiated_link_width(1);
  l0_mac_negotiated_link_width(0) <= NlwRenamedSig_OI_l0_mac_negotiated_link_width(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_DEBUG(338)
    );
  XST_VCC : VCC
    port map (
      P => usrclk
    );
  reg_l0_ltssm_state_internal_0 : FDC
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CLR => d_user_reset_n_inv,
      D => NlwRenamedSig_OI_l0_ltssm_state(0),
      Q => reg_l0_ltssm_state_internal(0)
    );
  reg_l0_ltssm_state_internal_1 : FDC
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CLR => d_user_reset_n_inv,
      D => NlwRenamedSig_OI_l0_ltssm_state(1),
      Q => reg_l0_ltssm_state_internal(1)
    );
  reg_l0_ltssm_state_internal_2 : FDC
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CLR => d_user_reset_n_inv,
      D => NlwRenamedSig_OI_l0_ltssm_state(2),
      Q => reg_l0_ltssm_state_internal(2)
    );
  reg_l0_ltssm_state_internal_3 : FDC
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CLR => d_user_reset_n_inv,
      D => NlwRenamedSig_OI_l0_ltssm_state(3),
      Q => reg_l0_ltssm_state_internal(3)
    );
  reg_enable_ltssm_reset : FDCE
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CE => reg_enable_ltssm_reset_not0001,
      CLR => d_user_reset_n_inv,
      D => reg_enable_ltssm_reset_mux0000,
      Q => reg_enable_ltssm_reset_18589
    );
  reg_ltssm_reset_0 : FDCE
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CE => reg_ltssm_reset_and0000,
      CLR => d_user_reset_n_inv,
      D => Result(0),
      Q => reg_ltssm_reset(0)
    );
  reg_ltssm_reset_1 : FDCE
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CE => reg_ltssm_reset_and0000,
      CLR => d_user_reset_n_inv,
      D => Result(1),
      Q => reg_ltssm_reset(1)
    );
  reg_ltssm_reset_2 : FDCE
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CE => reg_ltssm_reset_and0000,
      CLR => d_user_reset_n_inv,
      D => Result(2),
      Q => reg_ltssm_reset(2)
    );
  reg_ltssm_reset_3 : FDCE
    port map (
      C => NlwRenamedSig_OI_core_clk,
      CE => reg_ltssm_reset_and0000,
      CLR => d_user_reset_n_inv,
      D => Result(3),
      Q => reg_ltssm_reset(3)
    );
  pcie_ep_0 : PCIE_INTERNAL_1_1
    generic map(
      VC1RXFIFOLIMITNP => X"03FF",
      PBCAPABILITYDW3TYPE => X"0",
      SLOTCAPABILITYSLOTPOWERLIMITSCALE => X"0",
      BAR0ADDRWIDTH => 0,
      BAR0EXIST => TRUE,
      BAR0IOMEMN => 0,
      EXTCFGCAPPTR => X"00",
      BAR0PREFETCHABLE => FALSE,
      BAR1ADDRWIDTH => 0,
      BAR1EXIST => TRUE,
      BAR1IOMEMN => 0,
      EXTCFGXPCAPPTR => X"000",
      BAR1PREFETCHABLE => FALSE,
      BAR2ADDRWIDTH => 0,
      BAR2EXIST => FALSE,
      BAR2IOMEMN => 0,
      BAR0MASKWIDTH => X"15",
      BAR2PREFETCHABLE => FALSE,
      BAR3ADDRWIDTH => 0,
      BAR3EXIST => FALSE,
      BAR3IOMEMN => 0,
      BAR1MASKWIDTH => X"15",
      BAR3PREFETCHABLE => FALSE,
      BAR4ADDRWIDTH => 0,
      BAR4EXIST => FALSE,
      BAR4IOMEMN => 0,
      BAR2MASKWIDTH => X"20",
      BAR4PREFETCHABLE => FALSE,
      BAR5EXIST => FALSE,
      BAR5IOMEMN => 0,
      BAR3MASKWIDTH => X"20",
      BAR5PREFETCHABLE => FALSE,
      SUBSYSTEMVENDORID => X"4953",
      REVISIONID => X"20",
      DEVICEID => X"5507",
      CLKDIVIDED => FALSE,
      PCIECAPABILITYNEXTPTR => X"00",
      PCIECAPABILITYINTMSGNUM => X"00",
      HEADERTYPE => X"00",
      PORTVCCAPABILITYVCARBTABLEOFFSET => X"00",
      PBCAPABILITYDW3POWERRAIL => X"0",
      PORTVCCAPABILITYVCARBCAP => X"00",
      INFINITECOMPLETIONS => TRUE,
      SUBSYSTEMID => X"0001",
      L0SEXITLATENCY => 7,
      L0SEXITLATENCYCOMCLK => 7,
      L1EXITLATENCY => 7,
      L1EXITLATENCYCOMCLK => 7,
      DEVICECAPABILITYENDPOINTL1LATENCY => X"7",
      DEVICECAPABILITYENDPOINTL0SLATENCY => X"7",
      LINKSTATUSSLOTCLOCKCONFIG => TRUE,
      LOWPRIORITYVCCOUNT => 0,
      AERBASEPTR => X"10C",
      PMDATA8 => X"00",
      PMDATA7 => X"00",
      DSNBASEPTR => X"100",
      DEVICESERIALNUMBER => X"0000000000000000",
      PBCAPABILITYNEXTPTR => X"100",
      PBCAPABILITYDW0DATASCALE => X"0",
      PBCAPABILITYDW0BASEPOWER => X"00",
      PBCAPABILITYDW0PMSTATE => X"0",
      PBCAPABILITYDW0PMSUBSTATE => X"0",
      PBCAPABILITYDW0TYPE => X"0",
      PBCAPABILITYDW0POWERRAIL => X"0",
      PBCAPABILITYDW1DATASCALE => X"0",
      PBCAPABILITYDW1BASEPOWER => X"00",
      PBCAPABILITYDW1PMSTATE => X"0",
      PBCAPABILITYDW1PMSUBSTATE => X"0",
      PBCAPABILITYDW1TYPE => X"0",
      PBCAPABILITYDW1POWERRAIL => X"0",
      PBCAPABILITYDW2DATASCALE => X"0",
      PBCAPABILITYDW2BASEPOWER => X"00",
      PBCAPABILITYDW2PMSTATE => X"0",
      PBCAPABILITYDW2PMSUBSTATE => X"0",
      PBCAPABILITYDW2TYPE => X"0",
      PBCAPABILITYDW2POWERRAIL => X"0",
      PBCAPABILITYDW3DATASCALE => X"0",
      PBCAPABILITYDW3BASEPOWER => X"00",
      PBCAPABILITYDW3PMSTATE => X"0",
      PBCAPABILITYDW3PMSUBSTATE => X"0",
      DSNCAPABILITYNEXTPTR => X"000",
      PBCAPABILITYSYSTEMALLOCATED => FALSE,
      MSICAPABILITYNEXTPTR => X"60",
      MSIBASEPTR => X"048",
      INTERRUPTPIN => X"01",
      PMCAPABILITYD1SUPPORT => FALSE,
      PMCAPABILITYD2SUPPORT => FALSE,
      PMCAPABILITYDSI => TRUE,
      CAPABILITIESPOINTER => X"40",
      PMCAPABILITYNEXTPTR => X"48",
      PMCAPABILITYPMESUPPORT => X"00",
      PMSTATUSCONTROLDATASCALE => X"0",
      PMDATA0 => X"00",
      PMDATA1 => X"00",
      PMDATA2 => X"00",
      PMDATA3 => X"00",
      PMDATA4 => X"00",
      PMDATA5 => X"00",
      PMDATASCALE0 => 0,
      PMDATASCALE1 => 0,
      PMDATASCALE2 => 0,
      PMDATASCALE3 => 0,
      PMDATASCALE4 => 0,
      PMDATASCALE5 => 0,
      PMDATASCALE6 => 0,
      PMDATASCALE7 => 0,
      AERCAPABILITYNEXTPTR => X"144",
      VCCAPABILITYNEXTPTR => X"000",
      PORTVCCAPABILITYEXTENDEDVCCOUNT => X"0",
      RESETMODE => TRUE,
      RETRYRAMREADLATENCY => 3,
      VC1RXFIFOLIMITC => X"03FF",
      RETRYRAMWRITELATENCY => 1,
      VENDORID => X"4953",
      CARDBUSCISPOINTER => X"00000000",
      CLASSCODE => X"FFFFFF",
      TLRAMREADLATENCY => 3,
      TLRAMWRITELATENCY => 1,
      TXTSNFTS => 255,
      TXTSNFTSCOMCLK => 255,
      VC0RXFIFOBASEP => X"0000",
      VC0TOTALCREDITSCD => X"000",
      VC0TOTALCREDITSPD => X"080",
      VC0RXFIFOLIMITP => X"0117",
      VC0RXFIFOBASEC => X"0130",
      VC0RXFIFOBASENP => X"0118",
      VC0TOTALCREDITSCH => X"00",
      VC0TOTALCREDITSPH => X"01",
      VC0TXFIFOLIMITC => X"0217",
      VC0TOTALCREDITSNPH => X"01",
      VC0TXFIFOLIMITNP => X"0117",
      VC0TXFIFOBASEP => X"0000",
      VCBASEPTR => X"154",
      AERCAPABILITYECRCCHECKCAPABLE => FALSE,
      VC0TXFIFOLIMITP => X"00FF",
      VC0TXFIFOBASEC => X"0118",
      VC0TXFIFOBASENP => X"0100",
      VC1RXFIFOBASEP => X"0400",
      VC1TOTALCREDITSCD => X"000",
      VC1TOTALCREDITSPD => X"000",
      VC1RXFIFOLIMITP => X"03FF",
      VC1RXFIFOBASEC => X"0400",
      VC1RXFIFOBASENP => X"0400",
      VC1TOTALCREDITSCH => X"00",
      VC1TOTALCREDITSPH => X"00",
      VC1TXFIFOLIMITC => X"0217",
      VC1TOTALCREDITSNPH => X"00",
      VC1TXFIFOLIMITNP => X"0217",
      VC1TXFIFOBASEP => X"0218",
      VC0RXFIFOLIMITC => X"03FF",
      VC0RXFIFOLIMITNP => X"012F",
      VC1TXFIFOLIMITP => X"0217",
      VC1TXFIFOBASEC => X"0218",
      VC1TXFIFOBASENP => X"0218",
      PBBASEPTR => X"144",
      SLOTCAPABILITYPHYSICALSLOTNUM => X"0000",
      XPDEVICEPORTTYPE => X"0",
      PMBASEPTR => X"040",
      BAR5MASKWIDTH => X"20",
      XPMAXPAYLOAD => 1,
      RETRYRAMWIDTH => 0,
      TLRAMWIDTH => 0,
      DUALROLECFGCNTRLROOTEPN => 0,
      PCIEREVISION => 1,
      XPRCBCONTROL => 0,
      PMDATASCALE8 => 0,
      RETRYWRITEPIPE => FALSE,
      RETRYREADADDRPIPE => FALSE,
      RETRYREADDATAPIPE => FALSE,
      XLINKSUPPORTED => FALSE,
      RAMSHARETXRX => FALSE,
      DUALCORESLAVE => FALSE,
      DUALCOREENABLE => FALSE,
      RXREADADDRPIPE => FALSE,
      RXREADDATAPIPE => FALSE,
      TXWRITEPIPE => FALSE,
      TXREADADDRPIPE => FALSE,
      TXREADDATAPIPE => FALSE,
      RXWRITEPIPE => FALSE,
      LLKBYPASS => FALSE,
      SELECTDLLIF => FALSE,
      SELECTASMODE => FALSE,
      ISSWITCH => FALSE,
      UPSTREAMFACING => TRUE,
      SLOTIMPLEMENTED => FALSE,
      ACTIVELANESIN => X"FF",
      RETRYRAMSIZE => X"009",
      BAR4MASKWIDTH => X"20",
      CONFIGROUTING => X"1",
      PMCAPABILITYAUXCURRENT => X"0",
      PMDATA6 => X"00",
      PCIECAPABILITYSLOTIMPL => FALSE,
      MSICAPABILITYMULTIMSGCAP => X"0",
      SLOTCAPABILITYATTBUTTONPRESENT => FALSE,
      SLOTCAPABILITYPOWERCONTROLLERPRESENT => FALSE,
      SLOTCAPABILITYMSLSENSORPRESENT => FALSE,
      SLOTCAPABILITYATTINDICATORPRESENT => FALSE,
      SLOTCAPABILITYPOWERINDICATORPRESENT => FALSE,
      SLOTCAPABILITYHOTPLUGSURPRISE => FALSE,
      SLOTCAPABILITYHOTPLUGCAPABLE => FALSE,
      LINKCAPABILITYMAXLINKWIDTH => X"08",
      LINKCAPABILITYASPMSUPPORT => X"1",
      SLOTCAPABILITYSLOTPOWERLIMITVALUE => X"00",
      AERCAPABILITYECRCGENCAPABLE => FALSE,
      XPBASEPTR => X"60"
    )
    port map (
      PIPERXELECIDLEL0 => pipe_rx_elec_idle(0),
      PIPEPHYSTATUSL0 => pipe_rx_phy_status(0),
      PIPERXDATAKL0 => pipe_rx_data_k_out(0),
      PIPERXVALIDL0 => pipe_rx_valid_out(0),
      PIPERXCHANISALIGNEDL0 => pipe_rxchanisaligned(0),
      PIPETXDATAKL0 => pipe_tx_data_k_l0,
      PIPETXELECIDLEL0 => pipe_tx_elec_idle_l0,
      PIPETXDETECTRXLOOPBACKL0 => pipe_tx_detect_rx_loopback_l0,
      PIPETXCOMPLIANCEL0 => pipe_tx_compliance_l0,
      PIPERXPOLARITYL0 => pipe_rx_polarity_l0,
      PIPEDESKEWLANESL0 => pipe_deskew_lanes_l0,
      PIPERESETL0 => pipe_reset_l0,
      PIPERXELECIDLEL1 => pipe_rx_elec_idle(1),
      PIPEPHYSTATUSL1 => pipe_rx_phy_status(1),
      PIPERXDATAKL1 => pipe_rx_data_k_out(1),
      PIPERXVALIDL1 => pipe_rx_valid_out(1),
      PIPERXCHANISALIGNEDL1 => pipe_rxchanisaligned(1),
      PIPETXDATAKL1 => pipe_tx_data_k_l1,
      PIPETXELECIDLEL1 => pipe_tx_elec_idle_l1,
      PIPETXDETECTRXLOOPBACKL1 => pipe_tx_detect_rx_loopback_l1,
      PIPETXCOMPLIANCEL1 => pipe_tx_compliance_l1,
      PIPERXPOLARITYL1 => pipe_rx_polarity_l1,
      PIPEDESKEWLANESL1 => pipe_deskew_lanes_l1,
      PIPERESETL1 => pipe_reset_l1,
      PIPERXELECIDLEL2 => pipe_rx_elec_idle(2),
      PIPEPHYSTATUSL2 => pipe_rx_phy_status(2),
      PIPERXDATAKL2 => pipe_rx_data_k_out(2),
      PIPERXVALIDL2 => pipe_rx_valid_out(2),
      PIPERXCHANISALIGNEDL2 => pipe_rxchanisaligned(2),
      PIPETXDATAKL2 => pipe_tx_data_k_l2,
      PIPETXELECIDLEL2 => pipe_tx_elec_idle_l2,
      PIPETXDETECTRXLOOPBACKL2 => pipe_tx_detect_rx_loopback_l2,
      PIPETXCOMPLIANCEL2 => pipe_tx_compliance_l2,
      PIPERXPOLARITYL2 => pipe_rx_polarity_l2,
      PIPEDESKEWLANESL2 => pipe_deskew_lanes_l2,
      PIPERESETL2 => pipe_reset_l2,
      PIPERXELECIDLEL3 => pipe_rx_elec_idle(3),
      PIPEPHYSTATUSL3 => pipe_rx_phy_status(3),
      PIPERXDATAKL3 => pipe_rx_data_k_out(3),
      PIPERXVALIDL3 => pipe_rx_valid_out(3),
      PIPERXCHANISALIGNEDL3 => pipe_rxchanisaligned(3),
      PIPETXDATAKL3 => pipe_tx_data_k_l3,
      PIPETXELECIDLEL3 => pipe_tx_elec_idle_l3,
      PIPETXDETECTRXLOOPBACKL3 => pipe_tx_detect_rx_loopback_l3,
      PIPETXCOMPLIANCEL3 => pipe_tx_compliance_l3,
      PIPERXPOLARITYL3 => pipe_rx_polarity_l3,
      PIPEDESKEWLANESL3 => pipe_deskew_lanes_l3,
      PIPERESETL3 => pipe_reset_l3,
      PIPERXELECIDLEL4 => pipe_rx_elec_idle(4),
      PIPEPHYSTATUSL4 => pipe_rx_phy_status(4),
      PIPERXDATAKL4 => pipe_rx_data_k_out(4),
      PIPERXVALIDL4 => pipe_rx_valid_out(4),
      PIPERXCHANISALIGNEDL4 => pipe_rxchanisaligned(4),
      PIPETXDATAKL4 => pipe_tx_data_k_l4,
      PIPETXELECIDLEL4 => pipe_tx_elec_idle_l4,
      PIPETXDETECTRXLOOPBACKL4 => pipe_tx_detect_rx_loopback_l4,
      PIPETXCOMPLIANCEL4 => pipe_tx_compliance_l4,
      PIPERXPOLARITYL4 => pipe_rx_polarity_l4,
      PIPEDESKEWLANESL4 => pipe_deskew_lanes_l4,
      PIPERESETL4 => pipe_reset_l4,
      PIPERXELECIDLEL5 => pipe_rx_elec_idle(5),
      PIPEPHYSTATUSL5 => pipe_rx_phy_status(5),
      PIPERXDATAKL5 => pipe_rx_data_k_out(5),
      PIPERXVALIDL5 => pipe_rx_valid_out(5),
      PIPERXCHANISALIGNEDL5 => pipe_rxchanisaligned(5),
      PIPETXDATAKL5 => pipe_tx_data_k_l5,
      PIPETXELECIDLEL5 => pipe_tx_elec_idle_l5,
      PIPETXDETECTRXLOOPBACKL5 => pipe_tx_detect_rx_loopback_l5,
      PIPETXCOMPLIANCEL5 => pipe_tx_compliance_l5,
      PIPERXPOLARITYL5 => pipe_rx_polarity_l5,
      PIPEDESKEWLANESL5 => pipe_deskew_lanes_l5,
      PIPERESETL5 => pipe_reset_l5,
      PIPERXELECIDLEL6 => pipe_rx_elec_idle(6),
      PIPEPHYSTATUSL6 => pipe_rx_phy_status(6),
      PIPERXDATAKL6 => pipe_rx_data_k_out(6),
      PIPERXVALIDL6 => pipe_rx_valid_out(6),
      PIPERXCHANISALIGNEDL6 => pipe_rxchanisaligned(6),
      PIPETXDATAKL6 => pipe_tx_data_k_l6,
      PIPETXELECIDLEL6 => pipe_tx_elec_idle_l6,
      PIPETXDETECTRXLOOPBACKL6 => pipe_tx_detect_rx_loopback_l6,
      PIPETXCOMPLIANCEL6 => pipe_tx_compliance_l6,
      PIPERXPOLARITYL6 => pipe_rx_polarity_l6,
      PIPEDESKEWLANESL6 => pipe_deskew_lanes_l6,
      PIPERESETL6 => pipe_reset_l6,
      PIPERXELECIDLEL7 => pipe_rx_elec_idle(7),
      PIPEPHYSTATUSL7 => pipe_rx_phy_status(7),
      PIPERXDATAKL7 => pipe_rx_data_k_out(7),
      PIPERXVALIDL7 => pipe_rx_valid_out(7),
      PIPERXCHANISALIGNEDL7 => pipe_rxchanisaligned(7),
      PIPETXDATAKL7 => pipe_tx_data_k_l7,
      PIPETXELECIDLEL7 => pipe_tx_elec_idle_l7,
      PIPETXDETECTRXLOOPBACKL7 => pipe_tx_detect_rx_loopback_l7,
      PIPETXCOMPLIANCEL7 => pipe_tx_compliance_l7,
      PIPERXPOLARITYL7 => pipe_rx_polarity_l7,
      PIPEDESKEWLANESL7 => pipe_deskew_lanes_l7,
      PIPERESETL7 => pipe_reset_l7,
      MIMRXBWEN => NlwRenamedSig_OI_DEBUG(105),
      MIMRXBREN => NlwRenamedSig_OI_DEBUG(106),
      CRMCORECLKRXO => NlwRenamedSig_OI_core_clk,
      CRMUSERCLKRXO => usrclk,
      MIMTXBWEN => NlwRenamedSig_OI_DEBUG(13),
      MIMTXBREN => NlwRenamedSig_OI_DEBUG(14),
      CRMCORECLKTXO => NlwRenamedSig_OI_core_clk,
      CRMUSERCLKTXO => usrclk,
      MIMDLLBWEN => NlwRenamedSig_OI_DEBUG(337),
      MIMDLLBREN => NlwRenamedSig_OI_DEBUG(260),
      CRMCORECLKDLO => NlwRenamedSig_OI_core_clk,
      CRMCORECLK => NlwRenamedSig_OI_core_clk,
      CRMUSERCLK => usrclk,
      CRMURSTN => rb_crm_urst_n,
      CRMNVRSTN => rb_crm_nvrst_n,
      CRMMGMTRSTN => NlwRenamedSig_OI_mgmt_rdy,
      CRMUSERCFGRSTN => rb_crm_user_cfg_rst_n,
      CRMMACRSTN => rb_crm_mac_rst_n,
      CRMLINKRSTN => rb_crm_link_rst_n,
      CRMTXHOTRESETN => usrclk,
      CRMRXHOTRESETN => NLW_pcie_ep_CRMRXHOTRESETN_UNCONNECTED,
      CRMDOHOTRESETN => NlwRenamedSig_OI_crm_do_hot_reset_n,
      CRMCFGBRIDGEHOTRESET => NlwRenamedSig_OI_DEBUG(338),
      CRMPWRSOFTRESETN => NlwRenamedSig_OI_crm_pwr_soft_reset_n,
      LLKTXSRCRDYN => llk_tx_src_rdy_n,
      LLKTXDSTRDYN => llk_tx_dst_rdy_n,
      LLKTXSRCDSCN => llk_tx_src_dsc_n,
      LLKTXCOMPLETEN => usrclk,
      LLKTXSOFN => llk_tx_sof_n,
      LLKTXEOFN => llk_tx_eof_n,
      LLKTXSOPN => llk_tx_sop_n,
      LLKTXEOPN => llk_tx_eop_n,
      LLKTXCONFIGREADYN => NLW_pcie_ep_LLKTXCONFIGREADYN_UNCONNECTED,
      LLKTXCREATEECRCN => usrclk,
      LLKTX4DWHEADERN => usrclk,
      LLKRXSRCRDYN => llk_rx_src_rdy_n,
      LLKRXDSTREQN => llk_rx_dst_req_n,
      LLKRXSRCLASTREQN => llk_rx_src_last_req_n,
      LLKRXSRCDSCN => NLW_pcie_ep_LLKRXSRCDSCN_UNCONNECTED,
      LLKRXSOFN => llk_rx_sof_n,
      LLKRXEOFN => llk_rx_eof_n,
      LLKRXSOPN => llk_rx_sop_n,
      LLKRXEOPN => llk_rx_eop_n,
      LLKRXCHCONFIGAVAILABLEN => NLW_pcie_ep_LLKRXCHCONFIGAVAILABLEN_UNCONNECTED,
      LLKRXCHCONFIGPARTIALN => NLW_pcie_ep_LLKRXCHCONFIGPARTIALN_UNCONNECTED,
      LLKRX4DWHEADERN => NLW_pcie_ep_LLKRX4DWHEADERN_UNCONNECTED,
      LLKRXECRCBADN => NLW_pcie_ep_LLKRXECRCBADN_UNCONNECTED,
      LLKRXDSTCONTREQN => llk_rx_dst_cont_req_n,
      MGMTWREN => mgmt_wren,
      MGMTRDEN => mgmt_rden,
      MAINPOWER => usrclk,
      AUXPOWER => NlwRenamedSig_OI_DEBUG(338),
      L0TLLINKRETRAIN => NlwRenamedSig_OI_DEBUG(338),
      L0RXDLLTLPECRCOK => NLW_pcie_ep_L0RXDLLTLPECRCOK_UNCONNECTED,
      DLLTXPMDLLPOUTSTANDING => NLW_pcie_ep_DLLTXPMDLLPOUTSTANDING_UNCONNECTED,
      CROSSLINKSEED => usrclk,
      COMPLIANCEAVOID => compliance_avoid,
      L0VC0PREVIEWEXPAND => NlwRenamedSig_OI_DEBUG(338),
      L0FIRSTCFGWRITEOCCURRED => l0_first_cfg_write_occurred,
      L0CFGLOOPBACKMASTER => l0_cfg_loopback_master,
      L0CFGLOOPBACKACK => l0_cfg_loopback_ack,
      L0MACUPSTREAMDOWNSTREAM => NLW_pcie_ep_L0MACUPSTREAMDOWNSTREAM_UNCONNECTED,
      L0MACLINKUP => l0_mac_link_up,
      L0MACLINKTRAINING => l0_mac_link_training,
      L0DLLHOLDLINKUP => NlwRenamedSig_OI_DEBUG(338),
      L0CFGASSPANTREEOWNEDSTATE => NlwRenamedSig_OI_DEBUG(338),
      L0ASE => NlwRenamedSig_OI_DEBUG(338),
      L0CFGDISABLESCRAMBLE => NlwRenamedSig_OI_DEBUG(338),
      L0CFGEXTENDEDSYNC => NlwRenamedSig_OI_DEBUG(338),
      L0CFGLINKDISABLE => NlwRenamedSig_OI_DEBUG(338),
      L0DLLASTXSTATE => NLW_pcie_ep_L0DLLASTXSTATE_UNCONNECTED,
      L0ASAUTONOMOUSINITCOMPLETED => NLW_pcie_ep_L0ASAUTONOMOUSINITCOMPLETED_UNCONNECTED,
      L0SENDUNLOCKMESSAGE => NlwRenamedSig_OI_DEBUG(338),
      L0UNLOCKRECEIVED => NLW_pcie_ep_L0UNLOCKRECEIVED_UNCONNECTED,
      L0ALLDOWNRXPORTSINL0S => NlwRenamedSig_OI_DEBUG(338),
      L0UPSTREAMRXPORTINL0S => NlwRenamedSig_OI_DEBUG(338),
      L0TRANSACTIONSPENDING => l0_transactions_pending,
      L0ALLDOWNPORTSINL1 => NlwRenamedSig_OI_DEBUG(338),
      L0CORRERRMSGRCVD => NLW_pcie_ep_L0CORRERRMSGRCVD_UNCONNECTED,
      L0FATALERRMSGRCVD => NLW_pcie_ep_L0FATALERRMSGRCVD_UNCONNECTED,
      L0NONFATALERRMSGRCVD => NLW_pcie_ep_L0NONFATALERRMSGRCVD_UNCONNECTED,
      L0FWDCORRERRIN => NlwRenamedSig_OI_DEBUG(338),
      L0FWDFATALERRIN => NlwRenamedSig_OI_DEBUG(338),
      L0FWDNONFATALERRIN => NlwRenamedSig_OI_DEBUG(338),
      L0FWDCORRERROUT => NLW_pcie_ep_L0FWDCORRERROUT_UNCONNECTED,
      L0FWDFATALERROUT => NLW_pcie_ep_L0FWDFATALERROUT_UNCONNECTED,
      L0FWDNONFATALERROUT => NLW_pcie_ep_L0FWDNONFATALERROUT_UNCONNECTED,
      L0SETCOMPLETERABORTERROR => l0_set_completer_abort_error,
      L0SETDETECTEDCORRERROR => l0_set_detected_corr_error,
      L0SETDETECTEDFATALERROR => l0_set_detected_fatal_error,
      L0SETDETECTEDNONFATALERROR => l0_set_detected_nonfatal_error,
      L0SETLINKDETECTEDPARITYERROR => NlwRenamedSig_OI_DEBUG(338),
      L0SETLINKMASTERDATAPARITY => NlwRenamedSig_OI_DEBUG(338),
      L0SETLINKRECEIVEDMASTERABORT => NlwRenamedSig_OI_DEBUG(338),
      L0SETLINKRECEIVEDTARGETABORT => NlwRenamedSig_OI_DEBUG(338),
      L0SETLINKSYSTEMERROR => NlwRenamedSig_OI_DEBUG(338),
      L0SETLINKSIGNALLEDTARGETABORT => NlwRenamedSig_OI_DEBUG(338),
      L0SETUSERDETECTEDPARITYERROR => l0_set_user_detected_parity_error,
      L0SETUSERMASTERDATAPARITY => l0_set_user_master_data_parity,
      L0SETUSERRECEIVEDMASTERABORT => l0_set_user_received_master_abort,
      L0SETUSERRECEIVEDTARGETABORT => l0_set_user_received_target_abort,
      L0SETUSERSYSTEMERROR => l0_set_user_system_error,
      L0SETUSERSIGNALLEDTARGETABORT => l0_set_user_signalled_target_abort,
      L0SETCOMPLETIONTIMEOUTUNCORRERROR => l0_set_completion_timeout_uncorr_error,
      L0SETCOMPLETIONTIMEOUTCORRERROR => l0_set_completion_timeout_corr_error,
      L0SETUNEXPECTEDCOMPLETIONUNCORRERROR => l0_set_unexpected_completion_uncorr_error,
      L0SETUNEXPECTEDCOMPLETIONCORRERROR => l0_set_unexpected_completion_corr_error,
      L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR => l0_set_unsupported_request_nonposted_error,
      L0SETUNSUPPORTEDREQUESTOTHERERROR => l0_set_unsupported_request_other_error,
      L0LEGACYINTFUNCT0 => l0_legacy_int_funct0,
      L0FWDASSERTINTALEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDASSERTINTBLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDASSERTINTCLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDASSERTINTDLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDDEASSERTINTALEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDDEASSERTINTBLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDDEASSERTINTCLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0FWDDEASSERTINTDLEGACYINT => NlwRenamedSig_OI_DEBUG(338),
      L0RECEIVEDASSERTINTALEGACYINT => NLW_pcie_ep_L0RECEIVEDASSERTINTALEGACYINT_UNCONNECTED,
      L0RECEIVEDASSERTINTBLEGACYINT => NLW_pcie_ep_L0RECEIVEDASSERTINTBLEGACYINT_UNCONNECTED,
      L0RECEIVEDASSERTINTCLEGACYINT => NLW_pcie_ep_L0RECEIVEDASSERTINTCLEGACYINT_UNCONNECTED,
      L0RECEIVEDASSERTINTDLEGACYINT => NLW_pcie_ep_L0RECEIVEDASSERTINTDLEGACYINT_UNCONNECTED,
      L0RECEIVEDDEASSERTINTALEGACYINT => NLW_pcie_ep_L0RECEIVEDDEASSERTINTALEGACYINT_UNCONNECTED,
      L0RECEIVEDDEASSERTINTBLEGACYINT => NLW_pcie_ep_L0RECEIVEDDEASSERTINTBLEGACYINT_UNCONNECTED,
      L0RECEIVEDDEASSERTINTCLEGACYINT => NLW_pcie_ep_L0RECEIVEDDEASSERTINTCLEGACYINT_UNCONNECTED,
      L0RECEIVEDDEASSERTINTDLEGACYINT => NLW_pcie_ep_L0RECEIVEDDEASSERTINTDLEGACYINT_UNCONNECTED,
      L0MSIENABLE0 => l0_msi_enable0,
      L0STATSDLLPRECEIVED => l0_stats_dllp_received,
      L0STATSDLLPTRANSMITTED => l0_stats_dllp_transmitted,
      L0STATSOSRECEIVED => l0_stats_os_received,
      L0STATSOSTRANSMITTED => l0_stats_os_transmitted,
      L0STATSTLPRECEIVED => l0_stats_tlp_received,
      L0STATSTLPTRANSMITTED => l0_stats_tlp_transmitted,
      L0STATSCFGRECEIVED => l0_stats_cfg_received,
      L0STATSCFGTRANSMITTED => NlwRenamedSig_OI_l0_stats_cfg_transmitted,
      L0STATSCFGOTHERRECEIVED => l0_stats_cfg_other_received,
      L0STATSCFGOTHERTRANSMITTED => l0_stats_cfg_other_transmitted,
      IOSPACEENABLE => io_space_enable,
      MEMSPACEENABLE => mem_space_enable,
      L0ELECTROMECHANICALINTERLOCKENGAGED => NlwRenamedSig_OI_DEBUG(338),
      L0MRLSENSORCLOSEDN => NlwRenamedSig_OI_DEBUG(338),
      L0POWERFAULTDETECTED => NlwRenamedSig_OI_DEBUG(338),
      L0PRESENCEDETECTSLOTEMPTYN => NlwRenamedSig_OI_DEBUG(338),
      L0ATTENTIONBUTTONPRESSED => NlwRenamedSig_OI_DEBUG(338),
      L0POWERCONTROLLERCONTROL => NLW_pcie_ep_L0POWERCONTROLLERCONTROL_UNCONNECTED,
      L0TOGGLEELECTROMECHANICALINTERLOCK => NLW_pcie_ep_L0TOGGLEELECTROMECHANICALINTERLOCK_UNCONNECTED,
      L0TXBEACON => NlwRenamedSig_OI_DEBUG(338),
      L0WAKEN => usrclk,
      L0RXBEACON => NLW_pcie_ep_L0RXBEACON_UNCONNECTED,
      L0PMEREQIN => l0_pme_req_in,
      L0PMEACK => l0_pme_ack,
      L0PMEREQOUT => NLW_pcie_ep_L0PMEREQOUT_UNCONNECTED,
      L0PMEEN => NLW_pcie_ep_L0PMEEN_UNCONNECTED,
      L0PWRINHIBITTRANSFERS => NLW_pcie_ep_L0PWRINHIBITTRANSFERS_UNCONNECTED,
      L0PWRL1STATE => NLW_pcie_ep_L0PWRL1STATE_UNCONNECTED,
      L0PWRL23READYDEVICE => NLW_pcie_ep_L0PWRL23READYDEVICE_UNCONNECTED,
      L0PWRL23READYSTATE => l0_pwr_l23_ready_state,
      L0PWRTXL0SSTATE => l0_pwr_tx_l0s_state,
      L0ROOTTURNOFFREQ => NlwRenamedSig_OI_DEBUG(338),
      L0PWRTURNOFFREQ => l0_pwr_turn_off_req,
      L0RXDLLPM => NLW_pcie_ep_L0RXDLLPM_UNCONNECTED,
      L0TXCFGPM => NlwRenamedSig_OI_DEBUG(338),
      L0TXDLLPMUPDATED => NLW_pcie_ep_L0TXDLLPMUPDATED_UNCONNECTED,
      L0PWRNEWSTATEREQ => NlwRenamedSig_OI_DEBUG(338),
      L0CFGL0SENTRYSUP => NlwRenamedSig_OI_DEBUG(338),
      L0CFGL0SENTRYENABLE => NlwRenamedSig_OI_DEBUG(338),
      L0MACNEWSTATEACK => l0_mac_new_state_ack,
      L0MACRXL0SSTATE => l0_mac_rx_l0s_state,
      L0MACENTEREDL0 => l0_mac_entered_l0,
      L0DLLRXACKOUTSTANDING => NLW_pcie_ep_L0DLLRXACKOUTSTANDING_UNCONNECTED,
      L0DLLTXOUTSTANDING => NLW_pcie_ep_L0DLLTXOUTSTANDING_UNCONNECTED,
      L0DLLTXNONFCOUTSTANDING => NLW_pcie_ep_L0DLLTXNONFCOUTSTANDING_UNCONNECTED,
      L0TXTLTLPEDB => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPREQ => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPREQEND => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPWIDTH => NlwRenamedSig_OI_DEBUG(338),
      L0TLASFCCREDSTARVATION => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCUPDATE => NlwRenamedSig_OI_DEBUG(338),
      L0TXDLLSBFCUPDATED => NLW_pcie_ep_L0TXDLLSBFCUPDATED_UNCONNECTED,
      L0RXDLLSBFCUPDATE => NLW_pcie_ep_L0RXDLLSBFCUPDATE_UNCONNECTED,
      BUSMASTERENABLE => bus_master_enable,
      PARITYERRORRESPONSE => parity_error_response,
      SERRENABLE => serr_enable,
      INTERRUPTDISABLE => interrupt_disable,
      URREPORTINGENABLE => ur_reporting_enable,
      PIPERXSTATUSL0(2) => pipe_rx_status(2),
      PIPERXSTATUSL0(1) => pipe_rx_status(1),
      PIPERXSTATUSL0(0) => pipe_rx_status(0),
      PIPERXDATAL0(7) => pipe_rx_data_l0_out(7),
      PIPERXDATAL0(6) => pipe_rx_data_l0_out(6),
      PIPERXDATAL0(5) => pipe_rx_data_l0_out(5),
      PIPERXDATAL0(4) => pipe_rx_data_l0_out(4),
      PIPERXDATAL0(3) => pipe_rx_data_l0_out(3),
      PIPERXDATAL0(2) => pipe_rx_data_l0_out(2),
      PIPERXDATAL0(1) => pipe_rx_data_l0_out(1),
      PIPERXDATAL0(0) => pipe_rx_data_l0_out(0),
      PIPETXDATAL0(7) => pipe_tx_data_l0(7),
      PIPETXDATAL0(6) => pipe_tx_data_l0(6),
      PIPETXDATAL0(5) => pipe_tx_data_l0(5),
      PIPETXDATAL0(4) => pipe_tx_data_l0(4),
      PIPETXDATAL0(3) => pipe_tx_data_l0(3),
      PIPETXDATAL0(2) => pipe_tx_data_l0(2),
      PIPETXDATAL0(1) => pipe_tx_data_l0(1),
      PIPETXDATAL0(0) => pipe_tx_data_l0(0),
      PIPEPOWERDOWNL0(1) => pipe_power_down_l0(1),
      PIPEPOWERDOWNL0(0) => pipe_power_down_l0(0),
      PIPERXSTATUSL1(2) => pipe_rx_status(5),
      PIPERXSTATUSL1(1) => pipe_rx_status(4),
      PIPERXSTATUSL1(0) => pipe_rx_status(3),
      PIPERXDATAL1(7) => pipe_rx_data_l1_out(7),
      PIPERXDATAL1(6) => pipe_rx_data_l1_out(6),
      PIPERXDATAL1(5) => pipe_rx_data_l1_out(5),
      PIPERXDATAL1(4) => pipe_rx_data_l1_out(4),
      PIPERXDATAL1(3) => pipe_rx_data_l1_out(3),
      PIPERXDATAL1(2) => pipe_rx_data_l1_out(2),
      PIPERXDATAL1(1) => pipe_rx_data_l1_out(1),
      PIPERXDATAL1(0) => pipe_rx_data_l1_out(0),
      PIPETXDATAL1(7) => pipe_tx_data_l1(7),
      PIPETXDATAL1(6) => pipe_tx_data_l1(6),
      PIPETXDATAL1(5) => pipe_tx_data_l1(5),
      PIPETXDATAL1(4) => pipe_tx_data_l1(4),
      PIPETXDATAL1(3) => pipe_tx_data_l1(3),
      PIPETXDATAL1(2) => pipe_tx_data_l1(2),
      PIPETXDATAL1(1) => pipe_tx_data_l1(1),
      PIPETXDATAL1(0) => pipe_tx_data_l1(0),
      PIPEPOWERDOWNL1(1) => pipe_power_down_l1(1),
      PIPEPOWERDOWNL1(0) => pipe_power_down_l1(0),
      PIPERXSTATUSL2(2) => pipe_rx_status(8),
      PIPERXSTATUSL2(1) => pipe_rx_status(7),
      PIPERXSTATUSL2(0) => pipe_rx_status(6),
      PIPERXDATAL2(7) => pipe_rx_data_l2_out(7),
      PIPERXDATAL2(6) => pipe_rx_data_l2_out(6),
      PIPERXDATAL2(5) => pipe_rx_data_l2_out(5),
      PIPERXDATAL2(4) => pipe_rx_data_l2_out(4),
      PIPERXDATAL2(3) => pipe_rx_data_l2_out(3),
      PIPERXDATAL2(2) => pipe_rx_data_l2_out(2),
      PIPERXDATAL2(1) => pipe_rx_data_l2_out(1),
      PIPERXDATAL2(0) => pipe_rx_data_l2_out(0),
      PIPETXDATAL2(7) => pipe_tx_data_l2(7),
      PIPETXDATAL2(6) => pipe_tx_data_l2(6),
      PIPETXDATAL2(5) => pipe_tx_data_l2(5),
      PIPETXDATAL2(4) => pipe_tx_data_l2(4),
      PIPETXDATAL2(3) => pipe_tx_data_l2(3),
      PIPETXDATAL2(2) => pipe_tx_data_l2(2),
      PIPETXDATAL2(1) => pipe_tx_data_l2(1),
      PIPETXDATAL2(0) => pipe_tx_data_l2(0),
      PIPEPOWERDOWNL2(1) => pipe_power_down_l2(1),
      PIPEPOWERDOWNL2(0) => pipe_power_down_l2(0),
      PIPERXSTATUSL3(2) => pipe_rx_status(11),
      PIPERXSTATUSL3(1) => pipe_rx_status(10),
      PIPERXSTATUSL3(0) => pipe_rx_status(9),
      PIPERXDATAL3(7) => pipe_rx_data_l3_out(7),
      PIPERXDATAL3(6) => pipe_rx_data_l3_out(6),
      PIPERXDATAL3(5) => pipe_rx_data_l3_out(5),
      PIPERXDATAL3(4) => pipe_rx_data_l3_out(4),
      PIPERXDATAL3(3) => pipe_rx_data_l3_out(3),
      PIPERXDATAL3(2) => pipe_rx_data_l3_out(2),
      PIPERXDATAL3(1) => pipe_rx_data_l3_out(1),
      PIPERXDATAL3(0) => pipe_rx_data_l3_out(0),
      PIPETXDATAL3(7) => pipe_tx_data_l3(7),
      PIPETXDATAL3(6) => pipe_tx_data_l3(6),
      PIPETXDATAL3(5) => pipe_tx_data_l3(5),
      PIPETXDATAL3(4) => pipe_tx_data_l3(4),
      PIPETXDATAL3(3) => pipe_tx_data_l3(3),
      PIPETXDATAL3(2) => pipe_tx_data_l3(2),
      PIPETXDATAL3(1) => pipe_tx_data_l3(1),
      PIPETXDATAL3(0) => pipe_tx_data_l3(0),
      PIPEPOWERDOWNL3(1) => pipe_power_down_l3(1),
      PIPEPOWERDOWNL3(0) => pipe_power_down_l3(0),
      PIPERXSTATUSL4(2) => pipe_rx_status(14),
      PIPERXSTATUSL4(1) => pipe_rx_status(13),
      PIPERXSTATUSL4(0) => pipe_rx_status(12),
      PIPERXDATAL4(7) => pipe_rx_data_l4_out(7),
      PIPERXDATAL4(6) => pipe_rx_data_l4_out(6),
      PIPERXDATAL4(5) => pipe_rx_data_l4_out(5),
      PIPERXDATAL4(4) => pipe_rx_data_l4_out(4),
      PIPERXDATAL4(3) => pipe_rx_data_l4_out(3),
      PIPERXDATAL4(2) => pipe_rx_data_l4_out(2),
      PIPERXDATAL4(1) => pipe_rx_data_l4_out(1),
      PIPERXDATAL4(0) => pipe_rx_data_l4_out(0),
      PIPETXDATAL4(7) => pipe_tx_data_l4(7),
      PIPETXDATAL4(6) => pipe_tx_data_l4(6),
      PIPETXDATAL4(5) => pipe_tx_data_l4(5),
      PIPETXDATAL4(4) => pipe_tx_data_l4(4),
      PIPETXDATAL4(3) => pipe_tx_data_l4(3),
      PIPETXDATAL4(2) => pipe_tx_data_l4(2),
      PIPETXDATAL4(1) => pipe_tx_data_l4(1),
      PIPETXDATAL4(0) => pipe_tx_data_l4(0),
      PIPEPOWERDOWNL4(1) => pipe_power_down_l4(1),
      PIPEPOWERDOWNL4(0) => pipe_power_down_l4(0),
      PIPERXSTATUSL5(2) => pipe_rx_status(17),
      PIPERXSTATUSL5(1) => pipe_rx_status(16),
      PIPERXSTATUSL5(0) => pipe_rx_status(15),
      PIPERXDATAL5(7) => pipe_rx_data_l5_out(7),
      PIPERXDATAL5(6) => pipe_rx_data_l5_out(6),
      PIPERXDATAL5(5) => pipe_rx_data_l5_out(5),
      PIPERXDATAL5(4) => pipe_rx_data_l5_out(4),
      PIPERXDATAL5(3) => pipe_rx_data_l5_out(3),
      PIPERXDATAL5(2) => pipe_rx_data_l5_out(2),
      PIPERXDATAL5(1) => pipe_rx_data_l5_out(1),
      PIPERXDATAL5(0) => pipe_rx_data_l5_out(0),
      PIPETXDATAL5(7) => pipe_tx_data_l5(7),
      PIPETXDATAL5(6) => pipe_tx_data_l5(6),
      PIPETXDATAL5(5) => pipe_tx_data_l5(5),
      PIPETXDATAL5(4) => pipe_tx_data_l5(4),
      PIPETXDATAL5(3) => pipe_tx_data_l5(3),
      PIPETXDATAL5(2) => pipe_tx_data_l5(2),
      PIPETXDATAL5(1) => pipe_tx_data_l5(1),
      PIPETXDATAL5(0) => pipe_tx_data_l5(0),
      PIPEPOWERDOWNL5(1) => pipe_power_down_l5(1),
      PIPEPOWERDOWNL5(0) => pipe_power_down_l5(0),
      PIPERXSTATUSL6(2) => pipe_rx_status(20),
      PIPERXSTATUSL6(1) => pipe_rx_status(19),
      PIPERXSTATUSL6(0) => pipe_rx_status(18),
      PIPERXDATAL6(7) => pipe_rx_data_l6_out(7),
      PIPERXDATAL6(6) => pipe_rx_data_l6_out(6),
      PIPERXDATAL6(5) => pipe_rx_data_l6_out(5),
      PIPERXDATAL6(4) => pipe_rx_data_l6_out(4),
      PIPERXDATAL6(3) => pipe_rx_data_l6_out(3),
      PIPERXDATAL6(2) => pipe_rx_data_l6_out(2),
      PIPERXDATAL6(1) => pipe_rx_data_l6_out(1),
      PIPERXDATAL6(0) => pipe_rx_data_l6_out(0),
      PIPETXDATAL6(7) => pipe_tx_data_l6(7),
      PIPETXDATAL6(6) => pipe_tx_data_l6(6),
      PIPETXDATAL6(5) => pipe_tx_data_l6(5),
      PIPETXDATAL6(4) => pipe_tx_data_l6(4),
      PIPETXDATAL6(3) => pipe_tx_data_l6(3),
      PIPETXDATAL6(2) => pipe_tx_data_l6(2),
      PIPETXDATAL6(1) => pipe_tx_data_l6(1),
      PIPETXDATAL6(0) => pipe_tx_data_l6(0),
      PIPEPOWERDOWNL6(1) => pipe_power_down_l6(1),
      PIPEPOWERDOWNL6(0) => pipe_power_down_l6(0),
      PIPERXSTATUSL7(2) => pipe_rx_status(23),
      PIPERXSTATUSL7(1) => pipe_rx_status(22),
      PIPERXSTATUSL7(0) => pipe_rx_status(21),
      PIPERXDATAL7(7) => pipe_rx_data_l7_out(7),
      PIPERXDATAL7(6) => pipe_rx_data_l7_out(6),
      PIPERXDATAL7(5) => pipe_rx_data_l7_out(5),
      PIPERXDATAL7(4) => pipe_rx_data_l7_out(4),
      PIPERXDATAL7(3) => pipe_rx_data_l7_out(3),
      PIPERXDATAL7(2) => pipe_rx_data_l7_out(2),
      PIPERXDATAL7(1) => pipe_rx_data_l7_out(1),
      PIPERXDATAL7(0) => pipe_rx_data_l7_out(0),
      PIPETXDATAL7(7) => pipe_tx_data_l7(7),
      PIPETXDATAL7(6) => pipe_tx_data_l7(6),
      PIPETXDATAL7(5) => pipe_tx_data_l7(5),
      PIPETXDATAL7(4) => pipe_tx_data_l7(4),
      PIPETXDATAL7(3) => pipe_tx_data_l7(3),
      PIPETXDATAL7(2) => pipe_tx_data_l7(2),
      PIPETXDATAL7(1) => pipe_tx_data_l7(1),
      PIPETXDATAL7(0) => pipe_tx_data_l7(0),
      PIPEPOWERDOWNL7(1) => pipe_power_down_l7(1),
      PIPEPOWERDOWNL7(0) => pipe_power_down_l7(0),
      MIMRXBWDATA(63) => NlwRenamedSig_OI_DEBUG(170),
      MIMRXBWDATA(62) => NlwRenamedSig_OI_DEBUG(169),
      MIMRXBWDATA(61) => NlwRenamedSig_OI_DEBUG(168),
      MIMRXBWDATA(60) => NlwRenamedSig_OI_DEBUG(167),
      MIMRXBWDATA(59) => NlwRenamedSig_OI_DEBUG(166),
      MIMRXBWDATA(58) => NlwRenamedSig_OI_DEBUG(165),
      MIMRXBWDATA(57) => NlwRenamedSig_OI_DEBUG(164),
      MIMRXBWDATA(56) => NlwRenamedSig_OI_DEBUG(163),
      MIMRXBWDATA(55) => NlwRenamedSig_OI_DEBUG(162),
      MIMRXBWDATA(54) => NlwRenamedSig_OI_DEBUG(161),
      MIMRXBWDATA(53) => NlwRenamedSig_OI_DEBUG(160),
      MIMRXBWDATA(52) => NlwRenamedSig_OI_DEBUG(159),
      MIMRXBWDATA(51) => NlwRenamedSig_OI_DEBUG(158),
      MIMRXBWDATA(50) => NlwRenamedSig_OI_DEBUG(157),
      MIMRXBWDATA(49) => NlwRenamedSig_OI_DEBUG(156),
      MIMRXBWDATA(48) => NlwRenamedSig_OI_DEBUG(155),
      MIMRXBWDATA(47) => NlwRenamedSig_OI_DEBUG(154),
      MIMRXBWDATA(46) => NlwRenamedSig_OI_DEBUG(153),
      MIMRXBWDATA(45) => NlwRenamedSig_OI_DEBUG(152),
      MIMRXBWDATA(44) => NlwRenamedSig_OI_DEBUG(151),
      MIMRXBWDATA(43) => NlwRenamedSig_OI_DEBUG(150),
      MIMRXBWDATA(42) => NlwRenamedSig_OI_DEBUG(149),
      MIMRXBWDATA(41) => NlwRenamedSig_OI_DEBUG(148),
      MIMRXBWDATA(40) => NlwRenamedSig_OI_DEBUG(147),
      MIMRXBWDATA(39) => NlwRenamedSig_OI_DEBUG(146),
      MIMRXBWDATA(38) => NlwRenamedSig_OI_DEBUG(145),
      MIMRXBWDATA(37) => NlwRenamedSig_OI_DEBUG(144),
      MIMRXBWDATA(36) => NlwRenamedSig_OI_DEBUG(143),
      MIMRXBWDATA(35) => NlwRenamedSig_OI_DEBUG(142),
      MIMRXBWDATA(34) => NlwRenamedSig_OI_DEBUG(141),
      MIMRXBWDATA(33) => NlwRenamedSig_OI_DEBUG(140),
      MIMRXBWDATA(32) => NlwRenamedSig_OI_DEBUG(139),
      MIMRXBWDATA(31) => NlwRenamedSig_OI_DEBUG(138),
      MIMRXBWDATA(30) => NlwRenamedSig_OI_DEBUG(137),
      MIMRXBWDATA(29) => NlwRenamedSig_OI_DEBUG(136),
      MIMRXBWDATA(28) => NlwRenamedSig_OI_DEBUG(135),
      MIMRXBWDATA(27) => NlwRenamedSig_OI_DEBUG(134),
      MIMRXBWDATA(26) => NlwRenamedSig_OI_DEBUG(133),
      MIMRXBWDATA(25) => NlwRenamedSig_OI_DEBUG(132),
      MIMRXBWDATA(24) => NlwRenamedSig_OI_DEBUG(131),
      MIMRXBWDATA(23) => NlwRenamedSig_OI_DEBUG(130),
      MIMRXBWDATA(22) => NlwRenamedSig_OI_DEBUG(129),
      MIMRXBWDATA(21) => NlwRenamedSig_OI_DEBUG(128),
      MIMRXBWDATA(20) => NlwRenamedSig_OI_DEBUG(127),
      MIMRXBWDATA(19) => NlwRenamedSig_OI_DEBUG(126),
      MIMRXBWDATA(18) => NlwRenamedSig_OI_DEBUG(125),
      MIMRXBWDATA(17) => NlwRenamedSig_OI_DEBUG(124),
      MIMRXBWDATA(16) => NlwRenamedSig_OI_DEBUG(123),
      MIMRXBWDATA(15) => NlwRenamedSig_OI_DEBUG(122),
      MIMRXBWDATA(14) => NlwRenamedSig_OI_DEBUG(121),
      MIMRXBWDATA(13) => NlwRenamedSig_OI_DEBUG(120),
      MIMRXBWDATA(12) => NlwRenamedSig_OI_DEBUG(119),
      MIMRXBWDATA(11) => NlwRenamedSig_OI_DEBUG(118),
      MIMRXBWDATA(10) => NlwRenamedSig_OI_DEBUG(117),
      MIMRXBWDATA(9) => NlwRenamedSig_OI_DEBUG(116),
      MIMRXBWDATA(8) => NlwRenamedSig_OI_DEBUG(115),
      MIMRXBWDATA(7) => NlwRenamedSig_OI_DEBUG(114),
      MIMRXBWDATA(6) => NlwRenamedSig_OI_DEBUG(113),
      MIMRXBWDATA(5) => NlwRenamedSig_OI_DEBUG(112),
      MIMRXBWDATA(4) => NlwRenamedSig_OI_DEBUG(111),
      MIMRXBWDATA(3) => NlwRenamedSig_OI_DEBUG(110),
      MIMRXBWDATA(2) => NlwRenamedSig_OI_DEBUG(109),
      MIMRXBWDATA(1) => NlwRenamedSig_OI_DEBUG(108),
      MIMRXBWDATA(0) => NlwRenamedSig_OI_DEBUG(107),
      MIMRXBWADD(12) => NlwRenamedSig_OI_DEBUG(104),
      MIMRXBWADD(11) => NlwRenamedSig_OI_DEBUG(103),
      MIMRXBWADD(10) => NlwRenamedSig_OI_DEBUG(102),
      MIMRXBWADD(9) => NlwRenamedSig_OI_DEBUG(101),
      MIMRXBWADD(8) => NlwRenamedSig_OI_DEBUG(100),
      MIMRXBWADD(7) => NlwRenamedSig_OI_DEBUG(99),
      MIMRXBWADD(6) => NlwRenamedSig_OI_DEBUG(98),
      MIMRXBWADD(5) => NlwRenamedSig_OI_DEBUG(97),
      MIMRXBWADD(4) => NlwRenamedSig_OI_DEBUG(96),
      MIMRXBWADD(3) => NlwRenamedSig_OI_DEBUG(95),
      MIMRXBWADD(2) => NlwRenamedSig_OI_DEBUG(94),
      MIMRXBWADD(1) => NlwRenamedSig_OI_DEBUG(93),
      MIMRXBWADD(0) => NlwRenamedSig_OI_DEBUG(92),
      MIMRXBRADD(12) => NlwRenamedSig_OI_DEBUG(183),
      MIMRXBRADD(11) => NlwRenamedSig_OI_DEBUG(182),
      MIMRXBRADD(10) => NlwRenamedSig_OI_DEBUG(181),
      MIMRXBRADD(9) => NlwRenamedSig_OI_DEBUG(180),
      MIMRXBRADD(8) => NlwRenamedSig_OI_DEBUG(179),
      MIMRXBRADD(7) => NlwRenamedSig_OI_DEBUG(178),
      MIMRXBRADD(6) => NlwRenamedSig_OI_DEBUG(177),
      MIMRXBRADD(5) => NlwRenamedSig_OI_DEBUG(176),
      MIMRXBRADD(4) => NlwRenamedSig_OI_DEBUG(175),
      MIMRXBRADD(3) => NlwRenamedSig_OI_DEBUG(174),
      MIMRXBRADD(2) => NlwRenamedSig_OI_DEBUG(173),
      MIMRXBRADD(1) => NlwRenamedSig_OI_DEBUG(172),
      MIMRXBRADD(0) => NlwRenamedSig_OI_DEBUG(171),
      MIMRXBRDATA(63) => mim_rx_brdata(63),
      MIMRXBRDATA(62) => mim_rx_brdata(62),
      MIMRXBRDATA(61) => mim_rx_brdata(61),
      MIMRXBRDATA(60) => mim_rx_brdata(60),
      MIMRXBRDATA(59) => mim_rx_brdata(59),
      MIMRXBRDATA(58) => mim_rx_brdata(58),
      MIMRXBRDATA(57) => mim_rx_brdata(57),
      MIMRXBRDATA(56) => mim_rx_brdata(56),
      MIMRXBRDATA(55) => mim_rx_brdata(55),
      MIMRXBRDATA(54) => mim_rx_brdata(54),
      MIMRXBRDATA(53) => mim_rx_brdata(53),
      MIMRXBRDATA(52) => mim_rx_brdata(52),
      MIMRXBRDATA(51) => mim_rx_brdata(51),
      MIMRXBRDATA(50) => mim_rx_brdata(50),
      MIMRXBRDATA(49) => mim_rx_brdata(49),
      MIMRXBRDATA(48) => mim_rx_brdata(48),
      MIMRXBRDATA(47) => mim_rx_brdata(47),
      MIMRXBRDATA(46) => mim_rx_brdata(46),
      MIMRXBRDATA(45) => mim_rx_brdata(45),
      MIMRXBRDATA(44) => mim_rx_brdata(44),
      MIMRXBRDATA(43) => mim_rx_brdata(43),
      MIMRXBRDATA(42) => mim_rx_brdata(42),
      MIMRXBRDATA(41) => mim_rx_brdata(41),
      MIMRXBRDATA(40) => mim_rx_brdata(40),
      MIMRXBRDATA(39) => mim_rx_brdata(39),
      MIMRXBRDATA(38) => mim_rx_brdata(38),
      MIMRXBRDATA(37) => mim_rx_brdata(37),
      MIMRXBRDATA(36) => mim_rx_brdata(36),
      MIMRXBRDATA(35) => mim_rx_brdata(35),
      MIMRXBRDATA(34) => mim_rx_brdata(34),
      MIMRXBRDATA(33) => mim_rx_brdata(33),
      MIMRXBRDATA(32) => mim_rx_brdata(32),
      MIMRXBRDATA(31) => mim_rx_brdata(31),
      MIMRXBRDATA(30) => mim_rx_brdata(30),
      MIMRXBRDATA(29) => mim_rx_brdata(29),
      MIMRXBRDATA(28) => mim_rx_brdata(28),
      MIMRXBRDATA(27) => mim_rx_brdata(27),
      MIMRXBRDATA(26) => mim_rx_brdata(26),
      MIMRXBRDATA(25) => mim_rx_brdata(25),
      MIMRXBRDATA(24) => mim_rx_brdata(24),
      MIMRXBRDATA(23) => mim_rx_brdata(23),
      MIMRXBRDATA(22) => mim_rx_brdata(22),
      MIMRXBRDATA(21) => mim_rx_brdata(21),
      MIMRXBRDATA(20) => mim_rx_brdata(20),
      MIMRXBRDATA(19) => mim_rx_brdata(19),
      MIMRXBRDATA(18) => mim_rx_brdata(18),
      MIMRXBRDATA(17) => mim_rx_brdata(17),
      MIMRXBRDATA(16) => mim_rx_brdata(16),
      MIMRXBRDATA(15) => mim_rx_brdata(15),
      MIMRXBRDATA(14) => mim_rx_brdata(14),
      MIMRXBRDATA(13) => mim_rx_brdata(13),
      MIMRXBRDATA(12) => mim_rx_brdata(12),
      MIMRXBRDATA(11) => mim_rx_brdata(11),
      MIMRXBRDATA(10) => mim_rx_brdata(10),
      MIMRXBRDATA(9) => mim_rx_brdata(9),
      MIMRXBRDATA(8) => mim_rx_brdata(8),
      MIMRXBRDATA(7) => mim_rx_brdata(7),
      MIMRXBRDATA(6) => mim_rx_brdata(6),
      MIMRXBRDATA(5) => mim_rx_brdata(5),
      MIMRXBRDATA(4) => mim_rx_brdata(4),
      MIMRXBRDATA(3) => mim_rx_brdata(3),
      MIMRXBRDATA(2) => mim_rx_brdata(2),
      MIMRXBRDATA(1) => mim_rx_brdata(1),
      MIMRXBRDATA(0) => mim_rx_brdata(0),
      MIMTXBWDATA(63) => NlwRenamedSig_OI_DEBUG(78),
      MIMTXBWDATA(62) => NlwRenamedSig_OI_DEBUG(77),
      MIMTXBWDATA(61) => NlwRenamedSig_OI_DEBUG(76),
      MIMTXBWDATA(60) => NlwRenamedSig_OI_DEBUG(75),
      MIMTXBWDATA(59) => NlwRenamedSig_OI_DEBUG(74),
      MIMTXBWDATA(58) => NlwRenamedSig_OI_DEBUG(73),
      MIMTXBWDATA(57) => NlwRenamedSig_OI_DEBUG(72),
      MIMTXBWDATA(56) => NlwRenamedSig_OI_DEBUG(71),
      MIMTXBWDATA(55) => NlwRenamedSig_OI_DEBUG(70),
      MIMTXBWDATA(54) => NlwRenamedSig_OI_DEBUG(69),
      MIMTXBWDATA(53) => NlwRenamedSig_OI_DEBUG(68),
      MIMTXBWDATA(52) => NlwRenamedSig_OI_DEBUG(67),
      MIMTXBWDATA(51) => NlwRenamedSig_OI_DEBUG(66),
      MIMTXBWDATA(50) => NlwRenamedSig_OI_DEBUG(65),
      MIMTXBWDATA(49) => NlwRenamedSig_OI_DEBUG(64),
      MIMTXBWDATA(48) => NlwRenamedSig_OI_DEBUG(63),
      MIMTXBWDATA(47) => NlwRenamedSig_OI_DEBUG(62),
      MIMTXBWDATA(46) => NlwRenamedSig_OI_DEBUG(61),
      MIMTXBWDATA(45) => NlwRenamedSig_OI_DEBUG(60),
      MIMTXBWDATA(44) => NlwRenamedSig_OI_DEBUG(59),
      MIMTXBWDATA(43) => NlwRenamedSig_OI_DEBUG(58),
      MIMTXBWDATA(42) => NlwRenamedSig_OI_DEBUG(57),
      MIMTXBWDATA(41) => NlwRenamedSig_OI_DEBUG(56),
      MIMTXBWDATA(40) => NlwRenamedSig_OI_DEBUG(55),
      MIMTXBWDATA(39) => NlwRenamedSig_OI_DEBUG(54),
      MIMTXBWDATA(38) => NlwRenamedSig_OI_DEBUG(53),
      MIMTXBWDATA(37) => NlwRenamedSig_OI_DEBUG(52),
      MIMTXBWDATA(36) => NlwRenamedSig_OI_DEBUG(51),
      MIMTXBWDATA(35) => NlwRenamedSig_OI_DEBUG(50),
      MIMTXBWDATA(34) => NlwRenamedSig_OI_DEBUG(49),
      MIMTXBWDATA(33) => NlwRenamedSig_OI_DEBUG(48),
      MIMTXBWDATA(32) => NlwRenamedSig_OI_DEBUG(47),
      MIMTXBWDATA(31) => NlwRenamedSig_OI_DEBUG(46),
      MIMTXBWDATA(30) => NlwRenamedSig_OI_DEBUG(45),
      MIMTXBWDATA(29) => NlwRenamedSig_OI_DEBUG(44),
      MIMTXBWDATA(28) => NlwRenamedSig_OI_DEBUG(43),
      MIMTXBWDATA(27) => NlwRenamedSig_OI_DEBUG(42),
      MIMTXBWDATA(26) => NlwRenamedSig_OI_DEBUG(41),
      MIMTXBWDATA(25) => NlwRenamedSig_OI_DEBUG(40),
      MIMTXBWDATA(24) => NlwRenamedSig_OI_DEBUG(39),
      MIMTXBWDATA(23) => NlwRenamedSig_OI_DEBUG(38),
      MIMTXBWDATA(22) => NlwRenamedSig_OI_DEBUG(37),
      MIMTXBWDATA(21) => NlwRenamedSig_OI_DEBUG(36),
      MIMTXBWDATA(20) => NlwRenamedSig_OI_DEBUG(35),
      MIMTXBWDATA(19) => NlwRenamedSig_OI_DEBUG(34),
      MIMTXBWDATA(18) => NlwRenamedSig_OI_DEBUG(33),
      MIMTXBWDATA(17) => NlwRenamedSig_OI_DEBUG(32),
      MIMTXBWDATA(16) => NlwRenamedSig_OI_DEBUG(31),
      MIMTXBWDATA(15) => NlwRenamedSig_OI_DEBUG(30),
      MIMTXBWDATA(14) => NlwRenamedSig_OI_DEBUG(29),
      MIMTXBWDATA(13) => NlwRenamedSig_OI_DEBUG(28),
      MIMTXBWDATA(12) => NlwRenamedSig_OI_DEBUG(27),
      MIMTXBWDATA(11) => NlwRenamedSig_OI_DEBUG(26),
      MIMTXBWDATA(10) => NlwRenamedSig_OI_DEBUG(25),
      MIMTXBWDATA(9) => NlwRenamedSig_OI_DEBUG(24),
      MIMTXBWDATA(8) => NlwRenamedSig_OI_DEBUG(23),
      MIMTXBWDATA(7) => NlwRenamedSig_OI_DEBUG(22),
      MIMTXBWDATA(6) => NlwRenamedSig_OI_DEBUG(21),
      MIMTXBWDATA(5) => NlwRenamedSig_OI_DEBUG(20),
      MIMTXBWDATA(4) => NlwRenamedSig_OI_DEBUG(19),
      MIMTXBWDATA(3) => NlwRenamedSig_OI_DEBUG(18),
      MIMTXBWDATA(2) => NlwRenamedSig_OI_DEBUG(17),
      MIMTXBWDATA(1) => NlwRenamedSig_OI_DEBUG(16),
      MIMTXBWDATA(0) => NlwRenamedSig_OI_DEBUG(15),
      MIMTXBWADD(12) => NlwRenamedSig_OI_DEBUG(12),
      MIMTXBWADD(11) => NlwRenamedSig_OI_DEBUG(11),
      MIMTXBWADD(10) => NlwRenamedSig_OI_DEBUG(10),
      MIMTXBWADD(9) => NlwRenamedSig_OI_DEBUG(9),
      MIMTXBWADD(8) => NlwRenamedSig_OI_DEBUG(8),
      MIMTXBWADD(7) => NlwRenamedSig_OI_DEBUG(7),
      MIMTXBWADD(6) => NlwRenamedSig_OI_DEBUG(6),
      MIMTXBWADD(5) => NlwRenamedSig_OI_DEBUG(5),
      MIMTXBWADD(4) => NlwRenamedSig_OI_DEBUG(4),
      MIMTXBWADD(3) => NlwRenamedSig_OI_DEBUG(3),
      MIMTXBWADD(2) => NlwRenamedSig_OI_DEBUG(2),
      MIMTXBWADD(1) => NlwRenamedSig_OI_DEBUG(1),
      MIMTXBWADD(0) => NlwRenamedSig_OI_DEBUG(0),
      MIMTXBRADD(12) => NlwRenamedSig_OI_DEBUG(91),
      MIMTXBRADD(11) => NlwRenamedSig_OI_DEBUG(90),
      MIMTXBRADD(10) => NlwRenamedSig_OI_DEBUG(89),
      MIMTXBRADD(9) => NlwRenamedSig_OI_DEBUG(88),
      MIMTXBRADD(8) => NlwRenamedSig_OI_DEBUG(87),
      MIMTXBRADD(7) => NlwRenamedSig_OI_DEBUG(86),
      MIMTXBRADD(6) => NlwRenamedSig_OI_DEBUG(85),
      MIMTXBRADD(5) => NlwRenamedSig_OI_DEBUG(84),
      MIMTXBRADD(4) => NlwRenamedSig_OI_DEBUG(83),
      MIMTXBRADD(3) => NlwRenamedSig_OI_DEBUG(82),
      MIMTXBRADD(2) => NlwRenamedSig_OI_DEBUG(81),
      MIMTXBRADD(1) => NlwRenamedSig_OI_DEBUG(80),
      MIMTXBRADD(0) => NlwRenamedSig_OI_DEBUG(79),
      MIMTXBRDATA(63) => mim_tx_brdata(63),
      MIMTXBRDATA(62) => mim_tx_brdata(62),
      MIMTXBRDATA(61) => mim_tx_brdata(61),
      MIMTXBRDATA(60) => mim_tx_brdata(60),
      MIMTXBRDATA(59) => mim_tx_brdata(59),
      MIMTXBRDATA(58) => mim_tx_brdata(58),
      MIMTXBRDATA(57) => mim_tx_brdata(57),
      MIMTXBRDATA(56) => mim_tx_brdata(56),
      MIMTXBRDATA(55) => mim_tx_brdata(55),
      MIMTXBRDATA(54) => mim_tx_brdata(54),
      MIMTXBRDATA(53) => mim_tx_brdata(53),
      MIMTXBRDATA(52) => mim_tx_brdata(52),
      MIMTXBRDATA(51) => mim_tx_brdata(51),
      MIMTXBRDATA(50) => mim_tx_brdata(50),
      MIMTXBRDATA(49) => mim_tx_brdata(49),
      MIMTXBRDATA(48) => mim_tx_brdata(48),
      MIMTXBRDATA(47) => mim_tx_brdata(47),
      MIMTXBRDATA(46) => mim_tx_brdata(46),
      MIMTXBRDATA(45) => mim_tx_brdata(45),
      MIMTXBRDATA(44) => mim_tx_brdata(44),
      MIMTXBRDATA(43) => mim_tx_brdata(43),
      MIMTXBRDATA(42) => mim_tx_brdata(42),
      MIMTXBRDATA(41) => mim_tx_brdata(41),
      MIMTXBRDATA(40) => mim_tx_brdata(40),
      MIMTXBRDATA(39) => mim_tx_brdata(39),
      MIMTXBRDATA(38) => mim_tx_brdata(38),
      MIMTXBRDATA(37) => mim_tx_brdata(37),
      MIMTXBRDATA(36) => mim_tx_brdata(36),
      MIMTXBRDATA(35) => mim_tx_brdata(35),
      MIMTXBRDATA(34) => mim_tx_brdata(34),
      MIMTXBRDATA(33) => mim_tx_brdata(33),
      MIMTXBRDATA(32) => mim_tx_brdata(32),
      MIMTXBRDATA(31) => mim_tx_brdata(31),
      MIMTXBRDATA(30) => mim_tx_brdata(30),
      MIMTXBRDATA(29) => mim_tx_brdata(29),
      MIMTXBRDATA(28) => mim_tx_brdata(28),
      MIMTXBRDATA(27) => mim_tx_brdata(27),
      MIMTXBRDATA(26) => mim_tx_brdata(26),
      MIMTXBRDATA(25) => mim_tx_brdata(25),
      MIMTXBRDATA(24) => mim_tx_brdata(24),
      MIMTXBRDATA(23) => mim_tx_brdata(23),
      MIMTXBRDATA(22) => mim_tx_brdata(22),
      MIMTXBRDATA(21) => mim_tx_brdata(21),
      MIMTXBRDATA(20) => mim_tx_brdata(20),
      MIMTXBRDATA(19) => mim_tx_brdata(19),
      MIMTXBRDATA(18) => mim_tx_brdata(18),
      MIMTXBRDATA(17) => mim_tx_brdata(17),
      MIMTXBRDATA(16) => mim_tx_brdata(16),
      MIMTXBRDATA(15) => mim_tx_brdata(15),
      MIMTXBRDATA(14) => mim_tx_brdata(14),
      MIMTXBRDATA(13) => mim_tx_brdata(13),
      MIMTXBRDATA(12) => mim_tx_brdata(12),
      MIMTXBRDATA(11) => mim_tx_brdata(11),
      MIMTXBRDATA(10) => mim_tx_brdata(10),
      MIMTXBRDATA(9) => mim_tx_brdata(9),
      MIMTXBRDATA(8) => mim_tx_brdata(8),
      MIMTXBRDATA(7) => mim_tx_brdata(7),
      MIMTXBRDATA(6) => mim_tx_brdata(6),
      MIMTXBRDATA(5) => mim_tx_brdata(5),
      MIMTXBRDATA(4) => mim_tx_brdata(4),
      MIMTXBRDATA(3) => mim_tx_brdata(3),
      MIMTXBRDATA(2) => mim_tx_brdata(2),
      MIMTXBRDATA(1) => mim_tx_brdata(1),
      MIMTXBRDATA(0) => mim_tx_brdata(0),
      MIMDLLBWDATA(63) => NlwRenamedSig_OI_DEBUG(324),
      MIMDLLBWDATA(62) => NlwRenamedSig_OI_DEBUG(323),
      MIMDLLBWDATA(61) => NlwRenamedSig_OI_DEBUG(322),
      MIMDLLBWDATA(60) => NlwRenamedSig_OI_DEBUG(321),
      MIMDLLBWDATA(59) => NlwRenamedSig_OI_DEBUG(320),
      MIMDLLBWDATA(58) => NlwRenamedSig_OI_DEBUG(319),
      MIMDLLBWDATA(57) => NlwRenamedSig_OI_DEBUG(318),
      MIMDLLBWDATA(56) => NlwRenamedSig_OI_DEBUG(317),
      MIMDLLBWDATA(55) => NlwRenamedSig_OI_DEBUG(316),
      MIMDLLBWDATA(54) => NlwRenamedSig_OI_DEBUG(315),
      MIMDLLBWDATA(53) => NlwRenamedSig_OI_DEBUG(314),
      MIMDLLBWDATA(52) => NlwRenamedSig_OI_DEBUG(313),
      MIMDLLBWDATA(51) => NlwRenamedSig_OI_DEBUG(312),
      MIMDLLBWDATA(50) => NlwRenamedSig_OI_DEBUG(311),
      MIMDLLBWDATA(49) => NlwRenamedSig_OI_DEBUG(310),
      MIMDLLBWDATA(48) => NlwRenamedSig_OI_DEBUG(309),
      MIMDLLBWDATA(47) => NlwRenamedSig_OI_DEBUG(308),
      MIMDLLBWDATA(46) => NlwRenamedSig_OI_DEBUG(307),
      MIMDLLBWDATA(45) => NlwRenamedSig_OI_DEBUG(306),
      MIMDLLBWDATA(44) => NlwRenamedSig_OI_DEBUG(305),
      MIMDLLBWDATA(43) => NlwRenamedSig_OI_DEBUG(304),
      MIMDLLBWDATA(42) => NlwRenamedSig_OI_DEBUG(303),
      MIMDLLBWDATA(41) => NlwRenamedSig_OI_DEBUG(302),
      MIMDLLBWDATA(40) => NlwRenamedSig_OI_DEBUG(301),
      MIMDLLBWDATA(39) => NlwRenamedSig_OI_DEBUG(300),
      MIMDLLBWDATA(38) => NlwRenamedSig_OI_DEBUG(299),
      MIMDLLBWDATA(37) => NlwRenamedSig_OI_DEBUG(298),
      MIMDLLBWDATA(36) => NlwRenamedSig_OI_DEBUG(297),
      MIMDLLBWDATA(35) => NlwRenamedSig_OI_DEBUG(296),
      MIMDLLBWDATA(34) => NlwRenamedSig_OI_DEBUG(295),
      MIMDLLBWDATA(33) => NlwRenamedSig_OI_DEBUG(294),
      MIMDLLBWDATA(32) => NlwRenamedSig_OI_DEBUG(293),
      MIMDLLBWDATA(31) => NlwRenamedSig_OI_DEBUG(292),
      MIMDLLBWDATA(30) => NlwRenamedSig_OI_DEBUG(291),
      MIMDLLBWDATA(29) => NlwRenamedSig_OI_DEBUG(290),
      MIMDLLBWDATA(28) => NlwRenamedSig_OI_DEBUG(289),
      MIMDLLBWDATA(27) => NlwRenamedSig_OI_DEBUG(288),
      MIMDLLBWDATA(26) => NlwRenamedSig_OI_DEBUG(287),
      MIMDLLBWDATA(25) => NlwRenamedSig_OI_DEBUG(286),
      MIMDLLBWDATA(24) => NlwRenamedSig_OI_DEBUG(285),
      MIMDLLBWDATA(23) => NlwRenamedSig_OI_DEBUG(284),
      MIMDLLBWDATA(22) => NlwRenamedSig_OI_DEBUG(283),
      MIMDLLBWDATA(21) => NlwRenamedSig_OI_DEBUG(282),
      MIMDLLBWDATA(20) => NlwRenamedSig_OI_DEBUG(281),
      MIMDLLBWDATA(19) => NlwRenamedSig_OI_DEBUG(280),
      MIMDLLBWDATA(18) => NlwRenamedSig_OI_DEBUG(279),
      MIMDLLBWDATA(17) => NlwRenamedSig_OI_DEBUG(278),
      MIMDLLBWDATA(16) => NlwRenamedSig_OI_DEBUG(277),
      MIMDLLBWDATA(15) => NlwRenamedSig_OI_DEBUG(276),
      MIMDLLBWDATA(14) => NlwRenamedSig_OI_DEBUG(275),
      MIMDLLBWDATA(13) => NlwRenamedSig_OI_DEBUG(274),
      MIMDLLBWDATA(12) => NlwRenamedSig_OI_DEBUG(273),
      MIMDLLBWDATA(11) => NlwRenamedSig_OI_DEBUG(272),
      MIMDLLBWDATA(10) => NlwRenamedSig_OI_DEBUG(271),
      MIMDLLBWDATA(9) => NlwRenamedSig_OI_DEBUG(270),
      MIMDLLBWDATA(8) => NlwRenamedSig_OI_DEBUG(269),
      MIMDLLBWDATA(7) => NlwRenamedSig_OI_DEBUG(268),
      MIMDLLBWDATA(6) => NlwRenamedSig_OI_DEBUG(267),
      MIMDLLBWDATA(5) => NlwRenamedSig_OI_DEBUG(266),
      MIMDLLBWDATA(4) => NlwRenamedSig_OI_DEBUG(265),
      MIMDLLBWDATA(3) => NlwRenamedSig_OI_DEBUG(264),
      MIMDLLBWDATA(2) => NlwRenamedSig_OI_DEBUG(263),
      MIMDLLBWDATA(1) => NlwRenamedSig_OI_DEBUG(262),
      MIMDLLBWDATA(0) => NlwRenamedSig_OI_DEBUG(261),
      MIMDLLBWADD(11) => NlwRenamedSig_OI_DEBUG(336),
      MIMDLLBWADD(10) => NlwRenamedSig_OI_DEBUG(335),
      MIMDLLBWADD(9) => NlwRenamedSig_OI_DEBUG(334),
      MIMDLLBWADD(8) => NlwRenamedSig_OI_DEBUG(333),
      MIMDLLBWADD(7) => NlwRenamedSig_OI_DEBUG(332),
      MIMDLLBWADD(6) => NlwRenamedSig_OI_DEBUG(331),
      MIMDLLBWADD(5) => NlwRenamedSig_OI_DEBUG(330),
      MIMDLLBWADD(4) => NlwRenamedSig_OI_DEBUG(329),
      MIMDLLBWADD(3) => NlwRenamedSig_OI_DEBUG(328),
      MIMDLLBWADD(2) => NlwRenamedSig_OI_DEBUG(327),
      MIMDLLBWADD(1) => NlwRenamedSig_OI_DEBUG(326),
      MIMDLLBWADD(0) => NlwRenamedSig_OI_DEBUG(325),
      MIMDLLBRADD(11) => NlwRenamedSig_OI_DEBUG(259),
      MIMDLLBRADD(10) => NlwRenamedSig_OI_DEBUG(258),
      MIMDLLBRADD(9) => NlwRenamedSig_OI_DEBUG(257),
      MIMDLLBRADD(8) => NlwRenamedSig_OI_DEBUG(256),
      MIMDLLBRADD(7) => NlwRenamedSig_OI_DEBUG(255),
      MIMDLLBRADD(6) => NlwRenamedSig_OI_DEBUG(254),
      MIMDLLBRADD(5) => NlwRenamedSig_OI_DEBUG(253),
      MIMDLLBRADD(4) => NlwRenamedSig_OI_DEBUG(252),
      MIMDLLBRADD(3) => NlwRenamedSig_OI_DEBUG(251),
      MIMDLLBRADD(2) => NlwRenamedSig_OI_DEBUG(250),
      MIMDLLBRADD(1) => NlwRenamedSig_OI_DEBUG(249),
      MIMDLLBRADD(0) => NlwRenamedSig_OI_DEBUG(248),
      MIMDLLBRDATA(63) => NlwRenamedSig_OI_DEBUG(247),
      MIMDLLBRDATA(62) => NlwRenamedSig_OI_DEBUG(246),
      MIMDLLBRDATA(61) => NlwRenamedSig_OI_DEBUG(245),
      MIMDLLBRDATA(60) => NlwRenamedSig_OI_DEBUG(244),
      MIMDLLBRDATA(59) => NlwRenamedSig_OI_DEBUG(243),
      MIMDLLBRDATA(58) => NlwRenamedSig_OI_DEBUG(242),
      MIMDLLBRDATA(57) => NlwRenamedSig_OI_DEBUG(241),
      MIMDLLBRDATA(56) => NlwRenamedSig_OI_DEBUG(240),
      MIMDLLBRDATA(55) => NlwRenamedSig_OI_DEBUG(239),
      MIMDLLBRDATA(54) => NlwRenamedSig_OI_DEBUG(238),
      MIMDLLBRDATA(53) => NlwRenamedSig_OI_DEBUG(237),
      MIMDLLBRDATA(52) => NlwRenamedSig_OI_DEBUG(236),
      MIMDLLBRDATA(51) => NlwRenamedSig_OI_DEBUG(235),
      MIMDLLBRDATA(50) => NlwRenamedSig_OI_DEBUG(234),
      MIMDLLBRDATA(49) => NlwRenamedSig_OI_DEBUG(233),
      MIMDLLBRDATA(48) => NlwRenamedSig_OI_DEBUG(232),
      MIMDLLBRDATA(47) => NlwRenamedSig_OI_DEBUG(231),
      MIMDLLBRDATA(46) => NlwRenamedSig_OI_DEBUG(230),
      MIMDLLBRDATA(45) => NlwRenamedSig_OI_DEBUG(229),
      MIMDLLBRDATA(44) => NlwRenamedSig_OI_DEBUG(228),
      MIMDLLBRDATA(43) => NlwRenamedSig_OI_DEBUG(227),
      MIMDLLBRDATA(42) => NlwRenamedSig_OI_DEBUG(226),
      MIMDLLBRDATA(41) => NlwRenamedSig_OI_DEBUG(225),
      MIMDLLBRDATA(40) => NlwRenamedSig_OI_DEBUG(224),
      MIMDLLBRDATA(39) => NlwRenamedSig_OI_DEBUG(223),
      MIMDLLBRDATA(38) => NlwRenamedSig_OI_DEBUG(222),
      MIMDLLBRDATA(37) => NlwRenamedSig_OI_DEBUG(221),
      MIMDLLBRDATA(36) => NlwRenamedSig_OI_DEBUG(220),
      MIMDLLBRDATA(35) => NlwRenamedSig_OI_DEBUG(219),
      MIMDLLBRDATA(34) => NlwRenamedSig_OI_DEBUG(218),
      MIMDLLBRDATA(33) => NlwRenamedSig_OI_DEBUG(217),
      MIMDLLBRDATA(32) => NlwRenamedSig_OI_DEBUG(216),
      MIMDLLBRDATA(31) => NlwRenamedSig_OI_DEBUG(215),
      MIMDLLBRDATA(30) => NlwRenamedSig_OI_DEBUG(214),
      MIMDLLBRDATA(29) => NlwRenamedSig_OI_DEBUG(213),
      MIMDLLBRDATA(28) => NlwRenamedSig_OI_DEBUG(212),
      MIMDLLBRDATA(27) => NlwRenamedSig_OI_DEBUG(211),
      MIMDLLBRDATA(26) => NlwRenamedSig_OI_DEBUG(210),
      MIMDLLBRDATA(25) => NlwRenamedSig_OI_DEBUG(209),
      MIMDLLBRDATA(24) => NlwRenamedSig_OI_DEBUG(208),
      MIMDLLBRDATA(23) => NlwRenamedSig_OI_DEBUG(207),
      MIMDLLBRDATA(22) => NlwRenamedSig_OI_DEBUG(206),
      MIMDLLBRDATA(21) => NlwRenamedSig_OI_DEBUG(205),
      MIMDLLBRDATA(20) => NlwRenamedSig_OI_DEBUG(204),
      MIMDLLBRDATA(19) => NlwRenamedSig_OI_DEBUG(203),
      MIMDLLBRDATA(18) => NlwRenamedSig_OI_DEBUG(202),
      MIMDLLBRDATA(17) => NlwRenamedSig_OI_DEBUG(201),
      MIMDLLBRDATA(16) => NlwRenamedSig_OI_DEBUG(200),
      MIMDLLBRDATA(15) => NlwRenamedSig_OI_DEBUG(199),
      MIMDLLBRDATA(14) => NlwRenamedSig_OI_DEBUG(198),
      MIMDLLBRDATA(13) => NlwRenamedSig_OI_DEBUG(197),
      MIMDLLBRDATA(12) => NlwRenamedSig_OI_DEBUG(196),
      MIMDLLBRDATA(11) => NlwRenamedSig_OI_DEBUG(195),
      MIMDLLBRDATA(10) => NlwRenamedSig_OI_DEBUG(194),
      MIMDLLBRDATA(9) => NlwRenamedSig_OI_DEBUG(193),
      MIMDLLBRDATA(8) => NlwRenamedSig_OI_DEBUG(192),
      MIMDLLBRDATA(7) => NlwRenamedSig_OI_DEBUG(191),
      MIMDLLBRDATA(6) => NlwRenamedSig_OI_DEBUG(190),
      MIMDLLBRDATA(5) => NlwRenamedSig_OI_DEBUG(189),
      MIMDLLBRDATA(4) => NlwRenamedSig_OI_DEBUG(188),
      MIMDLLBRDATA(3) => NlwRenamedSig_OI_DEBUG(187),
      MIMDLLBRDATA(2) => NlwRenamedSig_OI_DEBUG(186),
      MIMDLLBRDATA(1) => NlwRenamedSig_OI_DEBUG(185),
      MIMDLLBRDATA(0) => NlwRenamedSig_OI_DEBUG(184),
      LLKTCSTATUS(7) => llk_tc_status(7),
      LLKTCSTATUS(6) => llk_tc_status(6),
      LLKTCSTATUS(5) => llk_tc_status(5),
      LLKTCSTATUS(4) => llk_tc_status(4),
      LLKTCSTATUS(3) => llk_tc_status(3),
      LLKTCSTATUS(2) => llk_tc_status(2),
      LLKTCSTATUS(1) => llk_tc_status(1),
      LLKTCSTATUS(0) => llk_tc_status(0),
      LLKTXDATA(63) => llk_tx_data(63),
      LLKTXDATA(62) => llk_tx_data(62),
      LLKTXDATA(61) => llk_tx_data(61),
      LLKTXDATA(60) => llk_tx_data(60),
      LLKTXDATA(59) => llk_tx_data(59),
      LLKTXDATA(58) => llk_tx_data(58),
      LLKTXDATA(57) => llk_tx_data(57),
      LLKTXDATA(56) => llk_tx_data(56),
      LLKTXDATA(55) => llk_tx_data(55),
      LLKTXDATA(54) => llk_tx_data(54),
      LLKTXDATA(53) => llk_tx_data(53),
      LLKTXDATA(52) => llk_tx_data(52),
      LLKTXDATA(51) => llk_tx_data(51),
      LLKTXDATA(50) => llk_tx_data(50),
      LLKTXDATA(49) => llk_tx_data(49),
      LLKTXDATA(48) => llk_tx_data(48),
      LLKTXDATA(47) => llk_tx_data(47),
      LLKTXDATA(46) => llk_tx_data(46),
      LLKTXDATA(45) => llk_tx_data(45),
      LLKTXDATA(44) => llk_tx_data(44),
      LLKTXDATA(43) => llk_tx_data(43),
      LLKTXDATA(42) => llk_tx_data(42),
      LLKTXDATA(41) => llk_tx_data(41),
      LLKTXDATA(40) => llk_tx_data(40),
      LLKTXDATA(39) => llk_tx_data(39),
      LLKTXDATA(38) => llk_tx_data(38),
      LLKTXDATA(37) => llk_tx_data(37),
      LLKTXDATA(36) => llk_tx_data(36),
      LLKTXDATA(35) => llk_tx_data(35),
      LLKTXDATA(34) => llk_tx_data(34),
      LLKTXDATA(33) => llk_tx_data(33),
      LLKTXDATA(32) => llk_tx_data(32),
      LLKTXDATA(31) => llk_tx_data(31),
      LLKTXDATA(30) => llk_tx_data(30),
      LLKTXDATA(29) => llk_tx_data(29),
      LLKTXDATA(28) => llk_tx_data(28),
      LLKTXDATA(27) => llk_tx_data(27),
      LLKTXDATA(26) => llk_tx_data(26),
      LLKTXDATA(25) => llk_tx_data(25),
      LLKTXDATA(24) => llk_tx_data(24),
      LLKTXDATA(23) => llk_tx_data(23),
      LLKTXDATA(22) => llk_tx_data(22),
      LLKTXDATA(21) => llk_tx_data(21),
      LLKTXDATA(20) => llk_tx_data(20),
      LLKTXDATA(19) => llk_tx_data(19),
      LLKTXDATA(18) => llk_tx_data(18),
      LLKTXDATA(17) => llk_tx_data(17),
      LLKTXDATA(16) => llk_tx_data(16),
      LLKTXDATA(15) => llk_tx_data(15),
      LLKTXDATA(14) => llk_tx_data(14),
      LLKTXDATA(13) => llk_tx_data(13),
      LLKTXDATA(12) => llk_tx_data(12),
      LLKTXDATA(11) => llk_tx_data(11),
      LLKTXDATA(10) => llk_tx_data(10),
      LLKTXDATA(9) => llk_tx_data(9),
      LLKTXDATA(8) => llk_tx_data(8),
      LLKTXDATA(7) => llk_tx_data(7),
      LLKTXDATA(6) => llk_tx_data(6),
      LLKTXDATA(5) => llk_tx_data(5),
      LLKTXDATA(4) => llk_tx_data(4),
      LLKTXDATA(3) => llk_tx_data(3),
      LLKTXDATA(2) => llk_tx_data(2),
      LLKTXDATA(1) => llk_tx_data(1),
      LLKTXDATA(0) => llk_tx_data(0),
      LLKTXCHANSPACE(9) => llk_tx_chan_space(9),
      LLKTXCHANSPACE(8) => llk_tx_chan_space(8),
      LLKTXCHANSPACE(7) => llk_tx_chan_space(7),
      LLKTXCHANSPACE(6) => llk_tx_chan_space(6),
      LLKTXCHANSPACE(5) => llk_tx_chan_space(5),
      LLKTXCHANSPACE(4) => llk_tx_chan_space(4),
      LLKTXCHANSPACE(3) => llk_tx_chan_space(3),
      LLKTXCHANSPACE(2) => llk_tx_chan_space(2),
      LLKTXCHANSPACE(1) => llk_tx_chan_space(1),
      LLKTXCHANSPACE(0) => llk_tx_chan_space(0),
      LLKTXENABLEN(1) => llk_tx_enable_n(1),
      LLKTXENABLEN(0) => llk_tx_enable_n(0),
      LLKTXCHTC(2) => llk_tx_ch_tc(2),
      LLKTXCHTC(1) => llk_tx_ch_tc(1),
      LLKTXCHTC(0) => llk_tx_ch_tc(0),
      LLKTXCHFIFO(1) => llk_tx_ch_fifo(1),
      LLKTXCHFIFO(0) => llk_tx_ch_fifo(0),
      LLKTXCHPOSTEDREADYN(7) => llk_tx_ch_posted_ready_n(7),
      LLKTXCHPOSTEDREADYN(6) => llk_tx_ch_posted_ready_n(6),
      LLKTXCHPOSTEDREADYN(5) => llk_tx_ch_posted_ready_n(5),
      LLKTXCHPOSTEDREADYN(4) => llk_tx_ch_posted_ready_n(4),
      LLKTXCHPOSTEDREADYN(3) => llk_tx_ch_posted_ready_n(3),
      LLKTXCHPOSTEDREADYN(2) => llk_tx_ch_posted_ready_n(2),
      LLKTXCHPOSTEDREADYN(1) => llk_tx_ch_posted_ready_n(1),
      LLKTXCHPOSTEDREADYN(0) => llk_tx_ch_posted_ready_n(0),
      LLKTXCHNONPOSTEDREADYN(7) => llk_tx_ch_non_posted_ready_n(7),
      LLKTXCHNONPOSTEDREADYN(6) => llk_tx_ch_non_posted_ready_n(6),
      LLKTXCHNONPOSTEDREADYN(5) => llk_tx_ch_non_posted_ready_n(5),
      LLKTXCHNONPOSTEDREADYN(4) => llk_tx_ch_non_posted_ready_n(4),
      LLKTXCHNONPOSTEDREADYN(3) => llk_tx_ch_non_posted_ready_n(3),
      LLKTXCHNONPOSTEDREADYN(2) => llk_tx_ch_non_posted_ready_n(2),
      LLKTXCHNONPOSTEDREADYN(1) => llk_tx_ch_non_posted_ready_n(1),
      LLKTXCHNONPOSTEDREADYN(0) => llk_tx_ch_non_posted_ready_n(0),
      LLKTXCHCOMPLETIONREADYN(7) => llk_tx_ch_completion_ready_n(7),
      LLKTXCHCOMPLETIONREADYN(6) => llk_tx_ch_completion_ready_n(6),
      LLKTXCHCOMPLETIONREADYN(5) => llk_tx_ch_completion_ready_n(5),
      LLKTXCHCOMPLETIONREADYN(4) => llk_tx_ch_completion_ready_n(4),
      LLKTXCHCOMPLETIONREADYN(3) => llk_tx_ch_completion_ready_n(3),
      LLKTXCHCOMPLETIONREADYN(2) => llk_tx_ch_completion_ready_n(2),
      LLKTXCHCOMPLETIONREADYN(1) => llk_tx_ch_completion_ready_n(1),
      LLKTXCHCOMPLETIONREADYN(0) => llk_tx_ch_completion_ready_n(0),
      LLKRXDATA(63) => llk_rx_data(63),
      LLKRXDATA(62) => llk_rx_data(62),
      LLKRXDATA(61) => llk_rx_data(61),
      LLKRXDATA(60) => llk_rx_data(60),
      LLKRXDATA(59) => llk_rx_data(59),
      LLKRXDATA(58) => llk_rx_data(58),
      LLKRXDATA(57) => llk_rx_data(57),
      LLKRXDATA(56) => llk_rx_data(56),
      LLKRXDATA(55) => llk_rx_data(55),
      LLKRXDATA(54) => llk_rx_data(54),
      LLKRXDATA(53) => llk_rx_data(53),
      LLKRXDATA(52) => llk_rx_data(52),
      LLKRXDATA(51) => llk_rx_data(51),
      LLKRXDATA(50) => llk_rx_data(50),
      LLKRXDATA(49) => llk_rx_data(49),
      LLKRXDATA(48) => llk_rx_data(48),
      LLKRXDATA(47) => llk_rx_data(47),
      LLKRXDATA(46) => llk_rx_data(46),
      LLKRXDATA(45) => llk_rx_data(45),
      LLKRXDATA(44) => llk_rx_data(44),
      LLKRXDATA(43) => llk_rx_data(43),
      LLKRXDATA(42) => llk_rx_data(42),
      LLKRXDATA(41) => llk_rx_data(41),
      LLKRXDATA(40) => llk_rx_data(40),
      LLKRXDATA(39) => llk_rx_data(39),
      LLKRXDATA(38) => llk_rx_data(38),
      LLKRXDATA(37) => llk_rx_data(37),
      LLKRXDATA(36) => llk_rx_data(36),
      LLKRXDATA(35) => llk_rx_data(35),
      LLKRXDATA(34) => llk_rx_data(34),
      LLKRXDATA(33) => llk_rx_data(33),
      LLKRXDATA(32) => llk_rx_data(32),
      LLKRXDATA(31) => llk_rx_data(31),
      LLKRXDATA(30) => llk_rx_data(30),
      LLKRXDATA(29) => llk_rx_data(29),
      LLKRXDATA(28) => llk_rx_data(28),
      LLKRXDATA(27) => llk_rx_data(27),
      LLKRXDATA(26) => llk_rx_data(26),
      LLKRXDATA(25) => llk_rx_data(25),
      LLKRXDATA(24) => llk_rx_data(24),
      LLKRXDATA(23) => llk_rx_data(23),
      LLKRXDATA(22) => llk_rx_data(22),
      LLKRXDATA(21) => llk_rx_data(21),
      LLKRXDATA(20) => llk_rx_data(20),
      LLKRXDATA(19) => llk_rx_data(19),
      LLKRXDATA(18) => llk_rx_data(18),
      LLKRXDATA(17) => llk_rx_data(17),
      LLKRXDATA(16) => llk_rx_data(16),
      LLKRXDATA(15) => llk_rx_data(15),
      LLKRXDATA(14) => llk_rx_data(14),
      LLKRXDATA(13) => llk_rx_data(13),
      LLKRXDATA(12) => llk_rx_data(12),
      LLKRXDATA(11) => llk_rx_data(11),
      LLKRXDATA(10) => llk_rx_data(10),
      LLKRXDATA(9) => llk_rx_data(9),
      LLKRXDATA(8) => llk_rx_data(8),
      LLKRXDATA(7) => llk_rx_data(7),
      LLKRXDATA(6) => llk_rx_data(6),
      LLKRXDATA(5) => llk_rx_data(5),
      LLKRXDATA(4) => llk_rx_data(4),
      LLKRXDATA(3) => llk_rx_data(3),
      LLKRXDATA(2) => llk_rx_data(2),
      LLKRXDATA(1) => llk_rx_data(1),
      LLKRXDATA(0) => llk_rx_data(0),
      LLKRXVALIDN(1) => llk_rx_valid_n(1),
      LLKRXVALIDN(0) => llk_rx_valid_n(0),
      LLKRXPREFERREDTYPE(15) => llk_rx_preferred_type(15),
      LLKRXPREFERREDTYPE(14) => llk_rx_preferred_type(14),
      LLKRXPREFERREDTYPE(13) => llk_rx_preferred_type(13),
      LLKRXPREFERREDTYPE(12) => llk_rx_preferred_type(12),
      LLKRXPREFERREDTYPE(11) => llk_rx_preferred_type(11),
      LLKRXPREFERREDTYPE(10) => llk_rx_preferred_type(10),
      LLKRXPREFERREDTYPE(9) => llk_rx_preferred_type(9),
      LLKRXPREFERREDTYPE(8) => llk_rx_preferred_type(8),
      LLKRXPREFERREDTYPE(7) => llk_rx_preferred_type(7),
      LLKRXPREFERREDTYPE(6) => llk_rx_preferred_type(6),
      LLKRXPREFERREDTYPE(5) => llk_rx_preferred_type(5),
      LLKRXPREFERREDTYPE(4) => llk_rx_preferred_type(4),
      LLKRXPREFERREDTYPE(3) => llk_rx_preferred_type(3),
      LLKRXPREFERREDTYPE(2) => llk_rx_preferred_type(2),
      LLKRXPREFERREDTYPE(1) => llk_rx_preferred_type(1),
      LLKRXPREFERREDTYPE(0) => llk_rx_preferred_type(0),
      LLKRXCHTC(2) => llk_rx_ch_tc(2),
      LLKRXCHTC(1) => llk_rx_ch_tc(1),
      LLKRXCHTC(0) => llk_rx_ch_tc(0),
      LLKRXCHFIFO(1) => llk_rx_ch_fifo(1),
      LLKRXCHFIFO(0) => llk_rx_ch_fifo(0),
      LLKRXCHPOSTEDAVAILABLEN(7) => llk_rx_ch_posted_available_n(7),
      LLKRXCHPOSTEDAVAILABLEN(6) => llk_rx_ch_posted_available_n(6),
      LLKRXCHPOSTEDAVAILABLEN(5) => llk_rx_ch_posted_available_n(5),
      LLKRXCHPOSTEDAVAILABLEN(4) => llk_rx_ch_posted_available_n(4),
      LLKRXCHPOSTEDAVAILABLEN(3) => llk_rx_ch_posted_available_n(3),
      LLKRXCHPOSTEDAVAILABLEN(2) => llk_rx_ch_posted_available_n(2),
      LLKRXCHPOSTEDAVAILABLEN(1) => llk_rx_ch_posted_available_n(1),
      LLKRXCHPOSTEDAVAILABLEN(0) => llk_rx_ch_posted_available_n(0),
      LLKRXCHNONPOSTEDAVAILABLEN(7) => llk_rx_ch_non_posted_available_n(7),
      LLKRXCHNONPOSTEDAVAILABLEN(6) => llk_rx_ch_non_posted_available_n(6),
      LLKRXCHNONPOSTEDAVAILABLEN(5) => llk_rx_ch_non_posted_available_n(5),
      LLKRXCHNONPOSTEDAVAILABLEN(4) => llk_rx_ch_non_posted_available_n(4),
      LLKRXCHNONPOSTEDAVAILABLEN(3) => llk_rx_ch_non_posted_available_n(3),
      LLKRXCHNONPOSTEDAVAILABLEN(2) => llk_rx_ch_non_posted_available_n(2),
      LLKRXCHNONPOSTEDAVAILABLEN(1) => llk_rx_ch_non_posted_available_n(1),
      LLKRXCHNONPOSTEDAVAILABLEN(0) => llk_rx_ch_non_posted_available_n(0),
      LLKRXCHCOMPLETIONAVAILABLEN(7) => llk_rx_ch_completion_available_n(7),
      LLKRXCHCOMPLETIONAVAILABLEN(6) => llk_rx_ch_completion_available_n(6),
      LLKRXCHCOMPLETIONAVAILABLEN(5) => llk_rx_ch_completion_available_n(5),
      LLKRXCHCOMPLETIONAVAILABLEN(4) => llk_rx_ch_completion_available_n(4),
      LLKRXCHCOMPLETIONAVAILABLEN(3) => llk_rx_ch_completion_available_n(3),
      LLKRXCHCOMPLETIONAVAILABLEN(2) => llk_rx_ch_completion_available_n(2),
      LLKRXCHCOMPLETIONAVAILABLEN(1) => llk_rx_ch_completion_available_n(1),
      LLKRXCHCOMPLETIONAVAILABLEN(0) => llk_rx_ch_completion_available_n(0),
      LLKRXCHPOSTEDPARTIALN(7) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_7_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(6) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_6_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(5) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_5_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(4) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_4_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(3) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_3_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(2) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_2_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(1) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_1_UNCONNECTED,
      LLKRXCHPOSTEDPARTIALN(0) => NLW_pcie_ep_LLKRXCHPOSTEDPARTIALN_0_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(7) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_7_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(6) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_6_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(5) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_5_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(4) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_4_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(3) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_3_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(2) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_2_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(1) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_1_UNCONNECTED,
      LLKRXCHNONPOSTEDPARTIALN(0) => NLW_pcie_ep_LLKRXCHNONPOSTEDPARTIALN_0_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(7) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_7_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(6) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_6_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(5) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_5_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(4) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_4_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(3) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_3_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(2) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_2_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(1) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_1_UNCONNECTED,
      LLKRXCHCOMPLETIONPARTIALN(0) => NLW_pcie_ep_LLKRXCHCOMPLETIONPARTIALN_0_UNCONNECTED,
      MGMTRDATA(31) => mgmt_rdata(31),
      MGMTRDATA(30) => mgmt_rdata(30),
      MGMTRDATA(29) => mgmt_rdata(29),
      MGMTRDATA(28) => mgmt_rdata(28),
      MGMTRDATA(27) => mgmt_rdata(27),
      MGMTRDATA(26) => mgmt_rdata(26),
      MGMTRDATA(25) => mgmt_rdata(25),
      MGMTRDATA(24) => mgmt_rdata(24),
      MGMTRDATA(23) => mgmt_rdata(23),
      MGMTRDATA(22) => mgmt_rdata(22),
      MGMTRDATA(21) => mgmt_rdata(21),
      MGMTRDATA(20) => mgmt_rdata(20),
      MGMTRDATA(19) => mgmt_rdata(19),
      MGMTRDATA(18) => mgmt_rdata(18),
      MGMTRDATA(17) => mgmt_rdata(17),
      MGMTRDATA(16) => mgmt_rdata(16),
      MGMTRDATA(15) => mgmt_rdata(15),
      MGMTRDATA(14) => mgmt_rdata(14),
      MGMTRDATA(13) => mgmt_rdata(13),
      MGMTRDATA(12) => mgmt_rdata(12),
      MGMTRDATA(11) => mgmt_rdata(11),
      MGMTRDATA(10) => mgmt_rdata(10),
      MGMTRDATA(9) => mgmt_rdata(9),
      MGMTRDATA(8) => mgmt_rdata(8),
      MGMTRDATA(7) => mgmt_rdata(7),
      MGMTRDATA(6) => mgmt_rdata(6),
      MGMTRDATA(5) => mgmt_rdata(5),
      MGMTRDATA(4) => mgmt_rdata(4),
      MGMTRDATA(3) => mgmt_rdata(3),
      MGMTRDATA(2) => mgmt_rdata(2),
      MGMTRDATA(1) => mgmt_rdata(1),
      MGMTRDATA(0) => mgmt_rdata(0),
      MGMTWDATA(31) => mgmt_wdata(31),
      MGMTWDATA(30) => mgmt_wdata(30),
      MGMTWDATA(29) => mgmt_wdata(29),
      MGMTWDATA(28) => mgmt_wdata(28),
      MGMTWDATA(27) => mgmt_wdata(27),
      MGMTWDATA(26) => mgmt_wdata(26),
      MGMTWDATA(25) => mgmt_wdata(25),
      MGMTWDATA(24) => mgmt_wdata(24),
      MGMTWDATA(23) => mgmt_wdata(23),
      MGMTWDATA(22) => mgmt_wdata(22),
      MGMTWDATA(21) => mgmt_wdata(21),
      MGMTWDATA(20) => mgmt_wdata(20),
      MGMTWDATA(19) => mgmt_wdata(19),
      MGMTWDATA(18) => mgmt_wdata(18),
      MGMTWDATA(17) => mgmt_wdata(17),
      MGMTWDATA(16) => mgmt_wdata(16),
      MGMTWDATA(15) => mgmt_wdata(15),
      MGMTWDATA(14) => mgmt_wdata(14),
      MGMTWDATA(13) => mgmt_wdata(13),
      MGMTWDATA(12) => mgmt_wdata(12),
      MGMTWDATA(11) => mgmt_wdata(11),
      MGMTWDATA(10) => mgmt_wdata(10),
      MGMTWDATA(9) => mgmt_wdata(9),
      MGMTWDATA(8) => mgmt_wdata(8),
      MGMTWDATA(7) => mgmt_wdata(7),
      MGMTWDATA(6) => mgmt_wdata(6),
      MGMTWDATA(5) => mgmt_wdata(5),
      MGMTWDATA(4) => mgmt_wdata(4),
      MGMTWDATA(3) => mgmt_wdata(3),
      MGMTWDATA(2) => mgmt_wdata(2),
      MGMTWDATA(1) => mgmt_wdata(1),
      MGMTWDATA(0) => mgmt_wdata(0),
      MGMTBWREN(3) => mgmt_bwren(3),
      MGMTBWREN(2) => mgmt_bwren(2),
      MGMTBWREN(1) => mgmt_bwren(1),
      MGMTBWREN(0) => mgmt_bwren(0),
      MGMTADDR(10) => mgmt_addr(10),
      MGMTADDR(9) => mgmt_addr(9),
      MGMTADDR(8) => mgmt_addr(8),
      MGMTADDR(7) => mgmt_addr(7),
      MGMTADDR(6) => mgmt_addr(6),
      MGMTADDR(5) => mgmt_addr(5),
      MGMTADDR(4) => mgmt_addr(4),
      MGMTADDR(3) => mgmt_addr(3),
      MGMTADDR(2) => mgmt_addr(2),
      MGMTADDR(1) => mgmt_addr(1),
      MGMTADDR(0) => mgmt_addr(0),
      MGMTPSO(16) => mgmt_pso(16),
      MGMTPSO(15) => mgmt_pso(15),
      MGMTPSO(14) => mgmt_pso(14),
      MGMTPSO(13) => mgmt_pso(13),
      MGMTPSO(12) => mgmt_pso(12),
      MGMTPSO(11) => mgmt_pso(11),
      MGMTPSO(10) => mgmt_pso(10),
      MGMTPSO(9) => mgmt_pso(9),
      MGMTPSO(8) => mgmt_pso(8),
      MGMTPSO(7) => mgmt_pso(7),
      MGMTPSO(6) => mgmt_pso(6),
      MGMTPSO(5) => mgmt_pso(5),
      MGMTPSO(4) => mgmt_pso(4),
      MGMTPSO(3) => mgmt_pso(3),
      MGMTPSO(2) => mgmt_pso(2),
      MGMTPSO(1) => mgmt_pso(1),
      MGMTPSO(0) => mgmt_pso(0),
      MGMTSTATSCREDIT(11) => mgmt_stats_credit(11),
      MGMTSTATSCREDIT(10) => mgmt_stats_credit(10),
      MGMTSTATSCREDIT(9) => mgmt_stats_credit(9),
      MGMTSTATSCREDIT(8) => mgmt_stats_credit(8),
      MGMTSTATSCREDIT(7) => mgmt_stats_credit(7),
      MGMTSTATSCREDIT(6) => mgmt_stats_credit(6),
      MGMTSTATSCREDIT(5) => mgmt_stats_credit(5),
      MGMTSTATSCREDIT(4) => mgmt_stats_credit(4),
      MGMTSTATSCREDIT(3) => mgmt_stats_credit(3),
      MGMTSTATSCREDIT(2) => mgmt_stats_credit(2),
      MGMTSTATSCREDIT(1) => mgmt_stats_credit(1),
      MGMTSTATSCREDIT(0) => mgmt_stats_credit(0),
      MGMTSTATSCREDITSEL(6) => mgmt_stats_credit_sel(6),
      MGMTSTATSCREDITSEL(5) => mgmt_stats_credit_sel(5),
      MGMTSTATSCREDITSEL(4) => mgmt_stats_credit_sel(4),
      MGMTSTATSCREDITSEL(3) => mgmt_stats_credit_sel(3),
      MGMTSTATSCREDITSEL(2) => mgmt_stats_credit_sel(2),
      MGMTSTATSCREDITSEL(1) => mgmt_stats_credit_sel(1),
      MGMTSTATSCREDITSEL(0) => mgmt_stats_credit_sel(0),
      CFGNEGOTIATEDLINKWIDTH(5) => NlwRenamedSig_OI_DEBUG(338),
      CFGNEGOTIATEDLINKWIDTH(4) => NlwRenamedSig_OI_DEBUG(338),
      CFGNEGOTIATEDLINKWIDTH(3) => NlwRenamedSig_OI_DEBUG(338),
      CFGNEGOTIATEDLINKWIDTH(2) => NlwRenamedSig_OI_DEBUG(338),
      CFGNEGOTIATEDLINKWIDTH(1) => NlwRenamedSig_OI_DEBUG(338),
      CFGNEGOTIATEDLINKWIDTH(0) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(23) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(22) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(21) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(20) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(19) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(18) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(17) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(16) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(15) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(14) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(13) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(12) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(11) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(10) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(9) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(8) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(7) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(6) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(5) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(4) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(3) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(2) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(1) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCID(0) => NlwRenamedSig_OI_DEBUG(338),
      L0RXMACLINKERROR(1) => l0_rx_mac_link_error(1),
      L0RXMACLINKERROR(0) => l0_rx_mac_link_error(0),
      L0MACNEGOTIATEDLINKWIDTH(3) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(3),
      L0MACNEGOTIATEDLINKWIDTH(2) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(2),
      L0MACNEGOTIATEDLINKWIDTH(1) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(1),
      L0MACNEGOTIATEDLINKWIDTH(0) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(0),
      L0LTSSMSTATE(3) => NlwRenamedSig_OI_l0_ltssm_state(3),
      L0LTSSMSTATE(2) => NlwRenamedSig_OI_l0_ltssm_state(2),
      L0LTSSMSTATE(1) => NlwRenamedSig_OI_l0_ltssm_state(1),
      L0LTSSMSTATE(0) => NlwRenamedSig_OI_l0_ltssm_state(0),
      L0REPLAYTIMERADJUSTMENT(11) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(10) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(9) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(8) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(7) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(6) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(5) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(4) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(3) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(2) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(1) => NlwRenamedSig_OI_DEBUG(338),
      L0REPLAYTIMERADJUSTMENT(0) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(11) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(10) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(9) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(8) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(7) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(6) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(5) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(4) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(3) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(2) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(1) => NlwRenamedSig_OI_DEBUG(338),
      L0ACKNAKTIMERADJUSTMENT(0) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGASSTATECHANGECMD(3) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGASSTATECHANGECMD(2) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGASSTATECHANGECMD(1) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGASSTATECHANGECMD(0) => NlwRenamedSig_OI_DEBUG(338),
      L0ASTURNPOOLBITSCONSUMED(2) => NlwRenamedSig_OI_DEBUG(338),
      L0ASTURNPOOLBITSCONSUMED(1) => NlwRenamedSig_OI_DEBUG(338),
      L0ASTURNPOOLBITSCONSUMED(0) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(7) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(6) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(5) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(4) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(3) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(2) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(1) => NlwRenamedSig_OI_DEBUG(338),
      L0ASPORTCOUNT(0) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(7) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(6) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(5) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(4) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(3) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(2) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGVCENABLE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0DLLVCSTATUS(7) => NLW_pcie_ep_L0DLLVCSTATUS_7_UNCONNECTED,
      L0DLLVCSTATUS(6) => NLW_pcie_ep_L0DLLVCSTATUS_6_UNCONNECTED,
      L0DLLVCSTATUS(5) => NLW_pcie_ep_L0DLLVCSTATUS_5_UNCONNECTED,
      L0DLLVCSTATUS(4) => NLW_pcie_ep_L0DLLVCSTATUS_4_UNCONNECTED,
      L0DLLVCSTATUS(3) => NLW_pcie_ep_L0DLLVCSTATUS_3_UNCONNECTED,
      L0DLLVCSTATUS(2) => NLW_pcie_ep_L0DLLVCSTATUS_2_UNCONNECTED,
      L0DLLVCSTATUS(1) => NLW_pcie_ep_L0DLLVCSTATUS_1_UNCONNECTED,
      L0DLLVCSTATUS(0) => NLW_pcie_ep_L0DLLVCSTATUS_0_UNCONNECTED,
      L0DLUPDOWN(7) => l0_dl_up_down(7),
      L0DLUPDOWN(6) => l0_dl_up_down(6),
      L0DLUPDOWN(5) => l0_dl_up_down(5),
      L0DLUPDOWN(4) => l0_dl_up_down(4),
      L0DLUPDOWN(3) => l0_dl_up_down(3),
      L0DLUPDOWN(2) => l0_dl_up_down(2),
      L0DLUPDOWN(1) => l0_dl_up_down(1),
      L0DLUPDOWN(0) => NlwRenamedSig_OI_l0_dl_up_down(0),
      L0CFGNEGOTIATEDMAXP(2) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGNEGOTIATEDMAXP(1) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGNEGOTIATEDMAXP(0) => NlwRenamedSig_OI_DEBUG(338),
      L0DLLERRORVECTOR(6) => l0_dll_error_vector(6),
      L0DLLERRORVECTOR(5) => l0_dll_error_vector(5),
      L0DLLERRORVECTOR(4) => l0_dll_error_vector(4),
      L0DLLERRORVECTOR(3) => l0_dll_error_vector(3),
      L0DLLERRORVECTOR(2) => l0_dll_error_vector(2),
      L0DLLERRORVECTOR(1) => l0_dll_error_vector(1),
      L0DLLERRORVECTOR(0) => l0_dll_error_vector(0),
      L0DLLASRXSTATE(1) => NLW_pcie_ep_L0DLLASRXSTATE_1_UNCONNECTED,
      L0DLLASRXSTATE(0) => NLW_pcie_ep_L0DLLASRXSTATE_0_UNCONNECTED,
      L0COMPLETERID(12) => l0_completer_id(12),
      L0COMPLETERID(11) => l0_completer_id(11),
      L0COMPLETERID(10) => l0_completer_id(10),
      L0COMPLETERID(9) => l0_completer_id(9),
      L0COMPLETERID(8) => l0_completer_id(8),
      L0COMPLETERID(7) => l0_completer_id(7),
      L0COMPLETERID(6) => l0_completer_id(6),
      L0COMPLETERID(5) => l0_completer_id(5),
      L0COMPLETERID(4) => l0_completer_id(4),
      L0COMPLETERID(3) => l0_completer_id(3),
      L0COMPLETERID(2) => l0_completer_id(2),
      L0COMPLETERID(1) => l0_completer_id(1),
      L0COMPLETERID(0) => l0_completer_id(0),
      L0PORTNUMBER(7) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(6) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(5) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(4) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(3) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(2) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(1) => NlwRenamedSig_OI_DEBUG(338),
      L0PORTNUMBER(0) => NlwRenamedSig_OI_DEBUG(338),
      L0ERRMSGREQID(15) => NLW_pcie_ep_L0ERRMSGREQID_15_UNCONNECTED,
      L0ERRMSGREQID(14) => NLW_pcie_ep_L0ERRMSGREQID_14_UNCONNECTED,
      L0ERRMSGREQID(13) => NLW_pcie_ep_L0ERRMSGREQID_13_UNCONNECTED,
      L0ERRMSGREQID(12) => NLW_pcie_ep_L0ERRMSGREQID_12_UNCONNECTED,
      L0ERRMSGREQID(11) => NLW_pcie_ep_L0ERRMSGREQID_11_UNCONNECTED,
      L0ERRMSGREQID(10) => NLW_pcie_ep_L0ERRMSGREQID_10_UNCONNECTED,
      L0ERRMSGREQID(9) => NLW_pcie_ep_L0ERRMSGREQID_9_UNCONNECTED,
      L0ERRMSGREQID(8) => NLW_pcie_ep_L0ERRMSGREQID_8_UNCONNECTED,
      L0ERRMSGREQID(7) => NLW_pcie_ep_L0ERRMSGREQID_7_UNCONNECTED,
      L0ERRMSGREQID(6) => NLW_pcie_ep_L0ERRMSGREQID_6_UNCONNECTED,
      L0ERRMSGREQID(5) => NLW_pcie_ep_L0ERRMSGREQID_5_UNCONNECTED,
      L0ERRMSGREQID(4) => NLW_pcie_ep_L0ERRMSGREQID_4_UNCONNECTED,
      L0ERRMSGREQID(3) => NLW_pcie_ep_L0ERRMSGREQID_3_UNCONNECTED,
      L0ERRMSGREQID(2) => NLW_pcie_ep_L0ERRMSGREQID_2_UNCONNECTED,
      L0ERRMSGREQID(1) => NLW_pcie_ep_L0ERRMSGREQID_1_UNCONNECTED,
      L0ERRMSGREQID(0) => NLW_pcie_ep_L0ERRMSGREQID_0_UNCONNECTED,
      L0PACKETHEADERFROMUSER(127) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(126) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(125) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(124) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(123) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(122) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(121) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(120) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(119) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(118) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(117) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(116) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(115) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(114) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(113) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(112) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(111) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(110) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(109) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(108) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(107) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(106) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(105) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(104) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(103) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(102) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(101) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(100) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(99) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(98) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(97) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(96) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(95) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(94) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(93) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(92) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(91) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(90) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(89) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(88) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(87) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(86) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(85) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(84) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(83) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(82) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(81) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(80) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(79) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(78) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(77) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(76) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(75) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(74) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(73) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(72) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(71) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(70) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(69) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(68) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(67) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(66) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(65) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(64) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(63) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(62) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(61) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(60) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(59) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(58) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(57) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(56) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(55) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(54) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(53) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(52) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(51) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(50) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(49) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(48) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(47) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(46) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(45) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(44) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(43) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(42) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(41) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(40) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(39) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(38) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(37) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(36) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(35) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(34) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(33) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(32) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(31) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(30) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(29) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(28) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(27) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(26) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(25) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(24) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(23) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(22) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(21) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(20) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(19) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(18) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(17) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(16) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(15) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(14) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(13) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(12) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(11) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(10) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(9) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(8) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(7) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(6) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(5) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(4) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(3) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(2) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(1) => NlwRenamedSig_OI_DEBUG(338),
      L0PACKETHEADERFROMUSER(0) => NlwRenamedSig_OI_DEBUG(338),
      L0MSIREQUEST0(3) => l0_msi_request0(3),
      L0MSIREQUEST0(2) => l0_msi_request0(2),
      L0MSIREQUEST0(1) => l0_msi_request0(1),
      L0MSIREQUEST0(0) => l0_msi_request0(0),
      L0MULTIMSGEN0(2) => l0_multi_msg_en0(2),
      L0MULTIMSGEN0(1) => l0_multi_msg_en0(1),
      L0MULTIMSGEN0(0) => l0_multi_msg_en0(0),
      MAXPAYLOADSIZE(2) => max_payload_size(2),
      MAXPAYLOADSIZE(1) => max_payload_size(1),
      MAXPAYLOADSIZE(0) => max_payload_size(0),
      MAXREADREQUESTSIZE(2) => max_read_request_size(2),
      MAXREADREQUESTSIZE(1) => max_read_request_size(1),
      MAXREADREQUESTSIZE(0) => max_read_request_size(0),
      L0ATTENTIONINDICATORCONTROL(1) => NLW_pcie_ep_L0ATTENTIONINDICATORCONTROL_1_UNCONNECTED,
      L0ATTENTIONINDICATORCONTROL(0) => NLW_pcie_ep_L0ATTENTIONINDICATORCONTROL_0_UNCONNECTED,
      L0POWERINDICATORCONTROL(1) => NLW_pcie_ep_L0POWERINDICATORCONTROL_1_UNCONNECTED,
      L0POWERINDICATORCONTROL(0) => NLW_pcie_ep_L0POWERINDICATORCONTROL_0_UNCONNECTED,
      L0PWRSTATE0(1) => l0_pwr_state0(1),
      L0PWRSTATE0(0) => l0_pwr_state0(0),
      L0RXDLLPMTYPE(2) => NLW_pcie_ep_L0RXDLLPMTYPE_2_UNCONNECTED,
      L0RXDLLPMTYPE(1) => NLW_pcie_ep_L0RXDLLPMTYPE_1_UNCONNECTED,
      L0RXDLLPMTYPE(0) => NLW_pcie_ep_L0RXDLLPMTYPE_0_UNCONNECTED,
      L0TXCFGPMTYPE(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXCFGPMTYPE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXCFGPMTYPE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0PWRNEXTLINKSTATE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0PWRNEXTLINKSTATE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGL0SEXITLAT(2) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGL0SEXITLAT(1) => NlwRenamedSig_OI_DEBUG(338),
      L0CFGL0SEXITLAT(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(63) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(62) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(61) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(60) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(59) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(58) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(57) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(56) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(55) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(54) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(53) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(52) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(51) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(50) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(49) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(48) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(47) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(46) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(45) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(44) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(43) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(42) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(41) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(40) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(39) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(38) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(37) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(36) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(35) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(34) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(33) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(32) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(31) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(30) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(29) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(28) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(27) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(26) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(25) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(24) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(23) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(22) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(21) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(20) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(19) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(18) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(17) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(16) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPDATA(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPEND(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPEND(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPENABLE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPENABLE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPLATENCY(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPLATENCY(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPLATENCY(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLTLPLATENCY(0) => NlwRenamedSig_OI_DEBUG(338),
      L0RXDLLTLPEND(1) => NLW_pcie_ep_L0RXDLLTLPEND_1_UNCONNECTED,
      L0RXDLLTLPEND(0) => NLW_pcie_ep_L0RXDLLTLPEND_0_UNCONNECTED,
      L0TXTLSBFCDATA(18) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(17) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(16) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLSBFCDATA(0) => NlwRenamedSig_OI_DEBUG(338),
      L0RXDLLSBFCDATA(18) => NLW_pcie_ep_L0RXDLLSBFCDATA_18_UNCONNECTED,
      L0RXDLLSBFCDATA(17) => NLW_pcie_ep_L0RXDLLSBFCDATA_17_UNCONNECTED,
      L0RXDLLSBFCDATA(16) => NLW_pcie_ep_L0RXDLLSBFCDATA_16_UNCONNECTED,
      L0RXDLLSBFCDATA(15) => NLW_pcie_ep_L0RXDLLSBFCDATA_15_UNCONNECTED,
      L0RXDLLSBFCDATA(14) => NLW_pcie_ep_L0RXDLLSBFCDATA_14_UNCONNECTED,
      L0RXDLLSBFCDATA(13) => NLW_pcie_ep_L0RXDLLSBFCDATA_13_UNCONNECTED,
      L0RXDLLSBFCDATA(12) => NLW_pcie_ep_L0RXDLLSBFCDATA_12_UNCONNECTED,
      L0RXDLLSBFCDATA(11) => NLW_pcie_ep_L0RXDLLSBFCDATA_11_UNCONNECTED,
      L0RXDLLSBFCDATA(10) => NLW_pcie_ep_L0RXDLLSBFCDATA_10_UNCONNECTED,
      L0RXDLLSBFCDATA(9) => NLW_pcie_ep_L0RXDLLSBFCDATA_9_UNCONNECTED,
      L0RXDLLSBFCDATA(8) => NLW_pcie_ep_L0RXDLLSBFCDATA_8_UNCONNECTED,
      L0RXDLLSBFCDATA(7) => NLW_pcie_ep_L0RXDLLSBFCDATA_7_UNCONNECTED,
      L0RXDLLSBFCDATA(6) => NLW_pcie_ep_L0RXDLLSBFCDATA_6_UNCONNECTED,
      L0RXDLLSBFCDATA(5) => NLW_pcie_ep_L0RXDLLSBFCDATA_5_UNCONNECTED,
      L0RXDLLSBFCDATA(4) => NLW_pcie_ep_L0RXDLLSBFCDATA_4_UNCONNECTED,
      L0RXDLLSBFCDATA(3) => NLW_pcie_ep_L0RXDLLSBFCDATA_3_UNCONNECTED,
      L0RXDLLSBFCDATA(2) => NLW_pcie_ep_L0RXDLLSBFCDATA_2_UNCONNECTED,
      L0RXDLLSBFCDATA(1) => NLW_pcie_ep_L0RXDLLSBFCDATA_1_UNCONNECTED,
      L0RXDLLSBFCDATA(0) => NLW_pcie_ep_L0RXDLLSBFCDATA_0_UNCONNECTED,
      L0TXTLFCNPOSTBYPCRED(191) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(190) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(189) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(188) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(187) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(186) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(185) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(184) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(183) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(182) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(181) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(180) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(179) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(178) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(177) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(176) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(175) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(174) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(173) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(172) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(171) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(170) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(169) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(168) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(167) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(166) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(165) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(164) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(163) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(162) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(161) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(160) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(159) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(158) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(157) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(156) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(155) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(154) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(153) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(152) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(151) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(150) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(149) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(148) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(147) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(146) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(145) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(144) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(143) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(142) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(141) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(140) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(139) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(138) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(137) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(136) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(135) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(134) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(133) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(132) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(131) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(130) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(129) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(128) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(127) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(126) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(125) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(124) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(123) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(122) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(121) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(120) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(119) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(118) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(117) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(116) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(115) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(114) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(113) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(112) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(111) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(110) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(109) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(108) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(107) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(106) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(105) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(104) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(103) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(102) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(101) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(100) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(99) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(98) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(97) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(96) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(95) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(94) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(93) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(92) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(91) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(90) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(89) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(88) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(87) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(86) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(85) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(84) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(83) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(82) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(81) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(80) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(79) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(78) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(77) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(76) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(75) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(74) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(73) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(72) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(71) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(70) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(69) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(68) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(67) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(66) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(65) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(64) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(63) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(62) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(61) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(60) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(59) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(58) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(57) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(56) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(55) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(54) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(53) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(52) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(51) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(50) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(49) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(48) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(47) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(46) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(45) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(44) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(43) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(42) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(41) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(40) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(39) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(38) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(37) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(36) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(35) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(34) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(33) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(32) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(31) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(30) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(29) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(28) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(27) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(26) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(25) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(24) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(23) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(22) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(21) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(20) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(19) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(18) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(17) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(16) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPCRED(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCNPOSTBYPUPDATE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXDLLFCNPOSTBYPUPDATED(7) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_7_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(6) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_6_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(5) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_5_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(4) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_4_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(3) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_3_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(2) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_2_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(1) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_1_UNCONNECTED,
      L0TXDLLFCNPOSTBYPUPDATED(0) => NLW_pcie_ep_L0TXDLLFCNPOSTBYPUPDATED_0_UNCONNECTED,
      L0TXTLFCPOSTORDCRED(159) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(158) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(157) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(156) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(155) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(154) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(153) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(152) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(151) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(150) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(149) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(148) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(147) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(146) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(145) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(144) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(143) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(142) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(141) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(140) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(139) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(138) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(137) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(136) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(135) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(134) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(133) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(132) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(131) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(130) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(129) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(128) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(127) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(126) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(125) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(124) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(123) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(122) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(121) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(120) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(119) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(118) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(117) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(116) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(115) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(114) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(113) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(112) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(111) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(110) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(109) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(108) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(107) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(106) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(105) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(104) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(103) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(102) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(101) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(100) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(99) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(98) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(97) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(96) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(95) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(94) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(93) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(92) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(91) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(90) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(89) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(88) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(87) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(86) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(85) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(84) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(83) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(82) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(81) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(80) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(79) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(78) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(77) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(76) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(75) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(74) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(73) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(72) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(71) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(70) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(69) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(68) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(67) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(66) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(65) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(64) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(63) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(62) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(61) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(60) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(59) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(58) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(57) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(56) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(55) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(54) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(53) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(52) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(51) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(50) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(49) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(48) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(47) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(46) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(45) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(44) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(43) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(42) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(41) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(40) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(39) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(38) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(37) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(36) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(35) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(34) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(33) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(32) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(31) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(30) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(29) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(28) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(27) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(26) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(25) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(24) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(23) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(22) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(21) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(20) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(19) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(18) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(17) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(16) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDCRED(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCPOSTORDUPDATE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXDLLFCPOSTORDUPDATED(7) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_7_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(6) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_6_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(5) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_5_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(4) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_4_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(3) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_3_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(2) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_2_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(1) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_1_UNCONNECTED,
      L0TXDLLFCPOSTORDUPDATED(0) => NLW_pcie_ep_L0TXDLLFCPOSTORDUPDATED_0_UNCONNECTED,
      L0TXTLFCCMPLMCCRED(159) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(158) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(157) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(156) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(155) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(154) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(153) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(152) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(151) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(150) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(149) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(148) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(147) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(146) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(145) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(144) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(143) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(142) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(141) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(140) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(139) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(138) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(137) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(136) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(135) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(134) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(133) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(132) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(131) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(130) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(129) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(128) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(127) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(126) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(125) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(124) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(123) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(122) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(121) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(120) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(119) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(118) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(117) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(116) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(115) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(114) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(113) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(112) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(111) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(110) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(109) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(108) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(107) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(106) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(105) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(104) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(103) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(102) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(101) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(100) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(99) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(98) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(97) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(96) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(95) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(94) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(93) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(92) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(91) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(90) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(89) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(88) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(87) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(86) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(85) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(84) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(83) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(82) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(81) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(80) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(79) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(78) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(77) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(76) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(75) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(74) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(73) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(72) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(71) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(70) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(69) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(68) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(67) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(66) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(65) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(64) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(63) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(62) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(61) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(60) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(59) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(58) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(57) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(56) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(55) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(54) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(53) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(52) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(51) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(50) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(49) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(48) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(47) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(46) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(45) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(44) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(43) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(42) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(41) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(40) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(39) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(38) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(37) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(36) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(35) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(34) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(33) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(32) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(31) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(30) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(29) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(28) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(27) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(26) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(25) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(24) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(23) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(22) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(21) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(20) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(19) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(18) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(17) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(16) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCCRED(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(15) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(14) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(13) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(12) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(11) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(10) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(9) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(8) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(7) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(6) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(5) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(4) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(3) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(2) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(1) => NlwRenamedSig_OI_DEBUG(338),
      L0TXTLFCCMPLMCUPDATE(0) => NlwRenamedSig_OI_DEBUG(338),
      L0TXDLLFCCMPLMCUPDATED(7) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_7_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(6) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_6_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(5) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_5_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(4) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_4_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(3) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_3_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(2) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_2_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(1) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_1_UNCONNECTED,
      L0TXDLLFCCMPLMCUPDATED(0) => NLW_pcie_ep_L0TXDLLFCCMPLMCUPDATED_0_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(19) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_19_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(18) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_18_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(17) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_17_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(16) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_16_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(15) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_15_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(14) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_14_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(13) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_13_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(12) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_12_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(11) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_11_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(10) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_10_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(9) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_9_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(8) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_8_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(7) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_7_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(6) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_6_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(5) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_5_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(4) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_4_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(3) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_3_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(2) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_2_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(1) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_1_UNCONNECTED,
      L0RXDLLFCNPOSTBYPCRED(0) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPCRED_0_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(7) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_7_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(6) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_6_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(5) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_5_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(4) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_4_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(3) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_3_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(2) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_2_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(1) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_1_UNCONNECTED,
      L0RXDLLFCNPOSTBYPUPDATE(0) => NLW_pcie_ep_L0RXDLLFCNPOSTBYPUPDATE_0_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(23) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_23_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(22) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_22_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(21) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_21_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(20) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_20_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(19) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_19_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(18) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_18_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(17) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_17_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(16) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_16_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(15) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_15_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(14) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_14_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(13) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_13_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(12) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_12_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(11) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_11_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(10) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_10_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(9) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_9_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(8) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_8_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(7) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_7_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(6) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_6_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(5) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_5_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(4) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_4_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(3) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_3_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(2) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_2_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(1) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_1_UNCONNECTED,
      L0RXDLLFCPOSTORDCRED(0) => NLW_pcie_ep_L0RXDLLFCPOSTORDCRED_0_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(7) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_7_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(6) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_6_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(5) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_5_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(4) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_4_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(3) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_3_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(2) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_2_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(1) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_1_UNCONNECTED,
      L0RXDLLFCPOSTORDUPDATE(0) => NLW_pcie_ep_L0RXDLLFCPOSTORDUPDATE_0_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(23) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_23_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(22) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_22_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(21) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_21_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(20) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_20_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(19) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_19_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(18) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_18_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(17) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_17_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(16) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_16_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(15) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_15_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(14) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_14_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(13) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_13_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(12) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_12_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(11) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_11_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(10) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_10_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(9) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_9_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(8) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_8_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(7) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_7_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(6) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_6_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(5) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_5_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(4) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_4_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(3) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_3_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(2) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_2_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(1) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_1_UNCONNECTED,
      L0RXDLLFCCMPLMCCRED(0) => NLW_pcie_ep_L0RXDLLFCCMPLMCCRED_0_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(7) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_7_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(6) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_6_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(5) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_5_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(4) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_4_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(3) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_3_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(2) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_2_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(1) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_1_UNCONNECTED,
      L0RXDLLFCCMPLMCUPDATE(0) => NLW_pcie_ep_L0RXDLLFCCMPLMCUPDATE_0_UNCONNECTED,
      L0RXTLTLPNONINITIALIZEDVC(7) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(6) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(5) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(4) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(3) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(2) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(1) => NlwRenamedSig_OI_DEBUG(338),
      L0RXTLTLPNONINITIALIZEDVC(0) => NlwRenamedSig_OI_DEBUG(338),
      L0UCBYPFOUND(3) => NLW_pcie_ep_L0UCBYPFOUND_3_UNCONNECTED,
      L0UCBYPFOUND(2) => NLW_pcie_ep_L0UCBYPFOUND_2_UNCONNECTED,
      L0UCBYPFOUND(1) => NLW_pcie_ep_L0UCBYPFOUND_1_UNCONNECTED,
      L0UCBYPFOUND(0) => NLW_pcie_ep_L0UCBYPFOUND_0_UNCONNECTED,
      L0UCORDFOUND(3) => NLW_pcie_ep_L0UCORDFOUND_3_UNCONNECTED,
      L0UCORDFOUND(2) => NLW_pcie_ep_L0UCORDFOUND_2_UNCONNECTED,
      L0UCORDFOUND(1) => NLW_pcie_ep_L0UCORDFOUND_1_UNCONNECTED,
      L0UCORDFOUND(0) => NLW_pcie_ep_L0UCORDFOUND_0_UNCONNECTED,
      L0MCFOUND(2) => NLW_pcie_ep_L0MCFOUND_2_UNCONNECTED,
      L0MCFOUND(1) => NLW_pcie_ep_L0MCFOUND_1_UNCONNECTED,
      L0MCFOUND(0) => NLW_pcie_ep_L0MCFOUND_0_UNCONNECTED,
      L0TRANSFORMEDVC(2) => NLW_pcie_ep_L0TRANSFORMEDVC_2_UNCONNECTED,
      L0TRANSFORMEDVC(1) => NLW_pcie_ep_L0TRANSFORMEDVC_1_UNCONNECTED,
      L0TRANSFORMEDVC(0) => NLW_pcie_ep_L0TRANSFORMEDVC_0_UNCONNECTED
    );
  prod_fixes_I : prod_fixes
    port map (
      clk => NlwRenamedSig_OI_core_clk,
      chan_bond_done => NLW_prod_fixes_I_chan_bond_done_UNCONNECTED,
      bit_reset_n => trn_reset_n,
      upcfgcap_cycle => NLW_prod_fixes_I_upcfgcap_cycle_UNCONNECTED,
      masking_ack => NLW_prod_fixes_I_masking_ack_UNCONNECTED,
      trn_lnk_up_n => trn_lnk_up_n,
      pipe_rx_data_l2_out(7) => pipe_rx_data_l2_out(7),
      pipe_rx_data_l2_out(6) => pipe_rx_data_l2_out(6),
      pipe_rx_data_l2_out(5) => pipe_rx_data_l2_out(5),
      pipe_rx_data_l2_out(4) => pipe_rx_data_l2_out(4),
      pipe_rx_data_l2_out(3) => pipe_rx_data_l2_out(3),
      pipe_rx_data_l2_out(2) => pipe_rx_data_l2_out(2),
      pipe_rx_data_l2_out(1) => pipe_rx_data_l2_out(1),
      pipe_rx_data_l2_out(0) => pipe_rx_data_l2_out(0),
      pipe_rx_data_k_out(7) => pipe_rx_data_k_out(7),
      pipe_rx_data_k_out(6) => pipe_rx_data_k_out(6),
      pipe_rx_data_k_out(5) => pipe_rx_data_k_out(5),
      pipe_rx_data_k_out(4) => pipe_rx_data_k_out(4),
      pipe_rx_data_k_out(3) => pipe_rx_data_k_out(3),
      pipe_rx_data_k_out(2) => pipe_rx_data_k_out(2),
      pipe_rx_data_k_out(1) => pipe_rx_data_k_out(1),
      pipe_rx_data_k_out(0) => pipe_rx_data_k_out(0),
      pipe_rx_data_l7_out(7) => pipe_rx_data_l7_out(7),
      pipe_rx_data_l7_out(6) => pipe_rx_data_l7_out(6),
      pipe_rx_data_l7_out(5) => pipe_rx_data_l7_out(5),
      pipe_rx_data_l7_out(4) => pipe_rx_data_l7_out(4),
      pipe_rx_data_l7_out(3) => pipe_rx_data_l7_out(3),
      pipe_rx_data_l7_out(2) => pipe_rx_data_l7_out(2),
      pipe_rx_data_l7_out(1) => pipe_rx_data_l7_out(1),
      pipe_rx_data_l7_out(0) => pipe_rx_data_l7_out(0),
      pipe_rx_data_l3_out(7) => pipe_rx_data_l3_out(7),
      pipe_rx_data_l3_out(6) => pipe_rx_data_l3_out(6),
      pipe_rx_data_l3_out(5) => pipe_rx_data_l3_out(5),
      pipe_rx_data_l3_out(4) => pipe_rx_data_l3_out(4),
      pipe_rx_data_l3_out(3) => pipe_rx_data_l3_out(3),
      pipe_rx_data_l3_out(2) => pipe_rx_data_l3_out(2),
      pipe_rx_data_l3_out(1) => pipe_rx_data_l3_out(1),
      pipe_rx_data_l3_out(0) => pipe_rx_data_l3_out(0),
      pipe_rx_data_l4_out(7) => pipe_rx_data_l4_out(7),
      pipe_rx_data_l4_out(6) => pipe_rx_data_l4_out(6),
      pipe_rx_data_l4_out(5) => pipe_rx_data_l4_out(5),
      pipe_rx_data_l4_out(4) => pipe_rx_data_l4_out(4),
      pipe_rx_data_l4_out(3) => pipe_rx_data_l4_out(3),
      pipe_rx_data_l4_out(2) => pipe_rx_data_l4_out(2),
      pipe_rx_data_l4_out(1) => pipe_rx_data_l4_out(1),
      pipe_rx_data_l4_out(0) => pipe_rx_data_l4_out(0),
      pipe_rx_data_l0_out(7) => pipe_rx_data_l0_out(7),
      pipe_rx_data_l0_out(6) => pipe_rx_data_l0_out(6),
      pipe_rx_data_l0_out(5) => pipe_rx_data_l0_out(5),
      pipe_rx_data_l0_out(4) => pipe_rx_data_l0_out(4),
      pipe_rx_data_l0_out(3) => pipe_rx_data_l0_out(3),
      pipe_rx_data_l0_out(2) => pipe_rx_data_l0_out(2),
      pipe_rx_data_l0_out(1) => pipe_rx_data_l0_out(1),
      pipe_rx_data_l0_out(0) => pipe_rx_data_l0_out(0),
      pipe_rx_data_l5_out(7) => pipe_rx_data_l5_out(7),
      pipe_rx_data_l5_out(6) => pipe_rx_data_l5_out(6),
      pipe_rx_data_l5_out(5) => pipe_rx_data_l5_out(5),
      pipe_rx_data_l5_out(4) => pipe_rx_data_l5_out(4),
      pipe_rx_data_l5_out(3) => pipe_rx_data_l5_out(3),
      pipe_rx_data_l5_out(2) => pipe_rx_data_l5_out(2),
      pipe_rx_data_l5_out(1) => pipe_rx_data_l5_out(1),
      pipe_rx_data_l5_out(0) => pipe_rx_data_l5_out(0),
      pipe_rx_data_l1_out(7) => pipe_rx_data_l1_out(7),
      pipe_rx_data_l1_out(6) => pipe_rx_data_l1_out(6),
      pipe_rx_data_l1_out(5) => pipe_rx_data_l1_out(5),
      pipe_rx_data_l1_out(4) => pipe_rx_data_l1_out(4),
      pipe_rx_data_l1_out(3) => pipe_rx_data_l1_out(3),
      pipe_rx_data_l1_out(2) => pipe_rx_data_l1_out(2),
      pipe_rx_data_l1_out(1) => pipe_rx_data_l1_out(1),
      pipe_rx_data_l1_out(0) => pipe_rx_data_l1_out(0),
      pipe_rx_valid_out(7) => pipe_rx_valid_out(7),
      pipe_rx_valid_out(6) => pipe_rx_valid_out(6),
      pipe_rx_valid_out(5) => pipe_rx_valid_out(5),
      pipe_rx_valid_out(4) => pipe_rx_valid_out(4),
      pipe_rx_valid_out(3) => pipe_rx_valid_out(3),
      pipe_rx_valid_out(2) => pipe_rx_valid_out(2),
      pipe_rx_valid_out(1) => pipe_rx_valid_out(1),
      pipe_rx_valid_out(0) => pipe_rx_valid_out(0),
      pipe_rx_data_l6_out(7) => pipe_rx_data_l6_out(7),
      pipe_rx_data_l6_out(6) => pipe_rx_data_l6_out(6),
      pipe_rx_data_l6_out(5) => pipe_rx_data_l6_out(5),
      pipe_rx_data_l6_out(4) => pipe_rx_data_l6_out(4),
      pipe_rx_data_l6_out(3) => pipe_rx_data_l6_out(3),
      pipe_rx_data_l6_out(2) => pipe_rx_data_l6_out(2),
      pipe_rx_data_l6_out(1) => pipe_rx_data_l6_out(1),
      pipe_rx_data_l6_out(0) => pipe_rx_data_l6_out(0),
      negotiated_link_width(3) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(3),
      negotiated_link_width(2) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(2),
      negotiated_link_width(1) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(1),
      negotiated_link_width(0) => NlwRenamedSig_OI_l0_mac_negotiated_link_width(0),
      pipe_rx_data_l0(7) => pipe_rx_data(7),
      pipe_rx_data_l0(6) => pipe_rx_data(6),
      pipe_rx_data_l0(5) => pipe_rx_data(5),
      pipe_rx_data_l0(4) => pipe_rx_data(4),
      pipe_rx_data_l0(3) => pipe_rx_data(3),
      pipe_rx_data_l0(2) => pipe_rx_data(2),
      pipe_rx_data_l0(1) => pipe_rx_data(1),
      pipe_rx_data_l0(0) => pipe_rx_data(0),
      pipe_rx_data_l1(7) => pipe_rx_data(15),
      pipe_rx_data_l1(6) => pipe_rx_data(14),
      pipe_rx_data_l1(5) => pipe_rx_data(13),
      pipe_rx_data_l1(4) => pipe_rx_data(12),
      pipe_rx_data_l1(3) => pipe_rx_data(11),
      pipe_rx_data_l1(2) => pipe_rx_data(10),
      pipe_rx_data_l1(1) => pipe_rx_data(9),
      pipe_rx_data_l1(0) => pipe_rx_data(8),
      pipe_rx_data_l2(7) => pipe_rx_data(23),
      pipe_rx_data_l2(6) => pipe_rx_data(22),
      pipe_rx_data_l2(5) => pipe_rx_data(21),
      pipe_rx_data_l2(4) => pipe_rx_data(20),
      pipe_rx_data_l2(3) => pipe_rx_data(19),
      pipe_rx_data_l2(2) => pipe_rx_data(18),
      pipe_rx_data_l2(1) => pipe_rx_data(17),
      pipe_rx_data_l2(0) => pipe_rx_data(16),
      pipe_rx_data_l3(7) => pipe_rx_data(31),
      pipe_rx_data_l3(6) => pipe_rx_data(30),
      pipe_rx_data_l3(5) => pipe_rx_data(29),
      pipe_rx_data_l3(4) => pipe_rx_data(28),
      pipe_rx_data_l3(3) => pipe_rx_data(27),
      pipe_rx_data_l3(2) => pipe_rx_data(26),
      pipe_rx_data_l3(1) => pipe_rx_data(25),
      pipe_rx_data_l3(0) => pipe_rx_data(24),
      pipe_rx_data_l4(7) => pipe_rx_data(39),
      pipe_rx_data_l4(6) => pipe_rx_data(38),
      pipe_rx_data_l4(5) => pipe_rx_data(37),
      pipe_rx_data_l4(4) => pipe_rx_data(36),
      pipe_rx_data_l4(3) => pipe_rx_data(35),
      pipe_rx_data_l4(2) => pipe_rx_data(34),
      pipe_rx_data_l4(1) => pipe_rx_data(33),
      pipe_rx_data_l4(0) => pipe_rx_data(32),
      pipe_rx_data_l5(7) => pipe_rx_data(47),
      pipe_rx_data_l5(6) => pipe_rx_data(46),
      pipe_rx_data_l5(5) => pipe_rx_data(45),
      pipe_rx_data_l5(4) => pipe_rx_data(44),
      pipe_rx_data_l5(3) => pipe_rx_data(43),
      pipe_rx_data_l5(2) => pipe_rx_data(42),
      pipe_rx_data_l5(1) => pipe_rx_data(41),
      pipe_rx_data_l5(0) => pipe_rx_data(40),
      pipe_rx_data_l6(7) => pipe_rx_data(55),
      pipe_rx_data_l6(6) => pipe_rx_data(54),
      pipe_rx_data_l6(5) => pipe_rx_data(53),
      pipe_rx_data_l6(4) => pipe_rx_data(52),
      pipe_rx_data_l6(3) => pipe_rx_data(51),
      pipe_rx_data_l6(2) => pipe_rx_data(50),
      pipe_rx_data_l6(1) => pipe_rx_data(49),
      pipe_rx_data_l6(0) => pipe_rx_data(48),
      l0_ltssm_state(3) => NlwRenamedSig_OI_l0_ltssm_state(3),
      l0_ltssm_state(2) => NlwRenamedSig_OI_l0_ltssm_state(2),
      l0_ltssm_state(1) => NlwRenamedSig_OI_l0_ltssm_state(1),
      l0_ltssm_state(0) => NlwRenamedSig_OI_l0_ltssm_state(0),
      pipe_rx_data_l7(7) => pipe_rx_data(63),
      pipe_rx_data_l7(6) => pipe_rx_data(62),
      pipe_rx_data_l7(5) => pipe_rx_data(61),
      pipe_rx_data_l7(4) => pipe_rx_data(60),
      pipe_rx_data_l7(3) => pipe_rx_data(59),
      pipe_rx_data_l7(2) => pipe_rx_data(58),
      pipe_rx_data_l7(1) => pipe_rx_data(57),
      pipe_rx_data_l7(0) => pipe_rx_data(56),
      pipe_rx_valid(7) => pipe_rx_valid(7),
      pipe_rx_valid(6) => pipe_rx_valid(6),
      pipe_rx_valid(5) => pipe_rx_valid(5),
      pipe_rx_valid(4) => pipe_rx_valid(4),
      pipe_rx_valid(3) => pipe_rx_valid(3),
      pipe_rx_valid(2) => pipe_rx_valid(2),
      pipe_rx_valid(1) => pipe_rx_valid(1),
      pipe_rx_valid(0) => pipe_rx_valid(0),
      pipe_rx_data_k(7) => pipe_rx_data_k(7),
      pipe_rx_data_k(6) => pipe_rx_data_k(6),
      pipe_rx_data_k(5) => pipe_rx_data_k(5),
      pipe_rx_data_k(4) => pipe_rx_data_k(4),
      pipe_rx_data_k(3) => pipe_rx_data_k(3),
      pipe_rx_data_k(2) => pipe_rx_data_k(2),
      pipe_rx_data_k(1) => pipe_rx_data_k(1),
      pipe_rx_data_k(0) => pipe_rx_data_k(0)
    );
  use_reset_logic_reset_i : reset_logic
    port map (
      CRMPWRSOFTRESETN => NlwRenamedSig_OI_crm_pwr_soft_reset_n,
      CRMLINKRSTN => rb_crm_link_rst_n,
      CRMUSERCFGRSTN => rb_crm_user_cfg_rst_n,
      CRMURSTN => rb_crm_urst_n,
      user_master_reset_n => user_reset_workaround_n,
      L0STATSCFGTRANSMITTED => NlwRenamedSig_OI_l0_stats_cfg_transmitted,
      CRMNVRSTN => rb_crm_nvrst_n,
      L0DLUPDOWN => NlwRenamedSig_OI_l0_dl_up_down(0),
      CRMCORECLK => NlwRenamedSig_OI_core_clk,
      CRMMACRSTN => rb_crm_mac_rst_n,
      clock_ready => NlwRenamedSig_OI_clock_lock,
      CRMDOHOTRESETN => NlwRenamedSig_OI_crm_do_hot_reset_n,
      CRMMGMTRSTN => NlwRenamedSig_OI_mgmt_rdy,
      USERCLK => NlwRenamedSig_OI_user_clk,
      L0LTSSMSTATE(3) => NlwRenamedSig_OI_l0_ltssm_state(3),
      L0LTSSMSTATE(2) => NlwRenamedSig_OI_l0_ltssm_state(2),
      L0LTSSMSTATE(1) => NlwRenamedSig_OI_l0_ltssm_state(1),
      L0LTSSMSTATE(0) => NlwRenamedSig_OI_l0_ltssm_state(0)
    );
  clocking_i : pcie_clocking
    port map (
      gtx_usrclk => gt_usrclk,
      txsync_clk => txsync_clk,
      rst => clocking_i_not0000,
      clkin_pll => NlwRenamedSig_OI_REFCLKOUT_bufg,
      fast_train_simulation_only => fast_train_simulation_only,
      coreclk => NlwRenamedSig_OI_core_clk,
      locked => NlwRenamedSig_OI_clock_lock,
      clkin_dcm => NlwRenamedSig_OI_GTPCLK_bufg,
      userclk => NlwRenamedSig_OI_user_clk
    );
  pcie_mim_wrapper_i : pcie_mim_wrapper
    port map (
      mim_tx_bwclk => NlwRenamedSig_OI_core_clk,
      mim_tx_bren => NlwRenamedSig_OI_DEBUG(14),
      mim_rx_bren => NlwRenamedSig_OI_DEBUG(106),
      mim_rx_brclk => NlwRenamedSig_OI_core_clk,
      mim_dll_bren => NlwRenamedSig_OI_DEBUG(260),
      mim_rx_bwclk => NlwRenamedSig_OI_core_clk,
      mim_dll_bclk => NlwRenamedSig_OI_core_clk,
      mim_tx_bwen => NlwRenamedSig_OI_DEBUG(13),
      mim_tx_brclk => NlwRenamedSig_OI_core_clk,
      mim_rx_bwen => NlwRenamedSig_OI_DEBUG(105),
      mim_dll_bwen => NlwRenamedSig_OI_DEBUG(337),
      mim_tx_brdata(63) => mim_tx_brdata(63),
      mim_tx_brdata(62) => mim_tx_brdata(62),
      mim_tx_brdata(61) => mim_tx_brdata(61),
      mim_tx_brdata(60) => mim_tx_brdata(60),
      mim_tx_brdata(59) => mim_tx_brdata(59),
      mim_tx_brdata(58) => mim_tx_brdata(58),
      mim_tx_brdata(57) => mim_tx_brdata(57),
      mim_tx_brdata(56) => mim_tx_brdata(56),
      mim_tx_brdata(55) => mim_tx_brdata(55),
      mim_tx_brdata(54) => mim_tx_brdata(54),
      mim_tx_brdata(53) => mim_tx_brdata(53),
      mim_tx_brdata(52) => mim_tx_brdata(52),
      mim_tx_brdata(51) => mim_tx_brdata(51),
      mim_tx_brdata(50) => mim_tx_brdata(50),
      mim_tx_brdata(49) => mim_tx_brdata(49),
      mim_tx_brdata(48) => mim_tx_brdata(48),
      mim_tx_brdata(47) => mim_tx_brdata(47),
      mim_tx_brdata(46) => mim_tx_brdata(46),
      mim_tx_brdata(45) => mim_tx_brdata(45),
      mim_tx_brdata(44) => mim_tx_brdata(44),
      mim_tx_brdata(43) => mim_tx_brdata(43),
      mim_tx_brdata(42) => mim_tx_brdata(42),
      mim_tx_brdata(41) => mim_tx_brdata(41),
      mim_tx_brdata(40) => mim_tx_brdata(40),
      mim_tx_brdata(39) => mim_tx_brdata(39),
      mim_tx_brdata(38) => mim_tx_brdata(38),
      mim_tx_brdata(37) => mim_tx_brdata(37),
      mim_tx_brdata(36) => mim_tx_brdata(36),
      mim_tx_brdata(35) => mim_tx_brdata(35),
      mim_tx_brdata(34) => mim_tx_brdata(34),
      mim_tx_brdata(33) => mim_tx_brdata(33),
      mim_tx_brdata(32) => mim_tx_brdata(32),
      mim_tx_brdata(31) => mim_tx_brdata(31),
      mim_tx_brdata(30) => mim_tx_brdata(30),
      mim_tx_brdata(29) => mim_tx_brdata(29),
      mim_tx_brdata(28) => mim_tx_brdata(28),
      mim_tx_brdata(27) => mim_tx_brdata(27),
      mim_tx_brdata(26) => mim_tx_brdata(26),
      mim_tx_brdata(25) => mim_tx_brdata(25),
      mim_tx_brdata(24) => mim_tx_brdata(24),
      mim_tx_brdata(23) => mim_tx_brdata(23),
      mim_tx_brdata(22) => mim_tx_brdata(22),
      mim_tx_brdata(21) => mim_tx_brdata(21),
      mim_tx_brdata(20) => mim_tx_brdata(20),
      mim_tx_brdata(19) => mim_tx_brdata(19),
      mim_tx_brdata(18) => mim_tx_brdata(18),
      mim_tx_brdata(17) => mim_tx_brdata(17),
      mim_tx_brdata(16) => mim_tx_brdata(16),
      mim_tx_brdata(15) => mim_tx_brdata(15),
      mim_tx_brdata(14) => mim_tx_brdata(14),
      mim_tx_brdata(13) => mim_tx_brdata(13),
      mim_tx_brdata(12) => mim_tx_brdata(12),
      mim_tx_brdata(11) => mim_tx_brdata(11),
      mim_tx_brdata(10) => mim_tx_brdata(10),
      mim_tx_brdata(9) => mim_tx_brdata(9),
      mim_tx_brdata(8) => mim_tx_brdata(8),
      mim_tx_brdata(7) => mim_tx_brdata(7),
      mim_tx_brdata(6) => mim_tx_brdata(6),
      mim_tx_brdata(5) => mim_tx_brdata(5),
      mim_tx_brdata(4) => mim_tx_brdata(4),
      mim_tx_brdata(3) => mim_tx_brdata(3),
      mim_tx_brdata(2) => mim_tx_brdata(2),
      mim_tx_brdata(1) => mim_tx_brdata(1),
      mim_tx_brdata(0) => mim_tx_brdata(0),
      mim_rx_brdata(63) => mim_rx_brdata(63),
      mim_rx_brdata(62) => mim_rx_brdata(62),
      mim_rx_brdata(61) => mim_rx_brdata(61),
      mim_rx_brdata(60) => mim_rx_brdata(60),
      mim_rx_brdata(59) => mim_rx_brdata(59),
      mim_rx_brdata(58) => mim_rx_brdata(58),
      mim_rx_brdata(57) => mim_rx_brdata(57),
      mim_rx_brdata(56) => mim_rx_brdata(56),
      mim_rx_brdata(55) => mim_rx_brdata(55),
      mim_rx_brdata(54) => mim_rx_brdata(54),
      mim_rx_brdata(53) => mim_rx_brdata(53),
      mim_rx_brdata(52) => mim_rx_brdata(52),
      mim_rx_brdata(51) => mim_rx_brdata(51),
      mim_rx_brdata(50) => mim_rx_brdata(50),
      mim_rx_brdata(49) => mim_rx_brdata(49),
      mim_rx_brdata(48) => mim_rx_brdata(48),
      mim_rx_brdata(47) => mim_rx_brdata(47),
      mim_rx_brdata(46) => mim_rx_brdata(46),
      mim_rx_brdata(45) => mim_rx_brdata(45),
      mim_rx_brdata(44) => mim_rx_brdata(44),
      mim_rx_brdata(43) => mim_rx_brdata(43),
      mim_rx_brdata(42) => mim_rx_brdata(42),
      mim_rx_brdata(41) => mim_rx_brdata(41),
      mim_rx_brdata(40) => mim_rx_brdata(40),
      mim_rx_brdata(39) => mim_rx_brdata(39),
      mim_rx_brdata(38) => mim_rx_brdata(38),
      mim_rx_brdata(37) => mim_rx_brdata(37),
      mim_rx_brdata(36) => mim_rx_brdata(36),
      mim_rx_brdata(35) => mim_rx_brdata(35),
      mim_rx_brdata(34) => mim_rx_brdata(34),
      mim_rx_brdata(33) => mim_rx_brdata(33),
      mim_rx_brdata(32) => mim_rx_brdata(32),
      mim_rx_brdata(31) => mim_rx_brdata(31),
      mim_rx_brdata(30) => mim_rx_brdata(30),
      mim_rx_brdata(29) => mim_rx_brdata(29),
      mim_rx_brdata(28) => mim_rx_brdata(28),
      mim_rx_brdata(27) => mim_rx_brdata(27),
      mim_rx_brdata(26) => mim_rx_brdata(26),
      mim_rx_brdata(25) => mim_rx_brdata(25),
      mim_rx_brdata(24) => mim_rx_brdata(24),
      mim_rx_brdata(23) => mim_rx_brdata(23),
      mim_rx_brdata(22) => mim_rx_brdata(22),
      mim_rx_brdata(21) => mim_rx_brdata(21),
      mim_rx_brdata(20) => mim_rx_brdata(20),
      mim_rx_brdata(19) => mim_rx_brdata(19),
      mim_rx_brdata(18) => mim_rx_brdata(18),
      mim_rx_brdata(17) => mim_rx_brdata(17),
      mim_rx_brdata(16) => mim_rx_brdata(16),
      mim_rx_brdata(15) => mim_rx_brdata(15),
      mim_rx_brdata(14) => mim_rx_brdata(14),
      mim_rx_brdata(13) => mim_rx_brdata(13),
      mim_rx_brdata(12) => mim_rx_brdata(12),
      mim_rx_brdata(11) => mim_rx_brdata(11),
      mim_rx_brdata(10) => mim_rx_brdata(10),
      mim_rx_brdata(9) => mim_rx_brdata(9),
      mim_rx_brdata(8) => mim_rx_brdata(8),
      mim_rx_brdata(7) => mim_rx_brdata(7),
      mim_rx_brdata(6) => mim_rx_brdata(6),
      mim_rx_brdata(5) => mim_rx_brdata(5),
      mim_rx_brdata(4) => mim_rx_brdata(4),
      mim_rx_brdata(3) => mim_rx_brdata(3),
      mim_rx_brdata(2) => mim_rx_brdata(2),
      mim_rx_brdata(1) => mim_rx_brdata(1),
      mim_rx_brdata(0) => mim_rx_brdata(0),
      mim_dll_brdata(63) => NlwRenamedSig_OI_DEBUG(247),
      mim_dll_brdata(62) => NlwRenamedSig_OI_DEBUG(246),
      mim_dll_brdata(61) => NlwRenamedSig_OI_DEBUG(245),
      mim_dll_brdata(60) => NlwRenamedSig_OI_DEBUG(244),
      mim_dll_brdata(59) => NlwRenamedSig_OI_DEBUG(243),
      mim_dll_brdata(58) => NlwRenamedSig_OI_DEBUG(242),
      mim_dll_brdata(57) => NlwRenamedSig_OI_DEBUG(241),
      mim_dll_brdata(56) => NlwRenamedSig_OI_DEBUG(240),
      mim_dll_brdata(55) => NlwRenamedSig_OI_DEBUG(239),
      mim_dll_brdata(54) => NlwRenamedSig_OI_DEBUG(238),
      mim_dll_brdata(53) => NlwRenamedSig_OI_DEBUG(237),
      mim_dll_brdata(52) => NlwRenamedSig_OI_DEBUG(236),
      mim_dll_brdata(51) => NlwRenamedSig_OI_DEBUG(235),
      mim_dll_brdata(50) => NlwRenamedSig_OI_DEBUG(234),
      mim_dll_brdata(49) => NlwRenamedSig_OI_DEBUG(233),
      mim_dll_brdata(48) => NlwRenamedSig_OI_DEBUG(232),
      mim_dll_brdata(47) => NlwRenamedSig_OI_DEBUG(231),
      mim_dll_brdata(46) => NlwRenamedSig_OI_DEBUG(230),
      mim_dll_brdata(45) => NlwRenamedSig_OI_DEBUG(229),
      mim_dll_brdata(44) => NlwRenamedSig_OI_DEBUG(228),
      mim_dll_brdata(43) => NlwRenamedSig_OI_DEBUG(227),
      mim_dll_brdata(42) => NlwRenamedSig_OI_DEBUG(226),
      mim_dll_brdata(41) => NlwRenamedSig_OI_DEBUG(225),
      mim_dll_brdata(40) => NlwRenamedSig_OI_DEBUG(224),
      mim_dll_brdata(39) => NlwRenamedSig_OI_DEBUG(223),
      mim_dll_brdata(38) => NlwRenamedSig_OI_DEBUG(222),
      mim_dll_brdata(37) => NlwRenamedSig_OI_DEBUG(221),
      mim_dll_brdata(36) => NlwRenamedSig_OI_DEBUG(220),
      mim_dll_brdata(35) => NlwRenamedSig_OI_DEBUG(219),
      mim_dll_brdata(34) => NlwRenamedSig_OI_DEBUG(218),
      mim_dll_brdata(33) => NlwRenamedSig_OI_DEBUG(217),
      mim_dll_brdata(32) => NlwRenamedSig_OI_DEBUG(216),
      mim_dll_brdata(31) => NlwRenamedSig_OI_DEBUG(215),
      mim_dll_brdata(30) => NlwRenamedSig_OI_DEBUG(214),
      mim_dll_brdata(29) => NlwRenamedSig_OI_DEBUG(213),
      mim_dll_brdata(28) => NlwRenamedSig_OI_DEBUG(212),
      mim_dll_brdata(27) => NlwRenamedSig_OI_DEBUG(211),
      mim_dll_brdata(26) => NlwRenamedSig_OI_DEBUG(210),
      mim_dll_brdata(25) => NlwRenamedSig_OI_DEBUG(209),
      mim_dll_brdata(24) => NlwRenamedSig_OI_DEBUG(208),
      mim_dll_brdata(23) => NlwRenamedSig_OI_DEBUG(207),
      mim_dll_brdata(22) => NlwRenamedSig_OI_DEBUG(206),
      mim_dll_brdata(21) => NlwRenamedSig_OI_DEBUG(205),
      mim_dll_brdata(20) => NlwRenamedSig_OI_DEBUG(204),
      mim_dll_brdata(19) => NlwRenamedSig_OI_DEBUG(203),
      mim_dll_brdata(18) => NlwRenamedSig_OI_DEBUG(202),
      mim_dll_brdata(17) => NlwRenamedSig_OI_DEBUG(201),
      mim_dll_brdata(16) => NlwRenamedSig_OI_DEBUG(200),
      mim_dll_brdata(15) => NlwRenamedSig_OI_DEBUG(199),
      mim_dll_brdata(14) => NlwRenamedSig_OI_DEBUG(198),
      mim_dll_brdata(13) => NlwRenamedSig_OI_DEBUG(197),
      mim_dll_brdata(12) => NlwRenamedSig_OI_DEBUG(196),
      mim_dll_brdata(11) => NlwRenamedSig_OI_DEBUG(195),
      mim_dll_brdata(10) => NlwRenamedSig_OI_DEBUG(194),
      mim_dll_brdata(9) => NlwRenamedSig_OI_DEBUG(193),
      mim_dll_brdata(8) => NlwRenamedSig_OI_DEBUG(192),
      mim_dll_brdata(7) => NlwRenamedSig_OI_DEBUG(191),
      mim_dll_brdata(6) => NlwRenamedSig_OI_DEBUG(190),
      mim_dll_brdata(5) => NlwRenamedSig_OI_DEBUG(189),
      mim_dll_brdata(4) => NlwRenamedSig_OI_DEBUG(188),
      mim_dll_brdata(3) => NlwRenamedSig_OI_DEBUG(187),
      mim_dll_brdata(2) => NlwRenamedSig_OI_DEBUG(186),
      mim_dll_brdata(1) => NlwRenamedSig_OI_DEBUG(185),
      mim_dll_brdata(0) => NlwRenamedSig_OI_DEBUG(184),
      mim_dll_bwdata(63) => NlwRenamedSig_OI_DEBUG(324),
      mim_dll_bwdata(62) => NlwRenamedSig_OI_DEBUG(323),
      mim_dll_bwdata(61) => NlwRenamedSig_OI_DEBUG(322),
      mim_dll_bwdata(60) => NlwRenamedSig_OI_DEBUG(321),
      mim_dll_bwdata(59) => NlwRenamedSig_OI_DEBUG(320),
      mim_dll_bwdata(58) => NlwRenamedSig_OI_DEBUG(319),
      mim_dll_bwdata(57) => NlwRenamedSig_OI_DEBUG(318),
      mim_dll_bwdata(56) => NlwRenamedSig_OI_DEBUG(317),
      mim_dll_bwdata(55) => NlwRenamedSig_OI_DEBUG(316),
      mim_dll_bwdata(54) => NlwRenamedSig_OI_DEBUG(315),
      mim_dll_bwdata(53) => NlwRenamedSig_OI_DEBUG(314),
      mim_dll_bwdata(52) => NlwRenamedSig_OI_DEBUG(313),
      mim_dll_bwdata(51) => NlwRenamedSig_OI_DEBUG(312),
      mim_dll_bwdata(50) => NlwRenamedSig_OI_DEBUG(311),
      mim_dll_bwdata(49) => NlwRenamedSig_OI_DEBUG(310),
      mim_dll_bwdata(48) => NlwRenamedSig_OI_DEBUG(309),
      mim_dll_bwdata(47) => NlwRenamedSig_OI_DEBUG(308),
      mim_dll_bwdata(46) => NlwRenamedSig_OI_DEBUG(307),
      mim_dll_bwdata(45) => NlwRenamedSig_OI_DEBUG(306),
      mim_dll_bwdata(44) => NlwRenamedSig_OI_DEBUG(305),
      mim_dll_bwdata(43) => NlwRenamedSig_OI_DEBUG(304),
      mim_dll_bwdata(42) => NlwRenamedSig_OI_DEBUG(303),
      mim_dll_bwdata(41) => NlwRenamedSig_OI_DEBUG(302),
      mim_dll_bwdata(40) => NlwRenamedSig_OI_DEBUG(301),
      mim_dll_bwdata(39) => NlwRenamedSig_OI_DEBUG(300),
      mim_dll_bwdata(38) => NlwRenamedSig_OI_DEBUG(299),
      mim_dll_bwdata(37) => NlwRenamedSig_OI_DEBUG(298),
      mim_dll_bwdata(36) => NlwRenamedSig_OI_DEBUG(297),
      mim_dll_bwdata(35) => NlwRenamedSig_OI_DEBUG(296),
      mim_dll_bwdata(34) => NlwRenamedSig_OI_DEBUG(295),
      mim_dll_bwdata(33) => NlwRenamedSig_OI_DEBUG(294),
      mim_dll_bwdata(32) => NlwRenamedSig_OI_DEBUG(293),
      mim_dll_bwdata(31) => NlwRenamedSig_OI_DEBUG(292),
      mim_dll_bwdata(30) => NlwRenamedSig_OI_DEBUG(291),
      mim_dll_bwdata(29) => NlwRenamedSig_OI_DEBUG(290),
      mim_dll_bwdata(28) => NlwRenamedSig_OI_DEBUG(289),
      mim_dll_bwdata(27) => NlwRenamedSig_OI_DEBUG(288),
      mim_dll_bwdata(26) => NlwRenamedSig_OI_DEBUG(287),
      mim_dll_bwdata(25) => NlwRenamedSig_OI_DEBUG(286),
      mim_dll_bwdata(24) => NlwRenamedSig_OI_DEBUG(285),
      mim_dll_bwdata(23) => NlwRenamedSig_OI_DEBUG(284),
      mim_dll_bwdata(22) => NlwRenamedSig_OI_DEBUG(283),
      mim_dll_bwdata(21) => NlwRenamedSig_OI_DEBUG(282),
      mim_dll_bwdata(20) => NlwRenamedSig_OI_DEBUG(281),
      mim_dll_bwdata(19) => NlwRenamedSig_OI_DEBUG(280),
      mim_dll_bwdata(18) => NlwRenamedSig_OI_DEBUG(279),
      mim_dll_bwdata(17) => NlwRenamedSig_OI_DEBUG(278),
      mim_dll_bwdata(16) => NlwRenamedSig_OI_DEBUG(277),
      mim_dll_bwdata(15) => NlwRenamedSig_OI_DEBUG(276),
      mim_dll_bwdata(14) => NlwRenamedSig_OI_DEBUG(275),
      mim_dll_bwdata(13) => NlwRenamedSig_OI_DEBUG(274),
      mim_dll_bwdata(12) => NlwRenamedSig_OI_DEBUG(273),
      mim_dll_bwdata(11) => NlwRenamedSig_OI_DEBUG(272),
      mim_dll_bwdata(10) => NlwRenamedSig_OI_DEBUG(271),
      mim_dll_bwdata(9) => NlwRenamedSig_OI_DEBUG(270),
      mim_dll_bwdata(8) => NlwRenamedSig_OI_DEBUG(269),
      mim_dll_bwdata(7) => NlwRenamedSig_OI_DEBUG(268),
      mim_dll_bwdata(6) => NlwRenamedSig_OI_DEBUG(267),
      mim_dll_bwdata(5) => NlwRenamedSig_OI_DEBUG(266),
      mim_dll_bwdata(4) => NlwRenamedSig_OI_DEBUG(265),
      mim_dll_bwdata(3) => NlwRenamedSig_OI_DEBUG(264),
      mim_dll_bwdata(2) => NlwRenamedSig_OI_DEBUG(263),
      mim_dll_bwdata(1) => NlwRenamedSig_OI_DEBUG(262),
      mim_dll_bwdata(0) => NlwRenamedSig_OI_DEBUG(261),
      mim_dll_bwadd(11) => NlwRenamedSig_OI_DEBUG(336),
      mim_dll_bwadd(10) => NlwRenamedSig_OI_DEBUG(335),
      mim_dll_bwadd(9) => NlwRenamedSig_OI_DEBUG(334),
      mim_dll_bwadd(8) => NlwRenamedSig_OI_DEBUG(333),
      mim_dll_bwadd(7) => NlwRenamedSig_OI_DEBUG(332),
      mim_dll_bwadd(6) => NlwRenamedSig_OI_DEBUG(331),
      mim_dll_bwadd(5) => NlwRenamedSig_OI_DEBUG(330),
      mim_dll_bwadd(4) => NlwRenamedSig_OI_DEBUG(329),
      mim_dll_bwadd(3) => NlwRenamedSig_OI_DEBUG(328),
      mim_dll_bwadd(2) => NlwRenamedSig_OI_DEBUG(327),
      mim_dll_bwadd(1) => NlwRenamedSig_OI_DEBUG(326),
      mim_dll_bwadd(0) => NlwRenamedSig_OI_DEBUG(325),
      mim_tx_bradd(12) => NlwRenamedSig_OI_DEBUG(91),
      mim_tx_bradd(11) => NlwRenamedSig_OI_DEBUG(90),
      mim_tx_bradd(10) => NlwRenamedSig_OI_DEBUG(89),
      mim_tx_bradd(9) => NlwRenamedSig_OI_DEBUG(88),
      mim_tx_bradd(8) => NlwRenamedSig_OI_DEBUG(87),
      mim_tx_bradd(7) => NlwRenamedSig_OI_DEBUG(86),
      mim_tx_bradd(6) => NlwRenamedSig_OI_DEBUG(85),
      mim_tx_bradd(5) => NlwRenamedSig_OI_DEBUG(84),
      mim_tx_bradd(4) => NlwRenamedSig_OI_DEBUG(83),
      mim_tx_bradd(3) => NlwRenamedSig_OI_DEBUG(82),
      mim_tx_bradd(2) => NlwRenamedSig_OI_DEBUG(81),
      mim_tx_bradd(1) => NlwRenamedSig_OI_DEBUG(80),
      mim_tx_bradd(0) => NlwRenamedSig_OI_DEBUG(79),
      mim_tx_bwadd(12) => NlwRenamedSig_OI_DEBUG(12),
      mim_tx_bwadd(11) => NlwRenamedSig_OI_DEBUG(11),
      mim_tx_bwadd(10) => NlwRenamedSig_OI_DEBUG(10),
      mim_tx_bwadd(9) => NlwRenamedSig_OI_DEBUG(9),
      mim_tx_bwadd(8) => NlwRenamedSig_OI_DEBUG(8),
      mim_tx_bwadd(7) => NlwRenamedSig_OI_DEBUG(7),
      mim_tx_bwadd(6) => NlwRenamedSig_OI_DEBUG(6),
      mim_tx_bwadd(5) => NlwRenamedSig_OI_DEBUG(5),
      mim_tx_bwadd(4) => NlwRenamedSig_OI_DEBUG(4),
      mim_tx_bwadd(3) => NlwRenamedSig_OI_DEBUG(3),
      mim_tx_bwadd(2) => NlwRenamedSig_OI_DEBUG(2),
      mim_tx_bwadd(1) => NlwRenamedSig_OI_DEBUG(1),
      mim_tx_bwadd(0) => NlwRenamedSig_OI_DEBUG(0),
      mim_rx_bradd(12) => NlwRenamedSig_OI_DEBUG(183),
      mim_rx_bradd(11) => NlwRenamedSig_OI_DEBUG(182),
      mim_rx_bradd(10) => NlwRenamedSig_OI_DEBUG(181),
      mim_rx_bradd(9) => NlwRenamedSig_OI_DEBUG(180),
      mim_rx_bradd(8) => NlwRenamedSig_OI_DEBUG(179),
      mim_rx_bradd(7) => NlwRenamedSig_OI_DEBUG(178),
      mim_rx_bradd(6) => NlwRenamedSig_OI_DEBUG(177),
      mim_rx_bradd(5) => NlwRenamedSig_OI_DEBUG(176),
      mim_rx_bradd(4) => NlwRenamedSig_OI_DEBUG(175),
      mim_rx_bradd(3) => NlwRenamedSig_OI_DEBUG(174),
      mim_rx_bradd(2) => NlwRenamedSig_OI_DEBUG(173),
      mim_rx_bradd(1) => NlwRenamedSig_OI_DEBUG(172),
      mim_rx_bradd(0) => NlwRenamedSig_OI_DEBUG(171),
      mim_tx_bwdata(63) => NlwRenamedSig_OI_DEBUG(78),
      mim_tx_bwdata(62) => NlwRenamedSig_OI_DEBUG(77),
      mim_tx_bwdata(61) => NlwRenamedSig_OI_DEBUG(76),
      mim_tx_bwdata(60) => NlwRenamedSig_OI_DEBUG(75),
      mim_tx_bwdata(59) => NlwRenamedSig_OI_DEBUG(74),
      mim_tx_bwdata(58) => NlwRenamedSig_OI_DEBUG(73),
      mim_tx_bwdata(57) => NlwRenamedSig_OI_DEBUG(72),
      mim_tx_bwdata(56) => NlwRenamedSig_OI_DEBUG(71),
      mim_tx_bwdata(55) => NlwRenamedSig_OI_DEBUG(70),
      mim_tx_bwdata(54) => NlwRenamedSig_OI_DEBUG(69),
      mim_tx_bwdata(53) => NlwRenamedSig_OI_DEBUG(68),
      mim_tx_bwdata(52) => NlwRenamedSig_OI_DEBUG(67),
      mim_tx_bwdata(51) => NlwRenamedSig_OI_DEBUG(66),
      mim_tx_bwdata(50) => NlwRenamedSig_OI_DEBUG(65),
      mim_tx_bwdata(49) => NlwRenamedSig_OI_DEBUG(64),
      mim_tx_bwdata(48) => NlwRenamedSig_OI_DEBUG(63),
      mim_tx_bwdata(47) => NlwRenamedSig_OI_DEBUG(62),
      mim_tx_bwdata(46) => NlwRenamedSig_OI_DEBUG(61),
      mim_tx_bwdata(45) => NlwRenamedSig_OI_DEBUG(60),
      mim_tx_bwdata(44) => NlwRenamedSig_OI_DEBUG(59),
      mim_tx_bwdata(43) => NlwRenamedSig_OI_DEBUG(58),
      mim_tx_bwdata(42) => NlwRenamedSig_OI_DEBUG(57),
      mim_tx_bwdata(41) => NlwRenamedSig_OI_DEBUG(56),
      mim_tx_bwdata(40) => NlwRenamedSig_OI_DEBUG(55),
      mim_tx_bwdata(39) => NlwRenamedSig_OI_DEBUG(54),
      mim_tx_bwdata(38) => NlwRenamedSig_OI_DEBUG(53),
      mim_tx_bwdata(37) => NlwRenamedSig_OI_DEBUG(52),
      mim_tx_bwdata(36) => NlwRenamedSig_OI_DEBUG(51),
      mim_tx_bwdata(35) => NlwRenamedSig_OI_DEBUG(50),
      mim_tx_bwdata(34) => NlwRenamedSig_OI_DEBUG(49),
      mim_tx_bwdata(33) => NlwRenamedSig_OI_DEBUG(48),
      mim_tx_bwdata(32) => NlwRenamedSig_OI_DEBUG(47),
      mim_tx_bwdata(31) => NlwRenamedSig_OI_DEBUG(46),
      mim_tx_bwdata(30) => NlwRenamedSig_OI_DEBUG(45),
      mim_tx_bwdata(29) => NlwRenamedSig_OI_DEBUG(44),
      mim_tx_bwdata(28) => NlwRenamedSig_OI_DEBUG(43),
      mim_tx_bwdata(27) => NlwRenamedSig_OI_DEBUG(42),
      mim_tx_bwdata(26) => NlwRenamedSig_OI_DEBUG(41),
      mim_tx_bwdata(25) => NlwRenamedSig_OI_DEBUG(40),
      mim_tx_bwdata(24) => NlwRenamedSig_OI_DEBUG(39),
      mim_tx_bwdata(23) => NlwRenamedSig_OI_DEBUG(38),
      mim_tx_bwdata(22) => NlwRenamedSig_OI_DEBUG(37),
      mim_tx_bwdata(21) => NlwRenamedSig_OI_DEBUG(36),
      mim_tx_bwdata(20) => NlwRenamedSig_OI_DEBUG(35),
      mim_tx_bwdata(19) => NlwRenamedSig_OI_DEBUG(34),
      mim_tx_bwdata(18) => NlwRenamedSig_OI_DEBUG(33),
      mim_tx_bwdata(17) => NlwRenamedSig_OI_DEBUG(32),
      mim_tx_bwdata(16) => NlwRenamedSig_OI_DEBUG(31),
      mim_tx_bwdata(15) => NlwRenamedSig_OI_DEBUG(30),
      mim_tx_bwdata(14) => NlwRenamedSig_OI_DEBUG(29),
      mim_tx_bwdata(13) => NlwRenamedSig_OI_DEBUG(28),
      mim_tx_bwdata(12) => NlwRenamedSig_OI_DEBUG(27),
      mim_tx_bwdata(11) => NlwRenamedSig_OI_DEBUG(26),
      mim_tx_bwdata(10) => NlwRenamedSig_OI_DEBUG(25),
      mim_tx_bwdata(9) => NlwRenamedSig_OI_DEBUG(24),
      mim_tx_bwdata(8) => NlwRenamedSig_OI_DEBUG(23),
      mim_tx_bwdata(7) => NlwRenamedSig_OI_DEBUG(22),
      mim_tx_bwdata(6) => NlwRenamedSig_OI_DEBUG(21),
      mim_tx_bwdata(5) => NlwRenamedSig_OI_DEBUG(20),
      mim_tx_bwdata(4) => NlwRenamedSig_OI_DEBUG(19),
      mim_tx_bwdata(3) => NlwRenamedSig_OI_DEBUG(18),
      mim_tx_bwdata(2) => NlwRenamedSig_OI_DEBUG(17),
      mim_tx_bwdata(1) => NlwRenamedSig_OI_DEBUG(16),
      mim_tx_bwdata(0) => NlwRenamedSig_OI_DEBUG(15),
      mim_rx_bwadd(12) => NlwRenamedSig_OI_DEBUG(104),
      mim_rx_bwadd(11) => NlwRenamedSig_OI_DEBUG(103),
      mim_rx_bwadd(10) => NlwRenamedSig_OI_DEBUG(102),
      mim_rx_bwadd(9) => NlwRenamedSig_OI_DEBUG(101),
      mim_rx_bwadd(8) => NlwRenamedSig_OI_DEBUG(100),
      mim_rx_bwadd(7) => NlwRenamedSig_OI_DEBUG(99),
      mim_rx_bwadd(6) => NlwRenamedSig_OI_DEBUG(98),
      mim_rx_bwadd(5) => NlwRenamedSig_OI_DEBUG(97),
      mim_rx_bwadd(4) => NlwRenamedSig_OI_DEBUG(96),
      mim_rx_bwadd(3) => NlwRenamedSig_OI_DEBUG(95),
      mim_rx_bwadd(2) => NlwRenamedSig_OI_DEBUG(94),
      mim_rx_bwadd(1) => NlwRenamedSig_OI_DEBUG(93),
      mim_rx_bwadd(0) => NlwRenamedSig_OI_DEBUG(92),
      mim_rx_bwdata(63) => NlwRenamedSig_OI_DEBUG(170),
      mim_rx_bwdata(62) => NlwRenamedSig_OI_DEBUG(169),
      mim_rx_bwdata(61) => NlwRenamedSig_OI_DEBUG(168),
      mim_rx_bwdata(60) => NlwRenamedSig_OI_DEBUG(167),
      mim_rx_bwdata(59) => NlwRenamedSig_OI_DEBUG(166),
      mim_rx_bwdata(58) => NlwRenamedSig_OI_DEBUG(165),
      mim_rx_bwdata(57) => NlwRenamedSig_OI_DEBUG(164),
      mim_rx_bwdata(56) => NlwRenamedSig_OI_DEBUG(163),
      mim_rx_bwdata(55) => NlwRenamedSig_OI_DEBUG(162),
      mim_rx_bwdata(54) => NlwRenamedSig_OI_DEBUG(161),
      mim_rx_bwdata(53) => NlwRenamedSig_OI_DEBUG(160),
      mim_rx_bwdata(52) => NlwRenamedSig_OI_DEBUG(159),
      mim_rx_bwdata(51) => NlwRenamedSig_OI_DEBUG(158),
      mim_rx_bwdata(50) => NlwRenamedSig_OI_DEBUG(157),
      mim_rx_bwdata(49) => NlwRenamedSig_OI_DEBUG(156),
      mim_rx_bwdata(48) => NlwRenamedSig_OI_DEBUG(155),
      mim_rx_bwdata(47) => NlwRenamedSig_OI_DEBUG(154),
      mim_rx_bwdata(46) => NlwRenamedSig_OI_DEBUG(153),
      mim_rx_bwdata(45) => NlwRenamedSig_OI_DEBUG(152),
      mim_rx_bwdata(44) => NlwRenamedSig_OI_DEBUG(151),
      mim_rx_bwdata(43) => NlwRenamedSig_OI_DEBUG(150),
      mim_rx_bwdata(42) => NlwRenamedSig_OI_DEBUG(149),
      mim_rx_bwdata(41) => NlwRenamedSig_OI_DEBUG(148),
      mim_rx_bwdata(40) => NlwRenamedSig_OI_DEBUG(147),
      mim_rx_bwdata(39) => NlwRenamedSig_OI_DEBUG(146),
      mim_rx_bwdata(38) => NlwRenamedSig_OI_DEBUG(145),
      mim_rx_bwdata(37) => NlwRenamedSig_OI_DEBUG(144),
      mim_rx_bwdata(36) => NlwRenamedSig_OI_DEBUG(143),
      mim_rx_bwdata(35) => NlwRenamedSig_OI_DEBUG(142),
      mim_rx_bwdata(34) => NlwRenamedSig_OI_DEBUG(141),
      mim_rx_bwdata(33) => NlwRenamedSig_OI_DEBUG(140),
      mim_rx_bwdata(32) => NlwRenamedSig_OI_DEBUG(139),
      mim_rx_bwdata(31) => NlwRenamedSig_OI_DEBUG(138),
      mim_rx_bwdata(30) => NlwRenamedSig_OI_DEBUG(137),
      mim_rx_bwdata(29) => NlwRenamedSig_OI_DEBUG(136),
      mim_rx_bwdata(28) => NlwRenamedSig_OI_DEBUG(135),
      mim_rx_bwdata(27) => NlwRenamedSig_OI_DEBUG(134),
      mim_rx_bwdata(26) => NlwRenamedSig_OI_DEBUG(133),
      mim_rx_bwdata(25) => NlwRenamedSig_OI_DEBUG(132),
      mim_rx_bwdata(24) => NlwRenamedSig_OI_DEBUG(131),
      mim_rx_bwdata(23) => NlwRenamedSig_OI_DEBUG(130),
      mim_rx_bwdata(22) => NlwRenamedSig_OI_DEBUG(129),
      mim_rx_bwdata(21) => NlwRenamedSig_OI_DEBUG(128),
      mim_rx_bwdata(20) => NlwRenamedSig_OI_DEBUG(127),
      mim_rx_bwdata(19) => NlwRenamedSig_OI_DEBUG(126),
      mim_rx_bwdata(18) => NlwRenamedSig_OI_DEBUG(125),
      mim_rx_bwdata(17) => NlwRenamedSig_OI_DEBUG(124),
      mim_rx_bwdata(16) => NlwRenamedSig_OI_DEBUG(123),
      mim_rx_bwdata(15) => NlwRenamedSig_OI_DEBUG(122),
      mim_rx_bwdata(14) => NlwRenamedSig_OI_DEBUG(121),
      mim_rx_bwdata(13) => NlwRenamedSig_OI_DEBUG(120),
      mim_rx_bwdata(12) => NlwRenamedSig_OI_DEBUG(119),
      mim_rx_bwdata(11) => NlwRenamedSig_OI_DEBUG(118),
      mim_rx_bwdata(10) => NlwRenamedSig_OI_DEBUG(117),
      mim_rx_bwdata(9) => NlwRenamedSig_OI_DEBUG(116),
      mim_rx_bwdata(8) => NlwRenamedSig_OI_DEBUG(115),
      mim_rx_bwdata(7) => NlwRenamedSig_OI_DEBUG(114),
      mim_rx_bwdata(6) => NlwRenamedSig_OI_DEBUG(113),
      mim_rx_bwdata(5) => NlwRenamedSig_OI_DEBUG(112),
      mim_rx_bwdata(4) => NlwRenamedSig_OI_DEBUG(111),
      mim_rx_bwdata(3) => NlwRenamedSig_OI_DEBUG(110),
      mim_rx_bwdata(2) => NlwRenamedSig_OI_DEBUG(109),
      mim_rx_bwdata(1) => NlwRenamedSig_OI_DEBUG(108),
      mim_rx_bwdata(0) => NlwRenamedSig_OI_DEBUG(107),
      mim_dll_bradd(11) => NlwRenamedSig_OI_DEBUG(259),
      mim_dll_bradd(10) => NlwRenamedSig_OI_DEBUG(258),
      mim_dll_bradd(9) => NlwRenamedSig_OI_DEBUG(257),
      mim_dll_bradd(8) => NlwRenamedSig_OI_DEBUG(256),
      mim_dll_bradd(7) => NlwRenamedSig_OI_DEBUG(255),
      mim_dll_bradd(6) => NlwRenamedSig_OI_DEBUG(254),
      mim_dll_bradd(5) => NlwRenamedSig_OI_DEBUG(253),
      mim_dll_bradd(4) => NlwRenamedSig_OI_DEBUG(252),
      mim_dll_bradd(3) => NlwRenamedSig_OI_DEBUG(251),
      mim_dll_bradd(2) => NlwRenamedSig_OI_DEBUG(250),
      mim_dll_bradd(1) => NlwRenamedSig_OI_DEBUG(249),
      mim_dll_bradd(0) => NlwRenamedSig_OI_DEBUG(248)
    );
  SIO : pcie_gt_wrapper_top
    port map (
      gtclk_bufg => NlwRenamedSig_OI_GTPCLK_bufg,
      txsync_clk => txsync_clk,
      gt_usrclk => gt_usrclk,
      refclkout_bufg => NlwRenamedSig_OI_REFCLKOUT_bufg,
      gtreset => GTPRESET,
      pcie_reset => pcie_reset,
      refclk => REFCLK,
      clock_lock => NlwRenamedSig_OI_clock_lock,
      gt_usrclk2 => NlwRenamedSig_OI_core_clk,
      gt_dclk => NlwRenamedSig_OI_DEBUG(338),
      trn_lnk_up_n => trn_lnk_up_n,
      gt_rx_chanisaligned(7) => pipe_rxchanisaligned(7),
      gt_rx_chanisaligned(6) => pipe_rxchanisaligned(6),
      gt_rx_chanisaligned(5) => pipe_rxchanisaligned(5),
      gt_rx_chanisaligned(4) => pipe_rxchanisaligned(4),
      gt_rx_chanisaligned(3) => pipe_rxchanisaligned(3),
      gt_rx_chanisaligned(2) => pipe_rxchanisaligned(2),
      gt_rx_chanisaligned(1) => pipe_rxchanisaligned(1),
      gt_rx_chanisaligned(0) => pipe_rxchanisaligned(0),
      gt_rx_elec_idle(7) => pipe_rx_elec_idle(7),
      gt_rx_elec_idle(6) => pipe_rx_elec_idle(6),
      gt_rx_elec_idle(5) => pipe_rx_elec_idle(5),
      gt_rx_elec_idle(4) => pipe_rx_elec_idle(4),
      gt_rx_elec_idle(3) => pipe_rx_elec_idle(3),
      gt_rx_elec_idle(2) => pipe_rx_elec_idle(2),
      gt_rx_elec_idle(1) => pipe_rx_elec_idle(1),
      gt_rx_elec_idle(0) => pipe_rx_elec_idle(0),
      rxchanbondseq(7) => NLW_SIO_rxchanbondseq_7_UNCONNECTED,
      rxchanbondseq(6) => NLW_SIO_rxchanbondseq_6_UNCONNECTED,
      rxchanbondseq(5) => NLW_SIO_rxchanbondseq_5_UNCONNECTED,
      rxchanbondseq(4) => NLW_SIO_rxchanbondseq_4_UNCONNECTED,
      rxchanbondseq(3) => NLW_SIO_rxchanbondseq_3_UNCONNECTED,
      rxchanbondseq(2) => NLW_SIO_rxchanbondseq_2_UNCONNECTED,
      rxchanbondseq(1) => NLW_SIO_rxchanbondseq_1_UNCONNECTED,
      rxchanbondseq(0) => NLW_SIO_rxchanbondseq_0_UNCONNECTED,
      resetdone(7) => RESETDONE(7),
      resetdone(6) => RESETDONE(6),
      resetdone(5) => RESETDONE(5),
      resetdone(4) => RESETDONE(4),
      resetdone(3) => RESETDONE(3),
      resetdone(2) => RESETDONE(2),
      resetdone(1) => RESETDONE(1),
      resetdone(0) => RESETDONE(0),
      gt_rx_valid(7) => pipe_rx_valid(7),
      gt_rx_valid(6) => pipe_rx_valid(6),
      gt_rx_valid(5) => pipe_rx_valid(5),
      gt_rx_valid(4) => pipe_rx_valid(4),
      gt_rx_valid(3) => pipe_rx_valid(3),
      gt_rx_valid(2) => pipe_rx_valid(2),
      gt_rx_valid(1) => pipe_rx_valid(1),
      gt_rx_valid(0) => pipe_rx_valid(0),
      gt_rx_data_k(7) => pipe_rx_data_k(7),
      gt_rx_data_k(6) => pipe_rx_data_k(6),
      gt_rx_data_k(5) => pipe_rx_data_k(5),
      gt_rx_data_k(4) => pipe_rx_data_k(4),
      gt_rx_data_k(3) => pipe_rx_data_k(3),
      gt_rx_data_k(2) => pipe_rx_data_k(2),
      gt_rx_data_k(1) => pipe_rx_data_k(1),
      gt_rx_data_k(0) => pipe_rx_data_k(0),
      rxbyteisaligned(7) => NLW_SIO_rxbyteisaligned_7_UNCONNECTED,
      rxbyteisaligned(6) => NLW_SIO_rxbyteisaligned_6_UNCONNECTED,
      rxbyteisaligned(5) => NLW_SIO_rxbyteisaligned_5_UNCONNECTED,
      rxbyteisaligned(4) => NLW_SIO_rxbyteisaligned_4_UNCONNECTED,
      rxbyteisaligned(3) => NLW_SIO_rxbyteisaligned_3_UNCONNECTED,
      rxbyteisaligned(2) => NLW_SIO_rxbyteisaligned_2_UNCONNECTED,
      rxbyteisaligned(1) => NLW_SIO_rxbyteisaligned_1_UNCONNECTED,
      rxbyteisaligned(0) => NLW_SIO_rxbyteisaligned_0_UNCONNECTED,
      gt_tx_n(7) => TXN(7),
      gt_tx_n(6) => TXN(6),
      gt_tx_n(5) => TXN(5),
      gt_tx_n(4) => TXN(4),
      gt_tx_n(3) => TXN(3),
      gt_tx_n(2) => TXN(2),
      gt_tx_n(1) => TXN(1),
      gt_tx_n(0) => TXN(0),
      gt_rx_data(63) => pipe_rx_data(63),
      gt_rx_data(62) => pipe_rx_data(62),
      gt_rx_data(61) => pipe_rx_data(61),
      gt_rx_data(60) => pipe_rx_data(60),
      gt_rx_data(59) => pipe_rx_data(59),
      gt_rx_data(58) => pipe_rx_data(58),
      gt_rx_data(57) => pipe_rx_data(57),
      gt_rx_data(56) => pipe_rx_data(56),
      gt_rx_data(55) => pipe_rx_data(55),
      gt_rx_data(54) => pipe_rx_data(54),
      gt_rx_data(53) => pipe_rx_data(53),
      gt_rx_data(52) => pipe_rx_data(52),
      gt_rx_data(51) => pipe_rx_data(51),
      gt_rx_data(50) => pipe_rx_data(50),
      gt_rx_data(49) => pipe_rx_data(49),
      gt_rx_data(48) => pipe_rx_data(48),
      gt_rx_data(47) => pipe_rx_data(47),
      gt_rx_data(46) => pipe_rx_data(46),
      gt_rx_data(45) => pipe_rx_data(45),
      gt_rx_data(44) => pipe_rx_data(44),
      gt_rx_data(43) => pipe_rx_data(43),
      gt_rx_data(42) => pipe_rx_data(42),
      gt_rx_data(41) => pipe_rx_data(41),
      gt_rx_data(40) => pipe_rx_data(40),
      gt_rx_data(39) => pipe_rx_data(39),
      gt_rx_data(38) => pipe_rx_data(38),
      gt_rx_data(37) => pipe_rx_data(37),
      gt_rx_data(36) => pipe_rx_data(36),
      gt_rx_data(35) => pipe_rx_data(35),
      gt_rx_data(34) => pipe_rx_data(34),
      gt_rx_data(33) => pipe_rx_data(33),
      gt_rx_data(32) => pipe_rx_data(32),
      gt_rx_data(31) => pipe_rx_data(31),
      gt_rx_data(30) => pipe_rx_data(30),
      gt_rx_data(29) => pipe_rx_data(29),
      gt_rx_data(28) => pipe_rx_data(28),
      gt_rx_data(27) => pipe_rx_data(27),
      gt_rx_data(26) => pipe_rx_data(26),
      gt_rx_data(25) => pipe_rx_data(25),
      gt_rx_data(24) => pipe_rx_data(24),
      gt_rx_data(23) => pipe_rx_data(23),
      gt_rx_data(22) => pipe_rx_data(22),
      gt_rx_data(21) => pipe_rx_data(21),
      gt_rx_data(20) => pipe_rx_data(20),
      gt_rx_data(19) => pipe_rx_data(19),
      gt_rx_data(18) => pipe_rx_data(18),
      gt_rx_data(17) => pipe_rx_data(17),
      gt_rx_data(16) => pipe_rx_data(16),
      gt_rx_data(15) => pipe_rx_data(15),
      gt_rx_data(14) => pipe_rx_data(14),
      gt_rx_data(13) => pipe_rx_data(13),
      gt_rx_data(12) => pipe_rx_data(12),
      gt_rx_data(11) => pipe_rx_data(11),
      gt_rx_data(10) => pipe_rx_data(10),
      gt_rx_data(9) => pipe_rx_data(9),
      gt_rx_data(8) => pipe_rx_data(8),
      gt_rx_data(7) => pipe_rx_data(7),
      gt_rx_data(6) => pipe_rx_data(6),
      gt_rx_data(5) => pipe_rx_data(5),
      gt_rx_data(4) => pipe_rx_data(4),
      gt_rx_data(3) => pipe_rx_data(3),
      gt_rx_data(2) => pipe_rx_data(2),
      gt_rx_data(1) => pipe_rx_data(1),
      gt_rx_data(0) => pipe_rx_data(0),
      gt_tx_p(7) => TXP(7),
      gt_tx_p(6) => TXP(6),
      gt_tx_p(5) => TXP(5),
      gt_tx_p(4) => TXP(4),
      gt_tx_p(3) => TXP(3),
      gt_tx_p(2) => TXP(2),
      gt_tx_p(1) => TXP(1),
      gt_tx_p(0) => TXP(0),
      gt_rx_status(23) => pipe_rx_status(23),
      gt_rx_status(22) => pipe_rx_status(22),
      gt_rx_status(21) => pipe_rx_status(21),
      gt_rx_status(20) => pipe_rx_status(20),
      gt_rx_status(19) => pipe_rx_status(19),
      gt_rx_status(18) => pipe_rx_status(18),
      gt_rx_status(17) => pipe_rx_status(17),
      gt_rx_status(16) => pipe_rx_status(16),
      gt_rx_status(15) => pipe_rx_status(15),
      gt_rx_status(14) => pipe_rx_status(14),
      gt_rx_status(13) => pipe_rx_status(13),
      gt_rx_status(12) => pipe_rx_status(12),
      gt_rx_status(11) => pipe_rx_status(11),
      gt_rx_status(10) => pipe_rx_status(10),
      gt_rx_status(9) => pipe_rx_status(9),
      gt_rx_status(8) => pipe_rx_status(8),
      gt_rx_status(7) => pipe_rx_status(7),
      gt_rx_status(6) => pipe_rx_status(6),
      gt_rx_status(5) => pipe_rx_status(5),
      gt_rx_status(4) => pipe_rx_status(4),
      gt_rx_status(3) => pipe_rx_status(3),
      gt_rx_status(2) => pipe_rx_status(2),
      gt_rx_status(1) => pipe_rx_status(1),
      gt_rx_status(0) => pipe_rx_status(0),
      plllkdet_out(3) => PLLLKDET_OUT(3),
      plllkdet_out(2) => PLLLKDET_OUT(2),
      plllkdet_out(1) => PLLLKDET_OUT(1),
      plllkdet_out(0) => NlwRenamedSig_OI_PLLLKDET_OUT(0),
      gt_drdy(7) => gt_drdy(7),
      gt_drdy(6) => gt_drdy(6),
      gt_drdy(5) => gt_drdy(5),
      gt_drdy(4) => gt_drdy(4),
      gt_drdy(3) => gt_drdy(3),
      gt_drdy(2) => gt_drdy(2),
      gt_drdy(1) => gt_drdy(1),
      gt_drdy(0) => gt_drdy(0),
      gt_do(127) => gt_do(127),
      gt_do(126) => gt_do(126),
      gt_do(125) => gt_do(125),
      gt_do(124) => gt_do(124),
      gt_do(123) => gt_do(123),
      gt_do(122) => gt_do(122),
      gt_do(121) => gt_do(121),
      gt_do(120) => gt_do(120),
      gt_do(119) => gt_do(119),
      gt_do(118) => gt_do(118),
      gt_do(117) => gt_do(117),
      gt_do(116) => gt_do(116),
      gt_do(115) => gt_do(115),
      gt_do(114) => gt_do(114),
      gt_do(113) => gt_do(113),
      gt_do(112) => gt_do(112),
      gt_do(111) => gt_do(111),
      gt_do(110) => gt_do(110),
      gt_do(109) => gt_do(109),
      gt_do(108) => gt_do(108),
      gt_do(107) => gt_do(107),
      gt_do(106) => gt_do(106),
      gt_do(105) => gt_do(105),
      gt_do(104) => gt_do(104),
      gt_do(103) => gt_do(103),
      gt_do(102) => gt_do(102),
      gt_do(101) => gt_do(101),
      gt_do(100) => gt_do(100),
      gt_do(99) => gt_do(99),
      gt_do(98) => gt_do(98),
      gt_do(97) => gt_do(97),
      gt_do(96) => gt_do(96),
      gt_do(95) => gt_do(95),
      gt_do(94) => gt_do(94),
      gt_do(93) => gt_do(93),
      gt_do(92) => gt_do(92),
      gt_do(91) => gt_do(91),
      gt_do(90) => gt_do(90),
      gt_do(89) => gt_do(89),
      gt_do(88) => gt_do(88),
      gt_do(87) => gt_do(87),
      gt_do(86) => gt_do(86),
      gt_do(85) => gt_do(85),
      gt_do(84) => gt_do(84),
      gt_do(83) => gt_do(83),
      gt_do(82) => gt_do(82),
      gt_do(81) => gt_do(81),
      gt_do(80) => gt_do(80),
      gt_do(79) => gt_do(79),
      gt_do(78) => gt_do(78),
      gt_do(77) => gt_do(77),
      gt_do(76) => gt_do(76),
      gt_do(75) => gt_do(75),
      gt_do(74) => gt_do(74),
      gt_do(73) => gt_do(73),
      gt_do(72) => gt_do(72),
      gt_do(71) => gt_do(71),
      gt_do(70) => gt_do(70),
      gt_do(69) => gt_do(69),
      gt_do(68) => gt_do(68),
      gt_do(67) => gt_do(67),
      gt_do(66) => gt_do(66),
      gt_do(65) => gt_do(65),
      gt_do(64) => gt_do(64),
      gt_do(63) => gt_do(63),
      gt_do(62) => gt_do(62),
      gt_do(61) => gt_do(61),
      gt_do(60) => gt_do(60),
      gt_do(59) => gt_do(59),
      gt_do(58) => gt_do(58),
      gt_do(57) => gt_do(57),
      gt_do(56) => gt_do(56),
      gt_do(55) => gt_do(55),
      gt_do(54) => gt_do(54),
      gt_do(53) => gt_do(53),
      gt_do(52) => gt_do(52),
      gt_do(51) => gt_do(51),
      gt_do(50) => gt_do(50),
      gt_do(49) => gt_do(49),
      gt_do(48) => gt_do(48),
      gt_do(47) => gt_do(47),
      gt_do(46) => gt_do(46),
      gt_do(45) => gt_do(45),
      gt_do(44) => gt_do(44),
      gt_do(43) => gt_do(43),
      gt_do(42) => gt_do(42),
      gt_do(41) => gt_do(41),
      gt_do(40) => gt_do(40),
      gt_do(39) => gt_do(39),
      gt_do(38) => gt_do(38),
      gt_do(37) => gt_do(37),
      gt_do(36) => gt_do(36),
      gt_do(35) => gt_do(35),
      gt_do(34) => gt_do(34),
      gt_do(33) => gt_do(33),
      gt_do(32) => gt_do(32),
      gt_do(31) => gt_do(31),
      gt_do(30) => gt_do(30),
      gt_do(29) => gt_do(29),
      gt_do(28) => gt_do(28),
      gt_do(27) => gt_do(27),
      gt_do(26) => gt_do(26),
      gt_do(25) => gt_do(25),
      gt_do(24) => gt_do(24),
      gt_do(23) => gt_do(23),
      gt_do(22) => gt_do(22),
      gt_do(21) => gt_do(21),
      gt_do(20) => gt_do(20),
      gt_do(19) => gt_do(19),
      gt_do(18) => gt_do(18),
      gt_do(17) => gt_do(17),
      gt_do(16) => gt_do(16),
      gt_do(15) => gt_do(15),
      gt_do(14) => gt_do(14),
      gt_do(13) => gt_do(13),
      gt_do(12) => gt_do(12),
      gt_do(11) => gt_do(11),
      gt_do(10) => gt_do(10),
      gt_do(9) => gt_do(9),
      gt_do(8) => gt_do(8),
      gt_do(7) => gt_do(7),
      gt_do(6) => gt_do(6),
      gt_do(5) => gt_do(5),
      gt_do(4) => gt_do(4),
      gt_do(3) => gt_do(3),
      gt_do(2) => gt_do(2),
      gt_do(1) => gt_do(1),
      gt_do(0) => gt_do(0),
      gt_rx_phy_status(7) => pipe_rx_phy_status(7),
      gt_rx_phy_status(6) => pipe_rx_phy_status(6),
      gt_rx_phy_status(5) => pipe_rx_phy_status(5),
      gt_rx_phy_status(4) => pipe_rx_phy_status(4),
      gt_rx_phy_status(3) => pipe_rx_phy_status(3),
      gt_rx_phy_status(2) => pipe_rx_phy_status(2),
      gt_rx_phy_status(1) => pipe_rx_phy_status(1),
      gt_rx_phy_status(0) => pipe_rx_phy_status(0),
      gt_tx_elec_idle(7) => pipe_tx_elec_idle_l7,
      gt_tx_elec_idle(6) => pipe_tx_elec_idle_l6,
      gt_tx_elec_idle(5) => pipe_tx_elec_idle_l5,
      gt_tx_elec_idle(4) => pipe_tx_elec_idle_l4,
      gt_tx_elec_idle(3) => pipe_tx_elec_idle_l3,
      gt_tx_elec_idle(2) => pipe_tx_elec_idle_l2,
      gt_tx_elec_idle(1) => pipe_tx_elec_idle_l1,
      gt_tx_elec_idle(0) => pipe_tx_elec_idle_l0,
      gt_rx_present(7) => usrclk,
      gt_rx_present(6) => usrclk,
      gt_rx_present(5) => usrclk,
      gt_rx_present(4) => usrclk,
      gt_rx_present(3) => usrclk,
      gt_rx_present(2) => usrclk,
      gt_rx_present(1) => usrclk,
      gt_rx_present(0) => usrclk,
      gt_tx_data_k(7) => pipe_tx_data_k_l7,
      gt_tx_data_k(6) => pipe_tx_data_k_l6,
      gt_tx_data_k(5) => pipe_tx_data_k_l5,
      gt_tx_data_k(4) => pipe_tx_data_k_l4,
      gt_tx_data_k(3) => pipe_tx_data_k_l3,
      gt_tx_data_k(2) => pipe_tx_data_k_l2,
      gt_tx_data_k(1) => pipe_tx_data_k_l1,
      gt_tx_data_k(0) => pipe_tx_data_k_l0,
      gt_den(7) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(6) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(5) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(4) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(3) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(2) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_den(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_rx_n(7) => RXN(7),
      gt_rx_n(6) => RXN(6),
      gt_rx_n(5) => RXN(5),
      gt_rx_n(4) => RXN(4),
      gt_rx_n(3) => RXN(3),
      gt_rx_n(2) => RXN(2),
      gt_rx_n(1) => RXN(1),
      gt_rx_n(0) => RXN(0),
      gt_rx_p(7) => RXP(7),
      gt_rx_p(6) => RXP(6),
      gt_rx_p(5) => RXP(5),
      gt_rx_p(4) => RXP(4),
      gt_rx_p(3) => RXP(3),
      gt_rx_p(2) => RXP(2),
      gt_rx_p(1) => RXP(1),
      gt_rx_p(0) => RXP(0),
      gt_deskew_lanes(7) => pipe_deskew_lanes_l7,
      gt_deskew_lanes(6) => pipe_deskew_lanes_l6,
      gt_deskew_lanes(5) => pipe_deskew_lanes_l5,
      gt_deskew_lanes(4) => pipe_deskew_lanes_l4,
      gt_deskew_lanes(3) => pipe_deskew_lanes_l3,
      gt_deskew_lanes(2) => pipe_deskew_lanes_l2,
      gt_deskew_lanes(1) => pipe_deskew_lanes_l1,
      gt_deskew_lanes(0) => pipe_deskew_lanes_l0,
      gt_dwen(7) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(6) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(5) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(4) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(3) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(2) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_dwen(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_daddr(55) => gt_daddr(55),
      gt_daddr(54) => gt_daddr(54),
      gt_daddr(53) => gt_daddr(53),
      gt_daddr(52) => gt_daddr(52),
      gt_daddr(51) => gt_daddr(51),
      gt_daddr(50) => gt_daddr(50),
      gt_daddr(49) => gt_daddr(49),
      gt_daddr(48) => gt_daddr(48),
      gt_daddr(47) => gt_daddr(47),
      gt_daddr(46) => gt_daddr(46),
      gt_daddr(45) => gt_daddr(45),
      gt_daddr(44) => gt_daddr(44),
      gt_daddr(43) => gt_daddr(43),
      gt_daddr(42) => gt_daddr(42),
      gt_daddr(41) => gt_daddr(41),
      gt_daddr(40) => gt_daddr(40),
      gt_daddr(39) => gt_daddr(39),
      gt_daddr(38) => gt_daddr(38),
      gt_daddr(37) => gt_daddr(37),
      gt_daddr(36) => gt_daddr(36),
      gt_daddr(35) => gt_daddr(35),
      gt_daddr(34) => gt_daddr(34),
      gt_daddr(33) => gt_daddr(33),
      gt_daddr(32) => gt_daddr(32),
      gt_daddr(31) => gt_daddr(31),
      gt_daddr(30) => gt_daddr(30),
      gt_daddr(29) => gt_daddr(29),
      gt_daddr(28) => gt_daddr(28),
      gt_daddr(27) => gt_daddr(27),
      gt_daddr(26) => gt_daddr(26),
      gt_daddr(25) => gt_daddr(25),
      gt_daddr(24) => gt_daddr(24),
      gt_daddr(23) => gt_daddr(23),
      gt_daddr(22) => gt_daddr(22),
      gt_daddr(21) => gt_daddr(21),
      gt_daddr(20) => gt_daddr(20),
      gt_daddr(19) => gt_daddr(19),
      gt_daddr(18) => gt_daddr(18),
      gt_daddr(17) => gt_daddr(17),
      gt_daddr(16) => gt_daddr(16),
      gt_daddr(15) => gt_daddr(15),
      gt_daddr(14) => gt_daddr(14),
      gt_daddr(13) => gt_daddr(13),
      gt_daddr(12) => gt_daddr(12),
      gt_daddr(11) => gt_daddr(11),
      gt_daddr(10) => gt_daddr(10),
      gt_daddr(9) => gt_daddr(9),
      gt_daddr(8) => gt_daddr(8),
      gt_daddr(7) => gt_daddr(7),
      gt_daddr(6) => gt_daddr(6),
      gt_daddr(5) => gt_daddr(5),
      gt_daddr(4) => gt_daddr(4),
      gt_daddr(3) => gt_daddr(3),
      gt_daddr(2) => gt_daddr(2),
      gt_daddr(1) => gt_daddr(1),
      gt_daddr(0) => gt_daddr(0),
      gt_tx_data(63) => pipe_tx_data_l7(7),
      gt_tx_data(62) => pipe_tx_data_l7(6),
      gt_tx_data(61) => pipe_tx_data_l7(5),
      gt_tx_data(60) => pipe_tx_data_l7(4),
      gt_tx_data(59) => pipe_tx_data_l7(3),
      gt_tx_data(58) => pipe_tx_data_l7(2),
      gt_tx_data(57) => pipe_tx_data_l7(1),
      gt_tx_data(56) => pipe_tx_data_l7(0),
      gt_tx_data(55) => pipe_tx_data_l6(7),
      gt_tx_data(54) => pipe_tx_data_l6(6),
      gt_tx_data(53) => pipe_tx_data_l6(5),
      gt_tx_data(52) => pipe_tx_data_l6(4),
      gt_tx_data(51) => pipe_tx_data_l6(3),
      gt_tx_data(50) => pipe_tx_data_l6(2),
      gt_tx_data(49) => pipe_tx_data_l6(1),
      gt_tx_data(48) => pipe_tx_data_l6(0),
      gt_tx_data(47) => pipe_tx_data_l5(7),
      gt_tx_data(46) => pipe_tx_data_l5(6),
      gt_tx_data(45) => pipe_tx_data_l5(5),
      gt_tx_data(44) => pipe_tx_data_l5(4),
      gt_tx_data(43) => pipe_tx_data_l5(3),
      gt_tx_data(42) => pipe_tx_data_l5(2),
      gt_tx_data(41) => pipe_tx_data_l5(1),
      gt_tx_data(40) => pipe_tx_data_l5(0),
      gt_tx_data(39) => pipe_tx_data_l4(7),
      gt_tx_data(38) => pipe_tx_data_l4(6),
      gt_tx_data(37) => pipe_tx_data_l4(5),
      gt_tx_data(36) => pipe_tx_data_l4(4),
      gt_tx_data(35) => pipe_tx_data_l4(3),
      gt_tx_data(34) => pipe_tx_data_l4(2),
      gt_tx_data(33) => pipe_tx_data_l4(1),
      gt_tx_data(32) => pipe_tx_data_l4(0),
      gt_tx_data(31) => pipe_tx_data_l3(7),
      gt_tx_data(30) => pipe_tx_data_l3(6),
      gt_tx_data(29) => pipe_tx_data_l3(5),
      gt_tx_data(28) => pipe_tx_data_l3(4),
      gt_tx_data(27) => pipe_tx_data_l3(3),
      gt_tx_data(26) => pipe_tx_data_l3(2),
      gt_tx_data(25) => pipe_tx_data_l3(1),
      gt_tx_data(24) => pipe_tx_data_l3(0),
      gt_tx_data(23) => pipe_tx_data_l2(7),
      gt_tx_data(22) => pipe_tx_data_l2(6),
      gt_tx_data(21) => pipe_tx_data_l2(5),
      gt_tx_data(20) => pipe_tx_data_l2(4),
      gt_tx_data(19) => pipe_tx_data_l2(3),
      gt_tx_data(18) => pipe_tx_data_l2(2),
      gt_tx_data(17) => pipe_tx_data_l2(1),
      gt_tx_data(16) => pipe_tx_data_l2(0),
      gt_tx_data(15) => pipe_tx_data_l1(7),
      gt_tx_data(14) => pipe_tx_data_l1(6),
      gt_tx_data(13) => pipe_tx_data_l1(5),
      gt_tx_data(12) => pipe_tx_data_l1(4),
      gt_tx_data(11) => pipe_tx_data_l1(3),
      gt_tx_data(10) => pipe_tx_data_l1(2),
      gt_tx_data(9) => pipe_tx_data_l1(1),
      gt_tx_data(8) => pipe_tx_data_l1(0),
      gt_tx_data(7) => pipe_tx_data_l0(7),
      gt_tx_data(6) => pipe_tx_data_l0(6),
      gt_tx_data(5) => pipe_tx_data_l0(5),
      gt_tx_data(4) => pipe_tx_data_l0(4),
      gt_tx_data(3) => pipe_tx_data_l0(3),
      gt_tx_data(2) => pipe_tx_data_l0(2),
      gt_tx_data(1) => pipe_tx_data_l0(1),
      gt_tx_data(0) => pipe_tx_data_l0(0),
      gt_txbuffctrl_0(2) => usrclk,
      gt_txbuffctrl_0(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_txbuffctrl_0(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_txbuffctrl_1(2) => usrclk,
      gt_txbuffctrl_1(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_txbuffctrl_1(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_tx_compliance(7) => pipe_tx_compliance_l7,
      gt_tx_compliance(6) => pipe_tx_compliance_l6,
      gt_tx_compliance(5) => pipe_tx_compliance_l5,
      gt_tx_compliance(4) => pipe_tx_compliance_l4,
      gt_tx_compliance(3) => pipe_tx_compliance_l3,
      gt_tx_compliance(2) => pipe_tx_compliance_l2,
      gt_tx_compliance(1) => pipe_tx_compliance_l1,
      gt_tx_compliance(0) => pipe_tx_compliance_l0,
      gt_txdiffctrl_0(2) => usrclk,
      gt_txdiffctrl_0(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_txdiffctrl_0(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_txdiffctrl_1(2) => usrclk,
      gt_txdiffctrl_1(1) => NlwRenamedSig_OI_DEBUG(338),
      gt_txdiffctrl_1(0) => NlwRenamedSig_OI_DEBUG(338),
      gt_pipe_reset(7) => pipe_reset_l7,
      gt_pipe_reset(6) => pipe_reset_l6,
      gt_pipe_reset(5) => pipe_reset_l5,
      gt_pipe_reset(4) => pipe_reset_l4,
      gt_pipe_reset(3) => pipe_reset_l3,
      gt_pipe_reset(2) => pipe_reset_l2,
      gt_pipe_reset(1) => pipe_reset_l1,
      gt_pipe_reset(0) => pipe_reset_l0,
      gt_tx_detect_rx_loopback(7) => pipe_tx_detect_rx_loopback_l7,
      gt_tx_detect_rx_loopback(6) => pipe_tx_detect_rx_loopback_l6,
      gt_tx_detect_rx_loopback(5) => pipe_tx_detect_rx_loopback_l5,
      gt_tx_detect_rx_loopback(4) => pipe_tx_detect_rx_loopback_l4,
      gt_tx_detect_rx_loopback(3) => pipe_tx_detect_rx_loopback_l3,
      gt_tx_detect_rx_loopback(2) => pipe_tx_detect_rx_loopback_l2,
      gt_tx_detect_rx_loopback(1) => pipe_tx_detect_rx_loopback_l1,
      gt_tx_detect_rx_loopback(0) => pipe_tx_detect_rx_loopback_l0,
      gt_txpreemphesis_0(2) => usrclk,
      gt_txpreemphesis_0(1) => usrclk,
      gt_txpreemphesis_0(0) => usrclk,
      gt_txpreemphesis_1(2) => usrclk,
      gt_txpreemphesis_1(1) => usrclk,
      gt_txpreemphesis_1(0) => usrclk,
      gt_di(127) => gt_di(127),
      gt_di(126) => gt_di(126),
      gt_di(125) => gt_di(125),
      gt_di(124) => gt_di(124),
      gt_di(123) => gt_di(123),
      gt_di(122) => gt_di(122),
      gt_di(121) => gt_di(121),
      gt_di(120) => gt_di(120),
      gt_di(119) => gt_di(119),
      gt_di(118) => gt_di(118),
      gt_di(117) => gt_di(117),
      gt_di(116) => gt_di(116),
      gt_di(115) => gt_di(115),
      gt_di(114) => gt_di(114),
      gt_di(113) => gt_di(113),
      gt_di(112) => gt_di(112),
      gt_di(111) => gt_di(111),
      gt_di(110) => gt_di(110),
      gt_di(109) => gt_di(109),
      gt_di(108) => gt_di(108),
      gt_di(107) => gt_di(107),
      gt_di(106) => gt_di(106),
      gt_di(105) => gt_di(105),
      gt_di(104) => gt_di(104),
      gt_di(103) => gt_di(103),
      gt_di(102) => gt_di(102),
      gt_di(101) => gt_di(101),
      gt_di(100) => gt_di(100),
      gt_di(99) => gt_di(99),
      gt_di(98) => gt_di(98),
      gt_di(97) => gt_di(97),
      gt_di(96) => gt_di(96),
      gt_di(95) => gt_di(95),
      gt_di(94) => gt_di(94),
      gt_di(93) => gt_di(93),
      gt_di(92) => gt_di(92),
      gt_di(91) => gt_di(91),
      gt_di(90) => gt_di(90),
      gt_di(89) => gt_di(89),
      gt_di(88) => gt_di(88),
      gt_di(87) => gt_di(87),
      gt_di(86) => gt_di(86),
      gt_di(85) => gt_di(85),
      gt_di(84) => gt_di(84),
      gt_di(83) => gt_di(83),
      gt_di(82) => gt_di(82),
      gt_di(81) => gt_di(81),
      gt_di(80) => gt_di(80),
      gt_di(79) => gt_di(79),
      gt_di(78) => gt_di(78),
      gt_di(77) => gt_di(77),
      gt_di(76) => gt_di(76),
      gt_di(75) => gt_di(75),
      gt_di(74) => gt_di(74),
      gt_di(73) => gt_di(73),
      gt_di(72) => gt_di(72),
      gt_di(71) => gt_di(71),
      gt_di(70) => gt_di(70),
      gt_di(69) => gt_di(69),
      gt_di(68) => gt_di(68),
      gt_di(67) => gt_di(67),
      gt_di(66) => gt_di(66),
      gt_di(65) => gt_di(65),
      gt_di(64) => gt_di(64),
      gt_di(63) => gt_di(63),
      gt_di(62) => gt_di(62),
      gt_di(61) => gt_di(61),
      gt_di(60) => gt_di(60),
      gt_di(59) => gt_di(59),
      gt_di(58) => gt_di(58),
      gt_di(57) => gt_di(57),
      gt_di(56) => gt_di(56),
      gt_di(55) => gt_di(55),
      gt_di(54) => gt_di(54),
      gt_di(53) => gt_di(53),
      gt_di(52) => gt_di(52),
      gt_di(51) => gt_di(51),
      gt_di(50) => gt_di(50),
      gt_di(49) => gt_di(49),
      gt_di(48) => gt_di(48),
      gt_di(47) => gt_di(47),
      gt_di(46) => gt_di(46),
      gt_di(45) => gt_di(45),
      gt_di(44) => gt_di(44),
      gt_di(43) => gt_di(43),
      gt_di(42) => gt_di(42),
      gt_di(41) => gt_di(41),
      gt_di(40) => gt_di(40),
      gt_di(39) => gt_di(39),
      gt_di(38) => gt_di(38),
      gt_di(37) => gt_di(37),
      gt_di(36) => gt_di(36),
      gt_di(35) => gt_di(35),
      gt_di(34) => gt_di(34),
      gt_di(33) => gt_di(33),
      gt_di(32) => gt_di(32),
      gt_di(31) => gt_di(31),
      gt_di(30) => gt_di(30),
      gt_di(29) => gt_di(29),
      gt_di(28) => gt_di(28),
      gt_di(27) => gt_di(27),
      gt_di(26) => gt_di(26),
      gt_di(25) => gt_di(25),
      gt_di(24) => gt_di(24),
      gt_di(23) => gt_di(23),
      gt_di(22) => gt_di(22),
      gt_di(21) => gt_di(21),
      gt_di(20) => gt_di(20),
      gt_di(19) => gt_di(19),
      gt_di(18) => gt_di(18),
      gt_di(17) => gt_di(17),
      gt_di(16) => gt_di(16),
      gt_di(15) => gt_di(15),
      gt_di(14) => gt_di(14),
      gt_di(13) => gt_di(13),
      gt_di(12) => gt_di(12),
      gt_di(11) => gt_di(11),
      gt_di(10) => gt_di(10),
      gt_di(9) => gt_di(9),
      gt_di(8) => gt_di(8),
      gt_di(7) => gt_di(7),
      gt_di(6) => gt_di(6),
      gt_di(5) => gt_di(5),
      gt_di(4) => gt_di(4),
      gt_di(3) => gt_di(3),
      gt_di(2) => gt_di(2),
      gt_di(1) => gt_di(1),
      gt_di(0) => gt_di(0),
      gt_power_down(15) => pipe_power_down_l7(1),
      gt_power_down(14) => pipe_power_down_l7(0),
      gt_power_down(13) => pipe_power_down_l6(1),
      gt_power_down(12) => pipe_power_down_l6(0),
      gt_power_down(11) => pipe_power_down_l5(1),
      gt_power_down(10) => pipe_power_down_l5(0),
      gt_power_down(9) => pipe_power_down_l4(1),
      gt_power_down(8) => pipe_power_down_l4(0),
      gt_power_down(7) => pipe_power_down_l3(1),
      gt_power_down(6) => pipe_power_down_l3(0),
      gt_power_down(5) => pipe_power_down_l2(1),
      gt_power_down(4) => pipe_power_down_l2(0),
      gt_power_down(3) => pipe_power_down_l1(1),
      gt_power_down(2) => pipe_power_down_l1(0),
      gt_power_down(1) => pipe_power_down_l0(1),
      gt_power_down(0) => pipe_power_down_l0(0),
      gt_rx_polarity(7) => pipe_rx_polarity_l7,
      gt_rx_polarity(6) => pipe_rx_polarity_l6,
      gt_rx_polarity(5) => pipe_rx_polarity_l5,
      gt_rx_polarity(4) => pipe_rx_polarity_l4,
      gt_rx_polarity(3) => pipe_rx_polarity_l3,
      gt_rx_polarity(2) => pipe_rx_polarity_l2,
      gt_rx_polarity(1) => pipe_rx_polarity_l1,
      gt_rx_polarity(0) => pipe_rx_polarity_l0
    );
  d_user_reset_n_inv1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => user_reset_n,
      I1 => pcie_reset,
      O => d_user_reset_n_inv
    );
  Mcount_reg_ltssm_reset_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => reg_ltssm_reset(1),
      I1 => reg_ltssm_reset(0),
      O => Result(1)
    );
  Mcount_reg_ltssm_reset_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => reg_ltssm_reset(0),
      I1 => reg_ltssm_reset(2),
      I2 => reg_ltssm_reset(1),
      O => Result(2)
    );
  Mcount_reg_ltssm_reset_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => reg_ltssm_reset(0),
      I1 => reg_ltssm_reset(3),
      I2 => reg_ltssm_reset(1),
      I3 => reg_ltssm_reset(2),
      O => Result(3)
    );
  reg_ltssm_reset_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => reg_enable_ltssm_reset_18589,
      I1 => reg_ltssm_reset(3),
      I2 => pipe_rx_elec_idle(0),
      O => reg_ltssm_reset_and0000
    );
  reg_enable_ltssm_reset_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFF00020000"
    )
    port map (
      I0 => pipe_rx_elec_idle(0),
      I1 => reg_l0_ltssm_state_internal(0),
      I2 => reg_l0_ltssm_state_internal(2),
      I3 => reg_l0_ltssm_state_internal(3),
      I4 => reg_l0_ltssm_state_internal(1),
      I5 => reg_ltssm_reset(3),
      O => reg_enable_ltssm_reset_not0001
    );
  trn_reset_n1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => NlwRenamedSig_OI_clock_lock,
      I1 => NlwRenamedSig_OI_PLLLKDET_OUT(0),
      I2 => user_reset_workaround_n,
      O => trn_reset_n
    );
  trn_reset_n21 : LUT5
    generic map(
      INIT => X"0C0C080C"
    )
    port map (
      I0 => pipe_rx_elec_idle(0),
      I1 => user_reset_n,
      I2 => pcie_reset,
      I3 => reg_enable_ltssm_reset_18589,
      I4 => reg_ltssm_reset(3),
      O => user_reset_workaround_n
    );
  clocking_i_not00001_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_PLLLKDET_OUT(0),
      O => clocking_i_not0000
    );
  reg_enable_ltssm_reset_mux00001_INV_0 : INV
    port map (
      I => reg_ltssm_reset(3),
      O => reg_enable_ltssm_reset_mux0000
    );
  Mcount_reg_ltssm_reset_xor_0_11_INV_0 : INV
    port map (
      I => reg_ltssm_reset(0),
      O => Result(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity extend_clk_extend_clk is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst_n : in STD_LOGIC := 'X'; 
    l0_rx_mac_link_error_retime : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    l0_dll_error_vector_retime : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end extend_clk_extend_clk;

architecture STRUCTURE of extend_clk_extend_clk is
  signal NlwRenamedSignal_l0_dll_error_vector_retime : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal NlwRenamedSignal_l0_rx_mac_link_error_retime : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  l0_rx_mac_link_error_retime(1) <= NlwRenamedSignal_l0_rx_mac_link_error_retime(0);
  l0_rx_mac_link_error_retime(0) <= NlwRenamedSignal_l0_rx_mac_link_error_retime(0);
  l0_dll_error_vector_retime(6) <= NlwRenamedSignal_l0_dll_error_vector_retime(6);
  l0_dll_error_vector_retime(5) <= NlwRenamedSignal_l0_dll_error_vector_retime(5);
  l0_dll_error_vector_retime(4) <= NlwRenamedSignal_l0_dll_error_vector_retime(4);
  l0_dll_error_vector_retime(3) <= NlwRenamedSignal_l0_dll_error_vector_retime(3);
  l0_dll_error_vector_retime(2) <= NlwRenamedSignal_l0_dll_error_vector_retime(2);
  l0_dll_error_vector_retime(1) <= NlwRenamedSignal_l0_dll_error_vector_retime(1);
  l0_dll_error_vector_retime(0) <= NlwRenamedSignal_l0_dll_error_vector_retime(0);
  NlwRenamedSignal_l0_dll_error_vector_retime(6) <= l0_dll_error_vector(6);
  NlwRenamedSignal_l0_dll_error_vector_retime(5) <= l0_dll_error_vector(5);
  NlwRenamedSignal_l0_dll_error_vector_retime(4) <= l0_dll_error_vector(4);
  NlwRenamedSignal_l0_dll_error_vector_retime(3) <= l0_dll_error_vector(3);
  NlwRenamedSignal_l0_dll_error_vector_retime(2) <= l0_dll_error_vector(2);
  NlwRenamedSignal_l0_dll_error_vector_retime(1) <= l0_dll_error_vector(1);
  NlwRenamedSignal_l0_dll_error_vector_retime(0) <= l0_dll_error_vector(0);
  NlwRenamedSignal_l0_rx_mac_link_error_retime(0) <= l0_rx_mac_link_error(0);

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_ep_top is
  port (
    trn_rsrc_rdy_n : out STD_LOGIC; 
    trn_terrfwd_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    trn_rerrfwd_n : out STD_LOGIC; 
    cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
    cfg_to_turnoff_n : out STD_LOGIC; 
    trn_rnp_ok_n : in STD_LOGIC := 'X'; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    cfg_rd_en_n : in STD_LOGIC := 'X'; 
    refclkout : out STD_LOGIC; 
    cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    trn_rsof_n : out STD_LOGIC; 
    cfg_rd_wr_done_n : out STD_LOGIC; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    trn_clk : out STD_LOGIC; 
    cfg_err_locked_n : in STD_LOGIC := 'X'; 
    cfg_trn_pending_n : in STD_LOGIC := 'X'; 
    trn_reset_n : out STD_LOGIC; 
    trn_rsrc_dsc_n : out STD_LOGIC; 
    fast_train_simulation_only : in STD_LOGIC := 'X'; 
    cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_msienable : out STD_LOGIC; 
    trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    cfg_err_ur_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_n : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    cfg_wr_en_n : in STD_LOGIC := 'X'; 
    cfg_pm_wake_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_rdy_n : out STD_LOGIC; 
    cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    cfg_err_posted_n : in STD_LOGIC := 'X'; 
    gt_dclk : in STD_LOGIC := 'X'; 
    cfg_err_cpl_rdy_n : out STD_LOGIC; 
    sys_reset_n : in STD_LOGIC := 'X'; 
    cfg_err_cor_n : in STD_LOGIC := 'X'; 
    trn_reof_n : out STD_LOGIC; 
    sys_clk : in STD_LOGIC := 'X'; 
    cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
    trn_lnk_up_n : out STD_LOGIC; 
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
    trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    cfg_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end pcie_ep_top;

architecture STRUCTURE of pcie_ep_top is
  component extend_clk_extend_clk
    port (
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      l0_rx_mac_link_error_retime : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      l0_dll_error_vector_retime : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  component pcie_top_wrapper
    port (
      llk_tx_src_rdy_n : in STD_LOGIC := 'X'; 
      l0_stats_tlp_received : out STD_LOGIC; 
      l0_set_user_system_error : in STD_LOGIC := 'X'; 
      l0_stats_os_transmitted : out STD_LOGIC; 
      llk_rx_eof_n : out STD_LOGIC; 
      l0_set_unexpected_completion_uncorr_error : in STD_LOGIC := 'X'; 
      l0_set_user_received_master_abort : in STD_LOGIC := 'X'; 
      llk_rx_src_rdy_n : out STD_LOGIC; 
      l0_set_detected_nonfatal_error : in STD_LOGIC := 'X'; 
      serr_enable : out STD_LOGIC; 
      llk_rx_dst_cont_req_n : in STD_LOGIC := 'X'; 
      l0_mac_rx_l0s_state : out STD_LOGIC; 
      l0_set_completer_abort_error : in STD_LOGIC := 'X'; 
      l0_mac_entered_l0 : out STD_LOGIC; 
      mgmt_rden : in STD_LOGIC := 'X'; 
      crm_link_rst_n : in STD_LOGIC := 'X'; 
      l0_cfg_loopback_master : in STD_LOGIC := 'X'; 
      l0_set_detected_corr_error : in STD_LOGIC := 'X'; 
      crm_nvrst_n : in STD_LOGIC := 'X'; 
      crm_do_hot_reset_n : out STD_LOGIC; 
      mgmt_wren : in STD_LOGIC := 'X'; 
      bus_master_enable : out STD_LOGIC; 
      l0_msi_enable0 : out STD_LOGIC; 
      llk_tx_sop_n : in STD_LOGIC := 'X'; 
      mgmt_rdy : out STD_LOGIC; 
      user_clk : out STD_LOGIC; 
      io_space_enable : out STD_LOGIC; 
      l0_pwr_turn_off_req : out STD_LOGIC; 
      parity_error_response : out STD_LOGIC; 
      llk_rx_dst_req_n : in STD_LOGIC := 'X'; 
      crm_urst_n : in STD_LOGIC := 'X'; 
      llk_rx_eop_n : out STD_LOGIC; 
      llk_rx_src_last_req_n : out STD_LOGIC; 
      l0_pme_req_in : in STD_LOGIC := 'X'; 
      GTPRESET : in STD_LOGIC := 'X'; 
      REFCLKOUT_bufg : out STD_LOGIC; 
      l0_stats_cfg_other_received : out STD_LOGIC; 
      interrupt_disable : out STD_LOGIC; 
      llk_rx_sof_n : out STD_LOGIC; 
      crm_mac_rst_n : in STD_LOGIC := 'X'; 
      GTPCLK_bufg : out STD_LOGIC; 
      l0_mac_link_training : out STD_LOGIC; 
      l0_set_user_master_data_parity : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : out STD_LOGIC; 
      l0_mac_link_up : out STD_LOGIC; 
      crm_user_cfg_rst_n : in STD_LOGIC := 'X'; 
      l0_set_user_signalled_target_abort : in STD_LOGIC := 'X'; 
      l0_set_user_detected_parity_error : in STD_LOGIC := 'X'; 
      ur_reporting_enable : out STD_LOGIC; 
      l0_set_detected_fatal_error : in STD_LOGIC := 'X'; 
      l0_cfg_loopback_ack : out STD_LOGIC; 
      llk_tx_src_dsc_n : in STD_LOGIC := 'X'; 
      l0_set_completion_timeout_corr_error : in STD_LOGIC := 'X'; 
      REFCLK : in STD_LOGIC := 'X'; 
      clock_lock : out STD_LOGIC; 
      l0_transactions_pending : in STD_LOGIC := 'X'; 
      l0_stats_os_received : out STD_LOGIC; 
      l0_stats_dllp_transmitted : out STD_LOGIC; 
      l0_legacy_int_funct0 : in STD_LOGIC := 'X'; 
      l0_first_cfg_write_occurred : out STD_LOGIC; 
      core_clk : out STD_LOGIC; 
      fast_train_simulation_only : in STD_LOGIC := 'X'; 
      llk_tx_eof_n : in STD_LOGIC := 'X'; 
      llk_tx_dst_rdy_n : out STD_LOGIC; 
      llk_rx_sop_n : out STD_LOGIC; 
      user_reset_n : in STD_LOGIC := 'X'; 
      l0_stats_dllp_received : out STD_LOGIC; 
      l0_stats_cfg_received : out STD_LOGIC; 
      l0_stats_tlp_transmitted : out STD_LOGIC; 
      l0_pme_ack : out STD_LOGIC; 
      crm_pwr_soft_reset_n : out STD_LOGIC; 
      l0_pwr_tx_l0s_state : out STD_LOGIC; 
      l0_set_unexpected_completion_corr_error : in STD_LOGIC := 'X'; 
      mem_space_enable : out STD_LOGIC; 
      l0_pwr_l23_ready_state : out STD_LOGIC; 
      mgmt_reset_delay_n : in STD_LOGIC := 'X'; 
      l0_set_unsupported_request_other_error : in STD_LOGIC := 'X'; 
      l0_set_unsupported_request_nonposted_error : in STD_LOGIC := 'X'; 
      l0_set_completion_timeout_uncorr_error : in STD_LOGIC := 'X'; 
      gt_dclk : in STD_LOGIC := 'X'; 
      crm_mgmt_rst_n : in STD_LOGIC := 'X'; 
      l0_set_user_received_target_abort : in STD_LOGIC := 'X'; 
      l0_stats_cfg_other_transmitted : out STD_LOGIC; 
      llk_tx_eop_n : in STD_LOGIC := 'X'; 
      compliance_avoid : in STD_LOGIC := 'X'; 
      l0_mac_new_state_ack : out STD_LOGIC; 
      llk_tx_sof_n : in STD_LOGIC := 'X'; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      l0_pwr_state0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_rx_ch_posted_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_non_posted_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      DEBUG : out STD_LOGIC_VECTOR ( 338 downto 0 ); 
      llk_rx_ch_non_posted_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      l0_ltssm_state : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      llk_rx_ch_completion_available_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_valid_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      RESETDONE : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_preferred_type : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      l0_dl_up_down : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tc_status : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      mgmt_pso : out STD_LOGIC_VECTOR ( 16 downto 0 ); 
      l0_dll_error_vector : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      llk_tx_ch_posted_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      l0_rx_mac_link_error : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      max_payload_size : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      TXN : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      TXP : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      PLLLKDET_OUT : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      llk_tx_chan_space : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      mgmt_stats_credit : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      l0_multi_msg_en0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      mgmt_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      llk_tx_ch_completion_ready_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      max_read_request_size : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
      l0_mac_negotiated_link_width : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      l0_completer_id : out STD_LOGIC_VECTOR ( 12 downto 0 ); 
      llk_rx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_rx_present : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      mgmt_bwren : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      mgmt_addr : in STD_LOGIC_VECTOR ( 10 downto 0 ); 
      gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      l0_msi_request0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      RXN : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      RXP : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
      llk_tx_ch_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      llk_tx_ch_fifo : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
      llk_tx_enable_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_rx_ch_fifo : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      mgmt_stats_credit_sel : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      llk_tx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      llk_rx_ch_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      mgmt_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  component pcie_blk_ll
    port (
      rx_err_cpl_ur_n : out STD_LOGIC; 
      llk_tx_src_rdy_n : out STD_LOGIC; 
      trn_rsrc_rdy_n : out STD_LOGIC; 
      l0_stats_tlp_received : in STD_LOGIC := 'X'; 
      trn_terrfwd_n : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      llk_rx_eof_n : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      cfg_tx_dst_rdy_n : out STD_LOGIC; 
      llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
      trn_rerrfwd_n : out STD_LOGIC; 
      llk_rx_dst_cont_req_n : out STD_LOGIC; 
      cfg_tx_eof_n : in STD_LOGIC := 'X'; 
      trn_rnp_ok_n : in STD_LOGIC := 'X'; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      err_tlp_malformed : out STD_LOGIC; 
      llk_tx_sop_n : out STD_LOGIC; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      err_tlp_ur_lock : out STD_LOGIC; 
      trn_rsof_n : out STD_LOGIC; 
      io_space_enable : in STD_LOGIC := 'X'; 
      llk_rx_dst_req_n : out STD_LOGIC; 
      llk_rx_src_last_req_n : in STD_LOGIC := 'X'; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      llk_rx_sof_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_ep_n : out STD_LOGIC; 
      cfg_tx_src_rdy_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      err_tlp_uc : out STD_LOGIC; 
      cfg_tx_sof_n : in STD_LOGIC := 'X'; 
      llk_tx_src_dsc_n : out STD_LOGIC; 
      trn_rsrc_dsc_n : out STD_LOGIC; 
      err_tlp_ur : out STD_LOGIC; 
      tx_err_wr_ep_n : out STD_LOGIC; 
      llk_rx_src_dsc_n : in STD_LOGIC := 'X'; 
      llk_tx_eof_n : out STD_LOGIC; 
      llk_tx_dst_rdy_n : in STD_LOGIC := 'X'; 
      trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      cfg_tx_rem_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_abort_n : out STD_LOGIC; 
      err_tlp_p : out STD_LOGIC; 
      mem_space_enable : in STD_LOGIC := 'X'; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      rx_err_ep_n : out STD_LOGIC; 
      llk_tx_eop_n : out STD_LOGIC; 
      trn_reof_n : out STD_LOGIC; 
      llk_tx_sof_n : out STD_LOGIC; 
      trn_lnk_up_n : in STD_LOGIC := 'X'; 
      trn_pfc_cplh_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_npd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      err_tlp_cpl_header : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
      trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_cpld_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_pfc_ph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      llk_tx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      llk_rx_data_d : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_pfc_nph_cl : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_tx_enable_n : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_rx_ch_fifo : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      mgmt_stats_credit_sel : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      llk_tx_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_pfc_pd_cl : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_rx_ch_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      llk_rx_ch_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_non_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
      llk_rx_ch_non_posted_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_ch_completion_available_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_rx_valid_n : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      cfg_tx_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      llk_rx_preferred_type : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tx_ch_posted_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_rx_xrom : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_pmcsr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      llk_tx_chan_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      mgmt_stats_credit : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      llk_tx_ch_completion_ready_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_rx_bar0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      llk_rx_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component pcie_blk_cf
    port (
      rx_err_cpl_ur_n : in STD_LOGIC := 'X'; 
      l0_set_user_system_error : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      rst_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_ur_lock_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      l0_set_user_received_master_abort : out STD_LOGIC; 
      llk_rx_src_rdy_n : in STD_LOGIC := 'X'; 
      l0_set_detected_nonfatal_error : out STD_LOGIC; 
      cfg_arb_teof_n : out STD_LOGIC; 
      cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
      serr_enable : in STD_LOGIC := 'X'; 
      mgmt_rden : out STD_LOGIC; 
      cfg_to_turnoff_n : out STD_LOGIC; 
      l0_set_detected_corr_error : out STD_LOGIC; 
      mac_link_up : in STD_LOGIC := 'X'; 
      mgmt_wren : out STD_LOGIC; 
      bus_master_enable : in STD_LOGIC := 'X'; 
      cfg_rd_en_n : in STD_LOGIC := 'X'; 
      cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
      cfg_arb_tsrc_rdy_n : out STD_LOGIC; 
      io_space_enable : in STD_LOGIC := 'X'; 
      l0_pwr_turn_off_req : in STD_LOGIC := 'X'; 
      parity_error_response : in STD_LOGIC := 'X'; 
      cfg_rd_wr_done_n : out STD_LOGIC; 
      l0_pme_req_in : out STD_LOGIC; 
      rx_err_cpl_ep_n : in STD_LOGIC := 'X'; 
      legacy_int_request : out STD_LOGIC; 
      rx_err_tlp_ur_n : in STD_LOGIC := 'X'; 
      l0_set_user_master_data_parity : out STD_LOGIC; 
      msi_8bit_en : in STD_LOGIC := 'X'; 
      cfg_err_locked_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_transmitted : in STD_LOGIC := 'X'; 
      cfg_arb_tsof_n : out STD_LOGIC; 
      cfg_trn_pending_n : in STD_LOGIC := 'X'; 
      l0_set_user_detected_parity_error : out STD_LOGIC; 
      l0_set_user_signaled_target_abort : out STD_LOGIC; 
      l0_set_detected_fatal_error : out STD_LOGIC; 
      tx_err_wr_ep_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_malformed_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_p_cpl_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_msienable : out STD_LOGIC; 
      cfg_err_ur_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_n : in STD_LOGIC := 'X'; 
      rx_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      cfg_wr_en_n : in STD_LOGIC := 'X'; 
      l0_stats_cfg_received : in STD_LOGIC := 'X'; 
      l0_pme_ack : in STD_LOGIC := 'X'; 
      msi_enable : in STD_LOGIC := 'X'; 
      cfg_pm_wake_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_rdy_n : out STD_LOGIC; 
      cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
      mem_space_enable : in STD_LOGIC := 'X'; 
      cfg_err_posted_n : in STD_LOGIC := 'X'; 
      rx_err_ep_n : in STD_LOGIC := 'X'; 
      l0_set_unsupported_request_other_error : out STD_LOGIC; 
      cfg_err_cpl_rdy_n : out STD_LOGIC; 
      l0_set_user_received_target_abort : out STD_LOGIC; 
      cfg_arb_tdst_rdy_n : in STD_LOGIC := 'X'; 
      rx_err_tlp_poisoned_n : in STD_LOGIC := 'X'; 
      cfg_err_cor_n : in STD_LOGIC := 'X'; 
      transactions_pending : out STD_LOGIC; 
      cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
      trn_lnk_up_n : out STD_LOGIC; 
      cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
      cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mgmt_bwren : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      mgmt_addr : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
      cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_arb_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_dcap : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_rx_xrom : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      msi_request : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_pmcsr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_arb_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_rx_bar0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      mgmt_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar1 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar4 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_rx_bar5 : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      l0_ltssm_state : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      llk_tc_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rx_err_tlp_hdr : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mac_negotiated_link_width : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      mgmt_pso : in STD_LOGIC_VECTOR ( 16 downto 0 ); 
      l0_dll_error_vector : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      completer_id : in STD_LOGIC_VECTOR ( 12 downto 0 ); 
      l0_rx_mac_link_error : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      max_payload_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      cfg_dwaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      llk_rx_data_d : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mgmt_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      max_read_request_size : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  signal GTPRESET : STD_LOGIC; 
  signal Mshreg_trn_lnk_up_n_reg_30518 : STD_LOGIC; 
  signal app_reset_n_30520 : STD_LOGIC; 
  signal app_reset_n_flt_reg_30521 : STD_LOGIC; 
  signal app_reset_n_flt_reg_and0000 : STD_LOGIC; 
  signal bridge_mgmt_rden : STD_LOGIC; 
  signal bridge_mgmt_wren : STD_LOGIC; 
  signal clock_lock : STD_LOGIC; 
  signal core_clk : STD_LOGIC; 
  signal fe_bus_master_enable : STD_LOGIC; 
  signal fe_compliance_avoid : STD_LOGIC; 
  signal fe_io_space_enable : STD_LOGIC; 
  signal fe_l0_legacy_int_funct0 : STD_LOGIC; 
  signal fe_l0_mac_link_up : STD_LOGIC; 
  signal fe_l0_msi_enable0 : STD_LOGIC; 
  signal fe_l0_pme_ack : STD_LOGIC; 
  signal fe_l0_pme_req_in : STD_LOGIC; 
  signal fe_l0_pwr_turn_off_req : STD_LOGIC; 
  signal fe_l0_set_detected_corr_error : STD_LOGIC; 
  signal fe_l0_set_detected_fatal_error : STD_LOGIC; 
  signal fe_l0_set_detected_nonfatal_error : STD_LOGIC; 
  signal fe_l0_set_unsupported_request_other_error : STD_LOGIC; 
  signal fe_l0_set_user_detected_parity_error : STD_LOGIC; 
  signal fe_l0_set_user_master_data_parity : STD_LOGIC; 
  signal fe_l0_set_user_received_master_abort : STD_LOGIC; 
  signal fe_l0_set_user_received_target_abort : STD_LOGIC; 
  signal fe_l0_set_user_signalled_target_abort : STD_LOGIC; 
  signal fe_l0_set_user_system_error : STD_LOGIC; 
  signal fe_l0_stats_cfg_received : STD_LOGIC; 
  signal fe_l0_stats_cfg_transmitted : STD_LOGIC; 
  signal fe_l0_stats_tlp_received : STD_LOGIC; 
  signal fe_l0_transactions_pending : STD_LOGIC; 
  signal fe_mem_space_enable : STD_LOGIC; 
  signal fe_parity_error_response : STD_LOGIC; 
  signal fe_serr_enable : STD_LOGIC; 
  signal llk_rx_dst_cont_req_n : STD_LOGIC; 
  signal llk_rx_dst_req_n : STD_LOGIC; 
  signal llk_rx_eof_n : STD_LOGIC; 
  signal llk_rx_sof_n : STD_LOGIC; 
  signal llk_rx_src_last_req_n : STD_LOGIC; 
  signal llk_rx_src_rdy_n : STD_LOGIC; 
  signal llk_tx_dst_rdy_n : STD_LOGIC; 
  signal llk_tx_eof_n : STD_LOGIC; 
  signal llk_tx_sof_n : STD_LOGIC; 
  signal llk_tx_src_dsc_n : STD_LOGIC; 
  signal llk_tx_src_rdy_n : STD_LOGIC; 
  signal mgmt_rdy : STD_LOGIC; 
  signal mgmt_rst_delay_n : STD_LOGIC; 
  signal mgt_reset_n : STD_LOGIC; 
  signal mgt_reset_n_flt_reg_31450 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_clk : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_lnk_up_n : STD_LOGIC; 
  signal trn_lnk_up_n_reg_31488 : STD_LOGIC; 
  signal pcie_blk_if_tx_err_wr_ep_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_ur_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_ur_lock_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_ur_lock : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_ur : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_p_cpl_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_p_cpl : STD_LOGIC; 
  signal pcie_blk_if_rx_err_tlp_malformed_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_ep_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_cpl_ur_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_cpl_ep_n : STD_LOGIC; 
  signal pcie_blk_if_rx_err_cpl_abort_n : STD_LOGIC; 
  signal pcie_blk_if_llk_tx_sop_n : STD_LOGIC; 
  signal pcie_blk_if_llk_tx_eop_n : STD_LOGIC; 
  signal pcie_blk_if_err_tlp_malformed : STD_LOGIC; 
  signal pcie_blk_if_cfg_arb_tsrc_rdy_n : STD_LOGIC; 
  signal pcie_blk_if_cfg_arb_tsof_n : STD_LOGIC; 
  signal pcie_blk_if_cfg_arb_teof_n : STD_LOGIC; 
  signal pcie_blk_if_cfg_arb_tdst_rdy_n : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_abort_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_unexpect_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_rd_en_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_ecrc_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_msi_8bit_en_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_locked_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_trn_pending_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_timeout_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_ur_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_wr_en_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pm_wake_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_turnoff_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_posted_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_rx_err_tlp_poisoned_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_cor_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dcap_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_dsn_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_payload_size_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_payload_size_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_payload_size_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_read_request_size_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_read_request_size_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_max_read_request_size_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_cf_bridge_cfg_di_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_err_tlp_uc_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_llk_rx_src_dsc_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_os_transmitted_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_mac_rx_l0s_state_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_mac_entered_l0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_crm_do_hot_reset_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_llk_rx_eop_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_cfg_other_received_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_interrupt_disable_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_GTPCLK_bufg_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_mac_link_training_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_ur_reporting_enable_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_cfg_loopback_ack_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_os_received_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_dllp_transmitted_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_first_cfg_write_occurred_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_llk_rx_sop_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_dllp_received_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_tlp_transmitted_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_crm_pwr_soft_reset_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_pwr_tx_l0s_state_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_pwr_l23_ready_state_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_stats_cfg_other_transmitted_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_mac_new_state_ack_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_pwr_state0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_pwr_state0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_338_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_337_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_336_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_335_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_334_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_333_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_332_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_331_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_330_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_329_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_328_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_327_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_326_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_325_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_324_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_323_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_322_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_321_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_320_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_319_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_318_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_317_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_316_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_315_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_314_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_313_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_312_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_311_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_310_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_309_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_308_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_307_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_306_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_305_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_304_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_303_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_302_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_301_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_300_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_299_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_298_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_297_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_296_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_295_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_294_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_293_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_292_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_291_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_290_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_289_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_288_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_287_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_286_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_285_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_284_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_283_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_282_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_281_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_280_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_279_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_278_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_277_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_276_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_275_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_274_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_273_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_272_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_271_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_270_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_269_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_268_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_267_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_266_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_265_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_264_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_263_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_262_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_261_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_260_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_259_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_258_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_257_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_256_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_255_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_254_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_253_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_252_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_251_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_250_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_249_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_248_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_247_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_246_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_245_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_244_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_243_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_242_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_241_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_240_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_239_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_238_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_237_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_236_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_235_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_234_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_233_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_232_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_231_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_230_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_229_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_228_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_227_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_226_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_225_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_224_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_223_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_222_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_221_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_220_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_219_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_218_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_217_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_216_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_215_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_214_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_213_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_212_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_211_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_210_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_209_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_208_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_207_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_206_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_205_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_204_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_203_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_202_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_201_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_200_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_199_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_198_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_197_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_196_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_195_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_194_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_193_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_192_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_191_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_190_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_189_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_188_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_187_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_186_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_185_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_184_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_183_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_182_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_181_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_180_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_179_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_178_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_177_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_176_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_175_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_174_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_173_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_172_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_171_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_170_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_169_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_168_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_167_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_166_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_165_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_164_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_163_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_162_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_161_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_160_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_159_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_158_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_157_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_156_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_155_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_154_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_153_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_152_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_151_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_150_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_149_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_148_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_147_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_146_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_145_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_144_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_143_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_142_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_141_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_140_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_139_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_138_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_137_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_136_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_135_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_134_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_133_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_132_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_131_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_130_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_129_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_128_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_127_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_126_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_125_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_124_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_123_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_122_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_121_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_120_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_119_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_118_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_117_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_116_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_115_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_114_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_113_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_112_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_111_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_110_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_109_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_108_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_107_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_106_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_105_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_104_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_103_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_102_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_101_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_100_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_99_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_98_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_97_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_96_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_95_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_94_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_93_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_92_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_91_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_90_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_89_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_88_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_87_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_86_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_85_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_84_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_83_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_82_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_81_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_80_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_79_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_78_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_77_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_76_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_75_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_74_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_73_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_72_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_71_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_70_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_69_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_68_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_67_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_66_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_65_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_64_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_DEBUG_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_RESETDONE_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_dl_up_down_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_PLLLKDET_OUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_PLLLKDET_OUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_PLLLKDET_OUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_multi_msg_en0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_multi_msg_en0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_blk_l0_multi_msg_en0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_trn_lnk_up_n_reg_Q15_UNCONNECTED : STD_LOGIC; 
  signal PLLLKDET_OUT : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal bridge_mgmt_addr : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal bridge_mgmt_bwren : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal bridge_mgmt_wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_bus_number : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_command : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_dcommand : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_device_number : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal NlwRenamedSig_OI_cfg_function_number : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal fe_l0_completer_id : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal fe_l0_dll_error_vector : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal fe_l0_dll_error_vector_ext : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal fe_l0_ltssm_state : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal fe_l0_mac_negotiated_link_width : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal fe_l0_msi_request0 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal fe_l0_rx_mac_link_error : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal fe_l0_rx_mac_link_error_ext : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal fe_max_payload_size : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal fe_max_read_request_size : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal llk_rx_ch_completion_available_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_rx_ch_fifo : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal llk_rx_ch_non_posted_available_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_rx_ch_posted_available_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_rx_ch_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal llk_rx_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal llk_rx_preferred_type : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal llk_rx_valid_n : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal llk_tc_status : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_tx_ch_completion_ready_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_tx_ch_fifo : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal llk_tx_ch_non_posted_ready_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_tx_ch_posted_ready_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal llk_tx_ch_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal llk_tx_chan_space : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal llk_tx_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal llk_tx_enable_n : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal mgmt_pso : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal mgmt_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal mgmt_stats_credit : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal mgmt_stats_credit_sel : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal pcie_blk_if_rx_err_tlp_hdr : STD_LOGIC_VECTOR ( 47 downto 0 ); 
  signal pcie_blk_if_mgmt_addr : STD_LOGIC_VECTOR ( 10 downto 10 ); 
  signal pcie_blk_if_llk_rx_data_d : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pcie_blk_if_cfg_rx_xrom : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar5 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar4 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar3 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar2 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar1 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_rx_bar0 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pcie_blk_if_cfg_pmcsr : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal pcie_blk_if_cfg_dcap : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal pcie_blk_if_cfg_arb_trem_n : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal pcie_blk_if_cfg_arb_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  trn_clk <= NlwRenamedSig_OI_trn_clk;
  trn_lnk_up_n <= NlwRenamedSig_OI_trn_lnk_up_n;
  cfg_device_number(4) <= NlwRenamedSig_OI_cfg_device_number(4);
  cfg_device_number(3) <= NlwRenamedSig_OI_cfg_device_number(3);
  cfg_device_number(2) <= NlwRenamedSig_OI_cfg_device_number(2);
  cfg_device_number(1) <= NlwRenamedSig_OI_cfg_device_number(1);
  cfg_device_number(0) <= NlwRenamedSig_OI_cfg_device_number(0);
  cfg_bus_number(7) <= NlwRenamedSig_OI_cfg_bus_number(7);
  cfg_bus_number(6) <= NlwRenamedSig_OI_cfg_bus_number(6);
  cfg_bus_number(5) <= NlwRenamedSig_OI_cfg_bus_number(5);
  cfg_bus_number(4) <= NlwRenamedSig_OI_cfg_bus_number(4);
  cfg_bus_number(3) <= NlwRenamedSig_OI_cfg_bus_number(3);
  cfg_bus_number(2) <= NlwRenamedSig_OI_cfg_bus_number(2);
  cfg_bus_number(1) <= NlwRenamedSig_OI_cfg_bus_number(1);
  cfg_bus_number(0) <= NlwRenamedSig_OI_cfg_bus_number(0);
  cfg_command(1) <= NlwRenamedSig_OI_cfg_command(1);
  cfg_command(0) <= NlwRenamedSig_OI_cfg_command(0);
  cfg_dcommand(15) <= NlwRenamedSig_OI_cfg_dcommand(15);
  cfg_dcommand(14) <= NlwRenamedSig_OI_cfg_dcommand(14);
  cfg_dcommand(13) <= NlwRenamedSig_OI_cfg_dcommand(13);
  cfg_dcommand(12) <= NlwRenamedSig_OI_cfg_dcommand(12);
  cfg_dcommand(11) <= NlwRenamedSig_OI_cfg_dcommand(11);
  cfg_dcommand(10) <= NlwRenamedSig_OI_cfg_dcommand(10);
  cfg_dcommand(9) <= NlwRenamedSig_OI_cfg_dcommand(9);
  cfg_dcommand(8) <= NlwRenamedSig_OI_cfg_dcommand(8);
  cfg_dcommand(7) <= NlwRenamedSig_OI_cfg_dcommand(7);
  cfg_dcommand(6) <= NlwRenamedSig_OI_cfg_dcommand(6);
  cfg_dcommand(5) <= NlwRenamedSig_OI_cfg_dcommand(5);
  cfg_dcommand(4) <= NlwRenamedSig_OI_cfg_dcommand(4);
  cfg_dcommand(3) <= NlwRenamedSig_OI_cfg_dcommand(3);
  cfg_dcommand(2) <= NlwRenamedSig_OI_cfg_dcommand(2);
  cfg_dcommand(1) <= NlwRenamedSig_OI_cfg_dcommand(1);
  cfg_dcommand(0) <= NlwRenamedSig_OI_cfg_dcommand(0);
  cfg_function_number(2) <= NlwRenamedSig_OI_cfg_function_number(2);
  cfg_function_number(1) <= NlwRenamedSig_OI_cfg_function_number(1);
  cfg_function_number(0) <= NlwRenamedSig_OI_cfg_function_number(0);
  XST_GND : GND
    port map (
      G => fe_compliance_avoid
    );
  XST_VCC : VCC
    port map (
      P => mgmt_rst_delay_n
    );
  mgt_reset_n_flt_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_trn_clk,
      D => mgt_reset_n,
      Q => mgt_reset_n_flt_reg_31450
    );
  app_reset_n_flt_reg : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_trn_clk,
      D => app_reset_n_flt_reg_and0000,
      Q => app_reset_n_flt_reg_30521
    );
  app_reset_n : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_trn_clk,
      D => app_reset_n_flt_reg_30521,
      Q => app_reset_n_30520
    );
  extend_clk : extend_clk_extend_clk
    port map (
      clk => core_clk,
      rst_n => sys_reset_n,
      l0_rx_mac_link_error_retime(1) => fe_l0_rx_mac_link_error_ext(1),
      l0_rx_mac_link_error_retime(0) => fe_l0_rx_mac_link_error_ext(0),
      l0_dll_error_vector_retime(6) => fe_l0_dll_error_vector_ext(6),
      l0_dll_error_vector_retime(5) => fe_l0_dll_error_vector_ext(5),
      l0_dll_error_vector_retime(4) => fe_l0_dll_error_vector_ext(4),
      l0_dll_error_vector_retime(3) => fe_l0_dll_error_vector_ext(3),
      l0_dll_error_vector_retime(2) => fe_l0_dll_error_vector_ext(2),
      l0_dll_error_vector_retime(1) => fe_l0_dll_error_vector_ext(1),
      l0_dll_error_vector_retime(0) => fe_l0_dll_error_vector_ext(0),
      l0_dll_error_vector(6) => fe_l0_dll_error_vector(6),
      l0_dll_error_vector(5) => fe_l0_dll_error_vector(5),
      l0_dll_error_vector(4) => fe_l0_dll_error_vector(4),
      l0_dll_error_vector(3) => fe_l0_dll_error_vector(3),
      l0_dll_error_vector(2) => fe_l0_dll_error_vector(2),
      l0_dll_error_vector(1) => fe_l0_dll_error_vector(1),
      l0_dll_error_vector(0) => fe_l0_dll_error_vector(0),
      l0_rx_mac_link_error(1) => fe_l0_rx_mac_link_error(1),
      l0_rx_mac_link_error(0) => fe_l0_rx_mac_link_error(0)
    );
  pcie_blk : pcie_top_wrapper
    port map (
      llk_tx_src_rdy_n => llk_tx_src_rdy_n,
      l0_stats_tlp_received => fe_l0_stats_tlp_received,
      l0_set_user_system_error => fe_l0_set_user_system_error,
      l0_stats_os_transmitted => NLW_pcie_blk_l0_stats_os_transmitted_UNCONNECTED,
      llk_rx_eof_n => llk_rx_eof_n,
      l0_set_unexpected_completion_uncorr_error => fe_compliance_avoid,
      l0_set_user_received_master_abort => fe_l0_set_user_received_master_abort,
      llk_rx_src_rdy_n => llk_rx_src_rdy_n,
      l0_set_detected_nonfatal_error => fe_l0_set_detected_nonfatal_error,
      serr_enable => fe_serr_enable,
      llk_rx_dst_cont_req_n => llk_rx_dst_cont_req_n,
      l0_mac_rx_l0s_state => NLW_pcie_blk_l0_mac_rx_l0s_state_UNCONNECTED,
      l0_set_completer_abort_error => fe_compliance_avoid,
      l0_mac_entered_l0 => NLW_pcie_blk_l0_mac_entered_l0_UNCONNECTED,
      mgmt_rden => bridge_mgmt_rden,
      crm_link_rst_n => sys_reset_n,
      l0_cfg_loopback_master => fe_compliance_avoid,
      l0_set_detected_corr_error => fe_l0_set_detected_corr_error,
      crm_nvrst_n => sys_reset_n,
      crm_do_hot_reset_n => NLW_pcie_blk_crm_do_hot_reset_n_UNCONNECTED,
      mgmt_wren => bridge_mgmt_wren,
      bus_master_enable => fe_bus_master_enable,
      l0_msi_enable0 => fe_l0_msi_enable0,
      llk_tx_sop_n => mgmt_rst_delay_n,
      mgmt_rdy => mgmt_rdy,
      user_clk => NlwRenamedSig_OI_trn_clk,
      io_space_enable => fe_io_space_enable,
      l0_pwr_turn_off_req => fe_l0_pwr_turn_off_req,
      parity_error_response => fe_parity_error_response,
      llk_rx_dst_req_n => llk_rx_dst_req_n,
      crm_urst_n => sys_reset_n,
      llk_rx_eop_n => NLW_pcie_blk_llk_rx_eop_n_UNCONNECTED,
      llk_rx_src_last_req_n => llk_rx_src_last_req_n,
      l0_pme_req_in => fe_l0_pme_req_in,
      GTPRESET => GTPRESET,
      REFCLKOUT_bufg => refclkout,
      l0_stats_cfg_other_received => NLW_pcie_blk_l0_stats_cfg_other_received_UNCONNECTED,
      interrupt_disable => NLW_pcie_blk_interrupt_disable_UNCONNECTED,
      llk_rx_sof_n => llk_rx_sof_n,
      crm_mac_rst_n => sys_reset_n,
      GTPCLK_bufg => NLW_pcie_blk_GTPCLK_bufg_UNCONNECTED,
      l0_mac_link_training => NLW_pcie_blk_l0_mac_link_training_UNCONNECTED,
      l0_set_user_master_data_parity => fe_l0_set_user_master_data_parity,
      l0_stats_cfg_transmitted => fe_l0_stats_cfg_transmitted,
      l0_mac_link_up => fe_l0_mac_link_up,
      crm_user_cfg_rst_n => sys_reset_n,
      l0_set_user_signalled_target_abort => fe_l0_set_user_signalled_target_abort,
      l0_set_user_detected_parity_error => fe_l0_set_user_detected_parity_error,
      ur_reporting_enable => NLW_pcie_blk_ur_reporting_enable_UNCONNECTED,
      l0_set_detected_fatal_error => fe_l0_set_detected_fatal_error,
      l0_cfg_loopback_ack => NLW_pcie_blk_l0_cfg_loopback_ack_UNCONNECTED,
      llk_tx_src_dsc_n => llk_tx_src_dsc_n,
      l0_set_completion_timeout_corr_error => fe_compliance_avoid,
      REFCLK => sys_clk,
      clock_lock => clock_lock,
      l0_transactions_pending => fe_l0_transactions_pending,
      l0_stats_os_received => NLW_pcie_blk_l0_stats_os_received_UNCONNECTED,
      l0_stats_dllp_transmitted => NLW_pcie_blk_l0_stats_dllp_transmitted_UNCONNECTED,
      l0_legacy_int_funct0 => fe_l0_legacy_int_funct0,
      l0_first_cfg_write_occurred => NLW_pcie_blk_l0_first_cfg_write_occurred_UNCONNECTED,
      core_clk => core_clk,
      fast_train_simulation_only => fast_train_simulation_only,
      llk_tx_eof_n => llk_tx_eof_n,
      llk_tx_dst_rdy_n => llk_tx_dst_rdy_n,
      llk_rx_sop_n => NLW_pcie_blk_llk_rx_sop_n_UNCONNECTED,
      user_reset_n => sys_reset_n,
      l0_stats_dllp_received => NLW_pcie_blk_l0_stats_dllp_received_UNCONNECTED,
      l0_stats_cfg_received => fe_l0_stats_cfg_received,
      l0_stats_tlp_transmitted => NLW_pcie_blk_l0_stats_tlp_transmitted_UNCONNECTED,
      l0_pme_ack => fe_l0_pme_ack,
      crm_pwr_soft_reset_n => NLW_pcie_blk_crm_pwr_soft_reset_n_UNCONNECTED,
      l0_pwr_tx_l0s_state => NLW_pcie_blk_l0_pwr_tx_l0s_state_UNCONNECTED,
      l0_set_unexpected_completion_corr_error => fe_compliance_avoid,
      mem_space_enable => fe_mem_space_enable,
      l0_pwr_l23_ready_state => NLW_pcie_blk_l0_pwr_l23_ready_state_UNCONNECTED,
      mgmt_reset_delay_n => mgmt_rst_delay_n,
      l0_set_unsupported_request_other_error => fe_l0_set_unsupported_request_other_error,
      l0_set_unsupported_request_nonposted_error => fe_compliance_avoid,
      l0_set_completion_timeout_uncorr_error => fe_compliance_avoid,
      gt_dclk => fe_compliance_avoid,
      crm_mgmt_rst_n => sys_reset_n,
      l0_set_user_received_target_abort => fe_l0_set_user_received_target_abort,
      l0_stats_cfg_other_transmitted => NLW_pcie_blk_l0_stats_cfg_other_transmitted_UNCONNECTED,
      llk_tx_eop_n => mgmt_rst_delay_n,
      compliance_avoid => fe_compliance_avoid,
      l0_mac_new_state_ack => NLW_pcie_blk_l0_mac_new_state_ack_UNCONNECTED,
      llk_tx_sof_n => llk_tx_sof_n,
      trn_lnk_up_n => trn_lnk_up_n_reg_31488,
      l0_pwr_state0(1) => NLW_pcie_blk_l0_pwr_state0_1_UNCONNECTED,
      l0_pwr_state0(0) => NLW_pcie_blk_l0_pwr_state0_0_UNCONNECTED,
      llk_rx_ch_posted_available_n(7) => llk_rx_ch_posted_available_n(7),
      llk_rx_ch_posted_available_n(6) => llk_rx_ch_posted_available_n(6),
      llk_rx_ch_posted_available_n(5) => llk_rx_ch_posted_available_n(5),
      llk_rx_ch_posted_available_n(4) => llk_rx_ch_posted_available_n(4),
      llk_rx_ch_posted_available_n(3) => llk_rx_ch_posted_available_n(3),
      llk_rx_ch_posted_available_n(2) => llk_rx_ch_posted_available_n(2),
      llk_rx_ch_posted_available_n(1) => llk_rx_ch_posted_available_n(1),
      llk_rx_ch_posted_available_n(0) => llk_rx_ch_posted_available_n(0),
      llk_tx_ch_non_posted_ready_n(7) => llk_tx_ch_non_posted_ready_n(7),
      llk_tx_ch_non_posted_ready_n(6) => llk_tx_ch_non_posted_ready_n(6),
      llk_tx_ch_non_posted_ready_n(5) => llk_tx_ch_non_posted_ready_n(5),
      llk_tx_ch_non_posted_ready_n(4) => llk_tx_ch_non_posted_ready_n(4),
      llk_tx_ch_non_posted_ready_n(3) => llk_tx_ch_non_posted_ready_n(3),
      llk_tx_ch_non_posted_ready_n(2) => llk_tx_ch_non_posted_ready_n(2),
      llk_tx_ch_non_posted_ready_n(1) => llk_tx_ch_non_posted_ready_n(1),
      llk_tx_ch_non_posted_ready_n(0) => llk_tx_ch_non_posted_ready_n(0),
      DEBUG(338) => NLW_pcie_blk_DEBUG_338_UNCONNECTED,
      DEBUG(337) => NLW_pcie_blk_DEBUG_337_UNCONNECTED,
      DEBUG(336) => NLW_pcie_blk_DEBUG_336_UNCONNECTED,
      DEBUG(335) => NLW_pcie_blk_DEBUG_335_UNCONNECTED,
      DEBUG(334) => NLW_pcie_blk_DEBUG_334_UNCONNECTED,
      DEBUG(333) => NLW_pcie_blk_DEBUG_333_UNCONNECTED,
      DEBUG(332) => NLW_pcie_blk_DEBUG_332_UNCONNECTED,
      DEBUG(331) => NLW_pcie_blk_DEBUG_331_UNCONNECTED,
      DEBUG(330) => NLW_pcie_blk_DEBUG_330_UNCONNECTED,
      DEBUG(329) => NLW_pcie_blk_DEBUG_329_UNCONNECTED,
      DEBUG(328) => NLW_pcie_blk_DEBUG_328_UNCONNECTED,
      DEBUG(327) => NLW_pcie_blk_DEBUG_327_UNCONNECTED,
      DEBUG(326) => NLW_pcie_blk_DEBUG_326_UNCONNECTED,
      DEBUG(325) => NLW_pcie_blk_DEBUG_325_UNCONNECTED,
      DEBUG(324) => NLW_pcie_blk_DEBUG_324_UNCONNECTED,
      DEBUG(323) => NLW_pcie_blk_DEBUG_323_UNCONNECTED,
      DEBUG(322) => NLW_pcie_blk_DEBUG_322_UNCONNECTED,
      DEBUG(321) => NLW_pcie_blk_DEBUG_321_UNCONNECTED,
      DEBUG(320) => NLW_pcie_blk_DEBUG_320_UNCONNECTED,
      DEBUG(319) => NLW_pcie_blk_DEBUG_319_UNCONNECTED,
      DEBUG(318) => NLW_pcie_blk_DEBUG_318_UNCONNECTED,
      DEBUG(317) => NLW_pcie_blk_DEBUG_317_UNCONNECTED,
      DEBUG(316) => NLW_pcie_blk_DEBUG_316_UNCONNECTED,
      DEBUG(315) => NLW_pcie_blk_DEBUG_315_UNCONNECTED,
      DEBUG(314) => NLW_pcie_blk_DEBUG_314_UNCONNECTED,
      DEBUG(313) => NLW_pcie_blk_DEBUG_313_UNCONNECTED,
      DEBUG(312) => NLW_pcie_blk_DEBUG_312_UNCONNECTED,
      DEBUG(311) => NLW_pcie_blk_DEBUG_311_UNCONNECTED,
      DEBUG(310) => NLW_pcie_blk_DEBUG_310_UNCONNECTED,
      DEBUG(309) => NLW_pcie_blk_DEBUG_309_UNCONNECTED,
      DEBUG(308) => NLW_pcie_blk_DEBUG_308_UNCONNECTED,
      DEBUG(307) => NLW_pcie_blk_DEBUG_307_UNCONNECTED,
      DEBUG(306) => NLW_pcie_blk_DEBUG_306_UNCONNECTED,
      DEBUG(305) => NLW_pcie_blk_DEBUG_305_UNCONNECTED,
      DEBUG(304) => NLW_pcie_blk_DEBUG_304_UNCONNECTED,
      DEBUG(303) => NLW_pcie_blk_DEBUG_303_UNCONNECTED,
      DEBUG(302) => NLW_pcie_blk_DEBUG_302_UNCONNECTED,
      DEBUG(301) => NLW_pcie_blk_DEBUG_301_UNCONNECTED,
      DEBUG(300) => NLW_pcie_blk_DEBUG_300_UNCONNECTED,
      DEBUG(299) => NLW_pcie_blk_DEBUG_299_UNCONNECTED,
      DEBUG(298) => NLW_pcie_blk_DEBUG_298_UNCONNECTED,
      DEBUG(297) => NLW_pcie_blk_DEBUG_297_UNCONNECTED,
      DEBUG(296) => NLW_pcie_blk_DEBUG_296_UNCONNECTED,
      DEBUG(295) => NLW_pcie_blk_DEBUG_295_UNCONNECTED,
      DEBUG(294) => NLW_pcie_blk_DEBUG_294_UNCONNECTED,
      DEBUG(293) => NLW_pcie_blk_DEBUG_293_UNCONNECTED,
      DEBUG(292) => NLW_pcie_blk_DEBUG_292_UNCONNECTED,
      DEBUG(291) => NLW_pcie_blk_DEBUG_291_UNCONNECTED,
      DEBUG(290) => NLW_pcie_blk_DEBUG_290_UNCONNECTED,
      DEBUG(289) => NLW_pcie_blk_DEBUG_289_UNCONNECTED,
      DEBUG(288) => NLW_pcie_blk_DEBUG_288_UNCONNECTED,
      DEBUG(287) => NLW_pcie_blk_DEBUG_287_UNCONNECTED,
      DEBUG(286) => NLW_pcie_blk_DEBUG_286_UNCONNECTED,
      DEBUG(285) => NLW_pcie_blk_DEBUG_285_UNCONNECTED,
      DEBUG(284) => NLW_pcie_blk_DEBUG_284_UNCONNECTED,
      DEBUG(283) => NLW_pcie_blk_DEBUG_283_UNCONNECTED,
      DEBUG(282) => NLW_pcie_blk_DEBUG_282_UNCONNECTED,
      DEBUG(281) => NLW_pcie_blk_DEBUG_281_UNCONNECTED,
      DEBUG(280) => NLW_pcie_blk_DEBUG_280_UNCONNECTED,
      DEBUG(279) => NLW_pcie_blk_DEBUG_279_UNCONNECTED,
      DEBUG(278) => NLW_pcie_blk_DEBUG_278_UNCONNECTED,
      DEBUG(277) => NLW_pcie_blk_DEBUG_277_UNCONNECTED,
      DEBUG(276) => NLW_pcie_blk_DEBUG_276_UNCONNECTED,
      DEBUG(275) => NLW_pcie_blk_DEBUG_275_UNCONNECTED,
      DEBUG(274) => NLW_pcie_blk_DEBUG_274_UNCONNECTED,
      DEBUG(273) => NLW_pcie_blk_DEBUG_273_UNCONNECTED,
      DEBUG(272) => NLW_pcie_blk_DEBUG_272_UNCONNECTED,
      DEBUG(271) => NLW_pcie_blk_DEBUG_271_UNCONNECTED,
      DEBUG(270) => NLW_pcie_blk_DEBUG_270_UNCONNECTED,
      DEBUG(269) => NLW_pcie_blk_DEBUG_269_UNCONNECTED,
      DEBUG(268) => NLW_pcie_blk_DEBUG_268_UNCONNECTED,
      DEBUG(267) => NLW_pcie_blk_DEBUG_267_UNCONNECTED,
      DEBUG(266) => NLW_pcie_blk_DEBUG_266_UNCONNECTED,
      DEBUG(265) => NLW_pcie_blk_DEBUG_265_UNCONNECTED,
      DEBUG(264) => NLW_pcie_blk_DEBUG_264_UNCONNECTED,
      DEBUG(263) => NLW_pcie_blk_DEBUG_263_UNCONNECTED,
      DEBUG(262) => NLW_pcie_blk_DEBUG_262_UNCONNECTED,
      DEBUG(261) => NLW_pcie_blk_DEBUG_261_UNCONNECTED,
      DEBUG(260) => NLW_pcie_blk_DEBUG_260_UNCONNECTED,
      DEBUG(259) => NLW_pcie_blk_DEBUG_259_UNCONNECTED,
      DEBUG(258) => NLW_pcie_blk_DEBUG_258_UNCONNECTED,
      DEBUG(257) => NLW_pcie_blk_DEBUG_257_UNCONNECTED,
      DEBUG(256) => NLW_pcie_blk_DEBUG_256_UNCONNECTED,
      DEBUG(255) => NLW_pcie_blk_DEBUG_255_UNCONNECTED,
      DEBUG(254) => NLW_pcie_blk_DEBUG_254_UNCONNECTED,
      DEBUG(253) => NLW_pcie_blk_DEBUG_253_UNCONNECTED,
      DEBUG(252) => NLW_pcie_blk_DEBUG_252_UNCONNECTED,
      DEBUG(251) => NLW_pcie_blk_DEBUG_251_UNCONNECTED,
      DEBUG(250) => NLW_pcie_blk_DEBUG_250_UNCONNECTED,
      DEBUG(249) => NLW_pcie_blk_DEBUG_249_UNCONNECTED,
      DEBUG(248) => NLW_pcie_blk_DEBUG_248_UNCONNECTED,
      DEBUG(247) => NLW_pcie_blk_DEBUG_247_UNCONNECTED,
      DEBUG(246) => NLW_pcie_blk_DEBUG_246_UNCONNECTED,
      DEBUG(245) => NLW_pcie_blk_DEBUG_245_UNCONNECTED,
      DEBUG(244) => NLW_pcie_blk_DEBUG_244_UNCONNECTED,
      DEBUG(243) => NLW_pcie_blk_DEBUG_243_UNCONNECTED,
      DEBUG(242) => NLW_pcie_blk_DEBUG_242_UNCONNECTED,
      DEBUG(241) => NLW_pcie_blk_DEBUG_241_UNCONNECTED,
      DEBUG(240) => NLW_pcie_blk_DEBUG_240_UNCONNECTED,
      DEBUG(239) => NLW_pcie_blk_DEBUG_239_UNCONNECTED,
      DEBUG(238) => NLW_pcie_blk_DEBUG_238_UNCONNECTED,
      DEBUG(237) => NLW_pcie_blk_DEBUG_237_UNCONNECTED,
      DEBUG(236) => NLW_pcie_blk_DEBUG_236_UNCONNECTED,
      DEBUG(235) => NLW_pcie_blk_DEBUG_235_UNCONNECTED,
      DEBUG(234) => NLW_pcie_blk_DEBUG_234_UNCONNECTED,
      DEBUG(233) => NLW_pcie_blk_DEBUG_233_UNCONNECTED,
      DEBUG(232) => NLW_pcie_blk_DEBUG_232_UNCONNECTED,
      DEBUG(231) => NLW_pcie_blk_DEBUG_231_UNCONNECTED,
      DEBUG(230) => NLW_pcie_blk_DEBUG_230_UNCONNECTED,
      DEBUG(229) => NLW_pcie_blk_DEBUG_229_UNCONNECTED,
      DEBUG(228) => NLW_pcie_blk_DEBUG_228_UNCONNECTED,
      DEBUG(227) => NLW_pcie_blk_DEBUG_227_UNCONNECTED,
      DEBUG(226) => NLW_pcie_blk_DEBUG_226_UNCONNECTED,
      DEBUG(225) => NLW_pcie_blk_DEBUG_225_UNCONNECTED,
      DEBUG(224) => NLW_pcie_blk_DEBUG_224_UNCONNECTED,
      DEBUG(223) => NLW_pcie_blk_DEBUG_223_UNCONNECTED,
      DEBUG(222) => NLW_pcie_blk_DEBUG_222_UNCONNECTED,
      DEBUG(221) => NLW_pcie_blk_DEBUG_221_UNCONNECTED,
      DEBUG(220) => NLW_pcie_blk_DEBUG_220_UNCONNECTED,
      DEBUG(219) => NLW_pcie_blk_DEBUG_219_UNCONNECTED,
      DEBUG(218) => NLW_pcie_blk_DEBUG_218_UNCONNECTED,
      DEBUG(217) => NLW_pcie_blk_DEBUG_217_UNCONNECTED,
      DEBUG(216) => NLW_pcie_blk_DEBUG_216_UNCONNECTED,
      DEBUG(215) => NLW_pcie_blk_DEBUG_215_UNCONNECTED,
      DEBUG(214) => NLW_pcie_blk_DEBUG_214_UNCONNECTED,
      DEBUG(213) => NLW_pcie_blk_DEBUG_213_UNCONNECTED,
      DEBUG(212) => NLW_pcie_blk_DEBUG_212_UNCONNECTED,
      DEBUG(211) => NLW_pcie_blk_DEBUG_211_UNCONNECTED,
      DEBUG(210) => NLW_pcie_blk_DEBUG_210_UNCONNECTED,
      DEBUG(209) => NLW_pcie_blk_DEBUG_209_UNCONNECTED,
      DEBUG(208) => NLW_pcie_blk_DEBUG_208_UNCONNECTED,
      DEBUG(207) => NLW_pcie_blk_DEBUG_207_UNCONNECTED,
      DEBUG(206) => NLW_pcie_blk_DEBUG_206_UNCONNECTED,
      DEBUG(205) => NLW_pcie_blk_DEBUG_205_UNCONNECTED,
      DEBUG(204) => NLW_pcie_blk_DEBUG_204_UNCONNECTED,
      DEBUG(203) => NLW_pcie_blk_DEBUG_203_UNCONNECTED,
      DEBUG(202) => NLW_pcie_blk_DEBUG_202_UNCONNECTED,
      DEBUG(201) => NLW_pcie_blk_DEBUG_201_UNCONNECTED,
      DEBUG(200) => NLW_pcie_blk_DEBUG_200_UNCONNECTED,
      DEBUG(199) => NLW_pcie_blk_DEBUG_199_UNCONNECTED,
      DEBUG(198) => NLW_pcie_blk_DEBUG_198_UNCONNECTED,
      DEBUG(197) => NLW_pcie_blk_DEBUG_197_UNCONNECTED,
      DEBUG(196) => NLW_pcie_blk_DEBUG_196_UNCONNECTED,
      DEBUG(195) => NLW_pcie_blk_DEBUG_195_UNCONNECTED,
      DEBUG(194) => NLW_pcie_blk_DEBUG_194_UNCONNECTED,
      DEBUG(193) => NLW_pcie_blk_DEBUG_193_UNCONNECTED,
      DEBUG(192) => NLW_pcie_blk_DEBUG_192_UNCONNECTED,
      DEBUG(191) => NLW_pcie_blk_DEBUG_191_UNCONNECTED,
      DEBUG(190) => NLW_pcie_blk_DEBUG_190_UNCONNECTED,
      DEBUG(189) => NLW_pcie_blk_DEBUG_189_UNCONNECTED,
      DEBUG(188) => NLW_pcie_blk_DEBUG_188_UNCONNECTED,
      DEBUG(187) => NLW_pcie_blk_DEBUG_187_UNCONNECTED,
      DEBUG(186) => NLW_pcie_blk_DEBUG_186_UNCONNECTED,
      DEBUG(185) => NLW_pcie_blk_DEBUG_185_UNCONNECTED,
      DEBUG(184) => NLW_pcie_blk_DEBUG_184_UNCONNECTED,
      DEBUG(183) => NLW_pcie_blk_DEBUG_183_UNCONNECTED,
      DEBUG(182) => NLW_pcie_blk_DEBUG_182_UNCONNECTED,
      DEBUG(181) => NLW_pcie_blk_DEBUG_181_UNCONNECTED,
      DEBUG(180) => NLW_pcie_blk_DEBUG_180_UNCONNECTED,
      DEBUG(179) => NLW_pcie_blk_DEBUG_179_UNCONNECTED,
      DEBUG(178) => NLW_pcie_blk_DEBUG_178_UNCONNECTED,
      DEBUG(177) => NLW_pcie_blk_DEBUG_177_UNCONNECTED,
      DEBUG(176) => NLW_pcie_blk_DEBUG_176_UNCONNECTED,
      DEBUG(175) => NLW_pcie_blk_DEBUG_175_UNCONNECTED,
      DEBUG(174) => NLW_pcie_blk_DEBUG_174_UNCONNECTED,
      DEBUG(173) => NLW_pcie_blk_DEBUG_173_UNCONNECTED,
      DEBUG(172) => NLW_pcie_blk_DEBUG_172_UNCONNECTED,
      DEBUG(171) => NLW_pcie_blk_DEBUG_171_UNCONNECTED,
      DEBUG(170) => NLW_pcie_blk_DEBUG_170_UNCONNECTED,
      DEBUG(169) => NLW_pcie_blk_DEBUG_169_UNCONNECTED,
      DEBUG(168) => NLW_pcie_blk_DEBUG_168_UNCONNECTED,
      DEBUG(167) => NLW_pcie_blk_DEBUG_167_UNCONNECTED,
      DEBUG(166) => NLW_pcie_blk_DEBUG_166_UNCONNECTED,
      DEBUG(165) => NLW_pcie_blk_DEBUG_165_UNCONNECTED,
      DEBUG(164) => NLW_pcie_blk_DEBUG_164_UNCONNECTED,
      DEBUG(163) => NLW_pcie_blk_DEBUG_163_UNCONNECTED,
      DEBUG(162) => NLW_pcie_blk_DEBUG_162_UNCONNECTED,
      DEBUG(161) => NLW_pcie_blk_DEBUG_161_UNCONNECTED,
      DEBUG(160) => NLW_pcie_blk_DEBUG_160_UNCONNECTED,
      DEBUG(159) => NLW_pcie_blk_DEBUG_159_UNCONNECTED,
      DEBUG(158) => NLW_pcie_blk_DEBUG_158_UNCONNECTED,
      DEBUG(157) => NLW_pcie_blk_DEBUG_157_UNCONNECTED,
      DEBUG(156) => NLW_pcie_blk_DEBUG_156_UNCONNECTED,
      DEBUG(155) => NLW_pcie_blk_DEBUG_155_UNCONNECTED,
      DEBUG(154) => NLW_pcie_blk_DEBUG_154_UNCONNECTED,
      DEBUG(153) => NLW_pcie_blk_DEBUG_153_UNCONNECTED,
      DEBUG(152) => NLW_pcie_blk_DEBUG_152_UNCONNECTED,
      DEBUG(151) => NLW_pcie_blk_DEBUG_151_UNCONNECTED,
      DEBUG(150) => NLW_pcie_blk_DEBUG_150_UNCONNECTED,
      DEBUG(149) => NLW_pcie_blk_DEBUG_149_UNCONNECTED,
      DEBUG(148) => NLW_pcie_blk_DEBUG_148_UNCONNECTED,
      DEBUG(147) => NLW_pcie_blk_DEBUG_147_UNCONNECTED,
      DEBUG(146) => NLW_pcie_blk_DEBUG_146_UNCONNECTED,
      DEBUG(145) => NLW_pcie_blk_DEBUG_145_UNCONNECTED,
      DEBUG(144) => NLW_pcie_blk_DEBUG_144_UNCONNECTED,
      DEBUG(143) => NLW_pcie_blk_DEBUG_143_UNCONNECTED,
      DEBUG(142) => NLW_pcie_blk_DEBUG_142_UNCONNECTED,
      DEBUG(141) => NLW_pcie_blk_DEBUG_141_UNCONNECTED,
      DEBUG(140) => NLW_pcie_blk_DEBUG_140_UNCONNECTED,
      DEBUG(139) => NLW_pcie_blk_DEBUG_139_UNCONNECTED,
      DEBUG(138) => NLW_pcie_blk_DEBUG_138_UNCONNECTED,
      DEBUG(137) => NLW_pcie_blk_DEBUG_137_UNCONNECTED,
      DEBUG(136) => NLW_pcie_blk_DEBUG_136_UNCONNECTED,
      DEBUG(135) => NLW_pcie_blk_DEBUG_135_UNCONNECTED,
      DEBUG(134) => NLW_pcie_blk_DEBUG_134_UNCONNECTED,
      DEBUG(133) => NLW_pcie_blk_DEBUG_133_UNCONNECTED,
      DEBUG(132) => NLW_pcie_blk_DEBUG_132_UNCONNECTED,
      DEBUG(131) => NLW_pcie_blk_DEBUG_131_UNCONNECTED,
      DEBUG(130) => NLW_pcie_blk_DEBUG_130_UNCONNECTED,
      DEBUG(129) => NLW_pcie_blk_DEBUG_129_UNCONNECTED,
      DEBUG(128) => NLW_pcie_blk_DEBUG_128_UNCONNECTED,
      DEBUG(127) => NLW_pcie_blk_DEBUG_127_UNCONNECTED,
      DEBUG(126) => NLW_pcie_blk_DEBUG_126_UNCONNECTED,
      DEBUG(125) => NLW_pcie_blk_DEBUG_125_UNCONNECTED,
      DEBUG(124) => NLW_pcie_blk_DEBUG_124_UNCONNECTED,
      DEBUG(123) => NLW_pcie_blk_DEBUG_123_UNCONNECTED,
      DEBUG(122) => NLW_pcie_blk_DEBUG_122_UNCONNECTED,
      DEBUG(121) => NLW_pcie_blk_DEBUG_121_UNCONNECTED,
      DEBUG(120) => NLW_pcie_blk_DEBUG_120_UNCONNECTED,
      DEBUG(119) => NLW_pcie_blk_DEBUG_119_UNCONNECTED,
      DEBUG(118) => NLW_pcie_blk_DEBUG_118_UNCONNECTED,
      DEBUG(117) => NLW_pcie_blk_DEBUG_117_UNCONNECTED,
      DEBUG(116) => NLW_pcie_blk_DEBUG_116_UNCONNECTED,
      DEBUG(115) => NLW_pcie_blk_DEBUG_115_UNCONNECTED,
      DEBUG(114) => NLW_pcie_blk_DEBUG_114_UNCONNECTED,
      DEBUG(113) => NLW_pcie_blk_DEBUG_113_UNCONNECTED,
      DEBUG(112) => NLW_pcie_blk_DEBUG_112_UNCONNECTED,
      DEBUG(111) => NLW_pcie_blk_DEBUG_111_UNCONNECTED,
      DEBUG(110) => NLW_pcie_blk_DEBUG_110_UNCONNECTED,
      DEBUG(109) => NLW_pcie_blk_DEBUG_109_UNCONNECTED,
      DEBUG(108) => NLW_pcie_blk_DEBUG_108_UNCONNECTED,
      DEBUG(107) => NLW_pcie_blk_DEBUG_107_UNCONNECTED,
      DEBUG(106) => NLW_pcie_blk_DEBUG_106_UNCONNECTED,
      DEBUG(105) => NLW_pcie_blk_DEBUG_105_UNCONNECTED,
      DEBUG(104) => NLW_pcie_blk_DEBUG_104_UNCONNECTED,
      DEBUG(103) => NLW_pcie_blk_DEBUG_103_UNCONNECTED,
      DEBUG(102) => NLW_pcie_blk_DEBUG_102_UNCONNECTED,
      DEBUG(101) => NLW_pcie_blk_DEBUG_101_UNCONNECTED,
      DEBUG(100) => NLW_pcie_blk_DEBUG_100_UNCONNECTED,
      DEBUG(99) => NLW_pcie_blk_DEBUG_99_UNCONNECTED,
      DEBUG(98) => NLW_pcie_blk_DEBUG_98_UNCONNECTED,
      DEBUG(97) => NLW_pcie_blk_DEBUG_97_UNCONNECTED,
      DEBUG(96) => NLW_pcie_blk_DEBUG_96_UNCONNECTED,
      DEBUG(95) => NLW_pcie_blk_DEBUG_95_UNCONNECTED,
      DEBUG(94) => NLW_pcie_blk_DEBUG_94_UNCONNECTED,
      DEBUG(93) => NLW_pcie_blk_DEBUG_93_UNCONNECTED,
      DEBUG(92) => NLW_pcie_blk_DEBUG_92_UNCONNECTED,
      DEBUG(91) => NLW_pcie_blk_DEBUG_91_UNCONNECTED,
      DEBUG(90) => NLW_pcie_blk_DEBUG_90_UNCONNECTED,
      DEBUG(89) => NLW_pcie_blk_DEBUG_89_UNCONNECTED,
      DEBUG(88) => NLW_pcie_blk_DEBUG_88_UNCONNECTED,
      DEBUG(87) => NLW_pcie_blk_DEBUG_87_UNCONNECTED,
      DEBUG(86) => NLW_pcie_blk_DEBUG_86_UNCONNECTED,
      DEBUG(85) => NLW_pcie_blk_DEBUG_85_UNCONNECTED,
      DEBUG(84) => NLW_pcie_blk_DEBUG_84_UNCONNECTED,
      DEBUG(83) => NLW_pcie_blk_DEBUG_83_UNCONNECTED,
      DEBUG(82) => NLW_pcie_blk_DEBUG_82_UNCONNECTED,
      DEBUG(81) => NLW_pcie_blk_DEBUG_81_UNCONNECTED,
      DEBUG(80) => NLW_pcie_blk_DEBUG_80_UNCONNECTED,
      DEBUG(79) => NLW_pcie_blk_DEBUG_79_UNCONNECTED,
      DEBUG(78) => NLW_pcie_blk_DEBUG_78_UNCONNECTED,
      DEBUG(77) => NLW_pcie_blk_DEBUG_77_UNCONNECTED,
      DEBUG(76) => NLW_pcie_blk_DEBUG_76_UNCONNECTED,
      DEBUG(75) => NLW_pcie_blk_DEBUG_75_UNCONNECTED,
      DEBUG(74) => NLW_pcie_blk_DEBUG_74_UNCONNECTED,
      DEBUG(73) => NLW_pcie_blk_DEBUG_73_UNCONNECTED,
      DEBUG(72) => NLW_pcie_blk_DEBUG_72_UNCONNECTED,
      DEBUG(71) => NLW_pcie_blk_DEBUG_71_UNCONNECTED,
      DEBUG(70) => NLW_pcie_blk_DEBUG_70_UNCONNECTED,
      DEBUG(69) => NLW_pcie_blk_DEBUG_69_UNCONNECTED,
      DEBUG(68) => NLW_pcie_blk_DEBUG_68_UNCONNECTED,
      DEBUG(67) => NLW_pcie_blk_DEBUG_67_UNCONNECTED,
      DEBUG(66) => NLW_pcie_blk_DEBUG_66_UNCONNECTED,
      DEBUG(65) => NLW_pcie_blk_DEBUG_65_UNCONNECTED,
      DEBUG(64) => NLW_pcie_blk_DEBUG_64_UNCONNECTED,
      DEBUG(63) => NLW_pcie_blk_DEBUG_63_UNCONNECTED,
      DEBUG(62) => NLW_pcie_blk_DEBUG_62_UNCONNECTED,
      DEBUG(61) => NLW_pcie_blk_DEBUG_61_UNCONNECTED,
      DEBUG(60) => NLW_pcie_blk_DEBUG_60_UNCONNECTED,
      DEBUG(59) => NLW_pcie_blk_DEBUG_59_UNCONNECTED,
      DEBUG(58) => NLW_pcie_blk_DEBUG_58_UNCONNECTED,
      DEBUG(57) => NLW_pcie_blk_DEBUG_57_UNCONNECTED,
      DEBUG(56) => NLW_pcie_blk_DEBUG_56_UNCONNECTED,
      DEBUG(55) => NLW_pcie_blk_DEBUG_55_UNCONNECTED,
      DEBUG(54) => NLW_pcie_blk_DEBUG_54_UNCONNECTED,
      DEBUG(53) => NLW_pcie_blk_DEBUG_53_UNCONNECTED,
      DEBUG(52) => NLW_pcie_blk_DEBUG_52_UNCONNECTED,
      DEBUG(51) => NLW_pcie_blk_DEBUG_51_UNCONNECTED,
      DEBUG(50) => NLW_pcie_blk_DEBUG_50_UNCONNECTED,
      DEBUG(49) => NLW_pcie_blk_DEBUG_49_UNCONNECTED,
      DEBUG(48) => NLW_pcie_blk_DEBUG_48_UNCONNECTED,
      DEBUG(47) => NLW_pcie_blk_DEBUG_47_UNCONNECTED,
      DEBUG(46) => NLW_pcie_blk_DEBUG_46_UNCONNECTED,
      DEBUG(45) => NLW_pcie_blk_DEBUG_45_UNCONNECTED,
      DEBUG(44) => NLW_pcie_blk_DEBUG_44_UNCONNECTED,
      DEBUG(43) => NLW_pcie_blk_DEBUG_43_UNCONNECTED,
      DEBUG(42) => NLW_pcie_blk_DEBUG_42_UNCONNECTED,
      DEBUG(41) => NLW_pcie_blk_DEBUG_41_UNCONNECTED,
      DEBUG(40) => NLW_pcie_blk_DEBUG_40_UNCONNECTED,
      DEBUG(39) => NLW_pcie_blk_DEBUG_39_UNCONNECTED,
      DEBUG(38) => NLW_pcie_blk_DEBUG_38_UNCONNECTED,
      DEBUG(37) => NLW_pcie_blk_DEBUG_37_UNCONNECTED,
      DEBUG(36) => NLW_pcie_blk_DEBUG_36_UNCONNECTED,
      DEBUG(35) => NLW_pcie_blk_DEBUG_35_UNCONNECTED,
      DEBUG(34) => NLW_pcie_blk_DEBUG_34_UNCONNECTED,
      DEBUG(33) => NLW_pcie_blk_DEBUG_33_UNCONNECTED,
      DEBUG(32) => NLW_pcie_blk_DEBUG_32_UNCONNECTED,
      DEBUG(31) => NLW_pcie_blk_DEBUG_31_UNCONNECTED,
      DEBUG(30) => NLW_pcie_blk_DEBUG_30_UNCONNECTED,
      DEBUG(29) => NLW_pcie_blk_DEBUG_29_UNCONNECTED,
      DEBUG(28) => NLW_pcie_blk_DEBUG_28_UNCONNECTED,
      DEBUG(27) => NLW_pcie_blk_DEBUG_27_UNCONNECTED,
      DEBUG(26) => NLW_pcie_blk_DEBUG_26_UNCONNECTED,
      DEBUG(25) => NLW_pcie_blk_DEBUG_25_UNCONNECTED,
      DEBUG(24) => NLW_pcie_blk_DEBUG_24_UNCONNECTED,
      DEBUG(23) => NLW_pcie_blk_DEBUG_23_UNCONNECTED,
      DEBUG(22) => NLW_pcie_blk_DEBUG_22_UNCONNECTED,
      DEBUG(21) => NLW_pcie_blk_DEBUG_21_UNCONNECTED,
      DEBUG(20) => NLW_pcie_blk_DEBUG_20_UNCONNECTED,
      DEBUG(19) => NLW_pcie_blk_DEBUG_19_UNCONNECTED,
      DEBUG(18) => NLW_pcie_blk_DEBUG_18_UNCONNECTED,
      DEBUG(17) => NLW_pcie_blk_DEBUG_17_UNCONNECTED,
      DEBUG(16) => NLW_pcie_blk_DEBUG_16_UNCONNECTED,
      DEBUG(15) => NLW_pcie_blk_DEBUG_15_UNCONNECTED,
      DEBUG(14) => NLW_pcie_blk_DEBUG_14_UNCONNECTED,
      DEBUG(13) => NLW_pcie_blk_DEBUG_13_UNCONNECTED,
      DEBUG(12) => NLW_pcie_blk_DEBUG_12_UNCONNECTED,
      DEBUG(11) => NLW_pcie_blk_DEBUG_11_UNCONNECTED,
      DEBUG(10) => NLW_pcie_blk_DEBUG_10_UNCONNECTED,
      DEBUG(9) => NLW_pcie_blk_DEBUG_9_UNCONNECTED,
      DEBUG(8) => NLW_pcie_blk_DEBUG_8_UNCONNECTED,
      DEBUG(7) => NLW_pcie_blk_DEBUG_7_UNCONNECTED,
      DEBUG(6) => NLW_pcie_blk_DEBUG_6_UNCONNECTED,
      DEBUG(5) => NLW_pcie_blk_DEBUG_5_UNCONNECTED,
      DEBUG(4) => NLW_pcie_blk_DEBUG_4_UNCONNECTED,
      DEBUG(3) => NLW_pcie_blk_DEBUG_3_UNCONNECTED,
      DEBUG(2) => NLW_pcie_blk_DEBUG_2_UNCONNECTED,
      DEBUG(1) => NLW_pcie_blk_DEBUG_1_UNCONNECTED,
      DEBUG(0) => NLW_pcie_blk_DEBUG_0_UNCONNECTED,
      llk_rx_ch_non_posted_available_n(7) => llk_rx_ch_non_posted_available_n(7),
      llk_rx_ch_non_posted_available_n(6) => llk_rx_ch_non_posted_available_n(6),
      llk_rx_ch_non_posted_available_n(5) => llk_rx_ch_non_posted_available_n(5),
      llk_rx_ch_non_posted_available_n(4) => llk_rx_ch_non_posted_available_n(4),
      llk_rx_ch_non_posted_available_n(3) => llk_rx_ch_non_posted_available_n(3),
      llk_rx_ch_non_posted_available_n(2) => llk_rx_ch_non_posted_available_n(2),
      llk_rx_ch_non_posted_available_n(1) => llk_rx_ch_non_posted_available_n(1),
      llk_rx_ch_non_posted_available_n(0) => llk_rx_ch_non_posted_available_n(0),
      l0_ltssm_state(3) => fe_l0_ltssm_state(3),
      l0_ltssm_state(2) => fe_l0_ltssm_state(2),
      l0_ltssm_state(1) => fe_l0_ltssm_state(1),
      l0_ltssm_state(0) => fe_l0_ltssm_state(0),
      llk_rx_ch_completion_available_n(7) => llk_rx_ch_completion_available_n(7),
      llk_rx_ch_completion_available_n(6) => llk_rx_ch_completion_available_n(6),
      llk_rx_ch_completion_available_n(5) => llk_rx_ch_completion_available_n(5),
      llk_rx_ch_completion_available_n(4) => llk_rx_ch_completion_available_n(4),
      llk_rx_ch_completion_available_n(3) => llk_rx_ch_completion_available_n(3),
      llk_rx_ch_completion_available_n(2) => llk_rx_ch_completion_available_n(2),
      llk_rx_ch_completion_available_n(1) => llk_rx_ch_completion_available_n(1),
      llk_rx_ch_completion_available_n(0) => llk_rx_ch_completion_available_n(0),
      llk_rx_valid_n(1) => llk_rx_valid_n(1),
      llk_rx_valid_n(0) => llk_rx_valid_n(0),
      RESETDONE(7) => NLW_pcie_blk_RESETDONE_7_UNCONNECTED,
      RESETDONE(6) => NLW_pcie_blk_RESETDONE_6_UNCONNECTED,
      RESETDONE(5) => NLW_pcie_blk_RESETDONE_5_UNCONNECTED,
      RESETDONE(4) => NLW_pcie_blk_RESETDONE_4_UNCONNECTED,
      RESETDONE(3) => NLW_pcie_blk_RESETDONE_3_UNCONNECTED,
      RESETDONE(2) => NLW_pcie_blk_RESETDONE_2_UNCONNECTED,
      RESETDONE(1) => NLW_pcie_blk_RESETDONE_1_UNCONNECTED,
      RESETDONE(0) => NLW_pcie_blk_RESETDONE_0_UNCONNECTED,
      llk_rx_preferred_type(15) => llk_rx_preferred_type(15),
      llk_rx_preferred_type(14) => llk_rx_preferred_type(14),
      llk_rx_preferred_type(13) => llk_rx_preferred_type(13),
      llk_rx_preferred_type(12) => llk_rx_preferred_type(12),
      llk_rx_preferred_type(11) => llk_rx_preferred_type(11),
      llk_rx_preferred_type(10) => llk_rx_preferred_type(10),
      llk_rx_preferred_type(9) => llk_rx_preferred_type(9),
      llk_rx_preferred_type(8) => llk_rx_preferred_type(8),
      llk_rx_preferred_type(7) => llk_rx_preferred_type(7),
      llk_rx_preferred_type(6) => llk_rx_preferred_type(6),
      llk_rx_preferred_type(5) => llk_rx_preferred_type(5),
      llk_rx_preferred_type(4) => llk_rx_preferred_type(4),
      llk_rx_preferred_type(3) => llk_rx_preferred_type(3),
      llk_rx_preferred_type(2) => llk_rx_preferred_type(2),
      llk_rx_preferred_type(1) => llk_rx_preferred_type(1),
      llk_rx_preferred_type(0) => llk_rx_preferred_type(0),
      l0_dl_up_down(7) => NLW_pcie_blk_l0_dl_up_down_7_UNCONNECTED,
      l0_dl_up_down(6) => NLW_pcie_blk_l0_dl_up_down_6_UNCONNECTED,
      l0_dl_up_down(5) => NLW_pcie_blk_l0_dl_up_down_5_UNCONNECTED,
      l0_dl_up_down(4) => NLW_pcie_blk_l0_dl_up_down_4_UNCONNECTED,
      l0_dl_up_down(3) => NLW_pcie_blk_l0_dl_up_down_3_UNCONNECTED,
      l0_dl_up_down(2) => NLW_pcie_blk_l0_dl_up_down_2_UNCONNECTED,
      l0_dl_up_down(1) => NLW_pcie_blk_l0_dl_up_down_1_UNCONNECTED,
      l0_dl_up_down(0) => NLW_pcie_blk_l0_dl_up_down_0_UNCONNECTED,
      llk_tc_status(7) => llk_tc_status(7),
      llk_tc_status(6) => llk_tc_status(6),
      llk_tc_status(5) => llk_tc_status(5),
      llk_tc_status(4) => llk_tc_status(4),
      llk_tc_status(3) => llk_tc_status(3),
      llk_tc_status(2) => llk_tc_status(2),
      llk_tc_status(1) => llk_tc_status(1),
      llk_tc_status(0) => llk_tc_status(0),
      mgmt_pso(16) => mgmt_pso(16),
      mgmt_pso(15) => mgmt_pso(15),
      mgmt_pso(14) => mgmt_pso(14),
      mgmt_pso(13) => mgmt_pso(13),
      mgmt_pso(12) => mgmt_pso(12),
      mgmt_pso(11) => mgmt_pso(11),
      mgmt_pso(10) => mgmt_pso(10),
      mgmt_pso(9) => mgmt_pso(9),
      mgmt_pso(8) => mgmt_pso(8),
      mgmt_pso(7) => mgmt_pso(7),
      mgmt_pso(6) => mgmt_pso(6),
      mgmt_pso(5) => mgmt_pso(5),
      mgmt_pso(4) => mgmt_pso(4),
      mgmt_pso(3) => mgmt_pso(3),
      mgmt_pso(2) => mgmt_pso(2),
      mgmt_pso(1) => mgmt_pso(1),
      mgmt_pso(0) => mgmt_pso(0),
      l0_dll_error_vector(6) => fe_l0_dll_error_vector(6),
      l0_dll_error_vector(5) => fe_l0_dll_error_vector(5),
      l0_dll_error_vector(4) => fe_l0_dll_error_vector(4),
      l0_dll_error_vector(3) => fe_l0_dll_error_vector(3),
      l0_dll_error_vector(2) => fe_l0_dll_error_vector(2),
      l0_dll_error_vector(1) => fe_l0_dll_error_vector(1),
      l0_dll_error_vector(0) => fe_l0_dll_error_vector(0),
      llk_tx_ch_posted_ready_n(7) => llk_tx_ch_posted_ready_n(7),
      llk_tx_ch_posted_ready_n(6) => llk_tx_ch_posted_ready_n(6),
      llk_tx_ch_posted_ready_n(5) => llk_tx_ch_posted_ready_n(5),
      llk_tx_ch_posted_ready_n(4) => llk_tx_ch_posted_ready_n(4),
      llk_tx_ch_posted_ready_n(3) => llk_tx_ch_posted_ready_n(3),
      llk_tx_ch_posted_ready_n(2) => llk_tx_ch_posted_ready_n(2),
      llk_tx_ch_posted_ready_n(1) => llk_tx_ch_posted_ready_n(1),
      llk_tx_ch_posted_ready_n(0) => llk_tx_ch_posted_ready_n(0),
      l0_rx_mac_link_error(1) => fe_l0_rx_mac_link_error(1),
      l0_rx_mac_link_error(0) => fe_l0_rx_mac_link_error(0),
      max_payload_size(2) => fe_max_payload_size(2),
      max_payload_size(1) => fe_max_payload_size(1),
      max_payload_size(0) => fe_max_payload_size(0),
      TXN(7) => pci_exp_txn(7),
      TXN(6) => pci_exp_txn(6),
      TXN(5) => pci_exp_txn(5),
      TXN(4) => pci_exp_txn(4),
      TXN(3) => pci_exp_txn(3),
      TXN(2) => pci_exp_txn(2),
      TXN(1) => pci_exp_txn(1),
      TXN(0) => pci_exp_txn(0),
      TXP(7) => pci_exp_txp(7),
      TXP(6) => pci_exp_txp(6),
      TXP(5) => pci_exp_txp(5),
      TXP(4) => pci_exp_txp(4),
      TXP(3) => pci_exp_txp(3),
      TXP(2) => pci_exp_txp(2),
      TXP(1) => pci_exp_txp(1),
      TXP(0) => pci_exp_txp(0),
      PLLLKDET_OUT(3) => NLW_pcie_blk_PLLLKDET_OUT_3_UNCONNECTED,
      PLLLKDET_OUT(2) => NLW_pcie_blk_PLLLKDET_OUT_2_UNCONNECTED,
      PLLLKDET_OUT(1) => NLW_pcie_blk_PLLLKDET_OUT_1_UNCONNECTED,
      PLLLKDET_OUT(0) => PLLLKDET_OUT(0),
      llk_tx_chan_space(9) => llk_tx_chan_space(9),
      llk_tx_chan_space(8) => llk_tx_chan_space(8),
      llk_tx_chan_space(7) => llk_tx_chan_space(7),
      llk_tx_chan_space(6) => llk_tx_chan_space(6),
      llk_tx_chan_space(5) => llk_tx_chan_space(5),
      llk_tx_chan_space(4) => llk_tx_chan_space(4),
      llk_tx_chan_space(3) => llk_tx_chan_space(3),
      llk_tx_chan_space(2) => llk_tx_chan_space(2),
      llk_tx_chan_space(1) => llk_tx_chan_space(1),
      llk_tx_chan_space(0) => llk_tx_chan_space(0),
      mgmt_stats_credit(11) => mgmt_stats_credit(11),
      mgmt_stats_credit(10) => mgmt_stats_credit(10),
      mgmt_stats_credit(9) => mgmt_stats_credit(9),
      mgmt_stats_credit(8) => mgmt_stats_credit(8),
      mgmt_stats_credit(7) => mgmt_stats_credit(7),
      mgmt_stats_credit(6) => mgmt_stats_credit(6),
      mgmt_stats_credit(5) => mgmt_stats_credit(5),
      mgmt_stats_credit(4) => mgmt_stats_credit(4),
      mgmt_stats_credit(3) => mgmt_stats_credit(3),
      mgmt_stats_credit(2) => mgmt_stats_credit(2),
      mgmt_stats_credit(1) => mgmt_stats_credit(1),
      mgmt_stats_credit(0) => mgmt_stats_credit(0),
      l0_multi_msg_en0(2) => NLW_pcie_blk_l0_multi_msg_en0_2_UNCONNECTED,
      l0_multi_msg_en0(1) => NLW_pcie_blk_l0_multi_msg_en0_1_UNCONNECTED,
      l0_multi_msg_en0(0) => NLW_pcie_blk_l0_multi_msg_en0_0_UNCONNECTED,
      gt_drdy(7) => gt_drdy(7),
      gt_drdy(6) => gt_drdy(6),
      gt_drdy(5) => gt_drdy(5),
      gt_drdy(4) => gt_drdy(4),
      gt_drdy(3) => gt_drdy(3),
      gt_drdy(2) => gt_drdy(2),
      gt_drdy(1) => gt_drdy(1),
      gt_drdy(0) => gt_drdy(0),
      mgmt_rdata(31) => mgmt_rdata(31),
      mgmt_rdata(30) => mgmt_rdata(30),
      mgmt_rdata(29) => mgmt_rdata(29),
      mgmt_rdata(28) => mgmt_rdata(28),
      mgmt_rdata(27) => mgmt_rdata(27),
      mgmt_rdata(26) => mgmt_rdata(26),
      mgmt_rdata(25) => mgmt_rdata(25),
      mgmt_rdata(24) => mgmt_rdata(24),
      mgmt_rdata(23) => mgmt_rdata(23),
      mgmt_rdata(22) => mgmt_rdata(22),
      mgmt_rdata(21) => mgmt_rdata(21),
      mgmt_rdata(20) => mgmt_rdata(20),
      mgmt_rdata(19) => mgmt_rdata(19),
      mgmt_rdata(18) => mgmt_rdata(18),
      mgmt_rdata(17) => mgmt_rdata(17),
      mgmt_rdata(16) => mgmt_rdata(16),
      mgmt_rdata(15) => mgmt_rdata(15),
      mgmt_rdata(14) => mgmt_rdata(14),
      mgmt_rdata(13) => mgmt_rdata(13),
      mgmt_rdata(12) => mgmt_rdata(12),
      mgmt_rdata(11) => mgmt_rdata(11),
      mgmt_rdata(10) => mgmt_rdata(10),
      mgmt_rdata(9) => mgmt_rdata(9),
      mgmt_rdata(8) => mgmt_rdata(8),
      mgmt_rdata(7) => mgmt_rdata(7),
      mgmt_rdata(6) => mgmt_rdata(6),
      mgmt_rdata(5) => mgmt_rdata(5),
      mgmt_rdata(4) => mgmt_rdata(4),
      mgmt_rdata(3) => mgmt_rdata(3),
      mgmt_rdata(2) => mgmt_rdata(2),
      mgmt_rdata(1) => mgmt_rdata(1),
      mgmt_rdata(0) => mgmt_rdata(0),
      llk_tx_ch_completion_ready_n(7) => llk_tx_ch_completion_ready_n(7),
      llk_tx_ch_completion_ready_n(6) => llk_tx_ch_completion_ready_n(6),
      llk_tx_ch_completion_ready_n(5) => llk_tx_ch_completion_ready_n(5),
      llk_tx_ch_completion_ready_n(4) => llk_tx_ch_completion_ready_n(4),
      llk_tx_ch_completion_ready_n(3) => llk_tx_ch_completion_ready_n(3),
      llk_tx_ch_completion_ready_n(2) => llk_tx_ch_completion_ready_n(2),
      llk_tx_ch_completion_ready_n(1) => llk_tx_ch_completion_ready_n(1),
      llk_tx_ch_completion_ready_n(0) => llk_tx_ch_completion_ready_n(0),
      max_read_request_size(2) => fe_max_read_request_size(2),
      max_read_request_size(1) => fe_max_read_request_size(1),
      max_read_request_size(0) => fe_max_read_request_size(0),
      gt_do(127) => gt_do(127),
      gt_do(126) => gt_do(126),
      gt_do(125) => gt_do(125),
      gt_do(124) => gt_do(124),
      gt_do(123) => gt_do(123),
      gt_do(122) => gt_do(122),
      gt_do(121) => gt_do(121),
      gt_do(120) => gt_do(120),
      gt_do(119) => gt_do(119),
      gt_do(118) => gt_do(118),
      gt_do(117) => gt_do(117),
      gt_do(116) => gt_do(116),
      gt_do(115) => gt_do(115),
      gt_do(114) => gt_do(114),
      gt_do(113) => gt_do(113),
      gt_do(112) => gt_do(112),
      gt_do(111) => gt_do(111),
      gt_do(110) => gt_do(110),
      gt_do(109) => gt_do(109),
      gt_do(108) => gt_do(108),
      gt_do(107) => gt_do(107),
      gt_do(106) => gt_do(106),
      gt_do(105) => gt_do(105),
      gt_do(104) => gt_do(104),
      gt_do(103) => gt_do(103),
      gt_do(102) => gt_do(102),
      gt_do(101) => gt_do(101),
      gt_do(100) => gt_do(100),
      gt_do(99) => gt_do(99),
      gt_do(98) => gt_do(98),
      gt_do(97) => gt_do(97),
      gt_do(96) => gt_do(96),
      gt_do(95) => gt_do(95),
      gt_do(94) => gt_do(94),
      gt_do(93) => gt_do(93),
      gt_do(92) => gt_do(92),
      gt_do(91) => gt_do(91),
      gt_do(90) => gt_do(90),
      gt_do(89) => gt_do(89),
      gt_do(88) => gt_do(88),
      gt_do(87) => gt_do(87),
      gt_do(86) => gt_do(86),
      gt_do(85) => gt_do(85),
      gt_do(84) => gt_do(84),
      gt_do(83) => gt_do(83),
      gt_do(82) => gt_do(82),
      gt_do(81) => gt_do(81),
      gt_do(80) => gt_do(80),
      gt_do(79) => gt_do(79),
      gt_do(78) => gt_do(78),
      gt_do(77) => gt_do(77),
      gt_do(76) => gt_do(76),
      gt_do(75) => gt_do(75),
      gt_do(74) => gt_do(74),
      gt_do(73) => gt_do(73),
      gt_do(72) => gt_do(72),
      gt_do(71) => gt_do(71),
      gt_do(70) => gt_do(70),
      gt_do(69) => gt_do(69),
      gt_do(68) => gt_do(68),
      gt_do(67) => gt_do(67),
      gt_do(66) => gt_do(66),
      gt_do(65) => gt_do(65),
      gt_do(64) => gt_do(64),
      gt_do(63) => gt_do(63),
      gt_do(62) => gt_do(62),
      gt_do(61) => gt_do(61),
      gt_do(60) => gt_do(60),
      gt_do(59) => gt_do(59),
      gt_do(58) => gt_do(58),
      gt_do(57) => gt_do(57),
      gt_do(56) => gt_do(56),
      gt_do(55) => gt_do(55),
      gt_do(54) => gt_do(54),
      gt_do(53) => gt_do(53),
      gt_do(52) => gt_do(52),
      gt_do(51) => gt_do(51),
      gt_do(50) => gt_do(50),
      gt_do(49) => gt_do(49),
      gt_do(48) => gt_do(48),
      gt_do(47) => gt_do(47),
      gt_do(46) => gt_do(46),
      gt_do(45) => gt_do(45),
      gt_do(44) => gt_do(44),
      gt_do(43) => gt_do(43),
      gt_do(42) => gt_do(42),
      gt_do(41) => gt_do(41),
      gt_do(40) => gt_do(40),
      gt_do(39) => gt_do(39),
      gt_do(38) => gt_do(38),
      gt_do(37) => gt_do(37),
      gt_do(36) => gt_do(36),
      gt_do(35) => gt_do(35),
      gt_do(34) => gt_do(34),
      gt_do(33) => gt_do(33),
      gt_do(32) => gt_do(32),
      gt_do(31) => gt_do(31),
      gt_do(30) => gt_do(30),
      gt_do(29) => gt_do(29),
      gt_do(28) => gt_do(28),
      gt_do(27) => gt_do(27),
      gt_do(26) => gt_do(26),
      gt_do(25) => gt_do(25),
      gt_do(24) => gt_do(24),
      gt_do(23) => gt_do(23),
      gt_do(22) => gt_do(22),
      gt_do(21) => gt_do(21),
      gt_do(20) => gt_do(20),
      gt_do(19) => gt_do(19),
      gt_do(18) => gt_do(18),
      gt_do(17) => gt_do(17),
      gt_do(16) => gt_do(16),
      gt_do(15) => gt_do(15),
      gt_do(14) => gt_do(14),
      gt_do(13) => gt_do(13),
      gt_do(12) => gt_do(12),
      gt_do(11) => gt_do(11),
      gt_do(10) => gt_do(10),
      gt_do(9) => gt_do(9),
      gt_do(8) => gt_do(8),
      gt_do(7) => gt_do(7),
      gt_do(6) => gt_do(6),
      gt_do(5) => gt_do(5),
      gt_do(4) => gt_do(4),
      gt_do(3) => gt_do(3),
      gt_do(2) => gt_do(2),
      gt_do(1) => gt_do(1),
      gt_do(0) => gt_do(0),
      l0_mac_negotiated_link_width(3) => fe_l0_mac_negotiated_link_width(3),
      l0_mac_negotiated_link_width(2) => fe_l0_mac_negotiated_link_width(2),
      l0_mac_negotiated_link_width(1) => fe_l0_mac_negotiated_link_width(1),
      l0_mac_negotiated_link_width(0) => fe_l0_mac_negotiated_link_width(0),
      l0_completer_id(12) => fe_l0_completer_id(12),
      l0_completer_id(11) => fe_l0_completer_id(11),
      l0_completer_id(10) => fe_l0_completer_id(10),
      l0_completer_id(9) => fe_l0_completer_id(9),
      l0_completer_id(8) => fe_l0_completer_id(8),
      l0_completer_id(7) => fe_l0_completer_id(7),
      l0_completer_id(6) => fe_l0_completer_id(6),
      l0_completer_id(5) => fe_l0_completer_id(5),
      l0_completer_id(4) => fe_l0_completer_id(4),
      l0_completer_id(3) => fe_l0_completer_id(3),
      l0_completer_id(2) => fe_l0_completer_id(2),
      l0_completer_id(1) => fe_l0_completer_id(1),
      l0_completer_id(0) => fe_l0_completer_id(0),
      llk_rx_data(63) => llk_rx_data(63),
      llk_rx_data(62) => llk_rx_data(62),
      llk_rx_data(61) => llk_rx_data(61),
      llk_rx_data(60) => llk_rx_data(60),
      llk_rx_data(59) => llk_rx_data(59),
      llk_rx_data(58) => llk_rx_data(58),
      llk_rx_data(57) => llk_rx_data(57),
      llk_rx_data(56) => llk_rx_data(56),
      llk_rx_data(55) => llk_rx_data(55),
      llk_rx_data(54) => llk_rx_data(54),
      llk_rx_data(53) => llk_rx_data(53),
      llk_rx_data(52) => llk_rx_data(52),
      llk_rx_data(51) => llk_rx_data(51),
      llk_rx_data(50) => llk_rx_data(50),
      llk_rx_data(49) => llk_rx_data(49),
      llk_rx_data(48) => llk_rx_data(48),
      llk_rx_data(47) => llk_rx_data(47),
      llk_rx_data(46) => llk_rx_data(46),
      llk_rx_data(45) => llk_rx_data(45),
      llk_rx_data(44) => llk_rx_data(44),
      llk_rx_data(43) => llk_rx_data(43),
      llk_rx_data(42) => llk_rx_data(42),
      llk_rx_data(41) => llk_rx_data(41),
      llk_rx_data(40) => llk_rx_data(40),
      llk_rx_data(39) => llk_rx_data(39),
      llk_rx_data(38) => llk_rx_data(38),
      llk_rx_data(37) => llk_rx_data(37),
      llk_rx_data(36) => llk_rx_data(36),
      llk_rx_data(35) => llk_rx_data(35),
      llk_rx_data(34) => llk_rx_data(34),
      llk_rx_data(33) => llk_rx_data(33),
      llk_rx_data(32) => llk_rx_data(32),
      llk_rx_data(31) => llk_rx_data(31),
      llk_rx_data(30) => llk_rx_data(30),
      llk_rx_data(29) => llk_rx_data(29),
      llk_rx_data(28) => llk_rx_data(28),
      llk_rx_data(27) => llk_rx_data(27),
      llk_rx_data(26) => llk_rx_data(26),
      llk_rx_data(25) => llk_rx_data(25),
      llk_rx_data(24) => llk_rx_data(24),
      llk_rx_data(23) => llk_rx_data(23),
      llk_rx_data(22) => llk_rx_data(22),
      llk_rx_data(21) => llk_rx_data(21),
      llk_rx_data(20) => llk_rx_data(20),
      llk_rx_data(19) => llk_rx_data(19),
      llk_rx_data(18) => llk_rx_data(18),
      llk_rx_data(17) => llk_rx_data(17),
      llk_rx_data(16) => llk_rx_data(16),
      llk_rx_data(15) => llk_rx_data(15),
      llk_rx_data(14) => llk_rx_data(14),
      llk_rx_data(13) => llk_rx_data(13),
      llk_rx_data(12) => llk_rx_data(12),
      llk_rx_data(11) => llk_rx_data(11),
      llk_rx_data(10) => llk_rx_data(10),
      llk_rx_data(9) => llk_rx_data(9),
      llk_rx_data(8) => llk_rx_data(8),
      llk_rx_data(7) => llk_rx_data(7),
      llk_rx_data(6) => llk_rx_data(6),
      llk_rx_data(5) => llk_rx_data(5),
      llk_rx_data(4) => llk_rx_data(4),
      llk_rx_data(3) => llk_rx_data(3),
      llk_rx_data(2) => llk_rx_data(2),
      llk_rx_data(1) => llk_rx_data(1),
      llk_rx_data(0) => llk_rx_data(0),
      gt_rx_present(7) => mgmt_rst_delay_n,
      gt_rx_present(6) => mgmt_rst_delay_n,
      gt_rx_present(5) => mgmt_rst_delay_n,
      gt_rx_present(4) => mgmt_rst_delay_n,
      gt_rx_present(3) => mgmt_rst_delay_n,
      gt_rx_present(2) => mgmt_rst_delay_n,
      gt_rx_present(1) => mgmt_rst_delay_n,
      gt_rx_present(0) => mgmt_rst_delay_n,
      mgmt_bwren(3) => bridge_mgmt_bwren(3),
      mgmt_bwren(2) => bridge_mgmt_bwren(2),
      mgmt_bwren(1) => bridge_mgmt_bwren(1),
      mgmt_bwren(0) => bridge_mgmt_bwren(0),
      mgmt_addr(10) => bridge_mgmt_addr(9),
      mgmt_addr(9) => fe_compliance_avoid,
      mgmt_addr(8) => bridge_mgmt_addr(8),
      mgmt_addr(7) => bridge_mgmt_addr(7),
      mgmt_addr(6) => bridge_mgmt_addr(6),
      mgmt_addr(5) => bridge_mgmt_addr(5),
      mgmt_addr(4) => bridge_mgmt_addr(4),
      mgmt_addr(3) => bridge_mgmt_addr(3),
      mgmt_addr(2) => bridge_mgmt_addr(2),
      mgmt_addr(1) => bridge_mgmt_addr(1),
      mgmt_addr(0) => bridge_mgmt_addr(0),
      gt_den(7) => fe_compliance_avoid,
      gt_den(6) => fe_compliance_avoid,
      gt_den(5) => fe_compliance_avoid,
      gt_den(4) => fe_compliance_avoid,
      gt_den(3) => fe_compliance_avoid,
      gt_den(2) => fe_compliance_avoid,
      gt_den(1) => fe_compliance_avoid,
      gt_den(0) => fe_compliance_avoid,
      l0_msi_request0(3) => fe_l0_msi_request0(3),
      l0_msi_request0(2) => fe_l0_msi_request0(2),
      l0_msi_request0(1) => fe_l0_msi_request0(1),
      l0_msi_request0(0) => fe_l0_msi_request0(0),
      RXN(7) => pci_exp_rxn(7),
      RXN(6) => pci_exp_rxn(6),
      RXN(5) => pci_exp_rxn(5),
      RXN(4) => pci_exp_rxn(4),
      RXN(3) => pci_exp_rxn(3),
      RXN(2) => pci_exp_rxn(2),
      RXN(1) => pci_exp_rxn(1),
      RXN(0) => pci_exp_rxn(0),
      gt_dwen(7) => fe_compliance_avoid,
      gt_dwen(6) => fe_compliance_avoid,
      gt_dwen(5) => fe_compliance_avoid,
      gt_dwen(4) => fe_compliance_avoid,
      gt_dwen(3) => fe_compliance_avoid,
      gt_dwen(2) => fe_compliance_avoid,
      gt_dwen(1) => fe_compliance_avoid,
      gt_dwen(0) => fe_compliance_avoid,
      RXP(7) => pci_exp_rxp(7),
      RXP(6) => pci_exp_rxp(6),
      RXP(5) => pci_exp_rxp(5),
      RXP(4) => pci_exp_rxp(4),
      RXP(3) => pci_exp_rxp(3),
      RXP(2) => pci_exp_rxp(2),
      RXP(1) => pci_exp_rxp(1),
      RXP(0) => pci_exp_rxp(0),
      gt_daddr(55) => gt_daddr(55),
      gt_daddr(54) => gt_daddr(54),
      gt_daddr(53) => gt_daddr(53),
      gt_daddr(52) => gt_daddr(52),
      gt_daddr(51) => gt_daddr(51),
      gt_daddr(50) => gt_daddr(50),
      gt_daddr(49) => gt_daddr(49),
      gt_daddr(48) => gt_daddr(48),
      gt_daddr(47) => gt_daddr(47),
      gt_daddr(46) => gt_daddr(46),
      gt_daddr(45) => gt_daddr(45),
      gt_daddr(44) => gt_daddr(44),
      gt_daddr(43) => gt_daddr(43),
      gt_daddr(42) => gt_daddr(42),
      gt_daddr(41) => gt_daddr(41),
      gt_daddr(40) => gt_daddr(40),
      gt_daddr(39) => gt_daddr(39),
      gt_daddr(38) => gt_daddr(38),
      gt_daddr(37) => gt_daddr(37),
      gt_daddr(36) => gt_daddr(36),
      gt_daddr(35) => gt_daddr(35),
      gt_daddr(34) => gt_daddr(34),
      gt_daddr(33) => gt_daddr(33),
      gt_daddr(32) => gt_daddr(32),
      gt_daddr(31) => gt_daddr(31),
      gt_daddr(30) => gt_daddr(30),
      gt_daddr(29) => gt_daddr(29),
      gt_daddr(28) => gt_daddr(28),
      gt_daddr(27) => gt_daddr(27),
      gt_daddr(26) => gt_daddr(26),
      gt_daddr(25) => gt_daddr(25),
      gt_daddr(24) => gt_daddr(24),
      gt_daddr(23) => gt_daddr(23),
      gt_daddr(22) => gt_daddr(22),
      gt_daddr(21) => gt_daddr(21),
      gt_daddr(20) => gt_daddr(20),
      gt_daddr(19) => gt_daddr(19),
      gt_daddr(18) => gt_daddr(18),
      gt_daddr(17) => gt_daddr(17),
      gt_daddr(16) => gt_daddr(16),
      gt_daddr(15) => gt_daddr(15),
      gt_daddr(14) => gt_daddr(14),
      gt_daddr(13) => gt_daddr(13),
      gt_daddr(12) => gt_daddr(12),
      gt_daddr(11) => gt_daddr(11),
      gt_daddr(10) => gt_daddr(10),
      gt_daddr(9) => gt_daddr(9),
      gt_daddr(8) => gt_daddr(8),
      gt_daddr(7) => gt_daddr(7),
      gt_daddr(6) => gt_daddr(6),
      gt_daddr(5) => gt_daddr(5),
      gt_daddr(4) => gt_daddr(4),
      gt_daddr(3) => gt_daddr(3),
      gt_daddr(2) => gt_daddr(2),
      gt_daddr(1) => gt_daddr(1),
      gt_daddr(0) => gt_daddr(0),
      llk_tx_ch_tc(2) => llk_tx_ch_tc(2),
      llk_tx_ch_tc(1) => llk_tx_ch_tc(1),
      llk_tx_ch_tc(0) => llk_tx_ch_tc(0),
      llk_tx_ch_fifo(1) => llk_tx_ch_fifo(1),
      llk_tx_ch_fifo(0) => llk_tx_ch_fifo(0),
      gt_txbuffctrl_0(2) => mgmt_rst_delay_n,
      gt_txbuffctrl_0(1) => fe_compliance_avoid,
      gt_txbuffctrl_0(0) => fe_compliance_avoid,
      gt_txbuffctrl_1(2) => mgmt_rst_delay_n,
      gt_txbuffctrl_1(1) => fe_compliance_avoid,
      gt_txbuffctrl_1(0) => fe_compliance_avoid,
      gt_txdiffctrl_0(2) => mgmt_rst_delay_n,
      gt_txdiffctrl_0(1) => fe_compliance_avoid,
      gt_txdiffctrl_0(0) => fe_compliance_avoid,
      gt_txdiffctrl_1(2) => mgmt_rst_delay_n,
      gt_txdiffctrl_1(1) => fe_compliance_avoid,
      gt_txdiffctrl_1(0) => fe_compliance_avoid,
      gt_txpreemphesis_0(2) => mgmt_rst_delay_n,
      gt_txpreemphesis_0(1) => mgmt_rst_delay_n,
      gt_txpreemphesis_0(0) => mgmt_rst_delay_n,
      gt_txpreemphesis_1(2) => mgmt_rst_delay_n,
      gt_txpreemphesis_1(1) => mgmt_rst_delay_n,
      gt_txpreemphesis_1(0) => mgmt_rst_delay_n,
      gt_di(127) => gt_di(127),
      gt_di(126) => gt_di(126),
      gt_di(125) => gt_di(125),
      gt_di(124) => gt_di(124),
      gt_di(123) => gt_di(123),
      gt_di(122) => gt_di(122),
      gt_di(121) => gt_di(121),
      gt_di(120) => gt_di(120),
      gt_di(119) => gt_di(119),
      gt_di(118) => gt_di(118),
      gt_di(117) => gt_di(117),
      gt_di(116) => gt_di(116),
      gt_di(115) => gt_di(115),
      gt_di(114) => gt_di(114),
      gt_di(113) => gt_di(113),
      gt_di(112) => gt_di(112),
      gt_di(111) => gt_di(111),
      gt_di(110) => gt_di(110),
      gt_di(109) => gt_di(109),
      gt_di(108) => gt_di(108),
      gt_di(107) => gt_di(107),
      gt_di(106) => gt_di(106),
      gt_di(105) => gt_di(105),
      gt_di(104) => gt_di(104),
      gt_di(103) => gt_di(103),
      gt_di(102) => gt_di(102),
      gt_di(101) => gt_di(101),
      gt_di(100) => gt_di(100),
      gt_di(99) => gt_di(99),
      gt_di(98) => gt_di(98),
      gt_di(97) => gt_di(97),
      gt_di(96) => gt_di(96),
      gt_di(95) => gt_di(95),
      gt_di(94) => gt_di(94),
      gt_di(93) => gt_di(93),
      gt_di(92) => gt_di(92),
      gt_di(91) => gt_di(91),
      gt_di(90) => gt_di(90),
      gt_di(89) => gt_di(89),
      gt_di(88) => gt_di(88),
      gt_di(87) => gt_di(87),
      gt_di(86) => gt_di(86),
      gt_di(85) => gt_di(85),
      gt_di(84) => gt_di(84),
      gt_di(83) => gt_di(83),
      gt_di(82) => gt_di(82),
      gt_di(81) => gt_di(81),
      gt_di(80) => gt_di(80),
      gt_di(79) => gt_di(79),
      gt_di(78) => gt_di(78),
      gt_di(77) => gt_di(77),
      gt_di(76) => gt_di(76),
      gt_di(75) => gt_di(75),
      gt_di(74) => gt_di(74),
      gt_di(73) => gt_di(73),
      gt_di(72) => gt_di(72),
      gt_di(71) => gt_di(71),
      gt_di(70) => gt_di(70),
      gt_di(69) => gt_di(69),
      gt_di(68) => gt_di(68),
      gt_di(67) => gt_di(67),
      gt_di(66) => gt_di(66),
      gt_di(65) => gt_di(65),
      gt_di(64) => gt_di(64),
      gt_di(63) => gt_di(63),
      gt_di(62) => gt_di(62),
      gt_di(61) => gt_di(61),
      gt_di(60) => gt_di(60),
      gt_di(59) => gt_di(59),
      gt_di(58) => gt_di(58),
      gt_di(57) => gt_di(57),
      gt_di(56) => gt_di(56),
      gt_di(55) => gt_di(55),
      gt_di(54) => gt_di(54),
      gt_di(53) => gt_di(53),
      gt_di(52) => gt_di(52),
      gt_di(51) => gt_di(51),
      gt_di(50) => gt_di(50),
      gt_di(49) => gt_di(49),
      gt_di(48) => gt_di(48),
      gt_di(47) => gt_di(47),
      gt_di(46) => gt_di(46),
      gt_di(45) => gt_di(45),
      gt_di(44) => gt_di(44),
      gt_di(43) => gt_di(43),
      gt_di(42) => gt_di(42),
      gt_di(41) => gt_di(41),
      gt_di(40) => gt_di(40),
      gt_di(39) => gt_di(39),
      gt_di(38) => gt_di(38),
      gt_di(37) => gt_di(37),
      gt_di(36) => gt_di(36),
      gt_di(35) => gt_di(35),
      gt_di(34) => gt_di(34),
      gt_di(33) => gt_di(33),
      gt_di(32) => gt_di(32),
      gt_di(31) => gt_di(31),
      gt_di(30) => gt_di(30),
      gt_di(29) => gt_di(29),
      gt_di(28) => gt_di(28),
      gt_di(27) => gt_di(27),
      gt_di(26) => gt_di(26),
      gt_di(25) => gt_di(25),
      gt_di(24) => gt_di(24),
      gt_di(23) => gt_di(23),
      gt_di(22) => gt_di(22),
      gt_di(21) => gt_di(21),
      gt_di(20) => gt_di(20),
      gt_di(19) => gt_di(19),
      gt_di(18) => gt_di(18),
      gt_di(17) => gt_di(17),
      gt_di(16) => gt_di(16),
      gt_di(15) => gt_di(15),
      gt_di(14) => gt_di(14),
      gt_di(13) => gt_di(13),
      gt_di(12) => gt_di(12),
      gt_di(11) => gt_di(11),
      gt_di(10) => gt_di(10),
      gt_di(9) => gt_di(9),
      gt_di(8) => gt_di(8),
      gt_di(7) => gt_di(7),
      gt_di(6) => gt_di(6),
      gt_di(5) => gt_di(5),
      gt_di(4) => gt_di(4),
      gt_di(3) => gt_di(3),
      gt_di(2) => gt_di(2),
      gt_di(1) => gt_di(1),
      gt_di(0) => gt_di(0),
      llk_tx_enable_n(1) => llk_tx_enable_n(1),
      llk_tx_enable_n(0) => llk_tx_enable_n(0),
      llk_rx_ch_fifo(1) => llk_rx_ch_fifo(1),
      llk_rx_ch_fifo(0) => llk_rx_ch_fifo(0),
      mgmt_stats_credit_sel(6) => mgmt_stats_credit_sel(6),
      mgmt_stats_credit_sel(5) => mgmt_stats_credit_sel(5),
      mgmt_stats_credit_sel(4) => mgmt_stats_credit_sel(4),
      mgmt_stats_credit_sel(3) => mgmt_stats_credit_sel(3),
      mgmt_stats_credit_sel(2) => mgmt_stats_credit_sel(2),
      mgmt_stats_credit_sel(1) => mgmt_stats_credit_sel(1),
      mgmt_stats_credit_sel(0) => mgmt_stats_credit_sel(0),
      llk_tx_data(63) => llk_tx_data(63),
      llk_tx_data(62) => llk_tx_data(62),
      llk_tx_data(61) => llk_tx_data(61),
      llk_tx_data(60) => llk_tx_data(60),
      llk_tx_data(59) => llk_tx_data(59),
      llk_tx_data(58) => llk_tx_data(58),
      llk_tx_data(57) => llk_tx_data(57),
      llk_tx_data(56) => llk_tx_data(56),
      llk_tx_data(55) => llk_tx_data(55),
      llk_tx_data(54) => llk_tx_data(54),
      llk_tx_data(53) => llk_tx_data(53),
      llk_tx_data(52) => llk_tx_data(52),
      llk_tx_data(51) => llk_tx_data(51),
      llk_tx_data(50) => llk_tx_data(50),
      llk_tx_data(49) => llk_tx_data(49),
      llk_tx_data(48) => llk_tx_data(48),
      llk_tx_data(47) => llk_tx_data(47),
      llk_tx_data(46) => llk_tx_data(46),
      llk_tx_data(45) => llk_tx_data(45),
      llk_tx_data(44) => llk_tx_data(44),
      llk_tx_data(43) => llk_tx_data(43),
      llk_tx_data(42) => llk_tx_data(42),
      llk_tx_data(41) => llk_tx_data(41),
      llk_tx_data(40) => llk_tx_data(40),
      llk_tx_data(39) => llk_tx_data(39),
      llk_tx_data(38) => llk_tx_data(38),
      llk_tx_data(37) => llk_tx_data(37),
      llk_tx_data(36) => llk_tx_data(36),
      llk_tx_data(35) => llk_tx_data(35),
      llk_tx_data(34) => llk_tx_data(34),
      llk_tx_data(33) => llk_tx_data(33),
      llk_tx_data(32) => llk_tx_data(32),
      llk_tx_data(31) => llk_tx_data(31),
      llk_tx_data(30) => llk_tx_data(30),
      llk_tx_data(29) => llk_tx_data(29),
      llk_tx_data(28) => llk_tx_data(28),
      llk_tx_data(27) => llk_tx_data(27),
      llk_tx_data(26) => llk_tx_data(26),
      llk_tx_data(25) => llk_tx_data(25),
      llk_tx_data(24) => llk_tx_data(24),
      llk_tx_data(23) => llk_tx_data(23),
      llk_tx_data(22) => llk_tx_data(22),
      llk_tx_data(21) => llk_tx_data(21),
      llk_tx_data(20) => llk_tx_data(20),
      llk_tx_data(19) => llk_tx_data(19),
      llk_tx_data(18) => llk_tx_data(18),
      llk_tx_data(17) => llk_tx_data(17),
      llk_tx_data(16) => llk_tx_data(16),
      llk_tx_data(15) => llk_tx_data(15),
      llk_tx_data(14) => llk_tx_data(14),
      llk_tx_data(13) => llk_tx_data(13),
      llk_tx_data(12) => llk_tx_data(12),
      llk_tx_data(11) => llk_tx_data(11),
      llk_tx_data(10) => llk_tx_data(10),
      llk_tx_data(9) => llk_tx_data(9),
      llk_tx_data(8) => llk_tx_data(8),
      llk_tx_data(7) => llk_tx_data(7),
      llk_tx_data(6) => llk_tx_data(6),
      llk_tx_data(5) => llk_tx_data(5),
      llk_tx_data(4) => llk_tx_data(4),
      llk_tx_data(3) => llk_tx_data(3),
      llk_tx_data(2) => llk_tx_data(2),
      llk_tx_data(1) => llk_tx_data(1),
      llk_tx_data(0) => llk_tx_data(0),
      llk_rx_ch_tc(2) => llk_rx_ch_tc(2),
      llk_rx_ch_tc(1) => llk_rx_ch_tc(1),
      llk_rx_ch_tc(0) => llk_rx_ch_tc(0),
      mgmt_wdata(31) => bridge_mgmt_wdata(31),
      mgmt_wdata(30) => bridge_mgmt_wdata(30),
      mgmt_wdata(29) => bridge_mgmt_wdata(29),
      mgmt_wdata(28) => bridge_mgmt_wdata(28),
      mgmt_wdata(27) => bridge_mgmt_wdata(27),
      mgmt_wdata(26) => bridge_mgmt_wdata(26),
      mgmt_wdata(25) => bridge_mgmt_wdata(25),
      mgmt_wdata(24) => bridge_mgmt_wdata(24),
      mgmt_wdata(23) => bridge_mgmt_wdata(23),
      mgmt_wdata(22) => bridge_mgmt_wdata(22),
      mgmt_wdata(21) => bridge_mgmt_wdata(21),
      mgmt_wdata(20) => bridge_mgmt_wdata(20),
      mgmt_wdata(19) => bridge_mgmt_wdata(19),
      mgmt_wdata(18) => bridge_mgmt_wdata(18),
      mgmt_wdata(17) => bridge_mgmt_wdata(17),
      mgmt_wdata(16) => bridge_mgmt_wdata(16),
      mgmt_wdata(15) => bridge_mgmt_wdata(15),
      mgmt_wdata(14) => bridge_mgmt_wdata(14),
      mgmt_wdata(13) => bridge_mgmt_wdata(13),
      mgmt_wdata(12) => bridge_mgmt_wdata(12),
      mgmt_wdata(11) => bridge_mgmt_wdata(11),
      mgmt_wdata(10) => bridge_mgmt_wdata(10),
      mgmt_wdata(9) => bridge_mgmt_wdata(9),
      mgmt_wdata(8) => bridge_mgmt_wdata(8),
      mgmt_wdata(7) => bridge_mgmt_wdata(7),
      mgmt_wdata(6) => bridge_mgmt_wdata(6),
      mgmt_wdata(5) => bridge_mgmt_wdata(5),
      mgmt_wdata(4) => bridge_mgmt_wdata(4),
      mgmt_wdata(3) => bridge_mgmt_wdata(3),
      mgmt_wdata(2) => bridge_mgmt_wdata(2),
      mgmt_wdata(1) => bridge_mgmt_wdata(1),
      mgmt_wdata(0) => bridge_mgmt_wdata(0)
    );
  app_reset_n_flt_reg_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => trn_lnk_up_n_reg_31488,
      I1 => mgt_reset_n_flt_reg_31450,
      O => app_reset_n_flt_reg_and0000
    );
  mgt_reset_n1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => PLLLKDET_OUT(0),
      I1 => clock_lock,
      I2 => sys_reset_n,
      O => mgt_reset_n
    );
  trn_reset_n1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => mgt_reset_n_flt_reg_31450,
      I1 => mgmt_rdy,
      O => trn_reset_n
    );
  GTPRESET1_INV_0 : INV
    port map (
      I => sys_reset_n,
      O => GTPRESET
    );
  Mshreg_trn_lnk_up_n_reg : SRLC16E
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => fe_compliance_avoid,
      A1 => fe_compliance_avoid,
      A2 => fe_compliance_avoid,
      A3 => fe_compliance_avoid,
      CE => mgmt_rst_delay_n,
      CLK => NlwRenamedSig_OI_trn_clk,
      D => NlwRenamedSig_OI_trn_lnk_up_n,
      Q => Mshreg_trn_lnk_up_n_reg_30518,
      Q15 => NLW_Mshreg_trn_lnk_up_n_reg_Q15_UNCONNECTED
    );
  trn_lnk_up_n_reg : FDE
    generic map(
      INIT => '1'
    )
    port map (
      C => NlwRenamedSig_OI_trn_clk,
      CE => mgmt_rst_delay_n,
      D => Mshreg_trn_lnk_up_n_reg_30518,
      Q => trn_lnk_up_n_reg_31488
    );
  pcie_blk_if_rx_err_tlp_p_cpl_n1_INV_0 : INV
    port map (
      I => pcie_blk_if_rx_err_tlp_p_cpl,
      O => pcie_blk_if_rx_err_tlp_p_cpl_n
    );
  pcie_blk_if_rx_err_tlp_ur_n1_INV_0 : INV
    port map (
      I => pcie_blk_if_rx_err_tlp_ur,
      O => pcie_blk_if_rx_err_tlp_ur_n
    );
  pcie_blk_if_rx_err_tlp_malformed_n1_INV_0 : INV
    port map (
      I => pcie_blk_if_err_tlp_malformed,
      O => pcie_blk_if_rx_err_tlp_malformed_n
    );
  pcie_blk_if_rx_err_tlp_ur_lock_n1_INV_0 : INV
    port map (
      I => pcie_blk_if_rx_err_tlp_ur_lock,
      O => pcie_blk_if_rx_err_tlp_ur_lock_n
    );
  pcie_blk_if_ll_bridge : pcie_blk_ll
    port map (
      rx_err_cpl_ur_n => pcie_blk_if_rx_err_cpl_ur_n,
      llk_tx_src_rdy_n => llk_tx_src_rdy_n,
      trn_rsrc_rdy_n => trn_rsrc_rdy_n,
      l0_stats_tlp_received => fe_l0_stats_tlp_received,
      trn_terrfwd_n => trn_terrfwd_n,
      clk => NlwRenamedSig_OI_trn_clk,
      llk_rx_eof_n => llk_rx_eof_n,
      rst_n => app_reset_n_30520,
      cfg_tx_dst_rdy_n => pcie_blk_if_cfg_arb_tdst_rdy_n,
      llk_rx_src_rdy_n => llk_rx_src_rdy_n,
      trn_rerrfwd_n => trn_rerrfwd_n,
      llk_rx_dst_cont_req_n => llk_rx_dst_cont_req_n,
      cfg_tx_eof_n => pcie_blk_if_cfg_arb_teof_n,
      trn_rnp_ok_n => NLW_pcie_blk_if_ll_bridge_trn_rnp_ok_n_UNCONNECTED,
      trn_tsrc_dsc_n => trn_tsrc_dsc_n,
      err_tlp_malformed => pcie_blk_if_err_tlp_malformed,
      llk_tx_sop_n => pcie_blk_if_llk_tx_sop_n,
      trn_tdst_rdy_n => trn_tdst_rdy_n,
      err_tlp_ur_lock => pcie_blk_if_rx_err_tlp_ur_lock,
      trn_rsof_n => trn_rsof_n,
      io_space_enable => NlwRenamedSig_OI_cfg_command(0),
      llk_rx_dst_req_n => llk_rx_dst_req_n,
      llk_rx_src_last_req_n => llk_rx_src_last_req_n,
      trn_teof_n => trn_teof_n,
      trn_rcpl_streaming_n => trn_rcpl_streaming_n,
      llk_rx_sof_n => llk_rx_sof_n,
      rx_err_cpl_ep_n => pcie_blk_if_rx_err_cpl_ep_n,
      cfg_tx_src_rdy_n => pcie_blk_if_cfg_arb_tsrc_rdy_n,
      l0_stats_cfg_transmitted => fe_l0_stats_cfg_transmitted,
      err_tlp_uc => NLW_pcie_blk_if_ll_bridge_err_tlp_uc_UNCONNECTED,
      cfg_tx_sof_n => pcie_blk_if_cfg_arb_tsof_n,
      llk_tx_src_dsc_n => llk_tx_src_dsc_n,
      trn_rsrc_dsc_n => trn_rsrc_dsc_n,
      err_tlp_ur => pcie_blk_if_rx_err_tlp_ur,
      tx_err_wr_ep_n => pcie_blk_if_tx_err_wr_ep_n,
      llk_rx_src_dsc_n => NLW_pcie_blk_if_ll_bridge_llk_rx_src_dsc_n_UNCONNECTED,
      llk_tx_eof_n => llk_tx_eof_n,
      llk_tx_dst_rdy_n => llk_tx_dst_rdy_n,
      trn_rdst_rdy_n => trn_rdst_rdy_n,
      trn_tsrc_rdy_n => trn_tsrc_rdy_n,
      trn_tsof_n => trn_tsof_n,
      cfg_tx_rem_n => pcie_blk_if_cfg_arb_trem_n(0),
      rx_err_cpl_abort_n => pcie_blk_if_rx_err_cpl_abort_n,
      err_tlp_p => pcie_blk_if_rx_err_tlp_p_cpl,
      mem_space_enable => NlwRenamedSig_OI_cfg_command(1),
      trn_tdst_dsc_n => trn_tdst_dsc_n,
      rx_err_ep_n => pcie_blk_if_rx_err_ep_n,
      llk_tx_eop_n => pcie_blk_if_llk_tx_eop_n,
      trn_reof_n => trn_reof_n,
      llk_tx_sof_n => llk_tx_sof_n,
      trn_lnk_up_n => NlwRenamedSig_OI_trn_lnk_up_n,
      trn_pfc_cplh_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_7_UNCONNECTED,
      trn_pfc_cplh_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_6_UNCONNECTED,
      trn_pfc_cplh_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_5_UNCONNECTED,
      trn_pfc_cplh_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_4_UNCONNECTED,
      trn_pfc_cplh_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_3_UNCONNECTED,
      trn_pfc_cplh_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_2_UNCONNECTED,
      trn_pfc_cplh_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_1_UNCONNECTED,
      trn_pfc_cplh_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cplh_cl_0_UNCONNECTED,
      trn_pfc_npd_cl(11) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_11_UNCONNECTED,
      trn_pfc_npd_cl(10) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_10_UNCONNECTED,
      trn_pfc_npd_cl(9) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_9_UNCONNECTED,
      trn_pfc_npd_cl(8) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_8_UNCONNECTED,
      trn_pfc_npd_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_7_UNCONNECTED,
      trn_pfc_npd_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_6_UNCONNECTED,
      trn_pfc_npd_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_5_UNCONNECTED,
      trn_pfc_npd_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_4_UNCONNECTED,
      trn_pfc_npd_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_3_UNCONNECTED,
      trn_pfc_npd_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_2_UNCONNECTED,
      trn_pfc_npd_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_1_UNCONNECTED,
      trn_pfc_npd_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_npd_cl_0_UNCONNECTED,
      trn_rfc_cplh_av(7) => trn_rfc_cplh_av(7),
      trn_rfc_cplh_av(6) => trn_rfc_cplh_av(6),
      trn_rfc_cplh_av(5) => trn_rfc_cplh_av(5),
      trn_rfc_cplh_av(4) => trn_rfc_cplh_av(4),
      trn_rfc_cplh_av(3) => trn_rfc_cplh_av(3),
      trn_rfc_cplh_av(2) => trn_rfc_cplh_av(2),
      trn_rfc_cplh_av(1) => trn_rfc_cplh_av(1),
      trn_rfc_cplh_av(0) => trn_rfc_cplh_av(0),
      err_tlp_cpl_header(47) => pcie_blk_if_rx_err_tlp_hdr(47),
      err_tlp_cpl_header(46) => pcie_blk_if_rx_err_tlp_hdr(46),
      err_tlp_cpl_header(45) => pcie_blk_if_rx_err_tlp_hdr(45),
      err_tlp_cpl_header(44) => pcie_blk_if_rx_err_tlp_hdr(44),
      err_tlp_cpl_header(43) => pcie_blk_if_rx_err_tlp_hdr(43),
      err_tlp_cpl_header(42) => pcie_blk_if_rx_err_tlp_hdr(42),
      err_tlp_cpl_header(41) => pcie_blk_if_rx_err_tlp_hdr(41),
      err_tlp_cpl_header(40) => pcie_blk_if_rx_err_tlp_hdr(40),
      err_tlp_cpl_header(39) => pcie_blk_if_rx_err_tlp_hdr(39),
      err_tlp_cpl_header(38) => pcie_blk_if_rx_err_tlp_hdr(38),
      err_tlp_cpl_header(37) => pcie_blk_if_rx_err_tlp_hdr(37),
      err_tlp_cpl_header(36) => pcie_blk_if_rx_err_tlp_hdr(36),
      err_tlp_cpl_header(35) => pcie_blk_if_rx_err_tlp_hdr(35),
      err_tlp_cpl_header(34) => pcie_blk_if_rx_err_tlp_hdr(34),
      err_tlp_cpl_header(33) => pcie_blk_if_rx_err_tlp_hdr(33),
      err_tlp_cpl_header(32) => pcie_blk_if_rx_err_tlp_hdr(32),
      err_tlp_cpl_header(31) => pcie_blk_if_rx_err_tlp_hdr(31),
      err_tlp_cpl_header(30) => pcie_blk_if_rx_err_tlp_hdr(30),
      err_tlp_cpl_header(29) => pcie_blk_if_rx_err_tlp_hdr(29),
      err_tlp_cpl_header(28) => pcie_blk_if_rx_err_tlp_hdr(28),
      err_tlp_cpl_header(27) => pcie_blk_if_rx_err_tlp_hdr(27),
      err_tlp_cpl_header(26) => pcie_blk_if_rx_err_tlp_hdr(26),
      err_tlp_cpl_header(25) => pcie_blk_if_rx_err_tlp_hdr(25),
      err_tlp_cpl_header(24) => pcie_blk_if_rx_err_tlp_hdr(24),
      err_tlp_cpl_header(23) => pcie_blk_if_rx_err_tlp_hdr(23),
      err_tlp_cpl_header(22) => pcie_blk_if_rx_err_tlp_hdr(22),
      err_tlp_cpl_header(21) => pcie_blk_if_rx_err_tlp_hdr(21),
      err_tlp_cpl_header(20) => pcie_blk_if_rx_err_tlp_hdr(20),
      err_tlp_cpl_header(19) => pcie_blk_if_rx_err_tlp_hdr(19),
      err_tlp_cpl_header(18) => pcie_blk_if_rx_err_tlp_hdr(18),
      err_tlp_cpl_header(17) => pcie_blk_if_rx_err_tlp_hdr(17),
      err_tlp_cpl_header(16) => pcie_blk_if_rx_err_tlp_hdr(16),
      err_tlp_cpl_header(15) => pcie_blk_if_rx_err_tlp_hdr(15),
      err_tlp_cpl_header(14) => pcie_blk_if_rx_err_tlp_hdr(14),
      err_tlp_cpl_header(13) => pcie_blk_if_rx_err_tlp_hdr(13),
      err_tlp_cpl_header(12) => pcie_blk_if_rx_err_tlp_hdr(12),
      err_tlp_cpl_header(11) => pcie_blk_if_rx_err_tlp_hdr(11),
      err_tlp_cpl_header(10) => pcie_blk_if_rx_err_tlp_hdr(10),
      err_tlp_cpl_header(9) => pcie_blk_if_rx_err_tlp_hdr(9),
      err_tlp_cpl_header(8) => pcie_blk_if_rx_err_tlp_hdr(8),
      err_tlp_cpl_header(7) => pcie_blk_if_rx_err_tlp_hdr(7),
      err_tlp_cpl_header(6) => pcie_blk_if_rx_err_tlp_hdr(6),
      err_tlp_cpl_header(5) => pcie_blk_if_rx_err_tlp_hdr(5),
      err_tlp_cpl_header(4) => pcie_blk_if_rx_err_tlp_hdr(4),
      err_tlp_cpl_header(3) => pcie_blk_if_rx_err_tlp_hdr(3),
      err_tlp_cpl_header(2) => pcie_blk_if_rx_err_tlp_hdr(2),
      err_tlp_cpl_header(1) => pcie_blk_if_rx_err_tlp_hdr(1),
      err_tlp_cpl_header(0) => pcie_blk_if_rx_err_tlp_hdr(0),
      trn_rfc_nph_av(7) => trn_rfc_nph_av(7),
      trn_rfc_nph_av(6) => trn_rfc_nph_av(6),
      trn_rfc_nph_av(5) => trn_rfc_nph_av(5),
      trn_rfc_nph_av(4) => trn_rfc_nph_av(4),
      trn_rfc_nph_av(3) => trn_rfc_nph_av(3),
      trn_rfc_nph_av(2) => trn_rfc_nph_av(2),
      trn_rfc_nph_av(1) => trn_rfc_nph_av(1),
      trn_rfc_nph_av(0) => trn_rfc_nph_av(0),
      trn_rfc_ph_av(7) => trn_rfc_ph_av(7),
      trn_rfc_ph_av(6) => trn_rfc_ph_av(6),
      trn_rfc_ph_av(5) => trn_rfc_ph_av(5),
      trn_rfc_ph_av(4) => trn_rfc_ph_av(4),
      trn_rfc_ph_av(3) => trn_rfc_ph_av(3),
      trn_rfc_ph_av(2) => trn_rfc_ph_av(2),
      trn_rfc_ph_av(1) => trn_rfc_ph_av(1),
      trn_rfc_ph_av(0) => trn_rfc_ph_av(0),
      trn_pfc_cpld_cl(11) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_11_UNCONNECTED,
      trn_pfc_cpld_cl(10) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_10_UNCONNECTED,
      trn_pfc_cpld_cl(9) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_9_UNCONNECTED,
      trn_pfc_cpld_cl(8) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_8_UNCONNECTED,
      trn_pfc_cpld_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_7_UNCONNECTED,
      trn_pfc_cpld_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_6_UNCONNECTED,
      trn_pfc_cpld_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_5_UNCONNECTED,
      trn_pfc_cpld_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_4_UNCONNECTED,
      trn_pfc_cpld_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_3_UNCONNECTED,
      trn_pfc_cpld_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_2_UNCONNECTED,
      trn_pfc_cpld_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_1_UNCONNECTED,
      trn_pfc_cpld_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_cpld_cl_0_UNCONNECTED,
      trn_rrem_n(7) => trn_rrem_n(7),
      trn_rrem_n(6) => trn_rrem_n(6),
      trn_rrem_n(5) => trn_rrem_n(5),
      trn_rrem_n(4) => trn_rrem_n(4),
      trn_rrem_n(3) => trn_rrem_n(3),
      trn_rrem_n(2) => trn_rrem_n(2),
      trn_rrem_n(1) => trn_rrem_n(1),
      trn_rrem_n(0) => trn_rrem_n(0),
      trn_pfc_ph_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_7_UNCONNECTED,
      trn_pfc_ph_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_6_UNCONNECTED,
      trn_pfc_ph_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_5_UNCONNECTED,
      trn_pfc_ph_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_4_UNCONNECTED,
      trn_pfc_ph_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_3_UNCONNECTED,
      trn_pfc_ph_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_2_UNCONNECTED,
      trn_pfc_ph_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_1_UNCONNECTED,
      trn_pfc_ph_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_ph_cl_0_UNCONNECTED,
      llk_tx_ch_fifo(1) => llk_tx_ch_fifo(1),
      llk_tx_ch_fifo(0) => llk_tx_ch_fifo(0),
      llk_tx_ch_tc(2) => llk_tx_ch_tc(2),
      llk_tx_ch_tc(1) => llk_tx_ch_tc(1),
      llk_tx_ch_tc(0) => llk_tx_ch_tc(0),
      llk_rx_data_d(63) => pcie_blk_if_llk_rx_data_d(63),
      llk_rx_data_d(62) => pcie_blk_if_llk_rx_data_d(62),
      llk_rx_data_d(61) => pcie_blk_if_llk_rx_data_d(61),
      llk_rx_data_d(60) => pcie_blk_if_llk_rx_data_d(60),
      llk_rx_data_d(59) => pcie_blk_if_llk_rx_data_d(59),
      llk_rx_data_d(58) => pcie_blk_if_llk_rx_data_d(58),
      llk_rx_data_d(57) => pcie_blk_if_llk_rx_data_d(57),
      llk_rx_data_d(56) => pcie_blk_if_llk_rx_data_d(56),
      llk_rx_data_d(55) => pcie_blk_if_llk_rx_data_d(55),
      llk_rx_data_d(54) => pcie_blk_if_llk_rx_data_d(54),
      llk_rx_data_d(53) => pcie_blk_if_llk_rx_data_d(53),
      llk_rx_data_d(52) => pcie_blk_if_llk_rx_data_d(52),
      llk_rx_data_d(51) => pcie_blk_if_llk_rx_data_d(51),
      llk_rx_data_d(50) => pcie_blk_if_llk_rx_data_d(50),
      llk_rx_data_d(49) => pcie_blk_if_llk_rx_data_d(49),
      llk_rx_data_d(48) => pcie_blk_if_llk_rx_data_d(48),
      llk_rx_data_d(47) => pcie_blk_if_llk_rx_data_d(47),
      llk_rx_data_d(46) => pcie_blk_if_llk_rx_data_d(46),
      llk_rx_data_d(45) => pcie_blk_if_llk_rx_data_d(45),
      llk_rx_data_d(44) => pcie_blk_if_llk_rx_data_d(44),
      llk_rx_data_d(43) => pcie_blk_if_llk_rx_data_d(43),
      llk_rx_data_d(42) => pcie_blk_if_llk_rx_data_d(42),
      llk_rx_data_d(41) => pcie_blk_if_llk_rx_data_d(41),
      llk_rx_data_d(40) => pcie_blk_if_llk_rx_data_d(40),
      llk_rx_data_d(39) => pcie_blk_if_llk_rx_data_d(39),
      llk_rx_data_d(38) => pcie_blk_if_llk_rx_data_d(38),
      llk_rx_data_d(37) => pcie_blk_if_llk_rx_data_d(37),
      llk_rx_data_d(36) => pcie_blk_if_llk_rx_data_d(36),
      llk_rx_data_d(35) => pcie_blk_if_llk_rx_data_d(35),
      llk_rx_data_d(34) => pcie_blk_if_llk_rx_data_d(34),
      llk_rx_data_d(33) => pcie_blk_if_llk_rx_data_d(33),
      llk_rx_data_d(32) => pcie_blk_if_llk_rx_data_d(32),
      llk_rx_data_d(31) => pcie_blk_if_llk_rx_data_d(31),
      llk_rx_data_d(30) => pcie_blk_if_llk_rx_data_d(30),
      llk_rx_data_d(29) => pcie_blk_if_llk_rx_data_d(29),
      llk_rx_data_d(28) => pcie_blk_if_llk_rx_data_d(28),
      llk_rx_data_d(27) => pcie_blk_if_llk_rx_data_d(27),
      llk_rx_data_d(26) => pcie_blk_if_llk_rx_data_d(26),
      llk_rx_data_d(25) => pcie_blk_if_llk_rx_data_d(25),
      llk_rx_data_d(24) => pcie_blk_if_llk_rx_data_d(24),
      llk_rx_data_d(23) => pcie_blk_if_llk_rx_data_d(23),
      llk_rx_data_d(22) => pcie_blk_if_llk_rx_data_d(22),
      llk_rx_data_d(21) => pcie_blk_if_llk_rx_data_d(21),
      llk_rx_data_d(20) => pcie_blk_if_llk_rx_data_d(20),
      llk_rx_data_d(19) => pcie_blk_if_llk_rx_data_d(19),
      llk_rx_data_d(18) => pcie_blk_if_llk_rx_data_d(18),
      llk_rx_data_d(17) => pcie_blk_if_llk_rx_data_d(17),
      llk_rx_data_d(16) => pcie_blk_if_llk_rx_data_d(16),
      llk_rx_data_d(15) => pcie_blk_if_llk_rx_data_d(15),
      llk_rx_data_d(14) => pcie_blk_if_llk_rx_data_d(14),
      llk_rx_data_d(13) => pcie_blk_if_llk_rx_data_d(13),
      llk_rx_data_d(12) => pcie_blk_if_llk_rx_data_d(12),
      llk_rx_data_d(11) => pcie_blk_if_llk_rx_data_d(11),
      llk_rx_data_d(10) => pcie_blk_if_llk_rx_data_d(10),
      llk_rx_data_d(9) => pcie_blk_if_llk_rx_data_d(9),
      llk_rx_data_d(8) => pcie_blk_if_llk_rx_data_d(8),
      llk_rx_data_d(7) => pcie_blk_if_llk_rx_data_d(7),
      llk_rx_data_d(6) => pcie_blk_if_llk_rx_data_d(6),
      llk_rx_data_d(5) => pcie_blk_if_llk_rx_data_d(5),
      llk_rx_data_d(4) => pcie_blk_if_llk_rx_data_d(4),
      llk_rx_data_d(3) => pcie_blk_if_llk_rx_data_d(3),
      llk_rx_data_d(2) => pcie_blk_if_llk_rx_data_d(2),
      llk_rx_data_d(1) => pcie_blk_if_llk_rx_data_d(1),
      llk_rx_data_d(0) => pcie_blk_if_llk_rx_data_d(0),
      trn_tbuf_av(3) => trn_tbuf_av(3),
      trn_tbuf_av(2) => trn_tbuf_av(2),
      trn_tbuf_av(1) => trn_tbuf_av(1),
      trn_tbuf_av(0) => trn_tbuf_av(0),
      trn_rfc_cpld_av(11) => trn_rfc_cpld_av(11),
      trn_rfc_cpld_av(10) => trn_rfc_cpld_av(10),
      trn_rfc_cpld_av(9) => trn_rfc_cpld_av(9),
      trn_rfc_cpld_av(8) => trn_rfc_cpld_av(8),
      trn_rfc_cpld_av(7) => trn_rfc_cpld_av(7),
      trn_rfc_cpld_av(6) => trn_rfc_cpld_av(6),
      trn_rfc_cpld_av(5) => trn_rfc_cpld_av(5),
      trn_rfc_cpld_av(4) => trn_rfc_cpld_av(4),
      trn_rfc_cpld_av(3) => trn_rfc_cpld_av(3),
      trn_rfc_cpld_av(2) => trn_rfc_cpld_av(2),
      trn_rfc_cpld_av(1) => trn_rfc_cpld_av(1),
      trn_rfc_cpld_av(0) => trn_rfc_cpld_av(0),
      trn_pfc_nph_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_7_UNCONNECTED,
      trn_pfc_nph_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_6_UNCONNECTED,
      trn_pfc_nph_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_5_UNCONNECTED,
      trn_pfc_nph_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_4_UNCONNECTED,
      trn_pfc_nph_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_3_UNCONNECTED,
      trn_pfc_nph_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_2_UNCONNECTED,
      trn_pfc_nph_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_1_UNCONNECTED,
      trn_pfc_nph_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_nph_cl_0_UNCONNECTED,
      trn_rbar_hit_n(6) => trn_rbar_hit_n(6),
      trn_rbar_hit_n(5) => trn_rbar_hit_n(5),
      trn_rbar_hit_n(4) => trn_rbar_hit_n(4),
      trn_rbar_hit_n(3) => trn_rbar_hit_n(3),
      trn_rbar_hit_n(2) => trn_rbar_hit_n(2),
      trn_rbar_hit_n(1) => trn_rbar_hit_n(1),
      trn_rbar_hit_n(0) => trn_rbar_hit_n(0),
      trn_rfc_npd_av(11) => trn_rfc_npd_av(11),
      trn_rfc_npd_av(10) => trn_rfc_npd_av(10),
      trn_rfc_npd_av(9) => trn_rfc_npd_av(9),
      trn_rfc_npd_av(8) => trn_rfc_npd_av(8),
      trn_rfc_npd_av(7) => trn_rfc_npd_av(7),
      trn_rfc_npd_av(6) => trn_rfc_npd_av(6),
      trn_rfc_npd_av(5) => trn_rfc_npd_av(5),
      trn_rfc_npd_av(4) => trn_rfc_npd_av(4),
      trn_rfc_npd_av(3) => trn_rfc_npd_av(3),
      trn_rfc_npd_av(2) => trn_rfc_npd_av(2),
      trn_rfc_npd_av(1) => trn_rfc_npd_av(1),
      trn_rfc_npd_av(0) => trn_rfc_npd_av(0),
      llk_tx_enable_n(1) => llk_tx_enable_n(1),
      llk_tx_enable_n(0) => llk_tx_enable_n(0),
      trn_rfc_pd_av(11) => trn_rfc_pd_av(11),
      trn_rfc_pd_av(10) => trn_rfc_pd_av(10),
      trn_rfc_pd_av(9) => trn_rfc_pd_av(9),
      trn_rfc_pd_av(8) => trn_rfc_pd_av(8),
      trn_rfc_pd_av(7) => trn_rfc_pd_av(7),
      trn_rfc_pd_av(6) => trn_rfc_pd_av(6),
      trn_rfc_pd_av(5) => trn_rfc_pd_av(5),
      trn_rfc_pd_av(4) => trn_rfc_pd_av(4),
      trn_rfc_pd_av(3) => trn_rfc_pd_av(3),
      trn_rfc_pd_av(2) => trn_rfc_pd_av(2),
      trn_rfc_pd_av(1) => trn_rfc_pd_av(1),
      trn_rfc_pd_av(0) => trn_rfc_pd_av(0),
      llk_rx_ch_fifo(1) => llk_rx_ch_fifo(1),
      llk_rx_ch_fifo(0) => llk_rx_ch_fifo(0),
      mgmt_stats_credit_sel(6) => mgmt_stats_credit_sel(6),
      mgmt_stats_credit_sel(5) => mgmt_stats_credit_sel(5),
      mgmt_stats_credit_sel(4) => mgmt_stats_credit_sel(4),
      mgmt_stats_credit_sel(3) => mgmt_stats_credit_sel(3),
      mgmt_stats_credit_sel(2) => mgmt_stats_credit_sel(2),
      mgmt_stats_credit_sel(1) => mgmt_stats_credit_sel(1),
      mgmt_stats_credit_sel(0) => mgmt_stats_credit_sel(0),
      llk_tx_data(63) => llk_tx_data(63),
      llk_tx_data(62) => llk_tx_data(62),
      llk_tx_data(61) => llk_tx_data(61),
      llk_tx_data(60) => llk_tx_data(60),
      llk_tx_data(59) => llk_tx_data(59),
      llk_tx_data(58) => llk_tx_data(58),
      llk_tx_data(57) => llk_tx_data(57),
      llk_tx_data(56) => llk_tx_data(56),
      llk_tx_data(55) => llk_tx_data(55),
      llk_tx_data(54) => llk_tx_data(54),
      llk_tx_data(53) => llk_tx_data(53),
      llk_tx_data(52) => llk_tx_data(52),
      llk_tx_data(51) => llk_tx_data(51),
      llk_tx_data(50) => llk_tx_data(50),
      llk_tx_data(49) => llk_tx_data(49),
      llk_tx_data(48) => llk_tx_data(48),
      llk_tx_data(47) => llk_tx_data(47),
      llk_tx_data(46) => llk_tx_data(46),
      llk_tx_data(45) => llk_tx_data(45),
      llk_tx_data(44) => llk_tx_data(44),
      llk_tx_data(43) => llk_tx_data(43),
      llk_tx_data(42) => llk_tx_data(42),
      llk_tx_data(41) => llk_tx_data(41),
      llk_tx_data(40) => llk_tx_data(40),
      llk_tx_data(39) => llk_tx_data(39),
      llk_tx_data(38) => llk_tx_data(38),
      llk_tx_data(37) => llk_tx_data(37),
      llk_tx_data(36) => llk_tx_data(36),
      llk_tx_data(35) => llk_tx_data(35),
      llk_tx_data(34) => llk_tx_data(34),
      llk_tx_data(33) => llk_tx_data(33),
      llk_tx_data(32) => llk_tx_data(32),
      llk_tx_data(31) => llk_tx_data(31),
      llk_tx_data(30) => llk_tx_data(30),
      llk_tx_data(29) => llk_tx_data(29),
      llk_tx_data(28) => llk_tx_data(28),
      llk_tx_data(27) => llk_tx_data(27),
      llk_tx_data(26) => llk_tx_data(26),
      llk_tx_data(25) => llk_tx_data(25),
      llk_tx_data(24) => llk_tx_data(24),
      llk_tx_data(23) => llk_tx_data(23),
      llk_tx_data(22) => llk_tx_data(22),
      llk_tx_data(21) => llk_tx_data(21),
      llk_tx_data(20) => llk_tx_data(20),
      llk_tx_data(19) => llk_tx_data(19),
      llk_tx_data(18) => llk_tx_data(18),
      llk_tx_data(17) => llk_tx_data(17),
      llk_tx_data(16) => llk_tx_data(16),
      llk_tx_data(15) => llk_tx_data(15),
      llk_tx_data(14) => llk_tx_data(14),
      llk_tx_data(13) => llk_tx_data(13),
      llk_tx_data(12) => llk_tx_data(12),
      llk_tx_data(11) => llk_tx_data(11),
      llk_tx_data(10) => llk_tx_data(10),
      llk_tx_data(9) => llk_tx_data(9),
      llk_tx_data(8) => llk_tx_data(8),
      llk_tx_data(7) => llk_tx_data(7),
      llk_tx_data(6) => llk_tx_data(6),
      llk_tx_data(5) => llk_tx_data(5),
      llk_tx_data(4) => llk_tx_data(4),
      llk_tx_data(3) => llk_tx_data(3),
      llk_tx_data(2) => llk_tx_data(2),
      llk_tx_data(1) => llk_tx_data(1),
      llk_tx_data(0) => llk_tx_data(0),
      trn_pfc_pd_cl(11) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_11_UNCONNECTED,
      trn_pfc_pd_cl(10) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_10_UNCONNECTED,
      trn_pfc_pd_cl(9) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_9_UNCONNECTED,
      trn_pfc_pd_cl(8) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_8_UNCONNECTED,
      trn_pfc_pd_cl(7) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_7_UNCONNECTED,
      trn_pfc_pd_cl(6) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_6_UNCONNECTED,
      trn_pfc_pd_cl(5) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_5_UNCONNECTED,
      trn_pfc_pd_cl(4) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_4_UNCONNECTED,
      trn_pfc_pd_cl(3) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_3_UNCONNECTED,
      trn_pfc_pd_cl(2) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_2_UNCONNECTED,
      trn_pfc_pd_cl(1) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_1_UNCONNECTED,
      trn_pfc_pd_cl(0) => NLW_pcie_blk_if_ll_bridge_trn_pfc_pd_cl_0_UNCONNECTED,
      llk_rx_ch_tc(2) => llk_rx_ch_tc(2),
      llk_rx_ch_tc(1) => llk_rx_ch_tc(1),
      llk_rx_ch_tc(0) => llk_rx_ch_tc(0),
      trn_rd(63) => trn_rd(63),
      trn_rd(62) => trn_rd(62),
      trn_rd(61) => trn_rd(61),
      trn_rd(60) => trn_rd(60),
      trn_rd(59) => trn_rd(59),
      trn_rd(58) => trn_rd(58),
      trn_rd(57) => trn_rd(57),
      trn_rd(56) => trn_rd(56),
      trn_rd(55) => trn_rd(55),
      trn_rd(54) => trn_rd(54),
      trn_rd(53) => trn_rd(53),
      trn_rd(52) => trn_rd(52),
      trn_rd(51) => trn_rd(51),
      trn_rd(50) => trn_rd(50),
      trn_rd(49) => trn_rd(49),
      trn_rd(48) => trn_rd(48),
      trn_rd(47) => trn_rd(47),
      trn_rd(46) => trn_rd(46),
      trn_rd(45) => trn_rd(45),
      trn_rd(44) => trn_rd(44),
      trn_rd(43) => trn_rd(43),
      trn_rd(42) => trn_rd(42),
      trn_rd(41) => trn_rd(41),
      trn_rd(40) => trn_rd(40),
      trn_rd(39) => trn_rd(39),
      trn_rd(38) => trn_rd(38),
      trn_rd(37) => trn_rd(37),
      trn_rd(36) => trn_rd(36),
      trn_rd(35) => trn_rd(35),
      trn_rd(34) => trn_rd(34),
      trn_rd(33) => trn_rd(33),
      trn_rd(32) => trn_rd(32),
      trn_rd(31) => trn_rd(31),
      trn_rd(30) => trn_rd(30),
      trn_rd(29) => trn_rd(29),
      trn_rd(28) => trn_rd(28),
      trn_rd(27) => trn_rd(27),
      trn_rd(26) => trn_rd(26),
      trn_rd(25) => trn_rd(25),
      trn_rd(24) => trn_rd(24),
      trn_rd(23) => trn_rd(23),
      trn_rd(22) => trn_rd(22),
      trn_rd(21) => trn_rd(21),
      trn_rd(20) => trn_rd(20),
      trn_rd(19) => trn_rd(19),
      trn_rd(18) => trn_rd(18),
      trn_rd(17) => trn_rd(17),
      trn_rd(16) => trn_rd(16),
      trn_rd(15) => trn_rd(15),
      trn_rd(14) => trn_rd(14),
      trn_rd(13) => trn_rd(13),
      trn_rd(12) => trn_rd(12),
      trn_rd(11) => trn_rd(11),
      trn_rd(10) => trn_rd(10),
      trn_rd(9) => trn_rd(9),
      trn_rd(8) => trn_rd(8),
      trn_rd(7) => trn_rd(7),
      trn_rd(6) => trn_rd(6),
      trn_rd(5) => trn_rd(5),
      trn_rd(4) => trn_rd(4),
      trn_rd(3) => trn_rd(3),
      trn_rd(2) => trn_rd(2),
      trn_rd(1) => trn_rd(1),
      trn_rd(0) => trn_rd(0),
      trn_td(63) => trn_td(63),
      trn_td(62) => trn_td(62),
      trn_td(61) => trn_td(61),
      trn_td(60) => trn_td(60),
      trn_td(59) => trn_td(59),
      trn_td(58) => trn_td(58),
      trn_td(57) => trn_td(57),
      trn_td(56) => trn_td(56),
      trn_td(55) => trn_td(55),
      trn_td(54) => trn_td(54),
      trn_td(53) => trn_td(53),
      trn_td(52) => trn_td(52),
      trn_td(51) => trn_td(51),
      trn_td(50) => trn_td(50),
      trn_td(49) => trn_td(49),
      trn_td(48) => trn_td(48),
      trn_td(47) => trn_td(47),
      trn_td(46) => trn_td(46),
      trn_td(45) => trn_td(45),
      trn_td(44) => trn_td(44),
      trn_td(43) => trn_td(43),
      trn_td(42) => trn_td(42),
      trn_td(41) => trn_td(41),
      trn_td(40) => trn_td(40),
      trn_td(39) => trn_td(39),
      trn_td(38) => trn_td(38),
      trn_td(37) => trn_td(37),
      trn_td(36) => trn_td(36),
      trn_td(35) => trn_td(35),
      trn_td(34) => trn_td(34),
      trn_td(33) => trn_td(33),
      trn_td(32) => trn_td(32),
      trn_td(31) => trn_td(31),
      trn_td(30) => trn_td(30),
      trn_td(29) => trn_td(29),
      trn_td(28) => trn_td(28),
      trn_td(27) => trn_td(27),
      trn_td(26) => trn_td(26),
      trn_td(25) => trn_td(25),
      trn_td(24) => trn_td(24),
      trn_td(23) => trn_td(23),
      trn_td(22) => trn_td(22),
      trn_td(21) => trn_td(21),
      trn_td(20) => trn_td(20),
      trn_td(19) => trn_td(19),
      trn_td(18) => trn_td(18),
      trn_td(17) => trn_td(17),
      trn_td(16) => trn_td(16),
      trn_td(15) => trn_td(15),
      trn_td(14) => trn_td(14),
      trn_td(13) => trn_td(13),
      trn_td(12) => trn_td(12),
      trn_td(11) => trn_td(11),
      trn_td(10) => trn_td(10),
      trn_td(9) => trn_td(9),
      trn_td(8) => trn_td(8),
      trn_td(7) => trn_td(7),
      trn_td(6) => trn_td(6),
      trn_td(5) => trn_td(5),
      trn_td(4) => trn_td(4),
      trn_td(3) => trn_td(3),
      trn_td(2) => trn_td(2),
      trn_td(1) => trn_td(1),
      trn_td(0) => trn_td(0),
      llk_rx_ch_posted_available_n(7) => llk_rx_ch_posted_available_n(7),
      llk_rx_ch_posted_available_n(6) => llk_rx_ch_posted_available_n(6),
      llk_rx_ch_posted_available_n(5) => llk_rx_ch_posted_available_n(5),
      llk_rx_ch_posted_available_n(4) => llk_rx_ch_posted_available_n(4),
      llk_rx_ch_posted_available_n(3) => llk_rx_ch_posted_available_n(3),
      llk_rx_ch_posted_available_n(2) => llk_rx_ch_posted_available_n(2),
      llk_rx_ch_posted_available_n(1) => llk_rx_ch_posted_available_n(1),
      llk_rx_ch_posted_available_n(0) => llk_rx_ch_posted_available_n(0),
      llk_tx_ch_non_posted_ready_n(7) => llk_tx_ch_non_posted_ready_n(7),
      llk_tx_ch_non_posted_ready_n(6) => llk_tx_ch_non_posted_ready_n(6),
      llk_tx_ch_non_posted_ready_n(5) => llk_tx_ch_non_posted_ready_n(5),
      llk_tx_ch_non_posted_ready_n(4) => llk_tx_ch_non_posted_ready_n(4),
      llk_tx_ch_non_posted_ready_n(3) => llk_tx_ch_non_posted_ready_n(3),
      llk_tx_ch_non_posted_ready_n(2) => llk_tx_ch_non_posted_ready_n(2),
      llk_tx_ch_non_posted_ready_n(1) => llk_tx_ch_non_posted_ready_n(1),
      llk_tx_ch_non_posted_ready_n(0) => llk_tx_ch_non_posted_ready_n(0),
      cfg_device_number(4) => NlwRenamedSig_OI_cfg_device_number(4),
      cfg_device_number(3) => NlwRenamedSig_OI_cfg_device_number(3),
      cfg_device_number(2) => NlwRenamedSig_OI_cfg_device_number(2),
      cfg_device_number(1) => NlwRenamedSig_OI_cfg_device_number(1),
      cfg_device_number(0) => NlwRenamedSig_OI_cfg_device_number(0),
      llk_rx_ch_non_posted_available_n(7) => llk_rx_ch_non_posted_available_n(7),
      llk_rx_ch_non_posted_available_n(6) => llk_rx_ch_non_posted_available_n(6),
      llk_rx_ch_non_posted_available_n(5) => llk_rx_ch_non_posted_available_n(5),
      llk_rx_ch_non_posted_available_n(4) => llk_rx_ch_non_posted_available_n(4),
      llk_rx_ch_non_posted_available_n(3) => llk_rx_ch_non_posted_available_n(3),
      llk_rx_ch_non_posted_available_n(2) => llk_rx_ch_non_posted_available_n(2),
      llk_rx_ch_non_posted_available_n(1) => llk_rx_ch_non_posted_available_n(1),
      llk_rx_ch_non_posted_available_n(0) => llk_rx_ch_non_posted_available_n(0),
      llk_rx_ch_completion_available_n(7) => llk_rx_ch_completion_available_n(7),
      llk_rx_ch_completion_available_n(6) => llk_rx_ch_completion_available_n(6),
      llk_rx_ch_completion_available_n(5) => llk_rx_ch_completion_available_n(5),
      llk_rx_ch_completion_available_n(4) => llk_rx_ch_completion_available_n(4),
      llk_rx_ch_completion_available_n(3) => llk_rx_ch_completion_available_n(3),
      llk_rx_ch_completion_available_n(2) => llk_rx_ch_completion_available_n(2),
      llk_rx_ch_completion_available_n(1) => llk_rx_ch_completion_available_n(1),
      llk_rx_ch_completion_available_n(0) => llk_rx_ch_completion_available_n(0),
      llk_rx_valid_n(1) => llk_rx_valid_n(1),
      llk_rx_valid_n(0) => llk_rx_valid_n(0),
      cfg_tx_td(63) => pcie_blk_if_cfg_arb_td(63),
      cfg_tx_td(62) => pcie_blk_if_cfg_arb_td(62),
      cfg_tx_td(61) => pcie_blk_if_cfg_arb_td(61),
      cfg_tx_td(60) => pcie_blk_if_cfg_arb_td(60),
      cfg_tx_td(59) => pcie_blk_if_cfg_arb_td(59),
      cfg_tx_td(58) => pcie_blk_if_cfg_arb_td(58),
      cfg_tx_td(57) => pcie_blk_if_cfg_arb_td(57),
      cfg_tx_td(56) => pcie_blk_if_cfg_arb_td(56),
      cfg_tx_td(55) => pcie_blk_if_cfg_arb_td(55),
      cfg_tx_td(54) => pcie_blk_if_cfg_arb_td(54),
      cfg_tx_td(53) => pcie_blk_if_cfg_arb_td(53),
      cfg_tx_td(52) => pcie_blk_if_cfg_arb_td(52),
      cfg_tx_td(51) => pcie_blk_if_cfg_arb_td(51),
      cfg_tx_td(50) => pcie_blk_if_cfg_arb_td(50),
      cfg_tx_td(49) => pcie_blk_if_cfg_arb_td(49),
      cfg_tx_td(48) => pcie_blk_if_cfg_arb_td(48),
      cfg_tx_td(47) => pcie_blk_if_cfg_arb_td(47),
      cfg_tx_td(46) => pcie_blk_if_cfg_arb_td(46),
      cfg_tx_td(45) => pcie_blk_if_cfg_arb_td(45),
      cfg_tx_td(44) => pcie_blk_if_cfg_arb_td(44),
      cfg_tx_td(43) => pcie_blk_if_cfg_arb_td(43),
      cfg_tx_td(42) => pcie_blk_if_cfg_arb_td(42),
      cfg_tx_td(41) => pcie_blk_if_cfg_arb_td(41),
      cfg_tx_td(40) => pcie_blk_if_cfg_arb_td(40),
      cfg_tx_td(39) => pcie_blk_if_cfg_arb_td(39),
      cfg_tx_td(38) => pcie_blk_if_cfg_arb_td(38),
      cfg_tx_td(37) => pcie_blk_if_cfg_arb_td(37),
      cfg_tx_td(36) => pcie_blk_if_cfg_arb_td(36),
      cfg_tx_td(35) => pcie_blk_if_cfg_arb_td(35),
      cfg_tx_td(34) => pcie_blk_if_cfg_arb_td(34),
      cfg_tx_td(33) => pcie_blk_if_cfg_arb_td(33),
      cfg_tx_td(32) => pcie_blk_if_cfg_arb_td(32),
      cfg_tx_td(31) => pcie_blk_if_cfg_arb_td(31),
      cfg_tx_td(30) => pcie_blk_if_cfg_arb_td(30),
      cfg_tx_td(29) => pcie_blk_if_cfg_arb_td(29),
      cfg_tx_td(28) => pcie_blk_if_cfg_arb_td(28),
      cfg_tx_td(27) => pcie_blk_if_cfg_arb_td(27),
      cfg_tx_td(26) => pcie_blk_if_cfg_arb_td(26),
      cfg_tx_td(25) => pcie_blk_if_cfg_arb_td(25),
      cfg_tx_td(24) => pcie_blk_if_cfg_arb_td(24),
      cfg_tx_td(23) => pcie_blk_if_cfg_arb_td(23),
      cfg_tx_td(22) => pcie_blk_if_cfg_arb_td(22),
      cfg_tx_td(21) => pcie_blk_if_cfg_arb_td(21),
      cfg_tx_td(20) => pcie_blk_if_cfg_arb_td(20),
      cfg_tx_td(19) => pcie_blk_if_cfg_arb_td(19),
      cfg_tx_td(18) => pcie_blk_if_cfg_arb_td(18),
      cfg_tx_td(17) => pcie_blk_if_cfg_arb_td(17),
      cfg_tx_td(16) => pcie_blk_if_cfg_arb_td(16),
      cfg_tx_td(15) => pcie_blk_if_cfg_arb_td(15),
      cfg_tx_td(14) => pcie_blk_if_cfg_arb_td(14),
      cfg_tx_td(13) => pcie_blk_if_cfg_arb_td(13),
      cfg_tx_td(12) => pcie_blk_if_cfg_arb_td(12),
      cfg_tx_td(11) => pcie_blk_if_cfg_arb_td(11),
      cfg_tx_td(10) => pcie_blk_if_cfg_arb_td(10),
      cfg_tx_td(9) => pcie_blk_if_cfg_arb_td(9),
      cfg_tx_td(8) => pcie_blk_if_cfg_arb_td(8),
      cfg_tx_td(7) => pcie_blk_if_cfg_arb_td(7),
      cfg_tx_td(6) => pcie_blk_if_cfg_arb_td(6),
      cfg_tx_td(5) => pcie_blk_if_cfg_arb_td(5),
      cfg_tx_td(4) => pcie_blk_if_cfg_arb_td(4),
      cfg_tx_td(3) => pcie_blk_if_cfg_arb_td(3),
      cfg_tx_td(2) => pcie_blk_if_cfg_arb_td(2),
      cfg_tx_td(1) => pcie_blk_if_cfg_arb_td(1),
      cfg_tx_td(0) => pcie_blk_if_cfg_arb_td(0),
      llk_rx_preferred_type(15) => llk_rx_preferred_type(15),
      llk_rx_preferred_type(14) => llk_rx_preferred_type(14),
      llk_rx_preferred_type(13) => llk_rx_preferred_type(13),
      llk_rx_preferred_type(12) => llk_rx_preferred_type(12),
      llk_rx_preferred_type(11) => llk_rx_preferred_type(11),
      llk_rx_preferred_type(10) => llk_rx_preferred_type(10),
      llk_rx_preferred_type(9) => llk_rx_preferred_type(9),
      llk_rx_preferred_type(8) => llk_rx_preferred_type(8),
      llk_rx_preferred_type(7) => llk_rx_preferred_type(7),
      llk_rx_preferred_type(6) => llk_rx_preferred_type(6),
      llk_rx_preferred_type(5) => llk_rx_preferred_type(5),
      llk_rx_preferred_type(4) => llk_rx_preferred_type(4),
      llk_rx_preferred_type(3) => llk_rx_preferred_type(3),
      llk_rx_preferred_type(2) => llk_rx_preferred_type(2),
      llk_rx_preferred_type(1) => llk_rx_preferred_type(1),
      llk_rx_preferred_type(0) => llk_rx_preferred_type(0),
      llk_tc_status(7) => llk_tc_status(7),
      llk_tc_status(6) => llk_tc_status(6),
      llk_tc_status(5) => llk_tc_status(5),
      llk_tc_status(4) => llk_tc_status(4),
      llk_tc_status(3) => llk_tc_status(3),
      llk_tc_status(2) => llk_tc_status(2),
      llk_tc_status(1) => llk_tc_status(1),
      llk_tc_status(0) => llk_tc_status(0),
      llk_tx_ch_posted_ready_n(7) => llk_tx_ch_posted_ready_n(7),
      llk_tx_ch_posted_ready_n(6) => llk_tx_ch_posted_ready_n(6),
      llk_tx_ch_posted_ready_n(5) => llk_tx_ch_posted_ready_n(5),
      llk_tx_ch_posted_ready_n(4) => llk_tx_ch_posted_ready_n(4),
      llk_tx_ch_posted_ready_n(3) => llk_tx_ch_posted_ready_n(3),
      llk_tx_ch_posted_ready_n(2) => llk_tx_ch_posted_ready_n(2),
      llk_tx_ch_posted_ready_n(1) => llk_tx_ch_posted_ready_n(1),
      llk_tx_ch_posted_ready_n(0) => llk_tx_ch_posted_ready_n(0),
      cfg_rx_xrom(31) => pcie_blk_if_cfg_rx_xrom(31),
      cfg_rx_xrom(30) => pcie_blk_if_cfg_rx_xrom(30),
      cfg_rx_xrom(29) => pcie_blk_if_cfg_rx_xrom(29),
      cfg_rx_xrom(28) => pcie_blk_if_cfg_rx_xrom(28),
      cfg_rx_xrom(27) => pcie_blk_if_cfg_rx_xrom(27),
      cfg_rx_xrom(26) => pcie_blk_if_cfg_rx_xrom(26),
      cfg_rx_xrom(25) => pcie_blk_if_cfg_rx_xrom(25),
      cfg_rx_xrom(24) => pcie_blk_if_cfg_rx_xrom(24),
      cfg_rx_xrom(23) => pcie_blk_if_cfg_rx_xrom(23),
      cfg_rx_xrom(22) => pcie_blk_if_cfg_rx_xrom(22),
      cfg_rx_xrom(21) => pcie_blk_if_cfg_rx_xrom(21),
      cfg_rx_xrom(20) => pcie_blk_if_cfg_rx_xrom(20),
      cfg_rx_xrom(19) => pcie_blk_if_cfg_rx_xrom(19),
      cfg_rx_xrom(18) => pcie_blk_if_cfg_rx_xrom(18),
      cfg_rx_xrom(17) => pcie_blk_if_cfg_rx_xrom(17),
      cfg_rx_xrom(16) => pcie_blk_if_cfg_rx_xrom(16),
      cfg_rx_xrom(15) => pcie_blk_if_cfg_rx_xrom(15),
      cfg_rx_xrom(14) => pcie_blk_if_cfg_rx_xrom(14),
      cfg_rx_xrom(13) => pcie_blk_if_cfg_rx_xrom(13),
      cfg_rx_xrom(12) => pcie_blk_if_cfg_rx_xrom(12),
      cfg_rx_xrom(11) => pcie_blk_if_cfg_rx_xrom(11),
      cfg_rx_xrom(10) => pcie_blk_if_cfg_rx_xrom(10),
      cfg_rx_xrom(9) => pcie_blk_if_cfg_rx_xrom(9),
      cfg_rx_xrom(8) => pcie_blk_if_cfg_rx_xrom(8),
      cfg_rx_xrom(7) => pcie_blk_if_cfg_rx_xrom(7),
      cfg_rx_xrom(6) => pcie_blk_if_cfg_rx_xrom(6),
      cfg_rx_xrom(5) => pcie_blk_if_cfg_rx_xrom(5),
      cfg_rx_xrom(4) => pcie_blk_if_cfg_rx_xrom(4),
      cfg_rx_xrom(3) => pcie_blk_if_cfg_rx_xrom(3),
      cfg_rx_xrom(2) => pcie_blk_if_cfg_rx_xrom(2),
      cfg_rx_xrom(1) => pcie_blk_if_cfg_rx_xrom(1),
      cfg_rx_xrom(0) => pcie_blk_if_cfg_rx_xrom(0),
      max_payload_size(2) => pcie_blk_if_cfg_dcap(2),
      max_payload_size(1) => pcie_blk_if_cfg_dcap(1),
      max_payload_size(0) => pcie_blk_if_cfg_dcap(0),
      cfg_bus_number(7) => NlwRenamedSig_OI_cfg_bus_number(7),
      cfg_bus_number(6) => NlwRenamedSig_OI_cfg_bus_number(6),
      cfg_bus_number(5) => NlwRenamedSig_OI_cfg_bus_number(5),
      cfg_bus_number(4) => NlwRenamedSig_OI_cfg_bus_number(4),
      cfg_bus_number(3) => NlwRenamedSig_OI_cfg_bus_number(3),
      cfg_bus_number(2) => NlwRenamedSig_OI_cfg_bus_number(2),
      cfg_bus_number(1) => NlwRenamedSig_OI_cfg_bus_number(1),
      cfg_bus_number(0) => NlwRenamedSig_OI_cfg_bus_number(0),
      cfg_pmcsr(15) => pcie_blk_if_cfg_pmcsr(15),
      cfg_pmcsr(14) => pcie_blk_if_cfg_pmcsr(14),
      cfg_pmcsr(13) => pcie_blk_if_cfg_pmcsr(13),
      cfg_pmcsr(12) => pcie_blk_if_cfg_pmcsr(12),
      cfg_pmcsr(11) => pcie_blk_if_cfg_pmcsr(11),
      cfg_pmcsr(10) => pcie_blk_if_cfg_pmcsr(10),
      cfg_pmcsr(9) => pcie_blk_if_cfg_pmcsr(9),
      cfg_pmcsr(8) => pcie_blk_if_cfg_pmcsr(8),
      cfg_pmcsr(7) => pcie_blk_if_cfg_pmcsr(7),
      cfg_pmcsr(6) => pcie_blk_if_cfg_pmcsr(6),
      cfg_pmcsr(5) => pcie_blk_if_cfg_pmcsr(5),
      cfg_pmcsr(4) => pcie_blk_if_cfg_pmcsr(4),
      cfg_pmcsr(3) => pcie_blk_if_cfg_pmcsr(3),
      cfg_pmcsr(2) => pcie_blk_if_cfg_pmcsr(2),
      cfg_pmcsr(1) => pcie_blk_if_cfg_pmcsr(1),
      cfg_pmcsr(0) => pcie_blk_if_cfg_pmcsr(0),
      llk_tx_chan_space(9) => llk_tx_chan_space(9),
      llk_tx_chan_space(8) => llk_tx_chan_space(8),
      llk_tx_chan_space(7) => llk_tx_chan_space(7),
      llk_tx_chan_space(6) => llk_tx_chan_space(6),
      llk_tx_chan_space(5) => llk_tx_chan_space(5),
      llk_tx_chan_space(4) => llk_tx_chan_space(4),
      llk_tx_chan_space(3) => llk_tx_chan_space(3),
      llk_tx_chan_space(2) => llk_tx_chan_space(2),
      llk_tx_chan_space(1) => llk_tx_chan_space(1),
      llk_tx_chan_space(0) => llk_tx_chan_space(0),
      mgmt_stats_credit(11) => mgmt_stats_credit(11),
      mgmt_stats_credit(10) => mgmt_stats_credit(10),
      mgmt_stats_credit(9) => mgmt_stats_credit(9),
      mgmt_stats_credit(8) => mgmt_stats_credit(8),
      mgmt_stats_credit(7) => mgmt_stats_credit(7),
      mgmt_stats_credit(6) => mgmt_stats_credit(6),
      mgmt_stats_credit(5) => mgmt_stats_credit(5),
      mgmt_stats_credit(4) => mgmt_stats_credit(4),
      mgmt_stats_credit(3) => mgmt_stats_credit(3),
      mgmt_stats_credit(2) => mgmt_stats_credit(2),
      mgmt_stats_credit(1) => mgmt_stats_credit(1),
      mgmt_stats_credit(0) => mgmt_stats_credit(0),
      cfg_dcommand(15) => NlwRenamedSig_OI_cfg_dcommand(15),
      cfg_dcommand(14) => NlwRenamedSig_OI_cfg_dcommand(14),
      cfg_dcommand(13) => NlwRenamedSig_OI_cfg_dcommand(13),
      cfg_dcommand(12) => NlwRenamedSig_OI_cfg_dcommand(12),
      cfg_dcommand(11) => NlwRenamedSig_OI_cfg_dcommand(11),
      cfg_dcommand(10) => NlwRenamedSig_OI_cfg_dcommand(10),
      cfg_dcommand(9) => NlwRenamedSig_OI_cfg_dcommand(9),
      cfg_dcommand(8) => NlwRenamedSig_OI_cfg_dcommand(8),
      cfg_dcommand(7) => NlwRenamedSig_OI_cfg_dcommand(7),
      cfg_dcommand(6) => NlwRenamedSig_OI_cfg_dcommand(6),
      cfg_dcommand(5) => NlwRenamedSig_OI_cfg_dcommand(5),
      cfg_dcommand(4) => NlwRenamedSig_OI_cfg_dcommand(4),
      cfg_dcommand(3) => NlwRenamedSig_OI_cfg_dcommand(3),
      cfg_dcommand(2) => NlwRenamedSig_OI_cfg_dcommand(2),
      cfg_dcommand(1) => NlwRenamedSig_OI_cfg_dcommand(1),
      cfg_dcommand(0) => NlwRenamedSig_OI_cfg_dcommand(0),
      llk_tx_ch_completion_ready_n(7) => llk_tx_ch_completion_ready_n(7),
      llk_tx_ch_completion_ready_n(6) => llk_tx_ch_completion_ready_n(6),
      llk_tx_ch_completion_ready_n(5) => llk_tx_ch_completion_ready_n(5),
      llk_tx_ch_completion_ready_n(4) => llk_tx_ch_completion_ready_n(4),
      llk_tx_ch_completion_ready_n(3) => llk_tx_ch_completion_ready_n(3),
      llk_tx_ch_completion_ready_n(2) => llk_tx_ch_completion_ready_n(2),
      llk_tx_ch_completion_ready_n(1) => llk_tx_ch_completion_ready_n(1),
      llk_tx_ch_completion_ready_n(0) => llk_tx_ch_completion_ready_n(0),
      trn_trem_n(7) => trn_trem_n(7),
      trn_trem_n(6) => trn_trem_n(6),
      trn_trem_n(5) => trn_trem_n(5),
      trn_trem_n(4) => trn_trem_n(4),
      trn_trem_n(3) => trn_trem_n(3),
      trn_trem_n(2) => trn_trem_n(2),
      trn_trem_n(1) => trn_trem_n(1),
      trn_trem_n(0) => trn_trem_n(0),
      cfg_function_number(2) => NlwRenamedSig_OI_cfg_function_number(2),
      cfg_function_number(1) => NlwRenamedSig_OI_cfg_function_number(1),
      cfg_function_number(0) => NlwRenamedSig_OI_cfg_function_number(0),
      cfg_rx_bar0(31) => pcie_blk_if_cfg_rx_bar0(31),
      cfg_rx_bar0(30) => pcie_blk_if_cfg_rx_bar0(30),
      cfg_rx_bar0(29) => pcie_blk_if_cfg_rx_bar0(29),
      cfg_rx_bar0(28) => pcie_blk_if_cfg_rx_bar0(28),
      cfg_rx_bar0(27) => pcie_blk_if_cfg_rx_bar0(27),
      cfg_rx_bar0(26) => pcie_blk_if_cfg_rx_bar0(26),
      cfg_rx_bar0(25) => pcie_blk_if_cfg_rx_bar0(25),
      cfg_rx_bar0(24) => pcie_blk_if_cfg_rx_bar0(24),
      cfg_rx_bar0(23) => pcie_blk_if_cfg_rx_bar0(23),
      cfg_rx_bar0(22) => pcie_blk_if_cfg_rx_bar0(22),
      cfg_rx_bar0(21) => pcie_blk_if_cfg_rx_bar0(21),
      cfg_rx_bar0(20) => pcie_blk_if_cfg_rx_bar0(20),
      cfg_rx_bar0(19) => pcie_blk_if_cfg_rx_bar0(19),
      cfg_rx_bar0(18) => pcie_blk_if_cfg_rx_bar0(18),
      cfg_rx_bar0(17) => pcie_blk_if_cfg_rx_bar0(17),
      cfg_rx_bar0(16) => pcie_blk_if_cfg_rx_bar0(16),
      cfg_rx_bar0(15) => pcie_blk_if_cfg_rx_bar0(15),
      cfg_rx_bar0(14) => pcie_blk_if_cfg_rx_bar0(14),
      cfg_rx_bar0(13) => pcie_blk_if_cfg_rx_bar0(13),
      cfg_rx_bar0(12) => pcie_blk_if_cfg_rx_bar0(12),
      cfg_rx_bar0(11) => pcie_blk_if_cfg_rx_bar0(11),
      cfg_rx_bar0(10) => pcie_blk_if_cfg_rx_bar0(10),
      cfg_rx_bar0(9) => pcie_blk_if_cfg_rx_bar0(9),
      cfg_rx_bar0(8) => pcie_blk_if_cfg_rx_bar0(8),
      cfg_rx_bar0(7) => pcie_blk_if_cfg_rx_bar0(7),
      cfg_rx_bar0(6) => pcie_blk_if_cfg_rx_bar0(6),
      cfg_rx_bar0(5) => pcie_blk_if_cfg_rx_bar0(5),
      cfg_rx_bar0(4) => pcie_blk_if_cfg_rx_bar0(4),
      cfg_rx_bar0(3) => pcie_blk_if_cfg_rx_bar0(3),
      cfg_rx_bar0(2) => pcie_blk_if_cfg_rx_bar0(2),
      cfg_rx_bar0(1) => pcie_blk_if_cfg_rx_bar0(1),
      cfg_rx_bar0(0) => pcie_blk_if_cfg_rx_bar0(0),
      cfg_rx_bar1(31) => pcie_blk_if_cfg_rx_bar1(31),
      cfg_rx_bar1(30) => pcie_blk_if_cfg_rx_bar1(30),
      cfg_rx_bar1(29) => pcie_blk_if_cfg_rx_bar1(29),
      cfg_rx_bar1(28) => pcie_blk_if_cfg_rx_bar1(28),
      cfg_rx_bar1(27) => pcie_blk_if_cfg_rx_bar1(27),
      cfg_rx_bar1(26) => pcie_blk_if_cfg_rx_bar1(26),
      cfg_rx_bar1(25) => pcie_blk_if_cfg_rx_bar1(25),
      cfg_rx_bar1(24) => pcie_blk_if_cfg_rx_bar1(24),
      cfg_rx_bar1(23) => pcie_blk_if_cfg_rx_bar1(23),
      cfg_rx_bar1(22) => pcie_blk_if_cfg_rx_bar1(22),
      cfg_rx_bar1(21) => pcie_blk_if_cfg_rx_bar1(21),
      cfg_rx_bar1(20) => pcie_blk_if_cfg_rx_bar1(20),
      cfg_rx_bar1(19) => pcie_blk_if_cfg_rx_bar1(19),
      cfg_rx_bar1(18) => pcie_blk_if_cfg_rx_bar1(18),
      cfg_rx_bar1(17) => pcie_blk_if_cfg_rx_bar1(17),
      cfg_rx_bar1(16) => pcie_blk_if_cfg_rx_bar1(16),
      cfg_rx_bar1(15) => pcie_blk_if_cfg_rx_bar1(15),
      cfg_rx_bar1(14) => pcie_blk_if_cfg_rx_bar1(14),
      cfg_rx_bar1(13) => pcie_blk_if_cfg_rx_bar1(13),
      cfg_rx_bar1(12) => pcie_blk_if_cfg_rx_bar1(12),
      cfg_rx_bar1(11) => pcie_blk_if_cfg_rx_bar1(11),
      cfg_rx_bar1(10) => pcie_blk_if_cfg_rx_bar1(10),
      cfg_rx_bar1(9) => pcie_blk_if_cfg_rx_bar1(9),
      cfg_rx_bar1(8) => pcie_blk_if_cfg_rx_bar1(8),
      cfg_rx_bar1(7) => pcie_blk_if_cfg_rx_bar1(7),
      cfg_rx_bar1(6) => pcie_blk_if_cfg_rx_bar1(6),
      cfg_rx_bar1(5) => pcie_blk_if_cfg_rx_bar1(5),
      cfg_rx_bar1(4) => pcie_blk_if_cfg_rx_bar1(4),
      cfg_rx_bar1(3) => pcie_blk_if_cfg_rx_bar1(3),
      cfg_rx_bar1(2) => pcie_blk_if_cfg_rx_bar1(2),
      cfg_rx_bar1(1) => pcie_blk_if_cfg_rx_bar1(1),
      cfg_rx_bar1(0) => pcie_blk_if_cfg_rx_bar1(0),
      cfg_rx_bar2(31) => pcie_blk_if_cfg_rx_bar2(31),
      cfg_rx_bar2(30) => pcie_blk_if_cfg_rx_bar2(30),
      cfg_rx_bar2(29) => pcie_blk_if_cfg_rx_bar2(29),
      cfg_rx_bar2(28) => pcie_blk_if_cfg_rx_bar2(28),
      cfg_rx_bar2(27) => pcie_blk_if_cfg_rx_bar2(27),
      cfg_rx_bar2(26) => pcie_blk_if_cfg_rx_bar2(26),
      cfg_rx_bar2(25) => pcie_blk_if_cfg_rx_bar2(25),
      cfg_rx_bar2(24) => pcie_blk_if_cfg_rx_bar2(24),
      cfg_rx_bar2(23) => pcie_blk_if_cfg_rx_bar2(23),
      cfg_rx_bar2(22) => pcie_blk_if_cfg_rx_bar2(22),
      cfg_rx_bar2(21) => pcie_blk_if_cfg_rx_bar2(21),
      cfg_rx_bar2(20) => pcie_blk_if_cfg_rx_bar2(20),
      cfg_rx_bar2(19) => pcie_blk_if_cfg_rx_bar2(19),
      cfg_rx_bar2(18) => pcie_blk_if_cfg_rx_bar2(18),
      cfg_rx_bar2(17) => pcie_blk_if_cfg_rx_bar2(17),
      cfg_rx_bar2(16) => pcie_blk_if_cfg_rx_bar2(16),
      cfg_rx_bar2(15) => pcie_blk_if_cfg_rx_bar2(15),
      cfg_rx_bar2(14) => pcie_blk_if_cfg_rx_bar2(14),
      cfg_rx_bar2(13) => pcie_blk_if_cfg_rx_bar2(13),
      cfg_rx_bar2(12) => pcie_blk_if_cfg_rx_bar2(12),
      cfg_rx_bar2(11) => pcie_blk_if_cfg_rx_bar2(11),
      cfg_rx_bar2(10) => pcie_blk_if_cfg_rx_bar2(10),
      cfg_rx_bar2(9) => pcie_blk_if_cfg_rx_bar2(9),
      cfg_rx_bar2(8) => pcie_blk_if_cfg_rx_bar2(8),
      cfg_rx_bar2(7) => pcie_blk_if_cfg_rx_bar2(7),
      cfg_rx_bar2(6) => pcie_blk_if_cfg_rx_bar2(6),
      cfg_rx_bar2(5) => pcie_blk_if_cfg_rx_bar2(5),
      cfg_rx_bar2(4) => pcie_blk_if_cfg_rx_bar2(4),
      cfg_rx_bar2(3) => pcie_blk_if_cfg_rx_bar2(3),
      cfg_rx_bar2(2) => pcie_blk_if_cfg_rx_bar2(2),
      cfg_rx_bar2(1) => pcie_blk_if_cfg_rx_bar2(1),
      cfg_rx_bar2(0) => pcie_blk_if_cfg_rx_bar2(0),
      cfg_rx_bar3(31) => pcie_blk_if_cfg_rx_bar3(31),
      cfg_rx_bar3(30) => pcie_blk_if_cfg_rx_bar3(30),
      cfg_rx_bar3(29) => pcie_blk_if_cfg_rx_bar3(29),
      cfg_rx_bar3(28) => pcie_blk_if_cfg_rx_bar3(28),
      cfg_rx_bar3(27) => pcie_blk_if_cfg_rx_bar3(27),
      cfg_rx_bar3(26) => pcie_blk_if_cfg_rx_bar3(26),
      cfg_rx_bar3(25) => pcie_blk_if_cfg_rx_bar3(25),
      cfg_rx_bar3(24) => pcie_blk_if_cfg_rx_bar3(24),
      cfg_rx_bar3(23) => pcie_blk_if_cfg_rx_bar3(23),
      cfg_rx_bar3(22) => pcie_blk_if_cfg_rx_bar3(22),
      cfg_rx_bar3(21) => pcie_blk_if_cfg_rx_bar3(21),
      cfg_rx_bar3(20) => pcie_blk_if_cfg_rx_bar3(20),
      cfg_rx_bar3(19) => pcie_blk_if_cfg_rx_bar3(19),
      cfg_rx_bar3(18) => pcie_blk_if_cfg_rx_bar3(18),
      cfg_rx_bar3(17) => pcie_blk_if_cfg_rx_bar3(17),
      cfg_rx_bar3(16) => pcie_blk_if_cfg_rx_bar3(16),
      cfg_rx_bar3(15) => pcie_blk_if_cfg_rx_bar3(15),
      cfg_rx_bar3(14) => pcie_blk_if_cfg_rx_bar3(14),
      cfg_rx_bar3(13) => pcie_blk_if_cfg_rx_bar3(13),
      cfg_rx_bar3(12) => pcie_blk_if_cfg_rx_bar3(12),
      cfg_rx_bar3(11) => pcie_blk_if_cfg_rx_bar3(11),
      cfg_rx_bar3(10) => pcie_blk_if_cfg_rx_bar3(10),
      cfg_rx_bar3(9) => pcie_blk_if_cfg_rx_bar3(9),
      cfg_rx_bar3(8) => pcie_blk_if_cfg_rx_bar3(8),
      cfg_rx_bar3(7) => pcie_blk_if_cfg_rx_bar3(7),
      cfg_rx_bar3(6) => pcie_blk_if_cfg_rx_bar3(6),
      cfg_rx_bar3(5) => pcie_blk_if_cfg_rx_bar3(5),
      cfg_rx_bar3(4) => pcie_blk_if_cfg_rx_bar3(4),
      cfg_rx_bar3(3) => pcie_blk_if_cfg_rx_bar3(3),
      cfg_rx_bar3(2) => pcie_blk_if_cfg_rx_bar3(2),
      cfg_rx_bar3(1) => pcie_blk_if_cfg_rx_bar3(1),
      cfg_rx_bar3(0) => pcie_blk_if_cfg_rx_bar3(0),
      cfg_rx_bar4(31) => pcie_blk_if_cfg_rx_bar4(31),
      cfg_rx_bar4(30) => pcie_blk_if_cfg_rx_bar4(30),
      cfg_rx_bar4(29) => pcie_blk_if_cfg_rx_bar4(29),
      cfg_rx_bar4(28) => pcie_blk_if_cfg_rx_bar4(28),
      cfg_rx_bar4(27) => pcie_blk_if_cfg_rx_bar4(27),
      cfg_rx_bar4(26) => pcie_blk_if_cfg_rx_bar4(26),
      cfg_rx_bar4(25) => pcie_blk_if_cfg_rx_bar4(25),
      cfg_rx_bar4(24) => pcie_blk_if_cfg_rx_bar4(24),
      cfg_rx_bar4(23) => pcie_blk_if_cfg_rx_bar4(23),
      cfg_rx_bar4(22) => pcie_blk_if_cfg_rx_bar4(22),
      cfg_rx_bar4(21) => pcie_blk_if_cfg_rx_bar4(21),
      cfg_rx_bar4(20) => pcie_blk_if_cfg_rx_bar4(20),
      cfg_rx_bar4(19) => pcie_blk_if_cfg_rx_bar4(19),
      cfg_rx_bar4(18) => pcie_blk_if_cfg_rx_bar4(18),
      cfg_rx_bar4(17) => pcie_blk_if_cfg_rx_bar4(17),
      cfg_rx_bar4(16) => pcie_blk_if_cfg_rx_bar4(16),
      cfg_rx_bar4(15) => pcie_blk_if_cfg_rx_bar4(15),
      cfg_rx_bar4(14) => pcie_blk_if_cfg_rx_bar4(14),
      cfg_rx_bar4(13) => pcie_blk_if_cfg_rx_bar4(13),
      cfg_rx_bar4(12) => pcie_blk_if_cfg_rx_bar4(12),
      cfg_rx_bar4(11) => pcie_blk_if_cfg_rx_bar4(11),
      cfg_rx_bar4(10) => pcie_blk_if_cfg_rx_bar4(10),
      cfg_rx_bar4(9) => pcie_blk_if_cfg_rx_bar4(9),
      cfg_rx_bar4(8) => pcie_blk_if_cfg_rx_bar4(8),
      cfg_rx_bar4(7) => pcie_blk_if_cfg_rx_bar4(7),
      cfg_rx_bar4(6) => pcie_blk_if_cfg_rx_bar4(6),
      cfg_rx_bar4(5) => pcie_blk_if_cfg_rx_bar4(5),
      cfg_rx_bar4(4) => pcie_blk_if_cfg_rx_bar4(4),
      cfg_rx_bar4(3) => pcie_blk_if_cfg_rx_bar4(3),
      cfg_rx_bar4(2) => pcie_blk_if_cfg_rx_bar4(2),
      cfg_rx_bar4(1) => pcie_blk_if_cfg_rx_bar4(1),
      cfg_rx_bar4(0) => pcie_blk_if_cfg_rx_bar4(0),
      cfg_rx_bar5(31) => pcie_blk_if_cfg_rx_bar5(31),
      cfg_rx_bar5(30) => pcie_blk_if_cfg_rx_bar5(30),
      cfg_rx_bar5(29) => pcie_blk_if_cfg_rx_bar5(29),
      cfg_rx_bar5(28) => pcie_blk_if_cfg_rx_bar5(28),
      cfg_rx_bar5(27) => pcie_blk_if_cfg_rx_bar5(27),
      cfg_rx_bar5(26) => pcie_blk_if_cfg_rx_bar5(26),
      cfg_rx_bar5(25) => pcie_blk_if_cfg_rx_bar5(25),
      cfg_rx_bar5(24) => pcie_blk_if_cfg_rx_bar5(24),
      cfg_rx_bar5(23) => pcie_blk_if_cfg_rx_bar5(23),
      cfg_rx_bar5(22) => pcie_blk_if_cfg_rx_bar5(22),
      cfg_rx_bar5(21) => pcie_blk_if_cfg_rx_bar5(21),
      cfg_rx_bar5(20) => pcie_blk_if_cfg_rx_bar5(20),
      cfg_rx_bar5(19) => pcie_blk_if_cfg_rx_bar5(19),
      cfg_rx_bar5(18) => pcie_blk_if_cfg_rx_bar5(18),
      cfg_rx_bar5(17) => pcie_blk_if_cfg_rx_bar5(17),
      cfg_rx_bar5(16) => pcie_blk_if_cfg_rx_bar5(16),
      cfg_rx_bar5(15) => pcie_blk_if_cfg_rx_bar5(15),
      cfg_rx_bar5(14) => pcie_blk_if_cfg_rx_bar5(14),
      cfg_rx_bar5(13) => pcie_blk_if_cfg_rx_bar5(13),
      cfg_rx_bar5(12) => pcie_blk_if_cfg_rx_bar5(12),
      cfg_rx_bar5(11) => pcie_blk_if_cfg_rx_bar5(11),
      cfg_rx_bar5(10) => pcie_blk_if_cfg_rx_bar5(10),
      cfg_rx_bar5(9) => pcie_blk_if_cfg_rx_bar5(9),
      cfg_rx_bar5(8) => pcie_blk_if_cfg_rx_bar5(8),
      cfg_rx_bar5(7) => pcie_blk_if_cfg_rx_bar5(7),
      cfg_rx_bar5(6) => pcie_blk_if_cfg_rx_bar5(6),
      cfg_rx_bar5(5) => pcie_blk_if_cfg_rx_bar5(5),
      cfg_rx_bar5(4) => pcie_blk_if_cfg_rx_bar5(4),
      cfg_rx_bar5(3) => pcie_blk_if_cfg_rx_bar5(3),
      cfg_rx_bar5(2) => pcie_blk_if_cfg_rx_bar5(2),
      cfg_rx_bar5(1) => pcie_blk_if_cfg_rx_bar5(1),
      cfg_rx_bar5(0) => pcie_blk_if_cfg_rx_bar5(0),
      llk_rx_data(63) => llk_rx_data(63),
      llk_rx_data(62) => llk_rx_data(62),
      llk_rx_data(61) => llk_rx_data(61),
      llk_rx_data(60) => llk_rx_data(60),
      llk_rx_data(59) => llk_rx_data(59),
      llk_rx_data(58) => llk_rx_data(58),
      llk_rx_data(57) => llk_rx_data(57),
      llk_rx_data(56) => llk_rx_data(56),
      llk_rx_data(55) => llk_rx_data(55),
      llk_rx_data(54) => llk_rx_data(54),
      llk_rx_data(53) => llk_rx_data(53),
      llk_rx_data(52) => llk_rx_data(52),
      llk_rx_data(51) => llk_rx_data(51),
      llk_rx_data(50) => llk_rx_data(50),
      llk_rx_data(49) => llk_rx_data(49),
      llk_rx_data(48) => llk_rx_data(48),
      llk_rx_data(47) => llk_rx_data(47),
      llk_rx_data(46) => llk_rx_data(46),
      llk_rx_data(45) => llk_rx_data(45),
      llk_rx_data(44) => llk_rx_data(44),
      llk_rx_data(43) => llk_rx_data(43),
      llk_rx_data(42) => llk_rx_data(42),
      llk_rx_data(41) => llk_rx_data(41),
      llk_rx_data(40) => llk_rx_data(40),
      llk_rx_data(39) => llk_rx_data(39),
      llk_rx_data(38) => llk_rx_data(38),
      llk_rx_data(37) => llk_rx_data(37),
      llk_rx_data(36) => llk_rx_data(36),
      llk_rx_data(35) => llk_rx_data(35),
      llk_rx_data(34) => llk_rx_data(34),
      llk_rx_data(33) => llk_rx_data(33),
      llk_rx_data(32) => llk_rx_data(32),
      llk_rx_data(31) => llk_rx_data(31),
      llk_rx_data(30) => llk_rx_data(30),
      llk_rx_data(29) => llk_rx_data(29),
      llk_rx_data(28) => llk_rx_data(28),
      llk_rx_data(27) => llk_rx_data(27),
      llk_rx_data(26) => llk_rx_data(26),
      llk_rx_data(25) => llk_rx_data(25),
      llk_rx_data(24) => llk_rx_data(24),
      llk_rx_data(23) => llk_rx_data(23),
      llk_rx_data(22) => llk_rx_data(22),
      llk_rx_data(21) => llk_rx_data(21),
      llk_rx_data(20) => llk_rx_data(20),
      llk_rx_data(19) => llk_rx_data(19),
      llk_rx_data(18) => llk_rx_data(18),
      llk_rx_data(17) => llk_rx_data(17),
      llk_rx_data(16) => llk_rx_data(16),
      llk_rx_data(15) => llk_rx_data(15),
      llk_rx_data(14) => llk_rx_data(14),
      llk_rx_data(13) => llk_rx_data(13),
      llk_rx_data(12) => llk_rx_data(12),
      llk_rx_data(11) => llk_rx_data(11),
      llk_rx_data(10) => llk_rx_data(10),
      llk_rx_data(9) => llk_rx_data(9),
      llk_rx_data(8) => llk_rx_data(8),
      llk_rx_data(7) => llk_rx_data(7),
      llk_rx_data(6) => llk_rx_data(6),
      llk_rx_data(5) => llk_rx_data(5),
      llk_rx_data(4) => llk_rx_data(4),
      llk_rx_data(3) => llk_rx_data(3),
      llk_rx_data(2) => llk_rx_data(2),
      llk_rx_data(1) => llk_rx_data(1),
      llk_rx_data(0) => llk_rx_data(0)
    );
  pcie_blk_if_cf_bridge : pcie_blk_cf
    port map (
      rx_err_cpl_ur_n => pcie_blk_if_rx_err_cpl_ur_n,
      l0_set_user_system_error => fe_l0_set_user_system_error,
      clk => NlwRenamedSig_OI_trn_clk,
      rst_n => app_reset_n_30520,
      rx_err_tlp_ur_lock_n => pcie_blk_if_rx_err_tlp_ur_lock_n,
      cfg_err_cpl_abort_n => NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_abort_n_UNCONNECTED,
      l0_set_user_received_master_abort => fe_l0_set_user_received_master_abort,
      llk_rx_src_rdy_n => llk_rx_src_rdy_n,
      l0_set_detected_nonfatal_error => fe_l0_set_detected_nonfatal_error,
      cfg_arb_teof_n => pcie_blk_if_cfg_arb_teof_n,
      cfg_err_cpl_unexpect_n => NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_unexpect_n_UNCONNECTED,
      serr_enable => fe_serr_enable,
      mgmt_rden => bridge_mgmt_rden,
      cfg_to_turnoff_n => cfg_to_turnoff_n,
      l0_set_detected_corr_error => fe_l0_set_detected_corr_error,
      mac_link_up => fe_l0_mac_link_up,
      mgmt_wren => bridge_mgmt_wren,
      bus_master_enable => fe_bus_master_enable,
      cfg_rd_en_n => NLW_pcie_blk_if_cf_bridge_cfg_rd_en_n_UNCONNECTED,
      cfg_err_ecrc_n => NLW_pcie_blk_if_cf_bridge_cfg_err_ecrc_n_UNCONNECTED,
      cfg_arb_tsrc_rdy_n => pcie_blk_if_cfg_arb_tsrc_rdy_n,
      io_space_enable => fe_io_space_enable,
      l0_pwr_turn_off_req => fe_l0_pwr_turn_off_req,
      parity_error_response => fe_parity_error_response,
      cfg_rd_wr_done_n => cfg_rd_wr_done_n,
      l0_pme_req_in => fe_l0_pme_req_in,
      rx_err_cpl_ep_n => pcie_blk_if_rx_err_cpl_ep_n,
      legacy_int_request => fe_l0_legacy_int_funct0,
      rx_err_tlp_ur_n => pcie_blk_if_rx_err_tlp_ur_n,
      l0_set_user_master_data_parity => fe_l0_set_user_master_data_parity,
      msi_8bit_en => NLW_pcie_blk_if_cf_bridge_msi_8bit_en_UNCONNECTED,
      cfg_err_locked_n => NLW_pcie_blk_if_cf_bridge_cfg_err_locked_n_UNCONNECTED,
      l0_stats_cfg_transmitted => fe_l0_stats_cfg_transmitted,
      cfg_arb_tsof_n => pcie_blk_if_cfg_arb_tsof_n,
      cfg_trn_pending_n => NLW_pcie_blk_if_cf_bridge_cfg_trn_pending_n_UNCONNECTED,
      l0_set_user_detected_parity_error => fe_l0_set_user_detected_parity_error,
      l0_set_user_signaled_target_abort => fe_l0_set_user_signalled_target_abort,
      l0_set_detected_fatal_error => fe_l0_set_detected_fatal_error,
      tx_err_wr_ep_n => pcie_blk_if_tx_err_wr_ep_n,
      rx_err_tlp_malformed_n => pcie_blk_if_rx_err_tlp_malformed_n,
      rx_err_tlp_p_cpl_n => pcie_blk_if_rx_err_tlp_p_cpl_n,
      cfg_err_cpl_timeout_n => NLW_pcie_blk_if_cf_bridge_cfg_err_cpl_timeout_n_UNCONNECTED,
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_err_ur_n => NLW_pcie_blk_if_cf_bridge_cfg_err_ur_n_UNCONNECTED,
      cfg_interrupt_n => cfg_interrupt_n,
      rx_err_cpl_abort_n => pcie_blk_if_rx_err_cpl_abort_n,
      cfg_wr_en_n => NLW_pcie_blk_if_cf_bridge_cfg_wr_en_n_UNCONNECTED,
      l0_stats_cfg_received => fe_l0_stats_cfg_received,
      l0_pme_ack => fe_l0_pme_ack,
      msi_enable => fe_l0_msi_enable0,
      cfg_pm_wake_n => NLW_pcie_blk_if_cf_bridge_cfg_pm_wake_n_UNCONNECTED,
      cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
      cfg_turnoff_ok_n => NLW_pcie_blk_if_cf_bridge_cfg_turnoff_ok_n_UNCONNECTED,
      mem_space_enable => fe_mem_space_enable,
      cfg_err_posted_n => NLW_pcie_blk_if_cf_bridge_cfg_err_posted_n_UNCONNECTED,
      rx_err_ep_n => pcie_blk_if_rx_err_ep_n,
      l0_set_unsupported_request_other_error => fe_l0_set_unsupported_request_other_error,
      cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
      l0_set_user_received_target_abort => fe_l0_set_user_received_target_abort,
      cfg_arb_tdst_rdy_n => pcie_blk_if_cfg_arb_tdst_rdy_n,
      rx_err_tlp_poisoned_n => NLW_pcie_blk_if_cf_bridge_rx_err_tlp_poisoned_n_UNCONNECTED,
      cfg_err_cor_n => NLW_pcie_blk_if_cf_bridge_cfg_err_cor_n_UNCONNECTED,
      transactions_pending => fe_l0_transactions_pending,
      cfg_interrupt_assert_n => cfg_interrupt_assert_n,
      trn_lnk_up_n => NlwRenamedSig_OI_trn_lnk_up_n,
      cfg_device_number(4) => NlwRenamedSig_OI_cfg_device_number(4),
      cfg_device_number(3) => NlwRenamedSig_OI_cfg_device_number(3),
      cfg_device_number(2) => NlwRenamedSig_OI_cfg_device_number(2),
      cfg_device_number(1) => NlwRenamedSig_OI_cfg_device_number(1),
      cfg_device_number(0) => NlwRenamedSig_OI_cfg_device_number(0),
      cfg_dstatus(15) => cfg_dstatus(15),
      cfg_dstatus(14) => cfg_dstatus(14),
      cfg_dstatus(13) => cfg_dstatus(13),
      cfg_dstatus(12) => cfg_dstatus(12),
      cfg_dstatus(11) => cfg_dstatus(11),
      cfg_dstatus(10) => cfg_dstatus(10),
      cfg_dstatus(9) => cfg_dstatus(9),
      cfg_dstatus(8) => cfg_dstatus(8),
      cfg_dstatus(7) => cfg_dstatus(7),
      cfg_dstatus(6) => cfg_dstatus(6),
      cfg_dstatus(5) => cfg_dstatus(5),
      cfg_dstatus(4) => cfg_dstatus(4),
      cfg_dstatus(3) => cfg_dstatus(3),
      cfg_dstatus(2) => cfg_dstatus(2),
      cfg_dstatus(1) => cfg_dstatus(1),
      cfg_dstatus(0) => cfg_dstatus(0),
      cfg_lcommand(15) => cfg_lcommand(15),
      cfg_lcommand(14) => cfg_lcommand(14),
      cfg_lcommand(13) => cfg_lcommand(13),
      cfg_lcommand(12) => cfg_lcommand(12),
      cfg_lcommand(11) => cfg_lcommand(11),
      cfg_lcommand(10) => cfg_lcommand(10),
      cfg_lcommand(9) => cfg_lcommand(9),
      cfg_lcommand(8) => cfg_lcommand(8),
      cfg_lcommand(7) => cfg_lcommand(7),
      cfg_lcommand(6) => cfg_lcommand(6),
      cfg_lcommand(5) => cfg_lcommand(5),
      cfg_lcommand(4) => cfg_lcommand(4),
      cfg_lcommand(3) => cfg_lcommand(3),
      cfg_lcommand(2) => cfg_lcommand(2),
      cfg_lcommand(1) => cfg_lcommand(1),
      cfg_lcommand(0) => cfg_lcommand(0),
      mgmt_bwren(3) => bridge_mgmt_bwren(3),
      mgmt_bwren(2) => bridge_mgmt_bwren(2),
      mgmt_bwren(1) => bridge_mgmt_bwren(1),
      mgmt_bwren(0) => bridge_mgmt_bwren(0),
      mgmt_addr(10) => pcie_blk_if_mgmt_addr(10),
      mgmt_addr(9) => bridge_mgmt_addr(9),
      mgmt_addr(8) => bridge_mgmt_addr(8),
      mgmt_addr(7) => bridge_mgmt_addr(7),
      mgmt_addr(6) => bridge_mgmt_addr(6),
      mgmt_addr(5) => bridge_mgmt_addr(5),
      mgmt_addr(4) => bridge_mgmt_addr(4),
      mgmt_addr(3) => bridge_mgmt_addr(3),
      mgmt_addr(2) => bridge_mgmt_addr(2),
      mgmt_addr(1) => bridge_mgmt_addr(1),
      mgmt_addr(0) => bridge_mgmt_addr(0),
      cfg_status(15) => cfg_status(15),
      cfg_status(14) => cfg_status(14),
      cfg_status(13) => cfg_status(13),
      cfg_status(12) => cfg_status(12),
      cfg_status(11) => cfg_status(11),
      cfg_status(10) => cfg_status(10),
      cfg_status(9) => cfg_status(9),
      cfg_status(8) => cfg_status(8),
      cfg_status(7) => cfg_status(7),
      cfg_status(6) => cfg_status(6),
      cfg_status(5) => cfg_status(5),
      cfg_status(4) => cfg_status(4),
      cfg_status(3) => cfg_status(3),
      cfg_status(2) => cfg_status(2),
      cfg_status(1) => cfg_status(1),
      cfg_status(0) => cfg_status(0),
      cfg_arb_td(63) => pcie_blk_if_cfg_arb_td(63),
      cfg_arb_td(62) => pcie_blk_if_cfg_arb_td(62),
      cfg_arb_td(61) => pcie_blk_if_cfg_arb_td(61),
      cfg_arb_td(60) => pcie_blk_if_cfg_arb_td(60),
      cfg_arb_td(59) => pcie_blk_if_cfg_arb_td(59),
      cfg_arb_td(58) => pcie_blk_if_cfg_arb_td(58),
      cfg_arb_td(57) => pcie_blk_if_cfg_arb_td(57),
      cfg_arb_td(56) => pcie_blk_if_cfg_arb_td(56),
      cfg_arb_td(55) => pcie_blk_if_cfg_arb_td(55),
      cfg_arb_td(54) => pcie_blk_if_cfg_arb_td(54),
      cfg_arb_td(53) => pcie_blk_if_cfg_arb_td(53),
      cfg_arb_td(52) => pcie_blk_if_cfg_arb_td(52),
      cfg_arb_td(51) => pcie_blk_if_cfg_arb_td(51),
      cfg_arb_td(50) => pcie_blk_if_cfg_arb_td(50),
      cfg_arb_td(49) => pcie_blk_if_cfg_arb_td(49),
      cfg_arb_td(48) => pcie_blk_if_cfg_arb_td(48),
      cfg_arb_td(47) => pcie_blk_if_cfg_arb_td(47),
      cfg_arb_td(46) => pcie_blk_if_cfg_arb_td(46),
      cfg_arb_td(45) => pcie_blk_if_cfg_arb_td(45),
      cfg_arb_td(44) => pcie_blk_if_cfg_arb_td(44),
      cfg_arb_td(43) => pcie_blk_if_cfg_arb_td(43),
      cfg_arb_td(42) => pcie_blk_if_cfg_arb_td(42),
      cfg_arb_td(41) => pcie_blk_if_cfg_arb_td(41),
      cfg_arb_td(40) => pcie_blk_if_cfg_arb_td(40),
      cfg_arb_td(39) => pcie_blk_if_cfg_arb_td(39),
      cfg_arb_td(38) => pcie_blk_if_cfg_arb_td(38),
      cfg_arb_td(37) => pcie_blk_if_cfg_arb_td(37),
      cfg_arb_td(36) => pcie_blk_if_cfg_arb_td(36),
      cfg_arb_td(35) => pcie_blk_if_cfg_arb_td(35),
      cfg_arb_td(34) => pcie_blk_if_cfg_arb_td(34),
      cfg_arb_td(33) => pcie_blk_if_cfg_arb_td(33),
      cfg_arb_td(32) => pcie_blk_if_cfg_arb_td(32),
      cfg_arb_td(31) => pcie_blk_if_cfg_arb_td(31),
      cfg_arb_td(30) => pcie_blk_if_cfg_arb_td(30),
      cfg_arb_td(29) => pcie_blk_if_cfg_arb_td(29),
      cfg_arb_td(28) => pcie_blk_if_cfg_arb_td(28),
      cfg_arb_td(27) => pcie_blk_if_cfg_arb_td(27),
      cfg_arb_td(26) => pcie_blk_if_cfg_arb_td(26),
      cfg_arb_td(25) => pcie_blk_if_cfg_arb_td(25),
      cfg_arb_td(24) => pcie_blk_if_cfg_arb_td(24),
      cfg_arb_td(23) => pcie_blk_if_cfg_arb_td(23),
      cfg_arb_td(22) => pcie_blk_if_cfg_arb_td(22),
      cfg_arb_td(21) => pcie_blk_if_cfg_arb_td(21),
      cfg_arb_td(20) => pcie_blk_if_cfg_arb_td(20),
      cfg_arb_td(19) => pcie_blk_if_cfg_arb_td(19),
      cfg_arb_td(18) => pcie_blk_if_cfg_arb_td(18),
      cfg_arb_td(17) => pcie_blk_if_cfg_arb_td(17),
      cfg_arb_td(16) => pcie_blk_if_cfg_arb_td(16),
      cfg_arb_td(15) => pcie_blk_if_cfg_arb_td(15),
      cfg_arb_td(14) => pcie_blk_if_cfg_arb_td(14),
      cfg_arb_td(13) => pcie_blk_if_cfg_arb_td(13),
      cfg_arb_td(12) => pcie_blk_if_cfg_arb_td(12),
      cfg_arb_td(11) => pcie_blk_if_cfg_arb_td(11),
      cfg_arb_td(10) => pcie_blk_if_cfg_arb_td(10),
      cfg_arb_td(9) => pcie_blk_if_cfg_arb_td(9),
      cfg_arb_td(8) => pcie_blk_if_cfg_arb_td(8),
      cfg_arb_td(7) => pcie_blk_if_cfg_arb_td(7),
      cfg_arb_td(6) => pcie_blk_if_cfg_arb_td(6),
      cfg_arb_td(5) => pcie_blk_if_cfg_arb_td(5),
      cfg_arb_td(4) => pcie_blk_if_cfg_arb_td(4),
      cfg_arb_td(3) => pcie_blk_if_cfg_arb_td(3),
      cfg_arb_td(2) => pcie_blk_if_cfg_arb_td(2),
      cfg_arb_td(1) => pcie_blk_if_cfg_arb_td(1),
      cfg_arb_td(0) => pcie_blk_if_cfg_arb_td(0),
      cfg_dcap(31) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_31_UNCONNECTED,
      cfg_dcap(30) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_30_UNCONNECTED,
      cfg_dcap(29) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_29_UNCONNECTED,
      cfg_dcap(28) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_28_UNCONNECTED,
      cfg_dcap(27) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_27_UNCONNECTED,
      cfg_dcap(26) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_26_UNCONNECTED,
      cfg_dcap(25) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_25_UNCONNECTED,
      cfg_dcap(24) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_24_UNCONNECTED,
      cfg_dcap(23) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_23_UNCONNECTED,
      cfg_dcap(22) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_22_UNCONNECTED,
      cfg_dcap(21) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_21_UNCONNECTED,
      cfg_dcap(20) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_20_UNCONNECTED,
      cfg_dcap(19) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_19_UNCONNECTED,
      cfg_dcap(18) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_18_UNCONNECTED,
      cfg_dcap(17) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_17_UNCONNECTED,
      cfg_dcap(16) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_16_UNCONNECTED,
      cfg_dcap(15) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_15_UNCONNECTED,
      cfg_dcap(14) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_14_UNCONNECTED,
      cfg_dcap(13) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_13_UNCONNECTED,
      cfg_dcap(12) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_12_UNCONNECTED,
      cfg_dcap(11) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_11_UNCONNECTED,
      cfg_dcap(10) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_10_UNCONNECTED,
      cfg_dcap(9) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_9_UNCONNECTED,
      cfg_dcap(8) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_8_UNCONNECTED,
      cfg_dcap(7) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_7_UNCONNECTED,
      cfg_dcap(6) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_6_UNCONNECTED,
      cfg_dcap(5) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_5_UNCONNECTED,
      cfg_dcap(4) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_4_UNCONNECTED,
      cfg_dcap(3) => NLW_pcie_blk_if_cf_bridge_cfg_dcap_3_UNCONNECTED,
      cfg_dcap(2) => pcie_blk_if_cfg_dcap(2),
      cfg_dcap(1) => pcie_blk_if_cfg_dcap(1),
      cfg_dcap(0) => pcie_blk_if_cfg_dcap(0),
      cfg_interrupt_do(7) => cfg_interrupt_do(7),
      cfg_interrupt_do(6) => cfg_interrupt_do(6),
      cfg_interrupt_do(5) => cfg_interrupt_do(5),
      cfg_interrupt_do(4) => cfg_interrupt_do(4),
      cfg_interrupt_do(3) => cfg_interrupt_do(3),
      cfg_interrupt_do(2) => cfg_interrupt_do(2),
      cfg_interrupt_do(1) => cfg_interrupt_do(1),
      cfg_interrupt_do(0) => cfg_interrupt_do(0),
      cfg_interrupt_mmenable(2) => cfg_interrupt_mmenable(2),
      cfg_interrupt_mmenable(1) => cfg_interrupt_mmenable(1),
      cfg_interrupt_mmenable(0) => cfg_interrupt_mmenable(0),
      cfg_rx_xrom(31) => pcie_blk_if_cfg_rx_xrom(31),
      cfg_rx_xrom(30) => pcie_blk_if_cfg_rx_xrom(30),
      cfg_rx_xrom(29) => pcie_blk_if_cfg_rx_xrom(29),
      cfg_rx_xrom(28) => pcie_blk_if_cfg_rx_xrom(28),
      cfg_rx_xrom(27) => pcie_blk_if_cfg_rx_xrom(27),
      cfg_rx_xrom(26) => pcie_blk_if_cfg_rx_xrom(26),
      cfg_rx_xrom(25) => pcie_blk_if_cfg_rx_xrom(25),
      cfg_rx_xrom(24) => pcie_blk_if_cfg_rx_xrom(24),
      cfg_rx_xrom(23) => pcie_blk_if_cfg_rx_xrom(23),
      cfg_rx_xrom(22) => pcie_blk_if_cfg_rx_xrom(22),
      cfg_rx_xrom(21) => pcie_blk_if_cfg_rx_xrom(21),
      cfg_rx_xrom(20) => pcie_blk_if_cfg_rx_xrom(20),
      cfg_rx_xrom(19) => pcie_blk_if_cfg_rx_xrom(19),
      cfg_rx_xrom(18) => pcie_blk_if_cfg_rx_xrom(18),
      cfg_rx_xrom(17) => pcie_blk_if_cfg_rx_xrom(17),
      cfg_rx_xrom(16) => pcie_blk_if_cfg_rx_xrom(16),
      cfg_rx_xrom(15) => pcie_blk_if_cfg_rx_xrom(15),
      cfg_rx_xrom(14) => pcie_blk_if_cfg_rx_xrom(14),
      cfg_rx_xrom(13) => pcie_blk_if_cfg_rx_xrom(13),
      cfg_rx_xrom(12) => pcie_blk_if_cfg_rx_xrom(12),
      cfg_rx_xrom(11) => pcie_blk_if_cfg_rx_xrom(11),
      cfg_rx_xrom(10) => pcie_blk_if_cfg_rx_xrom(10),
      cfg_rx_xrom(9) => pcie_blk_if_cfg_rx_xrom(9),
      cfg_rx_xrom(8) => pcie_blk_if_cfg_rx_xrom(8),
      cfg_rx_xrom(7) => pcie_blk_if_cfg_rx_xrom(7),
      cfg_rx_xrom(6) => pcie_blk_if_cfg_rx_xrom(6),
      cfg_rx_xrom(5) => pcie_blk_if_cfg_rx_xrom(5),
      cfg_rx_xrom(4) => pcie_blk_if_cfg_rx_xrom(4),
      cfg_rx_xrom(3) => pcie_blk_if_cfg_rx_xrom(3),
      cfg_rx_xrom(2) => pcie_blk_if_cfg_rx_xrom(2),
      cfg_rx_xrom(1) => pcie_blk_if_cfg_rx_xrom(1),
      cfg_rx_xrom(0) => pcie_blk_if_cfg_rx_xrom(0),
      cfg_bus_number(7) => NlwRenamedSig_OI_cfg_bus_number(7),
      cfg_bus_number(6) => NlwRenamedSig_OI_cfg_bus_number(6),
      cfg_bus_number(5) => NlwRenamedSig_OI_cfg_bus_number(5),
      cfg_bus_number(4) => NlwRenamedSig_OI_cfg_bus_number(4),
      cfg_bus_number(3) => NlwRenamedSig_OI_cfg_bus_number(3),
      cfg_bus_number(2) => NlwRenamedSig_OI_cfg_bus_number(2),
      cfg_bus_number(1) => NlwRenamedSig_OI_cfg_bus_number(1),
      cfg_bus_number(0) => NlwRenamedSig_OI_cfg_bus_number(0),
      msi_request(3) => fe_l0_msi_request0(3),
      msi_request(2) => fe_l0_msi_request0(2),
      msi_request(1) => fe_l0_msi_request0(1),
      msi_request(0) => fe_l0_msi_request0(0),
      cfg_pmcsr(31) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_31_UNCONNECTED,
      cfg_pmcsr(30) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_30_UNCONNECTED,
      cfg_pmcsr(29) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_29_UNCONNECTED,
      cfg_pmcsr(28) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_28_UNCONNECTED,
      cfg_pmcsr(27) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_27_UNCONNECTED,
      cfg_pmcsr(26) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_26_UNCONNECTED,
      cfg_pmcsr(25) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_25_UNCONNECTED,
      cfg_pmcsr(24) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_24_UNCONNECTED,
      cfg_pmcsr(23) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_23_UNCONNECTED,
      cfg_pmcsr(22) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_22_UNCONNECTED,
      cfg_pmcsr(21) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_21_UNCONNECTED,
      cfg_pmcsr(20) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_20_UNCONNECTED,
      cfg_pmcsr(19) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_19_UNCONNECTED,
      cfg_pmcsr(18) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_18_UNCONNECTED,
      cfg_pmcsr(17) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_17_UNCONNECTED,
      cfg_pmcsr(16) => NLW_pcie_blk_if_cf_bridge_cfg_pmcsr_16_UNCONNECTED,
      cfg_pmcsr(15) => pcie_blk_if_cfg_pmcsr(15),
      cfg_pmcsr(14) => pcie_blk_if_cfg_pmcsr(14),
      cfg_pmcsr(13) => pcie_blk_if_cfg_pmcsr(13),
      cfg_pmcsr(12) => pcie_blk_if_cfg_pmcsr(12),
      cfg_pmcsr(11) => pcie_blk_if_cfg_pmcsr(11),
      cfg_pmcsr(10) => pcie_blk_if_cfg_pmcsr(10),
      cfg_pmcsr(9) => pcie_blk_if_cfg_pmcsr(9),
      cfg_pmcsr(8) => pcie_blk_if_cfg_pmcsr(8),
      cfg_pmcsr(7) => pcie_blk_if_cfg_pmcsr(7),
      cfg_pmcsr(6) => pcie_blk_if_cfg_pmcsr(6),
      cfg_pmcsr(5) => pcie_blk_if_cfg_pmcsr(5),
      cfg_pmcsr(4) => pcie_blk_if_cfg_pmcsr(4),
      cfg_pmcsr(3) => pcie_blk_if_cfg_pmcsr(3),
      cfg_pmcsr(2) => pcie_blk_if_cfg_pmcsr(2),
      cfg_pmcsr(1) => pcie_blk_if_cfg_pmcsr(1),
      cfg_pmcsr(0) => pcie_blk_if_cfg_pmcsr(0),
      cfg_arb_trem_n(7) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_7_UNCONNECTED,
      cfg_arb_trem_n(6) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_6_UNCONNECTED,
      cfg_arb_trem_n(5) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_5_UNCONNECTED,
      cfg_arb_trem_n(4) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_4_UNCONNECTED,
      cfg_arb_trem_n(3) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_3_UNCONNECTED,
      cfg_arb_trem_n(2) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_2_UNCONNECTED,
      cfg_arb_trem_n(1) => NLW_pcie_blk_if_cf_bridge_cfg_arb_trem_n_1_UNCONNECTED,
      cfg_arb_trem_n(0) => pcie_blk_if_cfg_arb_trem_n(0),
      cfg_command(15) => cfg_command(15),
      cfg_command(14) => cfg_command(14),
      cfg_command(13) => cfg_command(13),
      cfg_command(12) => cfg_command(12),
      cfg_command(11) => cfg_command(11),
      cfg_command(10) => cfg_command(10),
      cfg_command(9) => cfg_command(9),
      cfg_command(8) => cfg_command(8),
      cfg_command(7) => cfg_command(7),
      cfg_command(6) => cfg_command(6),
      cfg_command(5) => cfg_command(5),
      cfg_command(4) => cfg_command(4),
      cfg_command(3) => cfg_command(3),
      cfg_command(2) => cfg_command(2),
      cfg_command(1) => NlwRenamedSig_OI_cfg_command(1),
      cfg_command(0) => NlwRenamedSig_OI_cfg_command(0),
      cfg_lstatus(15) => cfg_lstatus(15),
      cfg_lstatus(14) => cfg_lstatus(14),
      cfg_lstatus(13) => cfg_lstatus(13),
      cfg_lstatus(12) => cfg_lstatus(12),
      cfg_lstatus(11) => cfg_lstatus(11),
      cfg_lstatus(10) => cfg_lstatus(10),
      cfg_lstatus(9) => cfg_lstatus(9),
      cfg_lstatus(8) => cfg_lstatus(8),
      cfg_lstatus(7) => cfg_lstatus(7),
      cfg_lstatus(6) => cfg_lstatus(6),
      cfg_lstatus(5) => cfg_lstatus(5),
      cfg_lstatus(4) => cfg_lstatus(4),
      cfg_lstatus(3) => cfg_lstatus(3),
      cfg_lstatus(2) => cfg_lstatus(2),
      cfg_lstatus(1) => cfg_lstatus(1),
      cfg_lstatus(0) => cfg_lstatus(0),
      cfg_dcommand(15) => NlwRenamedSig_OI_cfg_dcommand(15),
      cfg_dcommand(14) => NlwRenamedSig_OI_cfg_dcommand(14),
      cfg_dcommand(13) => NlwRenamedSig_OI_cfg_dcommand(13),
      cfg_dcommand(12) => NlwRenamedSig_OI_cfg_dcommand(12),
      cfg_dcommand(11) => NlwRenamedSig_OI_cfg_dcommand(11),
      cfg_dcommand(10) => NlwRenamedSig_OI_cfg_dcommand(10),
      cfg_dcommand(9) => NlwRenamedSig_OI_cfg_dcommand(9),
      cfg_dcommand(8) => NlwRenamedSig_OI_cfg_dcommand(8),
      cfg_dcommand(7) => NlwRenamedSig_OI_cfg_dcommand(7),
      cfg_dcommand(6) => NlwRenamedSig_OI_cfg_dcommand(6),
      cfg_dcommand(5) => NlwRenamedSig_OI_cfg_dcommand(5),
      cfg_dcommand(4) => NlwRenamedSig_OI_cfg_dcommand(4),
      cfg_dcommand(3) => NlwRenamedSig_OI_cfg_dcommand(3),
      cfg_dcommand(2) => NlwRenamedSig_OI_cfg_dcommand(2),
      cfg_dcommand(1) => NlwRenamedSig_OI_cfg_dcommand(1),
      cfg_dcommand(0) => NlwRenamedSig_OI_cfg_dcommand(0),
      cfg_pcie_link_state_n(2) => cfg_pcie_link_state_n(2),
      cfg_pcie_link_state_n(1) => cfg_pcie_link_state_n(1),
      cfg_pcie_link_state_n(0) => cfg_pcie_link_state_n(0),
      cfg_function_number(2) => NlwRenamedSig_OI_cfg_function_number(2),
      cfg_function_number(1) => NlwRenamedSig_OI_cfg_function_number(1),
      cfg_function_number(0) => NlwRenamedSig_OI_cfg_function_number(0),
      cfg_rx_bar0(31) => pcie_blk_if_cfg_rx_bar0(31),
      cfg_rx_bar0(30) => pcie_blk_if_cfg_rx_bar0(30),
      cfg_rx_bar0(29) => pcie_blk_if_cfg_rx_bar0(29),
      cfg_rx_bar0(28) => pcie_blk_if_cfg_rx_bar0(28),
      cfg_rx_bar0(27) => pcie_blk_if_cfg_rx_bar0(27),
      cfg_rx_bar0(26) => pcie_blk_if_cfg_rx_bar0(26),
      cfg_rx_bar0(25) => pcie_blk_if_cfg_rx_bar0(25),
      cfg_rx_bar0(24) => pcie_blk_if_cfg_rx_bar0(24),
      cfg_rx_bar0(23) => pcie_blk_if_cfg_rx_bar0(23),
      cfg_rx_bar0(22) => pcie_blk_if_cfg_rx_bar0(22),
      cfg_rx_bar0(21) => pcie_blk_if_cfg_rx_bar0(21),
      cfg_rx_bar0(20) => pcie_blk_if_cfg_rx_bar0(20),
      cfg_rx_bar0(19) => pcie_blk_if_cfg_rx_bar0(19),
      cfg_rx_bar0(18) => pcie_blk_if_cfg_rx_bar0(18),
      cfg_rx_bar0(17) => pcie_blk_if_cfg_rx_bar0(17),
      cfg_rx_bar0(16) => pcie_blk_if_cfg_rx_bar0(16),
      cfg_rx_bar0(15) => pcie_blk_if_cfg_rx_bar0(15),
      cfg_rx_bar0(14) => pcie_blk_if_cfg_rx_bar0(14),
      cfg_rx_bar0(13) => pcie_blk_if_cfg_rx_bar0(13),
      cfg_rx_bar0(12) => pcie_blk_if_cfg_rx_bar0(12),
      cfg_rx_bar0(11) => pcie_blk_if_cfg_rx_bar0(11),
      cfg_rx_bar0(10) => pcie_blk_if_cfg_rx_bar0(10),
      cfg_rx_bar0(9) => pcie_blk_if_cfg_rx_bar0(9),
      cfg_rx_bar0(8) => pcie_blk_if_cfg_rx_bar0(8),
      cfg_rx_bar0(7) => pcie_blk_if_cfg_rx_bar0(7),
      cfg_rx_bar0(6) => pcie_blk_if_cfg_rx_bar0(6),
      cfg_rx_bar0(5) => pcie_blk_if_cfg_rx_bar0(5),
      cfg_rx_bar0(4) => pcie_blk_if_cfg_rx_bar0(4),
      cfg_rx_bar0(3) => pcie_blk_if_cfg_rx_bar0(3),
      cfg_rx_bar0(2) => pcie_blk_if_cfg_rx_bar0(2),
      cfg_rx_bar0(1) => pcie_blk_if_cfg_rx_bar0(1),
      cfg_rx_bar0(0) => pcie_blk_if_cfg_rx_bar0(0),
      mgmt_wdata(31) => bridge_mgmt_wdata(31),
      mgmt_wdata(30) => bridge_mgmt_wdata(30),
      mgmt_wdata(29) => bridge_mgmt_wdata(29),
      mgmt_wdata(28) => bridge_mgmt_wdata(28),
      mgmt_wdata(27) => bridge_mgmt_wdata(27),
      mgmt_wdata(26) => bridge_mgmt_wdata(26),
      mgmt_wdata(25) => bridge_mgmt_wdata(25),
      mgmt_wdata(24) => bridge_mgmt_wdata(24),
      mgmt_wdata(23) => bridge_mgmt_wdata(23),
      mgmt_wdata(22) => bridge_mgmt_wdata(22),
      mgmt_wdata(21) => bridge_mgmt_wdata(21),
      mgmt_wdata(20) => bridge_mgmt_wdata(20),
      mgmt_wdata(19) => bridge_mgmt_wdata(19),
      mgmt_wdata(18) => bridge_mgmt_wdata(18),
      mgmt_wdata(17) => bridge_mgmt_wdata(17),
      mgmt_wdata(16) => bridge_mgmt_wdata(16),
      mgmt_wdata(15) => bridge_mgmt_wdata(15),
      mgmt_wdata(14) => bridge_mgmt_wdata(14),
      mgmt_wdata(13) => bridge_mgmt_wdata(13),
      mgmt_wdata(12) => bridge_mgmt_wdata(12),
      mgmt_wdata(11) => bridge_mgmt_wdata(11),
      mgmt_wdata(10) => bridge_mgmt_wdata(10),
      mgmt_wdata(9) => bridge_mgmt_wdata(9),
      mgmt_wdata(8) => bridge_mgmt_wdata(8),
      mgmt_wdata(7) => bridge_mgmt_wdata(7),
      mgmt_wdata(6) => bridge_mgmt_wdata(6),
      mgmt_wdata(5) => bridge_mgmt_wdata(5),
      mgmt_wdata(4) => bridge_mgmt_wdata(4),
      mgmt_wdata(3) => bridge_mgmt_wdata(3),
      mgmt_wdata(2) => bridge_mgmt_wdata(2),
      mgmt_wdata(1) => bridge_mgmt_wdata(1),
      mgmt_wdata(0) => bridge_mgmt_wdata(0),
      cfg_rx_bar1(31) => pcie_blk_if_cfg_rx_bar1(31),
      cfg_rx_bar1(30) => pcie_blk_if_cfg_rx_bar1(30),
      cfg_rx_bar1(29) => pcie_blk_if_cfg_rx_bar1(29),
      cfg_rx_bar1(28) => pcie_blk_if_cfg_rx_bar1(28),
      cfg_rx_bar1(27) => pcie_blk_if_cfg_rx_bar1(27),
      cfg_rx_bar1(26) => pcie_blk_if_cfg_rx_bar1(26),
      cfg_rx_bar1(25) => pcie_blk_if_cfg_rx_bar1(25),
      cfg_rx_bar1(24) => pcie_blk_if_cfg_rx_bar1(24),
      cfg_rx_bar1(23) => pcie_blk_if_cfg_rx_bar1(23),
      cfg_rx_bar1(22) => pcie_blk_if_cfg_rx_bar1(22),
      cfg_rx_bar1(21) => pcie_blk_if_cfg_rx_bar1(21),
      cfg_rx_bar1(20) => pcie_blk_if_cfg_rx_bar1(20),
      cfg_rx_bar1(19) => pcie_blk_if_cfg_rx_bar1(19),
      cfg_rx_bar1(18) => pcie_blk_if_cfg_rx_bar1(18),
      cfg_rx_bar1(17) => pcie_blk_if_cfg_rx_bar1(17),
      cfg_rx_bar1(16) => pcie_blk_if_cfg_rx_bar1(16),
      cfg_rx_bar1(15) => pcie_blk_if_cfg_rx_bar1(15),
      cfg_rx_bar1(14) => pcie_blk_if_cfg_rx_bar1(14),
      cfg_rx_bar1(13) => pcie_blk_if_cfg_rx_bar1(13),
      cfg_rx_bar1(12) => pcie_blk_if_cfg_rx_bar1(12),
      cfg_rx_bar1(11) => pcie_blk_if_cfg_rx_bar1(11),
      cfg_rx_bar1(10) => pcie_blk_if_cfg_rx_bar1(10),
      cfg_rx_bar1(9) => pcie_blk_if_cfg_rx_bar1(9),
      cfg_rx_bar1(8) => pcie_blk_if_cfg_rx_bar1(8),
      cfg_rx_bar1(7) => pcie_blk_if_cfg_rx_bar1(7),
      cfg_rx_bar1(6) => pcie_blk_if_cfg_rx_bar1(6),
      cfg_rx_bar1(5) => pcie_blk_if_cfg_rx_bar1(5),
      cfg_rx_bar1(4) => pcie_blk_if_cfg_rx_bar1(4),
      cfg_rx_bar1(3) => pcie_blk_if_cfg_rx_bar1(3),
      cfg_rx_bar1(2) => pcie_blk_if_cfg_rx_bar1(2),
      cfg_rx_bar1(1) => pcie_blk_if_cfg_rx_bar1(1),
      cfg_rx_bar1(0) => pcie_blk_if_cfg_rx_bar1(0),
      cfg_rx_bar2(31) => pcie_blk_if_cfg_rx_bar2(31),
      cfg_rx_bar2(30) => pcie_blk_if_cfg_rx_bar2(30),
      cfg_rx_bar2(29) => pcie_blk_if_cfg_rx_bar2(29),
      cfg_rx_bar2(28) => pcie_blk_if_cfg_rx_bar2(28),
      cfg_rx_bar2(27) => pcie_blk_if_cfg_rx_bar2(27),
      cfg_rx_bar2(26) => pcie_blk_if_cfg_rx_bar2(26),
      cfg_rx_bar2(25) => pcie_blk_if_cfg_rx_bar2(25),
      cfg_rx_bar2(24) => pcie_blk_if_cfg_rx_bar2(24),
      cfg_rx_bar2(23) => pcie_blk_if_cfg_rx_bar2(23),
      cfg_rx_bar2(22) => pcie_blk_if_cfg_rx_bar2(22),
      cfg_rx_bar2(21) => pcie_blk_if_cfg_rx_bar2(21),
      cfg_rx_bar2(20) => pcie_blk_if_cfg_rx_bar2(20),
      cfg_rx_bar2(19) => pcie_blk_if_cfg_rx_bar2(19),
      cfg_rx_bar2(18) => pcie_blk_if_cfg_rx_bar2(18),
      cfg_rx_bar2(17) => pcie_blk_if_cfg_rx_bar2(17),
      cfg_rx_bar2(16) => pcie_blk_if_cfg_rx_bar2(16),
      cfg_rx_bar2(15) => pcie_blk_if_cfg_rx_bar2(15),
      cfg_rx_bar2(14) => pcie_blk_if_cfg_rx_bar2(14),
      cfg_rx_bar2(13) => pcie_blk_if_cfg_rx_bar2(13),
      cfg_rx_bar2(12) => pcie_blk_if_cfg_rx_bar2(12),
      cfg_rx_bar2(11) => pcie_blk_if_cfg_rx_bar2(11),
      cfg_rx_bar2(10) => pcie_blk_if_cfg_rx_bar2(10),
      cfg_rx_bar2(9) => pcie_blk_if_cfg_rx_bar2(9),
      cfg_rx_bar2(8) => pcie_blk_if_cfg_rx_bar2(8),
      cfg_rx_bar2(7) => pcie_blk_if_cfg_rx_bar2(7),
      cfg_rx_bar2(6) => pcie_blk_if_cfg_rx_bar2(6),
      cfg_rx_bar2(5) => pcie_blk_if_cfg_rx_bar2(5),
      cfg_rx_bar2(4) => pcie_blk_if_cfg_rx_bar2(4),
      cfg_rx_bar2(3) => pcie_blk_if_cfg_rx_bar2(3),
      cfg_rx_bar2(2) => pcie_blk_if_cfg_rx_bar2(2),
      cfg_rx_bar2(1) => pcie_blk_if_cfg_rx_bar2(1),
      cfg_rx_bar2(0) => pcie_blk_if_cfg_rx_bar2(0),
      cfg_rx_bar3(31) => pcie_blk_if_cfg_rx_bar3(31),
      cfg_rx_bar3(30) => pcie_blk_if_cfg_rx_bar3(30),
      cfg_rx_bar3(29) => pcie_blk_if_cfg_rx_bar3(29),
      cfg_rx_bar3(28) => pcie_blk_if_cfg_rx_bar3(28),
      cfg_rx_bar3(27) => pcie_blk_if_cfg_rx_bar3(27),
      cfg_rx_bar3(26) => pcie_blk_if_cfg_rx_bar3(26),
      cfg_rx_bar3(25) => pcie_blk_if_cfg_rx_bar3(25),
      cfg_rx_bar3(24) => pcie_blk_if_cfg_rx_bar3(24),
      cfg_rx_bar3(23) => pcie_blk_if_cfg_rx_bar3(23),
      cfg_rx_bar3(22) => pcie_blk_if_cfg_rx_bar3(22),
      cfg_rx_bar3(21) => pcie_blk_if_cfg_rx_bar3(21),
      cfg_rx_bar3(20) => pcie_blk_if_cfg_rx_bar3(20),
      cfg_rx_bar3(19) => pcie_blk_if_cfg_rx_bar3(19),
      cfg_rx_bar3(18) => pcie_blk_if_cfg_rx_bar3(18),
      cfg_rx_bar3(17) => pcie_blk_if_cfg_rx_bar3(17),
      cfg_rx_bar3(16) => pcie_blk_if_cfg_rx_bar3(16),
      cfg_rx_bar3(15) => pcie_blk_if_cfg_rx_bar3(15),
      cfg_rx_bar3(14) => pcie_blk_if_cfg_rx_bar3(14),
      cfg_rx_bar3(13) => pcie_blk_if_cfg_rx_bar3(13),
      cfg_rx_bar3(12) => pcie_blk_if_cfg_rx_bar3(12),
      cfg_rx_bar3(11) => pcie_blk_if_cfg_rx_bar3(11),
      cfg_rx_bar3(10) => pcie_blk_if_cfg_rx_bar3(10),
      cfg_rx_bar3(9) => pcie_blk_if_cfg_rx_bar3(9),
      cfg_rx_bar3(8) => pcie_blk_if_cfg_rx_bar3(8),
      cfg_rx_bar3(7) => pcie_blk_if_cfg_rx_bar3(7),
      cfg_rx_bar3(6) => pcie_blk_if_cfg_rx_bar3(6),
      cfg_rx_bar3(5) => pcie_blk_if_cfg_rx_bar3(5),
      cfg_rx_bar3(4) => pcie_blk_if_cfg_rx_bar3(4),
      cfg_rx_bar3(3) => pcie_blk_if_cfg_rx_bar3(3),
      cfg_rx_bar3(2) => pcie_blk_if_cfg_rx_bar3(2),
      cfg_rx_bar3(1) => pcie_blk_if_cfg_rx_bar3(1),
      cfg_rx_bar3(0) => pcie_blk_if_cfg_rx_bar3(0),
      cfg_rx_bar4(31) => pcie_blk_if_cfg_rx_bar4(31),
      cfg_rx_bar4(30) => pcie_blk_if_cfg_rx_bar4(30),
      cfg_rx_bar4(29) => pcie_blk_if_cfg_rx_bar4(29),
      cfg_rx_bar4(28) => pcie_blk_if_cfg_rx_bar4(28),
      cfg_rx_bar4(27) => pcie_blk_if_cfg_rx_bar4(27),
      cfg_rx_bar4(26) => pcie_blk_if_cfg_rx_bar4(26),
      cfg_rx_bar4(25) => pcie_blk_if_cfg_rx_bar4(25),
      cfg_rx_bar4(24) => pcie_blk_if_cfg_rx_bar4(24),
      cfg_rx_bar4(23) => pcie_blk_if_cfg_rx_bar4(23),
      cfg_rx_bar4(22) => pcie_blk_if_cfg_rx_bar4(22),
      cfg_rx_bar4(21) => pcie_blk_if_cfg_rx_bar4(21),
      cfg_rx_bar4(20) => pcie_blk_if_cfg_rx_bar4(20),
      cfg_rx_bar4(19) => pcie_blk_if_cfg_rx_bar4(19),
      cfg_rx_bar4(18) => pcie_blk_if_cfg_rx_bar4(18),
      cfg_rx_bar4(17) => pcie_blk_if_cfg_rx_bar4(17),
      cfg_rx_bar4(16) => pcie_blk_if_cfg_rx_bar4(16),
      cfg_rx_bar4(15) => pcie_blk_if_cfg_rx_bar4(15),
      cfg_rx_bar4(14) => pcie_blk_if_cfg_rx_bar4(14),
      cfg_rx_bar4(13) => pcie_blk_if_cfg_rx_bar4(13),
      cfg_rx_bar4(12) => pcie_blk_if_cfg_rx_bar4(12),
      cfg_rx_bar4(11) => pcie_blk_if_cfg_rx_bar4(11),
      cfg_rx_bar4(10) => pcie_blk_if_cfg_rx_bar4(10),
      cfg_rx_bar4(9) => pcie_blk_if_cfg_rx_bar4(9),
      cfg_rx_bar4(8) => pcie_blk_if_cfg_rx_bar4(8),
      cfg_rx_bar4(7) => pcie_blk_if_cfg_rx_bar4(7),
      cfg_rx_bar4(6) => pcie_blk_if_cfg_rx_bar4(6),
      cfg_rx_bar4(5) => pcie_blk_if_cfg_rx_bar4(5),
      cfg_rx_bar4(4) => pcie_blk_if_cfg_rx_bar4(4),
      cfg_rx_bar4(3) => pcie_blk_if_cfg_rx_bar4(3),
      cfg_rx_bar4(2) => pcie_blk_if_cfg_rx_bar4(2),
      cfg_rx_bar4(1) => pcie_blk_if_cfg_rx_bar4(1),
      cfg_rx_bar4(0) => pcie_blk_if_cfg_rx_bar4(0),
      cfg_rx_bar5(31) => pcie_blk_if_cfg_rx_bar5(31),
      cfg_rx_bar5(30) => pcie_blk_if_cfg_rx_bar5(30),
      cfg_rx_bar5(29) => pcie_blk_if_cfg_rx_bar5(29),
      cfg_rx_bar5(28) => pcie_blk_if_cfg_rx_bar5(28),
      cfg_rx_bar5(27) => pcie_blk_if_cfg_rx_bar5(27),
      cfg_rx_bar5(26) => pcie_blk_if_cfg_rx_bar5(26),
      cfg_rx_bar5(25) => pcie_blk_if_cfg_rx_bar5(25),
      cfg_rx_bar5(24) => pcie_blk_if_cfg_rx_bar5(24),
      cfg_rx_bar5(23) => pcie_blk_if_cfg_rx_bar5(23),
      cfg_rx_bar5(22) => pcie_blk_if_cfg_rx_bar5(22),
      cfg_rx_bar5(21) => pcie_blk_if_cfg_rx_bar5(21),
      cfg_rx_bar5(20) => pcie_blk_if_cfg_rx_bar5(20),
      cfg_rx_bar5(19) => pcie_blk_if_cfg_rx_bar5(19),
      cfg_rx_bar5(18) => pcie_blk_if_cfg_rx_bar5(18),
      cfg_rx_bar5(17) => pcie_blk_if_cfg_rx_bar5(17),
      cfg_rx_bar5(16) => pcie_blk_if_cfg_rx_bar5(16),
      cfg_rx_bar5(15) => pcie_blk_if_cfg_rx_bar5(15),
      cfg_rx_bar5(14) => pcie_blk_if_cfg_rx_bar5(14),
      cfg_rx_bar5(13) => pcie_blk_if_cfg_rx_bar5(13),
      cfg_rx_bar5(12) => pcie_blk_if_cfg_rx_bar5(12),
      cfg_rx_bar5(11) => pcie_blk_if_cfg_rx_bar5(11),
      cfg_rx_bar5(10) => pcie_blk_if_cfg_rx_bar5(10),
      cfg_rx_bar5(9) => pcie_blk_if_cfg_rx_bar5(9),
      cfg_rx_bar5(8) => pcie_blk_if_cfg_rx_bar5(8),
      cfg_rx_bar5(7) => pcie_blk_if_cfg_rx_bar5(7),
      cfg_rx_bar5(6) => pcie_blk_if_cfg_rx_bar5(6),
      cfg_rx_bar5(5) => pcie_blk_if_cfg_rx_bar5(5),
      cfg_rx_bar5(4) => pcie_blk_if_cfg_rx_bar5(4),
      cfg_rx_bar5(3) => pcie_blk_if_cfg_rx_bar5(3),
      cfg_rx_bar5(2) => pcie_blk_if_cfg_rx_bar5(2),
      cfg_rx_bar5(1) => pcie_blk_if_cfg_rx_bar5(1),
      cfg_rx_bar5(0) => pcie_blk_if_cfg_rx_bar5(0),
      cfg_do(31) => cfg_do(31),
      cfg_do(30) => cfg_do(30),
      cfg_do(29) => cfg_do(29),
      cfg_do(28) => cfg_do(28),
      cfg_do(27) => cfg_do(27),
      cfg_do(26) => cfg_do(26),
      cfg_do(25) => cfg_do(25),
      cfg_do(24) => cfg_do(24),
      cfg_do(23) => cfg_do(23),
      cfg_do(22) => cfg_do(22),
      cfg_do(21) => cfg_do(21),
      cfg_do(20) => cfg_do(20),
      cfg_do(19) => cfg_do(19),
      cfg_do(18) => cfg_do(18),
      cfg_do(17) => cfg_do(17),
      cfg_do(16) => cfg_do(16),
      cfg_do(15) => cfg_do(15),
      cfg_do(14) => cfg_do(14),
      cfg_do(13) => cfg_do(13),
      cfg_do(12) => cfg_do(12),
      cfg_do(11) => cfg_do(11),
      cfg_do(10) => cfg_do(10),
      cfg_do(9) => cfg_do(9),
      cfg_do(8) => cfg_do(8),
      cfg_do(7) => cfg_do(7),
      cfg_do(6) => cfg_do(6),
      cfg_do(5) => cfg_do(5),
      cfg_do(4) => cfg_do(4),
      cfg_do(3) => cfg_do(3),
      cfg_do(2) => cfg_do(2),
      cfg_do(1) => cfg_do(1),
      cfg_do(0) => cfg_do(0),
      l0_ltssm_state(3) => fe_l0_ltssm_state(3),
      l0_ltssm_state(2) => fe_l0_ltssm_state(2),
      l0_ltssm_state(1) => fe_l0_ltssm_state(1),
      l0_ltssm_state(0) => fe_l0_ltssm_state(0),
      cfg_byte_en_n(3) => NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_3_UNCONNECTED,
      cfg_byte_en_n(2) => NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_2_UNCONNECTED,
      cfg_byte_en_n(1) => NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_1_UNCONNECTED,
      cfg_byte_en_n(0) => NLW_pcie_blk_if_cf_bridge_cfg_byte_en_n_0_UNCONNECTED,
      cfg_interrupt_di(7) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_7_UNCONNECTED,
      cfg_interrupt_di(6) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_6_UNCONNECTED,
      cfg_interrupt_di(5) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_5_UNCONNECTED,
      cfg_interrupt_di(4) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_4_UNCONNECTED,
      cfg_interrupt_di(3) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_3_UNCONNECTED,
      cfg_interrupt_di(2) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_2_UNCONNECTED,
      cfg_interrupt_di(1) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_1_UNCONNECTED,
      cfg_interrupt_di(0) => NLW_pcie_blk_if_cf_bridge_cfg_interrupt_di_0_UNCONNECTED,
      llk_tc_status(7) => llk_tc_status(7),
      llk_tc_status(6) => llk_tc_status(6),
      llk_tc_status(5) => llk_tc_status(5),
      llk_tc_status(4) => llk_tc_status(4),
      llk_tc_status(3) => llk_tc_status(3),
      llk_tc_status(2) => llk_tc_status(2),
      llk_tc_status(1) => llk_tc_status(1),
      llk_tc_status(0) => llk_tc_status(0),
      rx_err_tlp_hdr(47) => pcie_blk_if_rx_err_tlp_hdr(47),
      rx_err_tlp_hdr(46) => pcie_blk_if_rx_err_tlp_hdr(46),
      rx_err_tlp_hdr(45) => pcie_blk_if_rx_err_tlp_hdr(45),
      rx_err_tlp_hdr(44) => pcie_blk_if_rx_err_tlp_hdr(44),
      rx_err_tlp_hdr(43) => pcie_blk_if_rx_err_tlp_hdr(43),
      rx_err_tlp_hdr(42) => pcie_blk_if_rx_err_tlp_hdr(42),
      rx_err_tlp_hdr(41) => pcie_blk_if_rx_err_tlp_hdr(41),
      rx_err_tlp_hdr(40) => pcie_blk_if_rx_err_tlp_hdr(40),
      rx_err_tlp_hdr(39) => pcie_blk_if_rx_err_tlp_hdr(39),
      rx_err_tlp_hdr(38) => pcie_blk_if_rx_err_tlp_hdr(38),
      rx_err_tlp_hdr(37) => pcie_blk_if_rx_err_tlp_hdr(37),
      rx_err_tlp_hdr(36) => pcie_blk_if_rx_err_tlp_hdr(36),
      rx_err_tlp_hdr(35) => pcie_blk_if_rx_err_tlp_hdr(35),
      rx_err_tlp_hdr(34) => pcie_blk_if_rx_err_tlp_hdr(34),
      rx_err_tlp_hdr(33) => pcie_blk_if_rx_err_tlp_hdr(33),
      rx_err_tlp_hdr(32) => pcie_blk_if_rx_err_tlp_hdr(32),
      rx_err_tlp_hdr(31) => pcie_blk_if_rx_err_tlp_hdr(31),
      rx_err_tlp_hdr(30) => pcie_blk_if_rx_err_tlp_hdr(30),
      rx_err_tlp_hdr(29) => pcie_blk_if_rx_err_tlp_hdr(29),
      rx_err_tlp_hdr(28) => pcie_blk_if_rx_err_tlp_hdr(28),
      rx_err_tlp_hdr(27) => pcie_blk_if_rx_err_tlp_hdr(27),
      rx_err_tlp_hdr(26) => pcie_blk_if_rx_err_tlp_hdr(26),
      rx_err_tlp_hdr(25) => pcie_blk_if_rx_err_tlp_hdr(25),
      rx_err_tlp_hdr(24) => pcie_blk_if_rx_err_tlp_hdr(24),
      rx_err_tlp_hdr(23) => pcie_blk_if_rx_err_tlp_hdr(23),
      rx_err_tlp_hdr(22) => pcie_blk_if_rx_err_tlp_hdr(22),
      rx_err_tlp_hdr(21) => pcie_blk_if_rx_err_tlp_hdr(21),
      rx_err_tlp_hdr(20) => pcie_blk_if_rx_err_tlp_hdr(20),
      rx_err_tlp_hdr(19) => pcie_blk_if_rx_err_tlp_hdr(19),
      rx_err_tlp_hdr(18) => pcie_blk_if_rx_err_tlp_hdr(18),
      rx_err_tlp_hdr(17) => pcie_blk_if_rx_err_tlp_hdr(17),
      rx_err_tlp_hdr(16) => pcie_blk_if_rx_err_tlp_hdr(16),
      rx_err_tlp_hdr(15) => pcie_blk_if_rx_err_tlp_hdr(15),
      rx_err_tlp_hdr(14) => pcie_blk_if_rx_err_tlp_hdr(14),
      rx_err_tlp_hdr(13) => pcie_blk_if_rx_err_tlp_hdr(13),
      rx_err_tlp_hdr(12) => pcie_blk_if_rx_err_tlp_hdr(12),
      rx_err_tlp_hdr(11) => pcie_blk_if_rx_err_tlp_hdr(11),
      rx_err_tlp_hdr(10) => pcie_blk_if_rx_err_tlp_hdr(10),
      rx_err_tlp_hdr(9) => pcie_blk_if_rx_err_tlp_hdr(9),
      rx_err_tlp_hdr(8) => pcie_blk_if_rx_err_tlp_hdr(8),
      rx_err_tlp_hdr(7) => pcie_blk_if_rx_err_tlp_hdr(7),
      rx_err_tlp_hdr(6) => pcie_blk_if_rx_err_tlp_hdr(6),
      rx_err_tlp_hdr(5) => pcie_blk_if_rx_err_tlp_hdr(5),
      rx_err_tlp_hdr(4) => pcie_blk_if_rx_err_tlp_hdr(4),
      rx_err_tlp_hdr(3) => pcie_blk_if_rx_err_tlp_hdr(3),
      rx_err_tlp_hdr(2) => pcie_blk_if_rx_err_tlp_hdr(2),
      rx_err_tlp_hdr(1) => pcie_blk_if_rx_err_tlp_hdr(1),
      rx_err_tlp_hdr(0) => pcie_blk_if_rx_err_tlp_hdr(0),
      mac_negotiated_link_width(3) => fe_l0_mac_negotiated_link_width(3),
      mac_negotiated_link_width(2) => fe_l0_mac_negotiated_link_width(2),
      mac_negotiated_link_width(1) => fe_l0_mac_negotiated_link_width(1),
      mac_negotiated_link_width(0) => fe_l0_mac_negotiated_link_width(0),
      mgmt_pso(16) => mgmt_pso(16),
      mgmt_pso(15) => mgmt_pso(15),
      mgmt_pso(14) => mgmt_pso(14),
      mgmt_pso(13) => mgmt_pso(13),
      mgmt_pso(12) => mgmt_pso(12),
      mgmt_pso(11) => mgmt_pso(11),
      mgmt_pso(10) => mgmt_pso(10),
      mgmt_pso(9) => mgmt_pso(9),
      mgmt_pso(8) => mgmt_pso(8),
      mgmt_pso(7) => mgmt_pso(7),
      mgmt_pso(6) => mgmt_pso(6),
      mgmt_pso(5) => mgmt_pso(5),
      mgmt_pso(4) => mgmt_pso(4),
      mgmt_pso(3) => mgmt_pso(3),
      mgmt_pso(2) => mgmt_pso(2),
      mgmt_pso(1) => mgmt_pso(1),
      mgmt_pso(0) => mgmt_pso(0),
      l0_dll_error_vector(6) => fe_l0_dll_error_vector_ext(6),
      l0_dll_error_vector(5) => fe_l0_dll_error_vector_ext(5),
      l0_dll_error_vector(4) => fe_l0_dll_error_vector_ext(4),
      l0_dll_error_vector(3) => fe_l0_dll_error_vector_ext(3),
      l0_dll_error_vector(2) => fe_l0_dll_error_vector_ext(2),
      l0_dll_error_vector(1) => fe_l0_dll_error_vector_ext(1),
      l0_dll_error_vector(0) => fe_l0_dll_error_vector_ext(0),
      completer_id(12) => fe_l0_completer_id(12),
      completer_id(11) => fe_l0_completer_id(11),
      completer_id(10) => fe_l0_completer_id(10),
      completer_id(9) => fe_l0_completer_id(9),
      completer_id(8) => fe_l0_completer_id(8),
      completer_id(7) => fe_l0_completer_id(7),
      completer_id(6) => fe_l0_completer_id(6),
      completer_id(5) => fe_l0_completer_id(5),
      completer_id(4) => fe_l0_completer_id(4),
      completer_id(3) => fe_l0_completer_id(3),
      completer_id(2) => fe_l0_completer_id(2),
      completer_id(1) => fe_l0_completer_id(1),
      completer_id(0) => fe_l0_completer_id(0),
      l0_rx_mac_link_error(1) => fe_l0_rx_mac_link_error_ext(1),
      l0_rx_mac_link_error(0) => fe_l0_rx_mac_link_error_ext(0),
      cfg_dsn(63) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_63_UNCONNECTED,
      cfg_dsn(62) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_62_UNCONNECTED,
      cfg_dsn(61) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_61_UNCONNECTED,
      cfg_dsn(60) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_60_UNCONNECTED,
      cfg_dsn(59) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_59_UNCONNECTED,
      cfg_dsn(58) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_58_UNCONNECTED,
      cfg_dsn(57) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_57_UNCONNECTED,
      cfg_dsn(56) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_56_UNCONNECTED,
      cfg_dsn(55) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_55_UNCONNECTED,
      cfg_dsn(54) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_54_UNCONNECTED,
      cfg_dsn(53) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_53_UNCONNECTED,
      cfg_dsn(52) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_52_UNCONNECTED,
      cfg_dsn(51) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_51_UNCONNECTED,
      cfg_dsn(50) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_50_UNCONNECTED,
      cfg_dsn(49) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_49_UNCONNECTED,
      cfg_dsn(48) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_48_UNCONNECTED,
      cfg_dsn(47) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_47_UNCONNECTED,
      cfg_dsn(46) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_46_UNCONNECTED,
      cfg_dsn(45) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_45_UNCONNECTED,
      cfg_dsn(44) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_44_UNCONNECTED,
      cfg_dsn(43) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_43_UNCONNECTED,
      cfg_dsn(42) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_42_UNCONNECTED,
      cfg_dsn(41) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_41_UNCONNECTED,
      cfg_dsn(40) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_40_UNCONNECTED,
      cfg_dsn(39) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_39_UNCONNECTED,
      cfg_dsn(38) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_38_UNCONNECTED,
      cfg_dsn(37) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_37_UNCONNECTED,
      cfg_dsn(36) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_36_UNCONNECTED,
      cfg_dsn(35) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_35_UNCONNECTED,
      cfg_dsn(34) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_34_UNCONNECTED,
      cfg_dsn(33) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_33_UNCONNECTED,
      cfg_dsn(32) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_32_UNCONNECTED,
      cfg_dsn(31) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_31_UNCONNECTED,
      cfg_dsn(30) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_30_UNCONNECTED,
      cfg_dsn(29) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_29_UNCONNECTED,
      cfg_dsn(28) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_28_UNCONNECTED,
      cfg_dsn(27) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_27_UNCONNECTED,
      cfg_dsn(26) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_26_UNCONNECTED,
      cfg_dsn(25) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_25_UNCONNECTED,
      cfg_dsn(24) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_24_UNCONNECTED,
      cfg_dsn(23) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_23_UNCONNECTED,
      cfg_dsn(22) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_22_UNCONNECTED,
      cfg_dsn(21) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_21_UNCONNECTED,
      cfg_dsn(20) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_20_UNCONNECTED,
      cfg_dsn(19) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_19_UNCONNECTED,
      cfg_dsn(18) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_18_UNCONNECTED,
      cfg_dsn(17) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_17_UNCONNECTED,
      cfg_dsn(16) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_16_UNCONNECTED,
      cfg_dsn(15) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_15_UNCONNECTED,
      cfg_dsn(14) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_14_UNCONNECTED,
      cfg_dsn(13) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_13_UNCONNECTED,
      cfg_dsn(12) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_12_UNCONNECTED,
      cfg_dsn(11) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_11_UNCONNECTED,
      cfg_dsn(10) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_10_UNCONNECTED,
      cfg_dsn(9) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_9_UNCONNECTED,
      cfg_dsn(8) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_8_UNCONNECTED,
      cfg_dsn(7) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_7_UNCONNECTED,
      cfg_dsn(6) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_6_UNCONNECTED,
      cfg_dsn(5) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_5_UNCONNECTED,
      cfg_dsn(4) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_4_UNCONNECTED,
      cfg_dsn(3) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_3_UNCONNECTED,
      cfg_dsn(2) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_2_UNCONNECTED,
      cfg_dsn(1) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_1_UNCONNECTED,
      cfg_dsn(0) => NLW_pcie_blk_if_cf_bridge_cfg_dsn_0_UNCONNECTED,
      max_payload_size(2) => NLW_pcie_blk_if_cf_bridge_max_payload_size_2_UNCONNECTED,
      max_payload_size(1) => NLW_pcie_blk_if_cf_bridge_max_payload_size_1_UNCONNECTED,
      max_payload_size(0) => NLW_pcie_blk_if_cf_bridge_max_payload_size_0_UNCONNECTED,
      cfg_err_tlp_cpl_header(47) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_47_UNCONNECTED,
      cfg_err_tlp_cpl_header(46) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_46_UNCONNECTED,
      cfg_err_tlp_cpl_header(45) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_45_UNCONNECTED,
      cfg_err_tlp_cpl_header(44) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_44_UNCONNECTED,
      cfg_err_tlp_cpl_header(43) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_43_UNCONNECTED,
      cfg_err_tlp_cpl_header(42) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_42_UNCONNECTED,
      cfg_err_tlp_cpl_header(41) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_41_UNCONNECTED,
      cfg_err_tlp_cpl_header(40) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_40_UNCONNECTED,
      cfg_err_tlp_cpl_header(39) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_39_UNCONNECTED,
      cfg_err_tlp_cpl_header(38) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_38_UNCONNECTED,
      cfg_err_tlp_cpl_header(37) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_37_UNCONNECTED,
      cfg_err_tlp_cpl_header(36) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_36_UNCONNECTED,
      cfg_err_tlp_cpl_header(35) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_35_UNCONNECTED,
      cfg_err_tlp_cpl_header(34) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_34_UNCONNECTED,
      cfg_err_tlp_cpl_header(33) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_33_UNCONNECTED,
      cfg_err_tlp_cpl_header(32) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_32_UNCONNECTED,
      cfg_err_tlp_cpl_header(31) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_31_UNCONNECTED,
      cfg_err_tlp_cpl_header(30) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_30_UNCONNECTED,
      cfg_err_tlp_cpl_header(29) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_29_UNCONNECTED,
      cfg_err_tlp_cpl_header(28) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_28_UNCONNECTED,
      cfg_err_tlp_cpl_header(27) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_27_UNCONNECTED,
      cfg_err_tlp_cpl_header(26) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_26_UNCONNECTED,
      cfg_err_tlp_cpl_header(25) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_25_UNCONNECTED,
      cfg_err_tlp_cpl_header(24) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_24_UNCONNECTED,
      cfg_err_tlp_cpl_header(23) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_23_UNCONNECTED,
      cfg_err_tlp_cpl_header(22) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_22_UNCONNECTED,
      cfg_err_tlp_cpl_header(21) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_21_UNCONNECTED,
      cfg_err_tlp_cpl_header(20) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_20_UNCONNECTED,
      cfg_err_tlp_cpl_header(19) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_19_UNCONNECTED,
      cfg_err_tlp_cpl_header(18) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_18_UNCONNECTED,
      cfg_err_tlp_cpl_header(17) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_17_UNCONNECTED,
      cfg_err_tlp_cpl_header(16) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_16_UNCONNECTED,
      cfg_err_tlp_cpl_header(15) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_15_UNCONNECTED,
      cfg_err_tlp_cpl_header(14) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_14_UNCONNECTED,
      cfg_err_tlp_cpl_header(13) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_13_UNCONNECTED,
      cfg_err_tlp_cpl_header(12) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_12_UNCONNECTED,
      cfg_err_tlp_cpl_header(11) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_11_UNCONNECTED,
      cfg_err_tlp_cpl_header(10) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_10_UNCONNECTED,
      cfg_err_tlp_cpl_header(9) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_9_UNCONNECTED,
      cfg_err_tlp_cpl_header(8) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_8_UNCONNECTED,
      cfg_err_tlp_cpl_header(7) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_7_UNCONNECTED,
      cfg_err_tlp_cpl_header(6) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_6_UNCONNECTED,
      cfg_err_tlp_cpl_header(5) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_5_UNCONNECTED,
      cfg_err_tlp_cpl_header(4) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_4_UNCONNECTED,
      cfg_err_tlp_cpl_header(3) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_3_UNCONNECTED,
      cfg_err_tlp_cpl_header(2) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_2_UNCONNECTED,
      cfg_err_tlp_cpl_header(1) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_1_UNCONNECTED,
      cfg_err_tlp_cpl_header(0) => NLW_pcie_blk_if_cf_bridge_cfg_err_tlp_cpl_header_0_UNCONNECTED,
      cfg_dwaddr(11) => fe_compliance_avoid,
      cfg_dwaddr(10) => fe_compliance_avoid,
      cfg_dwaddr(9) => cfg_dwaddr(9),
      cfg_dwaddr(8) => cfg_dwaddr(8),
      cfg_dwaddr(7) => cfg_dwaddr(7),
      cfg_dwaddr(6) => cfg_dwaddr(6),
      cfg_dwaddr(5) => cfg_dwaddr(5),
      cfg_dwaddr(4) => cfg_dwaddr(4),
      cfg_dwaddr(3) => cfg_dwaddr(3),
      cfg_dwaddr(2) => cfg_dwaddr(2),
      cfg_dwaddr(1) => cfg_dwaddr(1),
      cfg_dwaddr(0) => cfg_dwaddr(0),
      llk_rx_data_d(63) => pcie_blk_if_llk_rx_data_d(63),
      llk_rx_data_d(62) => pcie_blk_if_llk_rx_data_d(62),
      llk_rx_data_d(61) => pcie_blk_if_llk_rx_data_d(61),
      llk_rx_data_d(60) => pcie_blk_if_llk_rx_data_d(60),
      llk_rx_data_d(59) => pcie_blk_if_llk_rx_data_d(59),
      llk_rx_data_d(58) => pcie_blk_if_llk_rx_data_d(58),
      llk_rx_data_d(57) => pcie_blk_if_llk_rx_data_d(57),
      llk_rx_data_d(56) => pcie_blk_if_llk_rx_data_d(56),
      llk_rx_data_d(55) => pcie_blk_if_llk_rx_data_d(55),
      llk_rx_data_d(54) => pcie_blk_if_llk_rx_data_d(54),
      llk_rx_data_d(53) => pcie_blk_if_llk_rx_data_d(53),
      llk_rx_data_d(52) => pcie_blk_if_llk_rx_data_d(52),
      llk_rx_data_d(51) => pcie_blk_if_llk_rx_data_d(51),
      llk_rx_data_d(50) => pcie_blk_if_llk_rx_data_d(50),
      llk_rx_data_d(49) => pcie_blk_if_llk_rx_data_d(49),
      llk_rx_data_d(48) => pcie_blk_if_llk_rx_data_d(48),
      llk_rx_data_d(47) => pcie_blk_if_llk_rx_data_d(47),
      llk_rx_data_d(46) => pcie_blk_if_llk_rx_data_d(46),
      llk_rx_data_d(45) => pcie_blk_if_llk_rx_data_d(45),
      llk_rx_data_d(44) => pcie_blk_if_llk_rx_data_d(44),
      llk_rx_data_d(43) => pcie_blk_if_llk_rx_data_d(43),
      llk_rx_data_d(42) => pcie_blk_if_llk_rx_data_d(42),
      llk_rx_data_d(41) => pcie_blk_if_llk_rx_data_d(41),
      llk_rx_data_d(40) => pcie_blk_if_llk_rx_data_d(40),
      llk_rx_data_d(39) => pcie_blk_if_llk_rx_data_d(39),
      llk_rx_data_d(38) => pcie_blk_if_llk_rx_data_d(38),
      llk_rx_data_d(37) => pcie_blk_if_llk_rx_data_d(37),
      llk_rx_data_d(36) => pcie_blk_if_llk_rx_data_d(36),
      llk_rx_data_d(35) => pcie_blk_if_llk_rx_data_d(35),
      llk_rx_data_d(34) => pcie_blk_if_llk_rx_data_d(34),
      llk_rx_data_d(33) => pcie_blk_if_llk_rx_data_d(33),
      llk_rx_data_d(32) => pcie_blk_if_llk_rx_data_d(32),
      llk_rx_data_d(31) => pcie_blk_if_llk_rx_data_d(31),
      llk_rx_data_d(30) => pcie_blk_if_llk_rx_data_d(30),
      llk_rx_data_d(29) => pcie_blk_if_llk_rx_data_d(29),
      llk_rx_data_d(28) => pcie_blk_if_llk_rx_data_d(28),
      llk_rx_data_d(27) => pcie_blk_if_llk_rx_data_d(27),
      llk_rx_data_d(26) => pcie_blk_if_llk_rx_data_d(26),
      llk_rx_data_d(25) => pcie_blk_if_llk_rx_data_d(25),
      llk_rx_data_d(24) => pcie_blk_if_llk_rx_data_d(24),
      llk_rx_data_d(23) => pcie_blk_if_llk_rx_data_d(23),
      llk_rx_data_d(22) => pcie_blk_if_llk_rx_data_d(22),
      llk_rx_data_d(21) => pcie_blk_if_llk_rx_data_d(21),
      llk_rx_data_d(20) => pcie_blk_if_llk_rx_data_d(20),
      llk_rx_data_d(19) => pcie_blk_if_llk_rx_data_d(19),
      llk_rx_data_d(18) => pcie_blk_if_llk_rx_data_d(18),
      llk_rx_data_d(17) => pcie_blk_if_llk_rx_data_d(17),
      llk_rx_data_d(16) => pcie_blk_if_llk_rx_data_d(16),
      llk_rx_data_d(15) => pcie_blk_if_llk_rx_data_d(15),
      llk_rx_data_d(14) => pcie_blk_if_llk_rx_data_d(14),
      llk_rx_data_d(13) => pcie_blk_if_llk_rx_data_d(13),
      llk_rx_data_d(12) => pcie_blk_if_llk_rx_data_d(12),
      llk_rx_data_d(11) => pcie_blk_if_llk_rx_data_d(11),
      llk_rx_data_d(10) => pcie_blk_if_llk_rx_data_d(10),
      llk_rx_data_d(9) => pcie_blk_if_llk_rx_data_d(9),
      llk_rx_data_d(8) => pcie_blk_if_llk_rx_data_d(8),
      llk_rx_data_d(7) => pcie_blk_if_llk_rx_data_d(7),
      llk_rx_data_d(6) => pcie_blk_if_llk_rx_data_d(6),
      llk_rx_data_d(5) => pcie_blk_if_llk_rx_data_d(5),
      llk_rx_data_d(4) => pcie_blk_if_llk_rx_data_d(4),
      llk_rx_data_d(3) => pcie_blk_if_llk_rx_data_d(3),
      llk_rx_data_d(2) => pcie_blk_if_llk_rx_data_d(2),
      llk_rx_data_d(1) => pcie_blk_if_llk_rx_data_d(1),
      llk_rx_data_d(0) => pcie_blk_if_llk_rx_data_d(0),
      mgmt_rdata(31) => mgmt_rdata(31),
      mgmt_rdata(30) => mgmt_rdata(30),
      mgmt_rdata(29) => mgmt_rdata(29),
      mgmt_rdata(28) => mgmt_rdata(28),
      mgmt_rdata(27) => mgmt_rdata(27),
      mgmt_rdata(26) => mgmt_rdata(26),
      mgmt_rdata(25) => mgmt_rdata(25),
      mgmt_rdata(24) => mgmt_rdata(24),
      mgmt_rdata(23) => mgmt_rdata(23),
      mgmt_rdata(22) => mgmt_rdata(22),
      mgmt_rdata(21) => mgmt_rdata(21),
      mgmt_rdata(20) => mgmt_rdata(20),
      mgmt_rdata(19) => mgmt_rdata(19),
      mgmt_rdata(18) => mgmt_rdata(18),
      mgmt_rdata(17) => mgmt_rdata(17),
      mgmt_rdata(16) => mgmt_rdata(16),
      mgmt_rdata(15) => mgmt_rdata(15),
      mgmt_rdata(14) => mgmt_rdata(14),
      mgmt_rdata(13) => mgmt_rdata(13),
      mgmt_rdata(12) => mgmt_rdata(12),
      mgmt_rdata(11) => mgmt_rdata(11),
      mgmt_rdata(10) => mgmt_rdata(10),
      mgmt_rdata(9) => mgmt_rdata(9),
      mgmt_rdata(8) => mgmt_rdata(8),
      mgmt_rdata(7) => mgmt_rdata(7),
      mgmt_rdata(6) => mgmt_rdata(6),
      mgmt_rdata(5) => mgmt_rdata(5),
      mgmt_rdata(4) => mgmt_rdata(4),
      mgmt_rdata(3) => mgmt_rdata(3),
      mgmt_rdata(2) => mgmt_rdata(2),
      mgmt_rdata(1) => mgmt_rdata(1),
      mgmt_rdata(0) => mgmt_rdata(0),
      max_read_request_size(2) => NLW_pcie_blk_if_cf_bridge_max_read_request_size_2_UNCONNECTED,
      max_read_request_size(1) => NLW_pcie_blk_if_cf_bridge_max_read_request_size_1_UNCONNECTED,
      max_read_request_size(0) => NLW_pcie_blk_if_cf_bridge_max_read_request_size_0_UNCONNECTED,
      cfg_di(31) => NLW_pcie_blk_if_cf_bridge_cfg_di_31_UNCONNECTED,
      cfg_di(30) => NLW_pcie_blk_if_cf_bridge_cfg_di_30_UNCONNECTED,
      cfg_di(29) => NLW_pcie_blk_if_cf_bridge_cfg_di_29_UNCONNECTED,
      cfg_di(28) => NLW_pcie_blk_if_cf_bridge_cfg_di_28_UNCONNECTED,
      cfg_di(27) => NLW_pcie_blk_if_cf_bridge_cfg_di_27_UNCONNECTED,
      cfg_di(26) => NLW_pcie_blk_if_cf_bridge_cfg_di_26_UNCONNECTED,
      cfg_di(25) => NLW_pcie_blk_if_cf_bridge_cfg_di_25_UNCONNECTED,
      cfg_di(24) => NLW_pcie_blk_if_cf_bridge_cfg_di_24_UNCONNECTED,
      cfg_di(23) => NLW_pcie_blk_if_cf_bridge_cfg_di_23_UNCONNECTED,
      cfg_di(22) => NLW_pcie_blk_if_cf_bridge_cfg_di_22_UNCONNECTED,
      cfg_di(21) => NLW_pcie_blk_if_cf_bridge_cfg_di_21_UNCONNECTED,
      cfg_di(20) => NLW_pcie_blk_if_cf_bridge_cfg_di_20_UNCONNECTED,
      cfg_di(19) => NLW_pcie_blk_if_cf_bridge_cfg_di_19_UNCONNECTED,
      cfg_di(18) => NLW_pcie_blk_if_cf_bridge_cfg_di_18_UNCONNECTED,
      cfg_di(17) => NLW_pcie_blk_if_cf_bridge_cfg_di_17_UNCONNECTED,
      cfg_di(16) => NLW_pcie_blk_if_cf_bridge_cfg_di_16_UNCONNECTED,
      cfg_di(15) => NLW_pcie_blk_if_cf_bridge_cfg_di_15_UNCONNECTED,
      cfg_di(14) => NLW_pcie_blk_if_cf_bridge_cfg_di_14_UNCONNECTED,
      cfg_di(13) => NLW_pcie_blk_if_cf_bridge_cfg_di_13_UNCONNECTED,
      cfg_di(12) => NLW_pcie_blk_if_cf_bridge_cfg_di_12_UNCONNECTED,
      cfg_di(11) => NLW_pcie_blk_if_cf_bridge_cfg_di_11_UNCONNECTED,
      cfg_di(10) => NLW_pcie_blk_if_cf_bridge_cfg_di_10_UNCONNECTED,
      cfg_di(9) => NLW_pcie_blk_if_cf_bridge_cfg_di_9_UNCONNECTED,
      cfg_di(8) => NLW_pcie_blk_if_cf_bridge_cfg_di_8_UNCONNECTED,
      cfg_di(7) => NLW_pcie_blk_if_cf_bridge_cfg_di_7_UNCONNECTED,
      cfg_di(6) => NLW_pcie_blk_if_cf_bridge_cfg_di_6_UNCONNECTED,
      cfg_di(5) => NLW_pcie_blk_if_cf_bridge_cfg_di_5_UNCONNECTED,
      cfg_di(4) => NLW_pcie_blk_if_cf_bridge_cfg_di_4_UNCONNECTED,
      cfg_di(3) => NLW_pcie_blk_if_cf_bridge_cfg_di_3_UNCONNECTED,
      cfg_di(2) => NLW_pcie_blk_if_cf_bridge_cfg_di_2_UNCONNECTED,
      cfg_di(1) => NLW_pcie_blk_if_cf_bridge_cfg_di_1_UNCONNECTED,
      cfg_di(0) => NLW_pcie_blk_if_cf_bridge_cfg_di_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_pcie_x8 is
  port (
    trn_rsrc_rdy_n : out STD_LOGIC; 
    trn_terrfwd_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
    trn_rerrfwd_n : out STD_LOGIC; 
    cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
    trn_rnp_ok_n : in STD_LOGIC := 'X'; 
    cfg_to_turnoff_n : out STD_LOGIC; 
    trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
    refclkout : out STD_LOGIC; 
    cfg_rd_en_n : in STD_LOGIC := 'X'; 
    cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
    trn_tdst_rdy_n : out STD_LOGIC; 
    trn_rsof_n : out STD_LOGIC; 
    cfg_rd_wr_done_n : out STD_LOGIC; 
    trn_teof_n : in STD_LOGIC := 'X'; 
    trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
    trn_clk : out STD_LOGIC; 
    cfg_err_locked_n : in STD_LOGIC := 'X'; 
    cfg_trn_pending_n : in STD_LOGIC := 'X'; 
    trn_reset_n : out STD_LOGIC; 
    trn_rsrc_dsc_n : out STD_LOGIC; 
    fast_train_simulation_only : in STD_LOGIC := 'X'; 
    cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_msienable : out STD_LOGIC; 
    trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
    cfg_err_ur_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_n : in STD_LOGIC := 'X'; 
    trn_tsof_n : in STD_LOGIC := 'X'; 
    cfg_wr_en_n : in STD_LOGIC := 'X'; 
    cfg_pm_wake_n : in STD_LOGIC := 'X'; 
    cfg_interrupt_rdy_n : out STD_LOGIC; 
    trn_tdst_dsc_n : out STD_LOGIC; 
    cfg_err_posted_n : in STD_LOGIC := 'X'; 
    cfg_err_cpl_rdy_n : out STD_LOGIC; 
    sys_reset_n : in STD_LOGIC := 'X'; 
    trn_reof_n : out STD_LOGIC; 
    cfg_err_cor_n : in STD_LOGIC := 'X'; 
    sys_clk : in STD_LOGIC := 'X'; 
    trn_lnk_up_n : out STD_LOGIC; 
    cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
    cfg_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end ctrl_pcie_x8;

architecture STRUCTURE of ctrl_pcie_x8 is
  component pcie_ep_top
    port (
      trn_rsrc_rdy_n : out STD_LOGIC; 
      trn_terrfwd_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      trn_rerrfwd_n : out STD_LOGIC; 
      cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
      cfg_to_turnoff_n : out STD_LOGIC; 
      trn_rnp_ok_n : in STD_LOGIC := 'X'; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      cfg_rd_en_n : in STD_LOGIC := 'X'; 
      refclkout : out STD_LOGIC; 
      cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      trn_rsof_n : out STD_LOGIC; 
      cfg_rd_wr_done_n : out STD_LOGIC; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      trn_clk : out STD_LOGIC; 
      cfg_err_locked_n : in STD_LOGIC := 'X'; 
      cfg_trn_pending_n : in STD_LOGIC := 'X'; 
      trn_reset_n : out STD_LOGIC; 
      trn_rsrc_dsc_n : out STD_LOGIC; 
      fast_train_simulation_only : in STD_LOGIC := 'X'; 
      cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_msienable : out STD_LOGIC; 
      trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      cfg_err_ur_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_n : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      cfg_wr_en_n : in STD_LOGIC := 'X'; 
      cfg_pm_wake_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_rdy_n : out STD_LOGIC; 
      cfg_turnoff_ok_n : in STD_LOGIC := 'X'; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      cfg_err_posted_n : in STD_LOGIC := 'X'; 
      gt_dclk : in STD_LOGIC := 'X'; 
      cfg_err_cpl_rdy_n : out STD_LOGIC; 
      sys_reset_n : in STD_LOGIC := 'X'; 
      cfg_err_cor_n : in STD_LOGIC := 'X'; 
      trn_reof_n : out STD_LOGIC; 
      sys_clk : in STD_LOGIC := 'X'; 
      cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
      trn_lnk_up_n : out STD_LOGIC; 
      cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
      cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      trn_rfc_cplh_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      trn_rfc_cpld_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      gt_drdy : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_do : out STD_LOGIC_VECTOR ( 127 downto 0 ); 
      trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      gt_den : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_dwen : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      gt_daddr : in STD_LOGIC_VECTOR ( 55 downto 0 ); 
      cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      gt_txbuffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      cfg_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      gt_txbuffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txdiffctrl_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_txpreemphesis_1 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      gt_di : in STD_LOGIC_VECTOR ( 127 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_cpl_abort_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_cpl_unexpect_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_rd_en_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_ecrc_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_locked_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_trn_pending_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_cpl_timeout_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_ur_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_wr_en_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_pm_wake_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_turnoff_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_err_cor_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cplh_av_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_trn_rfc_cpld_av_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_drdy_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_127_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_126_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_125_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_124_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_123_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_122_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_121_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_120_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_119_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_118_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_117_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_116_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_115_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_114_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_113_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_112_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_111_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_110_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_109_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_108_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_107_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_106_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_105_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_104_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_103_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_102_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_101_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_100_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_99_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_98_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_97_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_96_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_95_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_94_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_93_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_92_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_91_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_90_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_89_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_88_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_87_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_86_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_85_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_84_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_83_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_82_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_81_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_80_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_79_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_78_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_77_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_76_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_75_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_74_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_73_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_72_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_71_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_70_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_69_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_68_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_67_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_66_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_65_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_64_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_do_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_byte_en_n_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_byte_en_n_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_byte_en_n_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_cfg_byte_en_n_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txbuffctrl_0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txbuffctrl_1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txdiffctrl_0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txdiffctrl_1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_pcie_ep0_gt_txpreemphesis_1_0_UNCONNECTED : STD_LOGIC; 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  pcie_ep0 : pcie_ep_top
    port map (
      trn_rsrc_rdy_n => trn_rsrc_rdy_n,
      trn_terrfwd_n => trn_terrfwd_n,
      cfg_err_cpl_abort_n => NLW_pcie_ep0_cfg_err_cpl_abort_n_UNCONNECTED,
      trn_rerrfwd_n => trn_rerrfwd_n,
      cfg_err_cpl_unexpect_n => NLW_pcie_ep0_cfg_err_cpl_unexpect_n_UNCONNECTED,
      cfg_to_turnoff_n => cfg_to_turnoff_n,
      trn_rnp_ok_n => NLW_pcie_ep0_trn_rnp_ok_n_UNCONNECTED,
      trn_tsrc_dsc_n => trn_tsrc_dsc_n,
      cfg_rd_en_n => NLW_pcie_ep0_cfg_rd_en_n_UNCONNECTED,
      refclkout => refclkout,
      cfg_err_ecrc_n => NLW_pcie_ep0_cfg_err_ecrc_n_UNCONNECTED,
      trn_tdst_rdy_n => trn_tdst_rdy_n,
      trn_rsof_n => trn_rsof_n,
      cfg_rd_wr_done_n => cfg_rd_wr_done_n,
      trn_teof_n => trn_teof_n,
      trn_rcpl_streaming_n => trn_rcpl_streaming_n,
      trn_clk => trn_clk,
      cfg_err_locked_n => NLW_pcie_ep0_cfg_err_locked_n_UNCONNECTED,
      cfg_trn_pending_n => NLW_pcie_ep0_cfg_trn_pending_n_UNCONNECTED,
      trn_reset_n => trn_reset_n,
      trn_rsrc_dsc_n => trn_rsrc_dsc_n,
      fast_train_simulation_only => fast_train_simulation_only,
      cfg_err_cpl_timeout_n => NLW_pcie_ep0_cfg_err_cpl_timeout_n_UNCONNECTED,
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      trn_rdst_rdy_n => trn_rdst_rdy_n,
      trn_tsrc_rdy_n => trn_tsrc_rdy_n,
      cfg_err_ur_n => NLW_pcie_ep0_cfg_err_ur_n_UNCONNECTED,
      cfg_interrupt_n => cfg_interrupt_n,
      trn_tsof_n => trn_tsof_n,
      cfg_wr_en_n => NLW_pcie_ep0_cfg_wr_en_n_UNCONNECTED,
      cfg_pm_wake_n => NLW_pcie_ep0_cfg_pm_wake_n_UNCONNECTED,
      cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
      cfg_turnoff_ok_n => NLW_pcie_ep0_cfg_turnoff_ok_n_UNCONNECTED,
      trn_tdst_dsc_n => trn_tdst_dsc_n,
      cfg_err_posted_n => N0,
      gt_dclk => N0,
      cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
      sys_reset_n => sys_reset_n,
      cfg_err_cor_n => NLW_pcie_ep0_cfg_err_cor_n_UNCONNECTED,
      trn_reof_n => trn_reof_n,
      sys_clk => sys_clk,
      cfg_interrupt_assert_n => cfg_interrupt_assert_n,
      trn_lnk_up_n => trn_lnk_up_n,
      cfg_device_number(4) => cfg_device_number(4),
      cfg_device_number(3) => cfg_device_number(3),
      cfg_device_number(2) => cfg_device_number(2),
      cfg_device_number(1) => cfg_device_number(1),
      cfg_device_number(0) => cfg_device_number(0),
      cfg_dstatus(15) => cfg_dstatus(15),
      cfg_dstatus(14) => cfg_dstatus(14),
      cfg_dstatus(13) => cfg_dstatus(13),
      cfg_dstatus(12) => cfg_dstatus(12),
      cfg_dstatus(11) => cfg_dstatus(11),
      cfg_dstatus(10) => cfg_dstatus(10),
      cfg_dstatus(9) => cfg_dstatus(9),
      cfg_dstatus(8) => cfg_dstatus(8),
      cfg_dstatus(7) => cfg_dstatus(7),
      cfg_dstatus(6) => cfg_dstatus(6),
      cfg_dstatus(5) => cfg_dstatus(5),
      cfg_dstatus(4) => cfg_dstatus(4),
      cfg_dstatus(3) => cfg_dstatus(3),
      cfg_dstatus(2) => cfg_dstatus(2),
      cfg_dstatus(1) => cfg_dstatus(1),
      cfg_dstatus(0) => cfg_dstatus(0),
      cfg_lcommand(15) => cfg_lcommand(15),
      cfg_lcommand(14) => cfg_lcommand(14),
      cfg_lcommand(13) => cfg_lcommand(13),
      cfg_lcommand(12) => cfg_lcommand(12),
      cfg_lcommand(11) => cfg_lcommand(11),
      cfg_lcommand(10) => cfg_lcommand(10),
      cfg_lcommand(9) => cfg_lcommand(9),
      cfg_lcommand(8) => cfg_lcommand(8),
      cfg_lcommand(7) => cfg_lcommand(7),
      cfg_lcommand(6) => cfg_lcommand(6),
      cfg_lcommand(5) => cfg_lcommand(5),
      cfg_lcommand(4) => cfg_lcommand(4),
      cfg_lcommand(3) => cfg_lcommand(3),
      cfg_lcommand(2) => cfg_lcommand(2),
      cfg_lcommand(1) => cfg_lcommand(1),
      cfg_lcommand(0) => cfg_lcommand(0),
      pci_exp_txn(7) => pci_exp_txn(7),
      pci_exp_txn(6) => pci_exp_txn(6),
      pci_exp_txn(5) => pci_exp_txn(5),
      pci_exp_txn(4) => pci_exp_txn(4),
      pci_exp_txn(3) => pci_exp_txn(3),
      pci_exp_txn(2) => pci_exp_txn(2),
      pci_exp_txn(1) => pci_exp_txn(1),
      pci_exp_txn(0) => pci_exp_txn(0),
      pci_exp_txp(7) => pci_exp_txp(7),
      pci_exp_txp(6) => pci_exp_txp(6),
      pci_exp_txp(5) => pci_exp_txp(5),
      pci_exp_txp(4) => pci_exp_txp(4),
      pci_exp_txp(3) => pci_exp_txp(3),
      pci_exp_txp(2) => pci_exp_txp(2),
      pci_exp_txp(1) => pci_exp_txp(1),
      pci_exp_txp(0) => pci_exp_txp(0),
      cfg_status(15) => cfg_status(15),
      cfg_status(14) => cfg_status(14),
      cfg_status(13) => cfg_status(13),
      cfg_status(12) => cfg_status(12),
      cfg_status(11) => cfg_status(11),
      cfg_status(10) => cfg_status(10),
      cfg_status(9) => cfg_status(9),
      cfg_status(8) => cfg_status(8),
      cfg_status(7) => cfg_status(7),
      cfg_status(6) => cfg_status(6),
      cfg_status(5) => cfg_status(5),
      cfg_status(4) => cfg_status(4),
      cfg_status(3) => cfg_status(3),
      cfg_status(2) => cfg_status(2),
      cfg_status(1) => cfg_status(1),
      cfg_status(0) => cfg_status(0),
      trn_rfc_cplh_av(7) => NLW_pcie_ep0_trn_rfc_cplh_av_7_UNCONNECTED,
      trn_rfc_cplh_av(6) => NLW_pcie_ep0_trn_rfc_cplh_av_6_UNCONNECTED,
      trn_rfc_cplh_av(5) => NLW_pcie_ep0_trn_rfc_cplh_av_5_UNCONNECTED,
      trn_rfc_cplh_av(4) => NLW_pcie_ep0_trn_rfc_cplh_av_4_UNCONNECTED,
      trn_rfc_cplh_av(3) => NLW_pcie_ep0_trn_rfc_cplh_av_3_UNCONNECTED,
      trn_rfc_cplh_av(2) => NLW_pcie_ep0_trn_rfc_cplh_av_2_UNCONNECTED,
      trn_rfc_cplh_av(1) => NLW_pcie_ep0_trn_rfc_cplh_av_1_UNCONNECTED,
      trn_rfc_cplh_av(0) => NLW_pcie_ep0_trn_rfc_cplh_av_0_UNCONNECTED,
      cfg_interrupt_do(7) => cfg_interrupt_do(7),
      cfg_interrupt_do(6) => cfg_interrupt_do(6),
      cfg_interrupt_do(5) => cfg_interrupt_do(5),
      cfg_interrupt_do(4) => cfg_interrupt_do(4),
      cfg_interrupt_do(3) => cfg_interrupt_do(3),
      cfg_interrupt_do(2) => cfg_interrupt_do(2),
      cfg_interrupt_do(1) => cfg_interrupt_do(1),
      cfg_interrupt_do(0) => cfg_interrupt_do(0),
      cfg_interrupt_mmenable(2) => cfg_interrupt_mmenable(2),
      cfg_interrupt_mmenable(1) => cfg_interrupt_mmenable(1),
      cfg_interrupt_mmenable(0) => cfg_interrupt_mmenable(0),
      trn_rfc_nph_av(7) => trn_rfc_nph_av(7),
      trn_rfc_nph_av(6) => trn_rfc_nph_av(6),
      trn_rfc_nph_av(5) => trn_rfc_nph_av(5),
      trn_rfc_nph_av(4) => trn_rfc_nph_av(4),
      trn_rfc_nph_av(3) => trn_rfc_nph_av(3),
      trn_rfc_nph_av(2) => trn_rfc_nph_av(2),
      trn_rfc_nph_av(1) => trn_rfc_nph_av(1),
      trn_rfc_nph_av(0) => trn_rfc_nph_av(0),
      trn_rfc_ph_av(7) => trn_rfc_ph_av(7),
      trn_rfc_ph_av(6) => trn_rfc_ph_av(6),
      trn_rfc_ph_av(5) => trn_rfc_ph_av(5),
      trn_rfc_ph_av(4) => trn_rfc_ph_av(4),
      trn_rfc_ph_av(3) => trn_rfc_ph_av(3),
      trn_rfc_ph_av(2) => trn_rfc_ph_av(2),
      trn_rfc_ph_av(1) => trn_rfc_ph_av(1),
      trn_rfc_ph_av(0) => trn_rfc_ph_av(0),
      trn_rrem_n(7) => trn_rrem_n(7),
      trn_rrem_n(6) => trn_rrem_n(6),
      trn_rrem_n(5) => trn_rrem_n(5),
      trn_rrem_n(4) => trn_rrem_n(4),
      trn_rrem_n(3) => trn_rrem_n(3),
      trn_rrem_n(2) => trn_rrem_n(2),
      trn_rrem_n(1) => trn_rrem_n(1),
      trn_rrem_n(0) => trn_rrem_n(0),
      cfg_bus_number(7) => cfg_bus_number(7),
      cfg_bus_number(6) => cfg_bus_number(6),
      cfg_bus_number(5) => cfg_bus_number(5),
      cfg_bus_number(4) => cfg_bus_number(4),
      cfg_bus_number(3) => cfg_bus_number(3),
      cfg_bus_number(2) => cfg_bus_number(2),
      cfg_bus_number(1) => cfg_bus_number(1),
      cfg_bus_number(0) => cfg_bus_number(0),
      trn_tbuf_av(3) => trn_tbuf_av(3),
      trn_tbuf_av(2) => trn_tbuf_av(2),
      trn_tbuf_av(1) => trn_tbuf_av(1),
      trn_tbuf_av(0) => trn_tbuf_av(0),
      trn_rfc_cpld_av(11) => NLW_pcie_ep0_trn_rfc_cpld_av_11_UNCONNECTED,
      trn_rfc_cpld_av(10) => NLW_pcie_ep0_trn_rfc_cpld_av_10_UNCONNECTED,
      trn_rfc_cpld_av(9) => NLW_pcie_ep0_trn_rfc_cpld_av_9_UNCONNECTED,
      trn_rfc_cpld_av(8) => NLW_pcie_ep0_trn_rfc_cpld_av_8_UNCONNECTED,
      trn_rfc_cpld_av(7) => NLW_pcie_ep0_trn_rfc_cpld_av_7_UNCONNECTED,
      trn_rfc_cpld_av(6) => NLW_pcie_ep0_trn_rfc_cpld_av_6_UNCONNECTED,
      trn_rfc_cpld_av(5) => NLW_pcie_ep0_trn_rfc_cpld_av_5_UNCONNECTED,
      trn_rfc_cpld_av(4) => NLW_pcie_ep0_trn_rfc_cpld_av_4_UNCONNECTED,
      trn_rfc_cpld_av(3) => NLW_pcie_ep0_trn_rfc_cpld_av_3_UNCONNECTED,
      trn_rfc_cpld_av(2) => NLW_pcie_ep0_trn_rfc_cpld_av_2_UNCONNECTED,
      trn_rfc_cpld_av(1) => NLW_pcie_ep0_trn_rfc_cpld_av_1_UNCONNECTED,
      trn_rfc_cpld_av(0) => NLW_pcie_ep0_trn_rfc_cpld_av_0_UNCONNECTED,
      cfg_command(15) => cfg_command(15),
      cfg_command(14) => cfg_command(14),
      cfg_command(13) => cfg_command(13),
      cfg_command(12) => cfg_command(12),
      cfg_command(11) => cfg_command(11),
      cfg_command(10) => cfg_command(10),
      cfg_command(9) => cfg_command(9),
      cfg_command(8) => cfg_command(8),
      cfg_command(7) => cfg_command(7),
      cfg_command(6) => cfg_command(6),
      cfg_command(5) => cfg_command(5),
      cfg_command(4) => cfg_command(4),
      cfg_command(3) => cfg_command(3),
      cfg_command(2) => cfg_command(2),
      cfg_command(1) => cfg_command(1),
      cfg_command(0) => cfg_command(0),
      cfg_lstatus(15) => cfg_lstatus(15),
      cfg_lstatus(14) => cfg_lstatus(14),
      cfg_lstatus(13) => cfg_lstatus(13),
      cfg_lstatus(12) => cfg_lstatus(12),
      cfg_lstatus(11) => cfg_lstatus(11),
      cfg_lstatus(10) => cfg_lstatus(10),
      cfg_lstatus(9) => cfg_lstatus(9),
      cfg_lstatus(8) => cfg_lstatus(8),
      cfg_lstatus(7) => cfg_lstatus(7),
      cfg_lstatus(6) => cfg_lstatus(6),
      cfg_lstatus(5) => cfg_lstatus(5),
      cfg_lstatus(4) => cfg_lstatus(4),
      cfg_lstatus(3) => cfg_lstatus(3),
      cfg_lstatus(2) => cfg_lstatus(2),
      cfg_lstatus(1) => cfg_lstatus(1),
      cfg_lstatus(0) => cfg_lstatus(0),
      gt_drdy(7) => NLW_pcie_ep0_gt_drdy_7_UNCONNECTED,
      gt_drdy(6) => NLW_pcie_ep0_gt_drdy_6_UNCONNECTED,
      gt_drdy(5) => NLW_pcie_ep0_gt_drdy_5_UNCONNECTED,
      gt_drdy(4) => NLW_pcie_ep0_gt_drdy_4_UNCONNECTED,
      gt_drdy(3) => NLW_pcie_ep0_gt_drdy_3_UNCONNECTED,
      gt_drdy(2) => NLW_pcie_ep0_gt_drdy_2_UNCONNECTED,
      gt_drdy(1) => NLW_pcie_ep0_gt_drdy_1_UNCONNECTED,
      gt_drdy(0) => NLW_pcie_ep0_gt_drdy_0_UNCONNECTED,
      trn_rbar_hit_n(6) => trn_rbar_hit_n(6),
      trn_rbar_hit_n(5) => trn_rbar_hit_n(5),
      trn_rbar_hit_n(4) => trn_rbar_hit_n(4),
      trn_rbar_hit_n(3) => trn_rbar_hit_n(3),
      trn_rbar_hit_n(2) => trn_rbar_hit_n(2),
      trn_rbar_hit_n(1) => trn_rbar_hit_n(1),
      trn_rbar_hit_n(0) => trn_rbar_hit_n(0),
      trn_rfc_npd_av(11) => trn_rfc_npd_av(11),
      trn_rfc_npd_av(10) => trn_rfc_npd_av(10),
      trn_rfc_npd_av(9) => trn_rfc_npd_av(9),
      trn_rfc_npd_av(8) => trn_rfc_npd_av(8),
      trn_rfc_npd_av(7) => trn_rfc_npd_av(7),
      trn_rfc_npd_av(6) => trn_rfc_npd_av(6),
      trn_rfc_npd_av(5) => trn_rfc_npd_av(5),
      trn_rfc_npd_av(4) => trn_rfc_npd_av(4),
      trn_rfc_npd_av(3) => trn_rfc_npd_av(3),
      trn_rfc_npd_av(2) => trn_rfc_npd_av(2),
      trn_rfc_npd_av(1) => trn_rfc_npd_av(1),
      trn_rfc_npd_av(0) => trn_rfc_npd_av(0),
      cfg_dcommand(15) => cfg_dcommand(15),
      cfg_dcommand(14) => cfg_dcommand(14),
      cfg_dcommand(13) => cfg_dcommand(13),
      cfg_dcommand(12) => cfg_dcommand(12),
      cfg_dcommand(11) => cfg_dcommand(11),
      cfg_dcommand(10) => cfg_dcommand(10),
      cfg_dcommand(9) => cfg_dcommand(9),
      cfg_dcommand(8) => cfg_dcommand(8),
      cfg_dcommand(7) => cfg_dcommand(7),
      cfg_dcommand(6) => cfg_dcommand(6),
      cfg_dcommand(5) => cfg_dcommand(5),
      cfg_dcommand(4) => cfg_dcommand(4),
      cfg_dcommand(3) => cfg_dcommand(3),
      cfg_dcommand(2) => cfg_dcommand(2),
      cfg_dcommand(1) => cfg_dcommand(1),
      cfg_dcommand(0) => cfg_dcommand(0),
      cfg_pcie_link_state_n(2) => cfg_pcie_link_state_n(2),
      cfg_pcie_link_state_n(1) => cfg_pcie_link_state_n(1),
      cfg_pcie_link_state_n(0) => cfg_pcie_link_state_n(0),
      gt_do(127) => NLW_pcie_ep0_gt_do_127_UNCONNECTED,
      gt_do(126) => NLW_pcie_ep0_gt_do_126_UNCONNECTED,
      gt_do(125) => NLW_pcie_ep0_gt_do_125_UNCONNECTED,
      gt_do(124) => NLW_pcie_ep0_gt_do_124_UNCONNECTED,
      gt_do(123) => NLW_pcie_ep0_gt_do_123_UNCONNECTED,
      gt_do(122) => NLW_pcie_ep0_gt_do_122_UNCONNECTED,
      gt_do(121) => NLW_pcie_ep0_gt_do_121_UNCONNECTED,
      gt_do(120) => NLW_pcie_ep0_gt_do_120_UNCONNECTED,
      gt_do(119) => NLW_pcie_ep0_gt_do_119_UNCONNECTED,
      gt_do(118) => NLW_pcie_ep0_gt_do_118_UNCONNECTED,
      gt_do(117) => NLW_pcie_ep0_gt_do_117_UNCONNECTED,
      gt_do(116) => NLW_pcie_ep0_gt_do_116_UNCONNECTED,
      gt_do(115) => NLW_pcie_ep0_gt_do_115_UNCONNECTED,
      gt_do(114) => NLW_pcie_ep0_gt_do_114_UNCONNECTED,
      gt_do(113) => NLW_pcie_ep0_gt_do_113_UNCONNECTED,
      gt_do(112) => NLW_pcie_ep0_gt_do_112_UNCONNECTED,
      gt_do(111) => NLW_pcie_ep0_gt_do_111_UNCONNECTED,
      gt_do(110) => NLW_pcie_ep0_gt_do_110_UNCONNECTED,
      gt_do(109) => NLW_pcie_ep0_gt_do_109_UNCONNECTED,
      gt_do(108) => NLW_pcie_ep0_gt_do_108_UNCONNECTED,
      gt_do(107) => NLW_pcie_ep0_gt_do_107_UNCONNECTED,
      gt_do(106) => NLW_pcie_ep0_gt_do_106_UNCONNECTED,
      gt_do(105) => NLW_pcie_ep0_gt_do_105_UNCONNECTED,
      gt_do(104) => NLW_pcie_ep0_gt_do_104_UNCONNECTED,
      gt_do(103) => NLW_pcie_ep0_gt_do_103_UNCONNECTED,
      gt_do(102) => NLW_pcie_ep0_gt_do_102_UNCONNECTED,
      gt_do(101) => NLW_pcie_ep0_gt_do_101_UNCONNECTED,
      gt_do(100) => NLW_pcie_ep0_gt_do_100_UNCONNECTED,
      gt_do(99) => NLW_pcie_ep0_gt_do_99_UNCONNECTED,
      gt_do(98) => NLW_pcie_ep0_gt_do_98_UNCONNECTED,
      gt_do(97) => NLW_pcie_ep0_gt_do_97_UNCONNECTED,
      gt_do(96) => NLW_pcie_ep0_gt_do_96_UNCONNECTED,
      gt_do(95) => NLW_pcie_ep0_gt_do_95_UNCONNECTED,
      gt_do(94) => NLW_pcie_ep0_gt_do_94_UNCONNECTED,
      gt_do(93) => NLW_pcie_ep0_gt_do_93_UNCONNECTED,
      gt_do(92) => NLW_pcie_ep0_gt_do_92_UNCONNECTED,
      gt_do(91) => NLW_pcie_ep0_gt_do_91_UNCONNECTED,
      gt_do(90) => NLW_pcie_ep0_gt_do_90_UNCONNECTED,
      gt_do(89) => NLW_pcie_ep0_gt_do_89_UNCONNECTED,
      gt_do(88) => NLW_pcie_ep0_gt_do_88_UNCONNECTED,
      gt_do(87) => NLW_pcie_ep0_gt_do_87_UNCONNECTED,
      gt_do(86) => NLW_pcie_ep0_gt_do_86_UNCONNECTED,
      gt_do(85) => NLW_pcie_ep0_gt_do_85_UNCONNECTED,
      gt_do(84) => NLW_pcie_ep0_gt_do_84_UNCONNECTED,
      gt_do(83) => NLW_pcie_ep0_gt_do_83_UNCONNECTED,
      gt_do(82) => NLW_pcie_ep0_gt_do_82_UNCONNECTED,
      gt_do(81) => NLW_pcie_ep0_gt_do_81_UNCONNECTED,
      gt_do(80) => NLW_pcie_ep0_gt_do_80_UNCONNECTED,
      gt_do(79) => NLW_pcie_ep0_gt_do_79_UNCONNECTED,
      gt_do(78) => NLW_pcie_ep0_gt_do_78_UNCONNECTED,
      gt_do(77) => NLW_pcie_ep0_gt_do_77_UNCONNECTED,
      gt_do(76) => NLW_pcie_ep0_gt_do_76_UNCONNECTED,
      gt_do(75) => NLW_pcie_ep0_gt_do_75_UNCONNECTED,
      gt_do(74) => NLW_pcie_ep0_gt_do_74_UNCONNECTED,
      gt_do(73) => NLW_pcie_ep0_gt_do_73_UNCONNECTED,
      gt_do(72) => NLW_pcie_ep0_gt_do_72_UNCONNECTED,
      gt_do(71) => NLW_pcie_ep0_gt_do_71_UNCONNECTED,
      gt_do(70) => NLW_pcie_ep0_gt_do_70_UNCONNECTED,
      gt_do(69) => NLW_pcie_ep0_gt_do_69_UNCONNECTED,
      gt_do(68) => NLW_pcie_ep0_gt_do_68_UNCONNECTED,
      gt_do(67) => NLW_pcie_ep0_gt_do_67_UNCONNECTED,
      gt_do(66) => NLW_pcie_ep0_gt_do_66_UNCONNECTED,
      gt_do(65) => NLW_pcie_ep0_gt_do_65_UNCONNECTED,
      gt_do(64) => NLW_pcie_ep0_gt_do_64_UNCONNECTED,
      gt_do(63) => NLW_pcie_ep0_gt_do_63_UNCONNECTED,
      gt_do(62) => NLW_pcie_ep0_gt_do_62_UNCONNECTED,
      gt_do(61) => NLW_pcie_ep0_gt_do_61_UNCONNECTED,
      gt_do(60) => NLW_pcie_ep0_gt_do_60_UNCONNECTED,
      gt_do(59) => NLW_pcie_ep0_gt_do_59_UNCONNECTED,
      gt_do(58) => NLW_pcie_ep0_gt_do_58_UNCONNECTED,
      gt_do(57) => NLW_pcie_ep0_gt_do_57_UNCONNECTED,
      gt_do(56) => NLW_pcie_ep0_gt_do_56_UNCONNECTED,
      gt_do(55) => NLW_pcie_ep0_gt_do_55_UNCONNECTED,
      gt_do(54) => NLW_pcie_ep0_gt_do_54_UNCONNECTED,
      gt_do(53) => NLW_pcie_ep0_gt_do_53_UNCONNECTED,
      gt_do(52) => NLW_pcie_ep0_gt_do_52_UNCONNECTED,
      gt_do(51) => NLW_pcie_ep0_gt_do_51_UNCONNECTED,
      gt_do(50) => NLW_pcie_ep0_gt_do_50_UNCONNECTED,
      gt_do(49) => NLW_pcie_ep0_gt_do_49_UNCONNECTED,
      gt_do(48) => NLW_pcie_ep0_gt_do_48_UNCONNECTED,
      gt_do(47) => NLW_pcie_ep0_gt_do_47_UNCONNECTED,
      gt_do(46) => NLW_pcie_ep0_gt_do_46_UNCONNECTED,
      gt_do(45) => NLW_pcie_ep0_gt_do_45_UNCONNECTED,
      gt_do(44) => NLW_pcie_ep0_gt_do_44_UNCONNECTED,
      gt_do(43) => NLW_pcie_ep0_gt_do_43_UNCONNECTED,
      gt_do(42) => NLW_pcie_ep0_gt_do_42_UNCONNECTED,
      gt_do(41) => NLW_pcie_ep0_gt_do_41_UNCONNECTED,
      gt_do(40) => NLW_pcie_ep0_gt_do_40_UNCONNECTED,
      gt_do(39) => NLW_pcie_ep0_gt_do_39_UNCONNECTED,
      gt_do(38) => NLW_pcie_ep0_gt_do_38_UNCONNECTED,
      gt_do(37) => NLW_pcie_ep0_gt_do_37_UNCONNECTED,
      gt_do(36) => NLW_pcie_ep0_gt_do_36_UNCONNECTED,
      gt_do(35) => NLW_pcie_ep0_gt_do_35_UNCONNECTED,
      gt_do(34) => NLW_pcie_ep0_gt_do_34_UNCONNECTED,
      gt_do(33) => NLW_pcie_ep0_gt_do_33_UNCONNECTED,
      gt_do(32) => NLW_pcie_ep0_gt_do_32_UNCONNECTED,
      gt_do(31) => NLW_pcie_ep0_gt_do_31_UNCONNECTED,
      gt_do(30) => NLW_pcie_ep0_gt_do_30_UNCONNECTED,
      gt_do(29) => NLW_pcie_ep0_gt_do_29_UNCONNECTED,
      gt_do(28) => NLW_pcie_ep0_gt_do_28_UNCONNECTED,
      gt_do(27) => NLW_pcie_ep0_gt_do_27_UNCONNECTED,
      gt_do(26) => NLW_pcie_ep0_gt_do_26_UNCONNECTED,
      gt_do(25) => NLW_pcie_ep0_gt_do_25_UNCONNECTED,
      gt_do(24) => NLW_pcie_ep0_gt_do_24_UNCONNECTED,
      gt_do(23) => NLW_pcie_ep0_gt_do_23_UNCONNECTED,
      gt_do(22) => NLW_pcie_ep0_gt_do_22_UNCONNECTED,
      gt_do(21) => NLW_pcie_ep0_gt_do_21_UNCONNECTED,
      gt_do(20) => NLW_pcie_ep0_gt_do_20_UNCONNECTED,
      gt_do(19) => NLW_pcie_ep0_gt_do_19_UNCONNECTED,
      gt_do(18) => NLW_pcie_ep0_gt_do_18_UNCONNECTED,
      gt_do(17) => NLW_pcie_ep0_gt_do_17_UNCONNECTED,
      gt_do(16) => NLW_pcie_ep0_gt_do_16_UNCONNECTED,
      gt_do(15) => NLW_pcie_ep0_gt_do_15_UNCONNECTED,
      gt_do(14) => NLW_pcie_ep0_gt_do_14_UNCONNECTED,
      gt_do(13) => NLW_pcie_ep0_gt_do_13_UNCONNECTED,
      gt_do(12) => NLW_pcie_ep0_gt_do_12_UNCONNECTED,
      gt_do(11) => NLW_pcie_ep0_gt_do_11_UNCONNECTED,
      gt_do(10) => NLW_pcie_ep0_gt_do_10_UNCONNECTED,
      gt_do(9) => NLW_pcie_ep0_gt_do_9_UNCONNECTED,
      gt_do(8) => NLW_pcie_ep0_gt_do_8_UNCONNECTED,
      gt_do(7) => NLW_pcie_ep0_gt_do_7_UNCONNECTED,
      gt_do(6) => NLW_pcie_ep0_gt_do_6_UNCONNECTED,
      gt_do(5) => NLW_pcie_ep0_gt_do_5_UNCONNECTED,
      gt_do(4) => NLW_pcie_ep0_gt_do_4_UNCONNECTED,
      gt_do(3) => NLW_pcie_ep0_gt_do_3_UNCONNECTED,
      gt_do(2) => NLW_pcie_ep0_gt_do_2_UNCONNECTED,
      gt_do(1) => NLW_pcie_ep0_gt_do_1_UNCONNECTED,
      gt_do(0) => NLW_pcie_ep0_gt_do_0_UNCONNECTED,
      trn_rfc_pd_av(11) => trn_rfc_pd_av(11),
      trn_rfc_pd_av(10) => trn_rfc_pd_av(10),
      trn_rfc_pd_av(9) => trn_rfc_pd_av(9),
      trn_rfc_pd_av(8) => trn_rfc_pd_av(8),
      trn_rfc_pd_av(7) => trn_rfc_pd_av(7),
      trn_rfc_pd_av(6) => trn_rfc_pd_av(6),
      trn_rfc_pd_av(5) => trn_rfc_pd_av(5),
      trn_rfc_pd_av(4) => trn_rfc_pd_av(4),
      trn_rfc_pd_av(3) => trn_rfc_pd_av(3),
      trn_rfc_pd_av(2) => trn_rfc_pd_av(2),
      trn_rfc_pd_av(1) => trn_rfc_pd_av(1),
      trn_rfc_pd_av(0) => trn_rfc_pd_av(0),
      cfg_function_number(2) => cfg_function_number(2),
      cfg_function_number(1) => cfg_function_number(1),
      cfg_function_number(0) => cfg_function_number(0),
      trn_rd(63) => trn_rd(63),
      trn_rd(62) => trn_rd(62),
      trn_rd(61) => trn_rd(61),
      trn_rd(60) => trn_rd(60),
      trn_rd(59) => trn_rd(59),
      trn_rd(58) => trn_rd(58),
      trn_rd(57) => trn_rd(57),
      trn_rd(56) => trn_rd(56),
      trn_rd(55) => trn_rd(55),
      trn_rd(54) => trn_rd(54),
      trn_rd(53) => trn_rd(53),
      trn_rd(52) => trn_rd(52),
      trn_rd(51) => trn_rd(51),
      trn_rd(50) => trn_rd(50),
      trn_rd(49) => trn_rd(49),
      trn_rd(48) => trn_rd(48),
      trn_rd(47) => trn_rd(47),
      trn_rd(46) => trn_rd(46),
      trn_rd(45) => trn_rd(45),
      trn_rd(44) => trn_rd(44),
      trn_rd(43) => trn_rd(43),
      trn_rd(42) => trn_rd(42),
      trn_rd(41) => trn_rd(41),
      trn_rd(40) => trn_rd(40),
      trn_rd(39) => trn_rd(39),
      trn_rd(38) => trn_rd(38),
      trn_rd(37) => trn_rd(37),
      trn_rd(36) => trn_rd(36),
      trn_rd(35) => trn_rd(35),
      trn_rd(34) => trn_rd(34),
      trn_rd(33) => trn_rd(33),
      trn_rd(32) => trn_rd(32),
      trn_rd(31) => trn_rd(31),
      trn_rd(30) => trn_rd(30),
      trn_rd(29) => trn_rd(29),
      trn_rd(28) => trn_rd(28),
      trn_rd(27) => trn_rd(27),
      trn_rd(26) => trn_rd(26),
      trn_rd(25) => trn_rd(25),
      trn_rd(24) => trn_rd(24),
      trn_rd(23) => trn_rd(23),
      trn_rd(22) => trn_rd(22),
      trn_rd(21) => trn_rd(21),
      trn_rd(20) => trn_rd(20),
      trn_rd(19) => trn_rd(19),
      trn_rd(18) => trn_rd(18),
      trn_rd(17) => trn_rd(17),
      trn_rd(16) => trn_rd(16),
      trn_rd(15) => trn_rd(15),
      trn_rd(14) => trn_rd(14),
      trn_rd(13) => trn_rd(13),
      trn_rd(12) => trn_rd(12),
      trn_rd(11) => trn_rd(11),
      trn_rd(10) => trn_rd(10),
      trn_rd(9) => trn_rd(9),
      trn_rd(8) => trn_rd(8),
      trn_rd(7) => trn_rd(7),
      trn_rd(6) => trn_rd(6),
      trn_rd(5) => trn_rd(5),
      trn_rd(4) => trn_rd(4),
      trn_rd(3) => trn_rd(3),
      trn_rd(2) => trn_rd(2),
      trn_rd(1) => trn_rd(1),
      trn_rd(0) => trn_rd(0),
      cfg_do(31) => cfg_do(31),
      cfg_do(30) => cfg_do(30),
      cfg_do(29) => cfg_do(29),
      cfg_do(28) => cfg_do(28),
      cfg_do(27) => cfg_do(27),
      cfg_do(26) => cfg_do(26),
      cfg_do(25) => cfg_do(25),
      cfg_do(24) => cfg_do(24),
      cfg_do(23) => cfg_do(23),
      cfg_do(22) => cfg_do(22),
      cfg_do(21) => cfg_do(21),
      cfg_do(20) => cfg_do(20),
      cfg_do(19) => cfg_do(19),
      cfg_do(18) => cfg_do(18),
      cfg_do(17) => cfg_do(17),
      cfg_do(16) => cfg_do(16),
      cfg_do(15) => cfg_do(15),
      cfg_do(14) => cfg_do(14),
      cfg_do(13) => cfg_do(13),
      cfg_do(12) => cfg_do(12),
      cfg_do(11) => cfg_do(11),
      cfg_do(10) => cfg_do(10),
      cfg_do(9) => cfg_do(9),
      cfg_do(8) => cfg_do(8),
      cfg_do(7) => cfg_do(7),
      cfg_do(6) => cfg_do(6),
      cfg_do(5) => cfg_do(5),
      cfg_do(4) => cfg_do(4),
      cfg_do(3) => cfg_do(3),
      cfg_do(2) => cfg_do(2),
      cfg_do(1) => cfg_do(1),
      cfg_do(0) => cfg_do(0),
      trn_td(63) => trn_td(63),
      trn_td(62) => trn_td(62),
      trn_td(61) => trn_td(61),
      trn_td(60) => trn_td(60),
      trn_td(59) => trn_td(59),
      trn_td(58) => trn_td(58),
      trn_td(57) => trn_td(57),
      trn_td(56) => trn_td(56),
      trn_td(55) => trn_td(55),
      trn_td(54) => trn_td(54),
      trn_td(53) => trn_td(53),
      trn_td(52) => trn_td(52),
      trn_td(51) => trn_td(51),
      trn_td(50) => trn_td(50),
      trn_td(49) => trn_td(49),
      trn_td(48) => trn_td(48),
      trn_td(47) => trn_td(47),
      trn_td(46) => trn_td(46),
      trn_td(45) => trn_td(45),
      trn_td(44) => trn_td(44),
      trn_td(43) => trn_td(43),
      trn_td(42) => trn_td(42),
      trn_td(41) => trn_td(41),
      trn_td(40) => trn_td(40),
      trn_td(39) => trn_td(39),
      trn_td(38) => trn_td(38),
      trn_td(37) => trn_td(37),
      trn_td(36) => trn_td(36),
      trn_td(35) => trn_td(35),
      trn_td(34) => trn_td(34),
      trn_td(33) => trn_td(33),
      trn_td(32) => trn_td(32),
      trn_td(31) => trn_td(31),
      trn_td(30) => trn_td(30),
      trn_td(29) => trn_td(29),
      trn_td(28) => trn_td(28),
      trn_td(27) => trn_td(27),
      trn_td(26) => trn_td(26),
      trn_td(25) => trn_td(25),
      trn_td(24) => trn_td(24),
      trn_td(23) => trn_td(23),
      trn_td(22) => trn_td(22),
      trn_td(21) => trn_td(21),
      trn_td(20) => trn_td(20),
      trn_td(19) => trn_td(19),
      trn_td(18) => trn_td(18),
      trn_td(17) => trn_td(17),
      trn_td(16) => trn_td(16),
      trn_td(15) => trn_td(15),
      trn_td(14) => trn_td(14),
      trn_td(13) => trn_td(13),
      trn_td(12) => trn_td(12),
      trn_td(11) => trn_td(11),
      trn_td(10) => trn_td(10),
      trn_td(9) => trn_td(9),
      trn_td(8) => trn_td(8),
      trn_td(7) => trn_td(7),
      trn_td(6) => trn_td(6),
      trn_td(5) => trn_td(5),
      trn_td(4) => trn_td(4),
      trn_td(3) => trn_td(3),
      trn_td(2) => trn_td(2),
      trn_td(1) => trn_td(1),
      trn_td(0) => trn_td(0),
      gt_den(7) => N0,
      gt_den(6) => N0,
      gt_den(5) => N0,
      gt_den(4) => N0,
      gt_den(3) => N0,
      gt_den(2) => N0,
      gt_den(1) => N0,
      gt_den(0) => N0,
      cfg_byte_en_n(3) => NLW_pcie_ep0_cfg_byte_en_n_3_UNCONNECTED,
      cfg_byte_en_n(2) => NLW_pcie_ep0_cfg_byte_en_n_2_UNCONNECTED,
      cfg_byte_en_n(1) => NLW_pcie_ep0_cfg_byte_en_n_1_UNCONNECTED,
      cfg_byte_en_n(0) => NLW_pcie_ep0_cfg_byte_en_n_0_UNCONNECTED,
      cfg_interrupt_di(7) => N0,
      cfg_interrupt_di(6) => N0,
      cfg_interrupt_di(5) => N0,
      cfg_interrupt_di(4) => N0,
      cfg_interrupt_di(3) => N0,
      cfg_interrupt_di(2) => N0,
      cfg_interrupt_di(1) => N0,
      cfg_interrupt_di(0) => N0,
      gt_dwen(7) => N0,
      gt_dwen(6) => N0,
      gt_dwen(5) => N0,
      gt_dwen(4) => N0,
      gt_dwen(3) => N0,
      gt_dwen(2) => N0,
      gt_dwen(1) => N0,
      gt_dwen(0) => N0,
      gt_daddr(55) => N0,
      gt_daddr(54) => N0,
      gt_daddr(53) => N0,
      gt_daddr(52) => N0,
      gt_daddr(51) => N0,
      gt_daddr(50) => N0,
      gt_daddr(49) => N0,
      gt_daddr(48) => N0,
      gt_daddr(47) => N0,
      gt_daddr(46) => N0,
      gt_daddr(45) => N0,
      gt_daddr(44) => N0,
      gt_daddr(43) => N0,
      gt_daddr(42) => N0,
      gt_daddr(41) => N0,
      gt_daddr(40) => N0,
      gt_daddr(39) => N0,
      gt_daddr(38) => N0,
      gt_daddr(37) => N0,
      gt_daddr(36) => N0,
      gt_daddr(35) => N0,
      gt_daddr(34) => N0,
      gt_daddr(33) => N0,
      gt_daddr(32) => N0,
      gt_daddr(31) => N0,
      gt_daddr(30) => N0,
      gt_daddr(29) => N0,
      gt_daddr(28) => N0,
      gt_daddr(27) => N0,
      gt_daddr(26) => N0,
      gt_daddr(25) => N0,
      gt_daddr(24) => N0,
      gt_daddr(23) => N0,
      gt_daddr(22) => N0,
      gt_daddr(21) => N0,
      gt_daddr(20) => N0,
      gt_daddr(19) => N0,
      gt_daddr(18) => N0,
      gt_daddr(17) => N0,
      gt_daddr(16) => N0,
      gt_daddr(15) => N0,
      gt_daddr(14) => N0,
      gt_daddr(13) => N0,
      gt_daddr(12) => N0,
      gt_daddr(11) => N0,
      gt_daddr(10) => N0,
      gt_daddr(9) => N0,
      gt_daddr(8) => N0,
      gt_daddr(7) => N0,
      gt_daddr(6) => N0,
      gt_daddr(5) => N0,
      gt_daddr(4) => N0,
      gt_daddr(3) => N0,
      gt_daddr(2) => N0,
      gt_daddr(1) => N0,
      gt_daddr(0) => N0,
      cfg_dsn(63) => N0,
      cfg_dsn(62) => N0,
      cfg_dsn(61) => N0,
      cfg_dsn(60) => N0,
      cfg_dsn(59) => N0,
      cfg_dsn(58) => N0,
      cfg_dsn(57) => N0,
      cfg_dsn(56) => N0,
      cfg_dsn(55) => N0,
      cfg_dsn(54) => N0,
      cfg_dsn(53) => N0,
      cfg_dsn(52) => N0,
      cfg_dsn(51) => N0,
      cfg_dsn(50) => N0,
      cfg_dsn(49) => N0,
      cfg_dsn(48) => N0,
      cfg_dsn(47) => N0,
      cfg_dsn(46) => N0,
      cfg_dsn(45) => N0,
      cfg_dsn(44) => N0,
      cfg_dsn(43) => N0,
      cfg_dsn(42) => N0,
      cfg_dsn(41) => N0,
      cfg_dsn(40) => N0,
      cfg_dsn(39) => N0,
      cfg_dsn(38) => N0,
      cfg_dsn(37) => N0,
      cfg_dsn(36) => N0,
      cfg_dsn(35) => N0,
      cfg_dsn(34) => N0,
      cfg_dsn(33) => N0,
      cfg_dsn(32) => N0,
      cfg_dsn(31) => N0,
      cfg_dsn(30) => N0,
      cfg_dsn(29) => N0,
      cfg_dsn(28) => N0,
      cfg_dsn(27) => N0,
      cfg_dsn(26) => N0,
      cfg_dsn(25) => N0,
      cfg_dsn(24) => N0,
      cfg_dsn(23) => N0,
      cfg_dsn(22) => N0,
      cfg_dsn(21) => N0,
      cfg_dsn(20) => N0,
      cfg_dsn(19) => N0,
      cfg_dsn(18) => N0,
      cfg_dsn(17) => N0,
      cfg_dsn(16) => N0,
      cfg_dsn(15) => N0,
      cfg_dsn(14) => N0,
      cfg_dsn(13) => N0,
      cfg_dsn(12) => N0,
      cfg_dsn(11) => N0,
      cfg_dsn(10) => N0,
      cfg_dsn(9) => N0,
      cfg_dsn(8) => N0,
      cfg_dsn(7) => N0,
      cfg_dsn(6) => N0,
      cfg_dsn(5) => N0,
      cfg_dsn(4) => N0,
      cfg_dsn(3) => N0,
      cfg_dsn(2) => N0,
      cfg_dsn(1) => N0,
      cfg_dsn(0) => N0,
      cfg_err_tlp_cpl_header(47) => N0,
      cfg_err_tlp_cpl_header(46) => N0,
      cfg_err_tlp_cpl_header(45) => N0,
      cfg_err_tlp_cpl_header(44) => N0,
      cfg_err_tlp_cpl_header(43) => N0,
      cfg_err_tlp_cpl_header(42) => N0,
      cfg_err_tlp_cpl_header(41) => N0,
      cfg_err_tlp_cpl_header(40) => N0,
      cfg_err_tlp_cpl_header(39) => N0,
      cfg_err_tlp_cpl_header(38) => N0,
      cfg_err_tlp_cpl_header(37) => N0,
      cfg_err_tlp_cpl_header(36) => N0,
      cfg_err_tlp_cpl_header(35) => N0,
      cfg_err_tlp_cpl_header(34) => N0,
      cfg_err_tlp_cpl_header(33) => N0,
      cfg_err_tlp_cpl_header(32) => N0,
      cfg_err_tlp_cpl_header(31) => N0,
      cfg_err_tlp_cpl_header(30) => N0,
      cfg_err_tlp_cpl_header(29) => N0,
      cfg_err_tlp_cpl_header(28) => N0,
      cfg_err_tlp_cpl_header(27) => N0,
      cfg_err_tlp_cpl_header(26) => N0,
      cfg_err_tlp_cpl_header(25) => N0,
      cfg_err_tlp_cpl_header(24) => N0,
      cfg_err_tlp_cpl_header(23) => N0,
      cfg_err_tlp_cpl_header(22) => N0,
      cfg_err_tlp_cpl_header(21) => N0,
      cfg_err_tlp_cpl_header(20) => N0,
      cfg_err_tlp_cpl_header(19) => N0,
      cfg_err_tlp_cpl_header(18) => N0,
      cfg_err_tlp_cpl_header(17) => N0,
      cfg_err_tlp_cpl_header(16) => N0,
      cfg_err_tlp_cpl_header(15) => N0,
      cfg_err_tlp_cpl_header(14) => N0,
      cfg_err_tlp_cpl_header(13) => N0,
      cfg_err_tlp_cpl_header(12) => N0,
      cfg_err_tlp_cpl_header(11) => N0,
      cfg_err_tlp_cpl_header(10) => N0,
      cfg_err_tlp_cpl_header(9) => N0,
      cfg_err_tlp_cpl_header(8) => N0,
      cfg_err_tlp_cpl_header(7) => N0,
      cfg_err_tlp_cpl_header(6) => N0,
      cfg_err_tlp_cpl_header(5) => N0,
      cfg_err_tlp_cpl_header(4) => N0,
      cfg_err_tlp_cpl_header(3) => N0,
      cfg_err_tlp_cpl_header(2) => N0,
      cfg_err_tlp_cpl_header(1) => N0,
      cfg_err_tlp_cpl_header(0) => N0,
      gt_txbuffctrl_0(2) => NLW_pcie_ep0_gt_txbuffctrl_0_2_UNCONNECTED,
      gt_txbuffctrl_0(1) => N0,
      gt_txbuffctrl_0(0) => N0,
      cfg_dwaddr(9) => N0,
      cfg_dwaddr(8) => N0,
      cfg_dwaddr(7) => N0,
      cfg_dwaddr(6) => N0,
      cfg_dwaddr(5) => N0,
      cfg_dwaddr(4) => N0,
      cfg_dwaddr(3) => N0,
      cfg_dwaddr(2) => N0,
      cfg_dwaddr(1) => N0,
      cfg_dwaddr(0) => N0,
      gt_txbuffctrl_1(2) => NLW_pcie_ep0_gt_txbuffctrl_1_2_UNCONNECTED,
      gt_txbuffctrl_1(1) => N0,
      gt_txbuffctrl_1(0) => N0,
      gt_txdiffctrl_0(2) => NLW_pcie_ep0_gt_txdiffctrl_0_2_UNCONNECTED,
      gt_txdiffctrl_0(1) => N0,
      gt_txdiffctrl_0(0) => N0,
      gt_txdiffctrl_1(2) => NLW_pcie_ep0_gt_txdiffctrl_1_2_UNCONNECTED,
      gt_txdiffctrl_1(1) => N0,
      gt_txdiffctrl_1(0) => N0,
      gt_txpreemphesis_0(2) => NLW_pcie_ep0_gt_txpreemphesis_0_2_UNCONNECTED,
      gt_txpreemphesis_0(1) => NLW_pcie_ep0_gt_txpreemphesis_0_1_UNCONNECTED,
      gt_txpreemphesis_0(0) => NLW_pcie_ep0_gt_txpreemphesis_0_0_UNCONNECTED,
      gt_txpreemphesis_1(2) => NLW_pcie_ep0_gt_txpreemphesis_1_2_UNCONNECTED,
      gt_txpreemphesis_1(1) => NLW_pcie_ep0_gt_txpreemphesis_1_1_UNCONNECTED,
      gt_txpreemphesis_1(0) => NLW_pcie_ep0_gt_txpreemphesis_1_0_UNCONNECTED,
      gt_di(127) => N0,
      gt_di(126) => N0,
      gt_di(125) => N0,
      gt_di(124) => N0,
      gt_di(123) => N0,
      gt_di(122) => N0,
      gt_di(121) => N0,
      gt_di(120) => N0,
      gt_di(119) => N0,
      gt_di(118) => N0,
      gt_di(117) => N0,
      gt_di(116) => N0,
      gt_di(115) => N0,
      gt_di(114) => N0,
      gt_di(113) => N0,
      gt_di(112) => N0,
      gt_di(111) => N0,
      gt_di(110) => N0,
      gt_di(109) => N0,
      gt_di(108) => N0,
      gt_di(107) => N0,
      gt_di(106) => N0,
      gt_di(105) => N0,
      gt_di(104) => N0,
      gt_di(103) => N0,
      gt_di(102) => N0,
      gt_di(101) => N0,
      gt_di(100) => N0,
      gt_di(99) => N0,
      gt_di(98) => N0,
      gt_di(97) => N0,
      gt_di(96) => N0,
      gt_di(95) => N0,
      gt_di(94) => N0,
      gt_di(93) => N0,
      gt_di(92) => N0,
      gt_di(91) => N0,
      gt_di(90) => N0,
      gt_di(89) => N0,
      gt_di(88) => N0,
      gt_di(87) => N0,
      gt_di(86) => N0,
      gt_di(85) => N0,
      gt_di(84) => N0,
      gt_di(83) => N0,
      gt_di(82) => N0,
      gt_di(81) => N0,
      gt_di(80) => N0,
      gt_di(79) => N0,
      gt_di(78) => N0,
      gt_di(77) => N0,
      gt_di(76) => N0,
      gt_di(75) => N0,
      gt_di(74) => N0,
      gt_di(73) => N0,
      gt_di(72) => N0,
      gt_di(71) => N0,
      gt_di(70) => N0,
      gt_di(69) => N0,
      gt_di(68) => N0,
      gt_di(67) => N0,
      gt_di(66) => N0,
      gt_di(65) => N0,
      gt_di(64) => N0,
      gt_di(63) => N0,
      gt_di(62) => N0,
      gt_di(61) => N0,
      gt_di(60) => N0,
      gt_di(59) => N0,
      gt_di(58) => N0,
      gt_di(57) => N0,
      gt_di(56) => N0,
      gt_di(55) => N0,
      gt_di(54) => N0,
      gt_di(53) => N0,
      gt_di(52) => N0,
      gt_di(51) => N0,
      gt_di(50) => N0,
      gt_di(49) => N0,
      gt_di(48) => N0,
      gt_di(47) => N0,
      gt_di(46) => N0,
      gt_di(45) => N0,
      gt_di(44) => N0,
      gt_di(43) => N0,
      gt_di(42) => N0,
      gt_di(41) => N0,
      gt_di(40) => N0,
      gt_di(39) => N0,
      gt_di(38) => N0,
      gt_di(37) => N0,
      gt_di(36) => N0,
      gt_di(35) => N0,
      gt_di(34) => N0,
      gt_di(33) => N0,
      gt_di(32) => N0,
      gt_di(31) => N0,
      gt_di(30) => N0,
      gt_di(29) => N0,
      gt_di(28) => N0,
      gt_di(27) => N0,
      gt_di(26) => N0,
      gt_di(25) => N0,
      gt_di(24) => N0,
      gt_di(23) => N0,
      gt_di(22) => N0,
      gt_di(21) => N0,
      gt_di(20) => N0,
      gt_di(19) => N0,
      gt_di(18) => N0,
      gt_di(17) => N0,
      gt_di(16) => N0,
      gt_di(15) => N0,
      gt_di(14) => N0,
      gt_di(13) => N0,
      gt_di(12) => N0,
      gt_di(11) => N0,
      gt_di(10) => N0,
      gt_di(9) => N0,
      gt_di(8) => N0,
      gt_di(7) => N0,
      gt_di(6) => N0,
      gt_di(5) => N0,
      gt_di(4) => N0,
      gt_di(3) => N0,
      gt_di(2) => N0,
      gt_di(1) => N0,
      gt_di(0) => N0,
      trn_trem_n(7) => trn_trem_n(7),
      trn_trem_n(6) => trn_trem_n(6),
      trn_trem_n(5) => trn_trem_n(5),
      trn_trem_n(4) => trn_trem_n(4),
      trn_trem_n(3) => trn_trem_n(3),
      trn_trem_n(2) => trn_trem_n(2),
      trn_trem_n(1) => trn_trem_n(1),
      trn_trem_n(0) => trn_trem_n(0),
      pci_exp_rxn(7) => pci_exp_rxn(7),
      pci_exp_rxn(6) => pci_exp_rxn(6),
      pci_exp_rxn(5) => pci_exp_rxn(5),
      pci_exp_rxn(4) => pci_exp_rxn(4),
      pci_exp_rxn(3) => pci_exp_rxn(3),
      pci_exp_rxn(2) => pci_exp_rxn(2),
      pci_exp_rxn(1) => pci_exp_rxn(1),
      pci_exp_rxn(0) => pci_exp_rxn(0),
      pci_exp_rxp(7) => pci_exp_rxp(7),
      pci_exp_rxp(6) => pci_exp_rxp(6),
      pci_exp_rxp(5) => pci_exp_rxp(5),
      pci_exp_rxp(4) => pci_exp_rxp(4),
      pci_exp_rxp(3) => pci_exp_rxp(3),
      pci_exp_rxp(2) => pci_exp_rxp(2),
      pci_exp_rxp(1) => pci_exp_rxp(1),
      pci_exp_rxp(0) => pci_exp_rxp(0),
      cfg_di(31) => N0,
      cfg_di(30) => N0,
      cfg_di(29) => N0,
      cfg_di(28) => N0,
      cfg_di(27) => N0,
      cfg_di(26) => N0,
      cfg_di(25) => N0,
      cfg_di(24) => N0,
      cfg_di(23) => N0,
      cfg_di(22) => N0,
      cfg_di(21) => N0,
      cfg_di(20) => N0,
      cfg_di(19) => N0,
      cfg_di(18) => N0,
      cfg_di(17) => N0,
      cfg_di(16) => N0,
      cfg_di(15) => N0,
      cfg_di(14) => N0,
      cfg_di(13) => N0,
      cfg_di(12) => N0,
      cfg_di(11) => N0,
      cfg_di(10) => N0,
      cfg_di(9) => N0,
      cfg_di(8) => N0,
      cfg_di(7) => N0,
      cfg_di(6) => N0,
      cfg_di(5) => N0,
      cfg_di(4) => N0,
      cfg_di(3) => N0,
      cfg_di(2) => N0,
      cfg_di(1) => N0,
      cfg_di(0) => N0
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ram_cmd_pb_INST_1 is
  port (
    pf_dma_rd_rdy : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    dmar : in STD_LOGIC := 'X'; 
    aclk : in STD_LOGIC := 'X'; 
    next_block : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    pf_dma_wr_rdy : out STD_LOGIC; 
    pf_repack_we : in STD_LOGIC := 'X'; 
    pf_ram_rd : in STD_LOGIC := 'X'; 
    act : in STD_LOGIC := 'X'; 
    adr_hi_wr : out STD_LOGIC; 
    pf_cb : out STD_LOGIC; 
    rdy : out STD_LOGIC; 
    flag_set : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    flag_clr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    flag_data : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end ctrl_ram_cmd_pb_INST_1;

architecture STRUCTURE of ctrl_ram_cmd_pb_INST_1 is
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal NlwRenamedSig_OI_cb : STD_LOGIC; 
  signal cb_mux0000_12381 : STD_LOGIC; 
  signal flag0_clr_0_mux0000 : STD_LOGIC; 
  signal flag0_clr_1_mux0000 : STD_LOGIC; 
  signal flag0_set_0_mux0000 : STD_LOGIC; 
  signal flag0_set_1_mux0000 : STD_LOGIC; 
  signal flag1_clr_0_or0000 : STD_LOGIC; 
  signal flag1_clr_1_or0000 : STD_LOGIC; 
  signal flag1_set_0_or0000 : STD_LOGIC; 
  signal flag1_set_1_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_dma_rd_rdy : STD_LOGIC; 
  signal pf_dma_rd_rdy_mux0001_12407 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_dma_wr_rdy : STD_LOGIC; 
  signal pf_dma_wr_rdy_mux0002_12409 : STD_LOGIC; 
  signal pf_ram_rd_z_12411 : STD_LOGIC; 
  signal pf_repack_we_z_12413 : STD_LOGIC; 
  signal NlwRenamedSig_OI_rdy : STD_LOGIC; 
  signal rdy_mux0000_12415 : STD_LOGIC; 
  signal rst_p_12421 : STD_LOGIC; 
  signal rst_p0_12422 : STD_LOGIC; 
  signal rst_p0_or0000 : STD_LOGIC; 
  signal start_rd0_12424 : STD_LOGIC; 
  signal start_rd0_and0000 : STD_LOGIC; 
  signal start_rd1_12426 : STD_LOGIC; 
  signal start_wr0_12427 : STD_LOGIC; 
  signal start_wr0_and0000 : STD_LOGIC; 
  signal start_wr1_12429 : STD_LOGIC; 
  signal stp_FSM_FFd1_12430 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_12432 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_12434 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_12436 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal stp_FSM_FFd5_12438 : STD_LOGIC; 
  signal stp_FSM_FFd5_In : STD_LOGIC; 
  signal stp_FSM_FFd6_12440 : STD_LOGIC; 
  signal stp_FSM_FFd6_In : STD_LOGIC; 
  signal stp_FSM_FFd7_12442 : STD_LOGIC; 
  signal stp_FSM_FFd7_In : STD_LOGIC; 
  signal flag0_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag0_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_flag1_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_flag1_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag2_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag2_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  pf_dma_rd_rdy <= NlwRenamedSig_OI_pf_dma_rd_rdy;
  pf_dma_wr_rdy <= NlwRenamedSig_OI_pf_dma_wr_rdy;
  pf_cb <= NlwRenamedSig_OI_cb;
  rdy <= NlwRenamedSig_OI_rdy;
  flag_set(1) <= NlwRenamedSig_OI_flag1_set(1);
  flag_set(0) <= NlwRenamedSig_OI_flag1_set(0);
  flag_clr(1) <= NlwRenamedSig_OI_flag1_clr(1);
  flag_clr(0) <= NlwRenamedSig_OI_flag1_clr(0);
  XST_GND : GND
    port map (
      G => N0
    );
  pf_dma_wr_rdy_9116 : FD
    port map (
      C => aclk,
      D => pf_dma_wr_rdy_mux0002_12409,
      Q => NlwRenamedSig_OI_pf_dma_wr_rdy
    );
  pf_ram_rd_z : FD
    port map (
      C => aclk,
      D => pf_ram_rd,
      Q => pf_ram_rd_z_12411
    );
  start_wr0 : FD
    port map (
      C => aclk,
      D => start_wr0_and0000,
      Q => start_wr0_12427
    );
  start_rd0 : FD
    port map (
      C => aclk,
      D => start_rd0_and0000,
      Q => start_rd0_12424
    );
  flag0_set_0 : FD
    port map (
      C => aclk,
      D => flag0_set_0_mux0000,
      Q => flag0_set(0)
    );
  pf_repack_we_z : FD
    port map (
      C => aclk,
      D => pf_repack_we,
      Q => pf_repack_we_z_12413
    );
  flag0_set_1 : FD
    port map (
      C => aclk,
      D => flag0_set_1_mux0000,
      Q => flag0_set(1)
    );
  flag0_clr_0 : FD
    port map (
      C => aclk,
      D => flag0_clr_0_mux0000,
      Q => flag0_clr(0)
    );
  pf_dma_rd_rdy_9124 : FD
    port map (
      C => aclk,
      D => pf_dma_rd_rdy_mux0001_12407,
      Q => NlwRenamedSig_OI_pf_dma_rd_rdy
    );
  rdy_9125 : FD
    port map (
      C => aclk,
      D => rdy_mux0000_12415,
      Q => NlwRenamedSig_OI_rdy
    );
  flag0_clr_1 : FD
    port map (
      C => aclk,
      D => flag0_clr_1_mux0000,
      Q => flag0_clr(1)
    );
  rst_p0 : FD
    port map (
      C => aclk,
      D => rst_p0_or0000,
      Q => rst_p0_12422
    );
  flag1_set_0 : FDPE
    port map (
      C => clk,
      CE => flag1_set_0_or0000,
      D => N0,
      PRE => flag0_set(0),
      Q => NlwRenamedSig_OI_flag1_set(0)
    );
  flag1_set_1 : FDPE
    port map (
      C => clk,
      CE => flag1_set_1_or0000,
      D => N0,
      PRE => flag0_set(1),
      Q => NlwRenamedSig_OI_flag1_set(1)
    );
  start_rd1 : FD
    port map (
      C => aclk,
      D => start_rd0_12424,
      Q => start_rd1_12426
    );
  start_wr1 : FD
    port map (
      C => aclk,
      D => start_wr0_12427,
      Q => start_wr1_12429
    );
  flag1_clr_1 : FDPE
    port map (
      C => clk,
      CE => flag1_clr_1_or0000,
      D => N0,
      PRE => flag0_clr(1),
      Q => NlwRenamedSig_OI_flag1_clr(1)
    );
  flag1_clr_0 : FDPE
    port map (
      C => clk,
      CE => flag1_clr_0_or0000,
      D => N0,
      PRE => flag0_clr(0),
      Q => NlwRenamedSig_OI_flag1_clr(0)
    );
  rst_p : FD
    port map (
      C => aclk,
      D => rst_p0_12422,
      Q => rst_p_12421
    );
  cb : FDR
    port map (
      C => aclk,
      D => cb_mux0000_12381,
      R => rst_p_12421,
      Q => NlwRenamedSig_OI_cb
    );
  flag2_set_0 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_set(0),
      Q => flag2_set(0)
    );
  flag2_set_1 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_set(1),
      Q => flag2_set(1)
    );
  flag2_clr_0 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_clr(0),
      Q => flag2_clr(0)
    );
  flag2_clr_1 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_clr(1),
      Q => flag2_clr(1)
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd1_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd1_12430
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd2_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd2_12432
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd3_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd3_12434
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd4_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd4_12436
    );
  stp_FSM_FFd7 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd7_In,
      S => rst_p_12421,
      Q => stp_FSM_FFd7_12442
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd5_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd5_12438
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd6_In,
      R => rst_p_12421,
      Q => stp_FSM_FFd6_12440
    );
  rst_p0_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => reg_ctrl(4),
      O => rst_p0_or0000
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => pf_repack_we_z_12413,
      I1 => stp_FSM_FFd6_12440,
      I2 => pf_repack_we,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd1_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => pf_ram_rd_z_12411,
      I1 => stp_FSM_FFd5_12438,
      I2 => pf_ram_rd,
      O => stp_FSM_FFd1_In
    );
  stp_FSM_FFd7_In1 : LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      I0 => act,
      I1 => stp_FSM_FFd7_12442,
      I2 => stp_FSM_FFd4_12436,
      I3 => stp_FSM_FFd2_12432,
      O => stp_FSM_FFd7_In
    );
  stp_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => act,
      I1 => stp_FSM_FFd2_12432,
      I2 => stp_FSM_FFd3_12434,
      I3 => stp_FSM_FFd1_12430,
      O => stp_FSM_FFd2_In
    );
  stp_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"AAAA0200"
    )
    port map (
      I0 => act,
      I1 => start_rd1_12426,
      I2 => start_wr1_12429,
      I3 => stp_FSM_FFd7_12442,
      I4 => stp_FSM_FFd4_12436,
      O => stp_FSM_FFd4_In
    );
  stp_FSM_FFd6_In1 : LUT6
    generic map(
      INIT => X"FF8A8A8A8A8A8A8A"
    )
    port map (
      I0 => stp_FSM_FFd6_12440,
      I1 => pf_repack_we,
      I2 => pf_repack_we_z_12413,
      I3 => start_rd1_12426,
      I4 => stp_FSM_FFd7_12442,
      I5 => act,
      O => stp_FSM_FFd6_In
    );
  flag1_set_1_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_set(1),
      I1 => rst_p_12421,
      O => flag1_set_1_or0000
    );
  flag1_set_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_set(0),
      I1 => rst_p_12421,
      O => flag1_set_0_or0000
    );
  flag1_clr_1_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_clr(1),
      I1 => rst_p_12421,
      O => flag1_clr_1_or0000
    );
  flag1_clr_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_clr(0),
      I1 => rst_p_12421,
      O => flag1_clr_0_or0000
    );
  rdy_mux0000_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd5_12438,
      I1 => stp_FSM_FFd6_12440,
      O => N02
    );
  rdy_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => stp_FSM_FFd4_12436,
      I1 => stp_FSM_FFd1_12430,
      I2 => NlwRenamedSig_OI_rdy,
      I3 => stp_FSM_FFd3_12434,
      I4 => N02,
      I5 => stp_FSM_FFd2_12432,
      O => rdy_mux0000_12415
    );
  adr_hi_wr_mux000011 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd5_12438,
      I1 => stp_FSM_FFd4_12436,
      I2 => stp_FSM_FFd6_12440,
      O => N7
    );
  start_rd0_and000011 : LUT3
    generic map(
      INIT => X"1B"
    )
    port map (
      I0 => NlwRenamedSig_OI_cb,
      I1 => flag_data(0),
      I2 => flag_data(1),
      O => N01
    );
  stp_FSM_FFd5_In1 : LUT4
    generic map(
      INIT => X"FAF2"
    )
    port map (
      I0 => stp_FSM_FFd5_12438,
      I1 => pf_ram_rd_z_12411,
      I2 => N61,
      I3 => pf_ram_rd,
      O => stp_FSM_FFd5_In
    );
  pf_dma_wr_rdy_mux000221 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => stp_FSM_FFd7_12442,
      I1 => start_rd1_12426,
      I2 => act,
      I3 => start_wr1_12429,
      O => N61
    );
  flag0_set_1_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => flag0_set(1),
      I1 => N7,
      I2 => stp_FSM_FFd1_12430,
      I3 => NlwRenamedSig_OI_cb,
      I4 => stp_FSM_FFd3_12434,
      O => flag0_set_1_mux0000
    );
  flag0_set_0_mux00001 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => stp_FSM_FFd3_12434,
      I1 => NlwRenamedSig_OI_cb,
      I2 => flag0_set(0),
      I3 => N7,
      I4 => stp_FSM_FFd1_12430,
      O => flag0_set_0_mux0000
    );
  flag0_clr_1_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => flag0_clr(1),
      I1 => N7,
      I2 => stp_FSM_FFd3_12434,
      I3 => NlwRenamedSig_OI_cb,
      I4 => stp_FSM_FFd1_12430,
      O => flag0_clr_1_mux0000
    );
  flag0_clr_0_mux00001 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => stp_FSM_FFd1_12430,
      I1 => NlwRenamedSig_OI_cb,
      I2 => flag0_clr(0),
      I3 => N7,
      I4 => stp_FSM_FFd3_12434,
      O => flag0_clr_0_mux0000
    );
  cb_mux0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd6_12440,
      I1 => stp_FSM_FFd4_12436,
      I2 => stp_FSM_FFd7_12442,
      O => N2
    );
  cb_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFFCFFFCBBB8"
    )
    port map (
      I0 => stp_FSM_FFd2_12432,
      I1 => NlwRenamedSig_OI_cb,
      I2 => stp_FSM_FFd1_12430,
      I3 => stp_FSM_FFd3_12434,
      I4 => stp_FSM_FFd5_12438,
      I5 => N2,
      O => cb_mux0000_12381
    );
  pf_dma_wr_rdy_mux0002_SW0 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => stp_FSM_FFd4_12436,
      I1 => stp_FSM_FFd5_12438,
      I2 => pf_ram_rd,
      I3 => stp_FSM_FFd6_12440,
      O => N4
    );
  pf_dma_wr_rdy_mux0002 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stp_FSM_FFd1_12430,
      I1 => NlwRenamedSig_OI_pf_dma_wr_rdy,
      I2 => stp_FSM_FFd2_12432,
      I3 => stp_FSM_FFd3_12434,
      I4 => N4,
      I5 => N61,
      O => pf_dma_wr_rdy_mux0002_12409
    );
  pf_dma_rd_rdy_mux0001_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
    port map (
      I0 => stp_FSM_FFd5_12438,
      I1 => stp_FSM_FFd2_12432,
      I2 => stp_FSM_FFd6_12440,
      I3 => pf_repack_we_z_12413,
      I4 => stp_FSM_FFd4_12436,
      I5 => stp_FSM_FFd3_12434,
      O => N6
    );
  pf_dma_rd_rdy_mux0001 : LUT6
    generic map(
      INIT => X"FCCCCCCCF8888888"
    )
    port map (
      I0 => stp_FSM_FFd1_12430,
      I1 => NlwRenamedSig_OI_pf_dma_rd_rdy,
      I2 => act,
      I3 => stp_FSM_FFd7_12442,
      I4 => start_rd1_12426,
      I5 => N6,
      O => pf_dma_rd_rdy_mux0001_12407
    );
  start_wr0_and00001 : LUT5
    generic map(
      INIT => X"000C0004"
    )
    port map (
      I0 => reg_ctrl(1),
      I1 => reg_ctrl(0),
      I2 => N01,
      I3 => reg_ctrl(2),
      I4 => dmar,
      O => start_wr0_and0000
    );
  start_rd0_and00001 : LUT5
    generic map(
      INIT => X"80800080"
    )
    port map (
      I0 => N01,
      I1 => reg_ctrl(0),
      I2 => reg_ctrl(2),
      I3 => reg_ctrl(1),
      I4 => dmar,
      O => start_rd0_and0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ram_cmd_pb is
  port (
    pf_dma_rd_rdy : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    dmar : in STD_LOGIC := 'X'; 
    aclk : in STD_LOGIC := 'X'; 
    next_block : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    pf_dma_wr_rdy : out STD_LOGIC; 
    pf_repack_we : in STD_LOGIC := 'X'; 
    pf_ram_rd : in STD_LOGIC := 'X'; 
    act : in STD_LOGIC := 'X'; 
    adr_hi_wr : out STD_LOGIC; 
    pf_cb : out STD_LOGIC; 
    rdy : out STD_LOGIC; 
    flag_set : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    flag_clr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    flag_data : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end ctrl_ram_cmd_pb;

architecture STRUCTURE of ctrl_ram_cmd_pb is
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal NlwRenamedSig_OI_cb : STD_LOGIC; 
  signal cb_mux0000_12307 : STD_LOGIC; 
  signal flag0_clr_0_mux0000 : STD_LOGIC; 
  signal flag0_clr_1_mux0000 : STD_LOGIC; 
  signal flag0_set_0_mux0000 : STD_LOGIC; 
  signal flag0_set_1_mux0000 : STD_LOGIC; 
  signal flag1_clr_0_or0000 : STD_LOGIC; 
  signal flag1_clr_1_or0000 : STD_LOGIC; 
  signal flag1_set_0_or0000 : STD_LOGIC; 
  signal flag1_set_1_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_dma_rd_rdy : STD_LOGIC; 
  signal pf_dma_rd_rdy_mux0001_12333 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_dma_wr_rdy : STD_LOGIC; 
  signal pf_dma_wr_rdy_mux0002_12335 : STD_LOGIC; 
  signal pf_ram_rd_z_12337 : STD_LOGIC; 
  signal pf_repack_we_z_12339 : STD_LOGIC; 
  signal NlwRenamedSig_OI_rdy : STD_LOGIC; 
  signal rdy_mux0000_12341 : STD_LOGIC; 
  signal rst_p_12347 : STD_LOGIC; 
  signal rst_p0_12348 : STD_LOGIC; 
  signal rst_p0_or0000 : STD_LOGIC; 
  signal start_rd0_12350 : STD_LOGIC; 
  signal start_rd0_and0000 : STD_LOGIC; 
  signal start_rd1_12352 : STD_LOGIC; 
  signal start_wr0_12353 : STD_LOGIC; 
  signal start_wr0_and0000 : STD_LOGIC; 
  signal start_wr1_12355 : STD_LOGIC; 
  signal stp_FSM_FFd1_12356 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_12358 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_12360 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_12362 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal stp_FSM_FFd5_12364 : STD_LOGIC; 
  signal stp_FSM_FFd5_In : STD_LOGIC; 
  signal stp_FSM_FFd6_12366 : STD_LOGIC; 
  signal stp_FSM_FFd6_In : STD_LOGIC; 
  signal stp_FSM_FFd7_12368 : STD_LOGIC; 
  signal stp_FSM_FFd7_In : STD_LOGIC; 
  signal flag0_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag0_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_flag1_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_flag1_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag2_clr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal flag2_set : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  pf_dma_rd_rdy <= NlwRenamedSig_OI_pf_dma_rd_rdy;
  pf_dma_wr_rdy <= NlwRenamedSig_OI_pf_dma_wr_rdy;
  pf_cb <= NlwRenamedSig_OI_cb;
  rdy <= NlwRenamedSig_OI_rdy;
  flag_set(1) <= NlwRenamedSig_OI_flag1_set(1);
  flag_set(0) <= NlwRenamedSig_OI_flag1_set(0);
  flag_clr(1) <= NlwRenamedSig_OI_flag1_clr(1);
  flag_clr(0) <= NlwRenamedSig_OI_flag1_clr(0);
  XST_GND : GND
    port map (
      G => N0
    );
  pf_dma_wr_rdy_9054 : FD
    port map (
      C => aclk,
      D => pf_dma_wr_rdy_mux0002_12335,
      Q => NlwRenamedSig_OI_pf_dma_wr_rdy
    );
  pf_ram_rd_z : FD
    port map (
      C => aclk,
      D => pf_ram_rd,
      Q => pf_ram_rd_z_12337
    );
  start_wr0 : FD
    port map (
      C => aclk,
      D => start_wr0_and0000,
      Q => start_wr0_12353
    );
  start_rd0 : FD
    port map (
      C => aclk,
      D => start_rd0_and0000,
      Q => start_rd0_12350
    );
  flag0_set_0 : FD
    port map (
      C => aclk,
      D => flag0_set_0_mux0000,
      Q => flag0_set(0)
    );
  pf_repack_we_z : FD
    port map (
      C => aclk,
      D => pf_repack_we,
      Q => pf_repack_we_z_12339
    );
  flag0_set_1 : FD
    port map (
      C => aclk,
      D => flag0_set_1_mux0000,
      Q => flag0_set(1)
    );
  flag0_clr_0 : FD
    port map (
      C => aclk,
      D => flag0_clr_0_mux0000,
      Q => flag0_clr(0)
    );
  pf_dma_rd_rdy_9062 : FD
    port map (
      C => aclk,
      D => pf_dma_rd_rdy_mux0001_12333,
      Q => NlwRenamedSig_OI_pf_dma_rd_rdy
    );
  rdy_9063 : FD
    port map (
      C => aclk,
      D => rdy_mux0000_12341,
      Q => NlwRenamedSig_OI_rdy
    );
  flag0_clr_1 : FD
    port map (
      C => aclk,
      D => flag0_clr_1_mux0000,
      Q => flag0_clr(1)
    );
  rst_p0 : FD
    port map (
      C => aclk,
      D => rst_p0_or0000,
      Q => rst_p0_12348
    );
  flag1_set_0 : FDPE
    port map (
      C => clk,
      CE => flag1_set_0_or0000,
      D => N0,
      PRE => flag0_set(0),
      Q => NlwRenamedSig_OI_flag1_set(0)
    );
  flag1_set_1 : FDPE
    port map (
      C => clk,
      CE => flag1_set_1_or0000,
      D => N0,
      PRE => flag0_set(1),
      Q => NlwRenamedSig_OI_flag1_set(1)
    );
  start_rd1 : FD
    port map (
      C => aclk,
      D => start_rd0_12350,
      Q => start_rd1_12352
    );
  start_wr1 : FD
    port map (
      C => aclk,
      D => start_wr0_12353,
      Q => start_wr1_12355
    );
  flag1_clr_1 : FDPE
    port map (
      C => clk,
      CE => flag1_clr_1_or0000,
      D => N0,
      PRE => flag0_clr(1),
      Q => NlwRenamedSig_OI_flag1_clr(1)
    );
  flag1_clr_0 : FDPE
    port map (
      C => clk,
      CE => flag1_clr_0_or0000,
      D => N0,
      PRE => flag0_clr(0),
      Q => NlwRenamedSig_OI_flag1_clr(0)
    );
  rst_p : FD
    port map (
      C => aclk,
      D => rst_p0_12348,
      Q => rst_p_12347
    );
  cb : FDR
    port map (
      C => aclk,
      D => cb_mux0000_12307,
      R => rst_p_12347,
      Q => NlwRenamedSig_OI_cb
    );
  flag2_set_0 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_set(0),
      Q => flag2_set(0)
    );
  flag2_set_1 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_set(1),
      Q => flag2_set(1)
    );
  flag2_clr_0 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_clr(0),
      Q => flag2_clr(0)
    );
  flag2_clr_1 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_flag1_clr(1),
      Q => flag2_clr(1)
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd1_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd1_12356
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd2_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd2_12358
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd3_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd3_12360
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd4_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd4_12362
    );
  stp_FSM_FFd7 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd7_In,
      S => rst_p_12347,
      Q => stp_FSM_FFd7_12368
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd5_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd5_12364
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd6_In,
      R => rst_p_12347,
      Q => stp_FSM_FFd6_12366
    );
  rst_p0_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => reg_ctrl(4),
      O => rst_p0_or0000
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => pf_repack_we_z_12339,
      I1 => stp_FSM_FFd6_12366,
      I2 => pf_repack_we,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd1_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => pf_ram_rd_z_12337,
      I1 => stp_FSM_FFd5_12364,
      I2 => pf_ram_rd,
      O => stp_FSM_FFd1_In
    );
  stp_FSM_FFd7_In1 : LUT4
    generic map(
      INIT => X"5554"
    )
    port map (
      I0 => act,
      I1 => stp_FSM_FFd7_12368,
      I2 => stp_FSM_FFd4_12362,
      I3 => stp_FSM_FFd2_12358,
      O => stp_FSM_FFd7_In
    );
  stp_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => act,
      I1 => stp_FSM_FFd2_12358,
      I2 => stp_FSM_FFd3_12360,
      I3 => stp_FSM_FFd1_12356,
      O => stp_FSM_FFd2_In
    );
  stp_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"AAAA0200"
    )
    port map (
      I0 => act,
      I1 => start_rd1_12352,
      I2 => start_wr1_12355,
      I3 => stp_FSM_FFd7_12368,
      I4 => stp_FSM_FFd4_12362,
      O => stp_FSM_FFd4_In
    );
  stp_FSM_FFd6_In1 : LUT6
    generic map(
      INIT => X"FF8A8A8A8A8A8A8A"
    )
    port map (
      I0 => stp_FSM_FFd6_12366,
      I1 => pf_repack_we,
      I2 => pf_repack_we_z_12339,
      I3 => start_rd1_12352,
      I4 => stp_FSM_FFd7_12368,
      I5 => act,
      O => stp_FSM_FFd6_In
    );
  flag1_set_1_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_set(1),
      I1 => rst_p_12347,
      O => flag1_set_1_or0000
    );
  flag1_set_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_set(0),
      I1 => rst_p_12347,
      O => flag1_set_0_or0000
    );
  flag1_clr_1_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_clr(1),
      I1 => rst_p_12347,
      O => flag1_clr_1_or0000
    );
  flag1_clr_0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => flag2_clr(0),
      I1 => rst_p_12347,
      O => flag1_clr_0_or0000
    );
  rdy_mux0000_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd5_12364,
      I1 => stp_FSM_FFd6_12366,
      O => N02
    );
  rdy_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => stp_FSM_FFd4_12362,
      I1 => stp_FSM_FFd1_12356,
      I2 => NlwRenamedSig_OI_rdy,
      I3 => stp_FSM_FFd3_12360,
      I4 => N02,
      I5 => stp_FSM_FFd2_12358,
      O => rdy_mux0000_12341
    );
  adr_hi_wr_mux000011 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd5_12364,
      I1 => stp_FSM_FFd4_12362,
      I2 => stp_FSM_FFd6_12366,
      O => N7
    );
  start_rd0_and000011 : LUT3
    generic map(
      INIT => X"1B"
    )
    port map (
      I0 => NlwRenamedSig_OI_cb,
      I1 => flag_data(0),
      I2 => flag_data(1),
      O => N01
    );
  stp_FSM_FFd5_In1 : LUT4
    generic map(
      INIT => X"FAF2"
    )
    port map (
      I0 => stp_FSM_FFd5_12364,
      I1 => pf_ram_rd_z_12337,
      I2 => N61,
      I3 => pf_ram_rd,
      O => stp_FSM_FFd5_In
    );
  pf_dma_wr_rdy_mux000221 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => stp_FSM_FFd7_12368,
      I1 => start_rd1_12352,
      I2 => act,
      I3 => start_wr1_12355,
      O => N61
    );
  flag0_set_1_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => flag0_set(1),
      I1 => N7,
      I2 => stp_FSM_FFd1_12356,
      I3 => NlwRenamedSig_OI_cb,
      I4 => stp_FSM_FFd3_12360,
      O => flag0_set_1_mux0000
    );
  flag0_set_0_mux00001 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => stp_FSM_FFd3_12360,
      I1 => NlwRenamedSig_OI_cb,
      I2 => flag0_set(0),
      I3 => N7,
      I4 => stp_FSM_FFd1_12356,
      O => flag0_set_0_mux0000
    );
  flag0_clr_1_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => flag0_clr(1),
      I1 => N7,
      I2 => stp_FSM_FFd3_12360,
      I3 => NlwRenamedSig_OI_cb,
      I4 => stp_FSM_FFd1_12356,
      O => flag0_clr_1_mux0000
    );
  flag0_clr_0_mux00001 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => stp_FSM_FFd1_12356,
      I1 => NlwRenamedSig_OI_cb,
      I2 => flag0_clr(0),
      I3 => N7,
      I4 => stp_FSM_FFd3_12360,
      O => flag0_clr_0_mux0000
    );
  cb_mux0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd6_12366,
      I1 => stp_FSM_FFd4_12362,
      I2 => stp_FSM_FFd7_12368,
      O => N2
    );
  cb_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFFCFFFCBBB8"
    )
    port map (
      I0 => stp_FSM_FFd2_12358,
      I1 => NlwRenamedSig_OI_cb,
      I2 => stp_FSM_FFd1_12356,
      I3 => stp_FSM_FFd3_12360,
      I4 => stp_FSM_FFd5_12364,
      I5 => N2,
      O => cb_mux0000_12307
    );
  pf_dma_wr_rdy_mux0002_SW0 : LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      I0 => stp_FSM_FFd4_12362,
      I1 => stp_FSM_FFd5_12364,
      I2 => pf_ram_rd,
      I3 => stp_FSM_FFd6_12366,
      O => N4
    );
  pf_dma_wr_rdy_mux0002 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stp_FSM_FFd1_12356,
      I1 => NlwRenamedSig_OI_pf_dma_wr_rdy,
      I2 => stp_FSM_FFd2_12358,
      I3 => stp_FSM_FFd3_12360,
      I4 => N4,
      I5 => N61,
      O => pf_dma_wr_rdy_mux0002_12335
    );
  pf_dma_rd_rdy_mux0001_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEFE"
    )
    port map (
      I0 => stp_FSM_FFd5_12364,
      I1 => stp_FSM_FFd2_12358,
      I2 => stp_FSM_FFd6_12366,
      I3 => pf_repack_we_z_12339,
      I4 => stp_FSM_FFd4_12362,
      I5 => stp_FSM_FFd3_12360,
      O => N6
    );
  pf_dma_rd_rdy_mux0001 : LUT6
    generic map(
      INIT => X"FCCCCCCCF8888888"
    )
    port map (
      I0 => stp_FSM_FFd1_12356,
      I1 => NlwRenamedSig_OI_pf_dma_rd_rdy,
      I2 => act,
      I3 => stp_FSM_FFd7_12368,
      I4 => start_rd1_12352,
      I5 => N6,
      O => pf_dma_rd_rdy_mux0001_12333
    );
  start_wr0_and00001 : LUT5
    generic map(
      INIT => X"000C0004"
    )
    port map (
      I0 => reg_ctrl(1),
      I1 => reg_ctrl(0),
      I2 => N01,
      I3 => reg_ctrl(2),
      I4 => dmar,
      O => start_wr0_and0000
    );
  start_rd0_and00001 : LUT5
    generic map(
      INIT => X"80800080"
    )
    port map (
      I0 => N01,
      I1 => reg_ctrl(0),
      I2 => reg_ctrl(2),
      I3 => reg_ctrl(1),
      I4 => dmar,
      O => start_rd0_and0000
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ram_cmd is
  port (
    clk : in STD_LOGIC := 'X'; 
    dma1_transfer_rdy : out STD_LOGIC; 
    allow_wr : in STD_LOGIC := 'X'; 
    aclk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    pf_repack_we : in STD_LOGIC := 'X'; 
    reg_write_E0 : in STD_LOGIC := 'X'; 
    pf_ram_rd_out : out STD_LOGIC; 
    dma0_transfer_rdy : out STD_LOGIC; 
    request_rd : out STD_LOGIC; 
    ram_adra_a9 : out STD_LOGIC; 
    request_wr : out STD_LOGIC; 
    dmar0 : in STD_LOGIC := 'X'; 
    dmar1 : in STD_LOGIC := 'X'; 
    dma_chn : in STD_LOGIC := 'X'; 
    ram_adrb : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
    reg_ch0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    reg_ch1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end ctrl_ram_cmd;

architecture STRUCTURE of ctrl_ram_cmd is
  component ctrl_ram_cmd_pb
    port (
      pf_dma_rd_rdy : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      dmar : in STD_LOGIC := 'X'; 
      aclk : in STD_LOGIC := 'X'; 
      next_block : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      pf_dma_wr_rdy : out STD_LOGIC; 
      pf_repack_we : in STD_LOGIC := 'X'; 
      pf_ram_rd : in STD_LOGIC := 'X'; 
      act : in STD_LOGIC := 'X'; 
      adr_hi_wr : out STD_LOGIC; 
      pf_cb : out STD_LOGIC; 
      rdy : out STD_LOGIC; 
      flag_set : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      flag_clr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      flag_data : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  component ctrl_ram_cmd_pb_INST_1
    port (
      pf_dma_rd_rdy : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      dmar : in STD_LOGIC := 'X'; 
      aclk : in STD_LOGIC := 'X'; 
      next_block : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      pf_dma_wr_rdy : out STD_LOGIC; 
      pf_repack_we : in STD_LOGIC := 'X'; 
      pf_ram_rd : in STD_LOGIC := 'X'; 
      act : in STD_LOGIC := 'X'; 
      adr_hi_wr : out STD_LOGIC; 
      pf_cb : out STD_LOGIC; 
      rdy : out STD_LOGIC; 
      flag_set : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      flag_clr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      flag_data : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal Q_mux0000 : STD_LOGIC; 
  signal carry : STD_LOGIC; 
  signal ch0_next_block : STD_LOGIC; 
  signal cnt_rstp_12451 : STD_LOGIC; 
  signal flag_data_0_or0000 : STD_LOGIC; 
  signal flag_data_0_or0001 : STD_LOGIC; 
  signal flag_data_1_or0000 : STD_LOGIC; 
  signal flag_data_1_or0001 : STD_LOGIC; 
  signal flag_data_2_or0000 : STD_LOGIC; 
  signal flag_data_2_or0001 : STD_LOGIC; 
  signal flag_data_3_or0000 : STD_LOGIC; 
  signal flag_data_3_or0001 : STD_LOGIC; 
  signal pb_current_block_0_and0000 : STD_LOGIC; 
  signal pb_current_block_0_not0001 : STD_LOGIC; 
  signal pb_current_block_1_and0000 : STD_LOGIC; 
  signal pb_current_block_1_not0001 : STD_LOGIC; 
  signal pb_flag_clr_0_or0000 : STD_LOGIC; 
  signal pb_flag_clr_1_or0000 : STD_LOGIC; 
  signal pb_flag_clr_2_or0000 : STD_LOGIC; 
  signal pb_flag_clr_3_or0000 : STD_LOGIC; 
  signal pb_flag_set_0_and0000 : STD_LOGIC; 
  signal pb_flag_set_1_and0000 : STD_LOGIC; 
  signal pb_flag_set_2_and0000 : STD_LOGIC; 
  signal pb_flag_set_3_and0000 : STD_LOGIC; 
  signal pf0_act_12490 : STD_LOGIC; 
  signal pf0_act_mux0000 : STD_LOGIC; 
  signal pf0_cb : STD_LOGIC; 
  signal pf0_dma_rd_rdy : STD_LOGIC; 
  signal pf0_dma_wr_rdy : STD_LOGIC; 
  signal pf0_rdy : STD_LOGIC; 
  signal pf1_act_12496 : STD_LOGIC; 
  signal pf1_act_mux0000 : STD_LOGIC; 
  signal pf1_cb : STD_LOGIC; 
  signal pf1_dma_rd_rdy : STD_LOGIC; 
  signal pf1_dma_wr_rdy : STD_LOGIC; 
  signal pf1_rdy : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_chn : STD_LOGIC; 
  signal pf_chn_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pf_ram_rd : STD_LOGIC; 
  signal pf_ram_rd_and0000 : STD_LOGIC; 
  signal pf_ram_rd_or0000_12514 : STD_LOGIC; 
  signal ram0_transfer_rdy_12555 : STD_LOGIC; 
  signal ram0_transfer_rdy_mux0002 : STD_LOGIC; 
  signal ram1_transfer_rdy_12557 : STD_LOGIC; 
  signal ram1_transfer_rdy_mux0002 : STD_LOGIC; 
  signal reg_write_E0_z_12587 : STD_LOGIC; 
  signal reg_write_E0_z1_12588 : STD_LOGIC; 
  signal rst_p_12592 : STD_LOGIC; 
  signal rst_p0_12593 : STD_LOGIC; 
  signal stp_FSM_FFd1_12594 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_12596 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_12598 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_12600 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal NLW_cmd0_adr_hi_wr_UNCONNECTED : STD_LOGIC; 
  signal NLW_cmd1_adr_hi_wr_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PATTERNDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_OVERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_UNDERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYCASCIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_MULTSIGNIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_0_UNCONNECTED : STD_LOGIC; 
  signal flag_data : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal opmode : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal pb_current_block : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal pb_flag_clr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal pb_flag_set : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal pf_flag_clr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal pf_flag_set : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal port_p : STD_LOGIC_VECTOR ( 47 downto 9 ); 
  signal NlwRenamedSig_OI_ram_adrb : STD_LOGIC_VECTOR ( 8 downto 0 ); 
begin
  dma1_transfer_rdy <= ram1_transfer_rdy_12557;
  pf_ram_rd_out <= NlwRenamedSig_OI_pf_ram_rd;
  dma0_transfer_rdy <= ram0_transfer_rdy_12555;
  ram_adrb(10) <= NlwRenamedSig_OI_pf_chn;
  ram_adrb(8) <= NlwRenamedSig_OI_ram_adrb(8);
  ram_adrb(7) <= NlwRenamedSig_OI_ram_adrb(7);
  ram_adrb(6) <= NlwRenamedSig_OI_ram_adrb(6);
  ram_adrb(5) <= NlwRenamedSig_OI_ram_adrb(5);
  ram_adrb(4) <= NlwRenamedSig_OI_ram_adrb(4);
  ram_adrb(3) <= NlwRenamedSig_OI_ram_adrb(3);
  ram_adrb(2) <= NlwRenamedSig_OI_ram_adrb(2);
  ram_adrb(1) <= NlwRenamedSig_OI_ram_adrb(1);
  ram_adrb(0) <= NlwRenamedSig_OI_ram_adrb(0);
  XST_GND : GND
    port map (
      G => opmode(0)
    );
  XST_VCC : VCC
    port map (
      P => ch0_next_block
    );
  pb_current_block_1 : FDRE
    port map (
      C => clk,
      CE => pb_current_block_1_and0000,
      D => pb_current_block_1_not0001,
      R => reg_ch1_ctrl(4),
      Q => pb_current_block(1)
    );
  pb_flag_set_3 : FD
    port map (
      C => clk,
      D => pb_flag_set_3_and0000,
      Q => pb_flag_set(3)
    );
  pf_ram_rd : FDRE
    port map (
      C => aclk,
      CE => pf_ram_rd_and0000,
      D => ch0_next_block,
      R => pf_ram_rd_or0000_12514,
      Q => NlwRenamedSig_OI_pf_ram_rd
    );
  pb_flag_clr_0 : FD
    port map (
      C => clk,
      D => pb_flag_clr_0_or0000,
      Q => pb_flag_clr(0)
    );
  pb_flag_clr_1 : FD
    port map (
      C => clk,
      D => pb_flag_clr_1_or0000,
      Q => pb_flag_clr(1)
    );
  reg_write_E0_z : FD
    port map (
      C => clk,
      D => reg_write_E0,
      Q => reg_write_E0_z_12587
    );
  pb_flag_clr_2 : FD
    port map (
      C => clk,
      D => pb_flag_clr_2_or0000,
      Q => pb_flag_clr(2)
    );
  flag_data_1 : FDRE
    port map (
      C => clk,
      CE => flag_data_1_or0001,
      D => ch0_next_block,
      R => flag_data_1_or0000,
      Q => flag_data(1)
    );
  flag_data_0 : FDRE
    port map (
      C => clk,
      CE => flag_data_0_or0001,
      D => ch0_next_block,
      R => flag_data_0_or0000,
      Q => flag_data(0)
    );
  pb_flag_clr_3 : FD
    port map (
      C => clk,
      D => pb_flag_clr_3_or0000,
      Q => pb_flag_clr(3)
    );
  flag_data_2 : FDRE
    port map (
      C => clk,
      CE => flag_data_2_or0001,
      D => ch0_next_block,
      R => flag_data_2_or0000,
      Q => flag_data(2)
    );
  flag_data_3 : FDRE
    port map (
      C => clk,
      CE => flag_data_3_or0001,
      D => ch0_next_block,
      R => flag_data_3_or0000,
      Q => flag_data(3)
    );
  pf_chn : FD
    port map (
      C => aclk,
      D => pf_chn_mux0000,
      Q => NlwRenamedSig_OI_pf_chn
    );
  ram0_transfer_rdy : FD
    port map (
      C => clk,
      D => ram0_transfer_rdy_mux0002,
      Q => ram0_transfer_rdy_12555
    );
  ram1_transfer_rdy : FD
    port map (
      C => clk,
      D => ram1_transfer_rdy_mux0002,
      Q => ram1_transfer_rdy_12557
    );
  pf1_act : FD
    port map (
      C => aclk,
      D => pf1_act_mux0000,
      Q => pf1_act_12496
    );
  pb_flag_set_0 : FD
    port map (
      C => clk,
      D => pb_flag_set_0_and0000,
      Q => pb_flag_set(0)
    );
  pb_flag_set_1 : FD
    port map (
      C => clk,
      D => pb_flag_set_1_and0000,
      Q => pb_flag_set(1)
    );
  rst_p0 : FDR
    port map (
      C => aclk,
      D => ch0_next_block,
      R => reset,
      Q => rst_p0_12593
    );
  pb_current_block_0 : FDRE
    port map (
      C => clk,
      CE => pb_current_block_0_and0000,
      D => pb_current_block_0_not0001,
      R => reg_ch0_ctrl(4),
      Q => pb_current_block(0)
    );
  pb_flag_set_2 : FD
    port map (
      C => clk,
      D => pb_flag_set_2_and0000,
      Q => pb_flag_set(2)
    );
  reg_write_E0_z1 : FD
    port map (
      C => clk,
      D => reg_write_E0_z_12587,
      Q => reg_write_E0_z1_12588
    );
  rst_p : FD
    port map (
      C => aclk,
      D => rst_p0_12593,
      Q => rst_p_12592
    );
  pf0_act : FDR
    port map (
      C => aclk,
      D => pf0_act_mux0000,
      R => rst_p_12592,
      Q => pf0_act_12490
    );
  cnt_rstp : FDS
    port map (
      C => aclk,
      D => Q_mux0000,
      S => rst_p_12592,
      Q => cnt_rstp_12451
    );
  gen_dsp48_dsp : DSP48E
    generic map(
      AREG => 1,
      ACASCREG => 1,
      BREG => 1,
      BCASCREG => 1,
      B_INPUT => "DIRECT",
      CARRYINREG => 0,
      CARRYINSELREG => 1,
      CREG => 1,
      USE_MULT => "NONE",
      MREG => 1,
      OPMODEREG => 1,
      PREG => 1,
      ALUMODEREG => 0,
      MULTCARRYINREG => 1,
      A_INPUT => "DIRECT",
      USE_SIMD => "ONE48",
      USE_PATTERN_DETECT => "NO_PATDET",
      PATTERN => X"000000000000",
      SEL_PATTERN => "PATTERN",
      SEL_MASK => "MASK",
      SEL_ROUNDING_MASK => "SEL_MASK",
      AUTORESET_PATTERN_DETECT => FALSE,
      AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
      MASK => X"3FFFFFFFFFFF"
    )
    port map (
      CARRYIN => carry,
      CEA1 => ch0_next_block,
      CEA2 => ch0_next_block,
      CEB1 => ch0_next_block,
      CEB2 => ch0_next_block,
      CEC => ch0_next_block,
      CECTRL => ch0_next_block,
      CEP => ch0_next_block,
      CEM => ch0_next_block,
      CECARRYIN => ch0_next_block,
      CEMULTCARRYIN => ch0_next_block,
      CLK => aclk,
      RSTA => opmode(0),
      RSTB => opmode(0),
      RSTC => opmode(0),
      RSTCTRL => opmode(0),
      RSTP => cnt_rstp_12451,
      RSTM => opmode(0),
      RSTALLCARRYIN => opmode(0),
      CEALUMODE => ch0_next_block,
      RSTALUMODE => opmode(0),
      PATTERNBDETECT => NLW_gen_dsp48_dsp_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_gen_dsp48_dsp_PATTERNDETECT_UNCONNECTED,
      OVERFLOW => NLW_gen_dsp48_dsp_OVERFLOW_UNCONNECTED,
      UNDERFLOW => NLW_gen_dsp48_dsp_UNDERFLOW_UNCONNECTED,
      CARRYCASCIN => NLW_gen_dsp48_dsp_CARRYCASCIN_UNCONNECTED,
      CARRYCASCOUT => NLW_gen_dsp48_dsp_CARRYCASCOUT_UNCONNECTED,
      MULTSIGNIN => NLW_gen_dsp48_dsp_MULTSIGNIN_UNCONNECTED,
      MULTSIGNOUT => NLW_gen_dsp48_dsp_MULTSIGNOUT_UNCONNECTED,
      A(29) => opmode(0),
      A(28) => opmode(0),
      A(27) => opmode(0),
      A(26) => opmode(0),
      A(25) => opmode(0),
      A(24) => opmode(0),
      A(23) => opmode(0),
      A(22) => opmode(0),
      A(21) => opmode(0),
      A(20) => opmode(0),
      A(19) => opmode(0),
      A(18) => opmode(0),
      A(17) => opmode(0),
      A(16) => opmode(0),
      A(15) => opmode(0),
      A(14) => opmode(0),
      A(13) => opmode(0),
      A(12) => opmode(0),
      A(11) => opmode(0),
      A(10) => opmode(0),
      A(9) => opmode(0),
      A(8) => opmode(0),
      A(7) => opmode(0),
      A(6) => opmode(0),
      A(5) => opmode(0),
      A(4) => opmode(0),
      A(3) => opmode(0),
      A(2) => opmode(0),
      A(1) => opmode(0),
      A(0) => opmode(0),
      PCIN(47) => opmode(0),
      PCIN(46) => opmode(0),
      PCIN(45) => opmode(0),
      PCIN(44) => opmode(0),
      PCIN(43) => opmode(0),
      PCIN(42) => opmode(0),
      PCIN(41) => opmode(0),
      PCIN(40) => opmode(0),
      PCIN(39) => opmode(0),
      PCIN(38) => opmode(0),
      PCIN(37) => opmode(0),
      PCIN(36) => opmode(0),
      PCIN(35) => opmode(0),
      PCIN(34) => opmode(0),
      PCIN(33) => opmode(0),
      PCIN(32) => opmode(0),
      PCIN(31) => opmode(0),
      PCIN(30) => opmode(0),
      PCIN(29) => opmode(0),
      PCIN(28) => opmode(0),
      PCIN(27) => opmode(0),
      PCIN(26) => opmode(0),
      PCIN(25) => opmode(0),
      PCIN(24) => opmode(0),
      PCIN(23) => opmode(0),
      PCIN(22) => opmode(0),
      PCIN(21) => opmode(0),
      PCIN(20) => opmode(0),
      PCIN(19) => opmode(0),
      PCIN(18) => opmode(0),
      PCIN(17) => opmode(0),
      PCIN(16) => opmode(0),
      PCIN(15) => opmode(0),
      PCIN(14) => opmode(0),
      PCIN(13) => opmode(0),
      PCIN(12) => opmode(0),
      PCIN(11) => opmode(0),
      PCIN(10) => opmode(0),
      PCIN(9) => opmode(0),
      PCIN(8) => opmode(0),
      PCIN(7) => opmode(0),
      PCIN(6) => opmode(0),
      PCIN(5) => opmode(0),
      PCIN(4) => opmode(0),
      PCIN(3) => opmode(0),
      PCIN(2) => opmode(0),
      PCIN(1) => opmode(0),
      PCIN(0) => opmode(0),
      B(17) => opmode(0),
      B(16) => opmode(0),
      B(15) => opmode(0),
      B(14) => opmode(0),
      B(13) => opmode(0),
      B(12) => opmode(0),
      B(11) => opmode(0),
      B(10) => opmode(0),
      B(9) => opmode(0),
      B(8) => opmode(0),
      B(7) => opmode(0),
      B(6) => opmode(0),
      B(5) => opmode(0),
      B(4) => opmode(0),
      B(3) => opmode(0),
      B(2) => opmode(0),
      B(1) => opmode(0),
      B(0) => opmode(0),
      C(47) => port_p(47),
      C(46) => port_p(46),
      C(45) => port_p(45),
      C(44) => port_p(44),
      C(43) => port_p(43),
      C(42) => port_p(42),
      C(41) => port_p(41),
      C(40) => port_p(40),
      C(39) => port_p(39),
      C(38) => port_p(38),
      C(37) => port_p(37),
      C(36) => port_p(36),
      C(35) => port_p(35),
      C(34) => port_p(34),
      C(33) => port_p(33),
      C(32) => port_p(32),
      C(31) => port_p(31),
      C(30) => port_p(30),
      C(29) => port_p(29),
      C(28) => port_p(28),
      C(27) => port_p(27),
      C(26) => port_p(26),
      C(25) => port_p(25),
      C(24) => port_p(24),
      C(23) => port_p(23),
      C(22) => port_p(22),
      C(21) => port_p(21),
      C(20) => port_p(20),
      C(19) => port_p(19),
      C(18) => port_p(18),
      C(17) => port_p(17),
      C(16) => port_p(16),
      C(15) => port_p(15),
      C(14) => port_p(14),
      C(13) => port_p(13),
      C(12) => port_p(12),
      C(11) => port_p(11),
      C(10) => port_p(10),
      C(9) => port_p(9),
      C(8) => NlwRenamedSig_OI_ram_adrb(8),
      C(7) => NlwRenamedSig_OI_ram_adrb(7),
      C(6) => NlwRenamedSig_OI_ram_adrb(6),
      C(5) => NlwRenamedSig_OI_ram_adrb(5),
      C(4) => NlwRenamedSig_OI_ram_adrb(4),
      C(3) => NlwRenamedSig_OI_ram_adrb(3),
      C(2) => NlwRenamedSig_OI_ram_adrb(2),
      C(1) => NlwRenamedSig_OI_ram_adrb(1),
      C(0) => NlwRenamedSig_OI_ram_adrb(0),
      CARRYINSEL(2) => opmode(0),
      CARRYINSEL(1) => opmode(0),
      CARRYINSEL(0) => opmode(0),
      OPMODE(6) => opmode(0),
      OPMODE(5) => ch0_next_block,
      OPMODE(4) => opmode(0),
      OPMODE(3) => opmode(0),
      OPMODE(2) => opmode(0),
      OPMODE(1) => opmode(0),
      OPMODE(0) => opmode(0),
      BCIN(17) => opmode(0),
      BCIN(16) => opmode(0),
      BCIN(15) => opmode(0),
      BCIN(14) => opmode(0),
      BCIN(13) => opmode(0),
      BCIN(12) => opmode(0),
      BCIN(11) => opmode(0),
      BCIN(10) => opmode(0),
      BCIN(9) => opmode(0),
      BCIN(8) => opmode(0),
      BCIN(7) => opmode(0),
      BCIN(6) => opmode(0),
      BCIN(5) => opmode(0),
      BCIN(4) => opmode(0),
      BCIN(3) => opmode(0),
      BCIN(2) => opmode(0),
      BCIN(1) => opmode(0),
      BCIN(0) => opmode(0),
      ALUMODE(3) => opmode(0),
      ALUMODE(2) => opmode(0),
      ALUMODE(1) => opmode(0),
      ALUMODE(0) => opmode(0),
      PCOUT(47) => NLW_gen_dsp48_dsp_PCOUT_47_UNCONNECTED,
      PCOUT(46) => NLW_gen_dsp48_dsp_PCOUT_46_UNCONNECTED,
      PCOUT(45) => NLW_gen_dsp48_dsp_PCOUT_45_UNCONNECTED,
      PCOUT(44) => NLW_gen_dsp48_dsp_PCOUT_44_UNCONNECTED,
      PCOUT(43) => NLW_gen_dsp48_dsp_PCOUT_43_UNCONNECTED,
      PCOUT(42) => NLW_gen_dsp48_dsp_PCOUT_42_UNCONNECTED,
      PCOUT(41) => NLW_gen_dsp48_dsp_PCOUT_41_UNCONNECTED,
      PCOUT(40) => NLW_gen_dsp48_dsp_PCOUT_40_UNCONNECTED,
      PCOUT(39) => NLW_gen_dsp48_dsp_PCOUT_39_UNCONNECTED,
      PCOUT(38) => NLW_gen_dsp48_dsp_PCOUT_38_UNCONNECTED,
      PCOUT(37) => NLW_gen_dsp48_dsp_PCOUT_37_UNCONNECTED,
      PCOUT(36) => NLW_gen_dsp48_dsp_PCOUT_36_UNCONNECTED,
      PCOUT(35) => NLW_gen_dsp48_dsp_PCOUT_35_UNCONNECTED,
      PCOUT(34) => NLW_gen_dsp48_dsp_PCOUT_34_UNCONNECTED,
      PCOUT(33) => NLW_gen_dsp48_dsp_PCOUT_33_UNCONNECTED,
      PCOUT(32) => NLW_gen_dsp48_dsp_PCOUT_32_UNCONNECTED,
      PCOUT(31) => NLW_gen_dsp48_dsp_PCOUT_31_UNCONNECTED,
      PCOUT(30) => NLW_gen_dsp48_dsp_PCOUT_30_UNCONNECTED,
      PCOUT(29) => NLW_gen_dsp48_dsp_PCOUT_29_UNCONNECTED,
      PCOUT(28) => NLW_gen_dsp48_dsp_PCOUT_28_UNCONNECTED,
      PCOUT(27) => NLW_gen_dsp48_dsp_PCOUT_27_UNCONNECTED,
      PCOUT(26) => NLW_gen_dsp48_dsp_PCOUT_26_UNCONNECTED,
      PCOUT(25) => NLW_gen_dsp48_dsp_PCOUT_25_UNCONNECTED,
      PCOUT(24) => NLW_gen_dsp48_dsp_PCOUT_24_UNCONNECTED,
      PCOUT(23) => NLW_gen_dsp48_dsp_PCOUT_23_UNCONNECTED,
      PCOUT(22) => NLW_gen_dsp48_dsp_PCOUT_22_UNCONNECTED,
      PCOUT(21) => NLW_gen_dsp48_dsp_PCOUT_21_UNCONNECTED,
      PCOUT(20) => NLW_gen_dsp48_dsp_PCOUT_20_UNCONNECTED,
      PCOUT(19) => NLW_gen_dsp48_dsp_PCOUT_19_UNCONNECTED,
      PCOUT(18) => NLW_gen_dsp48_dsp_PCOUT_18_UNCONNECTED,
      PCOUT(17) => NLW_gen_dsp48_dsp_PCOUT_17_UNCONNECTED,
      PCOUT(16) => NLW_gen_dsp48_dsp_PCOUT_16_UNCONNECTED,
      PCOUT(15) => NLW_gen_dsp48_dsp_PCOUT_15_UNCONNECTED,
      PCOUT(14) => NLW_gen_dsp48_dsp_PCOUT_14_UNCONNECTED,
      PCOUT(13) => NLW_gen_dsp48_dsp_PCOUT_13_UNCONNECTED,
      PCOUT(12) => NLW_gen_dsp48_dsp_PCOUT_12_UNCONNECTED,
      PCOUT(11) => NLW_gen_dsp48_dsp_PCOUT_11_UNCONNECTED,
      PCOUT(10) => NLW_gen_dsp48_dsp_PCOUT_10_UNCONNECTED,
      PCOUT(9) => NLW_gen_dsp48_dsp_PCOUT_9_UNCONNECTED,
      PCOUT(8) => NLW_gen_dsp48_dsp_PCOUT_8_UNCONNECTED,
      PCOUT(7) => NLW_gen_dsp48_dsp_PCOUT_7_UNCONNECTED,
      PCOUT(6) => NLW_gen_dsp48_dsp_PCOUT_6_UNCONNECTED,
      PCOUT(5) => NLW_gen_dsp48_dsp_PCOUT_5_UNCONNECTED,
      PCOUT(4) => NLW_gen_dsp48_dsp_PCOUT_4_UNCONNECTED,
      PCOUT(3) => NLW_gen_dsp48_dsp_PCOUT_3_UNCONNECTED,
      PCOUT(2) => NLW_gen_dsp48_dsp_PCOUT_2_UNCONNECTED,
      PCOUT(1) => NLW_gen_dsp48_dsp_PCOUT_1_UNCONNECTED,
      PCOUT(0) => NLW_gen_dsp48_dsp_PCOUT_0_UNCONNECTED,
      P(47) => port_p(47),
      P(46) => port_p(46),
      P(45) => port_p(45),
      P(44) => port_p(44),
      P(43) => port_p(43),
      P(42) => port_p(42),
      P(41) => port_p(41),
      P(40) => port_p(40),
      P(39) => port_p(39),
      P(38) => port_p(38),
      P(37) => port_p(37),
      P(36) => port_p(36),
      P(35) => port_p(35),
      P(34) => port_p(34),
      P(33) => port_p(33),
      P(32) => port_p(32),
      P(31) => port_p(31),
      P(30) => port_p(30),
      P(29) => port_p(29),
      P(28) => port_p(28),
      P(27) => port_p(27),
      P(26) => port_p(26),
      P(25) => port_p(25),
      P(24) => port_p(24),
      P(23) => port_p(23),
      P(22) => port_p(22),
      P(21) => port_p(21),
      P(20) => port_p(20),
      P(19) => port_p(19),
      P(18) => port_p(18),
      P(17) => port_p(17),
      P(16) => port_p(16),
      P(15) => port_p(15),
      P(14) => port_p(14),
      P(13) => port_p(13),
      P(12) => port_p(12),
      P(11) => port_p(11),
      P(10) => port_p(10),
      P(9) => port_p(9),
      P(8) => NlwRenamedSig_OI_ram_adrb(8),
      P(7) => NlwRenamedSig_OI_ram_adrb(7),
      P(6) => NlwRenamedSig_OI_ram_adrb(6),
      P(5) => NlwRenamedSig_OI_ram_adrb(5),
      P(4) => NlwRenamedSig_OI_ram_adrb(4),
      P(3) => NlwRenamedSig_OI_ram_adrb(3),
      P(2) => NlwRenamedSig_OI_ram_adrb(2),
      P(1) => NlwRenamedSig_OI_ram_adrb(1),
      P(0) => NlwRenamedSig_OI_ram_adrb(0),
      BCOUT(17) => NLW_gen_dsp48_dsp_BCOUT_17_UNCONNECTED,
      BCOUT(16) => NLW_gen_dsp48_dsp_BCOUT_16_UNCONNECTED,
      BCOUT(15) => NLW_gen_dsp48_dsp_BCOUT_15_UNCONNECTED,
      BCOUT(14) => NLW_gen_dsp48_dsp_BCOUT_14_UNCONNECTED,
      BCOUT(13) => NLW_gen_dsp48_dsp_BCOUT_13_UNCONNECTED,
      BCOUT(12) => NLW_gen_dsp48_dsp_BCOUT_12_UNCONNECTED,
      BCOUT(11) => NLW_gen_dsp48_dsp_BCOUT_11_UNCONNECTED,
      BCOUT(10) => NLW_gen_dsp48_dsp_BCOUT_10_UNCONNECTED,
      BCOUT(9) => NLW_gen_dsp48_dsp_BCOUT_9_UNCONNECTED,
      BCOUT(8) => NLW_gen_dsp48_dsp_BCOUT_8_UNCONNECTED,
      BCOUT(7) => NLW_gen_dsp48_dsp_BCOUT_7_UNCONNECTED,
      BCOUT(6) => NLW_gen_dsp48_dsp_BCOUT_6_UNCONNECTED,
      BCOUT(5) => NLW_gen_dsp48_dsp_BCOUT_5_UNCONNECTED,
      BCOUT(4) => NLW_gen_dsp48_dsp_BCOUT_4_UNCONNECTED,
      BCOUT(3) => NLW_gen_dsp48_dsp_BCOUT_3_UNCONNECTED,
      BCOUT(2) => NLW_gen_dsp48_dsp_BCOUT_2_UNCONNECTED,
      BCOUT(1) => NLW_gen_dsp48_dsp_BCOUT_1_UNCONNECTED,
      BCOUT(0) => NLW_gen_dsp48_dsp_BCOUT_0_UNCONNECTED,
      ACIN(29) => NLW_gen_dsp48_dsp_ACIN_29_UNCONNECTED,
      ACIN(28) => NLW_gen_dsp48_dsp_ACIN_28_UNCONNECTED,
      ACIN(27) => NLW_gen_dsp48_dsp_ACIN_27_UNCONNECTED,
      ACIN(26) => NLW_gen_dsp48_dsp_ACIN_26_UNCONNECTED,
      ACIN(25) => NLW_gen_dsp48_dsp_ACIN_25_UNCONNECTED,
      ACIN(24) => NLW_gen_dsp48_dsp_ACIN_24_UNCONNECTED,
      ACIN(23) => NLW_gen_dsp48_dsp_ACIN_23_UNCONNECTED,
      ACIN(22) => NLW_gen_dsp48_dsp_ACIN_22_UNCONNECTED,
      ACIN(21) => NLW_gen_dsp48_dsp_ACIN_21_UNCONNECTED,
      ACIN(20) => NLW_gen_dsp48_dsp_ACIN_20_UNCONNECTED,
      ACIN(19) => NLW_gen_dsp48_dsp_ACIN_19_UNCONNECTED,
      ACIN(18) => NLW_gen_dsp48_dsp_ACIN_18_UNCONNECTED,
      ACIN(17) => NLW_gen_dsp48_dsp_ACIN_17_UNCONNECTED,
      ACIN(16) => NLW_gen_dsp48_dsp_ACIN_16_UNCONNECTED,
      ACIN(15) => NLW_gen_dsp48_dsp_ACIN_15_UNCONNECTED,
      ACIN(14) => NLW_gen_dsp48_dsp_ACIN_14_UNCONNECTED,
      ACIN(13) => NLW_gen_dsp48_dsp_ACIN_13_UNCONNECTED,
      ACIN(12) => NLW_gen_dsp48_dsp_ACIN_12_UNCONNECTED,
      ACIN(11) => NLW_gen_dsp48_dsp_ACIN_11_UNCONNECTED,
      ACIN(10) => NLW_gen_dsp48_dsp_ACIN_10_UNCONNECTED,
      ACIN(9) => NLW_gen_dsp48_dsp_ACIN_9_UNCONNECTED,
      ACIN(8) => NLW_gen_dsp48_dsp_ACIN_8_UNCONNECTED,
      ACIN(7) => NLW_gen_dsp48_dsp_ACIN_7_UNCONNECTED,
      ACIN(6) => NLW_gen_dsp48_dsp_ACIN_6_UNCONNECTED,
      ACIN(5) => NLW_gen_dsp48_dsp_ACIN_5_UNCONNECTED,
      ACIN(4) => NLW_gen_dsp48_dsp_ACIN_4_UNCONNECTED,
      ACIN(3) => NLW_gen_dsp48_dsp_ACIN_3_UNCONNECTED,
      ACIN(2) => NLW_gen_dsp48_dsp_ACIN_2_UNCONNECTED,
      ACIN(1) => NLW_gen_dsp48_dsp_ACIN_1_UNCONNECTED,
      ACIN(0) => NLW_gen_dsp48_dsp_ACIN_0_UNCONNECTED,
      ACOUT(29) => NLW_gen_dsp48_dsp_ACOUT_29_UNCONNECTED,
      ACOUT(28) => NLW_gen_dsp48_dsp_ACOUT_28_UNCONNECTED,
      ACOUT(27) => NLW_gen_dsp48_dsp_ACOUT_27_UNCONNECTED,
      ACOUT(26) => NLW_gen_dsp48_dsp_ACOUT_26_UNCONNECTED,
      ACOUT(25) => NLW_gen_dsp48_dsp_ACOUT_25_UNCONNECTED,
      ACOUT(24) => NLW_gen_dsp48_dsp_ACOUT_24_UNCONNECTED,
      ACOUT(23) => NLW_gen_dsp48_dsp_ACOUT_23_UNCONNECTED,
      ACOUT(22) => NLW_gen_dsp48_dsp_ACOUT_22_UNCONNECTED,
      ACOUT(21) => NLW_gen_dsp48_dsp_ACOUT_21_UNCONNECTED,
      ACOUT(20) => NLW_gen_dsp48_dsp_ACOUT_20_UNCONNECTED,
      ACOUT(19) => NLW_gen_dsp48_dsp_ACOUT_19_UNCONNECTED,
      ACOUT(18) => NLW_gen_dsp48_dsp_ACOUT_18_UNCONNECTED,
      ACOUT(17) => NLW_gen_dsp48_dsp_ACOUT_17_UNCONNECTED,
      ACOUT(16) => NLW_gen_dsp48_dsp_ACOUT_16_UNCONNECTED,
      ACOUT(15) => NLW_gen_dsp48_dsp_ACOUT_15_UNCONNECTED,
      ACOUT(14) => NLW_gen_dsp48_dsp_ACOUT_14_UNCONNECTED,
      ACOUT(13) => NLW_gen_dsp48_dsp_ACOUT_13_UNCONNECTED,
      ACOUT(12) => NLW_gen_dsp48_dsp_ACOUT_12_UNCONNECTED,
      ACOUT(11) => NLW_gen_dsp48_dsp_ACOUT_11_UNCONNECTED,
      ACOUT(10) => NLW_gen_dsp48_dsp_ACOUT_10_UNCONNECTED,
      ACOUT(9) => NLW_gen_dsp48_dsp_ACOUT_9_UNCONNECTED,
      ACOUT(8) => NLW_gen_dsp48_dsp_ACOUT_8_UNCONNECTED,
      ACOUT(7) => NLW_gen_dsp48_dsp_ACOUT_7_UNCONNECTED,
      ACOUT(6) => NLW_gen_dsp48_dsp_ACOUT_6_UNCONNECTED,
      ACOUT(5) => NLW_gen_dsp48_dsp_ACOUT_5_UNCONNECTED,
      ACOUT(4) => NLW_gen_dsp48_dsp_ACOUT_4_UNCONNECTED,
      ACOUT(3) => NLW_gen_dsp48_dsp_ACOUT_3_UNCONNECTED,
      ACOUT(2) => NLW_gen_dsp48_dsp_ACOUT_2_UNCONNECTED,
      ACOUT(1) => NLW_gen_dsp48_dsp_ACOUT_1_UNCONNECTED,
      ACOUT(0) => NLW_gen_dsp48_dsp_ACOUT_0_UNCONNECTED,
      CARRYOUT(3) => NLW_gen_dsp48_dsp_CARRYOUT_3_UNCONNECTED,
      CARRYOUT(2) => NLW_gen_dsp48_dsp_CARRYOUT_2_UNCONNECTED,
      CARRYOUT(1) => NLW_gen_dsp48_dsp_CARRYOUT_1_UNCONNECTED,
      CARRYOUT(0) => NLW_gen_dsp48_dsp_CARRYOUT_0_UNCONNECTED
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd1_In,
      R => rst_p_12592,
      Q => stp_FSM_FFd1_12594
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd2_In,
      R => rst_p_12592,
      Q => stp_FSM_FFd2_12596
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd3_In,
      R => rst_p_12592,
      Q => stp_FSM_FFd3_12598
    );
  stp_FSM_FFd4 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd4_In,
      S => rst_p_12592,
      Q => stp_FSM_FFd4_12600
    );
  cmd1 : ctrl_ram_cmd_pb
    port map (
      pf_dma_rd_rdy => pf1_dma_rd_rdy,
      clk => clk,
      dmar => dmar1,
      aclk => aclk,
      next_block => ch0_next_block,
      reset => reset,
      pf_dma_wr_rdy => pf1_dma_wr_rdy,
      pf_repack_we => pf_repack_we,
      pf_ram_rd => NlwRenamedSig_OI_pf_ram_rd,
      act => pf1_act_12496,
      adr_hi_wr => NLW_cmd1_adr_hi_wr_UNCONNECTED,
      pf_cb => pf1_cb,
      rdy => pf1_rdy,
      flag_set(1) => pf_flag_set(3),
      flag_set(0) => pf_flag_set(2),
      flag_clr(1) => pf_flag_clr(3),
      flag_clr(0) => pf_flag_clr(2),
      reg_ctrl(7) => reg_ch1_ctrl(7),
      reg_ctrl(6) => reg_ch1_ctrl(6),
      reg_ctrl(5) => reg_ch1_ctrl(5),
      reg_ctrl(4) => reg_ch1_ctrl(4),
      reg_ctrl(3) => reg_ch1_ctrl(3),
      reg_ctrl(2) => reg_ch1_ctrl(2),
      reg_ctrl(1) => reg_ch1_ctrl(1),
      reg_ctrl(0) => reg_ch1_ctrl(0),
      flag_data(1) => flag_data(3),
      flag_data(0) => flag_data(2)
    );
  cmd0 : ctrl_ram_cmd_pb_INST_1
    port map (
      pf_dma_rd_rdy => pf0_dma_rd_rdy,
      clk => clk,
      dmar => dmar0,
      aclk => aclk,
      next_block => ch0_next_block,
      reset => reset,
      pf_dma_wr_rdy => pf0_dma_wr_rdy,
      pf_repack_we => pf_repack_we,
      pf_ram_rd => NlwRenamedSig_OI_pf_ram_rd,
      act => pf0_act_12490,
      adr_hi_wr => NLW_cmd0_adr_hi_wr_UNCONNECTED,
      pf_cb => pf0_cb,
      rdy => pf0_rdy,
      flag_set(1) => pf_flag_set(1),
      flag_set(0) => pf_flag_set(0),
      flag_clr(1) => pf_flag_clr(1),
      flag_clr(0) => pf_flag_clr(0),
      reg_ctrl(7) => reg_ch0_ctrl(7),
      reg_ctrl(6) => reg_ch0_ctrl(6),
      reg_ctrl(5) => reg_ch0_ctrl(5),
      reg_ctrl(4) => reg_ch0_ctrl(4),
      reg_ctrl(3) => reg_ch0_ctrl(3),
      reg_ctrl(2) => reg_ch0_ctrl(2),
      reg_ctrl(1) => reg_ch0_ctrl(1),
      reg_ctrl(0) => reg_ch0_ctrl(0),
      flag_data(1) => flag_data(1),
      flag_data(0) => flag_data(0)
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pf0_rdy,
      I1 => stp_FSM_FFd4_12600,
      I2 => stp_FSM_FFd3_12598,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd1_In1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => pf1_rdy,
      I1 => stp_FSM_FFd2_12596,
      I2 => stp_FSM_FFd1_12594,
      O => stp_FSM_FFd1_In
    );
  pf1_act_mux00001 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => stp_FSM_FFd3_12598,
      I1 => pf1_act_12496,
      I2 => stp_FSM_FFd2_12596,
      O => pf1_act_mux0000
    );
  stp_FSM_FFd4_In1 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => stp_FSM_FFd4_12600,
      I1 => pf0_rdy,
      I2 => stp_FSM_FFd1_12594,
      I3 => pf1_rdy,
      O => stp_FSM_FFd4_In
    );
  stp_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => stp_FSM_FFd3_12598,
      I1 => pf0_rdy,
      I2 => stp_FSM_FFd2_12596,
      I3 => pf1_rdy,
      O => stp_FSM_FFd2_In
    );
  pf0_act_mux00001 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => stp_FSM_FFd2_12596,
      I1 => pf0_act_12490,
      I2 => stp_FSM_FFd4_12600,
      I3 => stp_FSM_FFd1_12594,
      O => pf0_act_mux0000
    );
  pb_flag_set_3_and00001 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => dma_chn,
      I1 => reg_ch1_ctrl(2),
      I2 => reg_write_E0_z_12587,
      I3 => pb_current_block(1),
      O => pb_flag_set_3_and0000
    );
  pb_flag_set_2_and00001 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => reg_write_E0_z_12587,
      I1 => reg_ch1_ctrl(2),
      I2 => pb_current_block(1),
      I3 => dma_chn,
      O => pb_flag_set_2_and0000
    );
  pb_flag_set_1_and00001 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => reg_write_E0_z_12587,
      I1 => reg_ch0_ctrl(2),
      I2 => dma_chn,
      I3 => pb_current_block(0),
      O => pb_flag_set_1_and0000
    );
  pb_flag_set_0_and00001 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => reg_ch0_ctrl(2),
      I1 => dma_chn,
      I2 => pb_current_block(0),
      I3 => reg_write_E0_z_12587,
      O => pb_flag_set_0_and0000
    );
  pb_flag_clr_3_or00001 : LUT5
    generic map(
      INIT => X"FFFF8000"
    )
    port map (
      I0 => reg_ch1_ctrl(2),
      I1 => dma_chn,
      I2 => reg_write_E0_z_12587,
      I3 => pb_current_block(1),
      I4 => reg_ch1_ctrl(4),
      O => pb_flag_clr_3_or0000
    );
  pb_flag_clr_2_or00001 : LUT5
    generic map(
      INIT => X"AAAAEAAA"
    )
    port map (
      I0 => reg_ch1_ctrl(4),
      I1 => reg_ch1_ctrl(2),
      I2 => dma_chn,
      I3 => reg_write_E0_z_12587,
      I4 => pb_current_block(1),
      O => pb_flag_clr_2_or0000
    );
  pb_flag_clr_1_or00001 : LUT5
    generic map(
      INIT => X"AAAAEAAA"
    )
    port map (
      I0 => reg_ch0_ctrl(4),
      I1 => pb_current_block(0),
      I2 => reg_ch0_ctrl(2),
      I3 => reg_write_E0_z_12587,
      I4 => dma_chn,
      O => pb_flag_clr_1_or0000
    );
  pb_flag_clr_0_or00001 : LUT5
    generic map(
      INIT => X"FFFF0008"
    )
    port map (
      I0 => reg_write_E0_z_12587,
      I1 => reg_ch0_ctrl(2),
      I2 => dma_chn,
      I3 => pb_current_block(0),
      I4 => reg_ch0_ctrl(4),
      O => pb_flag_clr_0_or0000
    );
  ram1_transfer_rdy_mux00021 : LUT6
    generic map(
      INIT => X"2202002020000222"
    )
    port map (
      I0 => reg_ch1_ctrl(0),
      I1 => reg_ch1_ctrl(3),
      I2 => pb_current_block(1),
      I3 => flag_data(3),
      I4 => reg_ch1_ctrl(2),
      I5 => flag_data(2),
      O => ram1_transfer_rdy_mux0002
    );
  ram0_transfer_rdy_mux00021 : LUT6
    generic map(
      INIT => X"2202002020000222"
    )
    port map (
      I0 => reg_ch0_ctrl(0),
      I1 => reg_ch0_ctrl(3),
      I2 => pb_current_block(0),
      I3 => flag_data(1),
      I4 => reg_ch0_ctrl(2),
      I5 => flag_data(0),
      O => ram0_transfer_rdy_mux0002
    );
  pb_current_block_1_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => reg_write_E0_z1_12588,
      I1 => dma_chn,
      O => pb_current_block_1_and0000
    );
  pb_current_block_0_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => dma_chn,
      I1 => reg_write_E0_z1_12588,
      O => pb_current_block_0_and0000
    );
  flag_data_3_or00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pb_flag_set(3),
      I1 => pf_flag_set(3),
      O => flag_data_3_or0001
    );
  flag_data_2_or00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pb_flag_set(2),
      I1 => pf_flag_set(2),
      O => flag_data_2_or0001
    );
  flag_data_1_or00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pb_flag_set(1),
      I1 => pf_flag_set(1),
      O => flag_data_1_or0001
    );
  flag_data_0_or00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pb_flag_set(0),
      I1 => pf_flag_set(0),
      O => flag_data_0_or0001
    );
  ram_adrb_9_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_pf_chn,
      I1 => pf0_cb,
      I2 => pf1_cb,
      O => ram_adrb(9)
    );
  cb1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_chn,
      I1 => pb_current_block(0),
      I2 => pb_current_block(1),
      O => ram_adra_a9
    );
  stp_FSM_Out41 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd1_12594,
      I1 => stp_FSM_FFd3_12598,
      O => Q_mux0000
    );
  pf_dma_rd_rdy1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pf0_dma_rd_rdy,
      I1 => pf1_dma_rd_rdy,
      O => request_rd
    );
  flag_data_3_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => rst_p_12592,
      I1 => pb_flag_clr(3),
      I2 => pf_flag_clr(3),
      O => flag_data_3_or0000
    );
  flag_data_2_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => rst_p_12592,
      I1 => pb_flag_clr(2),
      I2 => pf_flag_clr(2),
      O => flag_data_2_or0000
    );
  flag_data_1_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => rst_p_12592,
      I1 => pb_flag_clr(1),
      I2 => pf_flag_clr(1),
      O => flag_data_1_or0000
    );
  flag_data_0_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => rst_p_12592,
      I1 => pb_flag_clr(0),
      I2 => pf_flag_clr(0),
      O => flag_data_0_or0000
    );
  pf_dma_wr_rdy1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pf0_dma_wr_rdy,
      I1 => pf1_dma_wr_rdy,
      O => request_wr
    );
  pf_ram_rd_or0000_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_ram_adrb(4),
      I1 => NlwRenamedSig_OI_ram_adrb(3),
      I2 => NlwRenamedSig_OI_ram_adrb(2),
      I3 => NlwRenamedSig_OI_ram_adrb(1),
      I4 => NlwRenamedSig_OI_ram_adrb(0),
      O => N0
    );
  pf_ram_rd_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFF80000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_ram_adrb(8),
      I1 => NlwRenamedSig_OI_ram_adrb(7),
      I2 => NlwRenamedSig_OI_ram_adrb(6),
      I3 => NlwRenamedSig_OI_ram_adrb(5),
      I4 => N0,
      I5 => cnt_rstp_12451,
      O => pf_ram_rd_or0000_12514
    );
  carry1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => pf_repack_we,
      I1 => NlwRenamedSig_OI_pf_ram_rd,
      O => carry
    );
  pf_ram_rd_and00001 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => allow_wr,
      I1 => pf0_dma_wr_rdy,
      I2 => pf1_dma_wr_rdy,
      O => pf_ram_rd_and0000
    );
  pf_chn_mux00001 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => stp_FSM_FFd1_12594,
      I1 => NlwRenamedSig_OI_pf_chn,
      I2 => stp_FSM_FFd2_12596,
      I3 => stp_FSM_FFd3_12598,
      O => pf_chn_mux0000
    );
  pb_current_block_1_not00011_INV_0 : INV
    port map (
      I => pb_current_block(1),
      O => pb_current_block_1_not0001
    );
  pb_current_block_0_not00011_INV_0 : INV
    port map (
      I => pb_current_block(0),
      O => pb_current_block_0_not0001
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ext_ram is
  port (
    clk : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_data_we : in STD_LOGIC := 'X'; 
    dma1_transfer_rdy : out STD_LOGIC; 
    aclk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    loc_adr_we : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_irq : in STD_LOGIC := 'X'; 
    ram_change : in STD_LOGIC := 'X'; 
    dma_wr_en : in STD_LOGIC := 'X'; 
    dma0_transfer_rdy : out STD_LOGIC; 
    dma_wr : in STD_LOGIC := 'X'; 
    ext_fifo_disp_data_we : out STD_LOGIC; 
    ext_fifo_disp_request_rd : out STD_LOGIC; 
    ext_fifo_disp_back_allow_wr : in STD_LOGIC := 'X'; 
    dma_chn : in STD_LOGIC := 'X'; 
    ext_fifo_disp_request_wr : out STD_LOGIC; 
    ext_fifo_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    dma_rddata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_back_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    dma_rdaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    dma0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dma_wrdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    dma1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dma_wraddr : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end ctrl_ext_ram;

architecture STRUCTURE of ctrl_ext_ram is
  component ctrl_ram_cmd
    port (
      clk : in STD_LOGIC := 'X'; 
      dma1_transfer_rdy : out STD_LOGIC; 
      allow_wr : in STD_LOGIC := 'X'; 
      aclk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      pf_repack_we : in STD_LOGIC := 'X'; 
      reg_write_E0 : in STD_LOGIC := 'X'; 
      pf_ram_rd_out : out STD_LOGIC; 
      dma0_transfer_rdy : out STD_LOGIC; 
      request_rd : out STD_LOGIC; 
      ram_adra_a9 : out STD_LOGIC; 
      request_wr : out STD_LOGIC; 
      dmar0 : in STD_LOGIC := 'X'; 
      dmar1 : in STD_LOGIC := 'X'; 
      dma_chn : in STD_LOGIC := 'X'; 
      ram_adrb : out STD_LOGIC_VECTOR ( 10 downto 0 ); 
      reg_ch0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      reg_ch1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal ext_fifo_disp_data_we_12805 : STD_LOGIC; 
  signal pf_ram_rd : STD_LOGIC; 
  signal ram_we_a : STD_LOGIC; 
  signal NLW_gen_ram_adr_0_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_1_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_2_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_3_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_4_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_5_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_6_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_7_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_8_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_9_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_10_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_11_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_12_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_13_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_14_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_15_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_16_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_17_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_18_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_19_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_20_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_21_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_22_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_23_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_24_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_25_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_26_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_27_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_28_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_29_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_30_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_adr_31_ram1_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_0_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_1_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_2_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_3_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_4_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_5_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_6_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOA_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_data_7_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal ram_adra : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal ram_adrb : STD_LOGIC_VECTOR ( 10 downto 0 ); 
begin
  ext_fifo_disp_data_we <= ext_fifo_disp_data_we_12805;
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  ext_fifo_disp_data_we_8976 : FD
    port map (
      C => aclk,
      D => pf_ram_rd,
      Q => ext_fifo_disp_data_we_12805
    );
  gen_ram_adr_0_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(0),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_0_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(0)
    );
  gen_ram_adr_1_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(1),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_1_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(1)
    );
  gen_ram_adr_2_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(2),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_2_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(2)
    );
  gen_ram_adr_3_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(3),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_3_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(3)
    );
  gen_ram_adr_4_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(4),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_4_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(4)
    );
  gen_ram_adr_5_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(5),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_5_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(5)
    );
  gen_ram_adr_6_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(6),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_6_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(6)
    );
  gen_ram_adr_7_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(7),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_7_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(7)
    );
  gen_ram_adr_8_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(8),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_8_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(8)
    );
  gen_ram_adr_9_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(9),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_9_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(9)
    );
  gen_ram_adr_10_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(10),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_10_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(10)
    );
  gen_ram_adr_11_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(11),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_11_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(11)
    );
  gen_ram_adr_12_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(12),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_12_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(12)
    );
  gen_ram_adr_13_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(13),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_13_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(13)
    );
  gen_ram_adr_14_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(14),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_14_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(14)
    );
  gen_ram_adr_15_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(15),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_15_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(15)
    );
  gen_ram_adr_16_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(16),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_16_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(16)
    );
  gen_ram_adr_17_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(17),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_17_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(17)
    );
  gen_ram_adr_18_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(18),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_18_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(18)
    );
  gen_ram_adr_19_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(19),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_19_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(19)
    );
  gen_ram_adr_20_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(20),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_20_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(20)
    );
  gen_ram_adr_21_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(21),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_21_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(21)
    );
  gen_ram_adr_22_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(22),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_22_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(22)
    );
  gen_ram_adr_23_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(23),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_23_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(23)
    );
  gen_ram_adr_24_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(24),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_24_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(24)
    );
  gen_ram_adr_25_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(25),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_25_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(25)
    );
  gen_ram_adr_26_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(26),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_26_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(26)
    );
  gen_ram_adr_27_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(27),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_27_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(27)
    );
  gen_ram_adr_28_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(28),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_28_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(28)
    );
  gen_ram_adr_29_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(29),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_29_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(29)
    );
  gen_ram_adr_30_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(30),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_30_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(30)
    );
  gen_ram_adr_31_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => N0,
      A2 => N0,
      A3 => N0,
      D => data_in(31),
      DPRA0 => ram_adrb(10),
      DPRA1 => N0,
      DPRA2 => N0,
      DPRA3 => N0,
      WCLK => clk,
      WE => loc_adr_we,
      SPO => NLW_gen_ram_adr_31_ram1_SPO_UNCONNECTED,
      DPO => ext_fifo_disp_adr(31)
    );
  ram_adra_8_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(11),
      I2 => dma_rdaddr(11),
      O => ram_adra(8)
    );
  ram_adra_7_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(10),
      I2 => dma_rdaddr(10),
      O => ram_adra(7)
    );
  ram_adra_6_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(9),
      I2 => dma_rdaddr(9),
      O => ram_adra(6)
    );
  ram_adra_5_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(8),
      I2 => dma_rdaddr(8),
      O => ram_adra(5)
    );
  ram_adra_4_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(7),
      I2 => dma_rdaddr(7),
      O => ram_adra(4)
    );
  ram_adra_3_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(6),
      I2 => dma_rdaddr(6),
      O => ram_adra(3)
    );
  ram_adra_2_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(5),
      I2 => dma_rdaddr(5),
      O => ram_adra(2)
    );
  ram_adra_1_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(4),
      I2 => dma_rdaddr(4),
      O => ram_adra(1)
    );
  ram_adra_0_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wraddr(3),
      I2 => dma_rdaddr(3),
      O => ram_adra(0)
    );
  ram_we_a1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => dma_wr_en,
      I1 => dma_wr,
      O => ram_we_a
    );
  cmd : ctrl_ram_cmd
    port map (
      clk => clk,
      dma1_transfer_rdy => dma1_transfer_rdy,
      allow_wr => ext_fifo_disp_back_allow_wr,
      aclk => aclk,
      reset => reset,
      pf_repack_we => ext_fifo_disp_back_data_we,
      reg_write_E0 => ram_change,
      pf_ram_rd_out => pf_ram_rd,
      dma0_transfer_rdy => dma0_transfer_rdy,
      request_rd => ext_fifo_disp_request_rd,
      ram_adra_a9 => ram_adra(9),
      request_wr => ext_fifo_disp_request_wr,
      dmar0 => ext_fifo_disp_back_dmar(0),
      dmar1 => ext_fifo_disp_back_dmar(1),
      dma_chn => dma_chn,
      ram_adrb(10) => ram_adrb(10),
      ram_adrb(9) => ram_adrb(9),
      ram_adrb(8) => ram_adrb(8),
      ram_adrb(7) => ram_adrb(7),
      ram_adrb(6) => ram_adrb(6),
      ram_adrb(5) => ram_adrb(5),
      ram_adrb(4) => ram_adrb(4),
      ram_adrb(3) => ram_adrb(3),
      ram_adrb(2) => ram_adrb(2),
      ram_adrb(1) => ram_adrb(1),
      ram_adrb(0) => ram_adrb(0),
      reg_ch0_ctrl(7) => dma0_ctrl(7),
      reg_ch0_ctrl(6) => dma0_ctrl(6),
      reg_ch0_ctrl(5) => dma0_ctrl(5),
      reg_ch0_ctrl(4) => dma0_ctrl(4),
      reg_ch0_ctrl(3) => dma0_ctrl(3),
      reg_ch0_ctrl(2) => dma0_ctrl(2),
      reg_ch0_ctrl(1) => dma0_ctrl(1),
      reg_ch0_ctrl(0) => dma0_ctrl(0),
      reg_ch1_ctrl(7) => dma1_ctrl(7),
      reg_ch1_ctrl(6) => dma1_ctrl(6),
      reg_ch1_ctrl(5) => dma1_ctrl(5),
      reg_ch1_ctrl(4) => dma1_ctrl(4),
      reg_ch1_ctrl(3) => dma1_ctrl(3),
      reg_ch1_ctrl(2) => dma1_ctrl(2),
      reg_ch1_ctrl(1) => dma1_ctrl(1),
      reg_ch1_ctrl(0) => dma1_ctrl(0)
    );
  gen_ram_data_0_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_0_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_0_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_0_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_0_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_0_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_0_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_0_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_0_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_0_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_0_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_0_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_0_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_0_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_0_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_0_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_0_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_0_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_0_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_0_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_0_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_0_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_0_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_0_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_0_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_0_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_0_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_0_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_0_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_0_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_0_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_0_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_0_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_0_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_0_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_0_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_0_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(7),
      DIA(6) => dma_wrdata(6),
      DIA(5) => dma_wrdata(5),
      DIA(4) => dma_wrdata(4),
      DIA(3) => dma_wrdata(3),
      DIA(2) => dma_wrdata(2),
      DIA(1) => dma_wrdata(1),
      DIA(0) => dma_wrdata(0),
      DIB(31) => NLW_gen_ram_data_0_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_0_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_0_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_0_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_0_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_0_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_0_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_0_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_0_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_0_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_0_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_0_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_0_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_0_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_0_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_0_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_0_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_0_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_0_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_0_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_0_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_0_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_0_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_0_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(7),
      DIB(6) => ext_fifo_disp_back_data(6),
      DIB(5) => ext_fifo_disp_back_data(5),
      DIB(4) => ext_fifo_disp_back_data(4),
      DIB(3) => ext_fifo_disp_back_data(3),
      DIB(2) => ext_fifo_disp_back_data(2),
      DIB(1) => ext_fifo_disp_back_data(1),
      DIB(0) => ext_fifo_disp_back_data(0),
      DIPA(3) => NLW_gen_ram_data_0_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_0_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_0_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_0_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_0_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_0_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_0_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_0_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_0_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_0_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_0_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_0_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_0_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_0_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_0_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_0_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_0_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_0_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_0_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_0_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_0_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_0_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_0_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_0_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_0_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_0_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_0_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_0_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_0_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_0_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(7),
      DOA(6) => dma_rddata(6),
      DOA(5) => dma_rddata(5),
      DOA(4) => dma_rddata(4),
      DOA(3) => dma_rddata(3),
      DOA(2) => dma_rddata(2),
      DOA(1) => dma_rddata(1),
      DOA(0) => dma_rddata(0),
      DOB(31) => NLW_gen_ram_data_0_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_0_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_0_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_0_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_0_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_0_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_0_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_0_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_0_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_0_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_0_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_0_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_0_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_0_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_0_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_0_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_0_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_0_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_0_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_0_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_0_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_0_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_0_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_0_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(7),
      DOB(6) => ext_fifo_disp_data(6),
      DOB(5) => ext_fifo_disp_data(5),
      DOB(4) => ext_fifo_disp_data(4),
      DOB(3) => ext_fifo_disp_data(3),
      DOB(2) => ext_fifo_disp_data(2),
      DOB(1) => ext_fifo_disp_data(1),
      DOB(0) => ext_fifo_disp_data(0),
      DOPA(3) => NLW_gen_ram_data_0_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_0_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_0_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_0_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_0_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_0_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_0_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_0_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_1_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_1_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_1_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_1_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_1_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_1_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_1_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_1_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_1_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_1_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_1_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_1_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_1_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_1_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_1_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_1_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_1_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_1_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_1_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_1_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_1_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_1_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_1_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_1_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_1_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_1_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_1_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_1_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_1_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_1_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_1_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_1_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_1_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_1_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_1_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_1_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_1_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(15),
      DIA(6) => dma_wrdata(14),
      DIA(5) => dma_wrdata(13),
      DIA(4) => dma_wrdata(12),
      DIA(3) => dma_wrdata(11),
      DIA(2) => dma_wrdata(10),
      DIA(1) => dma_wrdata(9),
      DIA(0) => dma_wrdata(8),
      DIB(31) => NLW_gen_ram_data_1_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_1_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_1_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_1_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_1_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_1_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_1_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_1_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_1_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_1_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_1_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_1_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_1_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_1_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_1_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_1_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_1_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_1_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_1_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_1_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_1_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_1_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_1_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_1_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(15),
      DIB(6) => ext_fifo_disp_back_data(14),
      DIB(5) => ext_fifo_disp_back_data(13),
      DIB(4) => ext_fifo_disp_back_data(12),
      DIB(3) => ext_fifo_disp_back_data(11),
      DIB(2) => ext_fifo_disp_back_data(10),
      DIB(1) => ext_fifo_disp_back_data(9),
      DIB(0) => ext_fifo_disp_back_data(8),
      DIPA(3) => NLW_gen_ram_data_1_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_1_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_1_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_1_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_1_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_1_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_1_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_1_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_1_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_1_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_1_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_1_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_1_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_1_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_1_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_1_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_1_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_1_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_1_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_1_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_1_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_1_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_1_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_1_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_1_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_1_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_1_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_1_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_1_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_1_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(15),
      DOA(6) => dma_rddata(14),
      DOA(5) => dma_rddata(13),
      DOA(4) => dma_rddata(12),
      DOA(3) => dma_rddata(11),
      DOA(2) => dma_rddata(10),
      DOA(1) => dma_rddata(9),
      DOA(0) => dma_rddata(8),
      DOB(31) => NLW_gen_ram_data_1_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_1_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_1_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_1_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_1_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_1_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_1_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_1_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_1_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_1_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_1_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_1_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_1_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_1_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_1_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_1_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_1_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_1_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_1_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_1_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_1_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_1_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_1_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_1_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(15),
      DOB(6) => ext_fifo_disp_data(14),
      DOB(5) => ext_fifo_disp_data(13),
      DOB(4) => ext_fifo_disp_data(12),
      DOB(3) => ext_fifo_disp_data(11),
      DOB(2) => ext_fifo_disp_data(10),
      DOB(1) => ext_fifo_disp_data(9),
      DOB(0) => ext_fifo_disp_data(8),
      DOPA(3) => NLW_gen_ram_data_1_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_1_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_1_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_1_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_1_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_1_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_1_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_1_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_2_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_2_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_2_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_2_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_2_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_2_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_2_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_2_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_2_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_2_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_2_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_2_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_2_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_2_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_2_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_2_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_2_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_2_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_2_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_2_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_2_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_2_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_2_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_2_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_2_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_2_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_2_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_2_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_2_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_2_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_2_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_2_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_2_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_2_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_2_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_2_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_2_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(23),
      DIA(6) => dma_wrdata(22),
      DIA(5) => dma_wrdata(21),
      DIA(4) => dma_wrdata(20),
      DIA(3) => dma_wrdata(19),
      DIA(2) => dma_wrdata(18),
      DIA(1) => dma_wrdata(17),
      DIA(0) => dma_wrdata(16),
      DIB(31) => NLW_gen_ram_data_2_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_2_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_2_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_2_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_2_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_2_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_2_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_2_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_2_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_2_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_2_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_2_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_2_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_2_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_2_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_2_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_2_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_2_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_2_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_2_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_2_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_2_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_2_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_2_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(23),
      DIB(6) => ext_fifo_disp_back_data(22),
      DIB(5) => ext_fifo_disp_back_data(21),
      DIB(4) => ext_fifo_disp_back_data(20),
      DIB(3) => ext_fifo_disp_back_data(19),
      DIB(2) => ext_fifo_disp_back_data(18),
      DIB(1) => ext_fifo_disp_back_data(17),
      DIB(0) => ext_fifo_disp_back_data(16),
      DIPA(3) => NLW_gen_ram_data_2_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_2_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_2_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_2_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_2_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_2_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_2_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_2_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_2_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_2_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_2_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_2_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_2_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_2_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_2_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_2_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_2_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_2_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_2_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_2_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_2_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_2_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_2_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_2_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_2_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_2_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_2_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_2_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_2_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_2_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(23),
      DOA(6) => dma_rddata(22),
      DOA(5) => dma_rddata(21),
      DOA(4) => dma_rddata(20),
      DOA(3) => dma_rddata(19),
      DOA(2) => dma_rddata(18),
      DOA(1) => dma_rddata(17),
      DOA(0) => dma_rddata(16),
      DOB(31) => NLW_gen_ram_data_2_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_2_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_2_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_2_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_2_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_2_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_2_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_2_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_2_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_2_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_2_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_2_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_2_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_2_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_2_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_2_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_2_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_2_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_2_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_2_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_2_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_2_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_2_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_2_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(23),
      DOB(6) => ext_fifo_disp_data(22),
      DOB(5) => ext_fifo_disp_data(21),
      DOB(4) => ext_fifo_disp_data(20),
      DOB(3) => ext_fifo_disp_data(19),
      DOB(2) => ext_fifo_disp_data(18),
      DOB(1) => ext_fifo_disp_data(17),
      DOB(0) => ext_fifo_disp_data(16),
      DOPA(3) => NLW_gen_ram_data_2_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_2_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_2_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_2_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_2_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_2_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_2_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_2_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_3_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_3_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_3_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_3_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_3_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_3_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_3_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_3_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_3_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_3_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_3_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_3_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_3_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_3_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_3_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_3_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_3_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_3_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_3_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_3_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_3_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_3_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_3_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_3_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_3_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_3_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_3_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_3_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_3_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_3_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_3_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_3_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_3_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_3_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_3_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_3_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_3_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(31),
      DIA(6) => dma_wrdata(30),
      DIA(5) => dma_wrdata(29),
      DIA(4) => dma_wrdata(28),
      DIA(3) => dma_wrdata(27),
      DIA(2) => dma_wrdata(26),
      DIA(1) => dma_wrdata(25),
      DIA(0) => dma_wrdata(24),
      DIB(31) => NLW_gen_ram_data_3_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_3_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_3_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_3_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_3_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_3_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_3_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_3_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_3_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_3_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_3_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_3_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_3_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_3_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_3_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_3_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_3_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_3_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_3_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_3_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_3_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_3_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_3_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_3_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(31),
      DIB(6) => ext_fifo_disp_back_data(30),
      DIB(5) => ext_fifo_disp_back_data(29),
      DIB(4) => ext_fifo_disp_back_data(28),
      DIB(3) => ext_fifo_disp_back_data(27),
      DIB(2) => ext_fifo_disp_back_data(26),
      DIB(1) => ext_fifo_disp_back_data(25),
      DIB(0) => ext_fifo_disp_back_data(24),
      DIPA(3) => NLW_gen_ram_data_3_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_3_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_3_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_3_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_3_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_3_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_3_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_3_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_3_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_3_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_3_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_3_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_3_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_3_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_3_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_3_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_3_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_3_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_3_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_3_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_3_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_3_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_3_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_3_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_3_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_3_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_3_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_3_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_3_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_3_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(31),
      DOA(6) => dma_rddata(30),
      DOA(5) => dma_rddata(29),
      DOA(4) => dma_rddata(28),
      DOA(3) => dma_rddata(27),
      DOA(2) => dma_rddata(26),
      DOA(1) => dma_rddata(25),
      DOA(0) => dma_rddata(24),
      DOB(31) => NLW_gen_ram_data_3_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_3_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_3_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_3_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_3_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_3_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_3_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_3_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_3_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_3_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_3_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_3_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_3_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_3_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_3_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_3_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_3_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_3_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_3_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_3_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_3_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_3_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_3_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_3_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(31),
      DOB(6) => ext_fifo_disp_data(30),
      DOB(5) => ext_fifo_disp_data(29),
      DOB(4) => ext_fifo_disp_data(28),
      DOB(3) => ext_fifo_disp_data(27),
      DOB(2) => ext_fifo_disp_data(26),
      DOB(1) => ext_fifo_disp_data(25),
      DOB(0) => ext_fifo_disp_data(24),
      DOPA(3) => NLW_gen_ram_data_3_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_3_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_3_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_3_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_3_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_3_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_3_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_3_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_4_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_4_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_4_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_4_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_4_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_4_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_4_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_4_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_4_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_4_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_4_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_4_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_4_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_4_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_4_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_4_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_4_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_4_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_4_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_4_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_4_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_4_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_4_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_4_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_4_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_4_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_4_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_4_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_4_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_4_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_4_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_4_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_4_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_4_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_4_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_4_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_4_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(39),
      DIA(6) => dma_wrdata(38),
      DIA(5) => dma_wrdata(37),
      DIA(4) => dma_wrdata(36),
      DIA(3) => dma_wrdata(35),
      DIA(2) => dma_wrdata(34),
      DIA(1) => dma_wrdata(33),
      DIA(0) => dma_wrdata(32),
      DIB(31) => NLW_gen_ram_data_4_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_4_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_4_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_4_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_4_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_4_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_4_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_4_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_4_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_4_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_4_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_4_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_4_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_4_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_4_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_4_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_4_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_4_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_4_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_4_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_4_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_4_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_4_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_4_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(39),
      DIB(6) => ext_fifo_disp_back_data(38),
      DIB(5) => ext_fifo_disp_back_data(37),
      DIB(4) => ext_fifo_disp_back_data(36),
      DIB(3) => ext_fifo_disp_back_data(35),
      DIB(2) => ext_fifo_disp_back_data(34),
      DIB(1) => ext_fifo_disp_back_data(33),
      DIB(0) => ext_fifo_disp_back_data(32),
      DIPA(3) => NLW_gen_ram_data_4_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_4_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_4_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_4_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_4_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_4_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_4_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_4_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_4_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_4_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_4_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_4_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_4_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_4_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_4_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_4_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_4_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_4_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_4_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_4_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_4_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_4_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_4_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_4_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_4_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_4_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_4_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_4_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_4_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_4_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(39),
      DOA(6) => dma_rddata(38),
      DOA(5) => dma_rddata(37),
      DOA(4) => dma_rddata(36),
      DOA(3) => dma_rddata(35),
      DOA(2) => dma_rddata(34),
      DOA(1) => dma_rddata(33),
      DOA(0) => dma_rddata(32),
      DOB(31) => NLW_gen_ram_data_4_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_4_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_4_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_4_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_4_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_4_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_4_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_4_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_4_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_4_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_4_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_4_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_4_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_4_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_4_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_4_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_4_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_4_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_4_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_4_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_4_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_4_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_4_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_4_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(39),
      DOB(6) => ext_fifo_disp_data(38),
      DOB(5) => ext_fifo_disp_data(37),
      DOB(4) => ext_fifo_disp_data(36),
      DOB(3) => ext_fifo_disp_data(35),
      DOB(2) => ext_fifo_disp_data(34),
      DOB(1) => ext_fifo_disp_data(33),
      DOB(0) => ext_fifo_disp_data(32),
      DOPA(3) => NLW_gen_ram_data_4_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_4_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_4_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_4_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_4_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_4_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_4_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_4_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_5_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_5_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_5_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_5_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_5_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_5_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_5_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_5_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_5_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_5_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_5_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_5_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_5_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_5_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_5_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_5_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_5_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_5_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_5_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_5_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_5_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_5_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_5_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_5_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_5_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_5_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_5_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_5_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_5_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_5_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_5_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_5_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_5_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_5_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_5_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_5_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_5_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(47),
      DIA(6) => dma_wrdata(46),
      DIA(5) => dma_wrdata(45),
      DIA(4) => dma_wrdata(44),
      DIA(3) => dma_wrdata(43),
      DIA(2) => dma_wrdata(42),
      DIA(1) => dma_wrdata(41),
      DIA(0) => dma_wrdata(40),
      DIB(31) => NLW_gen_ram_data_5_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_5_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_5_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_5_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_5_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_5_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_5_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_5_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_5_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_5_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_5_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_5_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_5_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_5_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_5_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_5_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_5_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_5_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_5_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_5_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_5_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_5_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_5_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_5_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(47),
      DIB(6) => ext_fifo_disp_back_data(46),
      DIB(5) => ext_fifo_disp_back_data(45),
      DIB(4) => ext_fifo_disp_back_data(44),
      DIB(3) => ext_fifo_disp_back_data(43),
      DIB(2) => ext_fifo_disp_back_data(42),
      DIB(1) => ext_fifo_disp_back_data(41),
      DIB(0) => ext_fifo_disp_back_data(40),
      DIPA(3) => NLW_gen_ram_data_5_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_5_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_5_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_5_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_5_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_5_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_5_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_5_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_5_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_5_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_5_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_5_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_5_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_5_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_5_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_5_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_5_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_5_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_5_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_5_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_5_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_5_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_5_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_5_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_5_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_5_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_5_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_5_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_5_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_5_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(47),
      DOA(6) => dma_rddata(46),
      DOA(5) => dma_rddata(45),
      DOA(4) => dma_rddata(44),
      DOA(3) => dma_rddata(43),
      DOA(2) => dma_rddata(42),
      DOA(1) => dma_rddata(41),
      DOA(0) => dma_rddata(40),
      DOB(31) => NLW_gen_ram_data_5_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_5_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_5_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_5_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_5_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_5_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_5_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_5_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_5_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_5_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_5_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_5_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_5_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_5_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_5_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_5_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_5_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_5_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_5_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_5_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_5_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_5_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_5_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_5_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(47),
      DOB(6) => ext_fifo_disp_data(46),
      DOB(5) => ext_fifo_disp_data(45),
      DOB(4) => ext_fifo_disp_data(44),
      DOB(3) => ext_fifo_disp_data(43),
      DOB(2) => ext_fifo_disp_data(42),
      DOB(1) => ext_fifo_disp_data(41),
      DOB(0) => ext_fifo_disp_data(40),
      DOPA(3) => NLW_gen_ram_data_5_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_5_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_5_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_5_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_5_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_5_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_5_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_5_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_6_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_6_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_6_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_6_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_6_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_6_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_6_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_6_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_6_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_6_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_6_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_6_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_6_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_6_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_6_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_6_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_6_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_6_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_6_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_6_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_6_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_6_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_6_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_6_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_6_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_6_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_6_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_6_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_6_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_6_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_6_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_6_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_6_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_6_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_6_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_6_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_6_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(55),
      DIA(6) => dma_wrdata(54),
      DIA(5) => dma_wrdata(53),
      DIA(4) => dma_wrdata(52),
      DIA(3) => dma_wrdata(51),
      DIA(2) => dma_wrdata(50),
      DIA(1) => dma_wrdata(49),
      DIA(0) => dma_wrdata(48),
      DIB(31) => NLW_gen_ram_data_6_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_6_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_6_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_6_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_6_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_6_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_6_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_6_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_6_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_6_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_6_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_6_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_6_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_6_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_6_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_6_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_6_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_6_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_6_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_6_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_6_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_6_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_6_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_6_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(55),
      DIB(6) => ext_fifo_disp_back_data(54),
      DIB(5) => ext_fifo_disp_back_data(53),
      DIB(4) => ext_fifo_disp_back_data(52),
      DIB(3) => ext_fifo_disp_back_data(51),
      DIB(2) => ext_fifo_disp_back_data(50),
      DIB(1) => ext_fifo_disp_back_data(49),
      DIB(0) => ext_fifo_disp_back_data(48),
      DIPA(3) => NLW_gen_ram_data_6_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_6_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_6_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_6_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_6_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_6_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_6_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_6_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_6_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_6_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_6_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_6_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_6_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_6_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_6_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_6_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_6_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_6_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_6_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_6_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_6_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_6_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_6_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_6_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_6_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_6_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_6_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_6_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_6_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_6_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(55),
      DOA(6) => dma_rddata(54),
      DOA(5) => dma_rddata(53),
      DOA(4) => dma_rddata(52),
      DOA(3) => dma_rddata(51),
      DOA(2) => dma_rddata(50),
      DOA(1) => dma_rddata(49),
      DOA(0) => dma_rddata(48),
      DOB(31) => NLW_gen_ram_data_6_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_6_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_6_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_6_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_6_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_6_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_6_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_6_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_6_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_6_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_6_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_6_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_6_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_6_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_6_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_6_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_6_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_6_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_6_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_6_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_6_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_6_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_6_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_6_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(55),
      DOB(6) => ext_fifo_disp_data(54),
      DOB(5) => ext_fifo_disp_data(53),
      DOB(4) => ext_fifo_disp_data(52),
      DOB(3) => ext_fifo_disp_data(51),
      DOB(2) => ext_fifo_disp_data(50),
      DOB(1) => ext_fifo_disp_data(49),
      DOB(0) => ext_fifo_disp_data(48),
      DOPA(3) => NLW_gen_ram_data_6_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_6_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_6_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_6_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_6_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_6_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_6_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_6_ram_DOPB_0_UNCONNECTED
    );
  gen_ram_data_7_ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_gen_ram_data_7_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_gen_ram_data_7_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => aclk,
      ENA => N1,
      REGCEA => N0,
      REGCEB => N0,
      ENB => N1,
      SSRA => N0,
      SSRB => N0,
      CASCADEOUTA => NLW_gen_ram_data_7_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_gen_ram_data_7_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_gen_ram_data_7_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => ram_adra(9),
      ADDRA(11) => ram_adra(8),
      ADDRA(10) => ram_adra(7),
      ADDRA(9) => ram_adra(6),
      ADDRA(8) => ram_adra(5),
      ADDRA(7) => ram_adra(4),
      ADDRA(6) => ram_adra(3),
      ADDRA(5) => ram_adra(2),
      ADDRA(4) => ram_adra(1),
      ADDRA(3) => ram_adra(0),
      ADDRA(2) => NLW_gen_ram_data_7_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_gen_ram_data_7_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_gen_ram_data_7_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_gen_ram_data_7_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => ram_adrb(10),
      ADDRB(12) => ram_adrb(9),
      ADDRB(11) => ram_adrb(8),
      ADDRB(10) => ram_adrb(7),
      ADDRB(9) => ram_adrb(6),
      ADDRB(8) => ram_adrb(5),
      ADDRB(7) => ram_adrb(4),
      ADDRB(6) => ram_adrb(3),
      ADDRB(5) => ram_adrb(2),
      ADDRB(4) => ram_adrb(1),
      ADDRB(3) => ram_adrb(0),
      ADDRB(2) => NLW_gen_ram_data_7_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_gen_ram_data_7_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_gen_ram_data_7_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_gen_ram_data_7_ram_DIA_31_UNCONNECTED,
      DIA(30) => NLW_gen_ram_data_7_ram_DIA_30_UNCONNECTED,
      DIA(29) => NLW_gen_ram_data_7_ram_DIA_29_UNCONNECTED,
      DIA(28) => NLW_gen_ram_data_7_ram_DIA_28_UNCONNECTED,
      DIA(27) => NLW_gen_ram_data_7_ram_DIA_27_UNCONNECTED,
      DIA(26) => NLW_gen_ram_data_7_ram_DIA_26_UNCONNECTED,
      DIA(25) => NLW_gen_ram_data_7_ram_DIA_25_UNCONNECTED,
      DIA(24) => NLW_gen_ram_data_7_ram_DIA_24_UNCONNECTED,
      DIA(23) => NLW_gen_ram_data_7_ram_DIA_23_UNCONNECTED,
      DIA(22) => NLW_gen_ram_data_7_ram_DIA_22_UNCONNECTED,
      DIA(21) => NLW_gen_ram_data_7_ram_DIA_21_UNCONNECTED,
      DIA(20) => NLW_gen_ram_data_7_ram_DIA_20_UNCONNECTED,
      DIA(19) => NLW_gen_ram_data_7_ram_DIA_19_UNCONNECTED,
      DIA(18) => NLW_gen_ram_data_7_ram_DIA_18_UNCONNECTED,
      DIA(17) => NLW_gen_ram_data_7_ram_DIA_17_UNCONNECTED,
      DIA(16) => NLW_gen_ram_data_7_ram_DIA_16_UNCONNECTED,
      DIA(15) => NLW_gen_ram_data_7_ram_DIA_15_UNCONNECTED,
      DIA(14) => NLW_gen_ram_data_7_ram_DIA_14_UNCONNECTED,
      DIA(13) => NLW_gen_ram_data_7_ram_DIA_13_UNCONNECTED,
      DIA(12) => NLW_gen_ram_data_7_ram_DIA_12_UNCONNECTED,
      DIA(11) => NLW_gen_ram_data_7_ram_DIA_11_UNCONNECTED,
      DIA(10) => NLW_gen_ram_data_7_ram_DIA_10_UNCONNECTED,
      DIA(9) => NLW_gen_ram_data_7_ram_DIA_9_UNCONNECTED,
      DIA(8) => NLW_gen_ram_data_7_ram_DIA_8_UNCONNECTED,
      DIA(7) => dma_wrdata(63),
      DIA(6) => dma_wrdata(62),
      DIA(5) => dma_wrdata(61),
      DIA(4) => dma_wrdata(60),
      DIA(3) => dma_wrdata(59),
      DIA(2) => dma_wrdata(58),
      DIA(1) => dma_wrdata(57),
      DIA(0) => dma_wrdata(56),
      DIB(31) => NLW_gen_ram_data_7_ram_DIB_31_UNCONNECTED,
      DIB(30) => NLW_gen_ram_data_7_ram_DIB_30_UNCONNECTED,
      DIB(29) => NLW_gen_ram_data_7_ram_DIB_29_UNCONNECTED,
      DIB(28) => NLW_gen_ram_data_7_ram_DIB_28_UNCONNECTED,
      DIB(27) => NLW_gen_ram_data_7_ram_DIB_27_UNCONNECTED,
      DIB(26) => NLW_gen_ram_data_7_ram_DIB_26_UNCONNECTED,
      DIB(25) => NLW_gen_ram_data_7_ram_DIB_25_UNCONNECTED,
      DIB(24) => NLW_gen_ram_data_7_ram_DIB_24_UNCONNECTED,
      DIB(23) => NLW_gen_ram_data_7_ram_DIB_23_UNCONNECTED,
      DIB(22) => NLW_gen_ram_data_7_ram_DIB_22_UNCONNECTED,
      DIB(21) => NLW_gen_ram_data_7_ram_DIB_21_UNCONNECTED,
      DIB(20) => NLW_gen_ram_data_7_ram_DIB_20_UNCONNECTED,
      DIB(19) => NLW_gen_ram_data_7_ram_DIB_19_UNCONNECTED,
      DIB(18) => NLW_gen_ram_data_7_ram_DIB_18_UNCONNECTED,
      DIB(17) => NLW_gen_ram_data_7_ram_DIB_17_UNCONNECTED,
      DIB(16) => NLW_gen_ram_data_7_ram_DIB_16_UNCONNECTED,
      DIB(15) => NLW_gen_ram_data_7_ram_DIB_15_UNCONNECTED,
      DIB(14) => NLW_gen_ram_data_7_ram_DIB_14_UNCONNECTED,
      DIB(13) => NLW_gen_ram_data_7_ram_DIB_13_UNCONNECTED,
      DIB(12) => NLW_gen_ram_data_7_ram_DIB_12_UNCONNECTED,
      DIB(11) => NLW_gen_ram_data_7_ram_DIB_11_UNCONNECTED,
      DIB(10) => NLW_gen_ram_data_7_ram_DIB_10_UNCONNECTED,
      DIB(9) => NLW_gen_ram_data_7_ram_DIB_9_UNCONNECTED,
      DIB(8) => NLW_gen_ram_data_7_ram_DIB_8_UNCONNECTED,
      DIB(7) => ext_fifo_disp_back_data(63),
      DIB(6) => ext_fifo_disp_back_data(62),
      DIB(5) => ext_fifo_disp_back_data(61),
      DIB(4) => ext_fifo_disp_back_data(60),
      DIB(3) => ext_fifo_disp_back_data(59),
      DIB(2) => ext_fifo_disp_back_data(58),
      DIB(1) => ext_fifo_disp_back_data(57),
      DIB(0) => ext_fifo_disp_back_data(56),
      DIPA(3) => NLW_gen_ram_data_7_ram_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_gen_ram_data_7_ram_DIPA_2_UNCONNECTED,
      DIPA(1) => NLW_gen_ram_data_7_ram_DIPA_1_UNCONNECTED,
      DIPA(0) => N0,
      DIPB(3) => NLW_gen_ram_data_7_ram_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_gen_ram_data_7_ram_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_gen_ram_data_7_ram_DIPB_1_UNCONNECTED,
      DIPB(0) => N0,
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => ext_fifo_disp_back_data_we,
      WEB(2) => ext_fifo_disp_back_data_we,
      WEB(1) => ext_fifo_disp_back_data_we,
      WEB(0) => ext_fifo_disp_back_data_we,
      DOA(31) => NLW_gen_ram_data_7_ram_DOA_31_UNCONNECTED,
      DOA(30) => NLW_gen_ram_data_7_ram_DOA_30_UNCONNECTED,
      DOA(29) => NLW_gen_ram_data_7_ram_DOA_29_UNCONNECTED,
      DOA(28) => NLW_gen_ram_data_7_ram_DOA_28_UNCONNECTED,
      DOA(27) => NLW_gen_ram_data_7_ram_DOA_27_UNCONNECTED,
      DOA(26) => NLW_gen_ram_data_7_ram_DOA_26_UNCONNECTED,
      DOA(25) => NLW_gen_ram_data_7_ram_DOA_25_UNCONNECTED,
      DOA(24) => NLW_gen_ram_data_7_ram_DOA_24_UNCONNECTED,
      DOA(23) => NLW_gen_ram_data_7_ram_DOA_23_UNCONNECTED,
      DOA(22) => NLW_gen_ram_data_7_ram_DOA_22_UNCONNECTED,
      DOA(21) => NLW_gen_ram_data_7_ram_DOA_21_UNCONNECTED,
      DOA(20) => NLW_gen_ram_data_7_ram_DOA_20_UNCONNECTED,
      DOA(19) => NLW_gen_ram_data_7_ram_DOA_19_UNCONNECTED,
      DOA(18) => NLW_gen_ram_data_7_ram_DOA_18_UNCONNECTED,
      DOA(17) => NLW_gen_ram_data_7_ram_DOA_17_UNCONNECTED,
      DOA(16) => NLW_gen_ram_data_7_ram_DOA_16_UNCONNECTED,
      DOA(15) => NLW_gen_ram_data_7_ram_DOA_15_UNCONNECTED,
      DOA(14) => NLW_gen_ram_data_7_ram_DOA_14_UNCONNECTED,
      DOA(13) => NLW_gen_ram_data_7_ram_DOA_13_UNCONNECTED,
      DOA(12) => NLW_gen_ram_data_7_ram_DOA_12_UNCONNECTED,
      DOA(11) => NLW_gen_ram_data_7_ram_DOA_11_UNCONNECTED,
      DOA(10) => NLW_gen_ram_data_7_ram_DOA_10_UNCONNECTED,
      DOA(9) => NLW_gen_ram_data_7_ram_DOA_9_UNCONNECTED,
      DOA(8) => NLW_gen_ram_data_7_ram_DOA_8_UNCONNECTED,
      DOA(7) => dma_rddata(63),
      DOA(6) => dma_rddata(62),
      DOA(5) => dma_rddata(61),
      DOA(4) => dma_rddata(60),
      DOA(3) => dma_rddata(59),
      DOA(2) => dma_rddata(58),
      DOA(1) => dma_rddata(57),
      DOA(0) => dma_rddata(56),
      DOB(31) => NLW_gen_ram_data_7_ram_DOB_31_UNCONNECTED,
      DOB(30) => NLW_gen_ram_data_7_ram_DOB_30_UNCONNECTED,
      DOB(29) => NLW_gen_ram_data_7_ram_DOB_29_UNCONNECTED,
      DOB(28) => NLW_gen_ram_data_7_ram_DOB_28_UNCONNECTED,
      DOB(27) => NLW_gen_ram_data_7_ram_DOB_27_UNCONNECTED,
      DOB(26) => NLW_gen_ram_data_7_ram_DOB_26_UNCONNECTED,
      DOB(25) => NLW_gen_ram_data_7_ram_DOB_25_UNCONNECTED,
      DOB(24) => NLW_gen_ram_data_7_ram_DOB_24_UNCONNECTED,
      DOB(23) => NLW_gen_ram_data_7_ram_DOB_23_UNCONNECTED,
      DOB(22) => NLW_gen_ram_data_7_ram_DOB_22_UNCONNECTED,
      DOB(21) => NLW_gen_ram_data_7_ram_DOB_21_UNCONNECTED,
      DOB(20) => NLW_gen_ram_data_7_ram_DOB_20_UNCONNECTED,
      DOB(19) => NLW_gen_ram_data_7_ram_DOB_19_UNCONNECTED,
      DOB(18) => NLW_gen_ram_data_7_ram_DOB_18_UNCONNECTED,
      DOB(17) => NLW_gen_ram_data_7_ram_DOB_17_UNCONNECTED,
      DOB(16) => NLW_gen_ram_data_7_ram_DOB_16_UNCONNECTED,
      DOB(15) => NLW_gen_ram_data_7_ram_DOB_15_UNCONNECTED,
      DOB(14) => NLW_gen_ram_data_7_ram_DOB_14_UNCONNECTED,
      DOB(13) => NLW_gen_ram_data_7_ram_DOB_13_UNCONNECTED,
      DOB(12) => NLW_gen_ram_data_7_ram_DOB_12_UNCONNECTED,
      DOB(11) => NLW_gen_ram_data_7_ram_DOB_11_UNCONNECTED,
      DOB(10) => NLW_gen_ram_data_7_ram_DOB_10_UNCONNECTED,
      DOB(9) => NLW_gen_ram_data_7_ram_DOB_9_UNCONNECTED,
      DOB(8) => NLW_gen_ram_data_7_ram_DOB_8_UNCONNECTED,
      DOB(7) => ext_fifo_disp_data(63),
      DOB(6) => ext_fifo_disp_data(62),
      DOB(5) => ext_fifo_disp_data(61),
      DOB(4) => ext_fifo_disp_data(60),
      DOB(3) => ext_fifo_disp_data(59),
      DOB(2) => ext_fifo_disp_data(58),
      DOB(1) => ext_fifo_disp_data(57),
      DOB(0) => ext_fifo_disp_data(56),
      DOPA(3) => NLW_gen_ram_data_7_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_gen_ram_data_7_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_gen_ram_data_7_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_gen_ram_data_7_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_gen_ram_data_7_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_gen_ram_data_7_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_gen_ram_data_7_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_gen_ram_data_7_ram_DOPB_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_dma_adr is
  port (
    clk : in STD_LOGIC := 'X'; 
    pci_size_z : out STD_LOGIC; 
    pci_rw : out STD_LOGIC; 
    reg41_wr : in STD_LOGIC := 'X'; 
    dma_chn : in STD_LOGIC := 'X'; 
    pci_adr : out STD_LOGIC_VECTOR ( 39 downto 0 ); 
    reg0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    dsc_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
    dsc_adr_h : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dsc_size : in STD_LOGIC_VECTOR ( 23 downto 0 ) 
  );
end ctrl_dma_adr;

architecture STRUCTURE of ctrl_dma_adr is
  signal N1 : STD_LOGIC; 
  signal n2 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_12_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_13_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_14_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_15_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_16_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_17_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_18_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_19_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_20_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_21_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_22_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_23_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_24_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_25_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_26_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_27_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_28_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_29_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_30_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_31_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_32_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_33_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_34_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_35_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_36_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_37_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_38_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_39_Q : STD_LOGIC; 
  signal reg410_wr : STD_LOGIC; 
  signal NLW_gen_ram_0_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_0_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_1_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_1_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_2_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_2_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_3_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_3_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_4_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_4_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_5_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_5_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_6_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_6_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_7_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_7_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_8_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_8_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_9_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_9_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_10_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_10_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_11_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_11_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_12_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_12_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_13_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_13_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_14_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_14_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_15_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_15_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_16_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_16_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_17_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_17_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_18_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_18_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_19_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_19_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_20_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_20_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_21_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_21_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_22_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_22_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_23_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_23_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_24_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_24_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_25_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_25_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_26_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_26_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_27_ram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_27_ram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram2_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_low_0_ram_low_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_low_1_ram_low_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_low_2_ram_low_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PATTERNDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_OVERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_UNDERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYCASCIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_MULTSIGNIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_PCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_P_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_BCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACIN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_ACOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp0_CARRYOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PATTERNDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_OVERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_UNDERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYCASCIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_MULTSIGNIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_PCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_P_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_BCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACIN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_ACOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp1_CARRYOUT_0_UNCONNECTED : STD_LOGIC; 
  signal port_c1 : STD_LOGIC_VECTOR ( 27 downto 0 ); 
  signal port_p0 : STD_LOGIC_VECTOR ( 27 downto 0 ); 
  signal port_p1 : STD_LOGIC_VECTOR ( 27 downto 0 ); 
begin
  pci_adr(39) <= NlwRenamedSig_OI_pci_adr_39_Q;
  pci_adr(38) <= NlwRenamedSig_OI_pci_adr_38_Q;
  pci_adr(37) <= NlwRenamedSig_OI_pci_adr_37_Q;
  pci_adr(36) <= NlwRenamedSig_OI_pci_adr_36_Q;
  pci_adr(35) <= NlwRenamedSig_OI_pci_adr_35_Q;
  pci_adr(34) <= NlwRenamedSig_OI_pci_adr_34_Q;
  pci_adr(33) <= NlwRenamedSig_OI_pci_adr_33_Q;
  pci_adr(32) <= NlwRenamedSig_OI_pci_adr_32_Q;
  pci_adr(31) <= NlwRenamedSig_OI_pci_adr_31_Q;
  pci_adr(30) <= NlwRenamedSig_OI_pci_adr_30_Q;
  pci_adr(29) <= NlwRenamedSig_OI_pci_adr_29_Q;
  pci_adr(28) <= NlwRenamedSig_OI_pci_adr_28_Q;
  pci_adr(27) <= NlwRenamedSig_OI_pci_adr_27_Q;
  pci_adr(26) <= NlwRenamedSig_OI_pci_adr_26_Q;
  pci_adr(25) <= NlwRenamedSig_OI_pci_adr_25_Q;
  pci_adr(24) <= NlwRenamedSig_OI_pci_adr_24_Q;
  pci_adr(23) <= NlwRenamedSig_OI_pci_adr_23_Q;
  pci_adr(22) <= NlwRenamedSig_OI_pci_adr_22_Q;
  pci_adr(21) <= NlwRenamedSig_OI_pci_adr_21_Q;
  pci_adr(20) <= NlwRenamedSig_OI_pci_adr_20_Q;
  pci_adr(19) <= NlwRenamedSig_OI_pci_adr_19_Q;
  pci_adr(18) <= NlwRenamedSig_OI_pci_adr_18_Q;
  pci_adr(17) <= NlwRenamedSig_OI_pci_adr_17_Q;
  pci_adr(16) <= NlwRenamedSig_OI_pci_adr_16_Q;
  pci_adr(15) <= NlwRenamedSig_OI_pci_adr_15_Q;
  pci_adr(14) <= NlwRenamedSig_OI_pci_adr_14_Q;
  pci_adr(13) <= NlwRenamedSig_OI_pci_adr_13_Q;
  pci_adr(12) <= NlwRenamedSig_OI_pci_adr_12_Q;
  pci_adr(8) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(7) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(6) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(5) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(4) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(3) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(2) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(1) <= NlwRenamedSig_OI_pci_adr_0_Q;
  pci_adr(0) <= NlwRenamedSig_OI_pci_adr_0_Q;
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_pci_adr_0_Q
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  gen_ram_0_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(0),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_12_Q,
      DPO => NLW_gen_ram_0_ram0_DPO_UNCONNECTED
    );
  gen_ram_0_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(0),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(0),
      DPO => NLW_gen_ram_0_ram1_DPO_UNCONNECTED
    );
  gen_ram_1_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(1),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_13_Q,
      DPO => NLW_gen_ram_1_ram0_DPO_UNCONNECTED
    );
  gen_ram_1_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(1),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(1),
      DPO => NLW_gen_ram_1_ram1_DPO_UNCONNECTED
    );
  gen_ram_2_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(2),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_14_Q,
      DPO => NLW_gen_ram_2_ram0_DPO_UNCONNECTED
    );
  gen_ram_2_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(2),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(2),
      DPO => NLW_gen_ram_2_ram1_DPO_UNCONNECTED
    );
  gen_ram_3_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(3),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_15_Q,
      DPO => NLW_gen_ram_3_ram0_DPO_UNCONNECTED
    );
  gen_ram_3_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(3),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(3),
      DPO => NLW_gen_ram_3_ram1_DPO_UNCONNECTED
    );
  gen_ram_4_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(4),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_16_Q,
      DPO => NLW_gen_ram_4_ram0_DPO_UNCONNECTED
    );
  gen_ram_4_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(4),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(4),
      DPO => NLW_gen_ram_4_ram1_DPO_UNCONNECTED
    );
  gen_ram_5_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(5),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_17_Q,
      DPO => NLW_gen_ram_5_ram0_DPO_UNCONNECTED
    );
  gen_ram_5_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(5),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(5),
      DPO => NLW_gen_ram_5_ram1_DPO_UNCONNECTED
    );
  gen_ram_6_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(6),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_18_Q,
      DPO => NLW_gen_ram_6_ram0_DPO_UNCONNECTED
    );
  gen_ram_6_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(6),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(6),
      DPO => NLW_gen_ram_6_ram1_DPO_UNCONNECTED
    );
  gen_ram_7_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(7),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_19_Q,
      DPO => NLW_gen_ram_7_ram0_DPO_UNCONNECTED
    );
  gen_ram_7_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(7),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(7),
      DPO => NLW_gen_ram_7_ram1_DPO_UNCONNECTED
    );
  gen_ram_8_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(8),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_20_Q,
      DPO => NLW_gen_ram_8_ram0_DPO_UNCONNECTED
    );
  gen_ram_8_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(8),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(8),
      DPO => NLW_gen_ram_8_ram1_DPO_UNCONNECTED
    );
  gen_ram_9_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(9),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_21_Q,
      DPO => NLW_gen_ram_9_ram0_DPO_UNCONNECTED
    );
  gen_ram_9_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(9),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(9),
      DPO => NLW_gen_ram_9_ram1_DPO_UNCONNECTED
    );
  gen_ram_10_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(10),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_22_Q,
      DPO => NLW_gen_ram_10_ram0_DPO_UNCONNECTED
    );
  gen_ram_10_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(10),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(10),
      DPO => NLW_gen_ram_10_ram1_DPO_UNCONNECTED
    );
  gen_ram_11_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(11),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_23_Q,
      DPO => NLW_gen_ram_11_ram0_DPO_UNCONNECTED
    );
  gen_ram_11_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(11),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(11),
      DPO => NLW_gen_ram_11_ram1_DPO_UNCONNECTED
    );
  gen_ram_12_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(12),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_24_Q,
      DPO => NLW_gen_ram_12_ram0_DPO_UNCONNECTED
    );
  gen_ram_12_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(12),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(12),
      DPO => NLW_gen_ram_12_ram1_DPO_UNCONNECTED
    );
  gen_ram_13_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(13),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_25_Q,
      DPO => NLW_gen_ram_13_ram0_DPO_UNCONNECTED
    );
  gen_ram_13_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(13),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(13),
      DPO => NLW_gen_ram_13_ram1_DPO_UNCONNECTED
    );
  gen_ram_14_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(14),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_26_Q,
      DPO => NLW_gen_ram_14_ram0_DPO_UNCONNECTED
    );
  gen_ram_14_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(14),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(14),
      DPO => NLW_gen_ram_14_ram1_DPO_UNCONNECTED
    );
  gen_ram_15_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(15),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_27_Q,
      DPO => NLW_gen_ram_15_ram0_DPO_UNCONNECTED
    );
  gen_ram_15_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(15),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(15),
      DPO => NLW_gen_ram_15_ram1_DPO_UNCONNECTED
    );
  gen_ram_16_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(16),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_28_Q,
      DPO => NLW_gen_ram_16_ram0_DPO_UNCONNECTED
    );
  gen_ram_16_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(16),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(16),
      DPO => NLW_gen_ram_16_ram1_DPO_UNCONNECTED
    );
  gen_ram_17_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(17),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_29_Q,
      DPO => NLW_gen_ram_17_ram0_DPO_UNCONNECTED
    );
  gen_ram_17_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(17),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(17),
      DPO => NLW_gen_ram_17_ram1_DPO_UNCONNECTED
    );
  gen_ram_18_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(18),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_30_Q,
      DPO => NLW_gen_ram_18_ram0_DPO_UNCONNECTED
    );
  gen_ram_18_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(18),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(18),
      DPO => NLW_gen_ram_18_ram1_DPO_UNCONNECTED
    );
  gen_ram_19_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(19),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_31_Q,
      DPO => NLW_gen_ram_19_ram0_DPO_UNCONNECTED
    );
  gen_ram_19_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(19),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(19),
      DPO => NLW_gen_ram_19_ram1_DPO_UNCONNECTED
    );
  gen_ram_20_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(20),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_32_Q,
      DPO => NLW_gen_ram_20_ram0_DPO_UNCONNECTED
    );
  gen_ram_20_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(20),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(20),
      DPO => NLW_gen_ram_20_ram1_DPO_UNCONNECTED
    );
  gen_ram_21_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(21),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_33_Q,
      DPO => NLW_gen_ram_21_ram0_DPO_UNCONNECTED
    );
  gen_ram_21_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(21),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(21),
      DPO => NLW_gen_ram_21_ram1_DPO_UNCONNECTED
    );
  gen_ram_22_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(22),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_34_Q,
      DPO => NLW_gen_ram_22_ram0_DPO_UNCONNECTED
    );
  gen_ram_22_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(22),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(22),
      DPO => NLW_gen_ram_22_ram1_DPO_UNCONNECTED
    );
  gen_ram_23_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(23),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_35_Q,
      DPO => NLW_gen_ram_23_ram0_DPO_UNCONNECTED
    );
  gen_ram_23_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(23),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(23),
      DPO => NLW_gen_ram_23_ram1_DPO_UNCONNECTED
    );
  gen_ram_24_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(24),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_36_Q,
      DPO => NLW_gen_ram_24_ram0_DPO_UNCONNECTED
    );
  gen_ram_24_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(24),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(24),
      DPO => NLW_gen_ram_24_ram1_DPO_UNCONNECTED
    );
  gen_ram_25_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(25),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_37_Q,
      DPO => NLW_gen_ram_25_ram0_DPO_UNCONNECTED
    );
  gen_ram_25_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(25),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(25),
      DPO => NLW_gen_ram_25_ram1_DPO_UNCONNECTED
    );
  gen_ram_26_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(26),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_38_Q,
      DPO => NLW_gen_ram_26_ram0_DPO_UNCONNECTED
    );
  gen_ram_26_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(26),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(26),
      DPO => NLW_gen_ram_26_ram1_DPO_UNCONNECTED
    );
  gen_ram_27_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p0(27),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => NlwRenamedSig_OI_pci_adr_39_Q,
      DPO => NLW_gen_ram_27_ram0_DPO_UNCONNECTED
    );
  gen_ram_27_ram1 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => port_p1(27),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => port_c1(27),
      DPO => NLW_gen_ram_27_ram1_DPO_UNCONNECTED
    );
  ram2 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => dsc_size(0),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg410_wr,
      SPO => pci_rw,
      DPO => NLW_ram2_DPO_UNCONNECTED
    );
  gen_ram_low_0_ram_low : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => dsc_adr(1),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => pci_adr(9),
      DPO => NLW_gen_ram_low_0_ram_low_DPO_UNCONNECTED
    );
  gen_ram_low_1_ram_low : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => dsc_adr(2),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => pci_adr(10),
      DPO => NLW_gen_ram_low_1_ram_low_DPO_UNCONNECTED
    );
  gen_ram_low_2_ram_low : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_pci_adr_0_Q,
      A2 => NlwRenamedSig_OI_pci_adr_0_Q,
      A3 => NlwRenamedSig_OI_pci_adr_0_Q,
      D => dsc_adr(3),
      DPRA0 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA1 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA2 => NlwRenamedSig_OI_pci_adr_0_Q,
      DPRA3 => N1,
      WCLK => clk,
      WE => reg41_wr,
      SPO => pci_adr(11),
      DPO => NLW_gen_ram_low_2_ram_low_DPO_UNCONNECTED
    );
  gen_dsp48_dsp0 : DSP48E
    generic map(
      AREG => 1,
      ACASCREG => 1,
      BREG => 1,
      BCASCREG => 1,
      B_INPUT => "DIRECT",
      CARRYINREG => 1,
      CARRYINSELREG => 1,
      CREG => 1,
      USE_MULT => "MULT_S",
      MREG => 1,
      OPMODEREG => 1,
      PREG => 1,
      ALUMODEREG => 1,
      MULTCARRYINREG => 1,
      A_INPUT => "DIRECT",
      USE_SIMD => "ONE48",
      USE_PATTERN_DETECT => "NO_PATDET",
      PATTERN => X"000000000000",
      SEL_PATTERN => "PATTERN",
      SEL_MASK => "MASK",
      SEL_ROUNDING_MASK => "SEL_MASK",
      AUTORESET_PATTERN_DETECT => FALSE,
      AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
      MASK => X"3FFFFFFFFFFF"
    )
    port map (
      CARRYIN => reg0(2),
      CEA1 => N1,
      CEA2 => N1,
      CEB1 => N1,
      CEB2 => N1,
      CEC => N1,
      CECTRL => N1,
      CEP => N1,
      CEM => N1,
      CECARRYIN => N1,
      CEMULTCARRYIN => N1,
      CLK => clk,
      RSTA => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTB => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTC => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTCTRL => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTP => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTM => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTALLCARRYIN => NlwRenamedSig_OI_pci_adr_0_Q,
      CEALUMODE => N1,
      RSTALUMODE => NlwRenamedSig_OI_pci_adr_0_Q,
      PATTERNBDETECT => NLW_gen_dsp48_dsp0_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_gen_dsp48_dsp0_PATTERNDETECT_UNCONNECTED,
      OVERFLOW => NLW_gen_dsp48_dsp0_OVERFLOW_UNCONNECTED,
      UNDERFLOW => NLW_gen_dsp48_dsp0_UNDERFLOW_UNCONNECTED,
      CARRYCASCIN => NLW_gen_dsp48_dsp0_CARRYCASCIN_UNCONNECTED,
      CARRYCASCOUT => NLW_gen_dsp48_dsp0_CARRYCASCOUT_UNCONNECTED,
      MULTSIGNIN => NLW_gen_dsp48_dsp0_MULTSIGNIN_UNCONNECTED,
      MULTSIGNOUT => NLW_gen_dsp48_dsp0_MULTSIGNOUT_UNCONNECTED,
      A(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(27) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(26) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(25) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(24) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(23) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(22) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(21) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(20) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(19) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(18) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(9) => dsc_adr_h(7),
      A(8) => dsc_adr_h(6),
      A(7) => dsc_adr_h(5),
      A(6) => dsc_adr_h(4),
      A(5) => dsc_adr_h(3),
      A(4) => dsc_adr_h(2),
      A(3) => dsc_adr_h(1),
      A(2) => dsc_adr_h(0),
      A(1) => dsc_adr(23),
      A(0) => dsc_adr(22),
      PCIN(47) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(46) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(45) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(44) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(43) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(42) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(41) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(40) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(39) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(38) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(37) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(36) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(35) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(34) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(33) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(32) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(31) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(30) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(27) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(26) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(25) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(24) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(23) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(22) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(21) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(20) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(19) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(18) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(9) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(8) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(7) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(5) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(4) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      B(17) => dsc_adr(21),
      B(16) => dsc_adr(20),
      B(15) => dsc_adr(19),
      B(14) => dsc_adr(18),
      B(13) => dsc_adr(17),
      B(12) => dsc_adr(16),
      B(11) => dsc_adr(15),
      B(10) => dsc_adr(14),
      B(9) => dsc_adr(13),
      B(8) => dsc_adr(12),
      B(7) => dsc_adr(11),
      B(6) => dsc_adr(10),
      B(5) => dsc_adr(9),
      B(4) => dsc_adr(8),
      B(3) => dsc_adr(7),
      B(2) => dsc_adr(6),
      B(1) => dsc_adr(5),
      B(0) => dsc_adr(4),
      C(47) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(46) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(45) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(44) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(43) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(42) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(41) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(40) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(39) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(38) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(37) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(36) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(35) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(34) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(33) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(32) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(31) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(30) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(27) => NlwRenamedSig_OI_pci_adr_39_Q,
      C(26) => NlwRenamedSig_OI_pci_adr_38_Q,
      C(25) => NlwRenamedSig_OI_pci_adr_37_Q,
      C(24) => NlwRenamedSig_OI_pci_adr_36_Q,
      C(23) => NlwRenamedSig_OI_pci_adr_35_Q,
      C(22) => NlwRenamedSig_OI_pci_adr_34_Q,
      C(21) => NlwRenamedSig_OI_pci_adr_33_Q,
      C(20) => NlwRenamedSig_OI_pci_adr_32_Q,
      C(19) => NlwRenamedSig_OI_pci_adr_31_Q,
      C(18) => NlwRenamedSig_OI_pci_adr_30_Q,
      C(17) => NlwRenamedSig_OI_pci_adr_29_Q,
      C(16) => NlwRenamedSig_OI_pci_adr_28_Q,
      C(15) => NlwRenamedSig_OI_pci_adr_27_Q,
      C(14) => NlwRenamedSig_OI_pci_adr_26_Q,
      C(13) => NlwRenamedSig_OI_pci_adr_25_Q,
      C(12) => NlwRenamedSig_OI_pci_adr_24_Q,
      C(11) => NlwRenamedSig_OI_pci_adr_23_Q,
      C(10) => NlwRenamedSig_OI_pci_adr_22_Q,
      C(9) => NlwRenamedSig_OI_pci_adr_21_Q,
      C(8) => NlwRenamedSig_OI_pci_adr_20_Q,
      C(7) => NlwRenamedSig_OI_pci_adr_19_Q,
      C(6) => NlwRenamedSig_OI_pci_adr_18_Q,
      C(5) => NlwRenamedSig_OI_pci_adr_17_Q,
      C(4) => NlwRenamedSig_OI_pci_adr_16_Q,
      C(3) => NlwRenamedSig_OI_pci_adr_15_Q,
      C(2) => NlwRenamedSig_OI_pci_adr_14_Q,
      C(1) => NlwRenamedSig_OI_pci_adr_13_Q,
      C(0) => NlwRenamedSig_OI_pci_adr_12_Q,
      CARRYINSEL(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      CARRYINSEL(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      CARRYINSEL(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(5) => reg0(2),
      OPMODE(4) => reg0(2),
      OPMODE(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(1) => n2,
      OPMODE(0) => n2,
      BCIN(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(9) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(8) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(7) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(5) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(4) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCOUT(47) => NLW_gen_dsp48_dsp0_PCOUT_47_UNCONNECTED,
      PCOUT(46) => NLW_gen_dsp48_dsp0_PCOUT_46_UNCONNECTED,
      PCOUT(45) => NLW_gen_dsp48_dsp0_PCOUT_45_UNCONNECTED,
      PCOUT(44) => NLW_gen_dsp48_dsp0_PCOUT_44_UNCONNECTED,
      PCOUT(43) => NLW_gen_dsp48_dsp0_PCOUT_43_UNCONNECTED,
      PCOUT(42) => NLW_gen_dsp48_dsp0_PCOUT_42_UNCONNECTED,
      PCOUT(41) => NLW_gen_dsp48_dsp0_PCOUT_41_UNCONNECTED,
      PCOUT(40) => NLW_gen_dsp48_dsp0_PCOUT_40_UNCONNECTED,
      PCOUT(39) => NLW_gen_dsp48_dsp0_PCOUT_39_UNCONNECTED,
      PCOUT(38) => NLW_gen_dsp48_dsp0_PCOUT_38_UNCONNECTED,
      PCOUT(37) => NLW_gen_dsp48_dsp0_PCOUT_37_UNCONNECTED,
      PCOUT(36) => NLW_gen_dsp48_dsp0_PCOUT_36_UNCONNECTED,
      PCOUT(35) => NLW_gen_dsp48_dsp0_PCOUT_35_UNCONNECTED,
      PCOUT(34) => NLW_gen_dsp48_dsp0_PCOUT_34_UNCONNECTED,
      PCOUT(33) => NLW_gen_dsp48_dsp0_PCOUT_33_UNCONNECTED,
      PCOUT(32) => NLW_gen_dsp48_dsp0_PCOUT_32_UNCONNECTED,
      PCOUT(31) => NLW_gen_dsp48_dsp0_PCOUT_31_UNCONNECTED,
      PCOUT(30) => NLW_gen_dsp48_dsp0_PCOUT_30_UNCONNECTED,
      PCOUT(29) => NLW_gen_dsp48_dsp0_PCOUT_29_UNCONNECTED,
      PCOUT(28) => NLW_gen_dsp48_dsp0_PCOUT_28_UNCONNECTED,
      PCOUT(27) => NLW_gen_dsp48_dsp0_PCOUT_27_UNCONNECTED,
      PCOUT(26) => NLW_gen_dsp48_dsp0_PCOUT_26_UNCONNECTED,
      PCOUT(25) => NLW_gen_dsp48_dsp0_PCOUT_25_UNCONNECTED,
      PCOUT(24) => NLW_gen_dsp48_dsp0_PCOUT_24_UNCONNECTED,
      PCOUT(23) => NLW_gen_dsp48_dsp0_PCOUT_23_UNCONNECTED,
      PCOUT(22) => NLW_gen_dsp48_dsp0_PCOUT_22_UNCONNECTED,
      PCOUT(21) => NLW_gen_dsp48_dsp0_PCOUT_21_UNCONNECTED,
      PCOUT(20) => NLW_gen_dsp48_dsp0_PCOUT_20_UNCONNECTED,
      PCOUT(19) => NLW_gen_dsp48_dsp0_PCOUT_19_UNCONNECTED,
      PCOUT(18) => NLW_gen_dsp48_dsp0_PCOUT_18_UNCONNECTED,
      PCOUT(17) => NLW_gen_dsp48_dsp0_PCOUT_17_UNCONNECTED,
      PCOUT(16) => NLW_gen_dsp48_dsp0_PCOUT_16_UNCONNECTED,
      PCOUT(15) => NLW_gen_dsp48_dsp0_PCOUT_15_UNCONNECTED,
      PCOUT(14) => NLW_gen_dsp48_dsp0_PCOUT_14_UNCONNECTED,
      PCOUT(13) => NLW_gen_dsp48_dsp0_PCOUT_13_UNCONNECTED,
      PCOUT(12) => NLW_gen_dsp48_dsp0_PCOUT_12_UNCONNECTED,
      PCOUT(11) => NLW_gen_dsp48_dsp0_PCOUT_11_UNCONNECTED,
      PCOUT(10) => NLW_gen_dsp48_dsp0_PCOUT_10_UNCONNECTED,
      PCOUT(9) => NLW_gen_dsp48_dsp0_PCOUT_9_UNCONNECTED,
      PCOUT(8) => NLW_gen_dsp48_dsp0_PCOUT_8_UNCONNECTED,
      PCOUT(7) => NLW_gen_dsp48_dsp0_PCOUT_7_UNCONNECTED,
      PCOUT(6) => NLW_gen_dsp48_dsp0_PCOUT_6_UNCONNECTED,
      PCOUT(5) => NLW_gen_dsp48_dsp0_PCOUT_5_UNCONNECTED,
      PCOUT(4) => NLW_gen_dsp48_dsp0_PCOUT_4_UNCONNECTED,
      PCOUT(3) => NLW_gen_dsp48_dsp0_PCOUT_3_UNCONNECTED,
      PCOUT(2) => NLW_gen_dsp48_dsp0_PCOUT_2_UNCONNECTED,
      PCOUT(1) => NLW_gen_dsp48_dsp0_PCOUT_1_UNCONNECTED,
      PCOUT(0) => NLW_gen_dsp48_dsp0_PCOUT_0_UNCONNECTED,
      P(47) => NLW_gen_dsp48_dsp0_P_47_UNCONNECTED,
      P(46) => NLW_gen_dsp48_dsp0_P_46_UNCONNECTED,
      P(45) => NLW_gen_dsp48_dsp0_P_45_UNCONNECTED,
      P(44) => NLW_gen_dsp48_dsp0_P_44_UNCONNECTED,
      P(43) => NLW_gen_dsp48_dsp0_P_43_UNCONNECTED,
      P(42) => NLW_gen_dsp48_dsp0_P_42_UNCONNECTED,
      P(41) => NLW_gen_dsp48_dsp0_P_41_UNCONNECTED,
      P(40) => NLW_gen_dsp48_dsp0_P_40_UNCONNECTED,
      P(39) => NLW_gen_dsp48_dsp0_P_39_UNCONNECTED,
      P(38) => NLW_gen_dsp48_dsp0_P_38_UNCONNECTED,
      P(37) => NLW_gen_dsp48_dsp0_P_37_UNCONNECTED,
      P(36) => NLW_gen_dsp48_dsp0_P_36_UNCONNECTED,
      P(35) => NLW_gen_dsp48_dsp0_P_35_UNCONNECTED,
      P(34) => NLW_gen_dsp48_dsp0_P_34_UNCONNECTED,
      P(33) => NLW_gen_dsp48_dsp0_P_33_UNCONNECTED,
      P(32) => NLW_gen_dsp48_dsp0_P_32_UNCONNECTED,
      P(31) => NLW_gen_dsp48_dsp0_P_31_UNCONNECTED,
      P(30) => NLW_gen_dsp48_dsp0_P_30_UNCONNECTED,
      P(29) => NLW_gen_dsp48_dsp0_P_29_UNCONNECTED,
      P(28) => NLW_gen_dsp48_dsp0_P_28_UNCONNECTED,
      P(27) => port_p0(27),
      P(26) => port_p0(26),
      P(25) => port_p0(25),
      P(24) => port_p0(24),
      P(23) => port_p0(23),
      P(22) => port_p0(22),
      P(21) => port_p0(21),
      P(20) => port_p0(20),
      P(19) => port_p0(19),
      P(18) => port_p0(18),
      P(17) => port_p0(17),
      P(16) => port_p0(16),
      P(15) => port_p0(15),
      P(14) => port_p0(14),
      P(13) => port_p0(13),
      P(12) => port_p0(12),
      P(11) => port_p0(11),
      P(10) => port_p0(10),
      P(9) => port_p0(9),
      P(8) => port_p0(8),
      P(7) => port_p0(7),
      P(6) => port_p0(6),
      P(5) => port_p0(5),
      P(4) => port_p0(4),
      P(3) => port_p0(3),
      P(2) => port_p0(2),
      P(1) => port_p0(1),
      P(0) => port_p0(0),
      BCOUT(17) => NLW_gen_dsp48_dsp0_BCOUT_17_UNCONNECTED,
      BCOUT(16) => NLW_gen_dsp48_dsp0_BCOUT_16_UNCONNECTED,
      BCOUT(15) => NLW_gen_dsp48_dsp0_BCOUT_15_UNCONNECTED,
      BCOUT(14) => NLW_gen_dsp48_dsp0_BCOUT_14_UNCONNECTED,
      BCOUT(13) => NLW_gen_dsp48_dsp0_BCOUT_13_UNCONNECTED,
      BCOUT(12) => NLW_gen_dsp48_dsp0_BCOUT_12_UNCONNECTED,
      BCOUT(11) => NLW_gen_dsp48_dsp0_BCOUT_11_UNCONNECTED,
      BCOUT(10) => NLW_gen_dsp48_dsp0_BCOUT_10_UNCONNECTED,
      BCOUT(9) => NLW_gen_dsp48_dsp0_BCOUT_9_UNCONNECTED,
      BCOUT(8) => NLW_gen_dsp48_dsp0_BCOUT_8_UNCONNECTED,
      BCOUT(7) => NLW_gen_dsp48_dsp0_BCOUT_7_UNCONNECTED,
      BCOUT(6) => NLW_gen_dsp48_dsp0_BCOUT_6_UNCONNECTED,
      BCOUT(5) => NLW_gen_dsp48_dsp0_BCOUT_5_UNCONNECTED,
      BCOUT(4) => NLW_gen_dsp48_dsp0_BCOUT_4_UNCONNECTED,
      BCOUT(3) => NLW_gen_dsp48_dsp0_BCOUT_3_UNCONNECTED,
      BCOUT(2) => NLW_gen_dsp48_dsp0_BCOUT_2_UNCONNECTED,
      BCOUT(1) => NLW_gen_dsp48_dsp0_BCOUT_1_UNCONNECTED,
      BCOUT(0) => NLW_gen_dsp48_dsp0_BCOUT_0_UNCONNECTED,
      ACIN(29) => NLW_gen_dsp48_dsp0_ACIN_29_UNCONNECTED,
      ACIN(28) => NLW_gen_dsp48_dsp0_ACIN_28_UNCONNECTED,
      ACIN(27) => NLW_gen_dsp48_dsp0_ACIN_27_UNCONNECTED,
      ACIN(26) => NLW_gen_dsp48_dsp0_ACIN_26_UNCONNECTED,
      ACIN(25) => NLW_gen_dsp48_dsp0_ACIN_25_UNCONNECTED,
      ACIN(24) => NLW_gen_dsp48_dsp0_ACIN_24_UNCONNECTED,
      ACIN(23) => NLW_gen_dsp48_dsp0_ACIN_23_UNCONNECTED,
      ACIN(22) => NLW_gen_dsp48_dsp0_ACIN_22_UNCONNECTED,
      ACIN(21) => NLW_gen_dsp48_dsp0_ACIN_21_UNCONNECTED,
      ACIN(20) => NLW_gen_dsp48_dsp0_ACIN_20_UNCONNECTED,
      ACIN(19) => NLW_gen_dsp48_dsp0_ACIN_19_UNCONNECTED,
      ACIN(18) => NLW_gen_dsp48_dsp0_ACIN_18_UNCONNECTED,
      ACIN(17) => NLW_gen_dsp48_dsp0_ACIN_17_UNCONNECTED,
      ACIN(16) => NLW_gen_dsp48_dsp0_ACIN_16_UNCONNECTED,
      ACIN(15) => NLW_gen_dsp48_dsp0_ACIN_15_UNCONNECTED,
      ACIN(14) => NLW_gen_dsp48_dsp0_ACIN_14_UNCONNECTED,
      ACIN(13) => NLW_gen_dsp48_dsp0_ACIN_13_UNCONNECTED,
      ACIN(12) => NLW_gen_dsp48_dsp0_ACIN_12_UNCONNECTED,
      ACIN(11) => NLW_gen_dsp48_dsp0_ACIN_11_UNCONNECTED,
      ACIN(10) => NLW_gen_dsp48_dsp0_ACIN_10_UNCONNECTED,
      ACIN(9) => NLW_gen_dsp48_dsp0_ACIN_9_UNCONNECTED,
      ACIN(8) => NLW_gen_dsp48_dsp0_ACIN_8_UNCONNECTED,
      ACIN(7) => NLW_gen_dsp48_dsp0_ACIN_7_UNCONNECTED,
      ACIN(6) => NLW_gen_dsp48_dsp0_ACIN_6_UNCONNECTED,
      ACIN(5) => NLW_gen_dsp48_dsp0_ACIN_5_UNCONNECTED,
      ACIN(4) => NLW_gen_dsp48_dsp0_ACIN_4_UNCONNECTED,
      ACIN(3) => NLW_gen_dsp48_dsp0_ACIN_3_UNCONNECTED,
      ACIN(2) => NLW_gen_dsp48_dsp0_ACIN_2_UNCONNECTED,
      ACIN(1) => NLW_gen_dsp48_dsp0_ACIN_1_UNCONNECTED,
      ACIN(0) => NLW_gen_dsp48_dsp0_ACIN_0_UNCONNECTED,
      ACOUT(29) => NLW_gen_dsp48_dsp0_ACOUT_29_UNCONNECTED,
      ACOUT(28) => NLW_gen_dsp48_dsp0_ACOUT_28_UNCONNECTED,
      ACOUT(27) => NLW_gen_dsp48_dsp0_ACOUT_27_UNCONNECTED,
      ACOUT(26) => NLW_gen_dsp48_dsp0_ACOUT_26_UNCONNECTED,
      ACOUT(25) => NLW_gen_dsp48_dsp0_ACOUT_25_UNCONNECTED,
      ACOUT(24) => NLW_gen_dsp48_dsp0_ACOUT_24_UNCONNECTED,
      ACOUT(23) => NLW_gen_dsp48_dsp0_ACOUT_23_UNCONNECTED,
      ACOUT(22) => NLW_gen_dsp48_dsp0_ACOUT_22_UNCONNECTED,
      ACOUT(21) => NLW_gen_dsp48_dsp0_ACOUT_21_UNCONNECTED,
      ACOUT(20) => NLW_gen_dsp48_dsp0_ACOUT_20_UNCONNECTED,
      ACOUT(19) => NLW_gen_dsp48_dsp0_ACOUT_19_UNCONNECTED,
      ACOUT(18) => NLW_gen_dsp48_dsp0_ACOUT_18_UNCONNECTED,
      ACOUT(17) => NLW_gen_dsp48_dsp0_ACOUT_17_UNCONNECTED,
      ACOUT(16) => NLW_gen_dsp48_dsp0_ACOUT_16_UNCONNECTED,
      ACOUT(15) => NLW_gen_dsp48_dsp0_ACOUT_15_UNCONNECTED,
      ACOUT(14) => NLW_gen_dsp48_dsp0_ACOUT_14_UNCONNECTED,
      ACOUT(13) => NLW_gen_dsp48_dsp0_ACOUT_13_UNCONNECTED,
      ACOUT(12) => NLW_gen_dsp48_dsp0_ACOUT_12_UNCONNECTED,
      ACOUT(11) => NLW_gen_dsp48_dsp0_ACOUT_11_UNCONNECTED,
      ACOUT(10) => NLW_gen_dsp48_dsp0_ACOUT_10_UNCONNECTED,
      ACOUT(9) => NLW_gen_dsp48_dsp0_ACOUT_9_UNCONNECTED,
      ACOUT(8) => NLW_gen_dsp48_dsp0_ACOUT_8_UNCONNECTED,
      ACOUT(7) => NLW_gen_dsp48_dsp0_ACOUT_7_UNCONNECTED,
      ACOUT(6) => NLW_gen_dsp48_dsp0_ACOUT_6_UNCONNECTED,
      ACOUT(5) => NLW_gen_dsp48_dsp0_ACOUT_5_UNCONNECTED,
      ACOUT(4) => NLW_gen_dsp48_dsp0_ACOUT_4_UNCONNECTED,
      ACOUT(3) => NLW_gen_dsp48_dsp0_ACOUT_3_UNCONNECTED,
      ACOUT(2) => NLW_gen_dsp48_dsp0_ACOUT_2_UNCONNECTED,
      ACOUT(1) => NLW_gen_dsp48_dsp0_ACOUT_1_UNCONNECTED,
      ACOUT(0) => NLW_gen_dsp48_dsp0_ACOUT_0_UNCONNECTED,
      CARRYOUT(3) => NLW_gen_dsp48_dsp0_CARRYOUT_3_UNCONNECTED,
      CARRYOUT(2) => NLW_gen_dsp48_dsp0_CARRYOUT_2_UNCONNECTED,
      CARRYOUT(1) => NLW_gen_dsp48_dsp0_CARRYOUT_1_UNCONNECTED,
      CARRYOUT(0) => NLW_gen_dsp48_dsp0_CARRYOUT_0_UNCONNECTED
    );
  gen_dsp48_dsp1 : DSP48E
    generic map(
      AREG => 1,
      ACASCREG => 1,
      BREG => 1,
      BCASCREG => 1,
      B_INPUT => "DIRECT",
      CARRYINREG => 1,
      CARRYINSELREG => 1,
      CREG => 1,
      USE_MULT => "MULT_S",
      MREG => 1,
      OPMODEREG => 1,
      PREG => 1,
      ALUMODEREG => 1,
      MULTCARRYINREG => 1,
      A_INPUT => "DIRECT",
      USE_SIMD => "ONE48",
      USE_PATTERN_DETECT => "NO_PATDET",
      PATTERN => X"000000000000",
      SEL_PATTERN => "PATTERN",
      SEL_MASK => "MASK",
      SEL_ROUNDING_MASK => "SEL_MASK",
      AUTORESET_PATTERN_DETECT => FALSE,
      AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
      MASK => X"3FFFFFFFFFFF"
    )
    port map (
      CARRYIN => reg0(2),
      CEA1 => N1,
      CEA2 => N1,
      CEB1 => N1,
      CEB2 => N1,
      CEC => N1,
      CECTRL => N1,
      CEP => N1,
      CEM => N1,
      CECARRYIN => N1,
      CEMULTCARRYIN => N1,
      CLK => clk,
      RSTA => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTB => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTC => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTCTRL => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTP => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTM => NlwRenamedSig_OI_pci_adr_0_Q,
      RSTALLCARRYIN => NlwRenamedSig_OI_pci_adr_0_Q,
      CEALUMODE => N1,
      RSTALUMODE => NlwRenamedSig_OI_pci_adr_0_Q,
      PATTERNBDETECT => NLW_gen_dsp48_dsp1_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_gen_dsp48_dsp1_PATTERNDETECT_UNCONNECTED,
      OVERFLOW => NLW_gen_dsp48_dsp1_OVERFLOW_UNCONNECTED,
      UNDERFLOW => NLW_gen_dsp48_dsp1_UNDERFLOW_UNCONNECTED,
      CARRYCASCIN => NLW_gen_dsp48_dsp1_CARRYCASCIN_UNCONNECTED,
      CARRYCASCOUT => NLW_gen_dsp48_dsp1_CARRYCASCOUT_UNCONNECTED,
      MULTSIGNIN => NLW_gen_dsp48_dsp1_MULTSIGNIN_UNCONNECTED,
      MULTSIGNOUT => NLW_gen_dsp48_dsp1_MULTSIGNOUT_UNCONNECTED,
      A(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(27) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(26) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(25) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(24) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(23) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(22) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(21) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(20) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(19) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(18) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(9) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(8) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(7) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(5) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(4) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      A(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(47) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(46) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(45) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(44) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(43) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(42) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(41) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(40) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(39) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(38) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(37) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(36) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(35) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(34) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(33) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(32) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(31) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(30) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(27) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(26) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(25) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(24) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(23) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(22) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(21) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(20) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(19) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(18) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(9) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(8) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(7) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(5) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(4) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      PCIN(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      B(17) => dsc_size(21),
      B(16) => dsc_size(20),
      B(15) => dsc_size(19),
      B(14) => dsc_size(18),
      B(13) => dsc_size(17),
      B(12) => dsc_size(16),
      B(11) => dsc_size(15),
      B(10) => dsc_size(14),
      B(9) => dsc_size(13),
      B(8) => dsc_size(12),
      B(7) => dsc_size(11),
      B(6) => dsc_size(10),
      B(5) => dsc_size(9),
      B(4) => dsc_size(8),
      B(3) => dsc_size(7),
      B(2) => dsc_size(6),
      B(1) => dsc_size(5),
      B(0) => dsc_size(4),
      C(47) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(46) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(45) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(44) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(43) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(42) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(41) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(40) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(39) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(38) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(37) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(36) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(35) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(34) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(33) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(32) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(31) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(30) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(29) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(28) => NlwRenamedSig_OI_pci_adr_0_Q,
      C(27) => port_c1(27),
      C(26) => port_c1(26),
      C(25) => port_c1(25),
      C(24) => port_c1(24),
      C(23) => port_c1(23),
      C(22) => port_c1(22),
      C(21) => port_c1(21),
      C(20) => port_c1(20),
      C(19) => port_c1(19),
      C(18) => port_c1(18),
      C(17) => port_c1(17),
      C(16) => port_c1(16),
      C(15) => port_c1(15),
      C(14) => port_c1(14),
      C(13) => port_c1(13),
      C(12) => port_c1(12),
      C(11) => port_c1(11),
      C(10) => port_c1(10),
      C(9) => port_c1(9),
      C(8) => port_c1(8),
      C(7) => port_c1(7),
      C(6) => port_c1(6),
      C(5) => port_c1(5),
      C(4) => port_c1(4),
      C(3) => port_c1(3),
      C(2) => port_c1(2),
      C(1) => port_c1(1),
      C(0) => port_c1(0),
      CARRYINSEL(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      CARRYINSEL(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      CARRYINSEL(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(5) => reg0(2),
      OPMODE(4) => reg0(2),
      OPMODE(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      OPMODE(1) => n2,
      OPMODE(0) => n2,
      BCIN(17) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(16) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(15) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(14) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(13) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(12) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(11) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(10) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(9) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(8) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(7) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(6) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(5) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(4) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(1) => NlwRenamedSig_OI_pci_adr_0_Q,
      BCIN(0) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(3) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(2) => NlwRenamedSig_OI_pci_adr_0_Q,
      ALUMODE(1) => reg0(2),
      ALUMODE(0) => reg0(2),
      PCOUT(47) => NLW_gen_dsp48_dsp1_PCOUT_47_UNCONNECTED,
      PCOUT(46) => NLW_gen_dsp48_dsp1_PCOUT_46_UNCONNECTED,
      PCOUT(45) => NLW_gen_dsp48_dsp1_PCOUT_45_UNCONNECTED,
      PCOUT(44) => NLW_gen_dsp48_dsp1_PCOUT_44_UNCONNECTED,
      PCOUT(43) => NLW_gen_dsp48_dsp1_PCOUT_43_UNCONNECTED,
      PCOUT(42) => NLW_gen_dsp48_dsp1_PCOUT_42_UNCONNECTED,
      PCOUT(41) => NLW_gen_dsp48_dsp1_PCOUT_41_UNCONNECTED,
      PCOUT(40) => NLW_gen_dsp48_dsp1_PCOUT_40_UNCONNECTED,
      PCOUT(39) => NLW_gen_dsp48_dsp1_PCOUT_39_UNCONNECTED,
      PCOUT(38) => NLW_gen_dsp48_dsp1_PCOUT_38_UNCONNECTED,
      PCOUT(37) => NLW_gen_dsp48_dsp1_PCOUT_37_UNCONNECTED,
      PCOUT(36) => NLW_gen_dsp48_dsp1_PCOUT_36_UNCONNECTED,
      PCOUT(35) => NLW_gen_dsp48_dsp1_PCOUT_35_UNCONNECTED,
      PCOUT(34) => NLW_gen_dsp48_dsp1_PCOUT_34_UNCONNECTED,
      PCOUT(33) => NLW_gen_dsp48_dsp1_PCOUT_33_UNCONNECTED,
      PCOUT(32) => NLW_gen_dsp48_dsp1_PCOUT_32_UNCONNECTED,
      PCOUT(31) => NLW_gen_dsp48_dsp1_PCOUT_31_UNCONNECTED,
      PCOUT(30) => NLW_gen_dsp48_dsp1_PCOUT_30_UNCONNECTED,
      PCOUT(29) => NLW_gen_dsp48_dsp1_PCOUT_29_UNCONNECTED,
      PCOUT(28) => NLW_gen_dsp48_dsp1_PCOUT_28_UNCONNECTED,
      PCOUT(27) => NLW_gen_dsp48_dsp1_PCOUT_27_UNCONNECTED,
      PCOUT(26) => NLW_gen_dsp48_dsp1_PCOUT_26_UNCONNECTED,
      PCOUT(25) => NLW_gen_dsp48_dsp1_PCOUT_25_UNCONNECTED,
      PCOUT(24) => NLW_gen_dsp48_dsp1_PCOUT_24_UNCONNECTED,
      PCOUT(23) => NLW_gen_dsp48_dsp1_PCOUT_23_UNCONNECTED,
      PCOUT(22) => NLW_gen_dsp48_dsp1_PCOUT_22_UNCONNECTED,
      PCOUT(21) => NLW_gen_dsp48_dsp1_PCOUT_21_UNCONNECTED,
      PCOUT(20) => NLW_gen_dsp48_dsp1_PCOUT_20_UNCONNECTED,
      PCOUT(19) => NLW_gen_dsp48_dsp1_PCOUT_19_UNCONNECTED,
      PCOUT(18) => NLW_gen_dsp48_dsp1_PCOUT_18_UNCONNECTED,
      PCOUT(17) => NLW_gen_dsp48_dsp1_PCOUT_17_UNCONNECTED,
      PCOUT(16) => NLW_gen_dsp48_dsp1_PCOUT_16_UNCONNECTED,
      PCOUT(15) => NLW_gen_dsp48_dsp1_PCOUT_15_UNCONNECTED,
      PCOUT(14) => NLW_gen_dsp48_dsp1_PCOUT_14_UNCONNECTED,
      PCOUT(13) => NLW_gen_dsp48_dsp1_PCOUT_13_UNCONNECTED,
      PCOUT(12) => NLW_gen_dsp48_dsp1_PCOUT_12_UNCONNECTED,
      PCOUT(11) => NLW_gen_dsp48_dsp1_PCOUT_11_UNCONNECTED,
      PCOUT(10) => NLW_gen_dsp48_dsp1_PCOUT_10_UNCONNECTED,
      PCOUT(9) => NLW_gen_dsp48_dsp1_PCOUT_9_UNCONNECTED,
      PCOUT(8) => NLW_gen_dsp48_dsp1_PCOUT_8_UNCONNECTED,
      PCOUT(7) => NLW_gen_dsp48_dsp1_PCOUT_7_UNCONNECTED,
      PCOUT(6) => NLW_gen_dsp48_dsp1_PCOUT_6_UNCONNECTED,
      PCOUT(5) => NLW_gen_dsp48_dsp1_PCOUT_5_UNCONNECTED,
      PCOUT(4) => NLW_gen_dsp48_dsp1_PCOUT_4_UNCONNECTED,
      PCOUT(3) => NLW_gen_dsp48_dsp1_PCOUT_3_UNCONNECTED,
      PCOUT(2) => NLW_gen_dsp48_dsp1_PCOUT_2_UNCONNECTED,
      PCOUT(1) => NLW_gen_dsp48_dsp1_PCOUT_1_UNCONNECTED,
      PCOUT(0) => NLW_gen_dsp48_dsp1_PCOUT_0_UNCONNECTED,
      P(47) => pci_size_z,
      P(46) => NLW_gen_dsp48_dsp1_P_46_UNCONNECTED,
      P(45) => NLW_gen_dsp48_dsp1_P_45_UNCONNECTED,
      P(44) => NLW_gen_dsp48_dsp1_P_44_UNCONNECTED,
      P(43) => NLW_gen_dsp48_dsp1_P_43_UNCONNECTED,
      P(42) => NLW_gen_dsp48_dsp1_P_42_UNCONNECTED,
      P(41) => NLW_gen_dsp48_dsp1_P_41_UNCONNECTED,
      P(40) => NLW_gen_dsp48_dsp1_P_40_UNCONNECTED,
      P(39) => NLW_gen_dsp48_dsp1_P_39_UNCONNECTED,
      P(38) => NLW_gen_dsp48_dsp1_P_38_UNCONNECTED,
      P(37) => NLW_gen_dsp48_dsp1_P_37_UNCONNECTED,
      P(36) => NLW_gen_dsp48_dsp1_P_36_UNCONNECTED,
      P(35) => NLW_gen_dsp48_dsp1_P_35_UNCONNECTED,
      P(34) => NLW_gen_dsp48_dsp1_P_34_UNCONNECTED,
      P(33) => NLW_gen_dsp48_dsp1_P_33_UNCONNECTED,
      P(32) => NLW_gen_dsp48_dsp1_P_32_UNCONNECTED,
      P(31) => NLW_gen_dsp48_dsp1_P_31_UNCONNECTED,
      P(30) => NLW_gen_dsp48_dsp1_P_30_UNCONNECTED,
      P(29) => NLW_gen_dsp48_dsp1_P_29_UNCONNECTED,
      P(28) => NLW_gen_dsp48_dsp1_P_28_UNCONNECTED,
      P(27) => port_p1(27),
      P(26) => port_p1(26),
      P(25) => port_p1(25),
      P(24) => port_p1(24),
      P(23) => port_p1(23),
      P(22) => port_p1(22),
      P(21) => port_p1(21),
      P(20) => port_p1(20),
      P(19) => port_p1(19),
      P(18) => port_p1(18),
      P(17) => port_p1(17),
      P(16) => port_p1(16),
      P(15) => port_p1(15),
      P(14) => port_p1(14),
      P(13) => port_p1(13),
      P(12) => port_p1(12),
      P(11) => port_p1(11),
      P(10) => port_p1(10),
      P(9) => port_p1(9),
      P(8) => port_p1(8),
      P(7) => port_p1(7),
      P(6) => port_p1(6),
      P(5) => port_p1(5),
      P(4) => port_p1(4),
      P(3) => port_p1(3),
      P(2) => port_p1(2),
      P(1) => port_p1(1),
      P(0) => port_p1(0),
      BCOUT(17) => NLW_gen_dsp48_dsp1_BCOUT_17_UNCONNECTED,
      BCOUT(16) => NLW_gen_dsp48_dsp1_BCOUT_16_UNCONNECTED,
      BCOUT(15) => NLW_gen_dsp48_dsp1_BCOUT_15_UNCONNECTED,
      BCOUT(14) => NLW_gen_dsp48_dsp1_BCOUT_14_UNCONNECTED,
      BCOUT(13) => NLW_gen_dsp48_dsp1_BCOUT_13_UNCONNECTED,
      BCOUT(12) => NLW_gen_dsp48_dsp1_BCOUT_12_UNCONNECTED,
      BCOUT(11) => NLW_gen_dsp48_dsp1_BCOUT_11_UNCONNECTED,
      BCOUT(10) => NLW_gen_dsp48_dsp1_BCOUT_10_UNCONNECTED,
      BCOUT(9) => NLW_gen_dsp48_dsp1_BCOUT_9_UNCONNECTED,
      BCOUT(8) => NLW_gen_dsp48_dsp1_BCOUT_8_UNCONNECTED,
      BCOUT(7) => NLW_gen_dsp48_dsp1_BCOUT_7_UNCONNECTED,
      BCOUT(6) => NLW_gen_dsp48_dsp1_BCOUT_6_UNCONNECTED,
      BCOUT(5) => NLW_gen_dsp48_dsp1_BCOUT_5_UNCONNECTED,
      BCOUT(4) => NLW_gen_dsp48_dsp1_BCOUT_4_UNCONNECTED,
      BCOUT(3) => NLW_gen_dsp48_dsp1_BCOUT_3_UNCONNECTED,
      BCOUT(2) => NLW_gen_dsp48_dsp1_BCOUT_2_UNCONNECTED,
      BCOUT(1) => NLW_gen_dsp48_dsp1_BCOUT_1_UNCONNECTED,
      BCOUT(0) => NLW_gen_dsp48_dsp1_BCOUT_0_UNCONNECTED,
      ACIN(29) => NLW_gen_dsp48_dsp1_ACIN_29_UNCONNECTED,
      ACIN(28) => NLW_gen_dsp48_dsp1_ACIN_28_UNCONNECTED,
      ACIN(27) => NLW_gen_dsp48_dsp1_ACIN_27_UNCONNECTED,
      ACIN(26) => NLW_gen_dsp48_dsp1_ACIN_26_UNCONNECTED,
      ACIN(25) => NLW_gen_dsp48_dsp1_ACIN_25_UNCONNECTED,
      ACIN(24) => NLW_gen_dsp48_dsp1_ACIN_24_UNCONNECTED,
      ACIN(23) => NLW_gen_dsp48_dsp1_ACIN_23_UNCONNECTED,
      ACIN(22) => NLW_gen_dsp48_dsp1_ACIN_22_UNCONNECTED,
      ACIN(21) => NLW_gen_dsp48_dsp1_ACIN_21_UNCONNECTED,
      ACIN(20) => NLW_gen_dsp48_dsp1_ACIN_20_UNCONNECTED,
      ACIN(19) => NLW_gen_dsp48_dsp1_ACIN_19_UNCONNECTED,
      ACIN(18) => NLW_gen_dsp48_dsp1_ACIN_18_UNCONNECTED,
      ACIN(17) => NLW_gen_dsp48_dsp1_ACIN_17_UNCONNECTED,
      ACIN(16) => NLW_gen_dsp48_dsp1_ACIN_16_UNCONNECTED,
      ACIN(15) => NLW_gen_dsp48_dsp1_ACIN_15_UNCONNECTED,
      ACIN(14) => NLW_gen_dsp48_dsp1_ACIN_14_UNCONNECTED,
      ACIN(13) => NLW_gen_dsp48_dsp1_ACIN_13_UNCONNECTED,
      ACIN(12) => NLW_gen_dsp48_dsp1_ACIN_12_UNCONNECTED,
      ACIN(11) => NLW_gen_dsp48_dsp1_ACIN_11_UNCONNECTED,
      ACIN(10) => NLW_gen_dsp48_dsp1_ACIN_10_UNCONNECTED,
      ACIN(9) => NLW_gen_dsp48_dsp1_ACIN_9_UNCONNECTED,
      ACIN(8) => NLW_gen_dsp48_dsp1_ACIN_8_UNCONNECTED,
      ACIN(7) => NLW_gen_dsp48_dsp1_ACIN_7_UNCONNECTED,
      ACIN(6) => NLW_gen_dsp48_dsp1_ACIN_6_UNCONNECTED,
      ACIN(5) => NLW_gen_dsp48_dsp1_ACIN_5_UNCONNECTED,
      ACIN(4) => NLW_gen_dsp48_dsp1_ACIN_4_UNCONNECTED,
      ACIN(3) => NLW_gen_dsp48_dsp1_ACIN_3_UNCONNECTED,
      ACIN(2) => NLW_gen_dsp48_dsp1_ACIN_2_UNCONNECTED,
      ACIN(1) => NLW_gen_dsp48_dsp1_ACIN_1_UNCONNECTED,
      ACIN(0) => NLW_gen_dsp48_dsp1_ACIN_0_UNCONNECTED,
      ACOUT(29) => NLW_gen_dsp48_dsp1_ACOUT_29_UNCONNECTED,
      ACOUT(28) => NLW_gen_dsp48_dsp1_ACOUT_28_UNCONNECTED,
      ACOUT(27) => NLW_gen_dsp48_dsp1_ACOUT_27_UNCONNECTED,
      ACOUT(26) => NLW_gen_dsp48_dsp1_ACOUT_26_UNCONNECTED,
      ACOUT(25) => NLW_gen_dsp48_dsp1_ACOUT_25_UNCONNECTED,
      ACOUT(24) => NLW_gen_dsp48_dsp1_ACOUT_24_UNCONNECTED,
      ACOUT(23) => NLW_gen_dsp48_dsp1_ACOUT_23_UNCONNECTED,
      ACOUT(22) => NLW_gen_dsp48_dsp1_ACOUT_22_UNCONNECTED,
      ACOUT(21) => NLW_gen_dsp48_dsp1_ACOUT_21_UNCONNECTED,
      ACOUT(20) => NLW_gen_dsp48_dsp1_ACOUT_20_UNCONNECTED,
      ACOUT(19) => NLW_gen_dsp48_dsp1_ACOUT_19_UNCONNECTED,
      ACOUT(18) => NLW_gen_dsp48_dsp1_ACOUT_18_UNCONNECTED,
      ACOUT(17) => NLW_gen_dsp48_dsp1_ACOUT_17_UNCONNECTED,
      ACOUT(16) => NLW_gen_dsp48_dsp1_ACOUT_16_UNCONNECTED,
      ACOUT(15) => NLW_gen_dsp48_dsp1_ACOUT_15_UNCONNECTED,
      ACOUT(14) => NLW_gen_dsp48_dsp1_ACOUT_14_UNCONNECTED,
      ACOUT(13) => NLW_gen_dsp48_dsp1_ACOUT_13_UNCONNECTED,
      ACOUT(12) => NLW_gen_dsp48_dsp1_ACOUT_12_UNCONNECTED,
      ACOUT(11) => NLW_gen_dsp48_dsp1_ACOUT_11_UNCONNECTED,
      ACOUT(10) => NLW_gen_dsp48_dsp1_ACOUT_10_UNCONNECTED,
      ACOUT(9) => NLW_gen_dsp48_dsp1_ACOUT_9_UNCONNECTED,
      ACOUT(8) => NLW_gen_dsp48_dsp1_ACOUT_8_UNCONNECTED,
      ACOUT(7) => NLW_gen_dsp48_dsp1_ACOUT_7_UNCONNECTED,
      ACOUT(6) => NLW_gen_dsp48_dsp1_ACOUT_6_UNCONNECTED,
      ACOUT(5) => NLW_gen_dsp48_dsp1_ACOUT_5_UNCONNECTED,
      ACOUT(4) => NLW_gen_dsp48_dsp1_ACOUT_4_UNCONNECTED,
      ACOUT(3) => NLW_gen_dsp48_dsp1_ACOUT_3_UNCONNECTED,
      ACOUT(2) => NLW_gen_dsp48_dsp1_ACOUT_2_UNCONNECTED,
      ACOUT(1) => NLW_gen_dsp48_dsp1_ACOUT_1_UNCONNECTED,
      ACOUT(0) => NLW_gen_dsp48_dsp1_ACOUT_0_UNCONNECTED,
      CARRYOUT(3) => NLW_gen_dsp48_dsp1_CARRYOUT_3_UNCONNECTED,
      CARRYOUT(2) => NLW_gen_dsp48_dsp1_CARRYOUT_2_UNCONNECTED,
      CARRYOUT(1) => NLW_gen_dsp48_dsp1_CARRYOUT_1_UNCONNECTED,
      CARRYOUT(0) => NLW_gen_dsp48_dsp1_CARRYOUT_0_UNCONNECTED
    );
  reg410_wr1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => reg0(2),
      I1 => reg41_wr,
      O => reg410_wr
    );
  n21_INV_0 : INV
    port map (
      I => reg0(2),
      O => n2
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_dma_ext_cmd is
  port (
    clk : in STD_LOGIC := 'X'; 
    tx_rd_size : out STD_LOGIC; 
    tx_req_rd : out STD_LOGIC; 
    tx_req_wr : out STD_LOGIC; 
    tx_ext_fifo_complete_error : in STD_LOGIC := 'X'; 
    rstp : in STD_LOGIC := 'X'; 
    rx_ext_fifo_data_we : in STD_LOGIC := 'X'; 
    dma_change_adr : in STD_LOGIC := 'X'; 
    tx_ext_fifo_complete_ok : in STD_LOGIC := 'X'; 
    dma_chn : in STD_LOGIC := 'X'; 
    dma_cmd_status : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    test : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    tx_pci_adr : out STD_LOGIC_VECTOR ( 39 downto 8 ); 
    dsc_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
    rx_ext_fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    tx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    dsc_adr_h : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    dsc_size : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
    dma_reg0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end ctrl_dma_ext_cmd;

architecture STRUCTURE of ctrl_dma_ext_cmd is
  component ctrl_dma_adr
    port (
      clk : in STD_LOGIC := 'X'; 
      pci_size_z : out STD_LOGIC; 
      pci_rw : out STD_LOGIC; 
      reg41_wr : in STD_LOGIC := 'X'; 
      dma_chn : in STD_LOGIC := 'X'; 
      pci_adr : out STD_LOGIC_VECTOR ( 39 downto 0 ); 
      reg0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      dsc_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
      dsc_adr_h : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dsc_size : in STD_LOGIC_VECTOR ( 23 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_dma_cmd_error : STD_LOGIC; 
  signal dma_cmd_error_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dma_cmd_rdy : STD_LOGIC; 
  signal dma_cmd_rdy_mux0000 : STD_LOGIC; 
  signal dma_rw : STD_LOGIC; 
  signal stp_FSM_FFd1_12248 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_12250 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_12252 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_12254 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal stp_cmp_eq0001_inv : STD_LOGIC; 
  signal NlwRenamedSignal_tx_rd_size : STD_LOGIC; 
  signal tx_req_rd_mux0001_norst : STD_LOGIC; 
  signal tx_req_wr_mux0001_norst : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dma_adr_pci_adr_0_UNCONNECTED : STD_LOGIC; 
begin
  tx_rd_size <= NlwRenamedSignal_tx_rd_size;
  dma_cmd_status(1) <= NlwRenamedSig_OI_dma_cmd_error;
  dma_cmd_status(0) <= NlwRenamedSig_OI_dma_cmd_rdy;
  NlwRenamedSignal_tx_rd_size <= dma_reg0(1);
  dma_cmd_rdy : FD
    port map (
      C => clk,
      D => dma_cmd_rdy_mux0000,
      Q => NlwRenamedSig_OI_dma_cmd_rdy
    );
  dma_cmd_error : FD
    port map (
      C => clk,
      D => dma_cmd_error_mux0000,
      Q => NlwRenamedSig_OI_dma_cmd_error
    );
  tx_req_rd_8891 : FDR
    port map (
      C => clk,
      D => tx_req_rd_mux0001_norst,
      R => stp_cmp_eq0001_inv,
      Q => tx_req_rd
    );
  tx_req_wr_8892 : FDR
    port map (
      C => clk,
      D => tx_req_wr_mux0001_norst,
      R => stp_cmp_eq0001_inv,
      Q => tx_req_wr
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstp,
      Q => stp_FSM_FFd1_12248
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd2_In,
      R => rstp,
      Q => stp_FSM_FFd2_12250
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_In,
      R => rstp,
      Q => stp_FSM_FFd3_12252
    );
  stp_FSM_FFd4 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd4_In,
      S => rstp,
      Q => stp_FSM_FFd4_12254
    );
  tx_req_wr_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma_rw,
      I1 => NlwRenamedSignal_tx_rd_size,
      O => tx_req_wr_mux0001_norst
    );
  tx_req_rd_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => dma_rw,
      I1 => NlwRenamedSignal_tx_rd_size,
      O => tx_req_rd_mux0001_norst
    );
  stp_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => dma_reg0(0),
      I1 => stp_FSM_FFd2_12250,
      I2 => tx_ext_fifo_complete_ok,
      I3 => stp_FSM_FFd3_12252,
      O => stp_FSM_FFd2_In
    );
  stp_FSM_FFd1_In1 : LUT4
    generic map(
      INIT => X"F020"
    )
    port map (
      I0 => stp_FSM_FFd3_12252,
      I1 => tx_ext_fifo_complete_ok,
      I2 => tx_ext_fifo_complete_error,
      I3 => stp_FSM_FFd1_12248,
      O => stp_FSM_FFd1_In
    );
  dma_cmd_rdy_mux00001 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => stp_FSM_FFd3_12252,
      I1 => NlwRenamedSig_OI_dma_cmd_rdy,
      I2 => stp_FSM_FFd2_12250,
      I3 => stp_FSM_FFd1_12248,
      O => dma_cmd_rdy_mux0000
    );
  stp_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"3232FF32"
    )
    port map (
      I0 => stp_FSM_FFd2_12250,
      I1 => dma_reg0(0),
      I2 => stp_FSM_FFd4_12254,
      I3 => stp_FSM_FFd1_12248,
      I4 => tx_ext_fifo_complete_error,
      O => stp_FSM_FFd4_In
    );
  stp_FSM_FFd3_In1 : LUT5
    generic map(
      INIT => X"888888F8"
    )
    port map (
      I0 => stp_FSM_FFd4_12254,
      I1 => dma_reg0(0),
      I2 => stp_FSM_FFd3_12252,
      I3 => tx_ext_fifo_complete_ok,
      I4 => tx_ext_fifo_complete_error,
      O => stp_FSM_FFd3_In
    );
  dma_cmd_error_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_cmd_error,
      I1 => stp_FSM_FFd2_12250,
      I2 => stp_FSM_FFd1_12248,
      I3 => stp_FSM_FFd3_12252,
      I4 => tx_ext_fifo_complete_error,
      O => dma_cmd_error_mux0000
    );
  dma_adr : ctrl_dma_adr
    port map (
      clk => clk,
      pci_size_z => dma_cmd_status(2),
      pci_rw => dma_rw,
      reg41_wr => dma_change_adr,
      dma_chn => dma_chn,
      pci_adr(39) => tx_pci_adr(39),
      pci_adr(38) => tx_pci_adr(38),
      pci_adr(37) => tx_pci_adr(37),
      pci_adr(36) => tx_pci_adr(36),
      pci_adr(35) => tx_pci_adr(35),
      pci_adr(34) => tx_pci_adr(34),
      pci_adr(33) => tx_pci_adr(33),
      pci_adr(32) => tx_pci_adr(32),
      pci_adr(31) => tx_pci_adr(31),
      pci_adr(30) => tx_pci_adr(30),
      pci_adr(29) => tx_pci_adr(29),
      pci_adr(28) => tx_pci_adr(28),
      pci_adr(27) => tx_pci_adr(27),
      pci_adr(26) => tx_pci_adr(26),
      pci_adr(25) => tx_pci_adr(25),
      pci_adr(24) => tx_pci_adr(24),
      pci_adr(23) => tx_pci_adr(23),
      pci_adr(22) => tx_pci_adr(22),
      pci_adr(21) => tx_pci_adr(21),
      pci_adr(20) => tx_pci_adr(20),
      pci_adr(19) => tx_pci_adr(19),
      pci_adr(18) => tx_pci_adr(18),
      pci_adr(17) => tx_pci_adr(17),
      pci_adr(16) => tx_pci_adr(16),
      pci_adr(15) => tx_pci_adr(15),
      pci_adr(14) => tx_pci_adr(14),
      pci_adr(13) => tx_pci_adr(13),
      pci_adr(12) => tx_pci_adr(12),
      pci_adr(11) => tx_pci_adr(11),
      pci_adr(10) => tx_pci_adr(10),
      pci_adr(9) => tx_pci_adr(9),
      pci_adr(8) => tx_pci_adr(8),
      pci_adr(7) => NLW_dma_adr_pci_adr_7_UNCONNECTED,
      pci_adr(6) => NLW_dma_adr_pci_adr_6_UNCONNECTED,
      pci_adr(5) => NLW_dma_adr_pci_adr_5_UNCONNECTED,
      pci_adr(4) => NLW_dma_adr_pci_adr_4_UNCONNECTED,
      pci_adr(3) => NLW_dma_adr_pci_adr_3_UNCONNECTED,
      pci_adr(2) => NLW_dma_adr_pci_adr_2_UNCONNECTED,
      pci_adr(1) => NLW_dma_adr_pci_adr_1_UNCONNECTED,
      pci_adr(0) => NLW_dma_adr_pci_adr_0_UNCONNECTED,
      reg0(2) => dma_reg0(2),
      reg0(1) => NlwRenamedSignal_tx_rd_size,
      reg0(0) => dma_reg0(0),
      dsc_adr(23) => dsc_adr(23),
      dsc_adr(22) => dsc_adr(22),
      dsc_adr(21) => dsc_adr(21),
      dsc_adr(20) => dsc_adr(20),
      dsc_adr(19) => dsc_adr(19),
      dsc_adr(18) => dsc_adr(18),
      dsc_adr(17) => dsc_adr(17),
      dsc_adr(16) => dsc_adr(16),
      dsc_adr(15) => dsc_adr(15),
      dsc_adr(14) => dsc_adr(14),
      dsc_adr(13) => dsc_adr(13),
      dsc_adr(12) => dsc_adr(12),
      dsc_adr(11) => dsc_adr(11),
      dsc_adr(10) => dsc_adr(10),
      dsc_adr(9) => dsc_adr(9),
      dsc_adr(8) => dsc_adr(8),
      dsc_adr(7) => dsc_adr(7),
      dsc_adr(6) => dsc_adr(6),
      dsc_adr(5) => dsc_adr(5),
      dsc_adr(4) => dsc_adr(4),
      dsc_adr(3) => dsc_adr(3),
      dsc_adr(2) => dsc_adr(2),
      dsc_adr(1) => dsc_adr(1),
      dsc_adr(0) => dsc_adr(0),
      dsc_adr_h(7) => dsc_adr_h(7),
      dsc_adr_h(6) => dsc_adr_h(6),
      dsc_adr_h(5) => dsc_adr_h(5),
      dsc_adr_h(4) => dsc_adr_h(4),
      dsc_adr_h(3) => dsc_adr_h(3),
      dsc_adr_h(2) => dsc_adr_h(2),
      dsc_adr_h(1) => dsc_adr_h(1),
      dsc_adr_h(0) => dsc_adr_h(0),
      dsc_size(23) => dsc_size(23),
      dsc_size(22) => dsc_size(22),
      dsc_size(21) => dsc_size(21),
      dsc_size(20) => dsc_size(20),
      dsc_size(19) => dsc_size(19),
      dsc_size(18) => dsc_size(18),
      dsc_size(17) => dsc_size(17),
      dsc_size(16) => dsc_size(16),
      dsc_size(15) => dsc_size(15),
      dsc_size(14) => dsc_size(14),
      dsc_size(13) => dsc_size(13),
      dsc_size(12) => dsc_size(12),
      dsc_size(11) => dsc_size(11),
      dsc_size(10) => dsc_size(10),
      dsc_size(9) => dsc_size(9),
      dsc_size(8) => dsc_size(8),
      dsc_size(7) => dsc_size(7),
      dsc_size(6) => dsc_size(6),
      dsc_size(5) => dsc_size(5),
      dsc_size(4) => dsc_size(4),
      dsc_size(3) => dsc_size(3),
      dsc_size(2) => dsc_size(2),
      dsc_size(1) => dsc_size(1),
      dsc_size(0) => dsc_size(0)
    );
  stp_cmp_eq0001_inv1_INV_0 : INV
    port map (
      I => stp_FSM_FFd3_12252,
      O => stp_cmp_eq0001_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ext_descriptor is
  port (
    clk : in STD_LOGIC := 'X'; 
    dsc_change_adr : in STD_LOGIC := 'X'; 
    dsc_load_en : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    dsc_correct : out STD_LOGIC; 
    ram0_wr : in STD_LOGIC := 'X'; 
    pci_adr_we : in STD_LOGIC := 'X'; 
    dsc_change_mode : in STD_LOGIC := 'X'; 
    dma_chn : in STD_LOGIC := 'X'; 
    pci_adr_h_we : in STD_LOGIC := 'X'; 
    dsc_adr : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
    dsc_cmd : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dsc_adr_h : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dsc_size : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
    test : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    dma_wrdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    dma_wraddr : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end ctrl_ext_descriptor;

architecture STRUCTURE of ctrl_ext_descriptor is
  signal carry : STD_LOGIC; 
  signal crc_0_not0001 : STD_LOGIC; 
  signal crc_10_xor0000 : STD_LOGIC; 
  signal crc_11_xor0000 : STD_LOGIC; 
  signal crc_12_xor0000 : STD_LOGIC; 
  signal crc_13_xor0000 : STD_LOGIC; 
  signal crc_14_xor0000 : STD_LOGIC; 
  signal crc_15_xor0000 : STD_LOGIC; 
  signal crc_1_xor0000 : STD_LOGIC; 
  signal crc_2_xor0000 : STD_LOGIC; 
  signal crc_3_xor0000 : STD_LOGIC; 
  signal crc_4_xor0000 : STD_LOGIC; 
  signal crc_5_xor0000 : STD_LOGIC; 
  signal crc_6_xor0000 : STD_LOGIC; 
  signal crc_7_xor0000 : STD_LOGIC; 
  signal crc_8_xor0000 : STD_LOGIC; 
  signal crc_9_xor0000 : STD_LOGIC; 
  signal crc_reset : STD_LOGIC; 
  signal dma_descriptor_error_11818 : STD_LOGIC; 
  signal dma_descriptor_error_or0000 : STD_LOGIC; 
  signal dma_descriptor_error_or000010_11820 : STD_LOGIC; 
  signal dma_descriptor_error_or000021_11821 : STD_LOGIC; 
  signal dma_descriptor_error_or000032_11822 : STD_LOGIC; 
  signal ram_b_wr : STD_LOGIC; 
  signal reg0_z_11998 : STD_LOGIC; 
  signal sig_error_11999 : STD_LOGIC; 
  signal sig_error_mux0001 : STD_LOGIC; 
  signal sig_error_mux000133_12001 : STD_LOGIC; 
  signal sig_error_mux000152_12002 : STD_LOGIC; 
  signal sig_error_mux00018_12003 : STD_LOGIC; 
  signal NLW_gen_ram_0_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_1_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_2_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_3_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_4_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_5_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_6_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_7_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_8_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_9_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_10_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_ram_11_ram_adr_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PATTERNDETECT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_OVERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_UNDERFLOW_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYCASCIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_MULTSIGNIN_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_PCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_P_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_BCOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACIN_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_ACOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_dsp48_dsp_CARRYOUT_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram0_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram1_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal crc : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal port_c : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal port_p : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal ram_a_in : STD_LOGIC_VECTOR ( 31 downto 24 ); 
  signal NlwRenamedSig_OI_test : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  dsc_correct <= dma_descriptor_error_11818;
  test(3) <= NlwRenamedSig_OI_test(0);
  test(2) <= NlwRenamedSig_OI_test(0);
  test(1) <= NlwRenamedSig_OI_test(0);
  test(0) <= NlwRenamedSig_OI_test(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_test(0)
    );
  XST_VCC : VCC
    port map (
      P => carry
    );
  sig_error : FDE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => sig_error_mux0001,
      Q => sig_error_11999
    );
  crc_0 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_0_not0001,
      S => crc_reset,
      Q => crc(0)
    );
  ram_a_in_24 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(0),
      Q => ram_a_in(24)
    );
  ram_a_in_30 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(6),
      Q => ram_a_in(30)
    );
  ram_a_in_25 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(1),
      Q => ram_a_in(25)
    );
  ram_a_in_31 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(7),
      Q => ram_a_in(31)
    );
  ram_a_in_26 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(2),
      Q => ram_a_in(26)
    );
  ram_a_in_27 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(3),
      Q => ram_a_in(27)
    );
  ram_a_in_28 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(4),
      Q => ram_a_in(28)
    );
  ram_a_in_29 : FDE
    port map (
      C => clk,
      CE => pci_adr_h_we,
      D => data_in(5),
      Q => ram_a_in(29)
    );
  reg0_z : FD
    port map (
      C => clk,
      D => dsc_load_en,
      Q => reg0_z_11998
    );
  dma_descriptor_error : FDR
    port map (
      C => clk,
      D => carry,
      R => dma_descriptor_error_or0000,
      Q => dma_descriptor_error_11818
    );
  crc_1 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_1_xor0000,
      S => crc_reset,
      Q => crc(1)
    );
  crc_2 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_2_xor0000,
      S => crc_reset,
      Q => crc(2)
    );
  crc_3 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_3_xor0000,
      S => crc_reset,
      Q => crc(3)
    );
  crc_4 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_4_xor0000,
      S => crc_reset,
      Q => crc(4)
    );
  crc_5 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_5_xor0000,
      S => crc_reset,
      Q => crc(5)
    );
  crc_6 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_6_xor0000,
      S => crc_reset,
      Q => crc(6)
    );
  crc_7 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_7_xor0000,
      S => crc_reset,
      Q => crc(7)
    );
  crc_8 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_8_xor0000,
      S => crc_reset,
      Q => crc(8)
    );
  crc_9 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_9_xor0000,
      S => crc_reset,
      Q => crc(9)
    );
  crc_10 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_10_xor0000,
      S => crc_reset,
      Q => crc(10)
    );
  crc_11 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_11_xor0000,
      S => crc_reset,
      Q => crc(11)
    );
  crc_12 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_12_xor0000,
      S => crc_reset,
      Q => crc(12)
    );
  crc_13 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_13_xor0000,
      S => crc_reset,
      Q => crc(13)
    );
  crc_14 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_14_xor0000,
      S => crc_reset,
      Q => crc(14)
    );
  crc_15 : FDSE
    port map (
      C => clk,
      CE => ram_b_wr,
      D => crc_15_xor0000,
      S => crc_reset,
      Q => crc(15)
    );
  gen_ram_0_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(0),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(0),
      DPO => NLW_gen_ram_0_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_1_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(1),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(1),
      DPO => NLW_gen_ram_1_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_2_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(2),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(2),
      DPO => NLW_gen_ram_2_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_3_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(3),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(3),
      DPO => NLW_gen_ram_3_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_4_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(4),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(4),
      DPO => NLW_gen_ram_4_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_5_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(5),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(5),
      DPO => NLW_gen_ram_5_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_6_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(6),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(6),
      DPO => NLW_gen_ram_6_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_7_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(7),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(7),
      DPO => NLW_gen_ram_7_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_8_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(8),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(8),
      DPO => NLW_gen_ram_8_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_9_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(9),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(9),
      DPO => NLW_gen_ram_9_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_10_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(10),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(10),
      DPO => NLW_gen_ram_10_ram_adr_DPO_UNCONNECTED
    );
  gen_ram_11_ram_adr : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => dma_chn,
      A1 => NlwRenamedSig_OI_test(0),
      A2 => NlwRenamedSig_OI_test(0),
      A3 => NlwRenamedSig_OI_test(0),
      D => port_p(11),
      DPRA0 => NlwRenamedSig_OI_test(0),
      DPRA1 => NlwRenamedSig_OI_test(0),
      DPRA2 => NlwRenamedSig_OI_test(0),
      DPRA3 => carry,
      WCLK => clk,
      WE => dsc_change_adr,
      SPO => port_c(11),
      DPO => NLW_gen_ram_11_ram_adr_DPO_UNCONNECTED
    );
  gen_dsp48_dsp : DSP48E
    generic map(
      AREG => 1,
      ACASCREG => 1,
      BREG => 1,
      BCASCREG => 1,
      B_INPUT => "DIRECT",
      CARRYINREG => 1,
      CARRYINSELREG => 1,
      CREG => 1,
      USE_MULT => "MULT_S",
      MREG => 1,
      OPMODEREG => 1,
      PREG => 1,
      ALUMODEREG => 1,
      MULTCARRYINREG => 1,
      A_INPUT => "DIRECT",
      USE_SIMD => "ONE48",
      USE_PATTERN_DETECT => "NO_PATDET",
      PATTERN => X"000000000000",
      SEL_PATTERN => "PATTERN",
      SEL_MASK => "MASK",
      SEL_ROUNDING_MASK => "SEL_MASK",
      AUTORESET_PATTERN_DETECT => FALSE,
      AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
      MASK => X"3FFFFFFFFFFF"
    )
    port map (
      CARRYIN => carry,
      CEA1 => carry,
      CEA2 => carry,
      CEB1 => carry,
      CEB2 => carry,
      CEC => carry,
      CECTRL => carry,
      CEP => carry,
      CEM => carry,
      CECARRYIN => carry,
      CEMULTCARRYIN => carry,
      CLK => clk,
      RSTA => NlwRenamedSig_OI_test(0),
      RSTB => NlwRenamedSig_OI_test(0),
      RSTC => NlwRenamedSig_OI_test(0),
      RSTCTRL => NlwRenamedSig_OI_test(0),
      RSTP => dsc_change_mode,
      RSTM => NlwRenamedSig_OI_test(0),
      RSTALLCARRYIN => NlwRenamedSig_OI_test(0),
      CEALUMODE => carry,
      RSTALUMODE => NlwRenamedSig_OI_test(0),
      PATTERNBDETECT => NLW_gen_dsp48_dsp_PATTERNBDETECT_UNCONNECTED,
      PATTERNDETECT => NLW_gen_dsp48_dsp_PATTERNDETECT_UNCONNECTED,
      OVERFLOW => NLW_gen_dsp48_dsp_OVERFLOW_UNCONNECTED,
      UNDERFLOW => NLW_gen_dsp48_dsp_UNDERFLOW_UNCONNECTED,
      CARRYCASCIN => NLW_gen_dsp48_dsp_CARRYCASCIN_UNCONNECTED,
      CARRYCASCOUT => NLW_gen_dsp48_dsp_CARRYCASCOUT_UNCONNECTED,
      MULTSIGNIN => NLW_gen_dsp48_dsp_MULTSIGNIN_UNCONNECTED,
      MULTSIGNOUT => NLW_gen_dsp48_dsp_MULTSIGNOUT_UNCONNECTED,
      A(29) => NlwRenamedSig_OI_test(0),
      A(28) => NlwRenamedSig_OI_test(0),
      A(27) => NlwRenamedSig_OI_test(0),
      A(26) => NlwRenamedSig_OI_test(0),
      A(25) => NlwRenamedSig_OI_test(0),
      A(24) => NlwRenamedSig_OI_test(0),
      A(23) => NlwRenamedSig_OI_test(0),
      A(22) => NlwRenamedSig_OI_test(0),
      A(21) => NlwRenamedSig_OI_test(0),
      A(20) => NlwRenamedSig_OI_test(0),
      A(19) => NlwRenamedSig_OI_test(0),
      A(18) => NlwRenamedSig_OI_test(0),
      A(17) => NlwRenamedSig_OI_test(0),
      A(16) => NlwRenamedSig_OI_test(0),
      A(15) => NlwRenamedSig_OI_test(0),
      A(14) => NlwRenamedSig_OI_test(0),
      A(13) => NlwRenamedSig_OI_test(0),
      A(12) => NlwRenamedSig_OI_test(0),
      A(11) => NlwRenamedSig_OI_test(0),
      A(10) => NlwRenamedSig_OI_test(0),
      A(9) => NlwRenamedSig_OI_test(0),
      A(8) => NlwRenamedSig_OI_test(0),
      A(7) => NlwRenamedSig_OI_test(0),
      A(6) => NlwRenamedSig_OI_test(0),
      A(5) => NlwRenamedSig_OI_test(0),
      A(4) => NlwRenamedSig_OI_test(0),
      A(3) => NlwRenamedSig_OI_test(0),
      A(2) => NlwRenamedSig_OI_test(0),
      A(1) => NlwRenamedSig_OI_test(0),
      A(0) => NlwRenamedSig_OI_test(0),
      PCIN(47) => NlwRenamedSig_OI_test(0),
      PCIN(46) => NlwRenamedSig_OI_test(0),
      PCIN(45) => NlwRenamedSig_OI_test(0),
      PCIN(44) => NlwRenamedSig_OI_test(0),
      PCIN(43) => NlwRenamedSig_OI_test(0),
      PCIN(42) => NlwRenamedSig_OI_test(0),
      PCIN(41) => NlwRenamedSig_OI_test(0),
      PCIN(40) => NlwRenamedSig_OI_test(0),
      PCIN(39) => NlwRenamedSig_OI_test(0),
      PCIN(38) => NlwRenamedSig_OI_test(0),
      PCIN(37) => NlwRenamedSig_OI_test(0),
      PCIN(36) => NlwRenamedSig_OI_test(0),
      PCIN(35) => NlwRenamedSig_OI_test(0),
      PCIN(34) => NlwRenamedSig_OI_test(0),
      PCIN(33) => NlwRenamedSig_OI_test(0),
      PCIN(32) => NlwRenamedSig_OI_test(0),
      PCIN(31) => NlwRenamedSig_OI_test(0),
      PCIN(30) => NlwRenamedSig_OI_test(0),
      PCIN(29) => NlwRenamedSig_OI_test(0),
      PCIN(28) => NlwRenamedSig_OI_test(0),
      PCIN(27) => NlwRenamedSig_OI_test(0),
      PCIN(26) => NlwRenamedSig_OI_test(0),
      PCIN(25) => NlwRenamedSig_OI_test(0),
      PCIN(24) => NlwRenamedSig_OI_test(0),
      PCIN(23) => NlwRenamedSig_OI_test(0),
      PCIN(22) => NlwRenamedSig_OI_test(0),
      PCIN(21) => NlwRenamedSig_OI_test(0),
      PCIN(20) => NlwRenamedSig_OI_test(0),
      PCIN(19) => NlwRenamedSig_OI_test(0),
      PCIN(18) => NlwRenamedSig_OI_test(0),
      PCIN(17) => NlwRenamedSig_OI_test(0),
      PCIN(16) => NlwRenamedSig_OI_test(0),
      PCIN(15) => NlwRenamedSig_OI_test(0),
      PCIN(14) => NlwRenamedSig_OI_test(0),
      PCIN(13) => NlwRenamedSig_OI_test(0),
      PCIN(12) => NlwRenamedSig_OI_test(0),
      PCIN(11) => NlwRenamedSig_OI_test(0),
      PCIN(10) => NlwRenamedSig_OI_test(0),
      PCIN(9) => NlwRenamedSig_OI_test(0),
      PCIN(8) => NlwRenamedSig_OI_test(0),
      PCIN(7) => NlwRenamedSig_OI_test(0),
      PCIN(6) => NlwRenamedSig_OI_test(0),
      PCIN(5) => NlwRenamedSig_OI_test(0),
      PCIN(4) => NlwRenamedSig_OI_test(0),
      PCIN(3) => NlwRenamedSig_OI_test(0),
      PCIN(2) => NlwRenamedSig_OI_test(0),
      PCIN(1) => NlwRenamedSig_OI_test(0),
      PCIN(0) => NlwRenamedSig_OI_test(0),
      B(17) => NlwRenamedSig_OI_test(0),
      B(16) => NlwRenamedSig_OI_test(0),
      B(15) => NlwRenamedSig_OI_test(0),
      B(14) => NlwRenamedSig_OI_test(0),
      B(13) => NlwRenamedSig_OI_test(0),
      B(12) => NlwRenamedSig_OI_test(0),
      B(11) => NlwRenamedSig_OI_test(0),
      B(10) => NlwRenamedSig_OI_test(0),
      B(9) => NlwRenamedSig_OI_test(0),
      B(8) => NlwRenamedSig_OI_test(0),
      B(7) => NlwRenamedSig_OI_test(0),
      B(6) => NlwRenamedSig_OI_test(0),
      B(5) => NlwRenamedSig_OI_test(0),
      B(4) => NlwRenamedSig_OI_test(0),
      B(3) => NlwRenamedSig_OI_test(0),
      B(2) => NlwRenamedSig_OI_test(0),
      B(1) => NlwRenamedSig_OI_test(0),
      B(0) => NlwRenamedSig_OI_test(0),
      C(47) => NlwRenamedSig_OI_test(0),
      C(46) => NlwRenamedSig_OI_test(0),
      C(45) => NlwRenamedSig_OI_test(0),
      C(44) => NlwRenamedSig_OI_test(0),
      C(43) => NlwRenamedSig_OI_test(0),
      C(42) => NlwRenamedSig_OI_test(0),
      C(41) => NlwRenamedSig_OI_test(0),
      C(40) => NlwRenamedSig_OI_test(0),
      C(39) => NlwRenamedSig_OI_test(0),
      C(38) => NlwRenamedSig_OI_test(0),
      C(37) => NlwRenamedSig_OI_test(0),
      C(36) => NlwRenamedSig_OI_test(0),
      C(35) => NlwRenamedSig_OI_test(0),
      C(34) => NlwRenamedSig_OI_test(0),
      C(33) => NlwRenamedSig_OI_test(0),
      C(32) => NlwRenamedSig_OI_test(0),
      C(31) => NlwRenamedSig_OI_test(0),
      C(30) => NlwRenamedSig_OI_test(0),
      C(29) => NlwRenamedSig_OI_test(0),
      C(28) => NlwRenamedSig_OI_test(0),
      C(27) => NlwRenamedSig_OI_test(0),
      C(26) => NlwRenamedSig_OI_test(0),
      C(25) => NlwRenamedSig_OI_test(0),
      C(24) => NlwRenamedSig_OI_test(0),
      C(23) => NlwRenamedSig_OI_test(0),
      C(22) => NlwRenamedSig_OI_test(0),
      C(21) => NlwRenamedSig_OI_test(0),
      C(20) => NlwRenamedSig_OI_test(0),
      C(19) => NlwRenamedSig_OI_test(0),
      C(18) => NlwRenamedSig_OI_test(0),
      C(17) => NlwRenamedSig_OI_test(0),
      C(16) => NlwRenamedSig_OI_test(0),
      C(15) => NlwRenamedSig_OI_test(0),
      C(14) => NlwRenamedSig_OI_test(0),
      C(13) => NlwRenamedSig_OI_test(0),
      C(12) => NlwRenamedSig_OI_test(0),
      C(11) => port_c(11),
      C(10) => port_c(10),
      C(9) => port_c(9),
      C(8) => port_c(8),
      C(7) => port_c(7),
      C(6) => port_c(6),
      C(5) => port_c(5),
      C(4) => port_c(4),
      C(3) => port_c(3),
      C(2) => port_c(2),
      C(1) => port_c(1),
      C(0) => port_c(0),
      CARRYINSEL(2) => NlwRenamedSig_OI_test(0),
      CARRYINSEL(1) => NlwRenamedSig_OI_test(0),
      CARRYINSEL(0) => NlwRenamedSig_OI_test(0),
      OPMODE(6) => NlwRenamedSig_OI_test(0),
      OPMODE(5) => carry,
      OPMODE(4) => carry,
      OPMODE(3) => NlwRenamedSig_OI_test(0),
      OPMODE(2) => NlwRenamedSig_OI_test(0),
      OPMODE(1) => NlwRenamedSig_OI_test(0),
      OPMODE(0) => NlwRenamedSig_OI_test(0),
      BCIN(17) => NlwRenamedSig_OI_test(0),
      BCIN(16) => NlwRenamedSig_OI_test(0),
      BCIN(15) => NlwRenamedSig_OI_test(0),
      BCIN(14) => NlwRenamedSig_OI_test(0),
      BCIN(13) => NlwRenamedSig_OI_test(0),
      BCIN(12) => NlwRenamedSig_OI_test(0),
      BCIN(11) => NlwRenamedSig_OI_test(0),
      BCIN(10) => NlwRenamedSig_OI_test(0),
      BCIN(9) => NlwRenamedSig_OI_test(0),
      BCIN(8) => NlwRenamedSig_OI_test(0),
      BCIN(7) => NlwRenamedSig_OI_test(0),
      BCIN(6) => NlwRenamedSig_OI_test(0),
      BCIN(5) => NlwRenamedSig_OI_test(0),
      BCIN(4) => NlwRenamedSig_OI_test(0),
      BCIN(3) => NlwRenamedSig_OI_test(0),
      BCIN(2) => NlwRenamedSig_OI_test(0),
      BCIN(1) => NlwRenamedSig_OI_test(0),
      BCIN(0) => NlwRenamedSig_OI_test(0),
      ALUMODE(3) => NlwRenamedSig_OI_test(0),
      ALUMODE(2) => NlwRenamedSig_OI_test(0),
      ALUMODE(1) => NlwRenamedSig_OI_test(0),
      ALUMODE(0) => NlwRenamedSig_OI_test(0),
      PCOUT(47) => NLW_gen_dsp48_dsp_PCOUT_47_UNCONNECTED,
      PCOUT(46) => NLW_gen_dsp48_dsp_PCOUT_46_UNCONNECTED,
      PCOUT(45) => NLW_gen_dsp48_dsp_PCOUT_45_UNCONNECTED,
      PCOUT(44) => NLW_gen_dsp48_dsp_PCOUT_44_UNCONNECTED,
      PCOUT(43) => NLW_gen_dsp48_dsp_PCOUT_43_UNCONNECTED,
      PCOUT(42) => NLW_gen_dsp48_dsp_PCOUT_42_UNCONNECTED,
      PCOUT(41) => NLW_gen_dsp48_dsp_PCOUT_41_UNCONNECTED,
      PCOUT(40) => NLW_gen_dsp48_dsp_PCOUT_40_UNCONNECTED,
      PCOUT(39) => NLW_gen_dsp48_dsp_PCOUT_39_UNCONNECTED,
      PCOUT(38) => NLW_gen_dsp48_dsp_PCOUT_38_UNCONNECTED,
      PCOUT(37) => NLW_gen_dsp48_dsp_PCOUT_37_UNCONNECTED,
      PCOUT(36) => NLW_gen_dsp48_dsp_PCOUT_36_UNCONNECTED,
      PCOUT(35) => NLW_gen_dsp48_dsp_PCOUT_35_UNCONNECTED,
      PCOUT(34) => NLW_gen_dsp48_dsp_PCOUT_34_UNCONNECTED,
      PCOUT(33) => NLW_gen_dsp48_dsp_PCOUT_33_UNCONNECTED,
      PCOUT(32) => NLW_gen_dsp48_dsp_PCOUT_32_UNCONNECTED,
      PCOUT(31) => NLW_gen_dsp48_dsp_PCOUT_31_UNCONNECTED,
      PCOUT(30) => NLW_gen_dsp48_dsp_PCOUT_30_UNCONNECTED,
      PCOUT(29) => NLW_gen_dsp48_dsp_PCOUT_29_UNCONNECTED,
      PCOUT(28) => NLW_gen_dsp48_dsp_PCOUT_28_UNCONNECTED,
      PCOUT(27) => NLW_gen_dsp48_dsp_PCOUT_27_UNCONNECTED,
      PCOUT(26) => NLW_gen_dsp48_dsp_PCOUT_26_UNCONNECTED,
      PCOUT(25) => NLW_gen_dsp48_dsp_PCOUT_25_UNCONNECTED,
      PCOUT(24) => NLW_gen_dsp48_dsp_PCOUT_24_UNCONNECTED,
      PCOUT(23) => NLW_gen_dsp48_dsp_PCOUT_23_UNCONNECTED,
      PCOUT(22) => NLW_gen_dsp48_dsp_PCOUT_22_UNCONNECTED,
      PCOUT(21) => NLW_gen_dsp48_dsp_PCOUT_21_UNCONNECTED,
      PCOUT(20) => NLW_gen_dsp48_dsp_PCOUT_20_UNCONNECTED,
      PCOUT(19) => NLW_gen_dsp48_dsp_PCOUT_19_UNCONNECTED,
      PCOUT(18) => NLW_gen_dsp48_dsp_PCOUT_18_UNCONNECTED,
      PCOUT(17) => NLW_gen_dsp48_dsp_PCOUT_17_UNCONNECTED,
      PCOUT(16) => NLW_gen_dsp48_dsp_PCOUT_16_UNCONNECTED,
      PCOUT(15) => NLW_gen_dsp48_dsp_PCOUT_15_UNCONNECTED,
      PCOUT(14) => NLW_gen_dsp48_dsp_PCOUT_14_UNCONNECTED,
      PCOUT(13) => NLW_gen_dsp48_dsp_PCOUT_13_UNCONNECTED,
      PCOUT(12) => NLW_gen_dsp48_dsp_PCOUT_12_UNCONNECTED,
      PCOUT(11) => NLW_gen_dsp48_dsp_PCOUT_11_UNCONNECTED,
      PCOUT(10) => NLW_gen_dsp48_dsp_PCOUT_10_UNCONNECTED,
      PCOUT(9) => NLW_gen_dsp48_dsp_PCOUT_9_UNCONNECTED,
      PCOUT(8) => NLW_gen_dsp48_dsp_PCOUT_8_UNCONNECTED,
      PCOUT(7) => NLW_gen_dsp48_dsp_PCOUT_7_UNCONNECTED,
      PCOUT(6) => NLW_gen_dsp48_dsp_PCOUT_6_UNCONNECTED,
      PCOUT(5) => NLW_gen_dsp48_dsp_PCOUT_5_UNCONNECTED,
      PCOUT(4) => NLW_gen_dsp48_dsp_PCOUT_4_UNCONNECTED,
      PCOUT(3) => NLW_gen_dsp48_dsp_PCOUT_3_UNCONNECTED,
      PCOUT(2) => NLW_gen_dsp48_dsp_PCOUT_2_UNCONNECTED,
      PCOUT(1) => NLW_gen_dsp48_dsp_PCOUT_1_UNCONNECTED,
      PCOUT(0) => NLW_gen_dsp48_dsp_PCOUT_0_UNCONNECTED,
      P(47) => NLW_gen_dsp48_dsp_P_47_UNCONNECTED,
      P(46) => NLW_gen_dsp48_dsp_P_46_UNCONNECTED,
      P(45) => NLW_gen_dsp48_dsp_P_45_UNCONNECTED,
      P(44) => NLW_gen_dsp48_dsp_P_44_UNCONNECTED,
      P(43) => NLW_gen_dsp48_dsp_P_43_UNCONNECTED,
      P(42) => NLW_gen_dsp48_dsp_P_42_UNCONNECTED,
      P(41) => NLW_gen_dsp48_dsp_P_41_UNCONNECTED,
      P(40) => NLW_gen_dsp48_dsp_P_40_UNCONNECTED,
      P(39) => NLW_gen_dsp48_dsp_P_39_UNCONNECTED,
      P(38) => NLW_gen_dsp48_dsp_P_38_UNCONNECTED,
      P(37) => NLW_gen_dsp48_dsp_P_37_UNCONNECTED,
      P(36) => NLW_gen_dsp48_dsp_P_36_UNCONNECTED,
      P(35) => NLW_gen_dsp48_dsp_P_35_UNCONNECTED,
      P(34) => NLW_gen_dsp48_dsp_P_34_UNCONNECTED,
      P(33) => NLW_gen_dsp48_dsp_P_33_UNCONNECTED,
      P(32) => NLW_gen_dsp48_dsp_P_32_UNCONNECTED,
      P(31) => NLW_gen_dsp48_dsp_P_31_UNCONNECTED,
      P(30) => NLW_gen_dsp48_dsp_P_30_UNCONNECTED,
      P(29) => NLW_gen_dsp48_dsp_P_29_UNCONNECTED,
      P(28) => NLW_gen_dsp48_dsp_P_28_UNCONNECTED,
      P(27) => NLW_gen_dsp48_dsp_P_27_UNCONNECTED,
      P(26) => NLW_gen_dsp48_dsp_P_26_UNCONNECTED,
      P(25) => NLW_gen_dsp48_dsp_P_25_UNCONNECTED,
      P(24) => NLW_gen_dsp48_dsp_P_24_UNCONNECTED,
      P(23) => NLW_gen_dsp48_dsp_P_23_UNCONNECTED,
      P(22) => NLW_gen_dsp48_dsp_P_22_UNCONNECTED,
      P(21) => NLW_gen_dsp48_dsp_P_21_UNCONNECTED,
      P(20) => NLW_gen_dsp48_dsp_P_20_UNCONNECTED,
      P(19) => NLW_gen_dsp48_dsp_P_19_UNCONNECTED,
      P(18) => NLW_gen_dsp48_dsp_P_18_UNCONNECTED,
      P(17) => NLW_gen_dsp48_dsp_P_17_UNCONNECTED,
      P(16) => NLW_gen_dsp48_dsp_P_16_UNCONNECTED,
      P(15) => NLW_gen_dsp48_dsp_P_15_UNCONNECTED,
      P(14) => NLW_gen_dsp48_dsp_P_14_UNCONNECTED,
      P(13) => NLW_gen_dsp48_dsp_P_13_UNCONNECTED,
      P(12) => NLW_gen_dsp48_dsp_P_12_UNCONNECTED,
      P(11) => port_p(11),
      P(10) => port_p(10),
      P(9) => port_p(9),
      P(8) => port_p(8),
      P(7) => port_p(7),
      P(6) => port_p(6),
      P(5) => port_p(5),
      P(4) => port_p(4),
      P(3) => port_p(3),
      P(2) => port_p(2),
      P(1) => port_p(1),
      P(0) => port_p(0),
      BCOUT(17) => NLW_gen_dsp48_dsp_BCOUT_17_UNCONNECTED,
      BCOUT(16) => NLW_gen_dsp48_dsp_BCOUT_16_UNCONNECTED,
      BCOUT(15) => NLW_gen_dsp48_dsp_BCOUT_15_UNCONNECTED,
      BCOUT(14) => NLW_gen_dsp48_dsp_BCOUT_14_UNCONNECTED,
      BCOUT(13) => NLW_gen_dsp48_dsp_BCOUT_13_UNCONNECTED,
      BCOUT(12) => NLW_gen_dsp48_dsp_BCOUT_12_UNCONNECTED,
      BCOUT(11) => NLW_gen_dsp48_dsp_BCOUT_11_UNCONNECTED,
      BCOUT(10) => NLW_gen_dsp48_dsp_BCOUT_10_UNCONNECTED,
      BCOUT(9) => NLW_gen_dsp48_dsp_BCOUT_9_UNCONNECTED,
      BCOUT(8) => NLW_gen_dsp48_dsp_BCOUT_8_UNCONNECTED,
      BCOUT(7) => NLW_gen_dsp48_dsp_BCOUT_7_UNCONNECTED,
      BCOUT(6) => NLW_gen_dsp48_dsp_BCOUT_6_UNCONNECTED,
      BCOUT(5) => NLW_gen_dsp48_dsp_BCOUT_5_UNCONNECTED,
      BCOUT(4) => NLW_gen_dsp48_dsp_BCOUT_4_UNCONNECTED,
      BCOUT(3) => NLW_gen_dsp48_dsp_BCOUT_3_UNCONNECTED,
      BCOUT(2) => NLW_gen_dsp48_dsp_BCOUT_2_UNCONNECTED,
      BCOUT(1) => NLW_gen_dsp48_dsp_BCOUT_1_UNCONNECTED,
      BCOUT(0) => NLW_gen_dsp48_dsp_BCOUT_0_UNCONNECTED,
      ACIN(29) => NLW_gen_dsp48_dsp_ACIN_29_UNCONNECTED,
      ACIN(28) => NLW_gen_dsp48_dsp_ACIN_28_UNCONNECTED,
      ACIN(27) => NLW_gen_dsp48_dsp_ACIN_27_UNCONNECTED,
      ACIN(26) => NLW_gen_dsp48_dsp_ACIN_26_UNCONNECTED,
      ACIN(25) => NLW_gen_dsp48_dsp_ACIN_25_UNCONNECTED,
      ACIN(24) => NLW_gen_dsp48_dsp_ACIN_24_UNCONNECTED,
      ACIN(23) => NLW_gen_dsp48_dsp_ACIN_23_UNCONNECTED,
      ACIN(22) => NLW_gen_dsp48_dsp_ACIN_22_UNCONNECTED,
      ACIN(21) => NLW_gen_dsp48_dsp_ACIN_21_UNCONNECTED,
      ACIN(20) => NLW_gen_dsp48_dsp_ACIN_20_UNCONNECTED,
      ACIN(19) => NLW_gen_dsp48_dsp_ACIN_19_UNCONNECTED,
      ACIN(18) => NLW_gen_dsp48_dsp_ACIN_18_UNCONNECTED,
      ACIN(17) => NLW_gen_dsp48_dsp_ACIN_17_UNCONNECTED,
      ACIN(16) => NLW_gen_dsp48_dsp_ACIN_16_UNCONNECTED,
      ACIN(15) => NLW_gen_dsp48_dsp_ACIN_15_UNCONNECTED,
      ACIN(14) => NLW_gen_dsp48_dsp_ACIN_14_UNCONNECTED,
      ACIN(13) => NLW_gen_dsp48_dsp_ACIN_13_UNCONNECTED,
      ACIN(12) => NLW_gen_dsp48_dsp_ACIN_12_UNCONNECTED,
      ACIN(11) => NLW_gen_dsp48_dsp_ACIN_11_UNCONNECTED,
      ACIN(10) => NLW_gen_dsp48_dsp_ACIN_10_UNCONNECTED,
      ACIN(9) => NLW_gen_dsp48_dsp_ACIN_9_UNCONNECTED,
      ACIN(8) => NLW_gen_dsp48_dsp_ACIN_8_UNCONNECTED,
      ACIN(7) => NLW_gen_dsp48_dsp_ACIN_7_UNCONNECTED,
      ACIN(6) => NLW_gen_dsp48_dsp_ACIN_6_UNCONNECTED,
      ACIN(5) => NLW_gen_dsp48_dsp_ACIN_5_UNCONNECTED,
      ACIN(4) => NLW_gen_dsp48_dsp_ACIN_4_UNCONNECTED,
      ACIN(3) => NLW_gen_dsp48_dsp_ACIN_3_UNCONNECTED,
      ACIN(2) => NLW_gen_dsp48_dsp_ACIN_2_UNCONNECTED,
      ACIN(1) => NLW_gen_dsp48_dsp_ACIN_1_UNCONNECTED,
      ACIN(0) => NLW_gen_dsp48_dsp_ACIN_0_UNCONNECTED,
      ACOUT(29) => NLW_gen_dsp48_dsp_ACOUT_29_UNCONNECTED,
      ACOUT(28) => NLW_gen_dsp48_dsp_ACOUT_28_UNCONNECTED,
      ACOUT(27) => NLW_gen_dsp48_dsp_ACOUT_27_UNCONNECTED,
      ACOUT(26) => NLW_gen_dsp48_dsp_ACOUT_26_UNCONNECTED,
      ACOUT(25) => NLW_gen_dsp48_dsp_ACOUT_25_UNCONNECTED,
      ACOUT(24) => NLW_gen_dsp48_dsp_ACOUT_24_UNCONNECTED,
      ACOUT(23) => NLW_gen_dsp48_dsp_ACOUT_23_UNCONNECTED,
      ACOUT(22) => NLW_gen_dsp48_dsp_ACOUT_22_UNCONNECTED,
      ACOUT(21) => NLW_gen_dsp48_dsp_ACOUT_21_UNCONNECTED,
      ACOUT(20) => NLW_gen_dsp48_dsp_ACOUT_20_UNCONNECTED,
      ACOUT(19) => NLW_gen_dsp48_dsp_ACOUT_19_UNCONNECTED,
      ACOUT(18) => NLW_gen_dsp48_dsp_ACOUT_18_UNCONNECTED,
      ACOUT(17) => NLW_gen_dsp48_dsp_ACOUT_17_UNCONNECTED,
      ACOUT(16) => NLW_gen_dsp48_dsp_ACOUT_16_UNCONNECTED,
      ACOUT(15) => NLW_gen_dsp48_dsp_ACOUT_15_UNCONNECTED,
      ACOUT(14) => NLW_gen_dsp48_dsp_ACOUT_14_UNCONNECTED,
      ACOUT(13) => NLW_gen_dsp48_dsp_ACOUT_13_UNCONNECTED,
      ACOUT(12) => NLW_gen_dsp48_dsp_ACOUT_12_UNCONNECTED,
      ACOUT(11) => NLW_gen_dsp48_dsp_ACOUT_11_UNCONNECTED,
      ACOUT(10) => NLW_gen_dsp48_dsp_ACOUT_10_UNCONNECTED,
      ACOUT(9) => NLW_gen_dsp48_dsp_ACOUT_9_UNCONNECTED,
      ACOUT(8) => NLW_gen_dsp48_dsp_ACOUT_8_UNCONNECTED,
      ACOUT(7) => NLW_gen_dsp48_dsp_ACOUT_7_UNCONNECTED,
      ACOUT(6) => NLW_gen_dsp48_dsp_ACOUT_6_UNCONNECTED,
      ACOUT(5) => NLW_gen_dsp48_dsp_ACOUT_5_UNCONNECTED,
      ACOUT(4) => NLW_gen_dsp48_dsp_ACOUT_4_UNCONNECTED,
      ACOUT(3) => NLW_gen_dsp48_dsp_ACOUT_3_UNCONNECTED,
      ACOUT(2) => NLW_gen_dsp48_dsp_ACOUT_2_UNCONNECTED,
      ACOUT(1) => NLW_gen_dsp48_dsp_ACOUT_1_UNCONNECTED,
      ACOUT(0) => NLW_gen_dsp48_dsp_ACOUT_0_UNCONNECTED,
      CARRYOUT(3) => NLW_gen_dsp48_dsp_CARRYOUT_3_UNCONNECTED,
      CARRYOUT(2) => NLW_gen_dsp48_dsp_CARRYOUT_2_UNCONNECTED,
      CARRYOUT(1) => NLW_gen_dsp48_dsp_CARRYOUT_1_UNCONNECTED,
      CARRYOUT(0) => NLW_gen_dsp48_dsp_CARRYOUT_0_UNCONNECTED
    );
  crc_0_not00011 : LUT5
    generic map(
      INIT => X"69969669"
    )
    port map (
      I0 => crc(15),
      I1 => dma_wrdata(15),
      I2 => dma_wrdata(31),
      I3 => dma_wrdata(47),
      I4 => dma_wrdata(63),
      O => crc_0_not0001
    );
  Mxor_crc_9_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(8),
      I1 => dma_wrdata(24),
      I2 => dma_wrdata(40),
      I3 => dma_wrdata(56),
      I4 => dma_wrdata(8),
      O => crc_9_xor0000
    );
  Mxor_crc_8_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(7),
      I1 => dma_wrdata(23),
      I2 => dma_wrdata(39),
      I3 => dma_wrdata(55),
      I4 => dma_wrdata(7),
      O => crc_8_xor0000
    );
  Mxor_crc_7_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(6),
      I1 => dma_wrdata(22),
      I2 => dma_wrdata(38),
      I3 => dma_wrdata(54),
      I4 => dma_wrdata(6),
      O => crc_7_xor0000
    );
  Mxor_crc_6_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(5),
      I1 => dma_wrdata(21),
      I2 => dma_wrdata(37),
      I3 => dma_wrdata(53),
      I4 => dma_wrdata(5),
      O => crc_6_xor0000
    );
  Mxor_crc_5_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(4),
      I1 => dma_wrdata(20),
      I2 => dma_wrdata(36),
      I3 => dma_wrdata(4),
      I4 => dma_wrdata(52),
      O => crc_5_xor0000
    );
  Mxor_crc_4_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(3),
      I1 => dma_wrdata(19),
      I2 => dma_wrdata(35),
      I3 => dma_wrdata(3),
      I4 => dma_wrdata(51),
      O => crc_4_xor0000
    );
  Mxor_crc_3_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(2),
      I1 => dma_wrdata(18),
      I2 => dma_wrdata(2),
      I3 => dma_wrdata(34),
      I4 => dma_wrdata(50),
      O => crc_3_xor0000
    );
  Mxor_crc_2_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(1),
      I1 => dma_wrdata(17),
      I2 => dma_wrdata(1),
      I3 => dma_wrdata(33),
      I4 => dma_wrdata(49),
      O => crc_2_xor0000
    );
  Mxor_crc_1_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(0),
      I1 => dma_wrdata(0),
      I2 => dma_wrdata(16),
      I3 => dma_wrdata(32),
      I4 => dma_wrdata(48),
      O => crc_1_xor0000
    );
  Mxor_crc_15_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(14),
      I1 => dma_wrdata(14),
      I2 => dma_wrdata(30),
      I3 => dma_wrdata(46),
      I4 => dma_wrdata(62),
      O => crc_15_xor0000
    );
  Mxor_crc_14_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(13),
      I1 => dma_wrdata(13),
      I2 => dma_wrdata(29),
      I3 => dma_wrdata(45),
      I4 => dma_wrdata(61),
      O => crc_14_xor0000
    );
  Mxor_crc_13_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(12),
      I1 => dma_wrdata(12),
      I2 => dma_wrdata(28),
      I3 => dma_wrdata(44),
      I4 => dma_wrdata(60),
      O => crc_13_xor0000
    );
  Mxor_crc_12_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(11),
      I1 => dma_wrdata(11),
      I2 => dma_wrdata(27),
      I3 => dma_wrdata(43),
      I4 => dma_wrdata(59),
      O => crc_12_xor0000
    );
  Mxor_crc_11_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(10),
      I1 => dma_wrdata(10),
      I2 => dma_wrdata(26),
      I3 => dma_wrdata(42),
      I4 => dma_wrdata(58),
      O => crc_11_xor0000
    );
  Mxor_crc_10_xor0000_xo_0_1 : LUT5
    generic map(
      INIT => X"96696996"
    )
    port map (
      I0 => crc(9),
      I1 => dma_wrdata(25),
      I2 => dma_wrdata(41),
      I3 => dma_wrdata(57),
      I4 => dma_wrdata(9),
      O => crc_10_xor0000
    );
  crc_reset_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => reg0_z_11998,
      I1 => dsc_load_en,
      O => crc_reset
    );
  ram_b_wr1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => ram0_wr,
      I1 => dsc_load_en,
      O => ram_b_wr
    );
  sig_error_mux00018 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => dma_wrdata(39),
      I1 => dma_wrdata(41),
      I2 => dma_wrdata(34),
      I3 => dma_wrdata(35),
      I4 => dma_wrdata(37),
      O => sig_error_mux00018_12003
    );
  sig_error_mux000133 : LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
    port map (
      I0 => dma_wrdata(47),
      I1 => dma_wrdata(33),
      I2 => dma_wrdata(32),
      I3 => dma_wrdata(46),
      I4 => dma_wrdata(45),
      O => sig_error_mux000133_12001
    );
  sig_error_mux000152 : LUT3
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => dma_wrdata(38),
      I1 => dma_wrdata(40),
      I2 => dma_wrdata(36),
      O => sig_error_mux000152_12002
    );
  sig_error_mux000172 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => dma_wrdata(42),
      I1 => dma_wrdata(44),
      I2 => sig_error_mux00018_12003,
      I3 => sig_error_mux000133_12001,
      I4 => dma_wrdata(43),
      I5 => sig_error_mux000152_12002,
      O => sig_error_mux0001
    );
  dma_descriptor_error_or000010 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => crc(1),
      I1 => crc(2),
      I2 => crc(3),
      I3 => crc(4),
      I4 => crc(5),
      I5 => crc(6),
      O => dma_descriptor_error_or000010_11820
    );
  dma_descriptor_error_or000021 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => crc(7),
      I1 => crc(8),
      I2 => crc(9),
      I3 => crc(10),
      I4 => crc(11),
      I5 => crc(12),
      O => dma_descriptor_error_or000021_11821
    );
  dma_descriptor_error_or000032 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => crc(14),
      I1 => crc(0),
      I2 => crc(15),
      I3 => sig_error_11999,
      I4 => crc(13),
      O => dma_descriptor_error_or000032_11822
    );
  dma_descriptor_error_or000045 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => dma_descriptor_error_or000010_11820,
      I1 => dma_descriptor_error_or000021_11821,
      I2 => dma_descriptor_error_or000032_11822,
      O => dma_descriptor_error_or0000
    );
  ram0 : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_ram0_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_ram0_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => clk,
      ENA => carry,
      REGCEA => NlwRenamedSig_OI_test(0),
      REGCEB => NlwRenamedSig_OI_test(0),
      ENB => carry,
      SSRA => NlwRenamedSig_OI_test(0),
      SSRB => NlwRenamedSig_OI_test(0),
      CASCADEOUTA => NLW_ram0_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_ram0_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_ram0_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => port_c(7),
      ADDRA(11) => port_c(6),
      ADDRA(10) => port_c(5),
      ADDRA(9) => port_c(4),
      ADDRA(8) => port_c(3),
      ADDRA(7) => port_c(2),
      ADDRA(6) => port_c(1),
      ADDRA(5) => port_c(0),
      ADDRA(4) => NLW_ram0_ADDRA_4_UNCONNECTED,
      ADDRA(3) => NLW_ram0_ADDRA_3_UNCONNECTED,
      ADDRA(2) => NLW_ram0_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_ram0_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_ram0_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_ram0_ADDRB_14_UNCONNECTED,
      ADDRB(13) => dma_chn,
      ADDRB(12) => dma_wraddr(10),
      ADDRB(11) => dma_wraddr(9),
      ADDRB(10) => dma_wraddr(8),
      ADDRB(9) => dma_wraddr(7),
      ADDRB(8) => dma_wraddr(6),
      ADDRB(7) => dma_wraddr(5),
      ADDRB(6) => dma_wraddr(4),
      ADDRB(5) => dma_wraddr(3),
      ADDRB(4) => NLW_ram0_ADDRB_4_UNCONNECTED,
      ADDRB(3) => NLW_ram0_ADDRB_3_UNCONNECTED,
      ADDRB(2) => NLW_ram0_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_ram0_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_ram0_ADDRB_0_UNCONNECTED,
      DIA(31) => ram_a_in(31),
      DIA(30) => ram_a_in(30),
      DIA(29) => ram_a_in(29),
      DIA(28) => ram_a_in(28),
      DIA(27) => ram_a_in(27),
      DIA(26) => ram_a_in(26),
      DIA(25) => ram_a_in(25),
      DIA(24) => ram_a_in(24),
      DIA(23) => data_in(31),
      DIA(22) => data_in(30),
      DIA(21) => data_in(29),
      DIA(20) => data_in(28),
      DIA(19) => data_in(27),
      DIA(18) => data_in(26),
      DIA(17) => data_in(25),
      DIA(16) => data_in(24),
      DIA(15) => data_in(23),
      DIA(14) => data_in(22),
      DIA(13) => data_in(21),
      DIA(12) => data_in(20),
      DIA(11) => data_in(19),
      DIA(10) => data_in(18),
      DIA(9) => data_in(17),
      DIA(8) => data_in(16),
      DIA(7) => data_in(15),
      DIA(6) => data_in(14),
      DIA(5) => data_in(13),
      DIA(4) => data_in(12),
      DIA(3) => data_in(11),
      DIA(2) => data_in(10),
      DIA(1) => data_in(9),
      DIA(0) => data_in(8),
      DIB(31) => dma_wrdata(31),
      DIB(30) => dma_wrdata(30),
      DIB(29) => dma_wrdata(29),
      DIB(28) => dma_wrdata(28),
      DIB(27) => dma_wrdata(27),
      DIB(26) => dma_wrdata(26),
      DIB(25) => dma_wrdata(25),
      DIB(24) => dma_wrdata(24),
      DIB(23) => dma_wrdata(23),
      DIB(22) => dma_wrdata(22),
      DIB(21) => dma_wrdata(21),
      DIB(20) => dma_wrdata(20),
      DIB(19) => dma_wrdata(19),
      DIB(18) => dma_wrdata(18),
      DIB(17) => dma_wrdata(17),
      DIB(16) => dma_wrdata(16),
      DIB(15) => dma_wrdata(15),
      DIB(14) => dma_wrdata(14),
      DIB(13) => dma_wrdata(13),
      DIB(12) => dma_wrdata(12),
      DIB(11) => dma_wrdata(11),
      DIB(10) => dma_wrdata(10),
      DIB(9) => dma_wrdata(9),
      DIB(8) => dma_wrdata(8),
      DIB(7) => dma_wrdata(7),
      DIB(6) => dma_wrdata(6),
      DIB(5) => dma_wrdata(5),
      DIB(4) => dma_wrdata(4),
      DIB(3) => dma_wrdata(3),
      DIB(2) => dma_wrdata(2),
      DIB(1) => dma_wrdata(1),
      DIB(0) => dma_wrdata(0),
      DIPA(3) => NlwRenamedSig_OI_test(0),
      DIPA(2) => NlwRenamedSig_OI_test(0),
      DIPA(1) => NlwRenamedSig_OI_test(0),
      DIPA(0) => NlwRenamedSig_OI_test(0),
      DIPB(3) => NlwRenamedSig_OI_test(0),
      DIPB(2) => NlwRenamedSig_OI_test(0),
      DIPB(1) => NlwRenamedSig_OI_test(0),
      DIPB(0) => NlwRenamedSig_OI_test(0),
      WEA(3) => pci_adr_we,
      WEA(2) => pci_adr_we,
      WEA(1) => pci_adr_we,
      WEA(0) => pci_adr_we,
      WEB(3) => ram_b_wr,
      WEB(2) => ram_b_wr,
      WEB(1) => ram_b_wr,
      WEB(0) => ram_b_wr,
      DOA(31) => dsc_adr_h(7),
      DOA(30) => dsc_adr_h(6),
      DOA(29) => dsc_adr_h(5),
      DOA(28) => dsc_adr_h(4),
      DOA(27) => dsc_adr_h(3),
      DOA(26) => dsc_adr_h(2),
      DOA(25) => dsc_adr_h(1),
      DOA(24) => dsc_adr_h(0),
      DOA(23) => dsc_adr(23),
      DOA(22) => dsc_adr(22),
      DOA(21) => dsc_adr(21),
      DOA(20) => dsc_adr(20),
      DOA(19) => dsc_adr(19),
      DOA(18) => dsc_adr(18),
      DOA(17) => dsc_adr(17),
      DOA(16) => dsc_adr(16),
      DOA(15) => dsc_adr(15),
      DOA(14) => dsc_adr(14),
      DOA(13) => dsc_adr(13),
      DOA(12) => dsc_adr(12),
      DOA(11) => dsc_adr(11),
      DOA(10) => dsc_adr(10),
      DOA(9) => dsc_adr(9),
      DOA(8) => dsc_adr(8),
      DOA(7) => dsc_adr(7),
      DOA(6) => dsc_adr(6),
      DOA(5) => dsc_adr(5),
      DOA(4) => dsc_adr(4),
      DOA(3) => dsc_adr(3),
      DOA(2) => dsc_adr(2),
      DOA(1) => dsc_adr(1),
      DOA(0) => dsc_adr(0),
      DOB(31) => NLW_ram0_DOB_31_UNCONNECTED,
      DOB(30) => NLW_ram0_DOB_30_UNCONNECTED,
      DOB(29) => NLW_ram0_DOB_29_UNCONNECTED,
      DOB(28) => NLW_ram0_DOB_28_UNCONNECTED,
      DOB(27) => NLW_ram0_DOB_27_UNCONNECTED,
      DOB(26) => NLW_ram0_DOB_26_UNCONNECTED,
      DOB(25) => NLW_ram0_DOB_25_UNCONNECTED,
      DOB(24) => NLW_ram0_DOB_24_UNCONNECTED,
      DOB(23) => NLW_ram0_DOB_23_UNCONNECTED,
      DOB(22) => NLW_ram0_DOB_22_UNCONNECTED,
      DOB(21) => NLW_ram0_DOB_21_UNCONNECTED,
      DOB(20) => NLW_ram0_DOB_20_UNCONNECTED,
      DOB(19) => NLW_ram0_DOB_19_UNCONNECTED,
      DOB(18) => NLW_ram0_DOB_18_UNCONNECTED,
      DOB(17) => NLW_ram0_DOB_17_UNCONNECTED,
      DOB(16) => NLW_ram0_DOB_16_UNCONNECTED,
      DOB(15) => NLW_ram0_DOB_15_UNCONNECTED,
      DOB(14) => NLW_ram0_DOB_14_UNCONNECTED,
      DOB(13) => NLW_ram0_DOB_13_UNCONNECTED,
      DOB(12) => NLW_ram0_DOB_12_UNCONNECTED,
      DOB(11) => NLW_ram0_DOB_11_UNCONNECTED,
      DOB(10) => NLW_ram0_DOB_10_UNCONNECTED,
      DOB(9) => NLW_ram0_DOB_9_UNCONNECTED,
      DOB(8) => NLW_ram0_DOB_8_UNCONNECTED,
      DOB(7) => NLW_ram0_DOB_7_UNCONNECTED,
      DOB(6) => NLW_ram0_DOB_6_UNCONNECTED,
      DOB(5) => NLW_ram0_DOB_5_UNCONNECTED,
      DOB(4) => NLW_ram0_DOB_4_UNCONNECTED,
      DOB(3) => NLW_ram0_DOB_3_UNCONNECTED,
      DOB(2) => NLW_ram0_DOB_2_UNCONNECTED,
      DOB(1) => NLW_ram0_DOB_1_UNCONNECTED,
      DOB(0) => NLW_ram0_DOB_0_UNCONNECTED,
      DOPA(3) => NLW_ram0_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_ram0_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_ram0_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_ram0_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_ram0_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_ram0_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_ram0_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_ram0_DOPB_0_UNCONNECTED
    );
  ram1 : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_ram1_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_ram1_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => clk,
      ENA => carry,
      REGCEA => NlwRenamedSig_OI_test(0),
      REGCEB => NlwRenamedSig_OI_test(0),
      ENB => carry,
      SSRA => NlwRenamedSig_OI_test(0),
      SSRB => NlwRenamedSig_OI_test(0),
      CASCADEOUTA => NLW_ram1_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_ram1_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_ram1_ADDRA_14_UNCONNECTED,
      ADDRA(13) => dma_chn,
      ADDRA(12) => port_c(7),
      ADDRA(11) => port_c(6),
      ADDRA(10) => port_c(5),
      ADDRA(9) => port_c(4),
      ADDRA(8) => port_c(3),
      ADDRA(7) => port_c(2),
      ADDRA(6) => port_c(1),
      ADDRA(5) => port_c(0),
      ADDRA(4) => NLW_ram1_ADDRA_4_UNCONNECTED,
      ADDRA(3) => NLW_ram1_ADDRA_3_UNCONNECTED,
      ADDRA(2) => NLW_ram1_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_ram1_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_ram1_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_ram1_ADDRB_14_UNCONNECTED,
      ADDRB(13) => dma_chn,
      ADDRB(12) => dma_wraddr(10),
      ADDRB(11) => dma_wraddr(9),
      ADDRB(10) => dma_wraddr(8),
      ADDRB(9) => dma_wraddr(7),
      ADDRB(8) => dma_wraddr(6),
      ADDRB(7) => dma_wraddr(5),
      ADDRB(6) => dma_wraddr(4),
      ADDRB(5) => dma_wraddr(3),
      ADDRB(4) => NLW_ram1_ADDRB_4_UNCONNECTED,
      ADDRB(3) => NLW_ram1_ADDRB_3_UNCONNECTED,
      ADDRB(2) => NLW_ram1_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_ram1_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_ram1_ADDRB_0_UNCONNECTED,
      DIA(31) => NlwRenamedSig_OI_test(0),
      DIA(30) => NlwRenamedSig_OI_test(0),
      DIA(29) => NlwRenamedSig_OI_test(0),
      DIA(28) => NlwRenamedSig_OI_test(0),
      DIA(27) => NlwRenamedSig_OI_test(0),
      DIA(26) => NlwRenamedSig_OI_test(0),
      DIA(25) => NlwRenamedSig_OI_test(0),
      DIA(24) => NlwRenamedSig_OI_test(0),
      DIA(23) => NlwRenamedSig_OI_test(0),
      DIA(22) => NlwRenamedSig_OI_test(0),
      DIA(21) => NlwRenamedSig_OI_test(0),
      DIA(20) => NlwRenamedSig_OI_test(0),
      DIA(19) => NlwRenamedSig_OI_test(0),
      DIA(18) => NlwRenamedSig_OI_test(0),
      DIA(17) => NlwRenamedSig_OI_test(0),
      DIA(16) => NlwRenamedSig_OI_test(0),
      DIA(15) => NlwRenamedSig_OI_test(0),
      DIA(14) => NlwRenamedSig_OI_test(0),
      DIA(13) => NlwRenamedSig_OI_test(0),
      DIA(12) => NlwRenamedSig_OI_test(0),
      DIA(11) => NlwRenamedSig_OI_test(0),
      DIA(10) => NlwRenamedSig_OI_test(0),
      DIA(9) => NlwRenamedSig_OI_test(0),
      DIA(8) => NlwRenamedSig_OI_test(0),
      DIA(7) => NlwRenamedSig_OI_test(0),
      DIA(6) => NlwRenamedSig_OI_test(0),
      DIA(5) => NlwRenamedSig_OI_test(0),
      DIA(4) => NlwRenamedSig_OI_test(0),
      DIA(3) => NlwRenamedSig_OI_test(0),
      DIA(2) => NlwRenamedSig_OI_test(0),
      DIA(1) => NlwRenamedSig_OI_test(0),
      DIA(0) => NlwRenamedSig_OI_test(0),
      DIB(31) => dma_wrdata(63),
      DIB(30) => dma_wrdata(62),
      DIB(29) => dma_wrdata(61),
      DIB(28) => dma_wrdata(60),
      DIB(27) => dma_wrdata(59),
      DIB(26) => dma_wrdata(58),
      DIB(25) => dma_wrdata(57),
      DIB(24) => dma_wrdata(56),
      DIB(23) => dma_wrdata(55),
      DIB(22) => dma_wrdata(54),
      DIB(21) => dma_wrdata(53),
      DIB(20) => dma_wrdata(52),
      DIB(19) => dma_wrdata(51),
      DIB(18) => dma_wrdata(50),
      DIB(17) => dma_wrdata(49),
      DIB(16) => dma_wrdata(48),
      DIB(15) => dma_wrdata(47),
      DIB(14) => dma_wrdata(46),
      DIB(13) => dma_wrdata(45),
      DIB(12) => dma_wrdata(44),
      DIB(11) => dma_wrdata(43),
      DIB(10) => dma_wrdata(42),
      DIB(9) => dma_wrdata(41),
      DIB(8) => dma_wrdata(40),
      DIB(7) => dma_wrdata(39),
      DIB(6) => dma_wrdata(38),
      DIB(5) => dma_wrdata(37),
      DIB(4) => dma_wrdata(36),
      DIB(3) => dma_wrdata(35),
      DIB(2) => dma_wrdata(34),
      DIB(1) => dma_wrdata(33),
      DIB(0) => dma_wrdata(32),
      DIPA(3) => NlwRenamedSig_OI_test(0),
      DIPA(2) => NlwRenamedSig_OI_test(0),
      DIPA(1) => NlwRenamedSig_OI_test(0),
      DIPA(0) => NlwRenamedSig_OI_test(0),
      DIPB(3) => NlwRenamedSig_OI_test(0),
      DIPB(2) => NlwRenamedSig_OI_test(0),
      DIPB(1) => NlwRenamedSig_OI_test(0),
      DIPB(0) => NlwRenamedSig_OI_test(0),
      WEA(3) => pci_adr_we,
      WEA(2) => pci_adr_we,
      WEA(1) => pci_adr_we,
      WEA(0) => pci_adr_we,
      WEB(3) => ram_b_wr,
      WEB(2) => ram_b_wr,
      WEB(1) => ram_b_wr,
      WEB(0) => ram_b_wr,
      DOA(31) => dsc_size(23),
      DOA(30) => dsc_size(22),
      DOA(29) => dsc_size(21),
      DOA(28) => dsc_size(20),
      DOA(27) => dsc_size(19),
      DOA(26) => dsc_size(18),
      DOA(25) => dsc_size(17),
      DOA(24) => dsc_size(16),
      DOA(23) => dsc_size(15),
      DOA(22) => dsc_size(14),
      DOA(21) => dsc_size(13),
      DOA(20) => dsc_size(12),
      DOA(19) => dsc_size(11),
      DOA(18) => dsc_size(10),
      DOA(17) => dsc_size(9),
      DOA(16) => dsc_size(8),
      DOA(15) => dsc_size(7),
      DOA(14) => dsc_size(6),
      DOA(13) => dsc_size(5),
      DOA(12) => dsc_size(4),
      DOA(11) => dsc_size(3),
      DOA(10) => dsc_size(2),
      DOA(9) => dsc_size(1),
      DOA(8) => dsc_size(0),
      DOA(7) => dsc_cmd(7),
      DOA(6) => dsc_cmd(6),
      DOA(5) => dsc_cmd(5),
      DOA(4) => dsc_cmd(4),
      DOA(3) => dsc_cmd(3),
      DOA(2) => dsc_cmd(2),
      DOA(1) => dsc_cmd(1),
      DOA(0) => dsc_cmd(0),
      DOB(31) => NLW_ram1_DOB_31_UNCONNECTED,
      DOB(30) => NLW_ram1_DOB_30_UNCONNECTED,
      DOB(29) => NLW_ram1_DOB_29_UNCONNECTED,
      DOB(28) => NLW_ram1_DOB_28_UNCONNECTED,
      DOB(27) => NLW_ram1_DOB_27_UNCONNECTED,
      DOB(26) => NLW_ram1_DOB_26_UNCONNECTED,
      DOB(25) => NLW_ram1_DOB_25_UNCONNECTED,
      DOB(24) => NLW_ram1_DOB_24_UNCONNECTED,
      DOB(23) => NLW_ram1_DOB_23_UNCONNECTED,
      DOB(22) => NLW_ram1_DOB_22_UNCONNECTED,
      DOB(21) => NLW_ram1_DOB_21_UNCONNECTED,
      DOB(20) => NLW_ram1_DOB_20_UNCONNECTED,
      DOB(19) => NLW_ram1_DOB_19_UNCONNECTED,
      DOB(18) => NLW_ram1_DOB_18_UNCONNECTED,
      DOB(17) => NLW_ram1_DOB_17_UNCONNECTED,
      DOB(16) => NLW_ram1_DOB_16_UNCONNECTED,
      DOB(15) => NLW_ram1_DOB_15_UNCONNECTED,
      DOB(14) => NLW_ram1_DOB_14_UNCONNECTED,
      DOB(13) => NLW_ram1_DOB_13_UNCONNECTED,
      DOB(12) => NLW_ram1_DOB_12_UNCONNECTED,
      DOB(11) => NLW_ram1_DOB_11_UNCONNECTED,
      DOB(10) => NLW_ram1_DOB_10_UNCONNECTED,
      DOB(9) => NLW_ram1_DOB_9_UNCONNECTED,
      DOB(8) => NLW_ram1_DOB_8_UNCONNECTED,
      DOB(7) => NLW_ram1_DOB_7_UNCONNECTED,
      DOB(6) => NLW_ram1_DOB_6_UNCONNECTED,
      DOB(5) => NLW_ram1_DOB_5_UNCONNECTED,
      DOB(4) => NLW_ram1_DOB_4_UNCONNECTED,
      DOB(3) => NLW_ram1_DOB_3_UNCONNECTED,
      DOB(2) => NLW_ram1_DOB_2_UNCONNECTED,
      DOB(1) => NLW_ram1_DOB_1_UNCONNECTED,
      DOB(0) => NLW_ram1_DOB_0_UNCONNECTED,
      DOPA(3) => NLW_ram1_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_ram1_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_ram1_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_ram1_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_ram1_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_ram1_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_ram1_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_ram1_DOPB_0_UNCONNECTED
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_main is
  port (
    ram_we : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    dma1_transfer_rdy : in STD_LOGIC := 'X'; 
    dsc_change_adr : out STD_LOGIC; 
    dsc_load_en : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    loc_adr_we : out STD_LOGIC; 
    ram_change : out STD_LOGIC; 
    dsc_correct : in STD_LOGIC := 'X'; 
    dma0_transfer_rdy : in STD_LOGIC := 'X'; 
    dma1_eot_clr : in STD_LOGIC := 'X'; 
    dma0_eot_clr : in STD_LOGIC := 'X'; 
    pci_adr_we : out STD_LOGIC; 
    dsc_change_mode : out STD_LOGIC; 
    dma_change_adr : out STD_LOGIC; 
    dma_chn : out STD_LOGIC; 
    pci_adr_h_we : out STD_LOGIC; 
    ram_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
    ram_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    reg_dma1_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    reg_dma0_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    dma_reg0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    dma_status : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    dma0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dsc_cmd : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    dma1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end ctrl_main;

architecture STRUCTURE of ctrl_main is
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N161 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N41 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal dma0_block : STD_LOGIC; 
  signal dma0_block_in : STD_LOGIC; 
  signal dma0_block_z_11559 : STD_LOGIC; 
  signal dma0_ctrl_0_inv : STD_LOGIC; 
  signal dma0_ctrl_z_11563 : STD_LOGIC; 
  signal dma0_ctrl_z_inv : STD_LOGIC; 
  signal dma0_eot_11565 : STD_LOGIC; 
  signal dma0_eot_and0000 : STD_LOGIC; 
  signal dma0_eot_or0000 : STD_LOGIC; 
  signal dma0_flag_start_11569 : STD_LOGIC; 
  signal dma0_flag_start_or0000 : STD_LOGIC; 
  signal dma0_sg_eot_11571 : STD_LOGIC; 
  signal dma0_sg_eot_and0000 : STD_LOGIC; 
  signal dma0_start_11573 : STD_LOGIC; 
  signal dma0_start_and0000 : STD_LOGIC; 
  signal dma0_wait_eot_11576 : STD_LOGIC; 
  signal dma0_wait_eot2_11577 : STD_LOGIC; 
  signal dma0_wait_eot2_and0000 : STD_LOGIC; 
  signal dma0_wait_eot_and0000 : STD_LOGIC; 
  signal dma0_wait_eot_or0000 : STD_LOGIC; 
  signal dma1_block : STD_LOGIC; 
  signal dma1_block_in : STD_LOGIC; 
  signal dma1_block_z_11583 : STD_LOGIC; 
  signal dma1_ctrl_0_inv : STD_LOGIC; 
  signal dma1_ctrl_z_11587 : STD_LOGIC; 
  signal dma1_ctrl_z_inv : STD_LOGIC; 
  signal dma1_eot_11589 : STD_LOGIC; 
  signal dma1_eot_and0000 : STD_LOGIC; 
  signal dma1_eot_or0000 : STD_LOGIC; 
  signal dma1_flag_start_11593 : STD_LOGIC; 
  signal dma1_flag_start_or0000 : STD_LOGIC; 
  signal dma1_sg_eot_11595 : STD_LOGIC; 
  signal dma1_sg_eot_and0000 : STD_LOGIC; 
  signal dma1_start_11597 : STD_LOGIC; 
  signal dma1_start_and0000 : STD_LOGIC; 
  signal dma1_wait_eot_11600 : STD_LOGIC; 
  signal dma1_wait_eot2_11601 : STD_LOGIC; 
  signal dma1_wait_eot2_and0000 : STD_LOGIC; 
  signal dma1_wait_eot_and0000 : STD_LOGIC; 
  signal dma1_wait_eot_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dma_change_adr : STD_LOGIC; 
  signal dma_change_adr_mux0000 : STD_LOGIC; 
  signal dma_change_adr_mux000016_11607 : STD_LOGIC; 
  signal dma_change_adr_mux000025_11608 : STD_LOGIC; 
  signal dma_chn_change_11609 : STD_LOGIC; 
  signal dma_chn_change_mux0000_11610 : STD_LOGIC; 
  signal dma_chn_change_mux00001110_11611 : STD_LOGIC; 
  signal dma_chn_change_mux00001119_11612 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dma_chni : STD_LOGIC; 
  signal dma_chni_inv : STD_LOGIC; 
  signal dma_chni_mux0000_11615 : STD_LOGIC; 
  signal dma_chni_not0001 : STD_LOGIC; 
  signal dma_eot_set_11617 : STD_LOGIC; 
  signal dma_eot_set_mux0000_11618 : STD_LOGIC; 
  signal dma_flag_start_11619 : STD_LOGIC; 
  signal dma_flag_start_clr_11620 : STD_LOGIC; 
  signal dma_flag_start_clr_mux0000 : STD_LOGIC; 
  signal dma_flag_start_not0001 : STD_LOGIC; 
  signal dma_flag_start_or0000 : STD_LOGIC; 
  signal dma_reg0_mux0000_1_1_11629 : STD_LOGIC; 
  signal dma_reg0_mux0000_1_110_11630 : STD_LOGIC; 
  signal dma_reg0_mux0000_1_119_11631 : STD_LOGIC; 
  signal dma_rotate_11633 : STD_LOGIC; 
  signal dma_rotate_mux0004 : STD_LOGIC; 
  signal dma_rotate_not0001 : STD_LOGIC; 
  signal dma_sg_eot_set_11636 : STD_LOGIC; 
  signal dma_sg_eot_set_mux0000_11637 : STD_LOGIC; 
  signal dma_sg_eot_set_mux00001 : STD_LOGIC; 
  signal dma_sg_eot_set_mux00001110_11639 : STD_LOGIC; 
  signal dma_sg_eot_set_mux00001121_11640 : STD_LOGIC; 
  signal dma_transfer_start_11644 : STD_LOGIC; 
  signal dma_transfer_start_not0001 : STD_LOGIC; 
  signal dma_transfer_start_or0000 : STD_LOGIC; 
  signal dma_transfer_start_or0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dsc_change_adr : STD_LOGIC; 
  signal dsc_change_adr_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dsc_change_mode : STD_LOGIC; 
  signal dsc_change_mode_mux0000_11651 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dsc_load_en : STD_LOGIC; 
  signal dsc_load_en_mux0000_11658 : STD_LOGIC; 
  signal init_compelte_11659 : STD_LOGIC; 
  signal init_compelte_mux0000_11660 : STD_LOGIC; 
  signal NlwRenamedSig_OI_loc_adr_we : STD_LOGIC; 
  signal loc_adr_we_mux0000_11662 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_h_we : STD_LOGIC; 
  signal pci_adr_h_we_mux0000_11664 : STD_LOGIC; 
  signal NlwRenamedSig_OI_pci_adr_we : STD_LOGIC; 
  signal pci_adr_we_mux0000_11666 : STD_LOGIC; 
  signal NlwRenamedSig_OI_ram_change : STD_LOGIC; 
  signal ram_change_mux0000 : STD_LOGIC; 
  signal ram_change_mux00001_11669 : STD_LOGIC; 
  signal ram_change_mux00002_11670 : STD_LOGIC; 
  signal NlwRenamedSig_OI_reg_dma0_status_13_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_reg_dma0_status_1_Q : STD_LOGIC; 
  signal reg_dma0_status_4_or0000 : STD_LOGIC; 
  signal reg_dma0_status_4_or0000_inv : STD_LOGIC; 
  signal reg_dma1_status_4_or0000 : STD_LOGIC; 
  signal reg_dma1_status_4_or0000_inv : STD_LOGIC; 
  signal rstp_11696 : STD_LOGIC; 
  signal stp_FSM_FFd1_11697 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd10_11699 : STD_LOGIC; 
  signal stp_FSM_FFd10_In : STD_LOGIC; 
  signal stp_FSM_FFd11_11701 : STD_LOGIC; 
  signal stp_FSM_FFd11_In : STD_LOGIC; 
  signal stp_FSM_FFd12_11703 : STD_LOGIC; 
  signal stp_FSM_FFd12_In : STD_LOGIC; 
  signal stp_FSM_FFd13_11705 : STD_LOGIC; 
  signal stp_FSM_FFd13_In : STD_LOGIC; 
  signal stp_FSM_FFd14_11707 : STD_LOGIC; 
  signal stp_FSM_FFd14_In : STD_LOGIC; 
  signal stp_FSM_FFd15_11709 : STD_LOGIC; 
  signal stp_FSM_FFd15_In : STD_LOGIC; 
  signal stp_FSM_FFd16_11711 : STD_LOGIC; 
  signal stp_FSM_FFd16_In : STD_LOGIC; 
  signal stp_FSM_FFd17_11713 : STD_LOGIC; 
  signal stp_FSM_FFd17_In : STD_LOGIC; 
  signal stp_FSM_FFd18_11715 : STD_LOGIC; 
  signal stp_FSM_FFd18_In : STD_LOGIC; 
  signal stp_FSM_FFd19_11717 : STD_LOGIC; 
  signal stp_FSM_FFd19_In : STD_LOGIC; 
  signal stp_FSM_FFd2_11719 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd20_11721 : STD_LOGIC; 
  signal stp_FSM_FFd20_In : STD_LOGIC; 
  signal stp_FSM_FFd21_11723 : STD_LOGIC; 
  signal stp_FSM_FFd21_In : STD_LOGIC; 
  signal stp_FSM_FFd22_11725 : STD_LOGIC; 
  signal stp_FSM_FFd22_In_11726 : STD_LOGIC; 
  signal stp_FSM_FFd3_11727 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_11729 : STD_LOGIC; 
  signal stp_FSM_FFd5_11730 : STD_LOGIC; 
  signal stp_FSM_FFd6_11731 : STD_LOGIC; 
  signal stp_FSM_FFd7_11732 : STD_LOGIC; 
  signal stp_FSM_FFd8_11733 : STD_LOGIC; 
  signal stp_FSM_FFd9_11734 : STD_LOGIC; 
  signal stw_FSM_FFd1_11735 : STD_LOGIC; 
  signal stw_FSM_FFd1_In : STD_LOGIC; 
  signal stw_FSM_FFd10_11737 : STD_LOGIC; 
  signal stw_FSM_FFd10_In : STD_LOGIC; 
  signal stw_FSM_FFd11_11739 : STD_LOGIC; 
  signal stw_FSM_FFd11_In : STD_LOGIC; 
  signal stw_FSM_FFd2_11741 : STD_LOGIC; 
  signal stw_FSM_FFd3_11742 : STD_LOGIC; 
  signal stw_FSM_FFd4_11743 : STD_LOGIC; 
  signal stw_FSM_FFd5_11744 : STD_LOGIC; 
  signal stw_FSM_FFd6_11745 : STD_LOGIC; 
  signal stw_FSM_FFd7_11746 : STD_LOGIC; 
  signal stw_FSM_FFd8_11747 : STD_LOGIC; 
  signal stw_FSM_FFd9_11748 : STD_LOGIC; 
  signal stw_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_dma_reg0 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal dma_reg0_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal NlwRenamedSig_OI_ram_sel : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal ram_sel_mux0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  ram_we <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  dsc_change_adr <= NlwRenamedSig_OI_dsc_change_adr;
  dsc_load_en <= NlwRenamedSig_OI_dsc_load_en;
  loc_adr_we <= NlwRenamedSig_OI_loc_adr_we;
  ram_change <= NlwRenamedSig_OI_ram_change;
  pci_adr_we <= NlwRenamedSig_OI_pci_adr_we;
  dsc_change_mode <= NlwRenamedSig_OI_dsc_change_mode;
  dma_change_adr <= NlwRenamedSig_OI_dma_change_adr;
  dma_chn <= NlwRenamedSig_OI_dma_chni;
  pci_adr_h_we <= NlwRenamedSig_OI_pci_adr_h_we;
  ram_adr(8) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_adr(7) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_adr(6) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_adr(5) <= NlwRenamedSig_OI_dma_chni;
  ram_adr(4) <= NlwRenamedSig_OI_reg_dma0_status_13_Q;
  ram_adr(3) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_adr(2) <= NlwRenamedSig_OI_ram_sel(2);
  ram_adr(1) <= NlwRenamedSig_OI_ram_sel(1);
  ram_adr(0) <= NlwRenamedSig_OI_ram_sel(0);
  ram_do(7) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(6) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(5) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(4) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(3) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(2) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(1) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  ram_do(0) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(15) <= NlwRenamedSig_OI_reg_dma0_status_13_Q;
  reg_dma1_status(14) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(13) <= NlwRenamedSig_OI_reg_dma0_status_13_Q;
  reg_dma1_status(12) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(11) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(10) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(9) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(3) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(2) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma1_status(1) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(15) <= NlwRenamedSig_OI_reg_dma0_status_13_Q;
  reg_dma0_status(14) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(13) <= NlwRenamedSig_OI_reg_dma0_status_13_Q;
  reg_dma0_status(12) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(11) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(10) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(9) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(3) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(2) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  reg_dma0_status(1) <= NlwRenamedSig_OI_reg_dma0_status_1_Q;
  dma_reg0(2) <= NlwRenamedSig_OI_dma_reg0(2);
  dma_reg0(1) <= NlwRenamedSig_OI_dma_reg0(1);
  dma_reg0(0) <= NlwRenamedSig_OI_dma_reg0(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_reg_dma0_status_1_Q
    );
  XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_reg_dma0_status_13_Q
    );
  dma_sg_eot_set : FD
    port map (
      C => clk,
      D => dma_sg_eot_set_mux0000_11637,
      Q => dma_sg_eot_set_11636
    );
  dma0_wait_eot2 : FDRE
    port map (
      C => clk,
      CE => dma0_eot_clr,
      D => dma0_wait_eot2_and0000,
      R => dma0_ctrl_0_inv,
      Q => dma0_wait_eot2_11577
    );
  dma_flag_start_clr : FD
    port map (
      C => clk,
      D => dma_flag_start_clr_mux0000,
      Q => dma_flag_start_clr_11620
    );
  dma1_wait_eot2 : FDRE
    port map (
      C => clk,
      CE => dma1_eot_clr,
      D => dma1_wait_eot2_and0000,
      R => dma1_ctrl_0_inv,
      Q => dma1_wait_eot2_11601
    );
  loc_adr_we_8629 : FD
    port map (
      C => clk,
      D => loc_adr_we_mux0000_11662,
      Q => NlwRenamedSig_OI_loc_adr_we
    );
  dma1_eot : FDRE
    port map (
      C => clk,
      CE => dma1_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma1_eot_or0000,
      Q => dma1_eot_11589
    );
  dma0_wait_eot : FDRE
    port map (
      C => clk,
      CE => dma0_wait_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma0_wait_eot_or0000,
      Q => dma0_wait_eot_11576
    );
  dma_change_adr_8632 : FD
    port map (
      C => clk,
      D => dma_change_adr_mux0000,
      Q => NlwRenamedSig_OI_dma_change_adr
    );
  dsc_load_en_8633 : FD
    port map (
      C => clk,
      D => dsc_load_en_mux0000_11658,
      Q => NlwRenamedSig_OI_dsc_load_en
    );
  ram_change_8634 : FD
    port map (
      C => clk,
      D => ram_change_mux0000,
      Q => NlwRenamedSig_OI_ram_change
    );
  dsc_change_mode_8635 : FD
    port map (
      C => clk,
      D => dsc_change_mode_mux0000_11651,
      Q => NlwRenamedSig_OI_dsc_change_mode
    );
  dsc_change_adr_8636 : FD
    port map (
      C => clk,
      D => dsc_change_adr_mux0000,
      Q => NlwRenamedSig_OI_dsc_change_adr
    );
  ram_sel_0 : FD
    port map (
      C => clk,
      D => ram_sel_mux0000(2),
      Q => NlwRenamedSig_OI_ram_sel(0)
    );
  ram_sel_1 : FD
    port map (
      C => clk,
      D => ram_sel_mux0000(1),
      Q => NlwRenamedSig_OI_ram_sel(1)
    );
  ram_sel_2 : FD
    port map (
      C => clk,
      D => ram_sel_mux0000(0),
      Q => NlwRenamedSig_OI_ram_sel(2)
    );
  dma1_ctrl_z : FD
    port map (
      C => clk,
      D => dma1_ctrl(0),
      Q => dma1_ctrl_z_11587
    );
  dma_flag_start : FDRE
    port map (
      C => clk,
      CE => dma_flag_start_not0001,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma_flag_start_or0000,
      Q => dma_flag_start_11619
    );
  pci_adr_we_8642 : FD
    port map (
      C => clk,
      D => pci_adr_we_mux0000_11666,
      Q => NlwRenamedSig_OI_pci_adr_we
    );
  dma1_sg_eot : FDRE
    port map (
      C => clk,
      CE => dma1_sg_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma1_ctrl_0_inv,
      Q => dma1_sg_eot_11595
    );
  dma0_ctrl_z : FD
    port map (
      C => clk,
      D => dma0_ctrl(0),
      Q => dma0_ctrl_z_11563
    );
  dma1_start : FDRE
    port map (
      C => clk,
      CE => dma1_start_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma1_ctrl_0_inv,
      Q => dma1_start_11597
    );
  dma0_start : FDRE
    port map (
      C => clk,
      CE => dma0_start_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma0_ctrl_0_inv,
      Q => dma0_start_11573
    );
  dma_reg0_0 : FD
    port map (
      C => clk,
      D => dma_reg0_mux0000(2),
      Q => NlwRenamedSig_OI_dma_reg0(0)
    );
  dma_reg0_1 : FD
    port map (
      C => clk,
      D => dma_reg0_mux0000(1),
      Q => NlwRenamedSig_OI_dma_reg0(1)
    );
  dma_reg0_2 : FD
    port map (
      C => clk,
      D => dma_reg0_mux0000(0),
      Q => NlwRenamedSig_OI_dma_reg0(2)
    );
  dma_eot_set : FD
    port map (
      C => clk,
      D => dma_eot_set_mux0000_11618,
      Q => dma_eot_set_11617
    );
  dma0_sg_eot : FDRE
    port map (
      C => clk,
      CE => dma0_sg_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma0_ctrl_0_inv,
      Q => dma0_sg_eot_11571
    );
  dma0_eot : FDRE
    port map (
      C => clk,
      CE => dma0_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma0_eot_or0000,
      Q => dma0_eot_11565
    );
  reg_dma0_status_4 : FD
    port map (
      C => clk,
      D => reg_dma0_status_4_or0000,
      Q => reg_dma0_status(4)
    );
  init_compelte : FD
    port map (
      C => clk,
      D => init_compelte_mux0000_11660,
      Q => init_compelte_11659
    );
  pci_adr_h_we_8655 : FD
    port map (
      C => clk,
      D => pci_adr_h_we_mux0000_11664,
      Q => NlwRenamedSig_OI_pci_adr_h_we
    );
  dma1_wait_eot : FDRE
    port map (
      C => clk,
      CE => dma1_wait_eot_and0000,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma1_wait_eot_or0000,
      Q => dma1_wait_eot_11600
    );
  dma_transfer_start : FDRE
    port map (
      C => clk,
      CE => dma_transfer_start_not0001,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma_flag_start_or0000,
      Q => dma_transfer_start_11644
    );
  dma_chni : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => dma_chni_not0001,
      D => dma_chni_mux0000_11615,
      Q => NlwRenamedSig_OI_dma_chni
    );
  reg_dma1_status_4 : FD
    port map (
      C => clk,
      D => reg_dma1_status_4_or0000,
      Q => reg_dma1_status(4)
    );
  reg_dma0_status_7 : FDR
    port map (
      C => clk,
      D => dma0_ctrl(5),
      R => reg_dma0_status_4_or0000_inv,
      Q => reg_dma0_status(7)
    );
  reg_dma1_status_7 : FDR
    port map (
      C => clk,
      D => dma1_ctrl(5),
      R => reg_dma1_status_4_or0000_inv,
      Q => reg_dma1_status(7)
    );
  rstp : FDR
    port map (
      C => clk,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => reset,
      Q => rstp_11696
    );
  reg_dma1_status_5 : FD
    port map (
      C => clk,
      D => dma1_sg_eot_11595,
      Q => reg_dma1_status(5)
    );
  reg_dma1_status_6 : FD
    port map (
      C => clk,
      D => dma1_wait_eot_11600,
      Q => reg_dma1_status(6)
    );
  dma_chn_change : FDR
    port map (
      C => clk,
      D => dma_chn_change_mux0000_11610,
      R => rstp_11696,
      Q => dma_chn_change_11609
    );
  dma0_flag_start : FDRE
    port map (
      C => clk,
      CE => dma0_ctrl_z_inv,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma0_flag_start_or0000,
      Q => dma0_flag_start_11569
    );
  reg_dma1_status_8 : FDE
    port map (
      C => clk,
      CE => NlwRenamedSig_OI_dma_chni,
      D => dsc_correct,
      Q => reg_dma1_status(8)
    );
  dma1_block_z : FD
    port map (
      C => clk,
      D => dma1_block,
      Q => dma1_block_z_11583
    );
  dma0_block_z : FD
    port map (
      C => clk,
      D => dma0_block,
      Q => dma0_block_z_11559
    );
  dma_rotate : FDRE
    port map (
      C => clk,
      CE => dma_rotate_not0001,
      D => dma_rotate_mux0004,
      R => rstp_11696,
      Q => dma_rotate_11633
    );
  dma1_flag_start : FDRE
    port map (
      C => clk,
      CE => dma1_ctrl_z_inv,
      D => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      R => dma1_flag_start_or0000,
      Q => dma1_flag_start_11593
    );
  reg_dma0_status_0 : FD
    port map (
      C => clk,
      D => dma0_start_11573,
      Q => reg_dma0_status(0)
    );
  reg_dma1_status_0 : FD
    port map (
      C => clk,
      D => dma1_start_11597,
      Q => reg_dma1_status(0)
    );
  reg_dma0_status_5 : FD
    port map (
      C => clk,
      D => dma0_sg_eot_11571,
      Q => reg_dma0_status(5)
    );
  reg_dma0_status_6 : FD
    port map (
      C => clk,
      D => dma0_wait_eot_11576,
      Q => reg_dma0_status(6)
    );
  reg_dma0_status_8 : FDE
    port map (
      C => clk,
      CE => dma_chni_inv,
      D => dsc_correct,
      Q => reg_dma0_status(8)
    );
  xb0 : SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      A1 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      A2 => NlwRenamedSig_OI_reg_dma0_status_1_Q,
      A3 => NlwRenamedSig_OI_reg_dma0_status_1_Q,
      CLK => clk,
      D => dma0_block_in,
      Q => dma0_block
    );
  xb1 : SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      A1 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      A2 => NlwRenamedSig_OI_reg_dma0_status_1_Q,
      A3 => NlwRenamedSig_OI_reg_dma0_status_1_Q,
      CLK => clk,
      D => dma1_block_in,
      Q => dma1_block
    );
  stw_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd1_In,
      R => stw_or0000,
      Q => stw_FSM_FFd1_11735
    );
  stw_FSM_FFd10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd10_In,
      R => stw_or0000,
      Q => stw_FSM_FFd10_11737
    );
  stw_FSM_FFd11 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd11_In,
      S => stw_or0000,
      Q => stw_FSM_FFd11_11739
    );
  stw_FSM_FFd9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd10_11737,
      R => stw_or0000,
      Q => stw_FSM_FFd9_11748
    );
  stw_FSM_FFd8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd9_11748,
      R => stw_or0000,
      Q => stw_FSM_FFd8_11747
    );
  stw_FSM_FFd7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd8_11747,
      R => stw_or0000,
      Q => stw_FSM_FFd7_11746
    );
  stw_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd7_11746,
      R => stw_or0000,
      Q => stw_FSM_FFd6_11745
    );
  stw_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd6_11745,
      R => stw_or0000,
      Q => stw_FSM_FFd5_11744
    );
  stw_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd5_11744,
      R => stw_or0000,
      Q => stw_FSM_FFd4_11743
    );
  stw_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd4_11743,
      R => stw_or0000,
      Q => stw_FSM_FFd3_11742
    );
  stw_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stw_FSM_FFd3_11742,
      R => stw_or0000,
      Q => stw_FSM_FFd2_11741
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_In,
      R => rstp_11696,
      Q => stp_FSM_FFd3_11727
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstp_11696,
      Q => stp_FSM_FFd1_11697
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd2_In,
      R => rstp_11696,
      Q => stp_FSM_FFd2_11719
    );
  stp_FSM_FFd10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd10_In,
      R => rstp_11696,
      Q => stp_FSM_FFd10_11699
    );
  stp_FSM_FFd11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd11_In,
      R => rstp_11696,
      Q => stp_FSM_FFd11_11701
    );
  stp_FSM_FFd14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd14_In,
      R => rstp_11696,
      Q => stp_FSM_FFd14_11707
    );
  stp_FSM_FFd12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd12_In,
      R => rstp_11696,
      Q => stp_FSM_FFd12_11703
    );
  stp_FSM_FFd13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd13_In,
      R => rstp_11696,
      Q => stp_FSM_FFd13_11705
    );
  stp_FSM_FFd17 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd17_In,
      R => rstp_11696,
      Q => stp_FSM_FFd17_11713
    );
  stp_FSM_FFd15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd15_In,
      R => rstp_11696,
      Q => stp_FSM_FFd15_11709
    );
  stp_FSM_FFd16 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd16_In,
      R => rstp_11696,
      Q => stp_FSM_FFd16_11711
    );
  stp_FSM_FFd20 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd20_In,
      R => rstp_11696,
      Q => stp_FSM_FFd20_11721
    );
  stp_FSM_FFd18 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd18_In,
      R => rstp_11696,
      Q => stp_FSM_FFd18_11715
    );
  stp_FSM_FFd19 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd19_In,
      R => rstp_11696,
      Q => stp_FSM_FFd19_11717
    );
  stp_FSM_FFd21 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd21_In,
      R => rstp_11696,
      Q => stp_FSM_FFd21_11723
    );
  stp_FSM_FFd22 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd22_In_11726,
      S => rstp_11696,
      Q => stp_FSM_FFd22_11725
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd10_11699,
      R => rstp_11696,
      Q => stp_FSM_FFd6_11731
    );
  stp_FSM_FFd9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd15_11709,
      R => rstp_11696,
      Q => stp_FSM_FFd9_11734
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd6_11731,
      R => rstp_11696,
      Q => stp_FSM_FFd5_11730
    );
  stp_FSM_FFd8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd9_11734,
      R => rstp_11696,
      Q => stp_FSM_FFd8_11733
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd5_11730,
      R => rstp_11696,
      Q => stp_FSM_FFd4_11729
    );
  stp_FSM_FFd7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd8_11733,
      R => rstp_11696,
      Q => stp_FSM_FFd7_11732
    );
  stw_FSM_FFd11_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => stp_FSM_FFd19_11717,
      I1 => stw_FSM_FFd11_11739,
      O => stw_FSM_FFd11_In
    );
  stw_FSM_FFd10_In1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => stp_FSM_FFd19_11717,
      I1 => stw_FSM_FFd11_11739,
      O => stw_FSM_FFd10_In
    );
  stw_FSM_FFd1_In1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stw_FSM_FFd1_11735,
      I1 => stw_FSM_FFd2_11741,
      O => stw_FSM_FFd1_In
    );
  stp_FSM_FFd18_In1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => init_compelte_11659,
      I1 => stp_FSM_FFd19_11717,
      O => stp_FSM_FFd18_In
    );
  stp_FSM_FFd11_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd12_11703,
      O => stp_FSM_FFd11_In
    );
  stp_FSM_FFd1_In1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd2_11719,
      O => stp_FSM_FFd1_In
    );
  dma1_wait_eot2_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma1_eot_11589,
      I1 => dma1_wait_eot_11600,
      O => dma1_wait_eot2_and0000
    );
  dma0_wait_eot2_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma0_eot_11565,
      I1 => dma0_wait_eot_11576,
      O => dma0_wait_eot2_and0000
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd3_11727,
      I2 => stp_FSM_FFd4_11729,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd20_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => dma_transfer_start_11644,
      I1 => stp_FSM_FFd22_11725,
      I2 => dma_flag_start_11619,
      O => stp_FSM_FFd20_In
    );
  stp_FSM_FFd2_In1 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => stp_FSM_FFd3_11727,
      I1 => dma_status(0),
      I2 => stp_FSM_FFd2_11719,
      O => stp_FSM_FFd2_In
    );
  stp_FSM_FFd19_In1 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => stp_FSM_FFd21_11723,
      I1 => init_compelte_11659,
      I2 => stp_FSM_FFd19_11717,
      O => stp_FSM_FFd19_In
    );
  stp_FSM_FFd17_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd18_11715,
      I1 => dma_status(0),
      I2 => stp_FSM_FFd17_11713,
      O => stp_FSM_FFd17_In
    );
  stp_FSM_FFd14_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd20_11721,
      I1 => dma_status(0),
      I2 => stp_FSM_FFd14_11707,
      O => stp_FSM_FFd14_In
    );
  dma_rotate_mux00041 : LUT3
    generic map(
      INIT => X"51"
    )
    port map (
      I0 => dma0_flag_start_11569,
      I1 => dma_rotate_11633,
      I2 => dma1_flag_start_11593,
      O => dma_rotate_mux0004
    );
  stp_FSM_FFd21_In1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => init_compelte_11659,
      I1 => stp_FSM_FFd21_11723,
      I2 => dma_flag_start_11619,
      I3 => stp_FSM_FFd22_11725,
      O => stp_FSM_FFd21_In
    );
  stp_FSM_FFd16_In1 : LUT5
    generic map(
      INIT => X"88088000"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd17_11713,
      I2 => NlwRenamedSig_OI_dma_chni,
      I3 => dma1_ctrl_z_11587,
      I4 => dma0_ctrl_z_11563,
      O => stp_FSM_FFd16_In
    );
  dma1_sg_eot_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma_sg_eot_set_11636,
      I1 => NlwRenamedSig_OI_dma_chni,
      O => dma1_sg_eot_and0000
    );
  dma1_eot_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma_eot_set_11617,
      I1 => NlwRenamedSig_OI_dma_chni,
      O => dma1_eot_and0000
    );
  dma0_sg_eot_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_chni,
      I1 => dma_sg_eot_set_11636,
      O => dma0_sg_eot_and0000
    );
  dma0_eot_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_chni,
      I1 => dma_eot_set_11617,
      O => dma0_eot_and0000
    );
  dma1_wait_eot_and00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => dma_eot_set_11617,
      I1 => dma1_eot_11589,
      I2 => NlwRenamedSig_OI_dma_chni,
      O => dma1_wait_eot_and0000
    );
  dma0_wait_eot_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => dma_eot_set_11617,
      I1 => dma0_eot_11565,
      I2 => NlwRenamedSig_OI_dma_chni,
      O => dma0_wait_eot_and0000
    );
  dma_flag_start_not00011 : LUT4
    generic map(
      INIT => X"0302"
    )
    port map (
      I0 => dma0_flag_start_11569,
      I1 => dma_flag_start_11619,
      I2 => dma_transfer_start_11644,
      I3 => dma1_flag_start_11593,
      O => dma_flag_start_not0001
    );
  dma1_block_in_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => stp_FSM_FFd14_11707,
      I1 => NlwRenamedSig_OI_dma_chni,
      O => dma1_block_in
    );
  dma0_block_in_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_chni,
      I1 => stp_FSM_FFd14_11707,
      O => dma0_block_in
    );
  ram_sel_mux0000_1_1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => NlwRenamedSig_OI_ram_sel(1),
      I1 => N1,
      I2 => stw_FSM_FFd4_11743,
      O => ram_sel_mux0000(1)
    );
  stp_FSM_FFd12_In1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd12_11703,
      I2 => dma_status(2),
      I3 => N21,
      O => stp_FSM_FFd12_In
    );
  ram_sel_mux0000_2_1 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => NlwRenamedSig_OI_ram_sel(0),
      I1 => N1,
      I2 => stw_FSM_FFd10_11737,
      I3 => stw_FSM_FFd4_11743,
      O => ram_sel_mux0000(2)
    );
  stp_FSM_FFd13_In1 : LUT5
    generic map(
      INIT => X"FFFFF444"
    )
    port map (
      I0 => dma_status(2),
      I1 => N21,
      I2 => dma_status(0),
      I3 => stp_FSM_FFd13_11705,
      I4 => stp_FSM_FFd7_11732,
      O => stp_FSM_FFd13_In
    );
  ram_sel_mux0000_0_2 : LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
    port map (
      I0 => stw_FSM_FFd4_11743,
      I1 => stw_FSM_FFd10_11737,
      I2 => N1,
      I3 => NlwRenamedSig_OI_ram_sel(2),
      I4 => stw_FSM_FFd7_11746,
      O => ram_sel_mux0000(0)
    );
  dma_change_adr_mux000021 : LUT5
    generic map(
      INIT => X"88088000"
    )
    port map (
      I0 => dma_status(0),
      I1 => stp_FSM_FFd14_11707,
      I2 => NlwRenamedSig_OI_dma_chni,
      I3 => dma1_ctrl_z_11587,
      I4 => dma0_ctrl_z_11563,
      O => N21
    );
  ram_sel_mux0000_0_11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stw_FSM_FFd9_11748,
      I1 => stw_FSM_FFd8_11747,
      I2 => stw_FSM_FFd6_11745,
      I3 => stw_FSM_FFd5_11744,
      I4 => stw_FSM_FFd3_11742,
      I5 => stw_FSM_FFd2_11741,
      O => N1
    );
  stp_FSM_FFd22_In_SW0 : LUT5
    generic map(
      INIT => X"05AF048C"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_chni,
      I1 => stp_FSM_FFd17_11713,
      I2 => dma0_ctrl_z_11563,
      I3 => dma1_ctrl_z_11587,
      I4 => stp_FSM_FFd14_11707,
      O => N01
    );
  stp_FSM_FFd22_In : LUT6
    generic map(
      INIT => X"FFFFFF1010FF1010"
    )
    port map (
      I0 => dma_transfer_start_11644,
      I1 => dma_flag_start_11619,
      I2 => stp_FSM_FFd22_11725,
      I3 => dma_status(0),
      I4 => stp_FSM_FFd13_11705,
      I5 => N01,
      O => stp_FSM_FFd22_In_11726
    );
  stw_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd22_11725,
      I1 => stp_FSM_FFd21_11723,
      O => stw_or0000
    );
  dma_flag_start_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => dma_chn_change_11609,
      I1 => rstp_11696,
      O => dma_flag_start_or0000
    );
  dma1_eot_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => dma1_ctrl(0),
      I1 => dma1_eot_clr,
      O => dma1_eot_or0000
    );
  dma0_eot_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => dma0_ctrl(0),
      I1 => dma0_eot_clr,
      O => dma0_eot_or0000
    );
  dma1_wait_eot_or00001 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => dma1_ctrl(0),
      I1 => dma1_eot_clr,
      I2 => dma1_wait_eot2_11601,
      O => dma1_wait_eot_or0000
    );
  dma0_wait_eot_or00001 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => dma0_ctrl(0),
      I1 => dma0_eot_clr,
      I2 => dma0_wait_eot2_11577,
      O => dma0_wait_eot_or0000
    );
  dma_chni_not000121 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => dma_chn_change_11609,
      I1 => dma_flag_start_11619,
      I2 => dma_transfer_start_11644,
      O => dma_rotate_not0001
    );
  dma_transfer_start_or00011 : LUT5
    generic map(
      INIT => X"FFFFFFFB"
    )
    port map (
      I0 => dma0_block_z_11559,
      I1 => dma0_transfer_rdy,
      I2 => dma_rotate_11633,
      I3 => dma0_wait_eot_11576,
      I4 => dma0_sg_eot_11571,
      O => dma_transfer_start_or0001
    );
  dma_transfer_start_or00001 : LUT5
    generic map(
      INIT => X"FFFFFFBF"
    )
    port map (
      I0 => dma1_wait_eot_11600,
      I1 => dma_rotate_11633,
      I2 => dma1_transfer_rdy,
      I3 => dma1_block_z_11583,
      I4 => dma1_sg_eot_11595,
      O => dma_transfer_start_or0000
    );
  dma_transfer_start_not00011 : LUT6
    generic map(
      INIT => X"0000000100010001"
    )
    port map (
      I0 => dma0_flag_start_11569,
      I1 => dma1_flag_start_11593,
      I2 => dma_flag_start_11619,
      I3 => dma_transfer_start_11644,
      I4 => dma_transfer_start_or0000,
      I5 => dma_transfer_start_or0001,
      O => dma_transfer_start_not0001
    );
  dma_chni_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFC8CCCCCC"
    )
    port map (
      I0 => dma0_flag_start_11569,
      I1 => dma_rotate_not0001,
      I2 => dma1_flag_start_11593,
      I3 => dma_transfer_start_or0000,
      I4 => dma_transfer_start_or0001,
      I5 => rstp_11696,
      O => dma_chni_not0001
    );
  dma_chni_mux0000_SW0 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => dma0_sg_eot_11571,
      I1 => dma_rotate_11633,
      I2 => dma1_flag_start_11593,
      I3 => dma0_block_z_11559,
      O => N2
    );
  dma_chni_mux0000 : LUT6
    generic map(
      INIT => X"0203CECF0303CFCF"
    )
    port map (
      I0 => dma0_wait_eot_11576,
      I1 => rstp_11696,
      I2 => dma0_flag_start_11569,
      I3 => dma0_transfer_rdy,
      I4 => NlwRenamedSig_OI_dma_chni,
      I5 => N2,
      O => dma_chni_mux0000_11615
    );
  pci_adr_we_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stw_FSM_FFd4_11743,
      I1 => stw_FSM_FFd7_11746,
      I2 => stw_FSM_FFd8_11747,
      I3 => stw_FSM_FFd10_11737,
      I4 => stw_FSM_FFd9_11748,
      O => N41
    );
  pci_adr_we_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stw_FSM_FFd2_11741,
      I1 => NlwRenamedSig_OI_pci_adr_we,
      I2 => stw_FSM_FFd1_11735,
      I3 => stw_FSM_FFd3_11742,
      I4 => N41,
      I5 => stw_FSM_FFd6_11745,
      O => pci_adr_we_mux0000_11666
    );
  pci_adr_h_we_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stw_FSM_FFd3_11742,
      I1 => stw_FSM_FFd4_11743,
      I2 => stw_FSM_FFd6_11745,
      I3 => stw_FSM_FFd7_11746,
      I4 => stw_FSM_FFd10_11737,
      O => N6
    );
  pci_adr_h_we_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stw_FSM_FFd2_11741,
      I1 => NlwRenamedSig_OI_pci_adr_h_we,
      I2 => stw_FSM_FFd5_11744,
      I3 => stw_FSM_FFd1_11735,
      I4 => N6,
      I5 => stw_FSM_FFd9_11748,
      O => pci_adr_h_we_mux0000_11664
    );
  loc_adr_we_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stw_FSM_FFd6_11745,
      I1 => stw_FSM_FFd7_11746,
      I2 => stw_FSM_FFd8_11747,
      I3 => stw_FSM_FFd10_11737,
      I4 => stw_FSM_FFd9_11748,
      O => N8
    );
  loc_adr_we_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stw_FSM_FFd5_11744,
      I1 => NlwRenamedSig_OI_loc_adr_we,
      I2 => stw_FSM_FFd1_11735,
      I3 => stw_FSM_FFd4_11743,
      I4 => N8,
      I5 => stw_FSM_FFd3_11742,
      O => loc_adr_we_mux0000_11662
    );
  dma_reg0_mux0000_2_1 : LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
    port map (
      I0 => stp_FSM_FFd2_11719,
      I1 => stp_FSM_FFd17_11713,
      I2 => NlwRenamedSig_OI_dma_reg0(0),
      I3 => N0,
      I4 => stp_FSM_FFd14_11707,
      O => dma_reg0_mux0000(2)
    );
  dsc_change_adr_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEEEA"
    )
    port map (
      I0 => stp_FSM_FFd19_11717,
      I1 => NlwRenamedSig_OI_dsc_change_adr,
      I2 => N16,
      I3 => stp_FSM_FFd20_11721,
      I4 => stp_FSM_FFd11_11701,
      I5 => stp_FSM_FFd5_11730,
      O => dsc_change_adr_mux0000
    );
  dma_reg0_mux0000_0_1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
    port map (
      I0 => stp_FSM_FFd14_11707,
      I1 => stp_FSM_FFd13_11705,
      I2 => NlwRenamedSig_OI_dma_reg0(2),
      I3 => N0,
      I4 => stp_FSM_FFd22_11725,
      I5 => stp_FSM_FFd21_11723,
      O => dma_reg0_mux0000(0)
    );
  init_compelte_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stw_FSM_FFd4_11743,
      I1 => stw_FSM_FFd6_11745,
      I2 => stw_FSM_FFd7_11746,
      I3 => stw_FSM_FFd8_11747,
      I4 => stw_FSM_FFd10_11737,
      I5 => stw_FSM_FFd9_11748,
      O => N10
    );
  init_compelte_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stw_FSM_FFd2_11741,
      I1 => init_compelte_11659,
      I2 => stw_FSM_FFd5_11744,
      I3 => stw_FSM_FFd3_11742,
      I4 => N10,
      I5 => stw_FSM_FFd1_11735,
      O => init_compelte_mux0000_11660
    );
  dma_change_adr_mux000016 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd16_11711,
      I1 => stp_FSM_FFd20_11721,
      I2 => stp_FSM_FFd12_11703,
      I3 => stp_FSM_FFd19_11717,
      I4 => stp_FSM_FFd9_11734,
      I5 => stp_FSM_FFd14_11707,
      O => dma_change_adr_mux000016_11607
    );
  dma_change_adr_mux000025 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd5_11730,
      I1 => stp_FSM_FFd8_11733,
      I2 => stp_FSM_FFd2_11719,
      I3 => stp_FSM_FFd1_11697,
      I4 => stp_FSM_FFd6_11731,
      O => dma_change_adr_mux000025_11608
    );
  reg_dma1_status_4_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => dma1_eot_11589,
      I1 => dma1_wait_eot2_11601,
      O => reg_dma1_status_4_or0000
    );
  reg_dma0_status_4_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => dma0_eot_11565,
      I1 => dma0_wait_eot2_11577,
      O => reg_dma0_status_4_or0000
    );
  dma1_start_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => dma_flag_start_clr_11620,
      I1 => NlwRenamedSig_OI_dma_chni,
      O => dma1_start_and0000
    );
  dma0_start_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_dma_chni,
      I1 => dma_flag_start_clr_11620,
      O => dma0_start_and0000
    );
  dma_flag_start_clr_mux00001 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => N4,
      I1 => dma_flag_start_clr_11620,
      I2 => stp_FSM_FFd16_11711,
      I3 => stp_FSM_FFd1_11697,
      O => dma_flag_start_clr_mux0000
    );
  dsc_load_en_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FF32"
    )
    port map (
      I0 => stp_FSM_FFd17_11713,
      I1 => dma_status(1),
      I2 => stp_FSM_FFd2_11719,
      I3 => stp_FSM_FFd19_11717,
      O => N14
    );
  dsc_load_en_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => N0,
      I1 => NlwRenamedSig_OI_dsc_load_en,
      I2 => stp_FSM_FFd14_11707,
      I3 => stp_FSM_FFd13_11705,
      I4 => stp_FSM_FFd12_11703,
      I5 => N14,
      O => dsc_load_en_mux0000_11658
    );
  dma_chn_change_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd10_11699,
      I1 => stp_FSM_FFd15_11709,
      I2 => stp_FSM_FFd11_11701,
      I3 => stp_FSM_FFd21_11723,
      O => N161
    );
  dma_chn_change_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => N16,
      I1 => dma_chn_change_11609,
      I2 => stp_FSM_FFd5_11730,
      I3 => stp_FSM_FFd18_11715,
      I4 => N161,
      I5 => stp_FSM_FFd22_11725,
      O => dma_chn_change_mux0000_11610
    );
  dma_reg0_mux0000_1_110 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd11_11701,
      I1 => stp_FSM_FFd15_11709,
      I2 => stp_FSM_FFd5_11730,
      I3 => stp_FSM_FFd20_11721,
      I4 => stp_FSM_FFd9_11734,
      I5 => stp_FSM_FFd10_11699,
      O => dma_reg0_mux0000_1_110_11630
    );
  dma_reg0_mux0000_1_119 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd4_11729,
      I1 => stp_FSM_FFd8_11733,
      I2 => stp_FSM_FFd1_11697,
      I3 => stp_FSM_FFd18_11715,
      I4 => stp_FSM_FFd6_11731,
      O => dma_reg0_mux0000_1_119_11631
    );
  dma_sg_eot_set_mux00001110 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd19_11717,
      I1 => stp_FSM_FFd18_11715,
      I2 => stp_FSM_FFd17_11713,
      I3 => stp_FSM_FFd20_11721,
      I4 => stp_FSM_FFd14_11707,
      I5 => stp_FSM_FFd9_11734,
      O => dma_sg_eot_set_mux00001110_11639
    );
  dma_sg_eot_set_mux00001121 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd8_11733,
      I1 => stp_FSM_FFd7_11732,
      I2 => stp_FSM_FFd6_11731,
      I3 => stp_FSM_FFd5_11730,
      I4 => stp_FSM_FFd4_11729,
      I5 => stp_FSM_FFd2_11719,
      O => dma_sg_eot_set_mux00001121_11640
    );
  dma_sg_eot_set_mux00001122 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => dma_sg_eot_set_mux00001110_11639,
      I1 => dma_sg_eot_set_mux00001121_11640,
      O => N19
    );
  dma_chn_change_mux00001110 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd12_11703,
      I1 => stp_FSM_FFd13_11705,
      I2 => stp_FSM_FFd2_11719,
      I3 => stp_FSM_FFd14_11707,
      I4 => stp_FSM_FFd9_11734,
      I5 => stp_FSM_FFd3_11727,
      O => dma_chn_change_mux00001110_11611
    );
  dma_chn_change_mux00001119 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd4_11729,
      I1 => stp_FSM_FFd8_11733,
      I2 => stp_FSM_FFd1_11697,
      I3 => stp_FSM_FFd17_11713,
      I4 => stp_FSM_FFd6_11731,
      O => dma_chn_change_mux00001119_11612
    );
  stp_FSM_FFd10_In1 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => dsc_cmd(1),
      I1 => dsc_cmd(2),
      I2 => dsc_cmd(0),
      I3 => stp_FSM_FFd11_11701,
      O => stp_FSM_FFd10_In
    );
  stp_FSM_FFd15_In1 : LUT6
    generic map(
      INIT => X"FFFFFFFFEEEAEEEE"
    )
    port map (
      I0 => stp_FSM_FFd16_11711,
      I1 => stp_FSM_FFd11_11701,
      I2 => dsc_cmd(0),
      I3 => dsc_cmd(2),
      I4 => dsc_cmd(1),
      I5 => stp_FSM_FFd1_11697,
      O => stp_FSM_FFd15_In
    );
  dma_sg_eot_set_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FF323232"
    )
    port map (
      I0 => stp_FSM_FFd1_11697,
      I1 => dsc_correct,
      I2 => stp_FSM_FFd16_11711,
      I3 => dma_sg_eot_set_11636,
      I4 => N4,
      O => N22
    );
  dma_sg_eot_set_mux0000 : LUT5
    generic map(
      INIT => X"AAABAAAA"
    )
    port map (
      I0 => N22,
      I1 => dsc_cmd(2),
      I2 => dsc_cmd(1),
      I3 => dsc_cmd(0),
      I4 => stp_FSM_FFd11_11701,
      O => dma_sg_eot_set_mux0000_11637
    );
  dma_eot_set_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd3_11727,
      I1 => stp_FSM_FFd13_11705,
      I2 => stp_FSM_FFd12_11703,
      I3 => stp_FSM_FFd16_11711,
      O => N24
    );
  dma_eot_set_mux0000 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => dma_eot_set_11617,
      I1 => N19,
      I2 => stp_FSM_FFd1_11697,
      I3 => N24,
      I4 => dsc_cmd(4),
      I5 => stp_FSM_FFd11_11701,
      O => dma_eot_set_mux0000_11618
    );
  dma_reg0_mux0000_1_126 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => dma_reg0_mux0000_1_110_11630,
      I1 => stp_FSM_FFd7_11732,
      I2 => stp_FSM_FFd16_11711,
      I3 => dma_reg0_mux0000_1_119_11631,
      O => N0
    );
  dma_chn_change_mux00001126 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => dma_chn_change_mux00001110_11611,
      I1 => stp_FSM_FFd7_11732,
      I2 => stp_FSM_FFd16_11711,
      I3 => dma_chn_change_mux00001119_11612,
      O => N16
    );
  dma_change_adr_mux000057_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => dma_change_adr_mux000016_11607,
      I1 => dma_change_adr_mux000025_11608,
      I2 => stp_FSM_FFd10_11699,
      I3 => stp_FSM_FFd15_11709,
      O => N29
    );
  dma_change_adr_mux000057 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
    port map (
      I0 => stp_FSM_FFd18_11715,
      I1 => stp_FSM_FFd4_11729,
      I2 => NlwRenamedSig_OI_dma_change_adr,
      I3 => N29,
      I4 => stp_FSM_FFd7_11732,
      I5 => N21,
      O => dma_change_adr_mux0000
    );
  reg_dma1_status_4_or0000_inv1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => dma1_eot_11589,
      I1 => dma1_wait_eot2_11601,
      O => reg_dma1_status_4_or0000_inv
    );
  reg_dma0_status_4_or0000_inv1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => dma0_eot_11565,
      I1 => dma0_wait_eot2_11577,
      O => reg_dma0_status_4_or0000_inv
    );
  dma1_flag_start_or00001 : LUT3
    generic map(
      INIT => X"D5"
    )
    port map (
      I0 => dma1_ctrl(0),
      I1 => dma_flag_start_clr_11620,
      I2 => NlwRenamedSig_OI_dma_chni,
      O => dma1_flag_start_or0000
    );
  dma0_flag_start_or00001 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => dma0_ctrl(0),
      I1 => dma_flag_start_clr_11620,
      I2 => NlwRenamedSig_OI_dma_chni,
      O => dma0_flag_start_or0000
    );
  dsc_change_mode_mux0000_SW2 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => N16,
      I1 => stp_FSM_FFd10_11699,
      I2 => stp_FSM_FFd11_11701,
      I3 => stp_FSM_FFd15_11709,
      I4 => stp_FSM_FFd18_11715,
      O => N31
    );
  dsc_change_mode_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd20_11721,
      I1 => dsc_cmd(2),
      I2 => N31,
      I3 => NlwRenamedSig_OI_dsc_change_mode,
      I4 => stp_FSM_FFd5_11730,
      I5 => stp_FSM_FFd19_11717,
      O => dsc_change_mode_mux0000_11651
    );
  dma_chni_inv1_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_dma_chni,
      O => dma_chni_inv
    );
  dma1_ctrl_z_inv1_INV_0 : INV
    port map (
      I => dma1_ctrl_z_11587,
      O => dma1_ctrl_z_inv
    );
  dma0_ctrl_z_inv1_INV_0 : INV
    port map (
      I => dma0_ctrl_z_11563,
      O => dma0_ctrl_z_inv
    );
  dma1_ctrl_0_inv1_INV_0 : INV
    port map (
      I => dma1_ctrl(0),
      O => dma1_ctrl_0_inv
    );
  dma0_ctrl_0_inv1_INV_0 : INV
    port map (
      I => dma0_ctrl(0),
      O => dma0_ctrl_0_inv
    );
  dma_reg0_mux0000_1_1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEEE"
    )
    port map (
      I0 => stp_FSM_FFd13_11705,
      I1 => stp_FSM_FFd12_11703,
      I2 => N0,
      I3 => NlwRenamedSig_OI_dma_reg0(1),
      I4 => stp_FSM_FFd14_11707,
      I5 => stp_FSM_FFd21_11723,
      O => dma_reg0_mux0000_1_1_11629
    );
  dma_reg0_mux0000_1_f7 : MUXF7
    port map (
      I0 => dma_reg0_mux0000_1_1_11629,
      I1 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      S => stp_FSM_FFd22_11725,
      O => dma_reg0_mux0000(1)
    );
  ram_change_mux00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => NlwRenamedSig_OI_ram_change,
      I1 => N21,
      O => ram_change_mux00001_11669
    );
  ram_change_mux00002 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => N19,
      I1 => NlwRenamedSig_OI_ram_change,
      I2 => stp_FSM_FFd1_11697,
      I3 => stp_FSM_FFd10_11699,
      I4 => stp_FSM_FFd15_11709,
      I5 => N21,
      O => ram_change_mux00002_11670
    );
  ram_change_mux0000_f7 : MUXF7
    port map (
      I0 => ram_change_mux00002_11670,
      I1 => ram_change_mux00001_11669,
      S => stp_FSM_FFd16_11711,
      O => ram_change_mux0000
    );
  dma_sg_eot_set_mux000011 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => N19,
      I1 => stp_FSM_FFd10_11699,
      I2 => stp_FSM_FFd13_11705,
      I3 => stp_FSM_FFd15_11709,
      I4 => stp_FSM_FFd12_11703,
      I5 => stp_FSM_FFd11_11701,
      O => dma_sg_eot_set_mux00001
    );
  dma_sg_eot_set_mux00001_f7 : MUXF7
    port map (
      I0 => dma_sg_eot_set_mux00001,
      I1 => NlwRenamedSig_OI_reg_dma0_status_13_Q,
      S => stp_FSM_FFd3_11727,
      O => N4
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity block_pe_fifo_ext is
  port (
    irq : out STD_LOGIC; 
    reg_ext_fifo_data_we : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_data_we : in STD_LOGIC := 'X'; 
    aclk : in STD_LOGIC := 'X'; 
    tx_ext_fifo_back_rd_size : out STD_LOGIC; 
    ext_fifo_disp_back_irq : in STD_LOGIC := 'X'; 
    tx_ext_fifo_complete_error : in STD_LOGIC := 'X'; 
    rstp : in STD_LOGIC := 'X'; 
    tx_ext_fifo_back_req_rd : out STD_LOGIC; 
    ext_fifo_disp_data_we : out STD_LOGIC; 
    rx_ext_fifo_data_we : in STD_LOGIC := 'X'; 
    tx_ext_fifo_back_req_wr : out STD_LOGIC; 
    ext_fifo_disp_request_rd : out STD_LOGIC; 
    ext_fifo_disp_back_allow_wr : in STD_LOGIC := 'X'; 
    tx_ext_fifo_complete_ok : in STD_LOGIC := 'X'; 
    ext_fifo_disp_request_wr : out STD_LOGIC; 
    ext_fifo_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    tx_ext_fifo_back_pci_adr : out STD_LOGIC_VECTOR ( 39 downto 8 ); 
    tx_ext_fifo_back_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    reg_ext_fifo_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    ext_fifo_disp_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_back_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_ext_fifo_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_ext_fifo_adr : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    rx_ext_fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    tx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    rx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ) 
  );
end block_pe_fifo_ext;

architecture STRUCTURE of block_pe_fifo_ext is
  component ctrl_main
    port (
      ram_we : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      dma1_transfer_rdy : in STD_LOGIC := 'X'; 
      dsc_change_adr : out STD_LOGIC; 
      dsc_load_en : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      loc_adr_we : out STD_LOGIC; 
      ram_change : out STD_LOGIC; 
      dsc_correct : in STD_LOGIC := 'X'; 
      dma0_transfer_rdy : in STD_LOGIC := 'X'; 
      dma1_eot_clr : in STD_LOGIC := 'X'; 
      dma0_eot_clr : in STD_LOGIC := 'X'; 
      pci_adr_we : out STD_LOGIC; 
      dsc_change_mode : out STD_LOGIC; 
      dma_change_adr : out STD_LOGIC; 
      dma_chn : out STD_LOGIC; 
      pci_adr_h_we : out STD_LOGIC; 
      ram_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
      ram_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      reg_dma1_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      reg_dma0_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      dma_reg0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      dma_status : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      dma0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dsc_cmd : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dma1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  component ctrl_ext_descriptor
    port (
      clk : in STD_LOGIC := 'X'; 
      dsc_change_adr : in STD_LOGIC := 'X'; 
      dsc_load_en : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      dsc_correct : out STD_LOGIC; 
      ram0_wr : in STD_LOGIC := 'X'; 
      pci_adr_we : in STD_LOGIC := 'X'; 
      dsc_change_mode : in STD_LOGIC := 'X'; 
      dma_chn : in STD_LOGIC := 'X'; 
      pci_adr_h_we : in STD_LOGIC := 'X'; 
      dsc_adr : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
      dsc_cmd : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dsc_adr_h : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dsc_size : out STD_LOGIC_VECTOR ( 23 downto 0 ); 
      test : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      dma_wrdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      dma_wraddr : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  component ctrl_dma_ext_cmd
    port (
      clk : in STD_LOGIC := 'X'; 
      tx_rd_size : out STD_LOGIC; 
      tx_req_rd : out STD_LOGIC; 
      tx_req_wr : out STD_LOGIC; 
      tx_ext_fifo_complete_error : in STD_LOGIC := 'X'; 
      rstp : in STD_LOGIC := 'X'; 
      rx_ext_fifo_data_we : in STD_LOGIC := 'X'; 
      dma_change_adr : in STD_LOGIC := 'X'; 
      tx_ext_fifo_complete_ok : in STD_LOGIC := 'X'; 
      dma_chn : in STD_LOGIC := 'X'; 
      dma_cmd_status : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      test : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      tx_pci_adr : out STD_LOGIC_VECTOR ( 39 downto 8 ); 
      dsc_adr : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
      rx_ext_fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      tx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
      dsc_adr_h : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
      dsc_size : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
      dma_reg0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component ctrl_ext_ram
    port (
      clk : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_data_we : in STD_LOGIC := 'X'; 
      dma1_transfer_rdy : out STD_LOGIC; 
      aclk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      loc_adr_we : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_irq : in STD_LOGIC := 'X'; 
      ram_change : in STD_LOGIC := 'X'; 
      dma_wr_en : in STD_LOGIC := 'X'; 
      dma0_transfer_rdy : out STD_LOGIC; 
      dma_wr : in STD_LOGIC := 'X'; 
      ext_fifo_disp_data_we : out STD_LOGIC; 
      ext_fifo_disp_request_rd : out STD_LOGIC; 
      ext_fifo_disp_back_allow_wr : in STD_LOGIC := 'X'; 
      dma_chn : in STD_LOGIC := 'X'; 
      ext_fifo_disp_request_wr : out STD_LOGIC; 
      ext_fifo_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      dma_rddata : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_back_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      dma_rdaddr : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      dma0_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dma_wrdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      dma1_ctrl : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      dma_wraddr : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal dma0_eot_clr_13005 : STD_LOGIC; 
  signal dma0_eot_clr_or0000_13006 : STD_LOGIC; 
  signal dma1_eot_clr_13007 : STD_LOGIC; 
  signal dma1_eot_clr_or0000_13008 : STD_LOGIC; 
  signal dma1_transfer_rdy : STD_LOGIC; 
  signal dma_change_adr : STD_LOGIC; 
  signal dsc_change_mode : STD_LOGIC; 
  signal irq_or0000 : STD_LOGIC; 
  signal loc_adr_we : STD_LOGIC; 
  signal pci_adr_h_we : STD_LOGIC; 
  signal pci_adr_we : STD_LOGIC; 
  signal ram1_wr : STD_LOGIC; 
  signal ram_change : STD_LOGIC; 
  signal ram_di_a_0_Q : STD_LOGIC; 
  signal ram_di_a_1_Q : STD_LOGIC; 
  signal ram_di_a_2_Q : STD_LOGIC; 
  signal ram_di_a_3_Q : STD_LOGIC; 
  signal ram_di_a_5_Q : STD_LOGIC; 
  signal ram_di_a_6_Q : STD_LOGIC; 
  signal ram_di_a_7_Q : STD_LOGIC; 
  signal ram_we_a : STD_LOGIC; 
  signal reg_dma0_ctrl_0_Q : STD_LOGIC; 
  signal reg_dma0_ctrl_3_Q : STD_LOGIC; 
  signal reg_dma0_ctrl_4_Q : STD_LOGIC; 
  signal reg_dma0_ctrl_not0001 : STD_LOGIC; 
  signal reg_dma0_mode_1_Q : STD_LOGIC; 
  signal reg_dma0_mode_2_Q : STD_LOGIC; 
  signal reg_dma0_mode_5_Q : STD_LOGIC; 
  signal reg_dma0_mode_not0001 : STD_LOGIC; 
  signal reg_dma0_status_0_Q : STD_LOGIC; 
  signal reg_dma0_status_4_Q : STD_LOGIC; 
  signal reg_dma0_status_5_Q : STD_LOGIC; 
  signal reg_dma0_status_6_Q : STD_LOGIC; 
  signal reg_dma0_status_7_Q : STD_LOGIC; 
  signal reg_dma0_status_8_Q : STD_LOGIC; 
  signal reg_dma1_ctrl_0_Q : STD_LOGIC; 
  signal reg_dma1_ctrl_3_Q : STD_LOGIC; 
  signal reg_dma1_ctrl_4_Q : STD_LOGIC; 
  signal reg_dma1_ctrl_not0001 : STD_LOGIC; 
  signal reg_dma1_mode_1_Q : STD_LOGIC; 
  signal reg_dma1_mode_2_Q : STD_LOGIC; 
  signal reg_dma1_mode_5_Q : STD_LOGIC; 
  signal reg_dma1_mode_not0001 : STD_LOGIC; 
  signal reg_dma1_status_0_Q : STD_LOGIC; 
  signal reg_dma1_status_4_Q : STD_LOGIC; 
  signal reg_dma1_status_5_Q : STD_LOGIC; 
  signal reg_dma1_status_6_Q : STD_LOGIC; 
  signal reg_dma1_status_7_Q : STD_LOGIC; 
  signal reg_dma1_status_8_Q : STD_LOGIC; 
  signal reset_13420 : STD_LOGIC; 
  signal reset_not0001_norst : STD_LOGIC; 
  signal NLW_cmd_test_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_cmd_test_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_cmd_test_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_cmd_test_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dsc_test_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dsc_test_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dsc_test_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dsc_test_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma1_status_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_reg_dma0_status_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ram_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal dma0_ctrl : STD_LOGIC_VECTOR ( 6 downto 6 ); 
  signal dma_cmd_status : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal dma_reg0 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal dsc_adr : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal dsc_adr_h : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal dsc_cmd : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal dsc_size : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal ram_adra : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal ram_do_a : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal ram_do_b : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_test : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  test(7) <= NlwRenamedSig_OI_test(7);
  test(6) <= NlwRenamedSig_OI_test(6);
  test(5) <= NlwRenamedSig_OI_test(5);
  test(4) <= NlwRenamedSig_OI_test(4);
  test(3) <= NlwRenamedSig_OI_test(3);
  test(2) <= NlwRenamedSig_OI_test(2);
  test(1) <= NlwRenamedSig_OI_test(1);
  test(0) <= NlwRenamedSig_OI_test(0);
  XST_GND : GND
    port map (
      G => dma0_ctrl(6)
    );
  XST_VCC : VCC
    port map (
      P => reset_not0001_norst
    );
  irq_8605 : FD
    port map (
      C => clk,
      D => irq_or0000,
      Q => irq
    );
  reg_dma0_mode_1 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_mode_not0001,
      D => reg_ext_fifo_data(1),
      R => rstp,
      Q => reg_dma0_mode_1_Q
    );
  reg_dma0_mode_2 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_mode_not0001,
      D => reg_ext_fifo_data(2),
      R => rstp,
      Q => reg_dma0_mode_2_Q
    );
  reg_dma0_mode_5 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_mode_not0001,
      D => reg_ext_fifo_data(5),
      R => rstp,
      Q => reg_dma0_mode_5_Q
    );
  dma1_eot_clr : FDR
    port map (
      C => clk,
      D => reg_ext_fifo_data(4),
      R => dma1_eot_clr_or0000_13008,
      Q => dma1_eot_clr_13007
    );
  reg_dma1_mode_1 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_mode_not0001,
      D => reg_ext_fifo_data(1),
      R => rstp,
      Q => reg_dma1_mode_1_Q
    );
  reg_dma1_mode_2 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_mode_not0001,
      D => reg_ext_fifo_data(2),
      R => rstp,
      Q => reg_dma1_mode_2_Q
    );
  reg_dma1_mode_5 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_mode_not0001,
      D => reg_ext_fifo_data(5),
      R => rstp,
      Q => reg_dma1_mode_5_Q
    );
  reg_dma0_ctrl_0 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_ctrl_not0001,
      D => reg_ext_fifo_data(0),
      R => rstp,
      Q => reg_dma0_ctrl_0_Q
    );
  reg_dma0_ctrl_3 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_ctrl_not0001,
      D => reg_ext_fifo_data(3),
      R => rstp,
      Q => reg_dma0_ctrl_3_Q
    );
  reg_dma0_ctrl_4 : FDRE
    port map (
      C => clk,
      CE => reg_dma0_ctrl_not0001,
      D => reg_ext_fifo_data(4),
      R => rstp,
      Q => reg_dma0_ctrl_4_Q
    );
  reset : FDR
    port map (
      C => clk,
      D => reset_not0001_norst,
      R => rstp,
      Q => reset_13420
    );
  dma0_eot_clr : FDR
    port map (
      C => clk,
      D => reg_ext_fifo_data(4),
      R => dma0_eot_clr_or0000_13006,
      Q => dma0_eot_clr_13005
    );
  reg_dma1_ctrl_0 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_ctrl_not0001,
      D => reg_ext_fifo_data(0),
      R => rstp,
      Q => reg_dma1_ctrl_0_Q
    );
  reg_dma1_ctrl_3 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_ctrl_not0001,
      D => reg_ext_fifo_data(3),
      R => rstp,
      Q => reg_dma1_ctrl_3_Q
    );
  reg_dma1_ctrl_4 : FDRE
    port map (
      C => clk,
      CE => reg_dma1_ctrl_not0001,
      D => reg_ext_fifo_data(4),
      R => rstp,
      Q => reg_dma1_ctrl_4_Q
    );
  ram : RAMB16
    generic map(
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      RAM_EXTENSION_B => "NONE",
      INIT_00 => X"0000000000000000000000000000000200000000000034000000010200001018",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000200000001000034000000010200001018",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SIM_COLLISION_CHECK => "NONE",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 36,
      READ_WIDTH_B => 36,
      WRITE_WIDTH_A => 36,
      WRITE_WIDTH_B => 36,
      SRVAL_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_ram_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_ram_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => clk,
      ENA => reset_not0001_norst,
      REGCEA => dma0_ctrl(6),
      REGCEB => dma0_ctrl(6),
      ENB => reset_not0001_norst,
      SSRA => dma0_ctrl(6),
      SSRB => dma0_ctrl(6),
      CASCADEOUTA => NLW_ram_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_ram_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_ram_ADDRA_14_UNCONNECTED,
      ADDRA(13) => ram_adra(8),
      ADDRA(12) => ram_adra(7),
      ADDRA(11) => ram_adra(6),
      ADDRA(10) => ram_adra(5),
      ADDRA(9) => ram_adra(4),
      ADDRA(8) => ram_adra(3),
      ADDRA(7) => ram_adra(2),
      ADDRA(6) => ram_adra(1),
      ADDRA(5) => ram_adra(0),
      ADDRA(4) => NLW_ram_ADDRA_4_UNCONNECTED,
      ADDRA(3) => NLW_ram_ADDRA_3_UNCONNECTED,
      ADDRA(2) => NLW_ram_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_ram_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_ram_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_ram_ADDRB_14_UNCONNECTED,
      ADDRB(13) => dma0_ctrl(6),
      ADDRB(12) => dma0_ctrl(6),
      ADDRB(11) => reg_ext_fifo_adr(6),
      ADDRB(10) => reg_ext_fifo_adr(5),
      ADDRB(9) => reg_ext_fifo_adr(4),
      ADDRB(8) => reg_ext_fifo_adr(3),
      ADDRB(7) => reg_ext_fifo_adr(2),
      ADDRB(6) => reg_ext_fifo_adr(1),
      ADDRB(5) => reg_ext_fifo_adr(0),
      ADDRB(4) => NLW_ram_ADDRB_4_UNCONNECTED,
      ADDRB(3) => NLW_ram_ADDRB_3_UNCONNECTED,
      ADDRB(2) => NLW_ram_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_ram_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_ram_ADDRB_0_UNCONNECTED,
      DIA(31) => dma0_ctrl(6),
      DIA(30) => dma0_ctrl(6),
      DIA(29) => dma0_ctrl(6),
      DIA(28) => dma0_ctrl(6),
      DIA(27) => dma0_ctrl(6),
      DIA(26) => dma0_ctrl(6),
      DIA(25) => dma0_ctrl(6),
      DIA(24) => dma0_ctrl(6),
      DIA(23) => dma0_ctrl(6),
      DIA(22) => dma0_ctrl(6),
      DIA(21) => dma0_ctrl(6),
      DIA(20) => dma0_ctrl(6),
      DIA(19) => dma0_ctrl(6),
      DIA(18) => dma0_ctrl(6),
      DIA(17) => dma0_ctrl(6),
      DIA(16) => dma0_ctrl(6),
      DIA(15) => dma0_ctrl(6),
      DIA(14) => dma0_ctrl(6),
      DIA(13) => dma0_ctrl(6),
      DIA(12) => dma0_ctrl(6),
      DIA(11) => dma0_ctrl(6),
      DIA(10) => dma0_ctrl(6),
      DIA(9) => dma0_ctrl(6),
      DIA(8) => dma0_ctrl(6),
      DIA(7) => ram_di_a_7_Q,
      DIA(6) => ram_di_a_6_Q,
      DIA(5) => ram_di_a_5_Q,
      DIA(4) => NlwRenamedSig_OI_test(0),
      DIA(3) => ram_di_a_3_Q,
      DIA(2) => ram_di_a_2_Q,
      DIA(1) => ram_di_a_1_Q,
      DIA(0) => ram_di_a_0_Q,
      DIB(31) => reg_ext_fifo_data(31),
      DIB(30) => reg_ext_fifo_data(30),
      DIB(29) => reg_ext_fifo_data(29),
      DIB(28) => reg_ext_fifo_data(28),
      DIB(27) => reg_ext_fifo_data(27),
      DIB(26) => reg_ext_fifo_data(26),
      DIB(25) => reg_ext_fifo_data(25),
      DIB(24) => reg_ext_fifo_data(24),
      DIB(23) => reg_ext_fifo_data(23),
      DIB(22) => reg_ext_fifo_data(22),
      DIB(21) => reg_ext_fifo_data(21),
      DIB(20) => reg_ext_fifo_data(20),
      DIB(19) => reg_ext_fifo_data(19),
      DIB(18) => reg_ext_fifo_data(18),
      DIB(17) => reg_ext_fifo_data(17),
      DIB(16) => reg_ext_fifo_data(16),
      DIB(15) => reg_ext_fifo_data(15),
      DIB(14) => reg_ext_fifo_data(14),
      DIB(13) => reg_ext_fifo_data(13),
      DIB(12) => reg_ext_fifo_data(12),
      DIB(11) => reg_ext_fifo_data(11),
      DIB(10) => reg_ext_fifo_data(10),
      DIB(9) => reg_ext_fifo_data(9),
      DIB(8) => reg_ext_fifo_data(8),
      DIB(7) => reg_ext_fifo_data(7),
      DIB(6) => reg_ext_fifo_data(6),
      DIB(5) => reg_ext_fifo_data(5),
      DIB(4) => reg_ext_fifo_data(4),
      DIB(3) => reg_ext_fifo_data(3),
      DIB(2) => reg_ext_fifo_data(2),
      DIB(1) => reg_ext_fifo_data(1),
      DIB(0) => reg_ext_fifo_data(0),
      DIPA(3) => dma0_ctrl(6),
      DIPA(2) => dma0_ctrl(6),
      DIPA(1) => dma0_ctrl(6),
      DIPA(0) => dma0_ctrl(6),
      DIPB(3) => dma0_ctrl(6),
      DIPB(2) => dma0_ctrl(6),
      DIPB(1) => dma0_ctrl(6),
      DIPB(0) => dma0_ctrl(6),
      WEA(3) => ram_we_a,
      WEA(2) => ram_we_a,
      WEA(1) => ram_we_a,
      WEA(0) => ram_we_a,
      WEB(3) => reg_ext_fifo_data_we,
      WEB(2) => reg_ext_fifo_data_we,
      WEB(1) => reg_ext_fifo_data_we,
      WEB(0) => reg_ext_fifo_data_we,
      DOA(31) => ram_do_a(31),
      DOA(30) => ram_do_a(30),
      DOA(29) => ram_do_a(29),
      DOA(28) => ram_do_a(28),
      DOA(27) => ram_do_a(27),
      DOA(26) => ram_do_a(26),
      DOA(25) => ram_do_a(25),
      DOA(24) => ram_do_a(24),
      DOA(23) => ram_do_a(23),
      DOA(22) => ram_do_a(22),
      DOA(21) => ram_do_a(21),
      DOA(20) => ram_do_a(20),
      DOA(19) => ram_do_a(19),
      DOA(18) => ram_do_a(18),
      DOA(17) => ram_do_a(17),
      DOA(16) => ram_do_a(16),
      DOA(15) => ram_do_a(15),
      DOA(14) => ram_do_a(14),
      DOA(13) => ram_do_a(13),
      DOA(12) => ram_do_a(12),
      DOA(11) => ram_do_a(11),
      DOA(10) => ram_do_a(10),
      DOA(9) => ram_do_a(9),
      DOA(8) => ram_do_a(8),
      DOA(7) => ram_do_a(7),
      DOA(6) => ram_do_a(6),
      DOA(5) => ram_do_a(5),
      DOA(4) => ram_do_a(4),
      DOA(3) => ram_do_a(3),
      DOA(2) => ram_do_a(2),
      DOA(1) => ram_do_a(1),
      DOA(0) => ram_do_a(0),
      DOB(31) => reg_ext_fifo_back_data(31),
      DOB(30) => reg_ext_fifo_back_data(30),
      DOB(29) => reg_ext_fifo_back_data(29),
      DOB(28) => reg_ext_fifo_back_data(28),
      DOB(27) => reg_ext_fifo_back_data(27),
      DOB(26) => reg_ext_fifo_back_data(26),
      DOB(25) => reg_ext_fifo_back_data(25),
      DOB(24) => reg_ext_fifo_back_data(24),
      DOB(23) => reg_ext_fifo_back_data(23),
      DOB(22) => reg_ext_fifo_back_data(22),
      DOB(21) => reg_ext_fifo_back_data(21),
      DOB(20) => reg_ext_fifo_back_data(20),
      DOB(19) => reg_ext_fifo_back_data(19),
      DOB(18) => reg_ext_fifo_back_data(18),
      DOB(17) => reg_ext_fifo_back_data(17),
      DOB(16) => reg_ext_fifo_back_data(16),
      DOB(15) => ram_do_b(15),
      DOB(14) => ram_do_b(14),
      DOB(13) => ram_do_b(13),
      DOB(12) => ram_do_b(12),
      DOB(11) => ram_do_b(11),
      DOB(10) => ram_do_b(10),
      DOB(9) => ram_do_b(9),
      DOB(8) => ram_do_b(8),
      DOB(7) => ram_do_b(7),
      DOB(6) => ram_do_b(6),
      DOB(5) => ram_do_b(5),
      DOB(4) => ram_do_b(4),
      DOB(3) => ram_do_b(3),
      DOB(2) => ram_do_b(2),
      DOB(1) => ram_do_b(1),
      DOB(0) => ram_do_b(0),
      DOPA(3) => NLW_ram_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_ram_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_ram_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_ram_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_ram_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_ram_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_ram_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_ram_DOPB_0_UNCONNECTED
    );
  main : ctrl_main
    port map (
      ram_we => ram_we_a,
      clk => clk,
      dma1_transfer_rdy => dma1_transfer_rdy,
      dsc_change_adr => NlwRenamedSig_OI_test(7),
      dsc_load_en => NlwRenamedSig_OI_test(6),
      reset => reset_13420,
      loc_adr_we => loc_adr_we,
      ram_change => ram_change,
      dsc_correct => NlwRenamedSig_OI_test(4),
      dma0_transfer_rdy => NlwRenamedSig_OI_test(1),
      dma1_eot_clr => dma1_eot_clr_13007,
      dma0_eot_clr => dma0_eot_clr_13005,
      pci_adr_we => pci_adr_we,
      dsc_change_mode => dsc_change_mode,
      dma_change_adr => dma_change_adr,
      dma_chn => NlwRenamedSig_OI_test(5),
      pci_adr_h_we => pci_adr_h_we,
      ram_adr(8) => ram_adra(8),
      ram_adr(7) => ram_adra(7),
      ram_adr(6) => ram_adra(6),
      ram_adr(5) => ram_adra(5),
      ram_adr(4) => ram_adra(4),
      ram_adr(3) => ram_adra(3),
      ram_adr(2) => ram_adra(2),
      ram_adr(1) => ram_adra(1),
      ram_adr(0) => ram_adra(0),
      ram_do(7) => ram_di_a_7_Q,
      ram_do(6) => ram_di_a_6_Q,
      ram_do(5) => ram_di_a_5_Q,
      ram_do(4) => NlwRenamedSig_OI_test(0),
      ram_do(3) => ram_di_a_3_Q,
      ram_do(2) => ram_di_a_2_Q,
      ram_do(1) => ram_di_a_1_Q,
      ram_do(0) => ram_di_a_0_Q,
      reg_dma1_status(15) => NLW_main_reg_dma1_status_15_UNCONNECTED,
      reg_dma1_status(14) => NLW_main_reg_dma1_status_14_UNCONNECTED,
      reg_dma1_status(13) => NLW_main_reg_dma1_status_13_UNCONNECTED,
      reg_dma1_status(12) => NLW_main_reg_dma1_status_12_UNCONNECTED,
      reg_dma1_status(11) => NLW_main_reg_dma1_status_11_UNCONNECTED,
      reg_dma1_status(10) => NLW_main_reg_dma1_status_10_UNCONNECTED,
      reg_dma1_status(9) => NLW_main_reg_dma1_status_9_UNCONNECTED,
      reg_dma1_status(8) => reg_dma1_status_8_Q,
      reg_dma1_status(7) => reg_dma1_status_7_Q,
      reg_dma1_status(6) => reg_dma1_status_6_Q,
      reg_dma1_status(5) => reg_dma1_status_5_Q,
      reg_dma1_status(4) => reg_dma1_status_4_Q,
      reg_dma1_status(3) => NLW_main_reg_dma1_status_3_UNCONNECTED,
      reg_dma1_status(2) => NLW_main_reg_dma1_status_2_UNCONNECTED,
      reg_dma1_status(1) => NLW_main_reg_dma1_status_1_UNCONNECTED,
      reg_dma1_status(0) => reg_dma1_status_0_Q,
      reg_dma0_status(15) => NLW_main_reg_dma0_status_15_UNCONNECTED,
      reg_dma0_status(14) => NLW_main_reg_dma0_status_14_UNCONNECTED,
      reg_dma0_status(13) => NLW_main_reg_dma0_status_13_UNCONNECTED,
      reg_dma0_status(12) => NLW_main_reg_dma0_status_12_UNCONNECTED,
      reg_dma0_status(11) => NLW_main_reg_dma0_status_11_UNCONNECTED,
      reg_dma0_status(10) => NLW_main_reg_dma0_status_10_UNCONNECTED,
      reg_dma0_status(9) => NLW_main_reg_dma0_status_9_UNCONNECTED,
      reg_dma0_status(8) => reg_dma0_status_8_Q,
      reg_dma0_status(7) => reg_dma0_status_7_Q,
      reg_dma0_status(6) => reg_dma0_status_6_Q,
      reg_dma0_status(5) => reg_dma0_status_5_Q,
      reg_dma0_status(4) => reg_dma0_status_4_Q,
      reg_dma0_status(3) => NLW_main_reg_dma0_status_3_UNCONNECTED,
      reg_dma0_status(2) => NLW_main_reg_dma0_status_2_UNCONNECTED,
      reg_dma0_status(1) => NLW_main_reg_dma0_status_1_UNCONNECTED,
      reg_dma0_status(0) => reg_dma0_status_0_Q,
      dma_reg0(2) => dma_reg0(2),
      dma_reg0(1) => dma_reg0(1),
      dma_reg0(0) => dma_reg0(0),
      dma_status(2) => dma_cmd_status(2),
      dma_status(1) => NlwRenamedSig_OI_test(3),
      dma_status(0) => NlwRenamedSig_OI_test(2),
      dma0_ctrl(7) => dma0_ctrl(6),
      dma0_ctrl(6) => dma0_ctrl(6),
      dma0_ctrl(5) => reg_dma0_mode_5_Q,
      dma0_ctrl(4) => reg_dma0_ctrl_4_Q,
      dma0_ctrl(3) => reg_dma0_ctrl_3_Q,
      dma0_ctrl(2) => reg_dma0_mode_2_Q,
      dma0_ctrl(1) => reg_dma0_mode_1_Q,
      dma0_ctrl(0) => reg_dma0_ctrl_0_Q,
      dsc_cmd(7) => dsc_cmd(7),
      dsc_cmd(6) => dsc_cmd(6),
      dsc_cmd(5) => dsc_cmd(5),
      dsc_cmd(4) => dsc_cmd(4),
      dsc_cmd(3) => dsc_cmd(3),
      dsc_cmd(2) => dsc_cmd(2),
      dsc_cmd(1) => dsc_cmd(1),
      dsc_cmd(0) => dsc_cmd(0),
      dma1_ctrl(7) => dma0_ctrl(6),
      dma1_ctrl(6) => dma0_ctrl(6),
      dma1_ctrl(5) => reg_dma1_mode_5_Q,
      dma1_ctrl(4) => reg_dma1_ctrl_4_Q,
      dma1_ctrl(3) => reg_dma1_ctrl_3_Q,
      dma1_ctrl(2) => reg_dma1_mode_2_Q,
      dma1_ctrl(1) => reg_dma1_mode_1_Q,
      dma1_ctrl(0) => reg_dma1_ctrl_0_Q
    );
  dsc : ctrl_ext_descriptor
    port map (
      clk => clk,
      dsc_change_adr => NlwRenamedSig_OI_test(7),
      dsc_load_en => NlwRenamedSig_OI_test(6),
      reset => reset_13420,
      dsc_correct => NlwRenamedSig_OI_test(4),
      ram0_wr => rx_ext_fifo_data_we,
      pci_adr_we => pci_adr_we,
      dsc_change_mode => dsc_change_mode,
      dma_chn => NlwRenamedSig_OI_test(5),
      pci_adr_h_we => pci_adr_h_we,
      dsc_adr(23) => dsc_adr(23),
      dsc_adr(22) => dsc_adr(22),
      dsc_adr(21) => dsc_adr(21),
      dsc_adr(20) => dsc_adr(20),
      dsc_adr(19) => dsc_adr(19),
      dsc_adr(18) => dsc_adr(18),
      dsc_adr(17) => dsc_adr(17),
      dsc_adr(16) => dsc_adr(16),
      dsc_adr(15) => dsc_adr(15),
      dsc_adr(14) => dsc_adr(14),
      dsc_adr(13) => dsc_adr(13),
      dsc_adr(12) => dsc_adr(12),
      dsc_adr(11) => dsc_adr(11),
      dsc_adr(10) => dsc_adr(10),
      dsc_adr(9) => dsc_adr(9),
      dsc_adr(8) => dsc_adr(8),
      dsc_adr(7) => dsc_adr(7),
      dsc_adr(6) => dsc_adr(6),
      dsc_adr(5) => dsc_adr(5),
      dsc_adr(4) => dsc_adr(4),
      dsc_adr(3) => dsc_adr(3),
      dsc_adr(2) => dsc_adr(2),
      dsc_adr(1) => dsc_adr(1),
      dsc_adr(0) => dsc_adr(0),
      dsc_cmd(7) => dsc_cmd(7),
      dsc_cmd(6) => dsc_cmd(6),
      dsc_cmd(5) => dsc_cmd(5),
      dsc_cmd(4) => dsc_cmd(4),
      dsc_cmd(3) => dsc_cmd(3),
      dsc_cmd(2) => dsc_cmd(2),
      dsc_cmd(1) => dsc_cmd(1),
      dsc_cmd(0) => dsc_cmd(0),
      dsc_adr_h(7) => dsc_adr_h(7),
      dsc_adr_h(6) => dsc_adr_h(6),
      dsc_adr_h(5) => dsc_adr_h(5),
      dsc_adr_h(4) => dsc_adr_h(4),
      dsc_adr_h(3) => dsc_adr_h(3),
      dsc_adr_h(2) => dsc_adr_h(2),
      dsc_adr_h(1) => dsc_adr_h(1),
      dsc_adr_h(0) => dsc_adr_h(0),
      dsc_size(23) => dsc_size(23),
      dsc_size(22) => dsc_size(22),
      dsc_size(21) => dsc_size(21),
      dsc_size(20) => dsc_size(20),
      dsc_size(19) => dsc_size(19),
      dsc_size(18) => dsc_size(18),
      dsc_size(17) => dsc_size(17),
      dsc_size(16) => dsc_size(16),
      dsc_size(15) => dsc_size(15),
      dsc_size(14) => dsc_size(14),
      dsc_size(13) => dsc_size(13),
      dsc_size(12) => dsc_size(12),
      dsc_size(11) => dsc_size(11),
      dsc_size(10) => dsc_size(10),
      dsc_size(9) => dsc_size(9),
      dsc_size(8) => dsc_size(8),
      dsc_size(7) => dsc_size(7),
      dsc_size(6) => dsc_size(6),
      dsc_size(5) => dsc_size(5),
      dsc_size(4) => dsc_size(4),
      dsc_size(3) => dsc_size(3),
      dsc_size(2) => dsc_size(2),
      dsc_size(1) => dsc_size(1),
      dsc_size(0) => dsc_size(0),
      test(3) => NLW_dsc_test_3_UNCONNECTED,
      test(2) => NLW_dsc_test_2_UNCONNECTED,
      test(1) => NLW_dsc_test_1_UNCONNECTED,
      test(0) => NLW_dsc_test_0_UNCONNECTED,
      data_in(31) => ram_do_a(31),
      data_in(30) => ram_do_a(30),
      data_in(29) => ram_do_a(29),
      data_in(28) => ram_do_a(28),
      data_in(27) => ram_do_a(27),
      data_in(26) => ram_do_a(26),
      data_in(25) => ram_do_a(25),
      data_in(24) => ram_do_a(24),
      data_in(23) => ram_do_a(23),
      data_in(22) => ram_do_a(22),
      data_in(21) => ram_do_a(21),
      data_in(20) => ram_do_a(20),
      data_in(19) => ram_do_a(19),
      data_in(18) => ram_do_a(18),
      data_in(17) => ram_do_a(17),
      data_in(16) => ram_do_a(16),
      data_in(15) => ram_do_a(15),
      data_in(14) => ram_do_a(14),
      data_in(13) => ram_do_a(13),
      data_in(12) => ram_do_a(12),
      data_in(11) => ram_do_a(11),
      data_in(10) => ram_do_a(10),
      data_in(9) => ram_do_a(9),
      data_in(8) => ram_do_a(8),
      data_in(7) => ram_do_a(7),
      data_in(6) => ram_do_a(6),
      data_in(5) => ram_do_a(5),
      data_in(4) => ram_do_a(4),
      data_in(3) => ram_do_a(3),
      data_in(2) => ram_do_a(2),
      data_in(1) => ram_do_a(1),
      data_in(0) => ram_do_a(0),
      dma_wrdata(63) => rx_ext_fifo_data(63),
      dma_wrdata(62) => rx_ext_fifo_data(62),
      dma_wrdata(61) => rx_ext_fifo_data(61),
      dma_wrdata(60) => rx_ext_fifo_data(60),
      dma_wrdata(59) => rx_ext_fifo_data(59),
      dma_wrdata(58) => rx_ext_fifo_data(58),
      dma_wrdata(57) => rx_ext_fifo_data(57),
      dma_wrdata(56) => rx_ext_fifo_data(56),
      dma_wrdata(55) => rx_ext_fifo_data(55),
      dma_wrdata(54) => rx_ext_fifo_data(54),
      dma_wrdata(53) => rx_ext_fifo_data(53),
      dma_wrdata(52) => rx_ext_fifo_data(52),
      dma_wrdata(51) => rx_ext_fifo_data(51),
      dma_wrdata(50) => rx_ext_fifo_data(50),
      dma_wrdata(49) => rx_ext_fifo_data(49),
      dma_wrdata(48) => rx_ext_fifo_data(48),
      dma_wrdata(47) => rx_ext_fifo_data(47),
      dma_wrdata(46) => rx_ext_fifo_data(46),
      dma_wrdata(45) => rx_ext_fifo_data(45),
      dma_wrdata(44) => rx_ext_fifo_data(44),
      dma_wrdata(43) => rx_ext_fifo_data(43),
      dma_wrdata(42) => rx_ext_fifo_data(42),
      dma_wrdata(41) => rx_ext_fifo_data(41),
      dma_wrdata(40) => rx_ext_fifo_data(40),
      dma_wrdata(39) => rx_ext_fifo_data(39),
      dma_wrdata(38) => rx_ext_fifo_data(38),
      dma_wrdata(37) => rx_ext_fifo_data(37),
      dma_wrdata(36) => rx_ext_fifo_data(36),
      dma_wrdata(35) => rx_ext_fifo_data(35),
      dma_wrdata(34) => rx_ext_fifo_data(34),
      dma_wrdata(33) => rx_ext_fifo_data(33),
      dma_wrdata(32) => rx_ext_fifo_data(32),
      dma_wrdata(31) => rx_ext_fifo_data(31),
      dma_wrdata(30) => rx_ext_fifo_data(30),
      dma_wrdata(29) => rx_ext_fifo_data(29),
      dma_wrdata(28) => rx_ext_fifo_data(28),
      dma_wrdata(27) => rx_ext_fifo_data(27),
      dma_wrdata(26) => rx_ext_fifo_data(26),
      dma_wrdata(25) => rx_ext_fifo_data(25),
      dma_wrdata(24) => rx_ext_fifo_data(24),
      dma_wrdata(23) => rx_ext_fifo_data(23),
      dma_wrdata(22) => rx_ext_fifo_data(22),
      dma_wrdata(21) => rx_ext_fifo_data(21),
      dma_wrdata(20) => rx_ext_fifo_data(20),
      dma_wrdata(19) => rx_ext_fifo_data(19),
      dma_wrdata(18) => rx_ext_fifo_data(18),
      dma_wrdata(17) => rx_ext_fifo_data(17),
      dma_wrdata(16) => rx_ext_fifo_data(16),
      dma_wrdata(15) => rx_ext_fifo_data(15),
      dma_wrdata(14) => rx_ext_fifo_data(14),
      dma_wrdata(13) => rx_ext_fifo_data(13),
      dma_wrdata(12) => rx_ext_fifo_data(12),
      dma_wrdata(11) => rx_ext_fifo_data(11),
      dma_wrdata(10) => rx_ext_fifo_data(10),
      dma_wrdata(9) => rx_ext_fifo_data(9),
      dma_wrdata(8) => rx_ext_fifo_data(8),
      dma_wrdata(7) => rx_ext_fifo_data(7),
      dma_wrdata(6) => rx_ext_fifo_data(6),
      dma_wrdata(5) => rx_ext_fifo_data(5),
      dma_wrdata(4) => rx_ext_fifo_data(4),
      dma_wrdata(3) => rx_ext_fifo_data(3),
      dma_wrdata(2) => rx_ext_fifo_data(2),
      dma_wrdata(1) => rx_ext_fifo_data(1),
      dma_wrdata(0) => rx_ext_fifo_data(0),
      dma_wraddr(11) => rx_ext_fifo_adr(8),
      dma_wraddr(10) => rx_ext_fifo_adr(7),
      dma_wraddr(9) => rx_ext_fifo_adr(6),
      dma_wraddr(8) => rx_ext_fifo_adr(5),
      dma_wraddr(7) => rx_ext_fifo_adr(4),
      dma_wraddr(6) => rx_ext_fifo_adr(3),
      dma_wraddr(5) => rx_ext_fifo_adr(2),
      dma_wraddr(4) => rx_ext_fifo_adr(1),
      dma_wraddr(3) => rx_ext_fifo_adr(0),
      dma_wraddr(2) => dma0_ctrl(6),
      dma_wraddr(1) => dma0_ctrl(6),
      dma_wraddr(0) => dma0_ctrl(6)
    );
  cmd : ctrl_dma_ext_cmd
    port map (
      clk => clk,
      tx_rd_size => tx_ext_fifo_back_rd_size,
      tx_req_rd => tx_ext_fifo_back_req_rd,
      tx_req_wr => tx_ext_fifo_back_req_wr,
      tx_ext_fifo_complete_error => tx_ext_fifo_complete_error,
      rstp => rstp,
      rx_ext_fifo_data_we => rx_ext_fifo_data_we,
      dma_change_adr => dma_change_adr,
      tx_ext_fifo_complete_ok => tx_ext_fifo_complete_ok,
      dma_chn => NlwRenamedSig_OI_test(5),
      dma_cmd_status(2) => dma_cmd_status(2),
      dma_cmd_status(1) => NlwRenamedSig_OI_test(3),
      dma_cmd_status(0) => NlwRenamedSig_OI_test(2),
      test(3) => NLW_cmd_test_3_UNCONNECTED,
      test(2) => NLW_cmd_test_2_UNCONNECTED,
      test(1) => NLW_cmd_test_1_UNCONNECTED,
      test(0) => NLW_cmd_test_0_UNCONNECTED,
      tx_pci_adr(39) => tx_ext_fifo_back_pci_adr(39),
      tx_pci_adr(38) => tx_ext_fifo_back_pci_adr(38),
      tx_pci_adr(37) => tx_ext_fifo_back_pci_adr(37),
      tx_pci_adr(36) => tx_ext_fifo_back_pci_adr(36),
      tx_pci_adr(35) => tx_ext_fifo_back_pci_adr(35),
      tx_pci_adr(34) => tx_ext_fifo_back_pci_adr(34),
      tx_pci_adr(33) => tx_ext_fifo_back_pci_adr(33),
      tx_pci_adr(32) => tx_ext_fifo_back_pci_adr(32),
      tx_pci_adr(31) => tx_ext_fifo_back_pci_adr(31),
      tx_pci_adr(30) => tx_ext_fifo_back_pci_adr(30),
      tx_pci_adr(29) => tx_ext_fifo_back_pci_adr(29),
      tx_pci_adr(28) => tx_ext_fifo_back_pci_adr(28),
      tx_pci_adr(27) => tx_ext_fifo_back_pci_adr(27),
      tx_pci_adr(26) => tx_ext_fifo_back_pci_adr(26),
      tx_pci_adr(25) => tx_ext_fifo_back_pci_adr(25),
      tx_pci_adr(24) => tx_ext_fifo_back_pci_adr(24),
      tx_pci_adr(23) => tx_ext_fifo_back_pci_adr(23),
      tx_pci_adr(22) => tx_ext_fifo_back_pci_adr(22),
      tx_pci_adr(21) => tx_ext_fifo_back_pci_adr(21),
      tx_pci_adr(20) => tx_ext_fifo_back_pci_adr(20),
      tx_pci_adr(19) => tx_ext_fifo_back_pci_adr(19),
      tx_pci_adr(18) => tx_ext_fifo_back_pci_adr(18),
      tx_pci_adr(17) => tx_ext_fifo_back_pci_adr(17),
      tx_pci_adr(16) => tx_ext_fifo_back_pci_adr(16),
      tx_pci_adr(15) => tx_ext_fifo_back_pci_adr(15),
      tx_pci_adr(14) => tx_ext_fifo_back_pci_adr(14),
      tx_pci_adr(13) => tx_ext_fifo_back_pci_adr(13),
      tx_pci_adr(12) => tx_ext_fifo_back_pci_adr(12),
      tx_pci_adr(11) => tx_ext_fifo_back_pci_adr(11),
      tx_pci_adr(10) => tx_ext_fifo_back_pci_adr(10),
      tx_pci_adr(9) => tx_ext_fifo_back_pci_adr(9),
      tx_pci_adr(8) => tx_ext_fifo_back_pci_adr(8),
      dsc_adr(23) => dsc_adr(23),
      dsc_adr(22) => dsc_adr(22),
      dsc_adr(21) => dsc_adr(21),
      dsc_adr(20) => dsc_adr(20),
      dsc_adr(19) => dsc_adr(19),
      dsc_adr(18) => dsc_adr(18),
      dsc_adr(17) => dsc_adr(17),
      dsc_adr(16) => dsc_adr(16),
      dsc_adr(15) => dsc_adr(15),
      dsc_adr(14) => dsc_adr(14),
      dsc_adr(13) => dsc_adr(13),
      dsc_adr(12) => dsc_adr(12),
      dsc_adr(11) => dsc_adr(11),
      dsc_adr(10) => dsc_adr(10),
      dsc_adr(9) => dsc_adr(9),
      dsc_adr(8) => dsc_adr(8),
      dsc_adr(7) => dsc_adr(7),
      dsc_adr(6) => dsc_adr(6),
      dsc_adr(5) => dsc_adr(5),
      dsc_adr(4) => dsc_adr(4),
      dsc_adr(3) => dsc_adr(3),
      dsc_adr(2) => dsc_adr(2),
      dsc_adr(1) => dsc_adr(1),
      dsc_adr(0) => dsc_adr(0),
      rx_ext_fifo_data(63) => rx_ext_fifo_data(63),
      rx_ext_fifo_data(62) => rx_ext_fifo_data(62),
      rx_ext_fifo_data(61) => rx_ext_fifo_data(61),
      rx_ext_fifo_data(60) => rx_ext_fifo_data(60),
      rx_ext_fifo_data(59) => rx_ext_fifo_data(59),
      rx_ext_fifo_data(58) => rx_ext_fifo_data(58),
      rx_ext_fifo_data(57) => rx_ext_fifo_data(57),
      rx_ext_fifo_data(56) => rx_ext_fifo_data(56),
      rx_ext_fifo_data(55) => rx_ext_fifo_data(55),
      rx_ext_fifo_data(54) => rx_ext_fifo_data(54),
      rx_ext_fifo_data(53) => rx_ext_fifo_data(53),
      rx_ext_fifo_data(52) => rx_ext_fifo_data(52),
      rx_ext_fifo_data(51) => rx_ext_fifo_data(51),
      rx_ext_fifo_data(50) => rx_ext_fifo_data(50),
      rx_ext_fifo_data(49) => rx_ext_fifo_data(49),
      rx_ext_fifo_data(48) => rx_ext_fifo_data(48),
      rx_ext_fifo_data(47) => rx_ext_fifo_data(47),
      rx_ext_fifo_data(46) => rx_ext_fifo_data(46),
      rx_ext_fifo_data(45) => rx_ext_fifo_data(45),
      rx_ext_fifo_data(44) => rx_ext_fifo_data(44),
      rx_ext_fifo_data(43) => rx_ext_fifo_data(43),
      rx_ext_fifo_data(42) => rx_ext_fifo_data(42),
      rx_ext_fifo_data(41) => rx_ext_fifo_data(41),
      rx_ext_fifo_data(40) => rx_ext_fifo_data(40),
      rx_ext_fifo_data(39) => rx_ext_fifo_data(39),
      rx_ext_fifo_data(38) => rx_ext_fifo_data(38),
      rx_ext_fifo_data(37) => rx_ext_fifo_data(37),
      rx_ext_fifo_data(36) => rx_ext_fifo_data(36),
      rx_ext_fifo_data(35) => rx_ext_fifo_data(35),
      rx_ext_fifo_data(34) => rx_ext_fifo_data(34),
      rx_ext_fifo_data(33) => rx_ext_fifo_data(33),
      rx_ext_fifo_data(32) => rx_ext_fifo_data(32),
      rx_ext_fifo_data(31) => rx_ext_fifo_data(31),
      rx_ext_fifo_data(30) => rx_ext_fifo_data(30),
      rx_ext_fifo_data(29) => rx_ext_fifo_data(29),
      rx_ext_fifo_data(28) => rx_ext_fifo_data(28),
      rx_ext_fifo_data(27) => rx_ext_fifo_data(27),
      rx_ext_fifo_data(26) => rx_ext_fifo_data(26),
      rx_ext_fifo_data(25) => rx_ext_fifo_data(25),
      rx_ext_fifo_data(24) => rx_ext_fifo_data(24),
      rx_ext_fifo_data(23) => rx_ext_fifo_data(23),
      rx_ext_fifo_data(22) => rx_ext_fifo_data(22),
      rx_ext_fifo_data(21) => rx_ext_fifo_data(21),
      rx_ext_fifo_data(20) => rx_ext_fifo_data(20),
      rx_ext_fifo_data(19) => rx_ext_fifo_data(19),
      rx_ext_fifo_data(18) => rx_ext_fifo_data(18),
      rx_ext_fifo_data(17) => rx_ext_fifo_data(17),
      rx_ext_fifo_data(16) => rx_ext_fifo_data(16),
      rx_ext_fifo_data(15) => rx_ext_fifo_data(15),
      rx_ext_fifo_data(14) => rx_ext_fifo_data(14),
      rx_ext_fifo_data(13) => rx_ext_fifo_data(13),
      rx_ext_fifo_data(12) => rx_ext_fifo_data(12),
      rx_ext_fifo_data(11) => rx_ext_fifo_data(11),
      rx_ext_fifo_data(10) => rx_ext_fifo_data(10),
      rx_ext_fifo_data(9) => rx_ext_fifo_data(9),
      rx_ext_fifo_data(8) => rx_ext_fifo_data(8),
      rx_ext_fifo_data(7) => rx_ext_fifo_data(7),
      rx_ext_fifo_data(6) => rx_ext_fifo_data(6),
      rx_ext_fifo_data(5) => rx_ext_fifo_data(5),
      rx_ext_fifo_data(4) => rx_ext_fifo_data(4),
      rx_ext_fifo_data(3) => rx_ext_fifo_data(3),
      rx_ext_fifo_data(2) => rx_ext_fifo_data(2),
      rx_ext_fifo_data(1) => rx_ext_fifo_data(1),
      rx_ext_fifo_data(0) => rx_ext_fifo_data(0),
      tx_ext_fifo_adr(8) => tx_ext_fifo_adr(8),
      tx_ext_fifo_adr(7) => tx_ext_fifo_adr(7),
      tx_ext_fifo_adr(6) => tx_ext_fifo_adr(6),
      tx_ext_fifo_adr(5) => tx_ext_fifo_adr(5),
      tx_ext_fifo_adr(4) => tx_ext_fifo_adr(4),
      tx_ext_fifo_adr(3) => tx_ext_fifo_adr(3),
      tx_ext_fifo_adr(2) => tx_ext_fifo_adr(2),
      tx_ext_fifo_adr(1) => tx_ext_fifo_adr(1),
      tx_ext_fifo_adr(0) => tx_ext_fifo_adr(0),
      dsc_adr_h(7) => dsc_adr_h(7),
      dsc_adr_h(6) => dsc_adr_h(6),
      dsc_adr_h(5) => dsc_adr_h(5),
      dsc_adr_h(4) => dsc_adr_h(4),
      dsc_adr_h(3) => dsc_adr_h(3),
      dsc_adr_h(2) => dsc_adr_h(2),
      dsc_adr_h(1) => dsc_adr_h(1),
      dsc_adr_h(0) => dsc_adr_h(0),
      rx_ext_fifo_adr(8) => rx_ext_fifo_adr(8),
      rx_ext_fifo_adr(7) => rx_ext_fifo_adr(7),
      rx_ext_fifo_adr(6) => rx_ext_fifo_adr(6),
      rx_ext_fifo_adr(5) => rx_ext_fifo_adr(5),
      rx_ext_fifo_adr(4) => rx_ext_fifo_adr(4),
      rx_ext_fifo_adr(3) => rx_ext_fifo_adr(3),
      rx_ext_fifo_adr(2) => rx_ext_fifo_adr(2),
      rx_ext_fifo_adr(1) => rx_ext_fifo_adr(1),
      rx_ext_fifo_adr(0) => rx_ext_fifo_adr(0),
      dsc_size(23) => dsc_size(23),
      dsc_size(22) => dsc_size(22),
      dsc_size(21) => dsc_size(21),
      dsc_size(20) => dsc_size(20),
      dsc_size(19) => dsc_size(19),
      dsc_size(18) => dsc_size(18),
      dsc_size(17) => dsc_size(17),
      dsc_size(16) => dsc_size(16),
      dsc_size(15) => dsc_size(15),
      dsc_size(14) => dsc_size(14),
      dsc_size(13) => dsc_size(13),
      dsc_size(12) => dsc_size(12),
      dsc_size(11) => dsc_size(11),
      dsc_size(10) => dsc_size(10),
      dsc_size(9) => dsc_size(9),
      dsc_size(8) => dsc_size(8),
      dsc_size(7) => dsc_size(7),
      dsc_size(6) => dsc_size(6),
      dsc_size(5) => dsc_size(5),
      dsc_size(4) => dsc_size(4),
      dsc_size(3) => dsc_size(3),
      dsc_size(2) => dsc_size(2),
      dsc_size(1) => dsc_size(1),
      dsc_size(0) => dsc_size(0),
      dma_reg0(2) => dma_reg0(2),
      dma_reg0(1) => dma_reg0(1),
      dma_reg0(0) => dma_reg0(0)
    );
  ram_data : ctrl_ext_ram
    port map (
      clk => clk,
      ext_fifo_disp_back_data_we => ext_fifo_disp_back_data_we,
      dma1_transfer_rdy => dma1_transfer_rdy,
      aclk => aclk,
      reset => reset_13420,
      loc_adr_we => loc_adr_we,
      ext_fifo_disp_back_irq => ext_fifo_disp_back_irq,
      ram_change => ram_change,
      dma_wr_en => dsc_size(0),
      dma0_transfer_rdy => NlwRenamedSig_OI_test(1),
      dma_wr => ram1_wr,
      ext_fifo_disp_data_we => ext_fifo_disp_data_we,
      ext_fifo_disp_request_rd => ext_fifo_disp_request_rd,
      ext_fifo_disp_back_allow_wr => ext_fifo_disp_back_allow_wr,
      dma_chn => NlwRenamedSig_OI_test(5),
      ext_fifo_disp_request_wr => ext_fifo_disp_request_wr,
      ext_fifo_disp_adr(31) => ext_fifo_disp_adr(31),
      ext_fifo_disp_adr(30) => ext_fifo_disp_adr(30),
      ext_fifo_disp_adr(29) => ext_fifo_disp_adr(29),
      ext_fifo_disp_adr(28) => ext_fifo_disp_adr(28),
      ext_fifo_disp_adr(27) => ext_fifo_disp_adr(27),
      ext_fifo_disp_adr(26) => ext_fifo_disp_adr(26),
      ext_fifo_disp_adr(25) => ext_fifo_disp_adr(25),
      ext_fifo_disp_adr(24) => ext_fifo_disp_adr(24),
      ext_fifo_disp_adr(23) => ext_fifo_disp_adr(23),
      ext_fifo_disp_adr(22) => ext_fifo_disp_adr(22),
      ext_fifo_disp_adr(21) => ext_fifo_disp_adr(21),
      ext_fifo_disp_adr(20) => ext_fifo_disp_adr(20),
      ext_fifo_disp_adr(19) => ext_fifo_disp_adr(19),
      ext_fifo_disp_adr(18) => ext_fifo_disp_adr(18),
      ext_fifo_disp_adr(17) => ext_fifo_disp_adr(17),
      ext_fifo_disp_adr(16) => ext_fifo_disp_adr(16),
      ext_fifo_disp_adr(15) => ext_fifo_disp_adr(15),
      ext_fifo_disp_adr(14) => ext_fifo_disp_adr(14),
      ext_fifo_disp_adr(13) => ext_fifo_disp_adr(13),
      ext_fifo_disp_adr(12) => ext_fifo_disp_adr(12),
      ext_fifo_disp_adr(11) => ext_fifo_disp_adr(11),
      ext_fifo_disp_adr(10) => ext_fifo_disp_adr(10),
      ext_fifo_disp_adr(9) => ext_fifo_disp_adr(9),
      ext_fifo_disp_adr(8) => ext_fifo_disp_adr(8),
      ext_fifo_disp_adr(7) => ext_fifo_disp_adr(7),
      ext_fifo_disp_adr(6) => ext_fifo_disp_adr(6),
      ext_fifo_disp_adr(5) => ext_fifo_disp_adr(5),
      ext_fifo_disp_adr(4) => ext_fifo_disp_adr(4),
      ext_fifo_disp_adr(3) => ext_fifo_disp_adr(3),
      ext_fifo_disp_adr(2) => ext_fifo_disp_adr(2),
      ext_fifo_disp_adr(1) => ext_fifo_disp_adr(1),
      ext_fifo_disp_adr(0) => ext_fifo_disp_adr(0),
      dma_rddata(63) => tx_ext_fifo_back_data(63),
      dma_rddata(62) => tx_ext_fifo_back_data(62),
      dma_rddata(61) => tx_ext_fifo_back_data(61),
      dma_rddata(60) => tx_ext_fifo_back_data(60),
      dma_rddata(59) => tx_ext_fifo_back_data(59),
      dma_rddata(58) => tx_ext_fifo_back_data(58),
      dma_rddata(57) => tx_ext_fifo_back_data(57),
      dma_rddata(56) => tx_ext_fifo_back_data(56),
      dma_rddata(55) => tx_ext_fifo_back_data(55),
      dma_rddata(54) => tx_ext_fifo_back_data(54),
      dma_rddata(53) => tx_ext_fifo_back_data(53),
      dma_rddata(52) => tx_ext_fifo_back_data(52),
      dma_rddata(51) => tx_ext_fifo_back_data(51),
      dma_rddata(50) => tx_ext_fifo_back_data(50),
      dma_rddata(49) => tx_ext_fifo_back_data(49),
      dma_rddata(48) => tx_ext_fifo_back_data(48),
      dma_rddata(47) => tx_ext_fifo_back_data(47),
      dma_rddata(46) => tx_ext_fifo_back_data(46),
      dma_rddata(45) => tx_ext_fifo_back_data(45),
      dma_rddata(44) => tx_ext_fifo_back_data(44),
      dma_rddata(43) => tx_ext_fifo_back_data(43),
      dma_rddata(42) => tx_ext_fifo_back_data(42),
      dma_rddata(41) => tx_ext_fifo_back_data(41),
      dma_rddata(40) => tx_ext_fifo_back_data(40),
      dma_rddata(39) => tx_ext_fifo_back_data(39),
      dma_rddata(38) => tx_ext_fifo_back_data(38),
      dma_rddata(37) => tx_ext_fifo_back_data(37),
      dma_rddata(36) => tx_ext_fifo_back_data(36),
      dma_rddata(35) => tx_ext_fifo_back_data(35),
      dma_rddata(34) => tx_ext_fifo_back_data(34),
      dma_rddata(33) => tx_ext_fifo_back_data(33),
      dma_rddata(32) => tx_ext_fifo_back_data(32),
      dma_rddata(31) => tx_ext_fifo_back_data(31),
      dma_rddata(30) => tx_ext_fifo_back_data(30),
      dma_rddata(29) => tx_ext_fifo_back_data(29),
      dma_rddata(28) => tx_ext_fifo_back_data(28),
      dma_rddata(27) => tx_ext_fifo_back_data(27),
      dma_rddata(26) => tx_ext_fifo_back_data(26),
      dma_rddata(25) => tx_ext_fifo_back_data(25),
      dma_rddata(24) => tx_ext_fifo_back_data(24),
      dma_rddata(23) => tx_ext_fifo_back_data(23),
      dma_rddata(22) => tx_ext_fifo_back_data(22),
      dma_rddata(21) => tx_ext_fifo_back_data(21),
      dma_rddata(20) => tx_ext_fifo_back_data(20),
      dma_rddata(19) => tx_ext_fifo_back_data(19),
      dma_rddata(18) => tx_ext_fifo_back_data(18),
      dma_rddata(17) => tx_ext_fifo_back_data(17),
      dma_rddata(16) => tx_ext_fifo_back_data(16),
      dma_rddata(15) => tx_ext_fifo_back_data(15),
      dma_rddata(14) => tx_ext_fifo_back_data(14),
      dma_rddata(13) => tx_ext_fifo_back_data(13),
      dma_rddata(12) => tx_ext_fifo_back_data(12),
      dma_rddata(11) => tx_ext_fifo_back_data(11),
      dma_rddata(10) => tx_ext_fifo_back_data(10),
      dma_rddata(9) => tx_ext_fifo_back_data(9),
      dma_rddata(8) => tx_ext_fifo_back_data(8),
      dma_rddata(7) => tx_ext_fifo_back_data(7),
      dma_rddata(6) => tx_ext_fifo_back_data(6),
      dma_rddata(5) => tx_ext_fifo_back_data(5),
      dma_rddata(4) => tx_ext_fifo_back_data(4),
      dma_rddata(3) => tx_ext_fifo_back_data(3),
      dma_rddata(2) => tx_ext_fifo_back_data(2),
      dma_rddata(1) => tx_ext_fifo_back_data(1),
      dma_rddata(0) => tx_ext_fifo_back_data(0),
      ext_fifo_disp_data(63) => ext_fifo_disp_data(63),
      ext_fifo_disp_data(62) => ext_fifo_disp_data(62),
      ext_fifo_disp_data(61) => ext_fifo_disp_data(61),
      ext_fifo_disp_data(60) => ext_fifo_disp_data(60),
      ext_fifo_disp_data(59) => ext_fifo_disp_data(59),
      ext_fifo_disp_data(58) => ext_fifo_disp_data(58),
      ext_fifo_disp_data(57) => ext_fifo_disp_data(57),
      ext_fifo_disp_data(56) => ext_fifo_disp_data(56),
      ext_fifo_disp_data(55) => ext_fifo_disp_data(55),
      ext_fifo_disp_data(54) => ext_fifo_disp_data(54),
      ext_fifo_disp_data(53) => ext_fifo_disp_data(53),
      ext_fifo_disp_data(52) => ext_fifo_disp_data(52),
      ext_fifo_disp_data(51) => ext_fifo_disp_data(51),
      ext_fifo_disp_data(50) => ext_fifo_disp_data(50),
      ext_fifo_disp_data(49) => ext_fifo_disp_data(49),
      ext_fifo_disp_data(48) => ext_fifo_disp_data(48),
      ext_fifo_disp_data(47) => ext_fifo_disp_data(47),
      ext_fifo_disp_data(46) => ext_fifo_disp_data(46),
      ext_fifo_disp_data(45) => ext_fifo_disp_data(45),
      ext_fifo_disp_data(44) => ext_fifo_disp_data(44),
      ext_fifo_disp_data(43) => ext_fifo_disp_data(43),
      ext_fifo_disp_data(42) => ext_fifo_disp_data(42),
      ext_fifo_disp_data(41) => ext_fifo_disp_data(41),
      ext_fifo_disp_data(40) => ext_fifo_disp_data(40),
      ext_fifo_disp_data(39) => ext_fifo_disp_data(39),
      ext_fifo_disp_data(38) => ext_fifo_disp_data(38),
      ext_fifo_disp_data(37) => ext_fifo_disp_data(37),
      ext_fifo_disp_data(36) => ext_fifo_disp_data(36),
      ext_fifo_disp_data(35) => ext_fifo_disp_data(35),
      ext_fifo_disp_data(34) => ext_fifo_disp_data(34),
      ext_fifo_disp_data(33) => ext_fifo_disp_data(33),
      ext_fifo_disp_data(32) => ext_fifo_disp_data(32),
      ext_fifo_disp_data(31) => ext_fifo_disp_data(31),
      ext_fifo_disp_data(30) => ext_fifo_disp_data(30),
      ext_fifo_disp_data(29) => ext_fifo_disp_data(29),
      ext_fifo_disp_data(28) => ext_fifo_disp_data(28),
      ext_fifo_disp_data(27) => ext_fifo_disp_data(27),
      ext_fifo_disp_data(26) => ext_fifo_disp_data(26),
      ext_fifo_disp_data(25) => ext_fifo_disp_data(25),
      ext_fifo_disp_data(24) => ext_fifo_disp_data(24),
      ext_fifo_disp_data(23) => ext_fifo_disp_data(23),
      ext_fifo_disp_data(22) => ext_fifo_disp_data(22),
      ext_fifo_disp_data(21) => ext_fifo_disp_data(21),
      ext_fifo_disp_data(20) => ext_fifo_disp_data(20),
      ext_fifo_disp_data(19) => ext_fifo_disp_data(19),
      ext_fifo_disp_data(18) => ext_fifo_disp_data(18),
      ext_fifo_disp_data(17) => ext_fifo_disp_data(17),
      ext_fifo_disp_data(16) => ext_fifo_disp_data(16),
      ext_fifo_disp_data(15) => ext_fifo_disp_data(15),
      ext_fifo_disp_data(14) => ext_fifo_disp_data(14),
      ext_fifo_disp_data(13) => ext_fifo_disp_data(13),
      ext_fifo_disp_data(12) => ext_fifo_disp_data(12),
      ext_fifo_disp_data(11) => ext_fifo_disp_data(11),
      ext_fifo_disp_data(10) => ext_fifo_disp_data(10),
      ext_fifo_disp_data(9) => ext_fifo_disp_data(9),
      ext_fifo_disp_data(8) => ext_fifo_disp_data(8),
      ext_fifo_disp_data(7) => ext_fifo_disp_data(7),
      ext_fifo_disp_data(6) => ext_fifo_disp_data(6),
      ext_fifo_disp_data(5) => ext_fifo_disp_data(5),
      ext_fifo_disp_data(4) => ext_fifo_disp_data(4),
      ext_fifo_disp_data(3) => ext_fifo_disp_data(3),
      ext_fifo_disp_data(2) => ext_fifo_disp_data(2),
      ext_fifo_disp_data(1) => ext_fifo_disp_data(1),
      ext_fifo_disp_data(0) => ext_fifo_disp_data(0),
      ext_fifo_disp_back_data(63) => ext_fifo_disp_back_data(63),
      ext_fifo_disp_back_data(62) => ext_fifo_disp_back_data(62),
      ext_fifo_disp_back_data(61) => ext_fifo_disp_back_data(61),
      ext_fifo_disp_back_data(60) => ext_fifo_disp_back_data(60),
      ext_fifo_disp_back_data(59) => ext_fifo_disp_back_data(59),
      ext_fifo_disp_back_data(58) => ext_fifo_disp_back_data(58),
      ext_fifo_disp_back_data(57) => ext_fifo_disp_back_data(57),
      ext_fifo_disp_back_data(56) => ext_fifo_disp_back_data(56),
      ext_fifo_disp_back_data(55) => ext_fifo_disp_back_data(55),
      ext_fifo_disp_back_data(54) => ext_fifo_disp_back_data(54),
      ext_fifo_disp_back_data(53) => ext_fifo_disp_back_data(53),
      ext_fifo_disp_back_data(52) => ext_fifo_disp_back_data(52),
      ext_fifo_disp_back_data(51) => ext_fifo_disp_back_data(51),
      ext_fifo_disp_back_data(50) => ext_fifo_disp_back_data(50),
      ext_fifo_disp_back_data(49) => ext_fifo_disp_back_data(49),
      ext_fifo_disp_back_data(48) => ext_fifo_disp_back_data(48),
      ext_fifo_disp_back_data(47) => ext_fifo_disp_back_data(47),
      ext_fifo_disp_back_data(46) => ext_fifo_disp_back_data(46),
      ext_fifo_disp_back_data(45) => ext_fifo_disp_back_data(45),
      ext_fifo_disp_back_data(44) => ext_fifo_disp_back_data(44),
      ext_fifo_disp_back_data(43) => ext_fifo_disp_back_data(43),
      ext_fifo_disp_back_data(42) => ext_fifo_disp_back_data(42),
      ext_fifo_disp_back_data(41) => ext_fifo_disp_back_data(41),
      ext_fifo_disp_back_data(40) => ext_fifo_disp_back_data(40),
      ext_fifo_disp_back_data(39) => ext_fifo_disp_back_data(39),
      ext_fifo_disp_back_data(38) => ext_fifo_disp_back_data(38),
      ext_fifo_disp_back_data(37) => ext_fifo_disp_back_data(37),
      ext_fifo_disp_back_data(36) => ext_fifo_disp_back_data(36),
      ext_fifo_disp_back_data(35) => ext_fifo_disp_back_data(35),
      ext_fifo_disp_back_data(34) => ext_fifo_disp_back_data(34),
      ext_fifo_disp_back_data(33) => ext_fifo_disp_back_data(33),
      ext_fifo_disp_back_data(32) => ext_fifo_disp_back_data(32),
      ext_fifo_disp_back_data(31) => ext_fifo_disp_back_data(31),
      ext_fifo_disp_back_data(30) => ext_fifo_disp_back_data(30),
      ext_fifo_disp_back_data(29) => ext_fifo_disp_back_data(29),
      ext_fifo_disp_back_data(28) => ext_fifo_disp_back_data(28),
      ext_fifo_disp_back_data(27) => ext_fifo_disp_back_data(27),
      ext_fifo_disp_back_data(26) => ext_fifo_disp_back_data(26),
      ext_fifo_disp_back_data(25) => ext_fifo_disp_back_data(25),
      ext_fifo_disp_back_data(24) => ext_fifo_disp_back_data(24),
      ext_fifo_disp_back_data(23) => ext_fifo_disp_back_data(23),
      ext_fifo_disp_back_data(22) => ext_fifo_disp_back_data(22),
      ext_fifo_disp_back_data(21) => ext_fifo_disp_back_data(21),
      ext_fifo_disp_back_data(20) => ext_fifo_disp_back_data(20),
      ext_fifo_disp_back_data(19) => ext_fifo_disp_back_data(19),
      ext_fifo_disp_back_data(18) => ext_fifo_disp_back_data(18),
      ext_fifo_disp_back_data(17) => ext_fifo_disp_back_data(17),
      ext_fifo_disp_back_data(16) => ext_fifo_disp_back_data(16),
      ext_fifo_disp_back_data(15) => ext_fifo_disp_back_data(15),
      ext_fifo_disp_back_data(14) => ext_fifo_disp_back_data(14),
      ext_fifo_disp_back_data(13) => ext_fifo_disp_back_data(13),
      ext_fifo_disp_back_data(12) => ext_fifo_disp_back_data(12),
      ext_fifo_disp_back_data(11) => ext_fifo_disp_back_data(11),
      ext_fifo_disp_back_data(10) => ext_fifo_disp_back_data(10),
      ext_fifo_disp_back_data(9) => ext_fifo_disp_back_data(9),
      ext_fifo_disp_back_data(8) => ext_fifo_disp_back_data(8),
      ext_fifo_disp_back_data(7) => ext_fifo_disp_back_data(7),
      ext_fifo_disp_back_data(6) => ext_fifo_disp_back_data(6),
      ext_fifo_disp_back_data(5) => ext_fifo_disp_back_data(5),
      ext_fifo_disp_back_data(4) => ext_fifo_disp_back_data(4),
      ext_fifo_disp_back_data(3) => ext_fifo_disp_back_data(3),
      ext_fifo_disp_back_data(2) => ext_fifo_disp_back_data(2),
      ext_fifo_disp_back_data(1) => ext_fifo_disp_back_data(1),
      ext_fifo_disp_back_data(0) => ext_fifo_disp_back_data(0),
      ext_fifo_disp_back_dmar(1) => ext_fifo_disp_back_dmar(1),
      ext_fifo_disp_back_dmar(0) => ext_fifo_disp_back_dmar(0),
      data_in(31) => ram_do_a(31),
      data_in(30) => ram_do_a(30),
      data_in(29) => ram_do_a(29),
      data_in(28) => ram_do_a(28),
      data_in(27) => ram_do_a(27),
      data_in(26) => ram_do_a(26),
      data_in(25) => ram_do_a(25),
      data_in(24) => ram_do_a(24),
      data_in(23) => ram_do_a(23),
      data_in(22) => ram_do_a(22),
      data_in(21) => ram_do_a(21),
      data_in(20) => ram_do_a(20),
      data_in(19) => ram_do_a(19),
      data_in(18) => ram_do_a(18),
      data_in(17) => ram_do_a(17),
      data_in(16) => ram_do_a(16),
      data_in(15) => ram_do_a(15),
      data_in(14) => ram_do_a(14),
      data_in(13) => ram_do_a(13),
      data_in(12) => ram_do_a(12),
      data_in(11) => ram_do_a(11),
      data_in(10) => ram_do_a(10),
      data_in(9) => ram_do_a(9),
      data_in(8) => ram_do_a(8),
      data_in(7) => ram_do_a(7),
      data_in(6) => ram_do_a(6),
      data_in(5) => ram_do_a(5),
      data_in(4) => ram_do_a(4),
      data_in(3) => ram_do_a(3),
      data_in(2) => ram_do_a(2),
      data_in(1) => ram_do_a(1),
      data_in(0) => ram_do_a(0),
      dma_rdaddr(11) => tx_ext_fifo_adr(8),
      dma_rdaddr(10) => tx_ext_fifo_adr(7),
      dma_rdaddr(9) => tx_ext_fifo_adr(6),
      dma_rdaddr(8) => tx_ext_fifo_adr(5),
      dma_rdaddr(7) => tx_ext_fifo_adr(4),
      dma_rdaddr(6) => tx_ext_fifo_adr(3),
      dma_rdaddr(5) => tx_ext_fifo_adr(2),
      dma_rdaddr(4) => tx_ext_fifo_adr(1),
      dma_rdaddr(3) => tx_ext_fifo_adr(0),
      dma_rdaddr(2) => dma0_ctrl(6),
      dma_rdaddr(1) => dma0_ctrl(6),
      dma_rdaddr(0) => dma0_ctrl(6),
      dma0_ctrl(7) => dma0_ctrl(6),
      dma0_ctrl(6) => dma0_ctrl(6),
      dma0_ctrl(5) => reg_dma0_mode_5_Q,
      dma0_ctrl(4) => reg_dma0_ctrl_4_Q,
      dma0_ctrl(3) => reg_dma0_ctrl_3_Q,
      dma0_ctrl(2) => reg_dma0_mode_2_Q,
      dma0_ctrl(1) => reg_dma0_mode_1_Q,
      dma0_ctrl(0) => reg_dma0_ctrl_0_Q,
      dma_wrdata(63) => rx_ext_fifo_data(63),
      dma_wrdata(62) => rx_ext_fifo_data(62),
      dma_wrdata(61) => rx_ext_fifo_data(61),
      dma_wrdata(60) => rx_ext_fifo_data(60),
      dma_wrdata(59) => rx_ext_fifo_data(59),
      dma_wrdata(58) => rx_ext_fifo_data(58),
      dma_wrdata(57) => rx_ext_fifo_data(57),
      dma_wrdata(56) => rx_ext_fifo_data(56),
      dma_wrdata(55) => rx_ext_fifo_data(55),
      dma_wrdata(54) => rx_ext_fifo_data(54),
      dma_wrdata(53) => rx_ext_fifo_data(53),
      dma_wrdata(52) => rx_ext_fifo_data(52),
      dma_wrdata(51) => rx_ext_fifo_data(51),
      dma_wrdata(50) => rx_ext_fifo_data(50),
      dma_wrdata(49) => rx_ext_fifo_data(49),
      dma_wrdata(48) => rx_ext_fifo_data(48),
      dma_wrdata(47) => rx_ext_fifo_data(47),
      dma_wrdata(46) => rx_ext_fifo_data(46),
      dma_wrdata(45) => rx_ext_fifo_data(45),
      dma_wrdata(44) => rx_ext_fifo_data(44),
      dma_wrdata(43) => rx_ext_fifo_data(43),
      dma_wrdata(42) => rx_ext_fifo_data(42),
      dma_wrdata(41) => rx_ext_fifo_data(41),
      dma_wrdata(40) => rx_ext_fifo_data(40),
      dma_wrdata(39) => rx_ext_fifo_data(39),
      dma_wrdata(38) => rx_ext_fifo_data(38),
      dma_wrdata(37) => rx_ext_fifo_data(37),
      dma_wrdata(36) => rx_ext_fifo_data(36),
      dma_wrdata(35) => rx_ext_fifo_data(35),
      dma_wrdata(34) => rx_ext_fifo_data(34),
      dma_wrdata(33) => rx_ext_fifo_data(33),
      dma_wrdata(32) => rx_ext_fifo_data(32),
      dma_wrdata(31) => rx_ext_fifo_data(31),
      dma_wrdata(30) => rx_ext_fifo_data(30),
      dma_wrdata(29) => rx_ext_fifo_data(29),
      dma_wrdata(28) => rx_ext_fifo_data(28),
      dma_wrdata(27) => rx_ext_fifo_data(27),
      dma_wrdata(26) => rx_ext_fifo_data(26),
      dma_wrdata(25) => rx_ext_fifo_data(25),
      dma_wrdata(24) => rx_ext_fifo_data(24),
      dma_wrdata(23) => rx_ext_fifo_data(23),
      dma_wrdata(22) => rx_ext_fifo_data(22),
      dma_wrdata(21) => rx_ext_fifo_data(21),
      dma_wrdata(20) => rx_ext_fifo_data(20),
      dma_wrdata(19) => rx_ext_fifo_data(19),
      dma_wrdata(18) => rx_ext_fifo_data(18),
      dma_wrdata(17) => rx_ext_fifo_data(17),
      dma_wrdata(16) => rx_ext_fifo_data(16),
      dma_wrdata(15) => rx_ext_fifo_data(15),
      dma_wrdata(14) => rx_ext_fifo_data(14),
      dma_wrdata(13) => rx_ext_fifo_data(13),
      dma_wrdata(12) => rx_ext_fifo_data(12),
      dma_wrdata(11) => rx_ext_fifo_data(11),
      dma_wrdata(10) => rx_ext_fifo_data(10),
      dma_wrdata(9) => rx_ext_fifo_data(9),
      dma_wrdata(8) => rx_ext_fifo_data(8),
      dma_wrdata(7) => rx_ext_fifo_data(7),
      dma_wrdata(6) => rx_ext_fifo_data(6),
      dma_wrdata(5) => rx_ext_fifo_data(5),
      dma_wrdata(4) => rx_ext_fifo_data(4),
      dma_wrdata(3) => rx_ext_fifo_data(3),
      dma_wrdata(2) => rx_ext_fifo_data(2),
      dma_wrdata(1) => rx_ext_fifo_data(1),
      dma_wrdata(0) => rx_ext_fifo_data(0),
      dma1_ctrl(7) => dma0_ctrl(6),
      dma1_ctrl(6) => dma0_ctrl(6),
      dma1_ctrl(5) => reg_dma1_mode_5_Q,
      dma1_ctrl(4) => reg_dma1_ctrl_4_Q,
      dma1_ctrl(3) => reg_dma1_ctrl_3_Q,
      dma1_ctrl(2) => reg_dma1_mode_2_Q,
      dma1_ctrl(1) => reg_dma1_mode_1_Q,
      dma1_ctrl(0) => reg_dma1_ctrl_0_Q,
      dma_wraddr(11) => rx_ext_fifo_adr(8),
      dma_wraddr(10) => rx_ext_fifo_adr(7),
      dma_wraddr(9) => rx_ext_fifo_adr(6),
      dma_wraddr(8) => rx_ext_fifo_adr(5),
      dma_wraddr(7) => rx_ext_fifo_adr(4),
      dma_wraddr(6) => rx_ext_fifo_adr(3),
      dma_wraddr(5) => rx_ext_fifo_adr(2),
      dma_wraddr(4) => rx_ext_fifo_adr(1),
      dma_wraddr(3) => rx_ext_fifo_adr(0),
      dma_wraddr(2) => dma0_ctrl(6),
      dma_wraddr(1) => dma0_ctrl(6),
      dma_wraddr(0) => dma0_ctrl(6)
    );
  irq_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => ext_fifo_disp_back_irq,
      I1 => reg_dma0_status_7_Q,
      I2 => reg_dma1_status_7_Q,
      O => irq_or0000
    );
  reg_dma1_mode_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N17,
      I1 => reg_ext_fifo_adr(5),
      I2 => reg_ext_fifo_adr(0),
      O => reg_dma1_mode_not0001
    );
  reg_dma1_ctrl_not00011 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => reg_ext_fifo_adr(0),
      I1 => reg_ext_fifo_adr(5),
      I2 => N17,
      O => reg_dma1_ctrl_not0001
    );
  reg_dma0_mode_not00011 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => N17,
      I1 => reg_ext_fifo_adr(0),
      I2 => reg_ext_fifo_adr(5),
      O => reg_dma0_mode_not0001
    );
  reg_dma0_ctrl_not00012 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N17,
      I1 => reg_ext_fifo_adr(0),
      I2 => reg_ext_fifo_adr(5),
      O => reg_dma0_ctrl_not0001
    );
  reg_dma0_ctrl_not000111 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => reg_ext_fifo_adr(3),
      I1 => reg_ext_fifo_data_we,
      I2 => reg_ext_fifo_adr(6),
      I3 => reg_ext_fifo_adr(4),
      I4 => reg_ext_fifo_adr(2),
      I5 => reg_ext_fifo_adr(1),
      O => N17
    );
  ram1_wr1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => rx_ext_fifo_data_we,
      I1 => dma_reg0(1),
      O => ram1_wr
    );
  reg_ext_fifo_back_data_0_mux000011 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => reg_ext_fifo_adr(6),
      I1 => reg_ext_fifo_adr(1),
      I2 => reg_ext_fifo_adr(2),
      I3 => reg_ext_fifo_adr(3),
      I4 => reg_ext_fifo_adr(4),
      I5 => reg_ext_fifo_adr(0),
      O => N0
    );
  dma1_eot_clr_or0000_SW0 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => reg_ext_fifo_adr(1),
      I1 => reg_ext_fifo_adr(2),
      I2 => reg_ext_fifo_adr(0),
      I3 => reg_ext_fifo_adr(3),
      O => N01
    );
  dma1_eot_clr_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => reg_ext_fifo_data_we,
      I1 => rstp,
      I2 => reg_ext_fifo_adr(6),
      I3 => reg_ext_fifo_adr(5),
      I4 => reg_ext_fifo_adr(4),
      I5 => N01,
      O => dma1_eot_clr_or0000_13008
    );
  dma0_eot_clr_or0000_SW0 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => reg_ext_fifo_adr(1),
      I1 => reg_ext_fifo_adr(2),
      I2 => reg_ext_fifo_adr(0),
      I3 => reg_ext_fifo_adr(3),
      O => N2
    );
  dma0_eot_clr_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => reg_ext_fifo_data_we,
      I1 => reg_ext_fifo_adr(6),
      I2 => reg_ext_fifo_adr(4),
      I3 => reg_ext_fifo_adr(5),
      I4 => rstp,
      I5 => N2,
      O => dma0_eot_clr_or0000_13006
    );
  reg_ext_fifo_back_data_9_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(9),
      O => reg_ext_fifo_back_data(9)
    );
  reg_ext_fifo_back_data_3_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(3),
      O => reg_ext_fifo_back_data(3)
    );
  reg_ext_fifo_back_data_2_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(2),
      O => reg_ext_fifo_back_data(2)
    );
  reg_ext_fifo_back_data_1_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(1),
      O => reg_ext_fifo_back_data(1)
    );
  reg_ext_fifo_back_data_14_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(14),
      O => reg_ext_fifo_back_data(14)
    );
  reg_ext_fifo_back_data_12_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(12),
      O => reg_ext_fifo_back_data(12)
    );
  reg_ext_fifo_back_data_11_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(11),
      O => reg_ext_fifo_back_data(11)
    );
  reg_ext_fifo_back_data_10_mux00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(10),
      O => reg_ext_fifo_back_data(10)
    );
  reg_ext_fifo_back_data_15_mux00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(15),
      O => reg_ext_fifo_back_data(15)
    );
  reg_ext_fifo_back_data_13_mux00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => N0,
      I1 => ram_do_b(13),
      O => reg_ext_fifo_back_data(13)
    );
  reg_ext_fifo_back_data_8_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_8_Q,
      I3 => reg_dma0_status_8_Q,
      I4 => ram_do_b(8),
      O => reg_ext_fifo_back_data(8)
    );
  reg_ext_fifo_back_data_7_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_7_Q,
      I3 => reg_dma0_status_7_Q,
      I4 => ram_do_b(7),
      O => reg_ext_fifo_back_data(7)
    );
  reg_ext_fifo_back_data_6_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_6_Q,
      I3 => reg_dma0_status_6_Q,
      I4 => ram_do_b(6),
      O => reg_ext_fifo_back_data(6)
    );
  reg_ext_fifo_back_data_5_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_5_Q,
      I3 => reg_dma0_status_5_Q,
      I4 => ram_do_b(5),
      O => reg_ext_fifo_back_data(5)
    );
  reg_ext_fifo_back_data_4_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_4_Q,
      I3 => reg_dma0_status_4_Q,
      I4 => ram_do_b(4),
      O => reg_ext_fifo_back_data(4)
    );
  reg_ext_fifo_back_data_0_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => reg_ext_fifo_adr(5),
      I1 => N0,
      I2 => reg_dma1_status_0_Q,
      I3 => reg_dma0_status_0_Q,
      I4 => ram_do_b(0),
      O => reg_ext_fifo_back_data(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_tx_engine is
  port (
    reg_access_back_data_we : in STD_LOGIC := 'X'; 
    rx_tx_engine_complete_we : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    tx_rx_engine_complete_reg : out STD_LOGIC; 
    tx_ext_fifo_back_rd_size : in STD_LOGIC := 'X'; 
    rx_tx_engine_request_reg_wr : in STD_LOGIC := 'X'; 
    trn_tx_trn_tsof_n : out STD_LOGIC; 
    tx_ext_fifo_complete_error : out STD_LOGIC; 
    trn_tx_trn_terrfwd_n : out STD_LOGIC; 
    rstp : in STD_LOGIC := 'X'; 
    tx_ext_fifo_back_req_rd : in STD_LOGIC := 'X'; 
    trn_tx_trn_tsrc_dsc_n : out STD_LOGIC; 
    trn_tx_back_trn_tdst_dsc_n : in STD_LOGIC := 'X'; 
    tx_ext_fifo_back_req_wr : in STD_LOGIC := 'X'; 
    tx_ext_fifo_complete_ok : out STD_LOGIC; 
    reg_access_back_complete : in STD_LOGIC := 'X'; 
    trn_tx_trn_teof_n : out STD_LOGIC; 
    rx_tx_engine_request_reg_rd : in STD_LOGIC := 'X'; 
    trn_tx_trn_tsrc_rdy_n : out STD_LOGIC; 
    trn_tx_back_trn_tdst_rdy_n : in STD_LOGIC := 'X'; 
    trn_tx_trn_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_tx_trn_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    tx_ext_fifo_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
    tx_ext_fifo_back_pci_adr : in STD_LOGIC_VECTOR ( 39 downto 8 ); 
    tx_ext_fifo_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    completer_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    rx_tx_engine_request_attr : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    rx_tx_engine_request_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    reg_access_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    rx_tx_engine_request_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
    trn_tx_back_trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    rx_tx_engine_request_tag : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_tx_back_cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    rx_tx_engine_lower_adr : in STD_LOGIC_VECTOR ( 6 downto 2 ) 
  );
end core64_tx_engine;

architecture STRUCTURE of core64_tx_engine is
  component ctrl_fifo64x67fw
    port (
      clk : in STD_LOGIC := 'X'; 
      rd_en : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      empty : out STD_LOGIC; 
      wr_en : in STD_LOGIC := 'X'; 
      valid : out STD_LOGIC; 
      full : out STD_LOGIC; 
      prog_empty : out STD_LOGIC; 
      prog_full : out STD_LOGIC; 
      dout : out STD_LOGIC_VECTOR ( 66 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 66 downto 0 ) 
    );
  end component;
  signal Mcount_complete_cnt_cy_1_rt_10744 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_2_rt_10746 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_3_rt_10748 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_4_rt_10750 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_5_rt_10752 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_6_rt_10754 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_7_rt_10756 : STD_LOGIC; 
  signal Mcount_complete_cnt_cy_8_rt_10758 : STD_LOGIC; 
  signal Mcount_complete_cnt_val : STD_LOGIC; 
  signal Mcount_complete_cnt_xor_9_rt_10761 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_1_rt_10764 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_2_rt_10766 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_3_rt_10768 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_4_rt_10770 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_5_rt_10772 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_6_rt_10774 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_7_rt_10776 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_8_rt_10778 : STD_LOGIC; 
  signal Mcount_timeout_cnt_cy_9_rt_10780 : STD_LOGIC; 
  signal Mcount_timeout_cnt_xor_10_rt_10782 : STD_LOGIC; 
  signal Mcount_write_cnt : STD_LOGIC; 
  signal Mcount_write_cnt1 : STD_LOGIC; 
  signal Mcount_write_cnt2 : STD_LOGIC; 
  signal Mcount_write_cnt3 : STD_LOGIC; 
  signal Mcount_write_cnt4 : STD_LOGIC; 
  signal Mcount_write_cnt5 : STD_LOGIC; 
  signal Mcount_write_cnt_xor_4_1 : STD_LOGIC; 
  signal Mcount_write_cnt_xor_4_11_10790 : STD_LOGIC; 
  signal Mcount_write_cnt_xor_5_1 : STD_LOGIC; 
  signal Mcount_write_cnt_xor_5_11_10792 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal N107 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N109 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N110 : STD_LOGIC; 
  signal N111 : STD_LOGIC; 
  signal N112 : STD_LOGIC; 
  signal N113 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N115 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal N117 : STD_LOGIC; 
  signal N118 : STD_LOGIC; 
  signal N119 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N121 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N141 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N161 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N181 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N201 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N222 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal N46 : STD_LOGIC; 
  signal N48 : STD_LOGIC; 
  signal N50 : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal N60 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal N64 : STD_LOGIC; 
  signal N66 : STD_LOGIC; 
  signal N68 : STD_LOGIC; 
  signal N70 : STD_LOGIC; 
  signal N72 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal N76 : STD_LOGIC; 
  signal N78 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal N82 : STD_LOGIC; 
  signal N84 : STD_LOGIC; 
  signal N86 : STD_LOGIC; 
  signal N88 : STD_LOGIC; 
  signal N90 : STD_LOGIC; 
  signal N92 : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal N94 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal Result_0_Q : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_0_2 : STD_LOGIC; 
  signal Result_0_3 : STD_LOGIC; 
  signal Result_10_Q : STD_LOGIC; 
  signal Result_1_Q : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_1_2 : STD_LOGIC; 
  signal Result_1_3 : STD_LOGIC; 
  signal Result_1_4 : STD_LOGIC; 
  signal Result_2_Q : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_2_2 : STD_LOGIC; 
  signal Result_2_3 : STD_LOGIC; 
  signal Result_2_4 : STD_LOGIC; 
  signal Result_3_Q : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_3_2 : STD_LOGIC; 
  signal Result_3_3 : STD_LOGIC; 
  signal Result_3_4 : STD_LOGIC; 
  signal Result_4_Q : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_4_2 : STD_LOGIC; 
  signal Result_4_3 : STD_LOGIC; 
  signal Result_4_4 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_5_2 : STD_LOGIC; 
  signal Result_5_3 : STD_LOGIC; 
  signal Result_6_Q : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_7_Q : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal Result_8_Q : STD_LOGIC; 
  signal Result_8_1 : STD_LOGIC; 
  signal Result_9_Q : STD_LOGIC; 
  signal Result_9_1 : STD_LOGIC; 
  signal adr64_10911 : STD_LOGIC; 
  signal complete_cnt_and0000 : STD_LOGIC; 
  signal complete_cnt_cst : STD_LOGIC; 
  signal fifo_data_0_mux0000_10944 : STD_LOGIC; 
  signal fifo_data_10_mux0000 : STD_LOGIC; 
  signal fifo_data_10_mux000015_10948 : STD_LOGIC; 
  signal fifo_data_10_mux000027_10949 : STD_LOGIC; 
  signal fifo_data_10_mux00004_10950 : STD_LOGIC; 
  signal fifo_data_11_mux0000 : STD_LOGIC; 
  signal fifo_data_11_mux000015_10953 : STD_LOGIC; 
  signal fifo_data_11_mux000027_10954 : STD_LOGIC; 
  signal fifo_data_11_mux00004_10955 : STD_LOGIC; 
  signal fifo_data_12_mux0000 : STD_LOGIC; 
  signal fifo_data_12_mux000010_10958 : STD_LOGIC; 
  signal fifo_data_13_mux0000_10960 : STD_LOGIC; 
  signal fifo_data_14_mux0000_10962 : STD_LOGIC; 
  signal fifo_data_15_mux0000_10964 : STD_LOGIC; 
  signal fifo_data_16_mux0000_10966 : STD_LOGIC; 
  signal fifo_data_17_mux0000_10968 : STD_LOGIC; 
  signal fifo_data_18_mux0000_10970 : STD_LOGIC; 
  signal fifo_data_19_mux0000 : STD_LOGIC; 
  signal fifo_data_19_mux00009_10973 : STD_LOGIC; 
  signal fifo_data_1_mux0000_10974 : STD_LOGIC; 
  signal fifo_data_20_mux0000 : STD_LOGIC; 
  signal fifo_data_20_mux00009_10978 : STD_LOGIC; 
  signal fifo_data_21_mux0000 : STD_LOGIC; 
  signal fifo_data_21_mux00009_10981 : STD_LOGIC; 
  signal fifo_data_22_mux0000 : STD_LOGIC; 
  signal fifo_data_22_mux00009_10984 : STD_LOGIC; 
  signal fifo_data_23_mux0000 : STD_LOGIC; 
  signal fifo_data_23_mux00009_10987 : STD_LOGIC; 
  signal fifo_data_24_mux0000 : STD_LOGIC; 
  signal fifo_data_24_mux00009_10990 : STD_LOGIC; 
  signal fifo_data_25_mux0000 : STD_LOGIC; 
  signal fifo_data_25_mux00009_10993 : STD_LOGIC; 
  signal fifo_data_26_mux0000 : STD_LOGIC; 
  signal fifo_data_26_mux00009_10996 : STD_LOGIC; 
  signal fifo_data_27_mux0000 : STD_LOGIC; 
  signal fifo_data_27_mux00009_10999 : STD_LOGIC; 
  signal fifo_data_28_mux0000 : STD_LOGIC; 
  signal fifo_data_28_mux00009_11002 : STD_LOGIC; 
  signal fifo_data_29_mux0000 : STD_LOGIC; 
  signal fifo_data_29_mux00009_11005 : STD_LOGIC; 
  signal fifo_data_2_mux0000 : STD_LOGIC; 
  signal fifo_data_2_mux000013 : STD_LOGIC; 
  signal fifo_data_2_mux0000131_11008 : STD_LOGIC; 
  signal fifo_data_2_mux0000132_11009 : STD_LOGIC; 
  signal fifo_data_30_mux0000 : STD_LOGIC; 
  signal fifo_data_30_mux00009_11013 : STD_LOGIC; 
  signal fifo_data_31_mux0000 : STD_LOGIC; 
  signal fifo_data_31_mux00009_11016 : STD_LOGIC; 
  signal fifo_data_32_mux0000_11018 : STD_LOGIC; 
  signal fifo_data_33_mux0000_11020 : STD_LOGIC; 
  signal fifo_data_34_mux0000_11022 : STD_LOGIC; 
  signal fifo_data_35_mux0000_11024 : STD_LOGIC; 
  signal fifo_data_36_mux0000_11026 : STD_LOGIC; 
  signal fifo_data_37_mux0000 : STD_LOGIC; 
  signal fifo_data_37_mux000025_11029 : STD_LOGIC; 
  signal fifo_data_38_mux0000 : STD_LOGIC; 
  signal fifo_data_38_mux000010_11032 : STD_LOGIC; 
  signal fifo_data_38_mux000011_11033 : STD_LOGIC; 
  signal fifo_data_39_mux0000_11035 : STD_LOGIC; 
  signal fifo_data_3_mux0000_11036 : STD_LOGIC; 
  signal fifo_data_40_mux0000 : STD_LOGIC; 
  signal fifo_data_40_mux000024_11040 : STD_LOGIC; 
  signal fifo_data_40_mux00004_11041 : STD_LOGIC; 
  signal fifo_data_41_mux0000 : STD_LOGIC; 
  signal fifo_data_41_mux00004_11044 : STD_LOGIC; 
  signal fifo_data_42_mux0000 : STD_LOGIC; 
  signal fifo_data_42_mux00004_11047 : STD_LOGIC; 
  signal fifo_data_43_mux0000 : STD_LOGIC; 
  signal fifo_data_43_mux00004_11050 : STD_LOGIC; 
  signal fifo_data_44_mux0000 : STD_LOGIC; 
  signal fifo_data_44_mux000010_11053 : STD_LOGIC; 
  signal fifo_data_44_mux000023_11054 : STD_LOGIC; 
  signal fifo_data_45_mux0000 : STD_LOGIC; 
  signal fifo_data_45_mux000010_11057 : STD_LOGIC; 
  signal fifo_data_45_mux000023_11058 : STD_LOGIC; 
  signal fifo_data_46_mux0000 : STD_LOGIC; 
  signal fifo_data_46_mux000010_11061 : STD_LOGIC; 
  signal fifo_data_46_mux000023_11062 : STD_LOGIC; 
  signal fifo_data_47_mux0000 : STD_LOGIC; 
  signal fifo_data_47_mux000010_11065 : STD_LOGIC; 
  signal fifo_data_47_mux000023_11066 : STD_LOGIC; 
  signal fifo_data_48_mux0000_11068 : STD_LOGIC; 
  signal fifo_data_49_mux0000_11070 : STD_LOGIC; 
  signal fifo_data_4_mux0000_11071 : STD_LOGIC; 
  signal fifo_data_50_mux0000_11074 : STD_LOGIC; 
  signal fifo_data_51_mux0000_11076 : STD_LOGIC; 
  signal fifo_data_52_mux0000 : STD_LOGIC; 
  signal fifo_data_52_mux000010_11079 : STD_LOGIC; 
  signal fifo_data_52_mux000023_11080 : STD_LOGIC; 
  signal fifo_data_53_mux0000 : STD_LOGIC; 
  signal fifo_data_53_mux000010_11083 : STD_LOGIC; 
  signal fifo_data_53_mux000023_11084 : STD_LOGIC; 
  signal fifo_data_54_mux0000 : STD_LOGIC; 
  signal fifo_data_54_mux000010_11087 : STD_LOGIC; 
  signal fifo_data_54_mux000023_11088 : STD_LOGIC; 
  signal fifo_data_55_mux0000_11090 : STD_LOGIC; 
  signal fifo_data_56_mux0000_11092 : STD_LOGIC; 
  signal fifo_data_57_mux0000_11094 : STD_LOGIC; 
  signal fifo_data_58_mux0000_11096 : STD_LOGIC; 
  signal fifo_data_59_mux0000_11098 : STD_LOGIC; 
  signal fifo_data_5_mux0000_11099 : STD_LOGIC; 
  signal fifo_data_60_mux0000_11102 : STD_LOGIC; 
  signal fifo_data_61_mux0000_11104 : STD_LOGIC; 
  signal fifo_data_62_mux0000 : STD_LOGIC; 
  signal fifo_data_62_mux000034_11107 : STD_LOGIC; 
  signal fifo_data_63_mux0000_11109 : STD_LOGIC; 
  signal fifo_data_6_mux0000_11110 : STD_LOGIC; 
  signal fifo_data_7_mux0000 : STD_LOGIC; 
  signal fifo_data_7_mux000012_11113 : STD_LOGIC; 
  signal fifo_data_7_mux000019_11114 : STD_LOGIC; 
  signal fifo_data_7_mux00004_11115 : STD_LOGIC; 
  signal fifo_data_8_mux0000 : STD_LOGIC; 
  signal fifo_data_8_mux000016_11118 : STD_LOGIC; 
  signal fifo_data_8_mux000022_11119 : STD_LOGIC; 
  signal fifo_data_9_mux0000 : STD_LOGIC; 
  signal fifo_data_9_mux000015_11122 : STD_LOGIC; 
  signal fifo_data_9_mux000027_11123 : STD_LOGIC; 
  signal fifo_data_9_mux00004_11124 : STD_LOGIC; 
  signal fifo_empty : STD_LOGIC; 
  signal fifo_eof_11126 : STD_LOGIC; 
  signal fifo_eof_mux0000 : STD_LOGIC; 
  signal fifo_paf : STD_LOGIC; 
  signal fifo_rd : STD_LOGIC; 
  signal fifo_rrem_11130 : STD_LOGIC; 
  signal fifo_rrem_mux0000_11131 : STD_LOGIC; 
  signal fifo_sof_11132 : STD_LOGIC; 
  signal fifo_sof_mux0000 : STD_LOGIC; 
  signal fifo_wr_11134 : STD_LOGIC; 
  signal fifo_wr_mux0000 : STD_LOGIC; 
  signal fifo_wr_mux000014_11136 : STD_LOGIC; 
  signal fifo_wr_mux000023_11137 : STD_LOGIC; 
  signal req_cnt_and0000 : STD_LOGIC; 
  signal rstpz_11212 : STD_LOGIC; 
  signal rstpz1_11213 : STD_LOGIC; 
  signal stp_FSM_FFd1_11253 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd10_11255 : STD_LOGIC; 
  signal stp_FSM_FFd11_11256 : STD_LOGIC; 
  signal stp_FSM_FFd11_In : STD_LOGIC; 
  signal stp_FSM_FFd12_11258 : STD_LOGIC; 
  signal stp_FSM_FFd12_In : STD_LOGIC; 
  signal stp_FSM_FFd13_11260 : STD_LOGIC; 
  signal stp_FSM_FFd13_In : STD_LOGIC; 
  signal stp_FSM_FFd13_In1_11262 : STD_LOGIC; 
  signal stp_FSM_FFd14_11263 : STD_LOGIC; 
  signal stp_FSM_FFd14_In : STD_LOGIC; 
  signal stp_FSM_FFd15_11265 : STD_LOGIC; 
  signal stp_FSM_FFd15_In : STD_LOGIC; 
  signal stp_FSM_FFd15_In1_11267 : STD_LOGIC; 
  signal stp_FSM_FFd15_In2_11268 : STD_LOGIC; 
  signal stp_FSM_FFd16_11269 : STD_LOGIC; 
  signal stp_FSM_FFd16_In : STD_LOGIC; 
  signal stp_FSM_FFd16_In101_11271 : STD_LOGIC; 
  signal stp_FSM_FFd16_In22_11272 : STD_LOGIC; 
  signal stp_FSM_FFd16_In29_11273 : STD_LOGIC; 
  signal stp_FSM_FFd16_In42_11274 : STD_LOGIC; 
  signal stp_FSM_FFd2_11275 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_11277 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_11279 : STD_LOGIC; 
  signal stp_FSM_FFd5_11280 : STD_LOGIC; 
  signal stp_FSM_FFd6_11281 : STD_LOGIC; 
  signal stp_FSM_FFd6_In : STD_LOGIC; 
  signal stp_FSM_FFd7_11283 : STD_LOGIC; 
  signal stp_FSM_FFd8_11284 : STD_LOGIC; 
  signal stp_FSM_FFd8_In : STD_LOGIC; 
  signal stp_FSM_FFd9_11286 : STD_LOGIC; 
  signal stp_FSM_FFd9_In : STD_LOGIC; 
  signal timeout_cnt_en : STD_LOGIC; 
  signal timeout_st0_11300 : STD_LOGIC; 
  signal timeout_st0_and0000_norst : STD_LOGIC; 
  signal NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_ext_fifo_complete_error : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_ext_fifo_complete_ok : STD_LOGIC; 
  signal tx_ext_fifo_complete_error_mux0000 : STD_LOGIC; 
  signal tx_ext_fifo_complete_ok_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_tx_rx_engine_complete_reg : STD_LOGIC; 
  signal tx_rx_engine_complete_reg_mux0000 : STD_LOGIC; 
  signal wait_complete_11517 : STD_LOGIC; 
  signal wait_complete_mux0000 : STD_LOGIC; 
  signal write_cnt_en_11525 : STD_LOGIC; 
  signal write_cnt_en_inv : STD_LOGIC; 
  signal write_cnt_en_mux0000_11527 : STD_LOGIC; 
  signal write_cnt_not0002 : STD_LOGIC; 
  signal write_cnt_pkg_and0000 : STD_LOGIC; 
  signal write_cnt_pkg_eq : STD_LOGIC; 
  signal write_state_11536 : STD_LOGIC; 
  signal write_state_mux0000 : STD_LOGIC; 
  signal NLW_fifo0_reg_valid_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_prog_empty_UNCONNECTED : STD_LOGIC; 
  signal NLW_xtcnt_Q_UNCONNECTED : STD_LOGIC; 
  signal Maccum_write_cnt_pkg_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_complete_cnt_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_complete_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_timeout_cnt_cy : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal Mcount_timeout_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSig_OI_adr_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal adr_cnt : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal complete_cnt : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal fifo_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal reg_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal req_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal timeout_cnt : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal tlp_read_dw3 : STD_LOGIC_VECTOR ( 11 downto 9 ); 
  signal tlp_write_data_z : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSignal_trn_tx_trn_trem_n : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSig_OI_trn_tx_trn_trem_n : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal write_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal write_cnt_pkg : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSig_OI_write_cnt_pkg : STD_LOGIC_VECTOR ( 4 downto 1 ); 
begin
  tx_rx_engine_complete_reg <= NlwRenamedSig_OI_tx_rx_engine_complete_reg;
  tx_ext_fifo_complete_error <= NlwRenamedSig_OI_tx_ext_fifo_complete_error;
  trn_tx_trn_terrfwd_n <= NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n;
  trn_tx_trn_tsrc_dsc_n <= NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n;
  tx_ext_fifo_complete_ok <= NlwRenamedSig_OI_tx_ext_fifo_complete_ok;
  trn_tx_trn_trem_n(7) <= NlwRenamedSig_OI_trn_tx_trn_trem_n(4);
  trn_tx_trn_trem_n(6) <= NlwRenamedSig_OI_trn_tx_trn_trem_n(4);
  trn_tx_trn_trem_n(5) <= NlwRenamedSig_OI_trn_tx_trn_trem_n(4);
  trn_tx_trn_trem_n(4) <= NlwRenamedSig_OI_trn_tx_trn_trem_n(4);
  trn_tx_trn_trem_n(3) <= NlwRenamedSignal_trn_tx_trn_trem_n(0);
  trn_tx_trn_trem_n(2) <= NlwRenamedSignal_trn_tx_trn_trem_n(0);
  trn_tx_trn_trem_n(1) <= NlwRenamedSignal_trn_tx_trn_trem_n(0);
  trn_tx_trn_trem_n(0) <= NlwRenamedSignal_trn_tx_trn_trem_n(0);
  tx_ext_fifo_adr(8) <= NlwRenamedSig_OI_write_cnt_pkg(4);
  tx_ext_fifo_adr(7) <= NlwRenamedSig_OI_write_cnt_pkg(3);
  tx_ext_fifo_adr(6) <= NlwRenamedSig_OI_write_cnt_pkg(2);
  tx_ext_fifo_adr(5) <= NlwRenamedSig_OI_write_cnt_pkg(1);
  tx_ext_fifo_adr(3) <= NlwRenamedSig_OI_adr_cnt(3);
  tx_ext_fifo_adr(2) <= NlwRenamedSig_OI_adr_cnt(2);
  tx_ext_fifo_adr(1) <= NlwRenamedSig_OI_adr_cnt(1);
  tx_ext_fifo_adr(0) <= NlwRenamedSig_OI_adr_cnt(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_trn_tx_trn_trem_n(4)
    );
  XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n
    );
  fifo_data_13 : FD
    port map (
      C => clk,
      D => fifo_data_13_mux0000_10960,
      Q => fifo_data(13)
    );
  fifo_data_11 : FD
    port map (
      C => clk,
      D => fifo_data_11_mux0000,
      Q => fifo_data(11)
    );
  fifo_data_12 : FD
    port map (
      C => clk,
      D => fifo_data_12_mux0000,
      Q => fifo_data(12)
    );
  fifo_data_15 : FD
    port map (
      C => clk,
      D => fifo_data_15_mux0000_10964,
      Q => fifo_data(15)
    );
  fifo_wr : FD
    port map (
      C => clk,
      D => fifo_wr_mux0000,
      Q => fifo_wr_11134
    );
  fifo_data_14 : FD
    port map (
      C => clk,
      D => fifo_data_14_mux0000_10962,
      Q => fifo_data(14)
    );
  fifo_data_20 : FD
    port map (
      C => clk,
      D => fifo_data_20_mux0000,
      Q => fifo_data(20)
    );
  fifo_data_17 : FD
    port map (
      C => clk,
      D => fifo_data_17_mux0000_10968,
      Q => fifo_data(17)
    );
  fifo_data_21 : FD
    port map (
      C => clk,
      D => fifo_data_21_mux0000,
      Q => fifo_data(21)
    );
  fifo_data_16 : FD
    port map (
      C => clk,
      D => fifo_data_16_mux0000_10966,
      Q => fifo_data(16)
    );
  fifo_data_23 : FD
    port map (
      C => clk,
      D => fifo_data_23_mux0000,
      Q => fifo_data(23)
    );
  fifo_data_22 : FD
    port map (
      C => clk,
      D => fifo_data_22_mux0000,
      Q => fifo_data(22)
    );
  fifo_data_18 : FD
    port map (
      C => clk,
      D => fifo_data_18_mux0000_10970,
      Q => fifo_data(18)
    );
  fifo_data_25 : FD
    port map (
      C => clk,
      D => fifo_data_25_mux0000,
      Q => fifo_data(25)
    );
  fifo_data_19 : FD
    port map (
      C => clk,
      D => fifo_data_19_mux0000,
      Q => fifo_data(19)
    );
  fifo_data_24 : FD
    port map (
      C => clk,
      D => fifo_data_24_mux0000,
      Q => fifo_data(24)
    );
  fifo_data_30 : FD
    port map (
      C => clk,
      D => fifo_data_30_mux0000,
      Q => fifo_data(30)
    );
  fifo_sof : FD
    port map (
      C => clk,
      D => fifo_sof_mux0000,
      Q => fifo_sof_11132
    );
  fifo_data_27 : FD
    port map (
      C => clk,
      D => fifo_data_27_mux0000,
      Q => fifo_data(27)
    );
  fifo_data_26 : FD
    port map (
      C => clk,
      D => fifo_data_26_mux0000,
      Q => fifo_data(26)
    );
  fifo_data_31 : FD
    port map (
      C => clk,
      D => fifo_data_31_mux0000,
      Q => fifo_data(31)
    );
  fifo_data_33 : FD
    port map (
      C => clk,
      D => fifo_data_33_mux0000_11020,
      Q => fifo_data(33)
    );
  fifo_data_32 : FD
    port map (
      C => clk,
      D => fifo_data_32_mux0000_11018,
      Q => fifo_data(32)
    );
  fifo_data_28 : FD
    port map (
      C => clk,
      D => fifo_data_28_mux0000,
      Q => fifo_data(28)
    );
  fifo_data_35 : FD
    port map (
      C => clk,
      D => fifo_data_35_mux0000_11024,
      Q => fifo_data(35)
    );
  fifo_data_34 : FD
    port map (
      C => clk,
      D => fifo_data_34_mux0000_11022,
      Q => fifo_data(34)
    );
  fifo_data_29 : FD
    port map (
      C => clk,
      D => fifo_data_29_mux0000,
      Q => fifo_data(29)
    );
  fifo_data_40 : FD
    port map (
      C => clk,
      D => fifo_data_40_mux0000,
      Q => fifo_data(40)
    );
  tx_rx_engine_complete_reg_8094 : FD
    port map (
      C => clk,
      D => tx_rx_engine_complete_reg_mux0000,
      Q => NlwRenamedSig_OI_tx_rx_engine_complete_reg
    );
  fifo_data_37 : FD
    port map (
      C => clk,
      D => fifo_data_37_mux0000,
      Q => fifo_data(37)
    );
  fifo_data_36 : FD
    port map (
      C => clk,
      D => fifo_data_36_mux0000_11026,
      Q => fifo_data(36)
    );
  fifo_data_41 : FD
    port map (
      C => clk,
      D => fifo_data_41_mux0000,
      Q => fifo_data(41)
    );
  fifo_data_43 : FD
    port map (
      C => clk,
      D => fifo_data_43_mux0000,
      Q => fifo_data(43)
    );
  fifo_data_42 : FD
    port map (
      C => clk,
      D => fifo_data_42_mux0000,
      Q => fifo_data(42)
    );
  fifo_data_38 : FD
    port map (
      C => clk,
      D => fifo_data_38_mux0000,
      Q => fifo_data(38)
    );
  fifo_data_44 : FD
    port map (
      C => clk,
      D => fifo_data_44_mux0000,
      Q => fifo_data(44)
    );
  fifo_eof : FD
    port map (
      C => clk,
      D => fifo_eof_mux0000,
      Q => fifo_eof_11126
    );
  fifo_data_39 : FD
    port map (
      C => clk,
      D => fifo_data_39_mux0000_11035,
      Q => fifo_data(39)
    );
  fifo_data_50 : FD
    port map (
      C => clk,
      D => fifo_data_50_mux0000_11074,
      Q => fifo_data(50)
    );
  fifo_data_45 : FD
    port map (
      C => clk,
      D => fifo_data_45_mux0000,
      Q => fifo_data(45)
    );
  fifo_data_51 : FD
    port map (
      C => clk,
      D => fifo_data_51_mux0000_11076,
      Q => fifo_data(51)
    );
  tx_ext_fifo_complete_error_8107 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_complete_error_mux0000,
      Q => NlwRenamedSig_OI_tx_ext_fifo_complete_error
    );
  fifo_data_46 : FD
    port map (
      C => clk,
      D => fifo_data_46_mux0000,
      Q => fifo_data(46)
    );
  fifo_data_48 : FD
    port map (
      C => clk,
      D => fifo_data_48_mux0000_11068,
      Q => fifo_data(48)
    );
  fifo_data_47 : FD
    port map (
      C => clk,
      D => fifo_data_47_mux0000,
      Q => fifo_data(47)
    );
  fifo_data_52 : FD
    port map (
      C => clk,
      D => fifo_data_52_mux0000,
      Q => fifo_data(52)
    );
  fifo_data_54 : FD
    port map (
      C => clk,
      D => fifo_data_54_mux0000,
      Q => fifo_data(54)
    );
  fifo_data_53 : FD
    port map (
      C => clk,
      D => fifo_data_53_mux0000,
      Q => fifo_data(53)
    );
  fifo_data_49 : FD
    port map (
      C => clk,
      D => fifo_data_49_mux0000_11070,
      Q => fifo_data(49)
    );
  reg_data_0 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(0),
      Q => reg_data(0)
    );
  reg_data_1 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(1),
      Q => reg_data(1)
    );
  reg_data_2 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(2),
      Q => reg_data(2)
    );
  reg_data_3 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(3),
      Q => reg_data(3)
    );
  reg_data_4 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(4),
      Q => reg_data(4)
    );
  reg_data_5 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(5),
      Q => reg_data(5)
    );
  reg_data_6 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(6),
      Q => reg_data(6)
    );
  reg_data_7 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(7),
      Q => reg_data(7)
    );
  reg_data_8 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(8),
      Q => reg_data(8)
    );
  reg_data_9 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(9),
      Q => reg_data(9)
    );
  reg_data_10 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(10),
      Q => reg_data(10)
    );
  reg_data_11 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(11),
      Q => reg_data(11)
    );
  reg_data_12 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(12),
      Q => reg_data(12)
    );
  reg_data_13 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(13),
      Q => reg_data(13)
    );
  reg_data_14 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(14),
      Q => reg_data(14)
    );
  reg_data_15 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(15),
      Q => reg_data(15)
    );
  reg_data_16 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(16),
      Q => reg_data(16)
    );
  reg_data_17 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(17),
      Q => reg_data(17)
    );
  reg_data_18 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(18),
      Q => reg_data(18)
    );
  reg_data_19 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(19),
      Q => reg_data(19)
    );
  reg_data_20 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(20),
      Q => reg_data(20)
    );
  reg_data_21 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(21),
      Q => reg_data(21)
    );
  reg_data_22 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(22),
      Q => reg_data(22)
    );
  reg_data_23 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(23),
      Q => reg_data(23)
    );
  reg_data_24 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(24),
      Q => reg_data(24)
    );
  reg_data_25 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(25),
      Q => reg_data(25)
    );
  reg_data_26 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(26),
      Q => reg_data(26)
    );
  reg_data_27 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(27),
      Q => reg_data(27)
    );
  reg_data_28 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(28),
      Q => reg_data(28)
    );
  reg_data_29 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(29),
      Q => reg_data(29)
    );
  reg_data_30 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(30),
      Q => reg_data(30)
    );
  reg_data_31 : FDE
    port map (
      C => clk,
      CE => reg_access_back_data_we,
      D => reg_access_back_data(31),
      Q => reg_data(31)
    );
  fifo_data_55 : FD
    port map (
      C => clk,
      D => fifo_data_55_mux0000_11090,
      Q => fifo_data(55)
    );
  fifo_data_56 : FD
    port map (
      C => clk,
      D => fifo_data_56_mux0000_11092,
      Q => fifo_data(56)
    );
  fifo_data_60 : FD
    port map (
      C => clk,
      D => fifo_data_60_mux0000_11102,
      Q => fifo_data(60)
    );
  fifo_data_57 : FD
    port map (
      C => clk,
      D => fifo_data_57_mux0000_11094,
      Q => fifo_data(57)
    );
  fifo_data_61 : FD
    port map (
      C => clk,
      D => fifo_data_61_mux0000_11104,
      Q => fifo_data(61)
    );
  rstpz : FD
    port map (
      C => clk,
      D => rstp,
      Q => rstpz_11212
    );
  fifo_data_63 : FD
    port map (
      C => clk,
      D => fifo_data_63_mux0000_11109,
      Q => fifo_data(63)
    );
  fifo_data_62 : FD
    port map (
      C => clk,
      D => fifo_data_62_mux0000,
      Q => fifo_data(62)
    );
  fifo_data_58 : FD
    port map (
      C => clk,
      D => fifo_data_58_mux0000_11096,
      Q => fifo_data(58)
    );
  fifo_data_59 : FD
    port map (
      C => clk,
      D => fifo_data_59_mux0000_11098,
      Q => fifo_data(59)
    );
  tx_ext_fifo_complete_ok_8157 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_complete_ok_mux0000,
      Q => NlwRenamedSig_OI_tx_ext_fifo_complete_ok
    );
  tlp_write_data_z_0 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(56),
      Q => tlp_write_data_z(0)
    );
  tlp_write_data_z_1 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(57),
      Q => tlp_write_data_z(1)
    );
  tlp_write_data_z_2 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(58),
      Q => tlp_write_data_z(2)
    );
  tlp_write_data_z_3 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(59),
      Q => tlp_write_data_z(3)
    );
  tlp_write_data_z_4 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(60),
      Q => tlp_write_data_z(4)
    );
  tlp_write_data_z_5 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(61),
      Q => tlp_write_data_z(5)
    );
  tlp_write_data_z_6 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(62),
      Q => tlp_write_data_z(6)
    );
  tlp_write_data_z_7 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(63),
      Q => tlp_write_data_z(7)
    );
  tlp_write_data_z_8 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(48),
      Q => tlp_write_data_z(8)
    );
  tlp_write_data_z_9 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(49),
      Q => tlp_write_data_z(9)
    );
  tlp_write_data_z_10 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(50),
      Q => tlp_write_data_z(10)
    );
  tlp_write_data_z_11 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(51),
      Q => tlp_write_data_z(11)
    );
  tlp_write_data_z_12 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(52),
      Q => tlp_write_data_z(12)
    );
  tlp_write_data_z_13 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(53),
      Q => tlp_write_data_z(13)
    );
  tlp_write_data_z_14 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(54),
      Q => tlp_write_data_z(14)
    );
  tlp_write_data_z_15 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(55),
      Q => tlp_write_data_z(15)
    );
  tlp_write_data_z_16 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(40),
      Q => tlp_write_data_z(16)
    );
  tlp_write_data_z_17 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(41),
      Q => tlp_write_data_z(17)
    );
  tlp_write_data_z_18 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(42),
      Q => tlp_write_data_z(18)
    );
  tlp_write_data_z_19 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(43),
      Q => tlp_write_data_z(19)
    );
  tlp_write_data_z_20 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(44),
      Q => tlp_write_data_z(20)
    );
  tlp_write_data_z_21 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(45),
      Q => tlp_write_data_z(21)
    );
  tlp_write_data_z_22 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(46),
      Q => tlp_write_data_z(22)
    );
  tlp_write_data_z_23 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(47),
      Q => tlp_write_data_z(23)
    );
  tlp_write_data_z_24 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(32),
      Q => tlp_write_data_z(24)
    );
  tlp_write_data_z_25 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(33),
      Q => tlp_write_data_z(25)
    );
  tlp_write_data_z_26 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(34),
      Q => tlp_write_data_z(26)
    );
  tlp_write_data_z_27 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(35),
      Q => tlp_write_data_z(27)
    );
  tlp_write_data_z_28 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(36),
      Q => tlp_write_data_z(28)
    );
  tlp_write_data_z_29 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(37),
      Q => tlp_write_data_z(29)
    );
  tlp_write_data_z_30 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(38),
      Q => tlp_write_data_z(30)
    );
  tlp_write_data_z_31 : FD
    port map (
      C => clk,
      D => tx_ext_fifo_back_data(39),
      Q => tlp_write_data_z(31)
    );
  fifo_rrem : FD
    port map (
      C => clk,
      D => fifo_rrem_mux0000_11131,
      Q => fifo_rrem_11130
    );
  fifo_data_0 : FD
    port map (
      C => clk,
      D => fifo_data_0_mux0000_10944,
      Q => fifo_data(0)
    );
  fifo_data_1 : FD
    port map (
      C => clk,
      D => fifo_data_1_mux0000_10974,
      Q => fifo_data(1)
    );
  fifo_data_4 : FD
    port map (
      C => clk,
      D => fifo_data_4_mux0000_11071,
      Q => fifo_data(4)
    );
  fifo_data_2 : FD
    port map (
      C => clk,
      D => fifo_data_2_mux0000,
      Q => fifo_data(2)
    );
  fifo_data_3 : FD
    port map (
      C => clk,
      D => fifo_data_3_mux0000_11036,
      Q => fifo_data(3)
    );
  fifo_data_7 : FD
    port map (
      C => clk,
      D => fifo_data_7_mux0000,
      Q => fifo_data(7)
    );
  fifo_data_5 : FD
    port map (
      C => clk,
      D => fifo_data_5_mux0000_11099,
      Q => fifo_data(5)
    );
  fifo_data_6 : FD
    port map (
      C => clk,
      D => fifo_data_6_mux0000_11110,
      Q => fifo_data(6)
    );
  write_cnt_en : FD
    port map (
      C => clk,
      D => write_cnt_en_mux0000_11527,
      Q => write_cnt_en_11525
    );
  fifo_data_8 : FD
    port map (
      C => clk,
      D => fifo_data_8_mux0000,
      Q => fifo_data(8)
    );
  fifo_data_9 : FD
    port map (
      C => clk,
      D => fifo_data_9_mux0000,
      Q => fifo_data(9)
    );
  fifo_data_10 : FD
    port map (
      C => clk,
      D => fifo_data_10_mux0000,
      Q => fifo_data(10)
    );
  wait_complete : FDR
    port map (
      C => clk,
      D => wait_complete_mux0000,
      R => rstpz_11212,
      Q => wait_complete_11517
    );
  write_state : FDR
    port map (
      C => clk,
      D => write_state_mux0000,
      R => rstpz_11212,
      Q => write_state_11536
    );
  rstpz1 : FD
    port map (
      C => clk,
      D => rstpz_11212,
      Q => rstpz1_11213
    );
  timeout_st0 : FDR
    port map (
      C => clk,
      D => timeout_st0_and0000_norst,
      R => rstpz_11212,
      Q => timeout_st0_11300
    );
  adr_cnt_0 : FDR
    port map (
      C => clk,
      D => Result_0_Q,
      R => write_cnt_en_inv,
      Q => NlwRenamedSig_OI_adr_cnt(0)
    );
  adr_cnt_1 : FDR
    port map (
      C => clk,
      D => Result_1_Q,
      R => write_cnt_en_inv,
      Q => NlwRenamedSig_OI_adr_cnt(1)
    );
  adr_cnt_2 : FDR
    port map (
      C => clk,
      D => Result_2_Q,
      R => write_cnt_en_inv,
      Q => NlwRenamedSig_OI_adr_cnt(2)
    );
  adr_cnt_3 : FDR
    port map (
      C => clk,
      D => Result_3_Q,
      R => write_cnt_en_inv,
      Q => NlwRenamedSig_OI_adr_cnt(3)
    );
  adr_cnt_4 : FDR
    port map (
      C => clk,
      D => Result_4_Q,
      R => write_cnt_en_inv,
      Q => adr_cnt(4)
    );
  complete_cnt_0 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_0_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(0)
    );
  complete_cnt_3 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_3_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(3)
    );
  complete_cnt_1 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_1_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(1)
    );
  complete_cnt_2 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_2_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(2)
    );
  complete_cnt_6 : FDRSE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_6_Q,
      R => complete_cnt_and0000,
      S => complete_cnt_cst,
      Q => complete_cnt(6)
    );
  complete_cnt_4 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_4_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(4)
    );
  complete_cnt_5 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_5_2,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(5)
    );
  complete_cnt_7 : FDRSE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_7_Q,
      R => complete_cnt_and0000,
      S => complete_cnt_cst,
      Q => complete_cnt(7)
    );
  complete_cnt_8 : FDRSE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_8_Q,
      R => complete_cnt_and0000,
      S => complete_cnt_cst,
      Q => complete_cnt(8)
    );
  write_cnt_0 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt,
      Q => write_cnt(0)
    );
  write_cnt_1 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt1,
      Q => write_cnt(1)
    );
  write_cnt_2 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt2,
      Q => write_cnt(2)
    );
  write_cnt_3 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt3,
      Q => write_cnt(3)
    );
  write_cnt_4 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt4,
      Q => write_cnt(4)
    );
  write_cnt_5 : FDE
    port map (
      C => clk,
      CE => write_cnt_not0002,
      D => Mcount_write_cnt5,
      Q => write_cnt(5)
    );
  req_cnt_0 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_0_1,
      R => req_cnt_and0000,
      Q => req_cnt(0)
    );
  req_cnt_1 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_1_1,
      R => req_cnt_and0000,
      Q => req_cnt(1)
    );
  req_cnt_2 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_2_1,
      R => req_cnt_and0000,
      Q => req_cnt(2)
    );
  req_cnt_3 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_3_1,
      R => req_cnt_and0000,
      Q => req_cnt(3)
    );
  req_cnt_4 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_4_1,
      R => req_cnt_and0000,
      Q => req_cnt(4)
    );
  req_cnt_5 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd7_11283,
      D => Result_5_1,
      R => req_cnt_and0000,
      Q => req_cnt(5)
    );
  timeout_cnt_0 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_0_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(0)
    );
  timeout_cnt_1 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_1_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(1)
    );
  timeout_cnt_2 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_2_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(2)
    );
  timeout_cnt_3 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_3_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(3)
    );
  timeout_cnt_4 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_4_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(4)
    );
  timeout_cnt_5 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_5_3,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(5)
    );
  timeout_cnt_6 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_6_1,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(6)
    );
  timeout_cnt_7 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_7_1,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(7)
    );
  timeout_cnt_8 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_8_1,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(8)
    );
  timeout_cnt_9 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_9_1,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(9)
    );
  timeout_cnt_10 : FDRE
    port map (
      C => clk,
      CE => timeout_cnt_en,
      D => Result_10_Q,
      R => Mcount_complete_cnt_val,
      Q => timeout_cnt(10)
    );
  complete_cnt_9 : FDRE
    port map (
      C => clk,
      CE => rx_tx_engine_complete_we,
      D => Result_9_Q,
      R => Mcount_complete_cnt_val,
      Q => complete_cnt(9)
    );
  write_cnt_pkg_0 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_11275,
      D => Maccum_write_cnt_pkg_lut(0),
      R => write_cnt_pkg_and0000,
      Q => write_cnt_pkg(0)
    );
  write_cnt_pkg_1 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_11275,
      D => Result_1_4,
      R => write_cnt_pkg_and0000,
      Q => NlwRenamedSig_OI_write_cnt_pkg(1)
    );
  write_cnt_pkg_2 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_11275,
      D => Result_2_4,
      R => write_cnt_pkg_and0000,
      Q => NlwRenamedSig_OI_write_cnt_pkg(2)
    );
  write_cnt_pkg_3 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_11275,
      D => Result_3_4,
      R => write_cnt_pkg_and0000,
      Q => NlwRenamedSig_OI_write_cnt_pkg(3)
    );
  write_cnt_pkg_4 : FDRE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_11275,
      D => Result_4_4,
      R => write_cnt_pkg_and0000,
      Q => NlwRenamedSig_OI_write_cnt_pkg(4)
    );
  Mcount_complete_cnt_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      DI => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      S => Mcount_complete_cnt_lut(0),
      O => Mcount_complete_cnt_cy(0)
    );
  Mcount_complete_cnt_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      LI => Mcount_complete_cnt_lut(0),
      O => Result_0_2
    );
  Mcount_complete_cnt_cy_1_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(0),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_1_rt_10744,
      O => Mcount_complete_cnt_cy(1)
    );
  Mcount_complete_cnt_xor_1_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(0),
      LI => Mcount_complete_cnt_cy_1_rt_10744,
      O => Result_1_2
    );
  Mcount_complete_cnt_cy_2_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(1),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_2_rt_10746,
      O => Mcount_complete_cnt_cy(2)
    );
  Mcount_complete_cnt_xor_2_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(1),
      LI => Mcount_complete_cnt_cy_2_rt_10746,
      O => Result_2_2
    );
  Mcount_complete_cnt_cy_3_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(2),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_3_rt_10748,
      O => Mcount_complete_cnt_cy(3)
    );
  Mcount_complete_cnt_xor_3_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(2),
      LI => Mcount_complete_cnt_cy_3_rt_10748,
      O => Result_3_2
    );
  Mcount_complete_cnt_cy_4_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(3),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_4_rt_10750,
      O => Mcount_complete_cnt_cy(4)
    );
  Mcount_complete_cnt_xor_4_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(3),
      LI => Mcount_complete_cnt_cy_4_rt_10750,
      O => Result_4_2
    );
  Mcount_complete_cnt_cy_5_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(4),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_5_rt_10752,
      O => Mcount_complete_cnt_cy(5)
    );
  Mcount_complete_cnt_xor_5_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(4),
      LI => Mcount_complete_cnt_cy_5_rt_10752,
      O => Result_5_2
    );
  Mcount_complete_cnt_cy_6_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(5),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_6_rt_10754,
      O => Mcount_complete_cnt_cy(6)
    );
  Mcount_complete_cnt_xor_6_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(5),
      LI => Mcount_complete_cnt_cy_6_rt_10754,
      O => Result_6_Q
    );
  Mcount_complete_cnt_cy_7_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(6),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_7_rt_10756,
      O => Mcount_complete_cnt_cy(7)
    );
  Mcount_complete_cnt_xor_7_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(6),
      LI => Mcount_complete_cnt_cy_7_rt_10756,
      O => Result_7_Q
    );
  Mcount_complete_cnt_cy_8_Q : MUXCY
    port map (
      CI => Mcount_complete_cnt_cy(7),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_complete_cnt_cy_8_rt_10758,
      O => Mcount_complete_cnt_cy(8)
    );
  Mcount_complete_cnt_xor_8_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(7),
      LI => Mcount_complete_cnt_cy_8_rt_10758,
      O => Result_8_Q
    );
  Mcount_complete_cnt_xor_9_Q : XORCY
    port map (
      CI => Mcount_complete_cnt_cy(8),
      LI => Mcount_complete_cnt_xor_9_rt_10761,
      O => Result_9_Q
    );
  Mcount_timeout_cnt_cy_0_Q : MUXCY
    port map (
      CI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      DI => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      S => Mcount_timeout_cnt_lut(0),
      O => Mcount_timeout_cnt_cy(0)
    );
  Mcount_timeout_cnt_xor_0_Q : XORCY
    port map (
      CI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      LI => Mcount_timeout_cnt_lut(0),
      O => Result_0_3
    );
  Mcount_timeout_cnt_cy_1_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(0),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_1_rt_10764,
      O => Mcount_timeout_cnt_cy(1)
    );
  Mcount_timeout_cnt_xor_1_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(0),
      LI => Mcount_timeout_cnt_cy_1_rt_10764,
      O => Result_1_3
    );
  Mcount_timeout_cnt_cy_2_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(1),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_2_rt_10766,
      O => Mcount_timeout_cnt_cy(2)
    );
  Mcount_timeout_cnt_xor_2_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(1),
      LI => Mcount_timeout_cnt_cy_2_rt_10766,
      O => Result_2_3
    );
  Mcount_timeout_cnt_cy_3_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(2),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_3_rt_10768,
      O => Mcount_timeout_cnt_cy(3)
    );
  Mcount_timeout_cnt_xor_3_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(2),
      LI => Mcount_timeout_cnt_cy_3_rt_10768,
      O => Result_3_3
    );
  Mcount_timeout_cnt_cy_4_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(3),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_4_rt_10770,
      O => Mcount_timeout_cnt_cy(4)
    );
  Mcount_timeout_cnt_xor_4_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(3),
      LI => Mcount_timeout_cnt_cy_4_rt_10770,
      O => Result_4_3
    );
  Mcount_timeout_cnt_cy_5_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(4),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_5_rt_10772,
      O => Mcount_timeout_cnt_cy(5)
    );
  Mcount_timeout_cnt_xor_5_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(4),
      LI => Mcount_timeout_cnt_cy_5_rt_10772,
      O => Result_5_3
    );
  Mcount_timeout_cnt_cy_6_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(5),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_6_rt_10774,
      O => Mcount_timeout_cnt_cy(6)
    );
  Mcount_timeout_cnt_xor_6_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(5),
      LI => Mcount_timeout_cnt_cy_6_rt_10774,
      O => Result_6_1
    );
  Mcount_timeout_cnt_cy_7_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(6),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_7_rt_10776,
      O => Mcount_timeout_cnt_cy(7)
    );
  Mcount_timeout_cnt_xor_7_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(6),
      LI => Mcount_timeout_cnt_cy_7_rt_10776,
      O => Result_7_1
    );
  Mcount_timeout_cnt_cy_8_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(7),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_8_rt_10778,
      O => Mcount_timeout_cnt_cy(8)
    );
  Mcount_timeout_cnt_xor_8_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(7),
      LI => Mcount_timeout_cnt_cy_8_rt_10778,
      O => Result_8_1
    );
  Mcount_timeout_cnt_cy_9_Q : MUXCY
    port map (
      CI => Mcount_timeout_cnt_cy(8),
      DI => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      S => Mcount_timeout_cnt_cy_9_rt_10780,
      O => Mcount_timeout_cnt_cy(9)
    );
  Mcount_timeout_cnt_xor_9_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(8),
      LI => Mcount_timeout_cnt_cy_9_rt_10780,
      O => Result_9_1
    );
  Mcount_timeout_cnt_xor_10_Q : XORCY
    port map (
      CI => Mcount_timeout_cnt_cy(9),
      LI => Mcount_timeout_cnt_xor_10_rt_10782,
      O => Result_10_Q
    );
  fifo0_reg : ctrl_fifo64x67fw
    port map (
      clk => clk,
      rd_en => fifo_rd,
      rst => rstpz_11212,
      empty => fifo_empty,
      wr_en => fifo_wr_11134,
      valid => NLW_fifo0_reg_valid_UNCONNECTED,
      full => NLW_fifo0_reg_full_UNCONNECTED,
      prog_empty => NLW_fifo0_reg_prog_empty_UNCONNECTED,
      prog_full => fifo_paf,
      dout(66) => NlwRenamedSignal_trn_tx_trn_trem_n(0),
      dout(65) => trn_tx_trn_teof_n,
      dout(64) => trn_tx_trn_tsof_n,
      dout(63) => trn_tx_trn_td(63),
      dout(62) => trn_tx_trn_td(62),
      dout(61) => trn_tx_trn_td(61),
      dout(60) => trn_tx_trn_td(60),
      dout(59) => trn_tx_trn_td(59),
      dout(58) => trn_tx_trn_td(58),
      dout(57) => trn_tx_trn_td(57),
      dout(56) => trn_tx_trn_td(56),
      dout(55) => trn_tx_trn_td(55),
      dout(54) => trn_tx_trn_td(54),
      dout(53) => trn_tx_trn_td(53),
      dout(52) => trn_tx_trn_td(52),
      dout(51) => trn_tx_trn_td(51),
      dout(50) => trn_tx_trn_td(50),
      dout(49) => trn_tx_trn_td(49),
      dout(48) => trn_tx_trn_td(48),
      dout(47) => trn_tx_trn_td(47),
      dout(46) => trn_tx_trn_td(46),
      dout(45) => trn_tx_trn_td(45),
      dout(44) => trn_tx_trn_td(44),
      dout(43) => trn_tx_trn_td(43),
      dout(42) => trn_tx_trn_td(42),
      dout(41) => trn_tx_trn_td(41),
      dout(40) => trn_tx_trn_td(40),
      dout(39) => trn_tx_trn_td(39),
      dout(38) => trn_tx_trn_td(38),
      dout(37) => trn_tx_trn_td(37),
      dout(36) => trn_tx_trn_td(36),
      dout(35) => trn_tx_trn_td(35),
      dout(34) => trn_tx_trn_td(34),
      dout(33) => trn_tx_trn_td(33),
      dout(32) => trn_tx_trn_td(32),
      dout(31) => trn_tx_trn_td(31),
      dout(30) => trn_tx_trn_td(30),
      dout(29) => trn_tx_trn_td(29),
      dout(28) => trn_tx_trn_td(28),
      dout(27) => trn_tx_trn_td(27),
      dout(26) => trn_tx_trn_td(26),
      dout(25) => trn_tx_trn_td(25),
      dout(24) => trn_tx_trn_td(24),
      dout(23) => trn_tx_trn_td(23),
      dout(22) => trn_tx_trn_td(22),
      dout(21) => trn_tx_trn_td(21),
      dout(20) => trn_tx_trn_td(20),
      dout(19) => trn_tx_trn_td(19),
      dout(18) => trn_tx_trn_td(18),
      dout(17) => trn_tx_trn_td(17),
      dout(16) => trn_tx_trn_td(16),
      dout(15) => trn_tx_trn_td(15),
      dout(14) => trn_tx_trn_td(14),
      dout(13) => trn_tx_trn_td(13),
      dout(12) => trn_tx_trn_td(12),
      dout(11) => trn_tx_trn_td(11),
      dout(10) => trn_tx_trn_td(10),
      dout(9) => trn_tx_trn_td(9),
      dout(8) => trn_tx_trn_td(8),
      dout(7) => trn_tx_trn_td(7),
      dout(6) => trn_tx_trn_td(6),
      dout(5) => trn_tx_trn_td(5),
      dout(4) => trn_tx_trn_td(4),
      dout(3) => trn_tx_trn_td(3),
      dout(2) => trn_tx_trn_td(2),
      dout(1) => trn_tx_trn_td(1),
      dout(0) => trn_tx_trn_td(0),
      din(66) => fifo_rrem_11130,
      din(65) => fifo_eof_11126,
      din(64) => fifo_sof_11132,
      din(63) => fifo_data(63),
      din(62) => fifo_data(62),
      din(61) => fifo_data(61),
      din(60) => fifo_data(60),
      din(59) => fifo_data(59),
      din(58) => fifo_data(58),
      din(57) => fifo_data(57),
      din(56) => fifo_data(56),
      din(55) => fifo_data(55),
      din(54) => fifo_data(54),
      din(53) => fifo_data(53),
      din(52) => fifo_data(52),
      din(51) => fifo_data(51),
      din(50) => fifo_data(50),
      din(49) => fifo_data(49),
      din(48) => fifo_data(48),
      din(47) => fifo_data(47),
      din(46) => fifo_data(46),
      din(45) => fifo_data(45),
      din(44) => fifo_data(44),
      din(43) => fifo_data(43),
      din(42) => fifo_data(42),
      din(41) => fifo_data(41),
      din(40) => fifo_data(40),
      din(39) => fifo_data(39),
      din(38) => fifo_data(38),
      din(37) => fifo_data(37),
      din(36) => fifo_data(36),
      din(35) => fifo_data(35),
      din(34) => fifo_data(34),
      din(33) => fifo_data(33),
      din(32) => fifo_data(32),
      din(31) => fifo_data(31),
      din(30) => fifo_data(30),
      din(29) => fifo_data(29),
      din(28) => fifo_data(28),
      din(27) => fifo_data(27),
      din(26) => fifo_data(26),
      din(25) => fifo_data(25),
      din(24) => fifo_data(24),
      din(23) => fifo_data(23),
      din(22) => fifo_data(22),
      din(21) => fifo_data(21),
      din(20) => fifo_data(20),
      din(19) => fifo_data(19),
      din(18) => fifo_data(18),
      din(17) => fifo_data(17),
      din(16) => fifo_data(16),
      din(15) => fifo_data(15),
      din(14) => fifo_data(14),
      din(13) => fifo_data(13),
      din(12) => fifo_data(12),
      din(11) => fifo_data(11),
      din(10) => fifo_data(10),
      din(9) => fifo_data(9),
      din(8) => fifo_data(8),
      din(7) => fifo_data(7),
      din(6) => fifo_data(6),
      din(5) => fifo_data(5),
      din(4) => fifo_data(4),
      din(3) => fifo_data(3),
      din(2) => fifo_data(2),
      din(1) => fifo_data(1),
      din(0) => fifo_data(0)
    );
  xtcnt : SRLC32E
    generic map(
      INIT => X"00000000"
    )
    port map (
      CLK => clk,
      D => timeout_st0_11300,
      CE => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      Q => NLW_xtcnt_Q_UNCONNECTED,
      Q31 => timeout_cnt_en,
      A(4) => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      A(3) => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      A(2) => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      A(1) => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n,
      A(0) => NlwRenamedSig_OI_trn_tx_trn_tsrc_dsc_n
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd1_11253
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd2_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd2_11275
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd3_11277
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd6_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd6_11281
    );
  stp_FSM_FFd8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd8_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd8_11284
    );
  stp_FSM_FFd9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd9_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd9_11286
    );
  stp_FSM_FFd11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd11_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd11_11256
    );
  stp_FSM_FFd12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd12_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd12_11258
    );
  stp_FSM_FFd13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd13_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd13_11260
    );
  stp_FSM_FFd14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd14_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd14_11263
    );
  stp_FSM_FFd15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd15_In,
      R => rstpz_11212,
      Q => stp_FSM_FFd15_11265
    );
  stp_FSM_FFd16 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd16_In,
      S => rstpz_11212,
      Q => stp_FSM_FFd16_11269
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd13_11260,
      R => rstpz_11212,
      Q => stp_FSM_FFd5_11280
    );
  stp_FSM_FFd7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd8_11284,
      R => rstpz_11212,
      Q => stp_FSM_FFd7_11283
    );
  stp_FSM_FFd10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd11_11256,
      R => rstpz_11212,
      Q => stp_FSM_FFd10_11255
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd5_11280,
      R => rstpz_11212,
      Q => stp_FSM_FFd4_11279
    );
  stp_FSM_FFd2_In1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => write_cnt(5),
      I1 => stp_FSM_FFd3_11277,
      O => stp_FSM_FFd2_In
    );
  Maccum_write_cnt_pkg_lut_0_11 : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => write_cnt_pkg(0),
      I1 => trn_tx_back_cfg_dcommand(5),
      O => Maccum_write_cnt_pkg_lut(0)
    );
  Mcount_req_cnt_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => req_cnt(1),
      I1 => req_cnt(0),
      O => Result_1_1
    );
  Mcount_adr_cnt_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => NlwRenamedSig_OI_adr_cnt(1),
      I1 => NlwRenamedSig_OI_adr_cnt(0),
      O => Result_1_Q
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd4_11279,
      I1 => write_cnt(5),
      I2 => stp_FSM_FFd3_11277,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd11_In1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => stp_FSM_FFd15_11265,
      I1 => reg_access_back_complete,
      I2 => rx_tx_engine_request_reg_wr,
      O => stp_FSM_FFd11_In
    );
  Result_1_41 : LUT3
    generic map(
      INIT => X"56"
    )
    port map (
      I0 => NlwRenamedSig_OI_write_cnt_pkg(1),
      I1 => write_cnt_pkg(0),
      I2 => trn_tx_back_cfg_dcommand(5),
      O => Result_1_4
    );
  Mcount_write_cnt_xor_1_11 : LUT3
    generic map(
      INIT => X"14"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(0),
      I2 => write_cnt(1),
      O => Mcount_write_cnt1
    );
  Mcount_req_cnt_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => req_cnt(0),
      I1 => req_cnt(2),
      I2 => req_cnt(1),
      O => Result_2_1
    );
  Mcount_adr_cnt_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => NlwRenamedSig_OI_adr_cnt(0),
      I1 => NlwRenamedSig_OI_adr_cnt(2),
      I2 => NlwRenamedSig_OI_adr_cnt(1),
      O => Result_2_Q
    );
  stp_FSM_FFd9_In1 : LUT4
    generic map(
      INIT => X"F020"
    )
    port map (
      I0 => req_cnt(2),
      I1 => tx_ext_fifo_back_rd_size,
      I2 => stp_FSM_FFd14_11263,
      I3 => req_cnt(5),
      O => stp_FSM_FFd9_In
    );
  stp_FSM_FFd8_In1 : LUT4
    generic map(
      INIT => X"0C04"
    )
    port map (
      I0 => req_cnt(2),
      I1 => stp_FSM_FFd14_11263,
      I2 => req_cnt(5),
      I3 => tx_ext_fifo_back_rd_size,
      O => stp_FSM_FFd8_In
    );
  Result_2_41 : LUT4
    generic map(
      INIT => X"56AA"
    )
    port map (
      I0 => NlwRenamedSig_OI_write_cnt_pkg(2),
      I1 => trn_tx_back_cfg_dcommand(5),
      I2 => write_cnt_pkg(0),
      I3 => NlwRenamedSig_OI_write_cnt_pkg(1),
      O => Result_2_4
    );
  Mcount_write_cnt_xor_2_11 : LUT4
    generic map(
      INIT => X"1450"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(0),
      I2 => write_cnt(2),
      I3 => write_cnt(1),
      O => Mcount_write_cnt2
    );
  Mcount_req_cnt_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => req_cnt(0),
      I1 => req_cnt(3),
      I2 => req_cnt(1),
      I3 => req_cnt(2),
      O => Result_3_1
    );
  Mcount_adr_cnt_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => NlwRenamedSig_OI_adr_cnt(0),
      I1 => NlwRenamedSig_OI_adr_cnt(3),
      I2 => NlwRenamedSig_OI_adr_cnt(1),
      I3 => NlwRenamedSig_OI_adr_cnt(2),
      O => Result_3_Q
    );
  stp_FSM_FFd6_In1 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => stp_FSM_FFd9_11286,
      I1 => complete_cnt(9),
      I2 => timeout_cnt(10),
      I3 => stp_FSM_FFd6_11281,
      I4 => tx_ext_fifo_back_req_rd,
      O => stp_FSM_FFd6_In
    );
  Result_3_41 : LUT5
    generic map(
      INIT => X"666AAAAA"
    )
    port map (
      I0 => NlwRenamedSig_OI_write_cnt_pkg(3),
      I1 => NlwRenamedSig_OI_write_cnt_pkg(2),
      I2 => write_cnt_pkg(0),
      I3 => trn_tx_back_cfg_dcommand(5),
      I4 => NlwRenamedSig_OI_write_cnt_pkg(1),
      O => Result_3_4
    );
  Mcount_write_cnt_xor_3_11 : LUT5
    generic map(
      INIT => X"14505050"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(0),
      I2 => write_cnt(3),
      I3 => write_cnt(1),
      I4 => write_cnt(2),
      O => Mcount_write_cnt3
    );
  Mcount_req_cnt_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => req_cnt(0),
      I1 => req_cnt(4),
      I2 => req_cnt(1),
      I3 => req_cnt(2),
      I4 => req_cnt(3),
      O => Result_4_1
    );
  Mcount_adr_cnt_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => NlwRenamedSig_OI_adr_cnt(0),
      I1 => adr_cnt(4),
      I2 => NlwRenamedSig_OI_adr_cnt(1),
      I3 => NlwRenamedSig_OI_adr_cnt(2),
      I4 => NlwRenamedSig_OI_adr_cnt(3),
      O => Result_4_Q
    );
  stp_FSM_FFd12_In1 : LUT6
    generic map(
      INIT => X"FFFFFFFFF8C8C8C8"
    )
    port map (
      I0 => rx_tx_engine_request_reg_rd,
      I1 => stp_FSM_FFd12_11258,
      I2 => rx_tx_engine_request_reg_wr,
      I3 => reg_access_back_complete,
      I4 => stp_FSM_FFd15_11265,
      I5 => stp_FSM_FFd10_11255,
      O => stp_FSM_FFd12_In
    );
  Mcount_req_cnt_xor_5_11 : LUT6
    generic map(
      INIT => X"6CCCCCCCCCCCCCCC"
    )
    port map (
      I0 => req_cnt(0),
      I1 => req_cnt(5),
      I2 => req_cnt(1),
      I3 => req_cnt(2),
      I4 => req_cnt(3),
      I5 => req_cnt(4),
      O => Result_5_1
    );
  Result_4_41 : LUT6
    generic map(
      INIT => X"36CCCCCCCCCCCCCC"
    )
    port map (
      I0 => trn_tx_back_cfg_dcommand(5),
      I1 => NlwRenamedSig_OI_write_cnt_pkg(4),
      I2 => write_cnt_pkg(0),
      I3 => NlwRenamedSig_OI_write_cnt_pkg(1),
      I4 => NlwRenamedSig_OI_write_cnt_pkg(3),
      I5 => NlwRenamedSig_OI_write_cnt_pkg(2),
      O => Result_4_4
    );
  write_cnt_not00021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => write_cnt_en_11525,
      I1 => stp_FSM_FFd16_11269,
      O => write_cnt_not0002
    );
  stp_FSM_FFd1_In1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => tx_ext_fifo_back_req_wr,
      I1 => stp_FSM_FFd1_11253,
      I2 => write_cnt_pkg_eq,
      I3 => stp_FSM_FFd2_11275,
      O => stp_FSM_FFd1_In
    );
  stp_FSM_FFd14_In2 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => N14,
      I1 => tx_ext_fifo_back_req_rd,
      I2 => fifo_paf,
      I3 => stp_FSM_FFd16_11269,
      I4 => trn_tx_back_trn_tbuf_av(0),
      O => stp_FSM_FFd14_In
    );
  write_cnt_pkg_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => write_state_11536,
      I1 => stp_FSM_FFd16_11269,
      O => write_cnt_pkg_and0000
    );
  req_cnt_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => wait_complete_11517,
      I1 => stp_FSM_FFd16_11269,
      O => req_cnt_and0000
    );
  complete_cnt_cst1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => tx_ext_fifo_back_rd_size,
      I1 => wait_complete_11517,
      O => complete_cnt_cst
    );
  complete_cnt_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => wait_complete_11517,
      I1 => tx_ext_fifo_back_rd_size,
      O => complete_cnt_and0000
    );
  tx_ext_fifo_adr_4_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => adr_cnt(4),
      I1 => write_cnt_pkg(0),
      O => tx_ext_fifo_adr(4)
    );
  write_cnt_pkg_eq1 : LUT6
    generic map(
      INIT => X"C000000080000000"
    )
    port map (
      I0 => trn_tx_back_cfg_dcommand(5),
      I1 => NlwRenamedSig_OI_write_cnt_pkg(3),
      I2 => NlwRenamedSig_OI_write_cnt_pkg(4),
      I3 => NlwRenamedSig_OI_write_cnt_pkg(1),
      I4 => NlwRenamedSig_OI_write_cnt_pkg(2),
      I5 => write_cnt_pkg(0),
      O => write_cnt_pkg_eq
    );
  stp_FSM_FFd14_In11 : LUT3
    generic map(
      INIT => X"57"
    )
    port map (
      I0 => trn_tx_back_trn_tbuf_av(2),
      I1 => rx_tx_engine_request_reg_wr,
      I2 => rx_tx_engine_request_reg_rd,
      O => N14
    );
  fifo_sof_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => N15,
      I1 => stp_FSM_FFd2_11275,
      I2 => fifo_sof_11132,
      I3 => N0,
      I4 => stp_FSM_FFd3_11277,
      I5 => stp_FSM_FFd10_11255,
      O => fifo_sof_mux0000
    );
  fifo_wr_mux000014 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => stp_FSM_FFd9_11286,
      I2 => stp_FSM_FFd15_11265,
      I3 => stp_FSM_FFd14_11263,
      I4 => stp_FSM_FFd4_11279,
      O => fifo_wr_mux000014_11136
    );
  fifo_wr_mux000023 : LUT4
    generic map(
      INIT => X"CCC8"
    )
    port map (
      I0 => stp_FSM_FFd6_11281,
      I1 => fifo_wr_11134,
      I2 => stp_FSM_FFd13_11260,
      I3 => fifo_wr_mux000014_11136,
      O => fifo_wr_mux000023_11137
    );
  timeout_st0_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => rstpz1_11213,
      I1 => timeout_cnt_en,
      O => timeout_st0_and0000_norst
    );
  fifo_data_39_mux000011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd7_11283,
      I1 => stp_FSM_FFd4_11279,
      O => N15
    );
  write_state_mux00001 : LUT5
    generic map(
      INIT => X"FFFFAAA8"
    )
    port map (
      I0 => write_state_11536,
      I1 => stp_FSM_FFd12_11258,
      I2 => N13,
      I3 => stp_FSM_FFd16_11269,
      I4 => stp_FSM_FFd5_11280,
      O => write_state_mux0000
    );
  wait_complete_mux0000112 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd13_11260,
      I1 => stp_FSM_FFd5_11280,
      I2 => stp_FSM_FFd2_11275,
      I3 => N19,
      I4 => stp_FSM_FFd12_11258,
      O => N12
    );
  wait_complete_mux00001 : LUT5
    generic map(
      INIT => X"FFFFAAA8"
    )
    port map (
      I0 => wait_complete_11517,
      I1 => stp_FSM_FFd1_11253,
      I2 => N12,
      I3 => stp_FSM_FFd16_11269,
      I4 => stp_FSM_FFd8_11284,
      O => wait_complete_mux0000
    );
  tx_rx_engine_complete_reg_mux0000111 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd13_11260,
      I1 => stp_FSM_FFd6_11281,
      I2 => N19,
      I3 => stp_FSM_FFd8_11284,
      I4 => stp_FSM_FFd2_11275,
      O => N13
    );
  tx_rx_engine_complete_reg_mux00001 : LUT5
    generic map(
      INIT => X"FFFFAAA8"
    )
    port map (
      I0 => NlwRenamedSig_OI_tx_rx_engine_complete_reg,
      I1 => stp_FSM_FFd1_11253,
      I2 => N13,
      I3 => stp_FSM_FFd5_11280,
      I4 => stp_FSM_FFd12_11258,
      O => tx_rx_engine_complete_reg_mux0000
    );
  tx_ext_fifo_complete_error_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => NlwRenamedSig_OI_tx_ext_fifo_complete_error,
      I1 => N12,
      I2 => stp_FSM_FFd8_11284,
      I3 => stp_FSM_FFd6_11281,
      I4 => timeout_cnt(10),
      O => tx_ext_fifo_complete_error_mux0000
    );
  tx_ext_fifo_complete_ok_mux00001 : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => NlwRenamedSig_OI_tx_ext_fifo_complete_ok,
      I1 => N12,
      I2 => stp_FSM_FFd1_11253,
      I3 => stp_FSM_FFd6_11281,
      I4 => complete_cnt(9),
      I5 => stp_FSM_FFd8_11284,
      O => tx_ext_fifo_complete_ok_mux0000
    );
  wait_complete_mux0000111_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd11_11256,
      I1 => stp_FSM_FFd7_11283,
      I2 => stp_FSM_FFd10_11255,
      O => N8
    );
  wait_complete_mux0000111 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd15_11265,
      I1 => stp_FSM_FFd9_11286,
      I2 => stp_FSM_FFd3_11277,
      I3 => stp_FSM_FFd4_11279,
      I4 => stp_FSM_FFd14_11263,
      I5 => N8,
      O => N19
    );
  stp_FSM_FFd16_In22 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => stp_FSM_FFd9_11286,
      I1 => timeout_cnt(10),
      I2 => complete_cnt(9),
      O => stp_FSM_FFd16_In22_11272
    );
  stp_FSM_FFd16_In29 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF22F2"
    )
    port map (
      I0 => stp_FSM_FFd1_11253,
      I1 => tx_ext_fifo_back_req_wr,
      I2 => stp_FSM_FFd6_11281,
      I3 => tx_ext_fifo_back_req_rd,
      I4 => stp_FSM_FFd7_11283,
      I5 => stp_FSM_FFd16_In22_11272,
      O => stp_FSM_FFd16_In29_11273
    );
  stp_FSM_FFd16_In101 : LUT6
    generic map(
      INIT => X"FFFFFFFF02220AAA"
    )
    port map (
      I0 => N14,
      I1 => tx_ext_fifo_back_req_rd,
      I2 => tx_ext_fifo_back_req_wr,
      I3 => trn_tx_back_trn_tbuf_av(1),
      I4 => trn_tx_back_trn_tbuf_av(0),
      I5 => fifo_paf,
      O => stp_FSM_FFd16_In101_11271
    );
  stp_FSM_FFd16_In114 : LUT5
    generic map(
      INIT => X"FFFFF444"
    )
    port map (
      I0 => write_cnt_pkg_eq,
      I1 => stp_FSM_FFd2_11275,
      I2 => stp_FSM_FFd16_11269,
      I3 => stp_FSM_FFd16_In101_11271,
      I4 => stp_FSM_FFd16_In42_11274,
      O => stp_FSM_FFd16_In
    );
  fifo_data_16_mux000021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd3_11277,
      I1 => stp_FSM_FFd2_11275,
      O => N11
    );
  Mcount_write_cnt_xor_0_11 : LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(0),
      I2 => adr64_10911,
      O => Mcount_write_cnt
    );
  fifo_data_10_mux000011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd8_11284,
      I1 => stp_FSM_FFd5_11280,
      O => N20
    );
  fifo_data_16_mux00001_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd9_11286,
      I1 => stp_FSM_FFd14_11263,
      I2 => stp_FSM_FFd12_11258,
      O => N10
    );
  fifo_data_16_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd1_11253,
      I1 => stp_FSM_FFd13_11260,
      I2 => stp_FSM_FFd15_11265,
      I3 => stp_FSM_FFd16_11269,
      I4 => stp_FSM_FFd6_11281,
      I5 => N10,
      O => N0
    );
  tlp_read_dw3_9_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => tx_ext_fifo_back_rd_size,
      I1 => tx_ext_fifo_back_pci_adr(9),
      I2 => req_cnt(2),
      O => tlp_read_dw3(9)
    );
  tlp_read_dw3_11_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => tx_ext_fifo_back_rd_size,
      I1 => tx_ext_fifo_back_pci_adr(11),
      I2 => req_cnt(4),
      O => tlp_read_dw3(11)
    );
  tlp_read_dw3_10_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => tx_ext_fifo_back_rd_size,
      I1 => tx_ext_fifo_back_pci_adr(10),
      I2 => req_cnt(3),
      O => tlp_read_dw3(10)
    );
  write_cnt_en_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd6_11281,
      I1 => stp_FSM_FFd8_11284,
      I2 => stp_FSM_FFd12_11258,
      I3 => N19,
      O => N141
    );
  write_cnt_en_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCFC88F8"
    )
    port map (
      I0 => stp_FSM_FFd1_11253,
      I1 => write_cnt_en_11525,
      I2 => stp_FSM_FFd13_11260,
      I3 => adr64_10911,
      I4 => N141,
      I5 => stp_FSM_FFd5_11280,
      O => write_cnt_en_mux0000_11527
    );
  fifo_rrem_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCFC88F8"
    )
    port map (
      I0 => stp_FSM_FFd11_11256,
      I1 => rx_tx_engine_request_reg_wr,
      I2 => stp_FSM_FFd5_11280,
      I3 => adr64_10911,
      I4 => stp_FSM_FFd10_11255,
      I5 => N161,
      O => fifo_rrem_mux0000_11131
    );
  fifo_data_36_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(36),
      I1 => N15,
      I2 => rx_tx_engine_lower_adr(4),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(36),
      I5 => N0,
      O => N181
    );
  fifo_data_35_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(35),
      I1 => N15,
      I2 => rx_tx_engine_lower_adr(3),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(35),
      I5 => N0,
      O => N201
    );
  fifo_data_34_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(34),
      I1 => N15,
      I2 => rx_tx_engine_lower_adr(2),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(34),
      I5 => N0,
      O => N222
    );
  fifo_data_32_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(32),
      I1 => N15,
      I2 => rx_tx_engine_request_reg_rd,
      I3 => stp_FSM_FFd11_11256,
      I4 => fifo_data(32),
      I5 => N0,
      O => N24
    );
  fifo_data_38_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_lower_adr(6),
      I1 => stp_FSM_FFd10_11255,
      I2 => stp_FSM_FFd5_11280,
      I3 => trn_tx_back_cfg_dcommand(5),
      I4 => fifo_data(38),
      I5 => N0,
      O => fifo_data_38_mux000010_11032
    );
  fifo_data_38_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEAAA"
    )
    port map (
      I0 => fifo_data_38_mux000010_11032,
      I1 => N11,
      I2 => tx_ext_fifo_back_data(30),
      I3 => adr64_10911,
      I4 => tlp_write_data_z(6),
      I5 => fifo_data_38_mux000011_11033,
      O => fifo_data_38_mux0000
    );
  fifo_data_12_mux000011 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => adr64_10911,
      I1 => stp_FSM_FFd4_11279,
      I2 => stp_FSM_FFd7_11283,
      O => N18
    );
  fifo_data_61_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(29),
      I1 => N15,
      I2 => rx_tx_engine_request_id(13),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(61),
      I5 => N0,
      O => N26
    );
  fifo_data_61_mux0000 : LUT6
    generic map(
      INIT => X"FDFDF8A8DDDDD888"
    )
    port map (
      I0 => adr64_10911,
      I1 => N27,
      I2 => N11,
      I3 => tlp_write_data_z(29),
      I4 => N26,
      I5 => tx_ext_fifo_back_data(5),
      O => fifo_data_61_mux0000_11104
    );
  fifo_data_43_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => fifo_data(43),
      I1 => N0,
      I2 => rx_tx_engine_request_tag(3),
      I3 => stp_FSM_FFd10_11255,
      O => fifo_data_43_mux00004_11050
    );
  fifo_data_42_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => fifo_data(42),
      I1 => N0,
      I2 => rx_tx_engine_request_tag(2),
      I3 => stp_FSM_FFd10_11255,
      O => fifo_data_42_mux00004_11047
    );
  fifo_data_41_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => fifo_data(41),
      I1 => N0,
      I2 => rx_tx_engine_request_tag(1),
      I3 => stp_FSM_FFd10_11255,
      O => fifo_data_41_mux00004_11044
    );
  fifo_data_40_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => fifo_data(40),
      I1 => N0,
      I2 => rx_tx_engine_request_tag(0),
      I3 => stp_FSM_FFd10_11255,
      O => fifo_data_40_mux00004_11041
    );
  fifo_data_40_mux000024 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => req_cnt(1),
      I1 => stp_FSM_FFd7_11283,
      I2 => stp_FSM_FFd4_11279,
      I3 => NlwRenamedSig_OI_write_cnt_pkg(1),
      I4 => N11,
      I5 => tlp_write_data_z(8),
      O => fifo_data_40_mux000024_11040
    );
  trn_tx_trn_tsrc_rdy_n1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => fifo_empty,
      I1 => trn_tx_back_trn_tdst_rdy_n,
      O => trn_tx_trn_tsrc_rdy_n
    );
  fifo_data_39_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => stp_FSM_FFd4_11279,
      I1 => write_cnt_pkg(0),
      I2 => stp_FSM_FFd7_11283,
      I3 => req_cnt(0),
      I4 => fifo_data(39),
      I5 => N0,
      O => N29
    );
  fifo_data_39_mux0000_SW1 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(39),
      I1 => stp_FSM_FFd4_11279,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data(39),
      I4 => N0,
      O => N30
    );
  fifo_data_39_mux0000 : LUT6
    generic map(
      INIT => X"FDFDF8A8DDDDD888"
    )
    port map (
      I0 => adr64_10911,
      I1 => N30,
      I2 => N11,
      I3 => tlp_write_data_z(7),
      I4 => N29,
      I5 => tx_ext_fifo_back_data(31),
      O => fifo_data_39_mux0000_11035
    );
  adr64_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(34),
      I1 => tx_ext_fifo_back_pci_adr(33),
      I2 => tx_ext_fifo_back_pci_adr(32),
      O => N32
    );
  adr64 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(39),
      I1 => tx_ext_fifo_back_pci_adr(38),
      I2 => tx_ext_fifo_back_pci_adr(37),
      I3 => tx_ext_fifo_back_pci_adr(36),
      I4 => tx_ext_fifo_back_pci_adr(35),
      I5 => N32,
      O => adr64_10911
    );
  fifo_data_63_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(31),
      I1 => N22,
      I2 => rx_tx_engine_request_id(15),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(63),
      I5 => N0,
      O => N46
    );
  fifo_data_60_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(28),
      I1 => N22,
      I2 => rx_tx_engine_request_id(12),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(60),
      I5 => N0,
      O => N48
    );
  fifo_data_58_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(26),
      I1 => N22,
      I2 => rx_tx_engine_request_id(10),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(58),
      I5 => N0,
      O => N50
    );
  fifo_data_56_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(24),
      I1 => N22,
      I2 => rx_tx_engine_request_id(8),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(56),
      I5 => N0,
      O => N52
    );
  fifo_data_55_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(23),
      I1 => N22,
      I2 => rx_tx_engine_request_id(7),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(55),
      I5 => N0,
      O => N54
    );
  fifo_data_51_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(19),
      I1 => N22,
      I2 => rx_tx_engine_request_id(3),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(51),
      I5 => N0,
      O => N56
    );
  fifo_data_50_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(18),
      I1 => N22,
      I2 => rx_tx_engine_request_id(2),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(50),
      I5 => N0,
      O => N58
    );
  fifo_data_49_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(17),
      I1 => N22,
      I2 => rx_tx_engine_request_id(1),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(49),
      I5 => N0,
      O => N60
    );
  fifo_data_48_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(16),
      I1 => N22,
      I2 => rx_tx_engine_request_id(0),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(48),
      I5 => N0,
      O => N62
    );
  fifo_data_59_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(27),
      I1 => N22,
      I2 => rx_tx_engine_request_id(11),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(59),
      I5 => N0,
      O => N64
    );
  fifo_data_59_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEAAA"
    )
    port map (
      I0 => N64,
      I1 => N11,
      I2 => tx_ext_fifo_back_data(3),
      I3 => adr64_10911,
      I4 => tlp_write_data_z(27),
      I5 => stp_FSM_FFd11_11256,
      O => fifo_data_59_mux0000_11098
    );
  fifo_data_57_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(25),
      I1 => N22,
      I2 => rx_tx_engine_request_id(9),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(57),
      I5 => N0,
      O => N66
    );
  fifo_data_57_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEAAA"
    )
    port map (
      I0 => N66,
      I1 => N11,
      I2 => tx_ext_fifo_back_data(1),
      I3 => adr64_10911,
      I4 => tlp_write_data_z(25),
      I5 => stp_FSM_FFd11_11256,
      O => fifo_data_57_mux0000_11094
    );
  fifo_data_18_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(18),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(10),
      I4 => fifo_data(18),
      I5 => N0,
      O => N68
    );
  fifo_data_18_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(10),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(42),
      I5 => N68,
      O => fifo_data_18_mux0000_10970
    );
  fifo_data_17_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(17),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(9),
      I4 => fifo_data(17),
      I5 => N0,
      O => N70
    );
  fifo_data_17_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(9),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(41),
      I5 => N70,
      O => fifo_data_17_mux0000_10968
    );
  fifo_data_16_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(16),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(8),
      I4 => fifo_data(16),
      I5 => N0,
      O => N72
    );
  fifo_data_16_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(8),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(40),
      I5 => N72,
      O => fifo_data_16_mux0000_10966
    );
  fifo_data_15_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(15),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(23),
      I4 => fifo_data(15),
      I5 => N0,
      O => N74
    );
  fifo_data_15_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(23),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(55),
      I5 => N74,
      O => fifo_data_15_mux0000_10964
    );
  fifo_data_14_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(14),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(22),
      I4 => fifo_data(14),
      I5 => N0,
      O => N76
    );
  fifo_data_14_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(22),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(54),
      I5 => N76,
      O => fifo_data_14_mux0000_10962
    );
  fifo_data_13_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(13),
      I1 => N18,
      I2 => stp_FSM_FFd10_11255,
      I3 => reg_data(21),
      I4 => fifo_data(13),
      I5 => N0,
      O => N78
    );
  fifo_data_13_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(21),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(53),
      I5 => N78,
      O => fifo_data_13_mux0000_10960
    );
  fifo_data_54_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_id(6),
      I1 => stp_FSM_FFd10_11255,
      I2 => rx_tx_engine_request_tc(2),
      I3 => stp_FSM_FFd11_11256,
      I4 => fifo_data(54),
      I5 => N0,
      O => fifo_data_54_mux000010_11087
    );
  fifo_data_53_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_id(5),
      I1 => stp_FSM_FFd10_11255,
      I2 => rx_tx_engine_request_tc(1),
      I3 => stp_FSM_FFd11_11256,
      I4 => fifo_data(53),
      I5 => N0,
      O => fifo_data_53_mux000010_11083
    );
  fifo_data_52_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_id(4),
      I1 => stp_FSM_FFd10_11255,
      I2 => rx_tx_engine_request_tc(0),
      I3 => stp_FSM_FFd11_11256,
      I4 => fifo_data(52),
      I5 => N0,
      O => fifo_data_52_mux000010_11079
    );
  fifo_data_47_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_attr(3),
      I1 => stp_FSM_FFd11_11256,
      I2 => rx_tx_engine_request_tag(7),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(47),
      I5 => N0,
      O => fifo_data_47_mux000010_11065
    );
  fifo_data_46_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_attr(2),
      I1 => stp_FSM_FFd11_11256,
      I2 => rx_tx_engine_request_tag(6),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(46),
      I5 => N0,
      O => fifo_data_46_mux000010_11061
    );
  fifo_data_45_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_attr(1),
      I1 => stp_FSM_FFd11_11256,
      I2 => rx_tx_engine_request_tag(5),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(45),
      I5 => N0,
      O => fifo_data_45_mux000010_11057
    );
  fifo_data_44_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => rx_tx_engine_request_attr(0),
      I1 => stp_FSM_FFd11_11256,
      I2 => rx_tx_engine_request_tag(4),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(44),
      I5 => N0,
      O => fifo_data_44_mux000010_11053
    );
  fifo_data_12_mux000010 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => req_cnt(4),
      I1 => N20,
      I2 => reg_data(20),
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_data(12),
      I5 => N0,
      O => fifo_data_12_mux000010_10958
    );
  fifo_data_7_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => req_cnt(0),
      I1 => stp_FSM_FFd7_11283,
      I2 => reg_data(31),
      I3 => stp_FSM_FFd10_11255,
      O => fifo_data_7_mux00004_11115
    );
  fifo_data_9_mux000015 : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => fifo_data(9),
      I1 => N0,
      I2 => fifo_data_9_mux00004_11124,
      I3 => stp_FSM_FFd7_11283,
      I4 => tlp_read_dw3(9),
      O => fifo_data_9_mux000015_11122
    );
  fifo_data_11_mux000015 : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => fifo_data(11),
      I1 => N0,
      I2 => fifo_data_11_mux00004_10955,
      I3 => stp_FSM_FFd7_11283,
      I4 => tlp_read_dw3(11),
      O => fifo_data_11_mux000015_10953
    );
  fifo_data_10_mux000015 : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => fifo_data(10),
      I1 => N0,
      I2 => fifo_data_10_mux00004_10950,
      I3 => stp_FSM_FFd7_11283,
      I4 => tlp_read_dw3(10),
      O => fifo_data_10_mux000015_10948
    );
  Mcount_complete_cnt_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(1),
      O => Mcount_complete_cnt_cy_1_rt_10744
    );
  Mcount_complete_cnt_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(2),
      O => Mcount_complete_cnt_cy_2_rt_10746
    );
  Mcount_complete_cnt_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(3),
      O => Mcount_complete_cnt_cy_3_rt_10748
    );
  Mcount_complete_cnt_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(4),
      O => Mcount_complete_cnt_cy_4_rt_10750
    );
  Mcount_complete_cnt_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(5),
      O => Mcount_complete_cnt_cy_5_rt_10752
    );
  Mcount_complete_cnt_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(6),
      O => Mcount_complete_cnt_cy_6_rt_10754
    );
  Mcount_complete_cnt_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(7),
      O => Mcount_complete_cnt_cy_7_rt_10756
    );
  Mcount_complete_cnt_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(8),
      O => Mcount_complete_cnt_cy_8_rt_10758
    );
  Mcount_timeout_cnt_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(1),
      O => Mcount_timeout_cnt_cy_1_rt_10764
    );
  Mcount_timeout_cnt_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(2),
      O => Mcount_timeout_cnt_cy_2_rt_10766
    );
  Mcount_timeout_cnt_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(3),
      O => Mcount_timeout_cnt_cy_3_rt_10768
    );
  Mcount_timeout_cnt_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(4),
      O => Mcount_timeout_cnt_cy_4_rt_10770
    );
  Mcount_timeout_cnt_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(5),
      O => Mcount_timeout_cnt_cy_5_rt_10772
    );
  Mcount_timeout_cnt_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(6),
      O => Mcount_timeout_cnt_cy_6_rt_10774
    );
  Mcount_timeout_cnt_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(7),
      O => Mcount_timeout_cnt_cy_7_rt_10776
    );
  Mcount_timeout_cnt_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(8),
      O => Mcount_timeout_cnt_cy_8_rt_10778
    );
  Mcount_timeout_cnt_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(9),
      O => Mcount_timeout_cnt_cy_9_rt_10780
    );
  Mcount_complete_cnt_xor_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => complete_cnt(9),
      O => Mcount_complete_cnt_xor_9_rt_10761
    );
  Mcount_timeout_cnt_xor_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => timeout_cnt(10),
      O => Mcount_timeout_cnt_xor_10_rt_10782
    );
  fifo_wr_mux000028 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => N16,
      I1 => stp_FSM_FFd7_11283,
      I2 => stp_FSM_FFd3_11277,
      I3 => stp_FSM_FFd10_11255,
      I4 => fifo_wr_mux000023_11137,
      O => fifo_wr_mux0000
    );
  stp_FSM_FFd16_In42 : LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      I0 => stp_FSM_FFd16_In29_11273,
      I1 => rx_tx_engine_request_reg_wr,
      I2 => stp_FSM_FFd12_11258,
      I3 => rx_tx_engine_request_reg_rd,
      O => stp_FSM_FFd16_In42_11274
    );
  fifo_data_31_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(31),
      I1 => N0,
      I2 => reg_data(7),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(15),
      I5 => N16,
      O => fifo_data_31_mux00009_11016
    );
  fifo_data_30_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(30),
      I1 => N0,
      I2 => reg_data(6),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(14),
      I5 => N16,
      O => fifo_data_30_mux00009_11013
    );
  fifo_data_29_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(29),
      I1 => N0,
      I2 => reg_data(5),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(13),
      I5 => N16,
      O => fifo_data_29_mux00009_11005
    );
  fifo_data_28_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(28),
      I1 => N0,
      I2 => reg_data(4),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(12),
      I5 => N16,
      O => fifo_data_28_mux00009_11002
    );
  fifo_data_27_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(27),
      I1 => N0,
      I2 => reg_data(3),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(11),
      I5 => N16,
      O => fifo_data_27_mux00009_10999
    );
  fifo_data_26_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(26),
      I1 => N0,
      I2 => reg_data(2),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(10),
      I5 => N16,
      O => fifo_data_26_mux00009_10996
    );
  fifo_data_25_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(25),
      I1 => N0,
      I2 => reg_data(1),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(9),
      I5 => N16,
      O => fifo_data_25_mux00009_10993
    );
  fifo_data_24_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(24),
      I1 => N0,
      I2 => reg_data(0),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(8),
      I5 => N16,
      O => fifo_data_24_mux00009_10990
    );
  fifo_data_23_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(23),
      I1 => N0,
      I2 => reg_data(15),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(7),
      I5 => N16,
      O => fifo_data_23_mux00009_10987
    );
  fifo_data_22_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(22),
      I1 => N0,
      I2 => reg_data(14),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(6),
      I5 => N16,
      O => fifo_data_22_mux00009_10984
    );
  fifo_data_21_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(21),
      I1 => N0,
      I2 => reg_data(13),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(5),
      I5 => N16,
      O => fifo_data_21_mux00009_10981
    );
  fifo_data_20_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(20),
      I1 => N0,
      I2 => reg_data(12),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(4),
      I5 => N16,
      O => fifo_data_20_mux00009_10978
    );
  fifo_data_19_mux00009 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => fifo_data(19),
      I1 => N0,
      I2 => reg_data(11),
      I3 => stp_FSM_FFd10_11255,
      I4 => completer_id(3),
      I5 => N16,
      O => fifo_data_19_mux00009_10973
    );
  fifo_data_37_mux000025_SW0 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => stp_FSM_FFd5_11280,
      I1 => trn_tx_back_cfg_dcommand(5),
      I2 => tx_ext_fifo_back_pci_adr(37),
      I3 => stp_FSM_FFd4_11279,
      I4 => stp_FSM_FFd7_11283,
      O => N80
    );
  fifo_data_37_mux000025 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => N0,
      I1 => fifo_data(37),
      I2 => rx_tx_engine_lower_adr(5),
      I3 => stp_FSM_FFd10_11255,
      I4 => stp_FSM_FFd8_11284,
      I5 => N80,
      O => fifo_data_37_mux000025_11029
    );
  fifo_data_43_mux000039_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => N11,
      I1 => tlp_write_data_z(11),
      I2 => stp_FSM_FFd4_11279,
      I3 => NlwRenamedSig_OI_write_cnt_pkg(4),
      I4 => stp_FSM_FFd7_11283,
      I5 => tlp_read_dw3(11),
      O => N82
    );
  fifo_data_43_mux000039 : LUT6
    generic map(
      INIT => X"FFFFDD88FFFFD580"
    )
    port map (
      I0 => adr64_10911,
      I1 => tx_ext_fifo_back_data(19),
      I2 => stp_FSM_FFd2_11275,
      I3 => N82,
      I4 => fifo_data_43_mux00004_11050,
      I5 => stp_FSM_FFd3_11277,
      O => fifo_data_43_mux0000
    );
  fifo_data_42_mux000039_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => N11,
      I1 => tlp_write_data_z(10),
      I2 => stp_FSM_FFd4_11279,
      I3 => NlwRenamedSig_OI_write_cnt_pkg(3),
      I4 => stp_FSM_FFd7_11283,
      I5 => tlp_read_dw3(10),
      O => N84
    );
  fifo_data_42_mux000039 : LUT6
    generic map(
      INIT => X"FFFFDD88FFFFD580"
    )
    port map (
      I0 => adr64_10911,
      I1 => tx_ext_fifo_back_data(18),
      I2 => stp_FSM_FFd2_11275,
      I3 => N84,
      I4 => fifo_data_42_mux00004_11047,
      I5 => stp_FSM_FFd3_11277,
      O => fifo_data_42_mux0000
    );
  fifo_data_41_mux000039_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => N11,
      I1 => tlp_write_data_z(9),
      I2 => stp_FSM_FFd4_11279,
      I3 => NlwRenamedSig_OI_write_cnt_pkg(2),
      I4 => stp_FSM_FFd7_11283,
      I5 => tlp_read_dw3(9),
      O => N86
    );
  fifo_data_41_mux000039 : LUT6
    generic map(
      INIT => X"FFFFDD88FFFFD580"
    )
    port map (
      I0 => adr64_10911,
      I1 => tx_ext_fifo_back_data(17),
      I2 => stp_FSM_FFd2_11275,
      I3 => N86,
      I4 => fifo_data_41_mux00004_11044,
      I5 => stp_FSM_FFd3_11277,
      O => fifo_data_41_mux0000
    );
  fifo_data_62_mux000034_SW0 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => N0,
      I1 => fifo_data(62),
      I2 => rx_tx_engine_request_id(14),
      I3 => stp_FSM_FFd10_11255,
      I4 => rx_tx_engine_request_reg_rd,
      I5 => stp_FSM_FFd11_11256,
      O => N88
    );
  fifo_data_62_mux000034 : LUT6
    generic map(
      INIT => X"FFFFFFFFEAEEEAAA"
    )
    port map (
      I0 => N88,
      I1 => N11,
      I2 => tx_ext_fifo_back_data(6),
      I3 => adr64_10911,
      I4 => tlp_write_data_z(30),
      I5 => stp_FSM_FFd5_11280,
      O => fifo_data_62_mux000034_11107
    );
  fifo_data_8_mux000016_SW0 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => req_cnt(0),
      I1 => stp_FSM_FFd5_11280,
      I2 => stp_FSM_FFd8_11284,
      I3 => stp_FSM_FFd7_11283,
      I4 => req_cnt(1),
      O => N90
    );
  fifo_data_8_mux000016 : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => N0,
      I1 => fifo_data(8),
      I2 => N90,
      I3 => reg_data(16),
      I4 => stp_FSM_FFd10_11255,
      O => fifo_data_8_mux000016_11118
    );
  fifo_data_6_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(30),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(62),
      I5 => N34,
      O => fifo_data_6_mux0000_11110
    );
  fifo_data_5_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(29),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(61),
      I5 => N36,
      O => fifo_data_5_mux0000_11099
    );
  fifo_data_4_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(28),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(60),
      I5 => N38,
      O => fifo_data_4_mux0000_11071
    );
  fifo_data_3_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(27),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(59),
      I5 => N40,
      O => fifo_data_3_mux0000_11036
    );
  fifo_data_1_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(25),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(57),
      I5 => N42,
      O => fifo_data_1_mux0000_10974
    );
  fifo_data_0_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(24),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(56),
      I5 => N44,
      O => fifo_data_0_mux0000_10944
    );
  fifo_data_2_mux000032 : LUT6
    generic map(
      INIT => X"FFFFFFFFACA80C08"
    )
    port map (
      I0 => N11,
      I1 => tx_ext_fifo_back_data(26),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => tx_ext_fifo_back_data(58),
      I5 => fifo_data_2_mux000013,
      O => fifo_data_2_mux0000
    );
  fifo_data_7_mux000040 : LUT6
    generic map(
      INIT => X"FEFEFEEEBABABAAA"
    )
    port map (
      I0 => fifo_data_7_mux000012_11113,
      I1 => adr64_10911,
      I2 => tx_ext_fifo_back_data(31),
      I3 => N11,
      I4 => stp_FSM_FFd4_11279,
      I5 => fifo_data_7_mux000019_11114,
      O => fifo_data_7_mux0000
    );
  fifo_data_8_mux000043 : LUT6
    generic map(
      INIT => X"FEFEFEEEBABABAAA"
    )
    port map (
      I0 => fifo_data_8_mux000016_11118,
      I1 => adr64_10911,
      I2 => tx_ext_fifo_back_data(16),
      I3 => N11,
      I4 => stp_FSM_FFd4_11279,
      I5 => fifo_data_8_mux000022_11119,
      O => fifo_data_8_mux0000
    );
  fifo_rd1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => fifo_empty,
      I1 => trn_tx_back_trn_tdst_rdy_n,
      O => fifo_rd
    );
  fifo_eof_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => N20,
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_eof_11126,
      I3 => N0,
      I4 => stp_FSM_FFd4_11279,
      I5 => stp_FSM_FFd11_11256,
      O => fifo_eof_mux0000
    );
  fifo_data_33_mux0000_SW0 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(33),
      I1 => stp_FSM_FFd7_11283,
      I2 => stp_FSM_FFd4_11279,
      I3 => fifo_data(33),
      I4 => N0,
      O => N121
    );
  fifo_data_33_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(1),
      I3 => N121,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(25),
      O => fifo_data_33_mux0000_11020
    );
  fifo_rrem_mux0000_SW0 : LUT6
    generic map(
      INIT => X"CCCCCCCCCCCCCCC8"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => fifo_rrem_11130,
      I2 => stp_FSM_FFd3_11277,
      I3 => stp_FSM_FFd7_11283,
      I4 => stp_FSM_FFd4_11279,
      I5 => N0,
      O => N161
    );
  fifo_data_36_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(4),
      I3 => N181,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(28),
      O => fifo_data_36_mux0000_11026
    );
  fifo_data_35_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(3),
      I3 => N201,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(27),
      O => fifo_data_35_mux0000_11024
    );
  fifo_data_34_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(2),
      I3 => N222,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(26),
      O => fifo_data_34_mux0000_11022
    );
  fifo_data_32_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(0),
      I3 => N24,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(24),
      O => fifo_data_32_mux0000_11018
    );
  fifo_data_38_mux000011 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(38),
      I1 => stp_FSM_FFd7_11283,
      I2 => stp_FSM_FFd4_11279,
      O => fifo_data_38_mux000011_11033
    );
  fifo_data_37_mux000048 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(5),
      I3 => fifo_data_37_mux000025_11029,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(29),
      O => fifo_data_37_mux0000
    );
  fifo_data_62_mux000011 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => stp_FSM_FFd7_11283,
      I1 => adr64_10911,
      I2 => stp_FSM_FFd4_11279,
      O => N22
    );
  fifo_data_61_mux0000_SW1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => rx_tx_engine_request_id(13),
      I1 => stp_FSM_FFd10_11255,
      I2 => fifo_data(61),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N27
    );
  fifo_data_40_mux000038 : LUT6
    generic map(
      INIT => X"FFFFDD88FFFFD580"
    )
    port map (
      I0 => adr64_10911,
      I1 => tx_ext_fifo_back_data(16),
      I2 => stp_FSM_FFd3_11277,
      I3 => fifo_data_40_mux000024_11040,
      I4 => fifo_data_40_mux00004_11041,
      I5 => stp_FSM_FFd2_11275,
      O => fifo_data_40_mux0000
    );
  fifo_data_6_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(30),
      I2 => fifo_data(6),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N34
    );
  fifo_data_5_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(29),
      I2 => fifo_data(5),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N36
    );
  fifo_data_4_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(28),
      I2 => fifo_data(4),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N38
    );
  fifo_data_3_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(27),
      I2 => fifo_data(3),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N40
    );
  fifo_data_1_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(25),
      I2 => fifo_data(1),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N42
    );
  fifo_data_0_mux0000_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => stp_FSM_FFd10_11255,
      I1 => reg_data(24),
      I2 => fifo_data(0),
      I3 => N0,
      I4 => stp_FSM_FFd8_11284,
      I5 => stp_FSM_FFd5_11280,
      O => N44
    );
  fifo_data_63_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(31),
      I3 => N46,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(7),
      O => fifo_data_63_mux0000_11109
    );
  fifo_data_60_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(28),
      I3 => N48,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(4),
      O => fifo_data_60_mux0000_11102
    );
  fifo_data_58_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(26),
      I3 => N50,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(2),
      O => fifo_data_58_mux0000_11096
    );
  fifo_data_56_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(24),
      I3 => N52,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(0),
      O => fifo_data_56_mux0000_11092
    );
  fifo_data_55_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(23),
      I3 => N54,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(15),
      O => fifo_data_55_mux0000_11090
    );
  fifo_data_51_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(19),
      I3 => N56,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(11),
      O => fifo_data_51_mux0000_11076
    );
  fifo_data_50_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(18),
      I3 => N58,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(10),
      O => fifo_data_50_mux0000_11074
    );
  fifo_data_49_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(17),
      I3 => N60,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(9),
      O => fifo_data_49_mux0000_11070
    );
  fifo_data_48_mux0000 : LUT6
    generic map(
      INIT => X"FFFCFFA8FF30FF20"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(16),
      I3 => N62,
      I4 => stp_FSM_FFd3_11277,
      I5 => tx_ext_fifo_back_data(8),
      O => fifo_data_48_mux0000_11068
    );
  fifo_data_54_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(22),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(14),
      O => fifo_data_54_mux000023_11088
    );
  fifo_data_53_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(21),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(13),
      O => fifo_data_53_mux000023_11084
    );
  fifo_data_52_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(20),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(12),
      O => fifo_data_52_mux000023_11080
    );
  fifo_data_47_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(15),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(23),
      O => fifo_data_47_mux000023_11066
    );
  fifo_data_46_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(14),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(22),
      O => fifo_data_46_mux000023_11062
    );
  fifo_data_45_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(13),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(21),
      O => fifo_data_45_mux000023_11058
    );
  fifo_data_44_mux000023 : LUT5
    generic map(
      INIT => X"FCA83020"
    )
    port map (
      I0 => stp_FSM_FFd2_11275,
      I1 => adr64_10911,
      I2 => tlp_write_data_z(12),
      I3 => stp_FSM_FFd3_11277,
      I4 => tx_ext_fifo_back_data(20),
      O => fifo_data_44_mux000023_11054
    );
  fifo_data_7_mux000012 : LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
    port map (
      I0 => stp_FSM_FFd8_11284,
      I1 => stp_FSM_FFd5_11280,
      I2 => fifo_data(7),
      I3 => N0,
      I4 => fifo_data_7_mux00004_11115,
      O => fifo_data_7_mux000012_11113
    );
  fifo_data_9_mux00004 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => req_cnt(1),
      I1 => stp_FSM_FFd8_11284,
      I2 => stp_FSM_FFd5_11280,
      I3 => reg_data(17),
      I4 => stp_FSM_FFd10_11255,
      O => fifo_data_9_mux00004_11124
    );
  fifo_data_9_mux000027 : LUT6
    generic map(
      INIT => X"AAAAA080A080A080"
    )
    port map (
      I0 => adr64_10911,
      I1 => stp_FSM_FFd3_11277,
      I2 => tx_ext_fifo_back_data(49),
      I3 => stp_FSM_FFd2_11275,
      I4 => NlwRenamedSig_OI_write_cnt_pkg(2),
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_9_mux000027_11123
    );
  fifo_data_9_mux000042 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_data(17),
      I1 => adr64_10911,
      I2 => N11,
      I3 => fifo_data_9_mux000027_11123,
      I4 => fifo_data_9_mux000015_11122,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_9_mux0000
    );
  fifo_data_11_mux00004 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => req_cnt(3),
      I1 => stp_FSM_FFd8_11284,
      I2 => stp_FSM_FFd5_11280,
      I3 => reg_data(19),
      I4 => stp_FSM_FFd10_11255,
      O => fifo_data_11_mux00004_10955
    );
  fifo_data_11_mux000027 : LUT6
    generic map(
      INIT => X"AAAAA080A080A080"
    )
    port map (
      I0 => adr64_10911,
      I1 => stp_FSM_FFd3_11277,
      I2 => tx_ext_fifo_back_data(51),
      I3 => stp_FSM_FFd2_11275,
      I4 => NlwRenamedSig_OI_write_cnt_pkg(4),
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_11_mux000027_10954
    );
  fifo_data_11_mux000042 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_data(19),
      I1 => adr64_10911,
      I2 => N11,
      I3 => fifo_data_11_mux000027_10954,
      I4 => fifo_data_11_mux000015_10953,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_11_mux0000
    );
  fifo_data_10_mux00004 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => req_cnt(2),
      I1 => stp_FSM_FFd8_11284,
      I2 => stp_FSM_FFd5_11280,
      I3 => reg_data(18),
      I4 => stp_FSM_FFd10_11255,
      O => fifo_data_10_mux00004_10950
    );
  fifo_data_10_mux000027 : LUT6
    generic map(
      INIT => X"AAAAA080A080A080"
    )
    port map (
      I0 => adr64_10911,
      I1 => stp_FSM_FFd3_11277,
      I2 => tx_ext_fifo_back_data(50),
      I3 => stp_FSM_FFd2_11275,
      I4 => NlwRenamedSig_OI_write_cnt_pkg(3),
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_10_mux000027_10949
    );
  fifo_data_10_mux000042 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_data(18),
      I1 => adr64_10911,
      I2 => N11,
      I3 => fifo_data_10_mux000027_10949,
      I4 => fifo_data_10_mux000015_10948,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_10_mux0000
    );
  fifo_data_16_mux000031 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd8_11284,
      I1 => stp_FSM_FFd5_11280,
      I2 => stp_FSM_FFd11_11256,
      O => N16
    );
  fifo_data_54_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(22),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_54_mux000023_11088,
      I4 => fifo_data_54_mux000010_11087,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_54_mux0000
    );
  fifo_data_53_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(21),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_53_mux000023_11084,
      I4 => fifo_data_53_mux000010_11083,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_53_mux0000
    );
  fifo_data_52_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(20),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_52_mux000023_11080,
      I4 => fifo_data_52_mux000010_11079,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_52_mux0000
    );
  fifo_data_47_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(15),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_47_mux000023_11066,
      I4 => fifo_data_47_mux000010_11065,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_47_mux0000
    );
  fifo_data_46_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(14),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_46_mux000023_11062,
      I4 => fifo_data_46_mux000010_11061,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_46_mux0000
    );
  fifo_data_45_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(13),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_45_mux000023_11058,
      I4 => fifo_data_45_mux000010_11057,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_45_mux0000
    );
  fifo_data_44_mux000038 : LUT6
    generic map(
      INIT => X"FFFFFF22FFFFFF20"
    )
    port map (
      I0 => tx_ext_fifo_back_pci_adr(12),
      I1 => adr64_10911,
      I2 => stp_FSM_FFd7_11283,
      I3 => fifo_data_44_mux000023_11054,
      I4 => fifo_data_44_mux000010_11053,
      I5 => stp_FSM_FFd4_11279,
      O => fifo_data_44_mux0000
    );
  fifo_data_62_mux000042 : LUT5
    generic map(
      INIT => X"FFFF0C08"
    )
    port map (
      I0 => stp_FSM_FFd7_11283,
      I1 => tx_ext_fifo_back_pci_adr(30),
      I2 => adr64_10911,
      I3 => stp_FSM_FFd4_11279,
      I4 => fifo_data_62_mux000034_11107,
      O => fifo_data_62_mux0000
    );
  fifo_data_7_mux000019 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(63),
      I1 => stp_FSM_FFd3_11277,
      I2 => stp_FSM_FFd2_11275,
      I3 => stp_FSM_FFd4_11279,
      I4 => write_cnt_pkg(0),
      O => fifo_data_7_mux000019_11114
    );
  fifo_data_8_mux000022 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(48),
      I1 => stp_FSM_FFd3_11277,
      I2 => stp_FSM_FFd2_11275,
      I3 => stp_FSM_FFd4_11279,
      I4 => NlwRenamedSig_OI_write_cnt_pkg(1),
      O => fifo_data_8_mux000022_11119
    );
  fifo_data_31_mux000051 : MUXF7
    port map (
      I0 => N92,
      I1 => N93,
      S => adr64_10911,
      O => fifo_data_31_mux0000
    );
  fifo_data_31_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(7),
      I1 => N11,
      I2 => fifo_data_31_mux00009_11016,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(31),
      I5 => stp_FSM_FFd4_11279,
      O => N92
    );
  fifo_data_31_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(39),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_31_mux00009_11016,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(31),
      I5 => stp_FSM_FFd2_11275,
      O => N93
    );
  fifo_data_30_mux000051 : MUXF7
    port map (
      I0 => N94,
      I1 => N95,
      S => adr64_10911,
      O => fifo_data_30_mux0000
    );
  fifo_data_30_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(6),
      I1 => N11,
      I2 => fifo_data_30_mux00009_11013,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(30),
      I5 => stp_FSM_FFd4_11279,
      O => N94
    );
  fifo_data_30_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(38),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_30_mux00009_11013,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(30),
      I5 => stp_FSM_FFd2_11275,
      O => N95
    );
  fifo_data_29_mux000051 : MUXF7
    port map (
      I0 => N96,
      I1 => N97,
      S => adr64_10911,
      O => fifo_data_29_mux0000
    );
  fifo_data_29_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(5),
      I1 => N11,
      I2 => fifo_data_29_mux00009_11005,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(29),
      I5 => stp_FSM_FFd4_11279,
      O => N96
    );
  fifo_data_29_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(37),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_29_mux00009_11005,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(29),
      I5 => stp_FSM_FFd2_11275,
      O => N97
    );
  fifo_data_28_mux000051 : MUXF7
    port map (
      I0 => N98,
      I1 => N99,
      S => adr64_10911,
      O => fifo_data_28_mux0000
    );
  fifo_data_28_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(4),
      I1 => N11,
      I2 => fifo_data_28_mux00009_11002,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(28),
      I5 => stp_FSM_FFd4_11279,
      O => N98
    );
  fifo_data_28_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(36),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_28_mux00009_11002,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(28),
      I5 => stp_FSM_FFd2_11275,
      O => N99
    );
  fifo_data_27_mux000051 : MUXF7
    port map (
      I0 => N100,
      I1 => N101,
      S => adr64_10911,
      O => fifo_data_27_mux0000
    );
  fifo_data_27_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(3),
      I1 => N11,
      I2 => fifo_data_27_mux00009_10999,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(27),
      I5 => stp_FSM_FFd4_11279,
      O => N100
    );
  fifo_data_27_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(35),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_27_mux00009_10999,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(27),
      I5 => stp_FSM_FFd2_11275,
      O => N101
    );
  fifo_data_26_mux000051 : MUXF7
    port map (
      I0 => N102,
      I1 => N103,
      S => adr64_10911,
      O => fifo_data_26_mux0000
    );
  fifo_data_26_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(2),
      I1 => N11,
      I2 => fifo_data_26_mux00009_10996,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(26),
      I5 => stp_FSM_FFd4_11279,
      O => N102
    );
  fifo_data_26_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(34),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_26_mux00009_10996,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(26),
      I5 => stp_FSM_FFd2_11275,
      O => N103
    );
  fifo_data_25_mux000051 : MUXF7
    port map (
      I0 => N104,
      I1 => N105,
      S => adr64_10911,
      O => fifo_data_25_mux0000
    );
  fifo_data_25_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(1),
      I1 => N11,
      I2 => fifo_data_25_mux00009_10993,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(25),
      I5 => stp_FSM_FFd4_11279,
      O => N104
    );
  fifo_data_25_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(33),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_25_mux00009_10993,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(25),
      I5 => stp_FSM_FFd2_11275,
      O => N105
    );
  fifo_data_24_mux000051 : MUXF7
    port map (
      I0 => N106,
      I1 => N107,
      S => adr64_10911,
      O => fifo_data_24_mux0000
    );
  fifo_data_24_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(0),
      I1 => N11,
      I2 => fifo_data_24_mux00009_10990,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(24),
      I5 => stp_FSM_FFd4_11279,
      O => N106
    );
  fifo_data_24_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(32),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_24_mux00009_10990,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(24),
      I5 => stp_FSM_FFd2_11275,
      O => N107
    );
  fifo_data_23_mux000051 : MUXF7
    port map (
      I0 => N108,
      I1 => N109,
      S => adr64_10911,
      O => fifo_data_23_mux0000
    );
  fifo_data_23_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(15),
      I1 => N11,
      I2 => fifo_data_23_mux00009_10987,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(23),
      I5 => stp_FSM_FFd4_11279,
      O => N108
    );
  fifo_data_23_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(47),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_23_mux00009_10987,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(23),
      I5 => stp_FSM_FFd2_11275,
      O => N109
    );
  fifo_data_22_mux000051 : MUXF7
    port map (
      I0 => N110,
      I1 => N111,
      S => adr64_10911,
      O => fifo_data_22_mux0000
    );
  fifo_data_22_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(14),
      I1 => N11,
      I2 => fifo_data_22_mux00009_10984,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(22),
      I5 => stp_FSM_FFd4_11279,
      O => N110
    );
  fifo_data_22_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(46),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_22_mux00009_10984,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(22),
      I5 => stp_FSM_FFd2_11275,
      O => N111
    );
  fifo_data_21_mux000051 : MUXF7
    port map (
      I0 => N112,
      I1 => N113,
      S => adr64_10911,
      O => fifo_data_21_mux0000
    );
  fifo_data_21_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(13),
      I1 => N11,
      I2 => fifo_data_21_mux00009_10981,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(21),
      I5 => stp_FSM_FFd4_11279,
      O => N112
    );
  fifo_data_21_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(45),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_21_mux00009_10981,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(21),
      I5 => stp_FSM_FFd2_11275,
      O => N113
    );
  fifo_data_20_mux000051 : MUXF7
    port map (
      I0 => N114,
      I1 => N115,
      S => adr64_10911,
      O => fifo_data_20_mux0000
    );
  fifo_data_20_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(12),
      I1 => N11,
      I2 => fifo_data_20_mux00009_10978,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(20),
      I5 => stp_FSM_FFd4_11279,
      O => N114
    );
  fifo_data_20_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(44),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_20_mux00009_10978,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(20),
      I5 => stp_FSM_FFd2_11275,
      O => N115
    );
  fifo_data_19_mux000051 : MUXF7
    port map (
      I0 => N116,
      I1 => N117,
      S => adr64_10911,
      O => fifo_data_19_mux0000
    );
  fifo_data_19_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(11),
      I1 => N11,
      I2 => fifo_data_19_mux00009_10973,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(19),
      I5 => stp_FSM_FFd4_11279,
      O => N116
    );
  fifo_data_19_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(43),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_19_mux00009_10973,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(19),
      I5 => stp_FSM_FFd2_11275,
      O => N117
    );
  fifo_data_12_mux000051 : MUXF7
    port map (
      I0 => N118,
      I1 => N119,
      S => adr64_10911,
      O => fifo_data_12_mux0000
    );
  fifo_data_12_mux000051_F : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(20),
      I1 => N11,
      I2 => fifo_data_12_mux000010_10958,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(12),
      I5 => stp_FSM_FFd4_11279,
      O => N118
    );
  fifo_data_12_mux000051_G : LUT6
    generic map(
      INIT => X"FFFAFAFAFFF8F8F8"
    )
    port map (
      I0 => tx_ext_fifo_back_data(52),
      I1 => stp_FSM_FFd3_11277,
      I2 => fifo_data_12_mux000010_10958,
      I3 => N18,
      I4 => tx_ext_fifo_back_pci_adr(12),
      I5 => stp_FSM_FFd2_11275,
      O => N119
    );
  Mcount_complete_cnt_lut_0_INV_0 : INV
    port map (
      I => complete_cnt(0),
      O => Mcount_complete_cnt_lut(0)
    );
  Mcount_timeout_cnt_lut_0_INV_0 : INV
    port map (
      I => timeout_cnt(0),
      O => Mcount_timeout_cnt_lut(0)
    );
  Mcount_req_cnt_xor_0_11_INV_0 : INV
    port map (
      I => req_cnt(0),
      O => Result_0_1
    );
  Mcount_adr_cnt_xor_0_11_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_adr_cnt(0),
      O => Result_0_Q
    );
  write_cnt_en_inv1_INV_0 : INV
    port map (
      I => write_cnt_en_11525,
      O => write_cnt_en_inv
    );
  Mcount_complete_cnt_val1_INV_0 : INV
    port map (
      I => wait_complete_11517,
      O => Mcount_complete_cnt_val
    );
  stp_FSM_FFd15_In1 : LUT6
    generic map(
      INIT => X"22202220FFFF2220"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => fifo_paf,
      I2 => rx_tx_engine_request_reg_rd,
      I3 => rx_tx_engine_request_reg_wr,
      I4 => stp_FSM_FFd15_11265,
      I5 => reg_access_back_complete,
      O => stp_FSM_FFd15_In1_11267
    );
  stp_FSM_FFd15_In2 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => reg_access_back_complete,
      I1 => stp_FSM_FFd15_11265,
      O => stp_FSM_FFd15_In2_11268
    );
  stp_FSM_FFd15_In_f7 : MUXF7
    port map (
      I0 => stp_FSM_FFd15_In2_11268,
      I1 => stp_FSM_FFd15_In1_11267,
      S => trn_tx_back_trn_tbuf_av(2),
      O => stp_FSM_FFd15_In
    );
  stp_FSM_FFd13_In1 : LUT6
    generic map(
      INIT => X"0000008000008080"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => N14,
      I2 => trn_tx_back_trn_tbuf_av(1),
      I3 => trn_tx_back_trn_tbuf_av(0),
      I4 => fifo_paf,
      I5 => tx_ext_fifo_back_req_rd,
      O => stp_FSM_FFd13_In1_11262
    );
  stp_FSM_FFd13_In_f7 : MUXF7
    port map (
      I0 => NlwRenamedSig_OI_trn_tx_trn_trem_n(4),
      I1 => stp_FSM_FFd13_In1_11262,
      S => tx_ext_fifo_back_req_wr,
      O => stp_FSM_FFd13_In
    );
  Mcount_write_cnt_xor_4_11 : LUT6
    generic map(
      INIT => X"1555BFFF5555FFFF"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(3),
      I2 => write_cnt(0),
      I3 => write_cnt(2),
      I4 => trn_tx_back_cfg_dcommand(5),
      I5 => write_cnt(1),
      O => Mcount_write_cnt_xor_4_1
    );
  Mcount_write_cnt_xor_4_12 : LUT6
    generic map(
      INIT => X"7222222222222222"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => trn_tx_back_cfg_dcommand(5),
      I2 => write_cnt(3),
      I3 => write_cnt(1),
      I4 => write_cnt(0),
      I5 => write_cnt(2),
      O => Mcount_write_cnt_xor_4_11_10790
    );
  Mcount_write_cnt_xor_4_1_f7 : MUXF7
    port map (
      I0 => Mcount_write_cnt_xor_4_11_10790,
      I1 => Mcount_write_cnt_xor_4_1,
      S => write_cnt(4),
      O => Mcount_write_cnt4
    );
  Mcount_write_cnt_xor_5_11 : LUT6
    generic map(
      INIT => X"1555555555555555"
    )
    port map (
      I0 => stp_FSM_FFd16_11269,
      I1 => write_cnt(4),
      I2 => write_cnt(3),
      I3 => write_cnt(2),
      I4 => write_cnt(1),
      I5 => write_cnt(0),
      O => Mcount_write_cnt_xor_5_1
    );
  Mcount_write_cnt_xor_5_12 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => write_cnt(2),
      I1 => write_cnt(3),
      I2 => write_cnt(4),
      I3 => stp_FSM_FFd16_11269,
      I4 => write_cnt(1),
      I5 => write_cnt(0),
      O => Mcount_write_cnt_xor_5_11_10792
    );
  Mcount_write_cnt_xor_5_1_f7 : MUXF7
    port map (
      I0 => Mcount_write_cnt_xor_5_11_10792,
      I1 => Mcount_write_cnt_xor_5_1,
      S => write_cnt(5),
      O => Mcount_write_cnt5
    );
  fifo_data_2_mux0000131 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFF888"
    )
    port map (
      I0 => fifo_data(2),
      I1 => N0,
      I2 => reg_data(26),
      I3 => stp_FSM_FFd10_11255,
      I4 => rx_tx_engine_request_reg_rd,
      I5 => N20,
      O => fifo_data_2_mux0000131_11008
    );
  fifo_data_2_mux0000132 : LUT5
    generic map(
      INIT => X"FFF8F8F8"
    )
    port map (
      I0 => fifo_data(2),
      I1 => N0,
      I2 => N20,
      I3 => reg_data(26),
      I4 => stp_FSM_FFd10_11255,
      O => fifo_data_2_mux0000132_11009
    );
  fifo_data_2_mux000013_f7 : MUXF7
    port map (
      I0 => fifo_data_2_mux0000132_11009,
      I1 => fifo_data_2_mux0000131_11008,
      S => stp_FSM_FFd11_11256,
      O => fifo_data_2_mux000013
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_rx_engine is
  port (
    trn_rx_trn_rerrfwd_n : in STD_LOGIC := 'X'; 
    rx_tx_engine_complete_we : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    tx_rx_engine_complete_reg : in STD_LOGIC := 'X'; 
    trn_rx_trn_rsrc_dsc_n : in STD_LOGIC := 'X'; 
    rx_tx_engine_request_reg_wr : out STD_LOGIC; 
    trn_rx_trn_rsof_n : in STD_LOGIC := 'X'; 
    rstp : in STD_LOGIC := 'X'; 
    trn_rx_trn_rsrc_rdy_n : in STD_LOGIC := 'X'; 
    rx_ext_fifo_data_we : out STD_LOGIC; 
    trn_rx_back_trn_rnp_ok_n : out STD_LOGIC; 
    trn_rx_back_trn_rdst_rdy_n : out STD_LOGIC; 
    trn_rx_back_trn_rcpl_streaming_n : out STD_LOGIC; 
    trn_rx_trn_reof_n : in STD_LOGIC := 'X'; 
    rx_tx_engine_request_reg_rd : out STD_LOGIC; 
    reg_access_req_rd : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_access_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_access_req_wr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    rx_tx_engine_request_attr : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    rx_tx_engine_request_id : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    rx_ext_fifo_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    rx_tx_engine_request_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    reg_access_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    rx_ext_fifo_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
    rx_tx_engine_request_tag : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rx_tx_engine_lower_adr : out STD_LOGIC_VECTOR ( 6 downto 2 ); 
    trn_rx_trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trn_rx_trn_rbar_hit_n : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trn_rx_trn_rfc_npd_av : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rx_trn_rfc_ph_av : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rx_trn_rrem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trn_rx_trn_rfc_pd_av : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    trn_rx_trn_rfc_nph_av : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end core64_rx_engine;

architecture STRUCTURE of core64_rx_engine is
  component ctrl_fifo64x70st
    port (
      clk : in STD_LOGIC := 'X'; 
      rd_en : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      empty : out STD_LOGIC; 
      wr_en : in STD_LOGIC := 'X'; 
      valid : out STD_LOGIC; 
      full : out STD_LOGIC; 
      prog_empty : out STD_LOGIC; 
      prog_full : out STD_LOGIC; 
      dout : out STD_LOGIC_VECTOR ( 69 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 69 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal adr_cnt_0_or0000 : STD_LOGIC; 
  signal adr_cnt_3_not0001 : STD_LOGIC; 
  signal data_rx_we : STD_LOGIC; 
  signal data_rx_we_en_10255 : STD_LOGIC; 
  signal data_rx_we_en_mux0000_10256 : STD_LOGIC; 
  signal fifo0_dout_0_Q : STD_LOGIC; 
  signal fifo0_dout_10_Q : STD_LOGIC; 
  signal fifo0_dout_11_Q : STD_LOGIC; 
  signal fifo0_dout_12_Q : STD_LOGIC; 
  signal fifo0_dout_13_Q : STD_LOGIC; 
  signal fifo0_dout_14_Q : STD_LOGIC; 
  signal fifo0_dout_15_Q : STD_LOGIC; 
  signal fifo0_dout_16_Q : STD_LOGIC; 
  signal fifo0_dout_17_Q : STD_LOGIC; 
  signal fifo0_dout_18_Q : STD_LOGIC; 
  signal fifo0_dout_19_Q : STD_LOGIC; 
  signal fifo0_dout_1_Q : STD_LOGIC; 
  signal fifo0_dout_20_Q : STD_LOGIC; 
  signal fifo0_dout_21_Q : STD_LOGIC; 
  signal fifo0_dout_22_Q : STD_LOGIC; 
  signal fifo0_dout_23_Q : STD_LOGIC; 
  signal fifo0_dout_24_Q : STD_LOGIC; 
  signal fifo0_dout_25_Q : STD_LOGIC; 
  signal fifo0_dout_26_Q : STD_LOGIC; 
  signal fifo0_dout_27_Q : STD_LOGIC; 
  signal fifo0_dout_28_Q : STD_LOGIC; 
  signal fifo0_dout_29_Q : STD_LOGIC; 
  signal fifo0_dout_2_Q : STD_LOGIC; 
  signal fifo0_dout_30_Q : STD_LOGIC; 
  signal fifo0_dout_31_Q : STD_LOGIC; 
  signal fifo0_dout_34_Q : STD_LOGIC; 
  signal fifo0_dout_35_Q : STD_LOGIC; 
  signal fifo0_dout_36_Q : STD_LOGIC; 
  signal fifo0_dout_37_Q : STD_LOGIC; 
  signal fifo0_dout_38_Q : STD_LOGIC; 
  signal fifo0_dout_39_Q : STD_LOGIC; 
  signal fifo0_dout_3_Q : STD_LOGIC; 
  signal fifo0_dout_40_Q : STD_LOGIC; 
  signal fifo0_dout_41_Q : STD_LOGIC; 
  signal fifo0_dout_42_Q : STD_LOGIC; 
  signal fifo0_dout_43_Q : STD_LOGIC; 
  signal fifo0_dout_44_Q : STD_LOGIC; 
  signal fifo0_dout_45_Q : STD_LOGIC; 
  signal fifo0_dout_46_Q : STD_LOGIC; 
  signal fifo0_dout_47_Q : STD_LOGIC; 
  signal fifo0_dout_48_Q : STD_LOGIC; 
  signal fifo0_dout_49_Q : STD_LOGIC; 
  signal fifo0_dout_4_Q : STD_LOGIC; 
  signal fifo0_dout_52_Q : STD_LOGIC; 
  signal fifo0_dout_53_Q : STD_LOGIC; 
  signal fifo0_dout_54_Q : STD_LOGIC; 
  signal fifo0_dout_5_Q : STD_LOGIC; 
  signal fifo0_dout_62_Q : STD_LOGIC; 
  signal fifo0_dout_68_Q : STD_LOGIC; 
  signal fifo0_dout_69_Q : STD_LOGIC; 
  signal fifo0_dout_6_Q : STD_LOGIC; 
  signal fifo0_dout_7_Q : STD_LOGIC; 
  signal fifo0_dout_8_Q : STD_LOGIC; 
  signal fifo0_dout_9_Q : STD_LOGIC; 
  signal fifo0_empty : STD_LOGIC; 
  signal fifo0_paf : STD_LOGIC; 
  signal fifo0_rd_10313 : STD_LOGIC; 
  signal fifo0_rd_mux0000 : STD_LOGIC; 
  signal fifo0_wr : STD_LOGIC; 
  signal fifo0_wr_en_10316 : STD_LOGIC; 
  signal fifo0_wr_en_and0000 : STD_LOGIC; 
  signal fifo0_wr_en_z_10318 : STD_LOGIC; 
  signal fifo1_dout_0_Q : STD_LOGIC; 
  signal fifo1_dout_10_Q : STD_LOGIC; 
  signal fifo1_dout_11_Q : STD_LOGIC; 
  signal fifo1_dout_12_Q : STD_LOGIC; 
  signal fifo1_dout_13_Q : STD_LOGIC; 
  signal fifo1_dout_14_Q : STD_LOGIC; 
  signal fifo1_dout_15_Q : STD_LOGIC; 
  signal fifo1_dout_16_Q : STD_LOGIC; 
  signal fifo1_dout_17_Q : STD_LOGIC; 
  signal fifo1_dout_18_Q : STD_LOGIC; 
  signal fifo1_dout_19_Q : STD_LOGIC; 
  signal fifo1_dout_1_Q : STD_LOGIC; 
  signal fifo1_dout_20_Q : STD_LOGIC; 
  signal fifo1_dout_21_Q : STD_LOGIC; 
  signal fifo1_dout_22_Q : STD_LOGIC; 
  signal fifo1_dout_23_Q : STD_LOGIC; 
  signal fifo1_dout_24_Q : STD_LOGIC; 
  signal fifo1_dout_25_Q : STD_LOGIC; 
  signal fifo1_dout_26_Q : STD_LOGIC; 
  signal fifo1_dout_27_Q : STD_LOGIC; 
  signal fifo1_dout_28_Q : STD_LOGIC; 
  signal fifo1_dout_29_Q : STD_LOGIC; 
  signal fifo1_dout_2_Q : STD_LOGIC; 
  signal fifo1_dout_30_Q : STD_LOGIC; 
  signal fifo1_dout_31_Q : STD_LOGIC; 
  signal fifo1_dout_32_Q : STD_LOGIC; 
  signal fifo1_dout_33_Q : STD_LOGIC; 
  signal fifo1_dout_34_Q : STD_LOGIC; 
  signal fifo1_dout_35_Q : STD_LOGIC; 
  signal fifo1_dout_36_Q : STD_LOGIC; 
  signal fifo1_dout_37_Q : STD_LOGIC; 
  signal fifo1_dout_38_Q : STD_LOGIC; 
  signal fifo1_dout_39_Q : STD_LOGIC; 
  signal fifo1_dout_3_Q : STD_LOGIC; 
  signal fifo1_dout_40_Q : STD_LOGIC; 
  signal fifo1_dout_41_Q : STD_LOGIC; 
  signal fifo1_dout_42_Q : STD_LOGIC; 
  signal fifo1_dout_43_Q : STD_LOGIC; 
  signal fifo1_dout_44_Q : STD_LOGIC; 
  signal fifo1_dout_45_Q : STD_LOGIC; 
  signal fifo1_dout_46_Q : STD_LOGIC; 
  signal fifo1_dout_47_Q : STD_LOGIC; 
  signal fifo1_dout_48_Q : STD_LOGIC; 
  signal fifo1_dout_49_Q : STD_LOGIC; 
  signal fifo1_dout_4_Q : STD_LOGIC; 
  signal fifo1_dout_50_Q : STD_LOGIC; 
  signal fifo1_dout_51_Q : STD_LOGIC; 
  signal fifo1_dout_52_Q : STD_LOGIC; 
  signal fifo1_dout_53_Q : STD_LOGIC; 
  signal fifo1_dout_54_Q : STD_LOGIC; 
  signal fifo1_dout_55_Q : STD_LOGIC; 
  signal fifo1_dout_56_Q : STD_LOGIC; 
  signal fifo1_dout_57_Q : STD_LOGIC; 
  signal fifo1_dout_58_Q : STD_LOGIC; 
  signal fifo1_dout_59_Q : STD_LOGIC; 
  signal fifo1_dout_5_Q : STD_LOGIC; 
  signal fifo1_dout_60_Q : STD_LOGIC; 
  signal fifo1_dout_61_Q : STD_LOGIC; 
  signal fifo1_dout_62_Q : STD_LOGIC; 
  signal fifo1_dout_63_Q : STD_LOGIC; 
  signal fifo1_dout_65_Q : STD_LOGIC; 
  signal fifo1_dout_6_Q : STD_LOGIC; 
  signal fifo1_dout_7_Q : STD_LOGIC; 
  signal fifo1_dout_8_Q : STD_LOGIC; 
  signal fifo1_dout_9_Q : STD_LOGIC; 
  signal fifo1_pae : STD_LOGIC; 
  signal fifo1_paf : STD_LOGIC; 
  signal fifo1_rd_10386 : STD_LOGIC; 
  signal fifo1_rd_mux0000_10387 : STD_LOGIC; 
  signal fifo1_rd_x : STD_LOGIC; 
  signal fifo1_valid : STD_LOGIC; 
  signal fifo1_valid_inv : STD_LOGIC; 
  signal fifo1_wr : STD_LOGIC; 
  signal fifo1_wr_en_10392 : STD_LOGIC; 
  signal fifo1_wr_en_and0000 : STD_LOGIC; 
  signal fifo1_wr_en_or0000 : STD_LOGIC; 
  signal fifo1_wr_en_z_10395 : STD_LOGIC; 
  signal fifo_din_not0002 : STD_LOGIC; 
  signal fifo_din_not0003 : STD_LOGIC; 
  signal fifo_wr_norst : STD_LOGIC; 
  signal fifo_wr_or0000 : STD_LOGIC; 
  signal fifo_wr_z_10470 : STD_LOGIC; 
  signal NlwRenamedSig_OI_request_reg_rd : STD_LOGIC; 
  signal request_reg_rd_mux0000_10476 : STD_LOGIC; 
  signal NlwRenamedSig_OI_request_reg_wr : STD_LOGIC; 
  signal request_reg_wr_mux0000_10478 : STD_LOGIC; 
  signal rstpz_10480 : STD_LOGIC; 
  signal rx_ext_fifo_adr_0_10481 : STD_LOGIC; 
  signal rx_ext_fifo_adr_1_10482 : STD_LOGIC; 
  signal rx_ext_fifo_adr_2_10483 : STD_LOGIC; 
  signal rx_ext_fifo_adr_3_10484 : STD_LOGIC; 
  signal rx_ext_fifo_adr_4_10485 : STD_LOGIC; 
  signal rx_ext_fifo_adr_5_10486 : STD_LOGIC; 
  signal rx_ext_fifo_adr_6_10487 : STD_LOGIC; 
  signal rx_ext_fifo_adr_7_10488 : STD_LOGIC; 
  signal rx_ext_fifo_adr_8_10489 : STD_LOGIC; 
  signal rx_ext_fifo_data_0_10490 : STD_LOGIC; 
  signal rx_ext_fifo_data_1_10491 : STD_LOGIC; 
  signal rx_ext_fifo_data_10_10492 : STD_LOGIC; 
  signal rx_ext_fifo_data_11_10493 : STD_LOGIC; 
  signal rx_ext_fifo_data_12_10494 : STD_LOGIC; 
  signal rx_ext_fifo_data_13_10495 : STD_LOGIC; 
  signal rx_ext_fifo_data_14_10496 : STD_LOGIC; 
  signal rx_ext_fifo_data_15_10497 : STD_LOGIC; 
  signal rx_ext_fifo_data_16_10498 : STD_LOGIC; 
  signal rx_ext_fifo_data_17_10499 : STD_LOGIC; 
  signal rx_ext_fifo_data_18_10500 : STD_LOGIC; 
  signal rx_ext_fifo_data_19_10501 : STD_LOGIC; 
  signal rx_ext_fifo_data_2_10502 : STD_LOGIC; 
  signal rx_ext_fifo_data_20_10503 : STD_LOGIC; 
  signal rx_ext_fifo_data_21_10504 : STD_LOGIC; 
  signal rx_ext_fifo_data_22_10505 : STD_LOGIC; 
  signal rx_ext_fifo_data_23_10506 : STD_LOGIC; 
  signal rx_ext_fifo_data_24_10507 : STD_LOGIC; 
  signal rx_ext_fifo_data_25_10508 : STD_LOGIC; 
  signal rx_ext_fifo_data_26_10509 : STD_LOGIC; 
  signal rx_ext_fifo_data_27_10510 : STD_LOGIC; 
  signal rx_ext_fifo_data_28_10511 : STD_LOGIC; 
  signal rx_ext_fifo_data_29_10512 : STD_LOGIC; 
  signal rx_ext_fifo_data_3_10513 : STD_LOGIC; 
  signal rx_ext_fifo_data_30_10514 : STD_LOGIC; 
  signal rx_ext_fifo_data_31_10515 : STD_LOGIC; 
  signal rx_ext_fifo_data_32_10516 : STD_LOGIC; 
  signal rx_ext_fifo_data_33_10517 : STD_LOGIC; 
  signal rx_ext_fifo_data_34_10518 : STD_LOGIC; 
  signal rx_ext_fifo_data_35_10519 : STD_LOGIC; 
  signal rx_ext_fifo_data_36_10520 : STD_LOGIC; 
  signal rx_ext_fifo_data_37_10521 : STD_LOGIC; 
  signal rx_ext_fifo_data_38_10522 : STD_LOGIC; 
  signal rx_ext_fifo_data_39_10523 : STD_LOGIC; 
  signal rx_ext_fifo_data_4_10524 : STD_LOGIC; 
  signal rx_ext_fifo_data_40_10525 : STD_LOGIC; 
  signal rx_ext_fifo_data_41_10526 : STD_LOGIC; 
  signal rx_ext_fifo_data_42_10527 : STD_LOGIC; 
  signal rx_ext_fifo_data_43_10528 : STD_LOGIC; 
  signal rx_ext_fifo_data_44_10529 : STD_LOGIC; 
  signal rx_ext_fifo_data_45_10530 : STD_LOGIC; 
  signal rx_ext_fifo_data_46_10531 : STD_LOGIC; 
  signal rx_ext_fifo_data_47_10532 : STD_LOGIC; 
  signal rx_ext_fifo_data_48_10533 : STD_LOGIC; 
  signal rx_ext_fifo_data_49_10534 : STD_LOGIC; 
  signal rx_ext_fifo_data_5_10535 : STD_LOGIC; 
  signal rx_ext_fifo_data_50_10536 : STD_LOGIC; 
  signal rx_ext_fifo_data_51_10537 : STD_LOGIC; 
  signal rx_ext_fifo_data_52_10538 : STD_LOGIC; 
  signal rx_ext_fifo_data_53_10539 : STD_LOGIC; 
  signal rx_ext_fifo_data_54_10540 : STD_LOGIC; 
  signal rx_ext_fifo_data_55_10541 : STD_LOGIC; 
  signal rx_ext_fifo_data_56_10542 : STD_LOGIC; 
  signal rx_ext_fifo_data_57_10543 : STD_LOGIC; 
  signal rx_ext_fifo_data_58_10544 : STD_LOGIC; 
  signal rx_ext_fifo_data_59_10545 : STD_LOGIC; 
  signal rx_ext_fifo_data_6_10546 : STD_LOGIC; 
  signal rx_ext_fifo_data_60_10547 : STD_LOGIC; 
  signal rx_ext_fifo_data_61_10548 : STD_LOGIC; 
  signal rx_ext_fifo_data_62_10549 : STD_LOGIC; 
  signal rx_ext_fifo_data_63_10550 : STD_LOGIC; 
  signal rx_ext_fifo_data_7_10551 : STD_LOGIC; 
  signal rx_ext_fifo_data_8_10552 : STD_LOGIC; 
  signal rx_ext_fifo_data_9_10553 : STD_LOGIC; 
  signal rx_ext_fifo_data_we_10554 : STD_LOGIC; 
  signal rx_tx_engine_complete_we_10555 : STD_LOGIC; 
  signal stf_FSM_FFd1_10556 : STD_LOGIC; 
  signal stf_FSM_FFd1_In : STD_LOGIC; 
  signal stf_FSM_FFd2_10558 : STD_LOGIC; 
  signal stf_FSM_FFd2_In : STD_LOGIC; 
  signal stf_FSM_FFd3_10560 : STD_LOGIC; 
  signal stf_FSM_FFd4_10561 : STD_LOGIC; 
  signal stf_FSM_FFd5_10562 : STD_LOGIC; 
  signal stf_FSM_FFd6_10563 : STD_LOGIC; 
  signal stf_FSM_FFd6_In : STD_LOGIC; 
  signal stf_FSM_FFd7_10565 : STD_LOGIC; 
  signal stf_FSM_FFd7_In : STD_LOGIC; 
  signal stp_FSM_FFd1_10567 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_10569 : STD_LOGIC; 
  signal stp_FSM_FFd3_10570 : STD_LOGIC; 
  signal stp_FSM_FFd4_10571 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal stp_FSM_FFd5_10573 : STD_LOGIC; 
  signal stp_FSM_FFd5_In : STD_LOGIC; 
  signal stp_FSM_FFd6_10575 : STD_LOGIC; 
  signal stp_FSM_FFd7_10576 : STD_LOGIC; 
  signal stp_FSM_FFd7_In : STD_LOGIC; 
  signal stp_FSM_FFd8_10578 : STD_LOGIC; 
  signal stp_FSM_FFd8_In : STD_LOGIC; 
  signal tlp_cp_dw2_10_Q : STD_LOGIC; 
  signal tlp_cp_dw2_11_Q : STD_LOGIC; 
  signal tlp_cp_dw2_12_Q : STD_LOGIC; 
  signal tlp_cp_dw2_6_Q : STD_LOGIC; 
  signal tlp_cp_dw2_8_Q : STD_LOGIC; 
  signal tlp_cp_dw2_9_Q : STD_LOGIC; 
  signal tlp_dw0_20_Q : STD_LOGIC; 
  signal tlp_dw0_21_Q : STD_LOGIC; 
  signal tlp_dw0_22_Q : STD_LOGIC; 
  signal tlp_dw0_30_Q : STD_LOGIC; 
  signal tlp_dw0_4_Q : STD_LOGIC; 
  signal tlp_dw0_5_Q : STD_LOGIC; 
  signal tlp_dw0_6_Q : STD_LOGIC; 
  signal tlp_dw0_7_Q : STD_LOGIC; 
  signal tlp_dw2_10_Q : STD_LOGIC; 
  signal tlp_dw2_11_Q : STD_LOGIC; 
  signal tlp_dw2_12_Q : STD_LOGIC; 
  signal tlp_dw2_13_Q : STD_LOGIC; 
  signal tlp_dw2_14_Q : STD_LOGIC; 
  signal tlp_dw2_15_Q : STD_LOGIC; 
  signal tlp_dw2_16_Q : STD_LOGIC; 
  signal tlp_dw2_17_Q : STD_LOGIC; 
  signal tlp_dw2_20_Q : STD_LOGIC; 
  signal tlp_dw2_7_Q : STD_LOGIC; 
  signal tlp_dw2_8_Q : STD_LOGIC; 
  signal tlp_dw2_9_Q : STD_LOGIC; 
  signal NLW_fifo0_reg_valid_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_prog_empty_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_67_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_66_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_65_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_64_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo0_reg_dout_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_empty_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_dout_69_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_dout_68_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_dout_67_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_dout_66_UNCONNECTED : STD_LOGIC; 
  signal NLW_fifo1_cmpl_dout_64_UNCONNECTED : STD_LOGIC; 
  signal adr_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal adr_cnt_2_0_add0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal adr_rx : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal data_lrx : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal fifo_din : STD_LOGIC_VECTOR ( 69 downto 0 ); 
  signal tlp_cp_dw0 : STD_LOGIC_VECTOR ( 30 downto 30 ); 
  signal tlp_dw1 : STD_LOGIC_VECTOR ( 31 downto 8 ); 
  signal NlwRenamedSignal_tlp_dw2 : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal tlp_dw3 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
begin
  rx_tx_engine_complete_we <= rx_tx_engine_complete_we_10555;
  rx_tx_engine_request_reg_wr <= NlwRenamedSig_OI_request_reg_wr;
  rx_ext_fifo_data_we <= rx_ext_fifo_data_we_10554;
  rx_tx_engine_request_reg_rd <= NlwRenamedSig_OI_request_reg_rd;
  reg_access_adr(20) <= tlp_dw2_20_Q;
  reg_access_adr(17) <= tlp_dw2_17_Q;
  reg_access_adr(16) <= tlp_dw2_16_Q;
  reg_access_adr(15) <= tlp_dw2_15_Q;
  reg_access_adr(14) <= tlp_dw2_14_Q;
  reg_access_adr(13) <= tlp_dw2_13_Q;
  reg_access_adr(12) <= tlp_dw2_12_Q;
  reg_access_adr(11) <= tlp_dw2_11_Q;
  reg_access_adr(10) <= tlp_dw2_10_Q;
  reg_access_adr(9) <= tlp_dw2_9_Q;
  reg_access_adr(8) <= tlp_dw2_8_Q;
  reg_access_adr(7) <= tlp_dw2_7_Q;
  reg_access_adr(6) <= NlwRenamedSignal_tlp_dw2(6);
  reg_access_adr(5) <= NlwRenamedSignal_tlp_dw2(5);
  reg_access_adr(4) <= NlwRenamedSignal_tlp_dw2(4);
  reg_access_adr(3) <= NlwRenamedSignal_tlp_dw2(3);
  reg_access_adr(2) <= NlwRenamedSignal_tlp_dw2(2);
  rx_tx_engine_request_attr(3) <= tlp_dw0_7_Q;
  rx_tx_engine_request_attr(2) <= tlp_dw0_6_Q;
  rx_tx_engine_request_attr(1) <= tlp_dw0_5_Q;
  rx_tx_engine_request_attr(0) <= tlp_dw0_4_Q;
  rx_tx_engine_request_id(15) <= tlp_dw1(31);
  rx_tx_engine_request_id(14) <= tlp_dw1(30);
  rx_tx_engine_request_id(13) <= tlp_dw1(29);
  rx_tx_engine_request_id(12) <= tlp_dw1(28);
  rx_tx_engine_request_id(11) <= tlp_dw1(27);
  rx_tx_engine_request_id(10) <= tlp_dw1(26);
  rx_tx_engine_request_id(9) <= tlp_dw1(25);
  rx_tx_engine_request_id(8) <= tlp_dw1(24);
  rx_tx_engine_request_id(7) <= tlp_dw1(23);
  rx_tx_engine_request_id(6) <= tlp_dw1(22);
  rx_tx_engine_request_id(5) <= tlp_dw1(21);
  rx_tx_engine_request_id(4) <= tlp_dw1(20);
  rx_tx_engine_request_id(3) <= tlp_dw1(19);
  rx_tx_engine_request_id(2) <= tlp_dw1(18);
  rx_tx_engine_request_id(1) <= tlp_dw1(17);
  rx_tx_engine_request_id(0) <= tlp_dw1(16);
  rx_ext_fifo_data(63) <= rx_ext_fifo_data_63_10550;
  rx_ext_fifo_data(62) <= rx_ext_fifo_data_62_10549;
  rx_ext_fifo_data(61) <= rx_ext_fifo_data_61_10548;
  rx_ext_fifo_data(60) <= rx_ext_fifo_data_60_10547;
  rx_ext_fifo_data(59) <= rx_ext_fifo_data_59_10545;
  rx_ext_fifo_data(58) <= rx_ext_fifo_data_58_10544;
  rx_ext_fifo_data(57) <= rx_ext_fifo_data_57_10543;
  rx_ext_fifo_data(56) <= rx_ext_fifo_data_56_10542;
  rx_ext_fifo_data(55) <= rx_ext_fifo_data_55_10541;
  rx_ext_fifo_data(54) <= rx_ext_fifo_data_54_10540;
  rx_ext_fifo_data(53) <= rx_ext_fifo_data_53_10539;
  rx_ext_fifo_data(52) <= rx_ext_fifo_data_52_10538;
  rx_ext_fifo_data(51) <= rx_ext_fifo_data_51_10537;
  rx_ext_fifo_data(50) <= rx_ext_fifo_data_50_10536;
  rx_ext_fifo_data(49) <= rx_ext_fifo_data_49_10534;
  rx_ext_fifo_data(48) <= rx_ext_fifo_data_48_10533;
  rx_ext_fifo_data(47) <= rx_ext_fifo_data_47_10532;
  rx_ext_fifo_data(46) <= rx_ext_fifo_data_46_10531;
  rx_ext_fifo_data(45) <= rx_ext_fifo_data_45_10530;
  rx_ext_fifo_data(44) <= rx_ext_fifo_data_44_10529;
  rx_ext_fifo_data(43) <= rx_ext_fifo_data_43_10528;
  rx_ext_fifo_data(42) <= rx_ext_fifo_data_42_10527;
  rx_ext_fifo_data(41) <= rx_ext_fifo_data_41_10526;
  rx_ext_fifo_data(40) <= rx_ext_fifo_data_40_10525;
  rx_ext_fifo_data(39) <= rx_ext_fifo_data_39_10523;
  rx_ext_fifo_data(38) <= rx_ext_fifo_data_38_10522;
  rx_ext_fifo_data(37) <= rx_ext_fifo_data_37_10521;
  rx_ext_fifo_data(36) <= rx_ext_fifo_data_36_10520;
  rx_ext_fifo_data(35) <= rx_ext_fifo_data_35_10519;
  rx_ext_fifo_data(34) <= rx_ext_fifo_data_34_10518;
  rx_ext_fifo_data(33) <= rx_ext_fifo_data_33_10517;
  rx_ext_fifo_data(32) <= rx_ext_fifo_data_32_10516;
  rx_ext_fifo_data(31) <= rx_ext_fifo_data_31_10515;
  rx_ext_fifo_data(30) <= rx_ext_fifo_data_30_10514;
  rx_ext_fifo_data(29) <= rx_ext_fifo_data_29_10512;
  rx_ext_fifo_data(28) <= rx_ext_fifo_data_28_10511;
  rx_ext_fifo_data(27) <= rx_ext_fifo_data_27_10510;
  rx_ext_fifo_data(26) <= rx_ext_fifo_data_26_10509;
  rx_ext_fifo_data(25) <= rx_ext_fifo_data_25_10508;
  rx_ext_fifo_data(24) <= rx_ext_fifo_data_24_10507;
  rx_ext_fifo_data(23) <= rx_ext_fifo_data_23_10506;
  rx_ext_fifo_data(22) <= rx_ext_fifo_data_22_10505;
  rx_ext_fifo_data(21) <= rx_ext_fifo_data_21_10504;
  rx_ext_fifo_data(20) <= rx_ext_fifo_data_20_10503;
  rx_ext_fifo_data(19) <= rx_ext_fifo_data_19_10501;
  rx_ext_fifo_data(18) <= rx_ext_fifo_data_18_10500;
  rx_ext_fifo_data(17) <= rx_ext_fifo_data_17_10499;
  rx_ext_fifo_data(16) <= rx_ext_fifo_data_16_10498;
  rx_ext_fifo_data(15) <= rx_ext_fifo_data_15_10497;
  rx_ext_fifo_data(14) <= rx_ext_fifo_data_14_10496;
  rx_ext_fifo_data(13) <= rx_ext_fifo_data_13_10495;
  rx_ext_fifo_data(12) <= rx_ext_fifo_data_12_10494;
  rx_ext_fifo_data(11) <= rx_ext_fifo_data_11_10493;
  rx_ext_fifo_data(10) <= rx_ext_fifo_data_10_10492;
  rx_ext_fifo_data(9) <= rx_ext_fifo_data_9_10553;
  rx_ext_fifo_data(8) <= rx_ext_fifo_data_8_10552;
  rx_ext_fifo_data(7) <= rx_ext_fifo_data_7_10551;
  rx_ext_fifo_data(6) <= rx_ext_fifo_data_6_10546;
  rx_ext_fifo_data(5) <= rx_ext_fifo_data_5_10535;
  rx_ext_fifo_data(4) <= rx_ext_fifo_data_4_10524;
  rx_ext_fifo_data(3) <= rx_ext_fifo_data_3_10513;
  rx_ext_fifo_data(2) <= rx_ext_fifo_data_2_10502;
  rx_ext_fifo_data(1) <= rx_ext_fifo_data_1_10491;
  rx_ext_fifo_data(0) <= rx_ext_fifo_data_0_10490;
  rx_tx_engine_request_tc(2) <= tlp_dw0_22_Q;
  rx_tx_engine_request_tc(1) <= tlp_dw0_21_Q;
  rx_tx_engine_request_tc(0) <= tlp_dw0_20_Q;
  reg_access_data(31) <= tlp_dw3(7);
  reg_access_data(30) <= tlp_dw3(6);
  reg_access_data(29) <= tlp_dw3(5);
  reg_access_data(28) <= tlp_dw3(4);
  reg_access_data(27) <= tlp_dw3(3);
  reg_access_data(26) <= tlp_dw3(2);
  reg_access_data(25) <= tlp_dw3(1);
  reg_access_data(24) <= tlp_dw3(0);
  reg_access_data(23) <= tlp_dw3(15);
  reg_access_data(22) <= tlp_dw3(14);
  reg_access_data(21) <= tlp_dw3(13);
  reg_access_data(20) <= tlp_dw3(12);
  reg_access_data(19) <= tlp_dw3(11);
  reg_access_data(18) <= tlp_dw3(10);
  reg_access_data(17) <= tlp_dw3(9);
  reg_access_data(16) <= tlp_dw3(8);
  reg_access_data(15) <= tlp_dw3(23);
  reg_access_data(14) <= tlp_dw3(22);
  reg_access_data(13) <= tlp_dw3(21);
  reg_access_data(12) <= tlp_dw3(20);
  reg_access_data(11) <= tlp_dw3(19);
  reg_access_data(10) <= tlp_dw3(18);
  reg_access_data(9) <= tlp_dw3(17);
  reg_access_data(8) <= tlp_dw3(16);
  reg_access_data(7) <= tlp_dw3(31);
  reg_access_data(6) <= tlp_dw3(30);
  reg_access_data(5) <= tlp_dw3(29);
  reg_access_data(4) <= tlp_dw3(28);
  reg_access_data(3) <= tlp_dw3(27);
  reg_access_data(2) <= tlp_dw3(26);
  reg_access_data(1) <= tlp_dw3(25);
  reg_access_data(0) <= tlp_dw3(24);
  rx_ext_fifo_adr(8) <= rx_ext_fifo_adr_8_10489;
  rx_ext_fifo_adr(7) <= rx_ext_fifo_adr_7_10488;
  rx_ext_fifo_adr(6) <= rx_ext_fifo_adr_6_10487;
  rx_ext_fifo_adr(5) <= rx_ext_fifo_adr_5_10486;
  rx_ext_fifo_adr(4) <= rx_ext_fifo_adr_4_10485;
  rx_ext_fifo_adr(3) <= rx_ext_fifo_adr_3_10484;
  rx_ext_fifo_adr(2) <= rx_ext_fifo_adr_2_10483;
  rx_ext_fifo_adr(1) <= rx_ext_fifo_adr_1_10482;
  rx_ext_fifo_adr(0) <= rx_ext_fifo_adr_0_10481;
  rx_tx_engine_request_tag(7) <= tlp_dw1(15);
  rx_tx_engine_request_tag(6) <= tlp_dw1(14);
  rx_tx_engine_request_tag(5) <= tlp_dw1(13);
  rx_tx_engine_request_tag(4) <= tlp_dw1(12);
  rx_tx_engine_request_tag(3) <= tlp_dw1(11);
  rx_tx_engine_request_tag(2) <= tlp_dw1(10);
  rx_tx_engine_request_tag(1) <= tlp_dw1(9);
  rx_tx_engine_request_tag(0) <= tlp_dw1(8);
  rx_tx_engine_lower_adr(6) <= NlwRenamedSignal_tlp_dw2(6);
  rx_tx_engine_lower_adr(5) <= NlwRenamedSignal_tlp_dw2(5);
  rx_tx_engine_lower_adr(4) <= NlwRenamedSignal_tlp_dw2(4);
  rx_tx_engine_lower_adr(3) <= NlwRenamedSignal_tlp_dw2(3);
  rx_tx_engine_lower_adr(2) <= NlwRenamedSignal_tlp_dw2(2);
  XST_VCC : VCC
    port map (
      P => fifo_wr_norst
    );
  fifo1_rd : FD
    port map (
      C => clk,
      D => fifo1_rd_mux0000_10387,
      Q => fifo1_rd_10386
    );
  data_rx_we_en : FD
    port map (
      C => clk,
      D => data_rx_we_en_mux0000_10256,
      Q => data_rx_we_en_10255
    );
  rstpz : FD
    port map (
      C => clk,
      D => rstp,
      Q => rstpz_10480
    );
  request_reg_rd : FD
    port map (
      C => clk,
      D => request_reg_rd_mux0000_10476,
      Q => NlwRenamedSig_OI_request_reg_rd
    );
  fifo_din_0 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(0),
      Q => fifo_din(0)
    );
  fifo_din_1 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(1),
      Q => fifo_din(1)
    );
  fifo_din_2 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(2),
      Q => fifo_din(2)
    );
  fifo_din_3 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(3),
      Q => fifo_din(3)
    );
  fifo_din_4 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(4),
      Q => fifo_din(4)
    );
  fifo_din_5 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(5),
      Q => fifo_din(5)
    );
  fifo_din_6 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(6),
      Q => fifo_din(6)
    );
  fifo_din_7 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(7),
      Q => fifo_din(7)
    );
  fifo_din_8 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(8),
      Q => fifo_din(8)
    );
  fifo_din_9 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(9),
      Q => fifo_din(9)
    );
  fifo_din_10 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(10),
      Q => fifo_din(10)
    );
  fifo_din_11 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(11),
      Q => fifo_din(11)
    );
  fifo_din_12 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(12),
      Q => fifo_din(12)
    );
  fifo_din_13 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(13),
      Q => fifo_din(13)
    );
  fifo_din_14 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(14),
      Q => fifo_din(14)
    );
  fifo_din_15 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(15),
      Q => fifo_din(15)
    );
  fifo_din_16 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(16),
      Q => fifo_din(16)
    );
  fifo_din_17 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(17),
      Q => fifo_din(17)
    );
  fifo_din_18 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(18),
      Q => fifo_din(18)
    );
  fifo_din_19 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(19),
      Q => fifo_din(19)
    );
  fifo_din_20 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(20),
      Q => fifo_din(20)
    );
  fifo_din_21 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(21),
      Q => fifo_din(21)
    );
  fifo_din_22 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(22),
      Q => fifo_din(22)
    );
  fifo_din_23 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(23),
      Q => fifo_din(23)
    );
  fifo_din_24 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(24),
      Q => fifo_din(24)
    );
  fifo_din_25 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(25),
      Q => fifo_din(25)
    );
  fifo_din_26 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(26),
      Q => fifo_din(26)
    );
  fifo_din_27 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(27),
      Q => fifo_din(27)
    );
  fifo_din_28 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(28),
      Q => fifo_din(28)
    );
  fifo_din_29 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(29),
      Q => fifo_din(29)
    );
  fifo_din_30 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(30),
      Q => fifo_din(30)
    );
  fifo_din_31 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(31),
      Q => fifo_din(31)
    );
  fifo_din_32 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(32),
      Q => fifo_din(32)
    );
  fifo_din_33 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(33),
      Q => fifo_din(33)
    );
  fifo_din_34 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(34),
      Q => fifo_din(34)
    );
  fifo_din_35 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(35),
      Q => fifo_din(35)
    );
  fifo_din_36 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(36),
      Q => fifo_din(36)
    );
  fifo_din_37 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(37),
      Q => fifo_din(37)
    );
  fifo_din_38 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(38),
      Q => fifo_din(38)
    );
  fifo_din_39 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(39),
      Q => fifo_din(39)
    );
  fifo_din_40 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(40),
      Q => fifo_din(40)
    );
  fifo_din_41 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(41),
      Q => fifo_din(41)
    );
  fifo_din_42 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(42),
      Q => fifo_din(42)
    );
  fifo_din_43 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(43),
      Q => fifo_din(43)
    );
  fifo_din_44 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(44),
      Q => fifo_din(44)
    );
  fifo_din_45 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(45),
      Q => fifo_din(45)
    );
  fifo_din_46 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(46),
      Q => fifo_din(46)
    );
  fifo_din_47 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(47),
      Q => fifo_din(47)
    );
  fifo_din_48 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(48),
      Q => fifo_din(48)
    );
  fifo_din_49 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(49),
      Q => fifo_din(49)
    );
  fifo_din_50 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(50),
      Q => fifo_din(50)
    );
  fifo_din_51 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(51),
      Q => fifo_din(51)
    );
  fifo_din_52 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(52),
      Q => fifo_din(52)
    );
  fifo_din_53 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(53),
      Q => fifo_din(53)
    );
  fifo_din_54 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(54),
      Q => fifo_din(54)
    );
  fifo_din_55 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(55),
      Q => fifo_din(55)
    );
  fifo_din_56 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(56),
      Q => fifo_din(56)
    );
  fifo_din_57 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(57),
      Q => fifo_din(57)
    );
  fifo_din_58 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(58),
      Q => fifo_din(58)
    );
  fifo_din_59 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(59),
      Q => fifo_din(59)
    );
  fifo_din_60 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(60),
      Q => fifo_din(60)
    );
  fifo_din_61 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(61),
      Q => fifo_din(61)
    );
  fifo_din_62 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(62),
      Q => fifo_din(62)
    );
  fifo_din_63 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rd(63),
      Q => fifo_din(63)
    );
  fifo_din_64 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rsof_n,
      Q => fifo_din(64)
    );
  fifo_din_65 : FD
    port map (
      C => clk,
      D => trn_rx_trn_reof_n,
      Q => fifo_din(65)
    );
  fifo_din_66 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rrem_n(0),
      Q => fifo_din(66)
    );
  fifo_din_67 : FD
    port map (
      C => clk,
      D => trn_rx_trn_rerrfwd_n,
      Q => fifo_din(67)
    );
  fifo_din_68 : FD
    port map (
      C => clk,
      D => fifo_din_not0003,
      Q => fifo_din(68)
    );
  fifo_din_69 : FD
    port map (
      C => clk,
      D => fifo_din_not0002,
      Q => fifo_din(69)
    );
  fifo0_rd : FD
    port map (
      C => clk,
      D => fifo0_rd_mux0000,
      Q => fifo0_rd_10313
    );
  request_reg_wr : FD
    port map (
      C => clk,
      D => request_reg_wr_mux0000_10478,
      Q => NlwRenamedSig_OI_request_reg_wr
    );
  fifo1_wr_en : FDRE
    port map (
      C => clk,
      CE => fifo1_wr_en_and0000,
      D => fifo_wr_norst,
      R => fifo1_wr_en_or0000,
      Q => fifo1_wr_en_10392
    );
  fifo0_wr_en : FDRE
    port map (
      C => clk,
      CE => fifo0_wr_en_and0000,
      D => fifo_wr_norst,
      R => fifo1_wr_en_or0000,
      Q => fifo0_wr_en_10316
    );
  adr_cnt_0 : FDRE
    port map (
      C => clk,
      CE => data_rx_we,
      D => adr_cnt_2_0_add0000(0),
      R => adr_cnt_0_or0000,
      Q => adr_cnt(0)
    );
  adr_cnt_1 : FDRE
    port map (
      C => clk,
      CE => data_rx_we,
      D => adr_cnt_2_0_add0000(1),
      R => adr_cnt_0_or0000,
      Q => adr_cnt(1)
    );
  adr_cnt_3 : FDRE
    port map (
      C => clk,
      CE => adr_cnt_3_not0001,
      D => fifo_wr_norst,
      R => adr_cnt_0_or0000,
      Q => adr_cnt(3)
    );
  fifo_wr_z : FDR
    port map (
      C => clk,
      D => fifo_wr_norst,
      R => fifo_wr_or0000,
      Q => fifo_wr_z_10470
    );
  fifo1_wr_en_z : FD
    port map (
      C => clk,
      D => fifo1_wr_en_10392,
      Q => fifo1_wr_en_z_10395
    );
  fifo0_wr_en_z : FD
    port map (
      C => clk,
      D => fifo0_wr_en_10316,
      Q => fifo0_wr_en_z_10318
    );
  tlp_cp_dw0_30 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd4_10561,
      D => fifo1_dout_62_Q,
      Q => tlp_cp_dw0(30)
    );
  data_lrx_0 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_0_Q,
      Q => data_lrx(0)
    );
  data_lrx_1 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_1_Q,
      Q => data_lrx(1)
    );
  data_lrx_2 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_2_Q,
      Q => data_lrx(2)
    );
  data_lrx_3 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_3_Q,
      Q => data_lrx(3)
    );
  data_lrx_4 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_4_Q,
      Q => data_lrx(4)
    );
  data_lrx_5 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_5_Q,
      Q => data_lrx(5)
    );
  data_lrx_6 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_6_Q,
      Q => data_lrx(6)
    );
  data_lrx_7 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_7_Q,
      Q => data_lrx(7)
    );
  data_lrx_8 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_8_Q,
      Q => data_lrx(8)
    );
  data_lrx_9 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_9_Q,
      Q => data_lrx(9)
    );
  data_lrx_10 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_10_Q,
      Q => data_lrx(10)
    );
  data_lrx_11 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_11_Q,
      Q => data_lrx(11)
    );
  data_lrx_12 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_12_Q,
      Q => data_lrx(12)
    );
  data_lrx_13 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_13_Q,
      Q => data_lrx(13)
    );
  data_lrx_14 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_14_Q,
      Q => data_lrx(14)
    );
  data_lrx_15 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_15_Q,
      Q => data_lrx(15)
    );
  data_lrx_16 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_16_Q,
      Q => data_lrx(16)
    );
  data_lrx_17 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_17_Q,
      Q => data_lrx(17)
    );
  data_lrx_18 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_18_Q,
      Q => data_lrx(18)
    );
  data_lrx_19 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_19_Q,
      Q => data_lrx(19)
    );
  data_lrx_20 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_20_Q,
      Q => data_lrx(20)
    );
  data_lrx_21 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_21_Q,
      Q => data_lrx(21)
    );
  data_lrx_22 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_22_Q,
      Q => data_lrx(22)
    );
  data_lrx_23 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_23_Q,
      Q => data_lrx(23)
    );
  data_lrx_24 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_24_Q,
      Q => data_lrx(24)
    );
  data_lrx_25 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_25_Q,
      Q => data_lrx(25)
    );
  data_lrx_26 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_26_Q,
      Q => data_lrx(26)
    );
  data_lrx_27 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_27_Q,
      Q => data_lrx(27)
    );
  data_lrx_28 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_28_Q,
      Q => data_lrx(28)
    );
  data_lrx_29 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_29_Q,
      Q => data_lrx(29)
    );
  data_lrx_30 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_30_Q,
      Q => data_lrx(30)
    );
  data_lrx_31 : FDE
    port map (
      C => clk,
      CE => fifo1_valid,
      D => fifo1_dout_31_Q,
      Q => data_lrx(31)
    );
  adr_cnt_2 : FDRE
    port map (
      C => clk,
      CE => data_rx_we,
      D => adr_cnt_2_0_add0000(2),
      R => adr_cnt_0_or0000,
      Q => adr_cnt(2)
    );
  rx_ext_fifo_data_we_7843 : FDR
    port map (
      C => clk,
      D => data_rx_we_en_10255,
      R => fifo1_valid_inv,
      Q => rx_ext_fifo_data_we_10554
    );
  rx_tx_engine_complete_we_7844 : FDR
    port map (
      C => clk,
      D => data_rx_we_en_10255,
      R => fifo1_valid_inv,
      Q => rx_tx_engine_complete_we_10555
    );
  tlp_dw0_4 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_36_Q,
      Q => tlp_dw0_4_Q
    );
  tlp_dw0_5 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_37_Q,
      Q => tlp_dw0_5_Q
    );
  tlp_dw0_6 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_38_Q,
      Q => tlp_dw0_6_Q
    );
  tlp_dw0_7 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_39_Q,
      Q => tlp_dw0_7_Q
    );
  tlp_dw0_20 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_52_Q,
      Q => tlp_dw0_20_Q
    );
  tlp_dw0_21 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_53_Q,
      Q => tlp_dw0_21_Q
    );
  tlp_dw0_22 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_54_Q,
      Q => tlp_dw0_22_Q
    );
  tlp_dw0_30 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_62_Q,
      Q => tlp_dw0_30_Q
    );
  tlp_dw1_8 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_8_Q,
      Q => tlp_dw1(8)
    );
  tlp_dw1_9 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_9_Q,
      Q => tlp_dw1(9)
    );
  tlp_dw1_10 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_10_Q,
      Q => tlp_dw1(10)
    );
  tlp_dw1_11 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_11_Q,
      Q => tlp_dw1(11)
    );
  tlp_dw1_12 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_12_Q,
      Q => tlp_dw1(12)
    );
  tlp_dw1_13 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_13_Q,
      Q => tlp_dw1(13)
    );
  tlp_dw1_14 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_14_Q,
      Q => tlp_dw1(14)
    );
  tlp_dw1_15 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_15_Q,
      Q => tlp_dw1(15)
    );
  tlp_dw1_16 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_16_Q,
      Q => tlp_dw1(16)
    );
  tlp_dw1_17 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_17_Q,
      Q => tlp_dw1(17)
    );
  tlp_dw1_18 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_18_Q,
      Q => tlp_dw1(18)
    );
  tlp_dw1_19 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_19_Q,
      Q => tlp_dw1(19)
    );
  tlp_dw1_20 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_20_Q,
      Q => tlp_dw1(20)
    );
  tlp_dw1_21 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_21_Q,
      Q => tlp_dw1(21)
    );
  tlp_dw1_22 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_22_Q,
      Q => tlp_dw1(22)
    );
  tlp_dw1_23 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_23_Q,
      Q => tlp_dw1(23)
    );
  tlp_dw1_24 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_24_Q,
      Q => tlp_dw1(24)
    );
  tlp_dw1_25 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_25_Q,
      Q => tlp_dw1(25)
    );
  tlp_dw1_26 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_26_Q,
      Q => tlp_dw1(26)
    );
  tlp_dw1_27 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_27_Q,
      Q => tlp_dw1(27)
    );
  tlp_dw1_28 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_28_Q,
      Q => tlp_dw1(28)
    );
  tlp_dw1_29 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_29_Q,
      Q => tlp_dw1(29)
    );
  tlp_dw1_30 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_30_Q,
      Q => tlp_dw1(30)
    );
  tlp_dw1_31 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd5_10573,
      D => fifo0_dout_31_Q,
      Q => tlp_dw1(31)
    );
  tlp_dw2_2 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_34_Q,
      Q => NlwRenamedSignal_tlp_dw2(2)
    );
  tlp_dw2_3 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_35_Q,
      Q => NlwRenamedSignal_tlp_dw2(3)
    );
  tlp_dw2_4 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_36_Q,
      Q => NlwRenamedSignal_tlp_dw2(4)
    );
  tlp_dw2_5 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_37_Q,
      Q => NlwRenamedSignal_tlp_dw2(5)
    );
  tlp_dw2_6 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_38_Q,
      Q => NlwRenamedSignal_tlp_dw2(6)
    );
  tlp_dw2_7 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_39_Q,
      Q => tlp_dw2_7_Q
    );
  tlp_dw2_8 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_40_Q,
      Q => tlp_dw2_8_Q
    );
  tlp_dw2_9 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_41_Q,
      Q => tlp_dw2_9_Q
    );
  tlp_dw2_10 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_42_Q,
      Q => tlp_dw2_10_Q
    );
  tlp_dw2_11 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_43_Q,
      Q => tlp_dw2_11_Q
    );
  tlp_dw2_12 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_44_Q,
      Q => tlp_dw2_12_Q
    );
  tlp_dw2_13 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_45_Q,
      Q => tlp_dw2_13_Q
    );
  tlp_dw2_14 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_46_Q,
      Q => tlp_dw2_14_Q
    );
  tlp_dw2_15 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_47_Q,
      Q => tlp_dw2_15_Q
    );
  tlp_dw2_16 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_48_Q,
      Q => tlp_dw2_16_Q
    );
  tlp_dw2_17 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_49_Q,
      Q => tlp_dw2_17_Q
    );
  tlp_dw2_20 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_52_Q,
      Q => tlp_dw2_20_Q
    );
  tlp_dw3_0 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_0_Q,
      Q => tlp_dw3(0)
    );
  tlp_dw3_1 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_1_Q,
      Q => tlp_dw3(1)
    );
  tlp_dw3_2 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_2_Q,
      Q => tlp_dw3(2)
    );
  tlp_dw3_3 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_3_Q,
      Q => tlp_dw3(3)
    );
  tlp_dw3_4 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_4_Q,
      Q => tlp_dw3(4)
    );
  tlp_dw3_5 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_5_Q,
      Q => tlp_dw3(5)
    );
  tlp_dw3_6 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_6_Q,
      Q => tlp_dw3(6)
    );
  tlp_dw3_7 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_7_Q,
      Q => tlp_dw3(7)
    );
  tlp_dw3_8 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_8_Q,
      Q => tlp_dw3(8)
    );
  tlp_dw3_9 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_9_Q,
      Q => tlp_dw3(9)
    );
  tlp_dw3_10 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_10_Q,
      Q => tlp_dw3(10)
    );
  tlp_dw3_11 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_11_Q,
      Q => tlp_dw3(11)
    );
  tlp_dw3_12 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_12_Q,
      Q => tlp_dw3(12)
    );
  tlp_dw3_13 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_13_Q,
      Q => tlp_dw3(13)
    );
  tlp_dw3_14 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_14_Q,
      Q => tlp_dw3(14)
    );
  tlp_dw3_15 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_15_Q,
      Q => tlp_dw3(15)
    );
  tlp_dw3_16 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_16_Q,
      Q => tlp_dw3(16)
    );
  tlp_dw3_17 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_17_Q,
      Q => tlp_dw3(17)
    );
  tlp_dw3_18 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_18_Q,
      Q => tlp_dw3(18)
    );
  tlp_dw3_19 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_19_Q,
      Q => tlp_dw3(19)
    );
  tlp_dw3_20 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_20_Q,
      Q => tlp_dw3(20)
    );
  tlp_dw3_21 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_21_Q,
      Q => tlp_dw3(21)
    );
  tlp_dw3_22 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_22_Q,
      Q => tlp_dw3(22)
    );
  tlp_dw3_23 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_23_Q,
      Q => tlp_dw3(23)
    );
  tlp_dw3_24 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_24_Q,
      Q => tlp_dw3(24)
    );
  tlp_dw3_25 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_25_Q,
      Q => tlp_dw3(25)
    );
  tlp_dw3_26 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_26_Q,
      Q => tlp_dw3(26)
    );
  tlp_dw3_27 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_27_Q,
      Q => tlp_dw3(27)
    );
  tlp_dw3_28 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_28_Q,
      Q => tlp_dw3(28)
    );
  tlp_dw3_29 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_29_Q,
      Q => tlp_dw3(29)
    );
  tlp_dw3_30 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_30_Q,
      Q => tlp_dw3(30)
    );
  tlp_dw3_31 : FDE
    port map (
      C => clk,
      CE => stp_FSM_FFd2_10569,
      D => fifo0_dout_31_Q,
      Q => tlp_dw3(31)
    );
  rx_ext_fifo_data_0 : FD
    port map (
      C => clk,
      D => data_lrx(24),
      Q => rx_ext_fifo_data_0_10490
    );
  rx_ext_fifo_data_1 : FD
    port map (
      C => clk,
      D => data_lrx(25),
      Q => rx_ext_fifo_data_1_10491
    );
  rx_ext_fifo_data_2 : FD
    port map (
      C => clk,
      D => data_lrx(26),
      Q => rx_ext_fifo_data_2_10502
    );
  rx_ext_fifo_data_3 : FD
    port map (
      C => clk,
      D => data_lrx(27),
      Q => rx_ext_fifo_data_3_10513
    );
  rx_ext_fifo_data_4 : FD
    port map (
      C => clk,
      D => data_lrx(28),
      Q => rx_ext_fifo_data_4_10524
    );
  rx_ext_fifo_data_5 : FD
    port map (
      C => clk,
      D => data_lrx(29),
      Q => rx_ext_fifo_data_5_10535
    );
  rx_ext_fifo_data_6 : FD
    port map (
      C => clk,
      D => data_lrx(30),
      Q => rx_ext_fifo_data_6_10546
    );
  rx_ext_fifo_data_7 : FD
    port map (
      C => clk,
      D => data_lrx(31),
      Q => rx_ext_fifo_data_7_10551
    );
  rx_ext_fifo_data_8 : FD
    port map (
      C => clk,
      D => data_lrx(16),
      Q => rx_ext_fifo_data_8_10552
    );
  rx_ext_fifo_data_9 : FD
    port map (
      C => clk,
      D => data_lrx(17),
      Q => rx_ext_fifo_data_9_10553
    );
  rx_ext_fifo_data_10 : FD
    port map (
      C => clk,
      D => data_lrx(18),
      Q => rx_ext_fifo_data_10_10492
    );
  rx_ext_fifo_data_11 : FD
    port map (
      C => clk,
      D => data_lrx(19),
      Q => rx_ext_fifo_data_11_10493
    );
  rx_ext_fifo_data_12 : FD
    port map (
      C => clk,
      D => data_lrx(20),
      Q => rx_ext_fifo_data_12_10494
    );
  rx_ext_fifo_data_13 : FD
    port map (
      C => clk,
      D => data_lrx(21),
      Q => rx_ext_fifo_data_13_10495
    );
  rx_ext_fifo_data_14 : FD
    port map (
      C => clk,
      D => data_lrx(22),
      Q => rx_ext_fifo_data_14_10496
    );
  rx_ext_fifo_data_15 : FD
    port map (
      C => clk,
      D => data_lrx(23),
      Q => rx_ext_fifo_data_15_10497
    );
  rx_ext_fifo_data_16 : FD
    port map (
      C => clk,
      D => data_lrx(8),
      Q => rx_ext_fifo_data_16_10498
    );
  rx_ext_fifo_data_17 : FD
    port map (
      C => clk,
      D => data_lrx(9),
      Q => rx_ext_fifo_data_17_10499
    );
  rx_ext_fifo_data_18 : FD
    port map (
      C => clk,
      D => data_lrx(10),
      Q => rx_ext_fifo_data_18_10500
    );
  rx_ext_fifo_data_19 : FD
    port map (
      C => clk,
      D => data_lrx(11),
      Q => rx_ext_fifo_data_19_10501
    );
  rx_ext_fifo_data_20 : FD
    port map (
      C => clk,
      D => data_lrx(12),
      Q => rx_ext_fifo_data_20_10503
    );
  rx_ext_fifo_data_21 : FD
    port map (
      C => clk,
      D => data_lrx(13),
      Q => rx_ext_fifo_data_21_10504
    );
  rx_ext_fifo_data_22 : FD
    port map (
      C => clk,
      D => data_lrx(14),
      Q => rx_ext_fifo_data_22_10505
    );
  rx_ext_fifo_data_23 : FD
    port map (
      C => clk,
      D => data_lrx(15),
      Q => rx_ext_fifo_data_23_10506
    );
  rx_ext_fifo_data_24 : FD
    port map (
      C => clk,
      D => data_lrx(0),
      Q => rx_ext_fifo_data_24_10507
    );
  rx_ext_fifo_data_25 : FD
    port map (
      C => clk,
      D => data_lrx(1),
      Q => rx_ext_fifo_data_25_10508
    );
  rx_ext_fifo_data_26 : FD
    port map (
      C => clk,
      D => data_lrx(2),
      Q => rx_ext_fifo_data_26_10509
    );
  rx_ext_fifo_data_27 : FD
    port map (
      C => clk,
      D => data_lrx(3),
      Q => rx_ext_fifo_data_27_10510
    );
  rx_ext_fifo_data_28 : FD
    port map (
      C => clk,
      D => data_lrx(4),
      Q => rx_ext_fifo_data_28_10511
    );
  rx_ext_fifo_data_29 : FD
    port map (
      C => clk,
      D => data_lrx(5),
      Q => rx_ext_fifo_data_29_10512
    );
  rx_ext_fifo_data_30 : FD
    port map (
      C => clk,
      D => data_lrx(6),
      Q => rx_ext_fifo_data_30_10514
    );
  rx_ext_fifo_data_31 : FD
    port map (
      C => clk,
      D => data_lrx(7),
      Q => rx_ext_fifo_data_31_10515
    );
  rx_ext_fifo_data_32 : FD
    port map (
      C => clk,
      D => fifo1_dout_56_Q,
      Q => rx_ext_fifo_data_32_10516
    );
  rx_ext_fifo_data_33 : FD
    port map (
      C => clk,
      D => fifo1_dout_57_Q,
      Q => rx_ext_fifo_data_33_10517
    );
  rx_ext_fifo_data_34 : FD
    port map (
      C => clk,
      D => fifo1_dout_58_Q,
      Q => rx_ext_fifo_data_34_10518
    );
  rx_ext_fifo_data_35 : FD
    port map (
      C => clk,
      D => fifo1_dout_59_Q,
      Q => rx_ext_fifo_data_35_10519
    );
  rx_ext_fifo_data_36 : FD
    port map (
      C => clk,
      D => fifo1_dout_60_Q,
      Q => rx_ext_fifo_data_36_10520
    );
  rx_ext_fifo_data_37 : FD
    port map (
      C => clk,
      D => fifo1_dout_61_Q,
      Q => rx_ext_fifo_data_37_10521
    );
  rx_ext_fifo_data_38 : FD
    port map (
      C => clk,
      D => fifo1_dout_62_Q,
      Q => rx_ext_fifo_data_38_10522
    );
  rx_ext_fifo_data_39 : FD
    port map (
      C => clk,
      D => fifo1_dout_63_Q,
      Q => rx_ext_fifo_data_39_10523
    );
  rx_ext_fifo_data_40 : FD
    port map (
      C => clk,
      D => fifo1_dout_48_Q,
      Q => rx_ext_fifo_data_40_10525
    );
  rx_ext_fifo_data_41 : FD
    port map (
      C => clk,
      D => fifo1_dout_49_Q,
      Q => rx_ext_fifo_data_41_10526
    );
  rx_ext_fifo_data_42 : FD
    port map (
      C => clk,
      D => fifo1_dout_50_Q,
      Q => rx_ext_fifo_data_42_10527
    );
  rx_ext_fifo_data_43 : FD
    port map (
      C => clk,
      D => fifo1_dout_51_Q,
      Q => rx_ext_fifo_data_43_10528
    );
  rx_ext_fifo_data_44 : FD
    port map (
      C => clk,
      D => fifo1_dout_52_Q,
      Q => rx_ext_fifo_data_44_10529
    );
  rx_ext_fifo_data_45 : FD
    port map (
      C => clk,
      D => fifo1_dout_53_Q,
      Q => rx_ext_fifo_data_45_10530
    );
  rx_ext_fifo_data_46 : FD
    port map (
      C => clk,
      D => fifo1_dout_54_Q,
      Q => rx_ext_fifo_data_46_10531
    );
  rx_ext_fifo_data_47 : FD
    port map (
      C => clk,
      D => fifo1_dout_55_Q,
      Q => rx_ext_fifo_data_47_10532
    );
  rx_ext_fifo_data_48 : FD
    port map (
      C => clk,
      D => fifo1_dout_40_Q,
      Q => rx_ext_fifo_data_48_10533
    );
  rx_ext_fifo_data_49 : FD
    port map (
      C => clk,
      D => fifo1_dout_41_Q,
      Q => rx_ext_fifo_data_49_10534
    );
  rx_ext_fifo_data_50 : FD
    port map (
      C => clk,
      D => fifo1_dout_42_Q,
      Q => rx_ext_fifo_data_50_10536
    );
  rx_ext_fifo_data_51 : FD
    port map (
      C => clk,
      D => fifo1_dout_43_Q,
      Q => rx_ext_fifo_data_51_10537
    );
  rx_ext_fifo_data_52 : FD
    port map (
      C => clk,
      D => fifo1_dout_44_Q,
      Q => rx_ext_fifo_data_52_10538
    );
  rx_ext_fifo_data_53 : FD
    port map (
      C => clk,
      D => fifo1_dout_45_Q,
      Q => rx_ext_fifo_data_53_10539
    );
  rx_ext_fifo_data_54 : FD
    port map (
      C => clk,
      D => fifo1_dout_46_Q,
      Q => rx_ext_fifo_data_54_10540
    );
  rx_ext_fifo_data_55 : FD
    port map (
      C => clk,
      D => fifo1_dout_47_Q,
      Q => rx_ext_fifo_data_55_10541
    );
  rx_ext_fifo_data_56 : FD
    port map (
      C => clk,
      D => fifo1_dout_32_Q,
      Q => rx_ext_fifo_data_56_10542
    );
  rx_ext_fifo_data_57 : FD
    port map (
      C => clk,
      D => fifo1_dout_33_Q,
      Q => rx_ext_fifo_data_57_10543
    );
  rx_ext_fifo_data_58 : FD
    port map (
      C => clk,
      D => fifo1_dout_34_Q,
      Q => rx_ext_fifo_data_58_10544
    );
  rx_ext_fifo_data_59 : FD
    port map (
      C => clk,
      D => fifo1_dout_35_Q,
      Q => rx_ext_fifo_data_59_10545
    );
  rx_ext_fifo_data_60 : FD
    port map (
      C => clk,
      D => fifo1_dout_36_Q,
      Q => rx_ext_fifo_data_60_10547
    );
  rx_ext_fifo_data_61 : FD
    port map (
      C => clk,
      D => fifo1_dout_37_Q,
      Q => rx_ext_fifo_data_61_10548
    );
  rx_ext_fifo_data_62 : FD
    port map (
      C => clk,
      D => fifo1_dout_38_Q,
      Q => rx_ext_fifo_data_62_10549
    );
  rx_ext_fifo_data_63 : FD
    port map (
      C => clk,
      D => fifo1_dout_39_Q,
      Q => rx_ext_fifo_data_63_10550
    );
  tlp_cp_dw2_6 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_38_Q,
      Q => tlp_cp_dw2_6_Q
    );
  tlp_cp_dw2_8 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_40_Q,
      Q => tlp_cp_dw2_8_Q
    );
  tlp_cp_dw2_9 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_41_Q,
      Q => tlp_cp_dw2_9_Q
    );
  tlp_cp_dw2_10 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_42_Q,
      Q => tlp_cp_dw2_10_Q
    );
  tlp_cp_dw2_11 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_43_Q,
      Q => tlp_cp_dw2_11_Q
    );
  tlp_cp_dw2_12 : FDE
    port map (
      C => clk,
      CE => stf_FSM_FFd3_10560,
      D => fifo1_dout_44_Q,
      Q => tlp_cp_dw2_12_Q
    );
  rx_ext_fifo_adr_0 : FD
    port map (
      C => clk,
      D => adr_cnt(0),
      Q => rx_ext_fifo_adr_0_10481
    );
  rx_ext_fifo_adr_1 : FD
    port map (
      C => clk,
      D => adr_cnt(1),
      Q => rx_ext_fifo_adr_1_10482
    );
  rx_ext_fifo_adr_2 : FD
    port map (
      C => clk,
      D => adr_cnt(2),
      Q => rx_ext_fifo_adr_2_10483
    );
  rx_ext_fifo_adr_3 : FD
    port map (
      C => clk,
      D => adr_rx(3),
      Q => rx_ext_fifo_adr_3_10484
    );
  rx_ext_fifo_adr_4 : FD
    port map (
      C => clk,
      D => tlp_cp_dw2_8_Q,
      Q => rx_ext_fifo_adr_4_10485
    );
  rx_ext_fifo_adr_5 : FD
    port map (
      C => clk,
      D => tlp_cp_dw2_9_Q,
      Q => rx_ext_fifo_adr_5_10486
    );
  rx_ext_fifo_adr_6 : FD
    port map (
      C => clk,
      D => tlp_cp_dw2_10_Q,
      Q => rx_ext_fifo_adr_6_10487
    );
  rx_ext_fifo_adr_7 : FD
    port map (
      C => clk,
      D => tlp_cp_dw2_11_Q,
      Q => rx_ext_fifo_adr_7_10488
    );
  rx_ext_fifo_adr_8 : FD
    port map (
      C => clk,
      D => tlp_cp_dw2_12_Q,
      Q => rx_ext_fifo_adr_8_10489
    );
  fifo0_reg : ctrl_fifo64x70st
    port map (
      clk => clk,
      rd_en => fifo0_rd_10313,
      rst => rstpz_10480,
      empty => fifo0_empty,
      wr_en => fifo0_wr,
      valid => NLW_fifo0_reg_valid_UNCONNECTED,
      full => NLW_fifo0_reg_full_UNCONNECTED,
      prog_empty => NLW_fifo0_reg_prog_empty_UNCONNECTED,
      prog_full => fifo0_paf,
      dout(69) => fifo0_dout_69_Q,
      dout(68) => fifo0_dout_68_Q,
      dout(67) => NLW_fifo0_reg_dout_67_UNCONNECTED,
      dout(66) => NLW_fifo0_reg_dout_66_UNCONNECTED,
      dout(65) => NLW_fifo0_reg_dout_65_UNCONNECTED,
      dout(64) => NLW_fifo0_reg_dout_64_UNCONNECTED,
      dout(63) => NLW_fifo0_reg_dout_63_UNCONNECTED,
      dout(62) => fifo0_dout_62_Q,
      dout(61) => NLW_fifo0_reg_dout_61_UNCONNECTED,
      dout(60) => NLW_fifo0_reg_dout_60_UNCONNECTED,
      dout(59) => NLW_fifo0_reg_dout_59_UNCONNECTED,
      dout(58) => NLW_fifo0_reg_dout_58_UNCONNECTED,
      dout(57) => NLW_fifo0_reg_dout_57_UNCONNECTED,
      dout(56) => NLW_fifo0_reg_dout_56_UNCONNECTED,
      dout(55) => NLW_fifo0_reg_dout_55_UNCONNECTED,
      dout(54) => fifo0_dout_54_Q,
      dout(53) => fifo0_dout_53_Q,
      dout(52) => fifo0_dout_52_Q,
      dout(51) => NLW_fifo0_reg_dout_51_UNCONNECTED,
      dout(50) => NLW_fifo0_reg_dout_50_UNCONNECTED,
      dout(49) => fifo0_dout_49_Q,
      dout(48) => fifo0_dout_48_Q,
      dout(47) => fifo0_dout_47_Q,
      dout(46) => fifo0_dout_46_Q,
      dout(45) => fifo0_dout_45_Q,
      dout(44) => fifo0_dout_44_Q,
      dout(43) => fifo0_dout_43_Q,
      dout(42) => fifo0_dout_42_Q,
      dout(41) => fifo0_dout_41_Q,
      dout(40) => fifo0_dout_40_Q,
      dout(39) => fifo0_dout_39_Q,
      dout(38) => fifo0_dout_38_Q,
      dout(37) => fifo0_dout_37_Q,
      dout(36) => fifo0_dout_36_Q,
      dout(35) => fifo0_dout_35_Q,
      dout(34) => fifo0_dout_34_Q,
      dout(33) => NLW_fifo0_reg_dout_33_UNCONNECTED,
      dout(32) => NLW_fifo0_reg_dout_32_UNCONNECTED,
      dout(31) => fifo0_dout_31_Q,
      dout(30) => fifo0_dout_30_Q,
      dout(29) => fifo0_dout_29_Q,
      dout(28) => fifo0_dout_28_Q,
      dout(27) => fifo0_dout_27_Q,
      dout(26) => fifo0_dout_26_Q,
      dout(25) => fifo0_dout_25_Q,
      dout(24) => fifo0_dout_24_Q,
      dout(23) => fifo0_dout_23_Q,
      dout(22) => fifo0_dout_22_Q,
      dout(21) => fifo0_dout_21_Q,
      dout(20) => fifo0_dout_20_Q,
      dout(19) => fifo0_dout_19_Q,
      dout(18) => fifo0_dout_18_Q,
      dout(17) => fifo0_dout_17_Q,
      dout(16) => fifo0_dout_16_Q,
      dout(15) => fifo0_dout_15_Q,
      dout(14) => fifo0_dout_14_Q,
      dout(13) => fifo0_dout_13_Q,
      dout(12) => fifo0_dout_12_Q,
      dout(11) => fifo0_dout_11_Q,
      dout(10) => fifo0_dout_10_Q,
      dout(9) => fifo0_dout_9_Q,
      dout(8) => fifo0_dout_8_Q,
      dout(7) => fifo0_dout_7_Q,
      dout(6) => fifo0_dout_6_Q,
      dout(5) => fifo0_dout_5_Q,
      dout(4) => fifo0_dout_4_Q,
      dout(3) => fifo0_dout_3_Q,
      dout(2) => fifo0_dout_2_Q,
      dout(1) => fifo0_dout_1_Q,
      dout(0) => fifo0_dout_0_Q,
      din(69) => fifo_din(69),
      din(68) => fifo_din(68),
      din(67) => fifo_din(67),
      din(66) => fifo_din(66),
      din(65) => fifo_din(65),
      din(64) => fifo_din(64),
      din(63) => fifo_din(63),
      din(62) => fifo_din(62),
      din(61) => fifo_din(61),
      din(60) => fifo_din(60),
      din(59) => fifo_din(59),
      din(58) => fifo_din(58),
      din(57) => fifo_din(57),
      din(56) => fifo_din(56),
      din(55) => fifo_din(55),
      din(54) => fifo_din(54),
      din(53) => fifo_din(53),
      din(52) => fifo_din(52),
      din(51) => fifo_din(51),
      din(50) => fifo_din(50),
      din(49) => fifo_din(49),
      din(48) => fifo_din(48),
      din(47) => fifo_din(47),
      din(46) => fifo_din(46),
      din(45) => fifo_din(45),
      din(44) => fifo_din(44),
      din(43) => fifo_din(43),
      din(42) => fifo_din(42),
      din(41) => fifo_din(41),
      din(40) => fifo_din(40),
      din(39) => fifo_din(39),
      din(38) => fifo_din(38),
      din(37) => fifo_din(37),
      din(36) => fifo_din(36),
      din(35) => fifo_din(35),
      din(34) => fifo_din(34),
      din(33) => fifo_din(33),
      din(32) => fifo_din(32),
      din(31) => fifo_din(31),
      din(30) => fifo_din(30),
      din(29) => fifo_din(29),
      din(28) => fifo_din(28),
      din(27) => fifo_din(27),
      din(26) => fifo_din(26),
      din(25) => fifo_din(25),
      din(24) => fifo_din(24),
      din(23) => fifo_din(23),
      din(22) => fifo_din(22),
      din(21) => fifo_din(21),
      din(20) => fifo_din(20),
      din(19) => fifo_din(19),
      din(18) => fifo_din(18),
      din(17) => fifo_din(17),
      din(16) => fifo_din(16),
      din(15) => fifo_din(15),
      din(14) => fifo_din(14),
      din(13) => fifo_din(13),
      din(12) => fifo_din(12),
      din(11) => fifo_din(11),
      din(10) => fifo_din(10),
      din(9) => fifo_din(9),
      din(8) => fifo_din(8),
      din(7) => fifo_din(7),
      din(6) => fifo_din(6),
      din(5) => fifo_din(5),
      din(4) => fifo_din(4),
      din(3) => fifo_din(3),
      din(2) => fifo_din(2),
      din(1) => fifo_din(1),
      din(0) => fifo_din(0)
    );
  fifo1_cmpl : ctrl_fifo64x70st
    port map (
      clk => clk,
      rd_en => fifo1_rd_x,
      rst => rstpz_10480,
      empty => NLW_fifo1_cmpl_empty_UNCONNECTED,
      wr_en => fifo1_wr,
      valid => fifo1_valid,
      full => NLW_fifo1_cmpl_full_UNCONNECTED,
      prog_empty => fifo1_pae,
      prog_full => fifo1_paf,
      dout(69) => NLW_fifo1_cmpl_dout_69_UNCONNECTED,
      dout(68) => NLW_fifo1_cmpl_dout_68_UNCONNECTED,
      dout(67) => NLW_fifo1_cmpl_dout_67_UNCONNECTED,
      dout(66) => NLW_fifo1_cmpl_dout_66_UNCONNECTED,
      dout(65) => fifo1_dout_65_Q,
      dout(64) => NLW_fifo1_cmpl_dout_64_UNCONNECTED,
      dout(63) => fifo1_dout_63_Q,
      dout(62) => fifo1_dout_62_Q,
      dout(61) => fifo1_dout_61_Q,
      dout(60) => fifo1_dout_60_Q,
      dout(59) => fifo1_dout_59_Q,
      dout(58) => fifo1_dout_58_Q,
      dout(57) => fifo1_dout_57_Q,
      dout(56) => fifo1_dout_56_Q,
      dout(55) => fifo1_dout_55_Q,
      dout(54) => fifo1_dout_54_Q,
      dout(53) => fifo1_dout_53_Q,
      dout(52) => fifo1_dout_52_Q,
      dout(51) => fifo1_dout_51_Q,
      dout(50) => fifo1_dout_50_Q,
      dout(49) => fifo1_dout_49_Q,
      dout(48) => fifo1_dout_48_Q,
      dout(47) => fifo1_dout_47_Q,
      dout(46) => fifo1_dout_46_Q,
      dout(45) => fifo1_dout_45_Q,
      dout(44) => fifo1_dout_44_Q,
      dout(43) => fifo1_dout_43_Q,
      dout(42) => fifo1_dout_42_Q,
      dout(41) => fifo1_dout_41_Q,
      dout(40) => fifo1_dout_40_Q,
      dout(39) => fifo1_dout_39_Q,
      dout(38) => fifo1_dout_38_Q,
      dout(37) => fifo1_dout_37_Q,
      dout(36) => fifo1_dout_36_Q,
      dout(35) => fifo1_dout_35_Q,
      dout(34) => fifo1_dout_34_Q,
      dout(33) => fifo1_dout_33_Q,
      dout(32) => fifo1_dout_32_Q,
      dout(31) => fifo1_dout_31_Q,
      dout(30) => fifo1_dout_30_Q,
      dout(29) => fifo1_dout_29_Q,
      dout(28) => fifo1_dout_28_Q,
      dout(27) => fifo1_dout_27_Q,
      dout(26) => fifo1_dout_26_Q,
      dout(25) => fifo1_dout_25_Q,
      dout(24) => fifo1_dout_24_Q,
      dout(23) => fifo1_dout_23_Q,
      dout(22) => fifo1_dout_22_Q,
      dout(21) => fifo1_dout_21_Q,
      dout(20) => fifo1_dout_20_Q,
      dout(19) => fifo1_dout_19_Q,
      dout(18) => fifo1_dout_18_Q,
      dout(17) => fifo1_dout_17_Q,
      dout(16) => fifo1_dout_16_Q,
      dout(15) => fifo1_dout_15_Q,
      dout(14) => fifo1_dout_14_Q,
      dout(13) => fifo1_dout_13_Q,
      dout(12) => fifo1_dout_12_Q,
      dout(11) => fifo1_dout_11_Q,
      dout(10) => fifo1_dout_10_Q,
      dout(9) => fifo1_dout_9_Q,
      dout(8) => fifo1_dout_8_Q,
      dout(7) => fifo1_dout_7_Q,
      dout(6) => fifo1_dout_6_Q,
      dout(5) => fifo1_dout_5_Q,
      dout(4) => fifo1_dout_4_Q,
      dout(3) => fifo1_dout_3_Q,
      dout(2) => fifo1_dout_2_Q,
      dout(1) => fifo1_dout_1_Q,
      dout(0) => fifo1_dout_0_Q,
      din(69) => fifo_din(69),
      din(68) => fifo_din(68),
      din(67) => fifo_din(67),
      din(66) => fifo_din(66),
      din(65) => fifo_din(65),
      din(64) => fifo_din(64),
      din(63) => fifo_din(63),
      din(62) => fifo_din(62),
      din(61) => fifo_din(61),
      din(60) => fifo_din(60),
      din(59) => fifo_din(59),
      din(58) => fifo_din(58),
      din(57) => fifo_din(57),
      din(56) => fifo_din(56),
      din(55) => fifo_din(55),
      din(54) => fifo_din(54),
      din(53) => fifo_din(53),
      din(52) => fifo_din(52),
      din(51) => fifo_din(51),
      din(50) => fifo_din(50),
      din(49) => fifo_din(49),
      din(48) => fifo_din(48),
      din(47) => fifo_din(47),
      din(46) => fifo_din(46),
      din(45) => fifo_din(45),
      din(44) => fifo_din(44),
      din(43) => fifo_din(43),
      din(42) => fifo_din(42),
      din(41) => fifo_din(41),
      din(40) => fifo_din(40),
      din(39) => fifo_din(39),
      din(38) => fifo_din(38),
      din(37) => fifo_din(37),
      din(36) => fifo_din(36),
      din(35) => fifo_din(35),
      din(34) => fifo_din(34),
      din(33) => fifo_din(33),
      din(32) => fifo_din(32),
      din(31) => fifo_din(31),
      din(30) => fifo_din(30),
      din(29) => fifo_din(29),
      din(28) => fifo_din(28),
      din(27) => fifo_din(27),
      din(26) => fifo_din(26),
      din(25) => fifo_din(25),
      din(24) => fifo_din(24),
      din(23) => fifo_din(23),
      din(22) => fifo_din(22),
      din(21) => fifo_din(21),
      din(20) => fifo_din(20),
      din(19) => fifo_din(19),
      din(18) => fifo_din(18),
      din(17) => fifo_din(17),
      din(16) => fifo_din(16),
      din(15) => fifo_din(15),
      din(14) => fifo_din(14),
      din(13) => fifo_din(13),
      din(12) => fifo_din(12),
      din(11) => fifo_din(11),
      din(10) => fifo_din(10),
      din(9) => fifo_din(9),
      din(8) => fifo_din(8),
      din(7) => fifo_din(7),
      din(6) => fifo_din(6),
      din(5) => fifo_din(5),
      din(4) => fifo_din(4),
      din(3) => fifo_din(3),
      din(2) => fifo_din(2),
      din(1) => fifo_din(1),
      din(0) => fifo_din(0)
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstpz_10480,
      Q => stp_FSM_FFd1_10567
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd4_In,
      R => rstpz_10480,
      Q => stp_FSM_FFd4_10571
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd5_In,
      R => rstpz_10480,
      Q => stp_FSM_FFd5_10573
    );
  stp_FSM_FFd7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd7_In,
      R => rstpz_10480,
      Q => stp_FSM_FFd7_10576
    );
  stp_FSM_FFd8 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd8_In,
      S => rstpz_10480,
      Q => stp_FSM_FFd8_10578
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd4_10571,
      R => rstpz_10480,
      Q => stp_FSM_FFd3_10570
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd7_10576,
      R => rstpz_10480,
      Q => stp_FSM_FFd6_10575
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_10570,
      R => rstpz_10480,
      Q => stp_FSM_FFd2_10569
    );
  stf_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd1_In,
      R => rstpz_10480,
      Q => stf_FSM_FFd1_10556
    );
  stf_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd2_In,
      R => rstpz_10480,
      Q => stf_FSM_FFd2_10558
    );
  stf_FSM_FFd7 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd7_In,
      S => rstpz_10480,
      Q => stf_FSM_FFd7_10565
    );
  stf_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd6_In,
      R => rstpz_10480,
      Q => stf_FSM_FFd6_10563
    );
  stf_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd6_10563,
      R => rstpz_10480,
      Q => stf_FSM_FFd5_10562
    );
  stf_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd5_10562,
      R => rstpz_10480,
      Q => stf_FSM_FFd4_10561
    );
  stf_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stf_FSM_FFd4_10561,
      R => rstpz_10480,
      Q => stf_FSM_FFd3_10560
    );
  stp_FSM_FFd7_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => fifo0_empty,
      I1 => stp_FSM_FFd8_10578,
      O => stp_FSM_FFd7_In
    );
  stp_FSM_FFd4_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => fifo0_empty,
      I1 => stp_FSM_FFd5_10573,
      O => stp_FSM_FFd4_In
    );
  stf_FSM_FFd6_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => fifo1_pae,
      I1 => stf_FSM_FFd7_10565,
      O => stf_FSM_FFd6_In
    );
  adr_rx_3_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => tlp_cp_dw2_6_Q,
      I1 => adr_cnt(3),
      O => adr_rx(3)
    );
  Madd_adr_cnt_2_0_add0000_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => adr_cnt(1),
      I1 => adr_cnt(0),
      O => adr_cnt_2_0_add0000(1)
    );
  stp_FSM_FFd5_In1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => fifo0_empty,
      I1 => stp_FSM_FFd5_10573,
      I2 => stp_FSM_FFd6_10575,
      O => stp_FSM_FFd5_In
    );
  stp_FSM_FFd1_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd2_10569,
      I1 => tx_rx_engine_complete_reg,
      I2 => stp_FSM_FFd1_10567,
      O => stp_FSM_FFd1_In
    );
  stf_FSM_FFd7_In1 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => fifo1_pae,
      I1 => stf_FSM_FFd7_10565,
      I2 => stf_FSM_FFd1_10556,
      O => stf_FSM_FFd7_In
    );
  Madd_adr_cnt_2_0_add0000_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => adr_cnt(0),
      I1 => adr_cnt(2),
      I2 => adr_cnt(1),
      O => adr_cnt_2_0_add0000(2)
    );
  stp_FSM_FFd8_In1 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => tx_rx_engine_complete_reg,
      I1 => stp_FSM_FFd1_10567,
      I2 => fifo0_empty,
      I3 => stp_FSM_FFd8_10578,
      O => stp_FSM_FFd8_In
    );
  stf_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"FF8A8A8A"
    )
    port map (
      I0 => stf_FSM_FFd2_10558,
      I1 => fifo1_dout_65_Q,
      I2 => fifo1_valid,
      I3 => stf_FSM_FFd3_10560,
      I4 => tlp_cp_dw0(30),
      O => stf_FSM_FFd2_In
    );
  stf_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"4444F444"
    )
    port map (
      I0 => tlp_cp_dw0(30),
      I1 => stf_FSM_FFd3_10560,
      I2 => stf_FSM_FFd2_10558,
      I3 => fifo1_valid,
      I4 => fifo1_dout_65_Q,
      O => stf_FSM_FFd1_In
    );
  fifo0_rd_mux00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => stp_FSM_FFd7_10576,
      I1 => stp_FSM_FFd5_10573,
      I2 => fifo0_rd_10313,
      I3 => stp_FSM_FFd2_10569,
      I4 => stp_FSM_FFd1_10567,
      I5 => stp_FSM_FFd4_10571,
      O => fifo0_rd_mux0000
    );
  fifo1_wr1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => fifo_wr_z_10470,
      I1 => fifo1_wr_en_10392,
      I2 => fifo1_wr_en_z_10395,
      O => fifo1_wr
    );
  fifo1_rd_x1 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => fifo1_rd_10386,
      I1 => data_rx_we_en_10255,
      I2 => fifo1_dout_65_Q,
      O => fifo1_rd_x
    );
  fifo0_wr1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => fifo_wr_z_10470,
      I1 => fifo0_wr_en_10316,
      I2 => fifo0_wr_en_z_10318,
      O => fifo0_wr
    );
  data_rx_we1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => fifo1_valid,
      I1 => data_rx_we_en_10255,
      O => data_rx_we
    );
  adr_cnt_3_not00011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => data_rx_we_en_10255,
      I1 => fifo1_valid,
      I2 => adr_cnt(2),
      I3 => adr_cnt(0),
      I4 => adr_cnt(1),
      O => adr_cnt_3_not0001
    );
  fifo1_rd_mux0000_SW0 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => stf_FSM_FFd2_10558,
      I1 => fifo1_valid,
      I2 => fifo1_dout_65_Q,
      O => N0
    );
  fifo1_rd_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFFAFAFAEA"
    )
    port map (
      I0 => stf_FSM_FFd6_10563,
      I1 => stf_FSM_FFd5_10562,
      I2 => fifo1_rd_10386,
      I3 => stf_FSM_FFd1_10556,
      I4 => stf_FSM_FFd3_10560,
      I5 => N0,
      O => fifo1_rd_mux0000_10387
    );
  reg_access_req_wr_1_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_request_reg_wr,
      I1 => fifo0_dout_69_Q,
      O => reg_access_req_wr(1)
    );
  reg_access_req_wr_0_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_request_reg_wr,
      I1 => fifo0_dout_68_Q,
      O => reg_access_req_wr(0)
    );
  reg_access_req_rd_1_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => NlwRenamedSig_OI_request_reg_rd,
      I1 => fifo0_dout_69_Q,
      O => reg_access_req_rd(1)
    );
  reg_access_req_rd_0_and00001 : LUT3
    generic map(
      INIT => X"A2"
    )
    port map (
      I0 => NlwRenamedSig_OI_request_reg_rd,
      I1 => fifo0_dout_69_Q,
      I2 => fifo0_dout_68_Q,
      O => reg_access_req_rd(0)
    );
  data_rx_we_en_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stf_FSM_FFd5_10562,
      I1 => stf_FSM_FFd1_10556,
      I2 => stf_FSM_FFd3_10560,
      I3 => stf_FSM_FFd6_10563,
      O => N2
    );
  data_rx_we_en_mux0000 : LUT6
    generic map(
      INIT => X"FFA2FFA2FFA2A2A2"
    )
    port map (
      I0 => stf_FSM_FFd2_10558,
      I1 => fifo1_valid,
      I2 => fifo1_dout_65_Q,
      I3 => data_rx_we_en_10255,
      I4 => stf_FSM_FFd4_10561,
      I5 => N2,
      O => data_rx_we_en_mux0000_10256
    );
  adr_cnt_0_or00001 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => stf_FSM_FFd5_10562,
      I1 => stf_FSM_FFd4_10561,
      I2 => stf_FSM_FFd3_10560,
      I3 => stf_FSM_FFd1_10556,
      I4 => stf_FSM_FFd7_10565,
      I5 => stf_FSM_FFd6_10563,
      O => adr_cnt_0_or0000
    );
  request_reg_wr_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd3_10570,
      I1 => stp_FSM_FFd4_10571,
      I2 => stp_FSM_FFd7_10576,
      I3 => stp_FSM_FFd1_10567,
      O => N4
    );
  request_reg_wr_mux0000 : LUT6
    generic map(
      INIT => X"FF88FF88FF88FA88"
    )
    port map (
      I0 => stp_FSM_FFd2_10569,
      I1 => tlp_dw0_30_Q,
      I2 => stp_FSM_FFd5_10573,
      I3 => NlwRenamedSig_OI_request_reg_wr,
      I4 => stp_FSM_FFd6_10575,
      I5 => N4,
      O => request_reg_wr_mux0000_10478
    );
  request_reg_rd_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd3_10570,
      I1 => stp_FSM_FFd4_10571,
      I2 => stp_FSM_FFd7_10576,
      I3 => stp_FSM_FFd1_10567,
      O => N6
    );
  request_reg_rd_mux0000 : LUT6
    generic map(
      INIT => X"FF22FF22FF22FA22"
    )
    port map (
      I0 => stp_FSM_FFd2_10569,
      I1 => tlp_dw0_30_Q,
      I2 => stp_FSM_FFd5_10573,
      I3 => NlwRenamedSig_OI_request_reg_rd,
      I4 => stp_FSM_FFd6_10575,
      I5 => N6,
      O => request_reg_rd_mux0000_10476
    );
  fifo_wr_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => fifo0_paf,
      I1 => fifo1_paf,
      I2 => trn_rx_trn_rsrc_rdy_n,
      O => fifo_wr_or0000
    );
  fifo0_wr_en_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => N1,
      I1 => trn_rx_trn_rd(57),
      I2 => trn_rx_trn_rd(59),
      O => fifo0_wr_en_and0000
    );
  fifo1_wr_en_and00002 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => trn_rx_trn_rd(57),
      I1 => trn_rx_trn_rd(59),
      I2 => trn_rx_trn_rd(62),
      I3 => N1,
      O => fifo1_wr_en_and0000
    );
  fifo1_wr_en_and000011 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => trn_rx_trn_rd(58),
      I1 => trn_rx_trn_rd(60),
      I2 => trn_rx_trn_rd(61),
      I3 => trn_rx_trn_rd(63),
      I4 => trn_rx_trn_rsof_n,
      I5 => fifo_wr_or0000,
      O => N1
    );
  trn_rdst_rdy_n1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => fifo0_paf,
      I1 => fifo1_paf,
      O => trn_rx_back_trn_rdst_rdy_n
    );
  fifo1_wr_en_or00001 : LUT5
    generic map(
      INIT => X"FFFF0001"
    )
    port map (
      I0 => trn_rx_trn_reof_n,
      I1 => fifo0_paf,
      I2 => fifo1_paf,
      I3 => trn_rx_trn_rsrc_rdy_n,
      I4 => rstpz_10480,
      O => fifo1_wr_en_or0000
    );
  Madd_adr_cnt_2_0_add0000_xor_0_11_INV_0 : INV
    port map (
      I => adr_cnt(0),
      O => adr_cnt_2_0_add0000(0)
    );
  fifo1_valid_inv1_INV_0 : INV
    port map (
      I => fifo1_valid,
      O => fifo1_valid_inv
    );
  fifo_din_not00031_INV_0 : INV
    port map (
      I => trn_rx_trn_rbar_hit_n(0),
      O => fifo_din_not0003
    );
  fifo_din_not00021_INV_0 : INV
    port map (
      I => trn_rx_trn_rbar_hit_n(1),
      O => fifo_din_not0002
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_interrupt is
  port (
    irq : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    cfg_command10 : in STD_LOGIC := 'X'; 
    cfg_interrupt : out STD_LOGIC; 
    cfg_interrupt_assert : out STD_LOGIC; 
    rstp : in STD_LOGIC := 'X'; 
    cfg_interrupt_rdy : in STD_LOGIC := 'X' 
  );
end core64_interrupt;

architecture STRUCTURE of core64_interrupt is
  signal NlwRenamedSig_OI_cfg_interrupt_assert : STD_LOGIC; 
  signal cfg_interrupt_assert_mux0000 : STD_LOGIC; 
  signal cfg_interrupt_mux0001 : STD_LOGIC; 
  signal cnt_4_inv : STD_LOGIC; 
  signal cnt_or0000 : STD_LOGIC; 
  signal irq_en_10195 : STD_LOGIC; 
  signal irq_en_or0000 : STD_LOGIC; 
  signal stp_FSM_FFd1_10198 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_10200 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_10202 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_FSM_FFd4_10204 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal Result : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal cnt : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  cfg_interrupt_assert <= NlwRenamedSig_OI_cfg_interrupt_assert;
  cfg_interrupt_7697 : FD
    port map (
      C => clk,
      D => cfg_interrupt_mux0001,
      Q => cfg_interrupt
    );
  cfg_interrupt_assert_7698 : FD
    port map (
      C => clk,
      D => cfg_interrupt_assert_mux0000,
      Q => NlwRenamedSig_OI_cfg_interrupt_assert
    );
  irq_en : FDR
    port map (
      C => clk,
      D => irq,
      R => irq_en_or0000,
      Q => irq_en_10195
    );
  cnt_0 : FDRE
    port map (
      C => clk,
      CE => cnt_4_inv,
      D => Result(0),
      R => cnt_or0000,
      Q => cnt(0)
    );
  cnt_1 : FDRE
    port map (
      C => clk,
      CE => cnt_4_inv,
      D => Result(1),
      R => cnt_or0000,
      Q => cnt(1)
    );
  cnt_2 : FDRE
    port map (
      C => clk,
      CE => cnt_4_inv,
      D => Result(2),
      R => cnt_or0000,
      Q => cnt(2)
    );
  cnt_3 : FDRE
    port map (
      C => clk,
      CE => cnt_4_inv,
      D => Result(3),
      R => cnt_or0000,
      Q => cnt(3)
    );
  cnt_4 : FDRE
    port map (
      C => clk,
      CE => cnt_4_inv,
      D => Result(4),
      R => cnt_or0000,
      Q => cnt(4)
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstp,
      Q => stp_FSM_FFd1_10198
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd2_In,
      R => rstp,
      Q => stp_FSM_FFd2_10200
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_In,
      R => rstp,
      Q => stp_FSM_FFd3_10202
    );
  stp_FSM_FFd4 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd4_In,
      S => rstp,
      Q => stp_FSM_FFd4_10204
    );
  Mcount_cnt_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => cnt(1),
      I1 => cnt(0),
      O => Result(1)
    );
  Mcount_cnt_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => cnt(0),
      I1 => cnt(2),
      I2 => cnt(1),
      O => Result(2)
    );
  cfg_interrupt_assert_mux00001 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => stp_FSM_FFd3_10202,
      I1 => NlwRenamedSig_OI_cfg_interrupt_assert,
      I2 => stp_FSM_FFd2_10200,
      I3 => stp_FSM_FFd1_10198,
      O => cfg_interrupt_assert_mux0000
    );
  Mcount_cnt_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => cnt(0),
      I1 => cnt(3),
      I2 => cnt(1),
      I3 => cnt(2),
      O => Result(3)
    );
  Mcount_cnt_xor_4_11 : LUT5
    generic map(
      INIT => X"6CCCCCCC"
    )
    port map (
      I0 => cnt(0),
      I1 => cnt(4),
      I2 => cnt(1),
      I3 => cnt(2),
      I4 => cnt(3),
      O => Result(4)
    );
  stp_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"2AFF2A2A"
    )
    port map (
      I0 => stp_FSM_FFd4_10204,
      I1 => cnt(4),
      I2 => irq_en_10195,
      I3 => cfg_interrupt_rdy,
      I4 => stp_FSM_FFd1_10198,
      O => stp_FSM_FFd4_In
    );
  stp_FSM_FFd3_In1 : LUT5
    generic map(
      INIT => X"FF808080"
    )
    port map (
      I0 => stp_FSM_FFd4_10204,
      I1 => irq_en_10195,
      I2 => cnt(4),
      I3 => stp_FSM_FFd3_10202,
      I4 => cfg_interrupt_rdy,
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"8AFF8A8A"
    )
    port map (
      I0 => stp_FSM_FFd2_10200,
      I1 => irq_en_10195,
      I2 => cnt(4),
      I3 => cfg_interrupt_rdy,
      I4 => stp_FSM_FFd3_10202,
      O => stp_FSM_FFd2_In
    );
  stp_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"8888F888"
    )
    port map (
      I0 => cfg_interrupt_rdy,
      I1 => stp_FSM_FFd1_10198,
      I2 => cnt(4),
      I3 => stp_FSM_FFd2_10200,
      I4 => irq_en_10195,
      O => stp_FSM_FFd1_In
    );
  cfg_interrupt_mux00011 : LUT5
    generic map(
      INIT => X"FFFFAFAE"
    )
    port map (
      I0 => stp_FSM_FFd2_10200,
      I1 => stp_FSM_FFd3_10202,
      I2 => cfg_interrupt_rdy,
      I3 => stp_FSM_FFd1_10198,
      I4 => stp_FSM_FFd4_10204,
      O => cfg_interrupt_mux0001
    );
  irq_en_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => rstp,
      I1 => cfg_command10,
      O => irq_en_or0000
    );
  cnt_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd1_10198,
      I1 => rstp,
      I2 => stp_FSM_FFd3_10202,
      O => cnt_or0000
    );
  Mcount_cnt_xor_0_11_INV_0 : INV
    port map (
      I => cnt(0),
      O => Result(0)
    );
  cnt_4_inv1_INV_0 : INV
    port map (
      I => cnt(4),
      O => cnt_4_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_pb_disp is
  port (
    clk : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_data_we : out STD_LOGIC; 
    reg_disp_back_data_we : out STD_LOGIC; 
    pb_master_stb0 : out STD_LOGIC; 
    pb_master_stb1 : out STD_LOGIC; 
    aclk : in STD_LOGIC := 'X'; 
    reg_disp_back_complete : out STD_LOGIC; 
    reg_disp_request_reg_rd : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_irq : out STD_LOGIC; 
    pb_slave_stb0 : in STD_LOGIC := 'X'; 
    pb_slave_stb1 : in STD_LOGIC := 'X'; 
    reg_disp_request_reg_wr : in STD_LOGIC := 'X'; 
    rstp : in STD_LOGIC := 'X'; 
    ext_fifo_disp_data_we : in STD_LOGIC := 'X'; 
    ext_fifo_disp_request_rd : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_allow_wr : out STD_LOGIC; 
    ext_fifo_disp_request_wr : in STD_LOGIC := 'X'; 
    pb_slave_irq : in STD_LOGIC := 'X'; 
    ext_fifo_disp_back_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    ext_fifo_disp_back_dmar : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pb_master_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_master_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_disp_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    pb_master_cmd : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    ext_fifo_disp_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_disp_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_disp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    pb_slave_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_slave_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    ext_fifo_disp_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end core64_pb_disp;

architecture STRUCTURE of core64_pb_disp is
  signal Mshreg_reg_req_rd_z_9734 : STD_LOGIC; 
  signal Mshreg_reg_req_wr_z_9735 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal ex_fifo_stb1_z_9746 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_0_9754 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_1_9755 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_10_9756 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_11_9757 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_12_9758 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_13_9759 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_14_9760 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_15_9761 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_16_9762 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_17_9763 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_18_9764 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_19_9765 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_2_9766 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_20_9767 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_21_9768 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_22_9769 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_23_9770 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_24_9771 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_25_9772 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_26_9773 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_27_9774 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_28_9775 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_29_9776 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_3_9777 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_30_9778 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_31_9779 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_32_9780 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_33_9781 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_34_9782 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_35_9783 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_36_9784 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_37_9785 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_38_9786 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_39_9787 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_4_9788 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_40_9789 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_41_9790 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_42_9791 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_43_9792 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_44_9793 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_45_9794 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_46_9795 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_47_9796 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_48_9797 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_49_9798 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_5_9799 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_50_9800 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_51_9801 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_52_9802 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_53_9803 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_54_9804 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_55_9805 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_56_9806 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_57_9807 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_58_9808 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_59_9809 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_6_9810 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_60_9811 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_61_9812 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_62_9813 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_63_9814 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_7_9815 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_8_9816 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_9_9817 : STD_LOGIC; 
  signal ext_fifo_disp_back_data_we_9818 : STD_LOGIC; 
  signal NlwRenamedSignal_ext_fifo_disp_back_irq : STD_LOGIC; 
  signal ext_fifo_eot_9889 : STD_LOGIC; 
  signal ext_fifo_eot_or0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_fifo_allow_wr : STD_LOGIC; 
  signal fifo_allow_wr_mux0000_9892 : STD_LOGIC; 
  signal fifo_data_en_9893 : STD_LOGIC; 
  signal fifo_data_en_mux0000_9894 : STD_LOGIC; 
  signal master_cmd_1_mux0000 : STD_LOGIC; 
  signal master_cmd_2_mux0000 : STD_LOGIC; 
  signal master_stb0_9931 : STD_LOGIC; 
  signal master_stb0_mux0000_9932 : STD_LOGIC; 
  signal master_stb1 : STD_LOGIC; 
  signal pb_master_data_0_9934 : STD_LOGIC; 
  signal pb_master_data_1_9935 : STD_LOGIC; 
  signal pb_master_data_10_9936 : STD_LOGIC; 
  signal pb_master_data_11_9937 : STD_LOGIC; 
  signal pb_master_data_12_9938 : STD_LOGIC; 
  signal pb_master_data_13_9939 : STD_LOGIC; 
  signal pb_master_data_14_9940 : STD_LOGIC; 
  signal pb_master_data_15_9941 : STD_LOGIC; 
  signal pb_master_data_16_9942 : STD_LOGIC; 
  signal pb_master_data_17_9943 : STD_LOGIC; 
  signal pb_master_data_18_9944 : STD_LOGIC; 
  signal pb_master_data_19_9945 : STD_LOGIC; 
  signal pb_master_data_2_9946 : STD_LOGIC; 
  signal pb_master_data_20_9947 : STD_LOGIC; 
  signal pb_master_data_21_9948 : STD_LOGIC; 
  signal pb_master_data_22_9949 : STD_LOGIC; 
  signal pb_master_data_23_9950 : STD_LOGIC; 
  signal pb_master_data_24_9951 : STD_LOGIC; 
  signal pb_master_data_25_9952 : STD_LOGIC; 
  signal pb_master_data_26_9953 : STD_LOGIC; 
  signal pb_master_data_27_9954 : STD_LOGIC; 
  signal pb_master_data_28_9955 : STD_LOGIC; 
  signal pb_master_data_29_9956 : STD_LOGIC; 
  signal pb_master_data_3_9957 : STD_LOGIC; 
  signal pb_master_data_30_9958 : STD_LOGIC; 
  signal pb_master_data_31_9959 : STD_LOGIC; 
  signal pb_master_data_32_9960 : STD_LOGIC; 
  signal pb_master_data_33_9961 : STD_LOGIC; 
  signal pb_master_data_34_9962 : STD_LOGIC; 
  signal pb_master_data_35_9963 : STD_LOGIC; 
  signal pb_master_data_36_9964 : STD_LOGIC; 
  signal pb_master_data_37_9965 : STD_LOGIC; 
  signal pb_master_data_38_9966 : STD_LOGIC; 
  signal pb_master_data_39_9967 : STD_LOGIC; 
  signal pb_master_data_4_9968 : STD_LOGIC; 
  signal pb_master_data_40_9969 : STD_LOGIC; 
  signal pb_master_data_41_9970 : STD_LOGIC; 
  signal pb_master_data_42_9971 : STD_LOGIC; 
  signal pb_master_data_43_9972 : STD_LOGIC; 
  signal pb_master_data_44_9973 : STD_LOGIC; 
  signal pb_master_data_45_9974 : STD_LOGIC; 
  signal pb_master_data_46_9975 : STD_LOGIC; 
  signal pb_master_data_47_9976 : STD_LOGIC; 
  signal pb_master_data_48_9977 : STD_LOGIC; 
  signal pb_master_data_49_9978 : STD_LOGIC; 
  signal pb_master_data_5_9979 : STD_LOGIC; 
  signal pb_master_data_50_9980 : STD_LOGIC; 
  signal pb_master_data_51_9981 : STD_LOGIC; 
  signal pb_master_data_52_9982 : STD_LOGIC; 
  signal pb_master_data_53_9983 : STD_LOGIC; 
  signal pb_master_data_54_9984 : STD_LOGIC; 
  signal pb_master_data_55_9985 : STD_LOGIC; 
  signal pb_master_data_56_9986 : STD_LOGIC; 
  signal pb_master_data_57_9987 : STD_LOGIC; 
  signal pb_master_data_58_9988 : STD_LOGIC; 
  signal pb_master_data_59_9989 : STD_LOGIC; 
  signal pb_master_data_6_9990 : STD_LOGIC; 
  signal pb_master_data_60_9991 : STD_LOGIC; 
  signal pb_master_data_61_9992 : STD_LOGIC; 
  signal pb_master_data_62_9993 : STD_LOGIC; 
  signal pb_master_data_63_9994 : STD_LOGIC; 
  signal pb_master_data_7_9995 : STD_LOGIC; 
  signal pb_master_data_8_9996 : STD_LOGIC; 
  signal pb_master_data_9_9997 : STD_LOGIC; 
  signal pb_master_stb0_9998 : STD_LOGIC; 
  signal pb_master_stb1_9999 : STD_LOGIC; 
  signal pb_slave_stb1_inv : STD_LOGIC; 
  signal pb_slave_stb1_z_10074 : STD_LOGIC; 
  signal NlwRenamedSig_OI_reg_disp_back_complete : STD_LOGIC; 
  signal reg_disp_back_data_0_10083 : STD_LOGIC; 
  signal reg_disp_back_data_1_10084 : STD_LOGIC; 
  signal reg_disp_back_data_10_10085 : STD_LOGIC; 
  signal reg_disp_back_data_11_10086 : STD_LOGIC; 
  signal reg_disp_back_data_12_10087 : STD_LOGIC; 
  signal reg_disp_back_data_13_10088 : STD_LOGIC; 
  signal reg_disp_back_data_14_10089 : STD_LOGIC; 
  signal reg_disp_back_data_15_10090 : STD_LOGIC; 
  signal reg_disp_back_data_16_10091 : STD_LOGIC; 
  signal reg_disp_back_data_17_10092 : STD_LOGIC; 
  signal reg_disp_back_data_18_10093 : STD_LOGIC; 
  signal reg_disp_back_data_19_10094 : STD_LOGIC; 
  signal reg_disp_back_data_2_10095 : STD_LOGIC; 
  signal reg_disp_back_data_20_10096 : STD_LOGIC; 
  signal reg_disp_back_data_21_10097 : STD_LOGIC; 
  signal reg_disp_back_data_22_10098 : STD_LOGIC; 
  signal reg_disp_back_data_23_10099 : STD_LOGIC; 
  signal reg_disp_back_data_24_10100 : STD_LOGIC; 
  signal reg_disp_back_data_25_10101 : STD_LOGIC; 
  signal reg_disp_back_data_26_10102 : STD_LOGIC; 
  signal reg_disp_back_data_27_10103 : STD_LOGIC; 
  signal reg_disp_back_data_28_10104 : STD_LOGIC; 
  signal reg_disp_back_data_29_10105 : STD_LOGIC; 
  signal reg_disp_back_data_3_10106 : STD_LOGIC; 
  signal reg_disp_back_data_30_10107 : STD_LOGIC; 
  signal reg_disp_back_data_31_10108 : STD_LOGIC; 
  signal reg_disp_back_data_4_10109 : STD_LOGIC; 
  signal reg_disp_back_data_5_10110 : STD_LOGIC; 
  signal reg_disp_back_data_6_10111 : STD_LOGIC; 
  signal reg_disp_back_data_7_10112 : STD_LOGIC; 
  signal reg_disp_back_data_8_10113 : STD_LOGIC; 
  signal reg_disp_back_data_9_10114 : STD_LOGIC; 
  signal NlwRenamedSig_OI_reg_disp_back_data_we : STD_LOGIC; 
  signal reg_disp_back_complete_mux0000 : STD_LOGIC; 
  signal reg_disp_back_data_we_mux0000 : STD_LOGIC; 
  signal reg_req_rd_z_10152 : STD_LOGIC; 
  signal reg_req_wr_z_10153 : STD_LOGIC; 
  signal reg_stb1_10154 : STD_LOGIC; 
  signal reg_stb1_mux0000 : STD_LOGIC; 
  signal rstpz_10157 : STD_LOGIC; 
  signal stp_FSM_FFd1_10158 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_10160 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_10162 : STD_LOGIC; 
  signal stp_FSM_FFd3_In_10163 : STD_LOGIC; 
  signal stp_FSM_FFd4_10164 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal stp_FSM_FFd5_10166 : STD_LOGIC; 
  signal stp_FSM_FFd5_In : STD_LOGIC; 
  signal stp_FSM_FFd6_10168 : STD_LOGIC; 
  signal stp_FSM_FFd7_10169 : STD_LOGIC; 
  signal stp_FSM_FFd7_In : STD_LOGIC; 
  signal stp_FSM_FFd8_10171 : STD_LOGIC; 
  signal stp_FSM_FFd8_In : STD_LOGIC; 
  signal stp_FSM_FFd9_10173 : STD_LOGIC; 
  signal stp_FSM_FFd9_In_10174 : STD_LOGIC; 
  signal NLW_Mshreg_reg_req_rd_z_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_reg_req_wr_z_Q15_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSignal_ext_fifo_disp_back_dmar : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_master_cmd : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal master_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
begin
  ext_fifo_disp_back_data_we <= ext_fifo_disp_back_data_we_9818;
  reg_disp_back_data_we <= NlwRenamedSig_OI_reg_disp_back_data_we;
  pb_master_stb0 <= pb_master_stb0_9998;
  pb_master_stb1 <= pb_master_stb1_9999;
  reg_disp_back_complete <= NlwRenamedSig_OI_reg_disp_back_complete;
  ext_fifo_disp_back_irq <= NlwRenamedSignal_ext_fifo_disp_back_irq;
  ext_fifo_disp_back_allow_wr <= NlwRenamedSig_OI_fifo_allow_wr;
  NlwRenamedSignal_ext_fifo_disp_back_irq <= pb_slave_irq;
  ext_fifo_disp_back_data(63) <= ext_fifo_disp_back_data_63_9814;
  ext_fifo_disp_back_data(62) <= ext_fifo_disp_back_data_62_9813;
  ext_fifo_disp_back_data(61) <= ext_fifo_disp_back_data_61_9812;
  ext_fifo_disp_back_data(60) <= ext_fifo_disp_back_data_60_9811;
  ext_fifo_disp_back_data(59) <= ext_fifo_disp_back_data_59_9809;
  ext_fifo_disp_back_data(58) <= ext_fifo_disp_back_data_58_9808;
  ext_fifo_disp_back_data(57) <= ext_fifo_disp_back_data_57_9807;
  ext_fifo_disp_back_data(56) <= ext_fifo_disp_back_data_56_9806;
  ext_fifo_disp_back_data(55) <= ext_fifo_disp_back_data_55_9805;
  ext_fifo_disp_back_data(54) <= ext_fifo_disp_back_data_54_9804;
  ext_fifo_disp_back_data(53) <= ext_fifo_disp_back_data_53_9803;
  ext_fifo_disp_back_data(52) <= ext_fifo_disp_back_data_52_9802;
  ext_fifo_disp_back_data(51) <= ext_fifo_disp_back_data_51_9801;
  ext_fifo_disp_back_data(50) <= ext_fifo_disp_back_data_50_9800;
  ext_fifo_disp_back_data(49) <= ext_fifo_disp_back_data_49_9798;
  ext_fifo_disp_back_data(48) <= ext_fifo_disp_back_data_48_9797;
  ext_fifo_disp_back_data(47) <= ext_fifo_disp_back_data_47_9796;
  ext_fifo_disp_back_data(46) <= ext_fifo_disp_back_data_46_9795;
  ext_fifo_disp_back_data(45) <= ext_fifo_disp_back_data_45_9794;
  ext_fifo_disp_back_data(44) <= ext_fifo_disp_back_data_44_9793;
  ext_fifo_disp_back_data(43) <= ext_fifo_disp_back_data_43_9792;
  ext_fifo_disp_back_data(42) <= ext_fifo_disp_back_data_42_9791;
  ext_fifo_disp_back_data(41) <= ext_fifo_disp_back_data_41_9790;
  ext_fifo_disp_back_data(40) <= ext_fifo_disp_back_data_40_9789;
  ext_fifo_disp_back_data(39) <= ext_fifo_disp_back_data_39_9787;
  ext_fifo_disp_back_data(38) <= ext_fifo_disp_back_data_38_9786;
  ext_fifo_disp_back_data(37) <= ext_fifo_disp_back_data_37_9785;
  ext_fifo_disp_back_data(36) <= ext_fifo_disp_back_data_36_9784;
  ext_fifo_disp_back_data(35) <= ext_fifo_disp_back_data_35_9783;
  ext_fifo_disp_back_data(34) <= ext_fifo_disp_back_data_34_9782;
  ext_fifo_disp_back_data(33) <= ext_fifo_disp_back_data_33_9781;
  ext_fifo_disp_back_data(32) <= ext_fifo_disp_back_data_32_9780;
  ext_fifo_disp_back_data(31) <= ext_fifo_disp_back_data_31_9779;
  ext_fifo_disp_back_data(30) <= ext_fifo_disp_back_data_30_9778;
  ext_fifo_disp_back_data(29) <= ext_fifo_disp_back_data_29_9776;
  ext_fifo_disp_back_data(28) <= ext_fifo_disp_back_data_28_9775;
  ext_fifo_disp_back_data(27) <= ext_fifo_disp_back_data_27_9774;
  ext_fifo_disp_back_data(26) <= ext_fifo_disp_back_data_26_9773;
  ext_fifo_disp_back_data(25) <= ext_fifo_disp_back_data_25_9772;
  ext_fifo_disp_back_data(24) <= ext_fifo_disp_back_data_24_9771;
  ext_fifo_disp_back_data(23) <= ext_fifo_disp_back_data_23_9770;
  ext_fifo_disp_back_data(22) <= ext_fifo_disp_back_data_22_9769;
  ext_fifo_disp_back_data(21) <= ext_fifo_disp_back_data_21_9768;
  ext_fifo_disp_back_data(20) <= ext_fifo_disp_back_data_20_9767;
  ext_fifo_disp_back_data(19) <= ext_fifo_disp_back_data_19_9765;
  ext_fifo_disp_back_data(18) <= ext_fifo_disp_back_data_18_9764;
  ext_fifo_disp_back_data(17) <= ext_fifo_disp_back_data_17_9763;
  ext_fifo_disp_back_data(16) <= ext_fifo_disp_back_data_16_9762;
  ext_fifo_disp_back_data(15) <= ext_fifo_disp_back_data_15_9761;
  ext_fifo_disp_back_data(14) <= ext_fifo_disp_back_data_14_9760;
  ext_fifo_disp_back_data(13) <= ext_fifo_disp_back_data_13_9759;
  ext_fifo_disp_back_data(12) <= ext_fifo_disp_back_data_12_9758;
  ext_fifo_disp_back_data(11) <= ext_fifo_disp_back_data_11_9757;
  ext_fifo_disp_back_data(10) <= ext_fifo_disp_back_data_10_9756;
  ext_fifo_disp_back_data(9) <= ext_fifo_disp_back_data_9_9817;
  ext_fifo_disp_back_data(8) <= ext_fifo_disp_back_data_8_9816;
  ext_fifo_disp_back_data(7) <= ext_fifo_disp_back_data_7_9815;
  ext_fifo_disp_back_data(6) <= ext_fifo_disp_back_data_6_9810;
  ext_fifo_disp_back_data(5) <= ext_fifo_disp_back_data_5_9799;
  ext_fifo_disp_back_data(4) <= ext_fifo_disp_back_data_4_9788;
  ext_fifo_disp_back_data(3) <= ext_fifo_disp_back_data_3_9777;
  ext_fifo_disp_back_data(2) <= ext_fifo_disp_back_data_2_9766;
  ext_fifo_disp_back_data(1) <= ext_fifo_disp_back_data_1_9755;
  ext_fifo_disp_back_data(0) <= ext_fifo_disp_back_data_0_9754;
  ext_fifo_disp_back_dmar(1) <= NlwRenamedSignal_ext_fifo_disp_back_dmar(1);
  ext_fifo_disp_back_dmar(0) <= NlwRenamedSignal_ext_fifo_disp_back_dmar(0);
  pb_master_data(63) <= pb_master_data_63_9994;
  pb_master_data(62) <= pb_master_data_62_9993;
  pb_master_data(61) <= pb_master_data_61_9992;
  pb_master_data(60) <= pb_master_data_60_9991;
  pb_master_data(59) <= pb_master_data_59_9989;
  pb_master_data(58) <= pb_master_data_58_9988;
  pb_master_data(57) <= pb_master_data_57_9987;
  pb_master_data(56) <= pb_master_data_56_9986;
  pb_master_data(55) <= pb_master_data_55_9985;
  pb_master_data(54) <= pb_master_data_54_9984;
  pb_master_data(53) <= pb_master_data_53_9983;
  pb_master_data(52) <= pb_master_data_52_9982;
  pb_master_data(51) <= pb_master_data_51_9981;
  pb_master_data(50) <= pb_master_data_50_9980;
  pb_master_data(49) <= pb_master_data_49_9978;
  pb_master_data(48) <= pb_master_data_48_9977;
  pb_master_data(47) <= pb_master_data_47_9976;
  pb_master_data(46) <= pb_master_data_46_9975;
  pb_master_data(45) <= pb_master_data_45_9974;
  pb_master_data(44) <= pb_master_data_44_9973;
  pb_master_data(43) <= pb_master_data_43_9972;
  pb_master_data(42) <= pb_master_data_42_9971;
  pb_master_data(41) <= pb_master_data_41_9970;
  pb_master_data(40) <= pb_master_data_40_9969;
  pb_master_data(39) <= pb_master_data_39_9967;
  pb_master_data(38) <= pb_master_data_38_9966;
  pb_master_data(37) <= pb_master_data_37_9965;
  pb_master_data(36) <= pb_master_data_36_9964;
  pb_master_data(35) <= pb_master_data_35_9963;
  pb_master_data(34) <= pb_master_data_34_9962;
  pb_master_data(33) <= pb_master_data_33_9961;
  pb_master_data(32) <= pb_master_data_32_9960;
  pb_master_data(31) <= pb_master_data_31_9959;
  pb_master_data(30) <= pb_master_data_30_9958;
  pb_master_data(29) <= pb_master_data_29_9956;
  pb_master_data(28) <= pb_master_data_28_9955;
  pb_master_data(27) <= pb_master_data_27_9954;
  pb_master_data(26) <= pb_master_data_26_9953;
  pb_master_data(25) <= pb_master_data_25_9952;
  pb_master_data(24) <= pb_master_data_24_9951;
  pb_master_data(23) <= pb_master_data_23_9950;
  pb_master_data(22) <= pb_master_data_22_9949;
  pb_master_data(21) <= pb_master_data_21_9948;
  pb_master_data(20) <= pb_master_data_20_9947;
  pb_master_data(19) <= pb_master_data_19_9945;
  pb_master_data(18) <= pb_master_data_18_9944;
  pb_master_data(17) <= pb_master_data_17_9943;
  pb_master_data(16) <= pb_master_data_16_9942;
  pb_master_data(15) <= pb_master_data_15_9941;
  pb_master_data(14) <= pb_master_data_14_9940;
  pb_master_data(13) <= pb_master_data_13_9939;
  pb_master_data(12) <= pb_master_data_12_9938;
  pb_master_data(11) <= pb_master_data_11_9937;
  pb_master_data(10) <= pb_master_data_10_9936;
  pb_master_data(9) <= pb_master_data_9_9997;
  pb_master_data(8) <= pb_master_data_8_9996;
  pb_master_data(7) <= pb_master_data_7_9995;
  pb_master_data(6) <= pb_master_data_6_9990;
  pb_master_data(5) <= pb_master_data_5_9979;
  pb_master_data(4) <= pb_master_data_4_9968;
  pb_master_data(3) <= pb_master_data_3_9957;
  pb_master_data(2) <= pb_master_data_2_9946;
  pb_master_data(1) <= pb_master_data_1_9935;
  pb_master_data(0) <= pb_master_data_0_9934;
  reg_disp_back_data(31) <= reg_disp_back_data_31_10108;
  reg_disp_back_data(30) <= reg_disp_back_data_30_10107;
  reg_disp_back_data(29) <= reg_disp_back_data_29_10105;
  reg_disp_back_data(28) <= reg_disp_back_data_28_10104;
  reg_disp_back_data(27) <= reg_disp_back_data_27_10103;
  reg_disp_back_data(26) <= reg_disp_back_data_26_10102;
  reg_disp_back_data(25) <= reg_disp_back_data_25_10101;
  reg_disp_back_data(24) <= reg_disp_back_data_24_10100;
  reg_disp_back_data(23) <= reg_disp_back_data_23_10099;
  reg_disp_back_data(22) <= reg_disp_back_data_22_10098;
  reg_disp_back_data(21) <= reg_disp_back_data_21_10097;
  reg_disp_back_data(20) <= reg_disp_back_data_20_10096;
  reg_disp_back_data(19) <= reg_disp_back_data_19_10094;
  reg_disp_back_data(18) <= reg_disp_back_data_18_10093;
  reg_disp_back_data(17) <= reg_disp_back_data_17_10092;
  reg_disp_back_data(16) <= reg_disp_back_data_16_10091;
  reg_disp_back_data(15) <= reg_disp_back_data_15_10090;
  reg_disp_back_data(14) <= reg_disp_back_data_14_10089;
  reg_disp_back_data(13) <= reg_disp_back_data_13_10088;
  reg_disp_back_data(12) <= reg_disp_back_data_12_10087;
  reg_disp_back_data(11) <= reg_disp_back_data_11_10086;
  reg_disp_back_data(10) <= reg_disp_back_data_10_10085;
  reg_disp_back_data(9) <= reg_disp_back_data_9_10114;
  reg_disp_back_data(8) <= reg_disp_back_data_8_10113;
  reg_disp_back_data(7) <= reg_disp_back_data_7_10112;
  reg_disp_back_data(6) <= reg_disp_back_data_6_10111;
  reg_disp_back_data(5) <= reg_disp_back_data_5_10110;
  reg_disp_back_data(4) <= reg_disp_back_data_4_10109;
  reg_disp_back_data(3) <= reg_disp_back_data_3_10106;
  reg_disp_back_data(2) <= reg_disp_back_data_2_10095;
  reg_disp_back_data(1) <= reg_disp_back_data_1_10084;
  reg_disp_back_data(0) <= reg_disp_back_data_0_10083;
  pb_master_cmd(2) <= NlwRenamedSig_OI_master_cmd(2);
  pb_master_cmd(1) <= NlwRenamedSig_OI_master_cmd(1);
  NlwRenamedSignal_ext_fifo_disp_back_dmar(1) <= pb_slave_dmar(1);
  NlwRenamedSignal_ext_fifo_disp_back_dmar(0) <= pb_slave_dmar(0);
  master_cmd_1 : FD
    port map (
      C => aclk,
      D => master_cmd_1_mux0000,
      Q => NlwRenamedSig_OI_master_cmd(1)
    );
  fifo_data_en : FD
    port map (
      C => aclk,
      D => fifo_data_en_mux0000_9894,
      Q => fifo_data_en_9893
    );
  reg_disp_back_data_we_7443 : FD
    port map (
      C => aclk,
      D => reg_disp_back_data_we_mux0000,
      Q => NlwRenamedSig_OI_reg_disp_back_data_we
    );
  master_cmd_2 : FD
    port map (
      C => aclk,
      D => master_cmd_2_mux0000,
      Q => NlwRenamedSig_OI_master_cmd(2)
    );
  pb_master_data_0 : FD
    port map (
      C => aclk,
      D => master_data(0),
      Q => pb_master_data_0_9934
    );
  pb_master_data_1 : FD
    port map (
      C => aclk,
      D => master_data(1),
      Q => pb_master_data_1_9935
    );
  pb_master_data_2 : FD
    port map (
      C => aclk,
      D => master_data(2),
      Q => pb_master_data_2_9946
    );
  pb_master_data_3 : FD
    port map (
      C => aclk,
      D => master_data(3),
      Q => pb_master_data_3_9957
    );
  pb_master_data_4 : FD
    port map (
      C => aclk,
      D => master_data(4),
      Q => pb_master_data_4_9968
    );
  pb_master_data_5 : FD
    port map (
      C => aclk,
      D => master_data(5),
      Q => pb_master_data_5_9979
    );
  pb_master_data_6 : FD
    port map (
      C => aclk,
      D => master_data(6),
      Q => pb_master_data_6_9990
    );
  pb_master_data_7 : FD
    port map (
      C => aclk,
      D => master_data(7),
      Q => pb_master_data_7_9995
    );
  pb_master_data_8 : FD
    port map (
      C => aclk,
      D => master_data(8),
      Q => pb_master_data_8_9996
    );
  pb_master_data_9 : FD
    port map (
      C => aclk,
      D => master_data(9),
      Q => pb_master_data_9_9997
    );
  pb_master_data_10 : FD
    port map (
      C => aclk,
      D => master_data(10),
      Q => pb_master_data_10_9936
    );
  pb_master_data_11 : FD
    port map (
      C => aclk,
      D => master_data(11),
      Q => pb_master_data_11_9937
    );
  pb_master_data_12 : FD
    port map (
      C => aclk,
      D => master_data(12),
      Q => pb_master_data_12_9938
    );
  pb_master_data_13 : FD
    port map (
      C => aclk,
      D => master_data(13),
      Q => pb_master_data_13_9939
    );
  pb_master_data_14 : FD
    port map (
      C => aclk,
      D => master_data(14),
      Q => pb_master_data_14_9940
    );
  pb_master_data_15 : FD
    port map (
      C => aclk,
      D => master_data(15),
      Q => pb_master_data_15_9941
    );
  pb_master_data_16 : FD
    port map (
      C => aclk,
      D => master_data(16),
      Q => pb_master_data_16_9942
    );
  pb_master_data_17 : FD
    port map (
      C => aclk,
      D => master_data(17),
      Q => pb_master_data_17_9943
    );
  pb_master_data_18 : FD
    port map (
      C => aclk,
      D => master_data(18),
      Q => pb_master_data_18_9944
    );
  pb_master_data_19 : FD
    port map (
      C => aclk,
      D => master_data(19),
      Q => pb_master_data_19_9945
    );
  pb_master_data_20 : FD
    port map (
      C => aclk,
      D => master_data(20),
      Q => pb_master_data_20_9947
    );
  pb_master_data_21 : FD
    port map (
      C => aclk,
      D => master_data(21),
      Q => pb_master_data_21_9948
    );
  pb_master_data_22 : FD
    port map (
      C => aclk,
      D => master_data(22),
      Q => pb_master_data_22_9949
    );
  pb_master_data_23 : FD
    port map (
      C => aclk,
      D => master_data(23),
      Q => pb_master_data_23_9950
    );
  pb_master_data_24 : FD
    port map (
      C => aclk,
      D => master_data(24),
      Q => pb_master_data_24_9951
    );
  pb_master_data_25 : FD
    port map (
      C => aclk,
      D => master_data(25),
      Q => pb_master_data_25_9952
    );
  pb_master_data_26 : FD
    port map (
      C => aclk,
      D => master_data(26),
      Q => pb_master_data_26_9953
    );
  pb_master_data_27 : FD
    port map (
      C => aclk,
      D => master_data(27),
      Q => pb_master_data_27_9954
    );
  pb_master_data_28 : FD
    port map (
      C => aclk,
      D => master_data(28),
      Q => pb_master_data_28_9955
    );
  pb_master_data_29 : FD
    port map (
      C => aclk,
      D => master_data(29),
      Q => pb_master_data_29_9956
    );
  pb_master_data_30 : FD
    port map (
      C => aclk,
      D => master_data(30),
      Q => pb_master_data_30_9958
    );
  pb_master_data_31 : FD
    port map (
      C => aclk,
      D => master_data(31),
      Q => pb_master_data_31_9959
    );
  pb_master_data_32 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(32),
      Q => pb_master_data_32_9960
    );
  pb_master_data_33 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(33),
      Q => pb_master_data_33_9961
    );
  pb_master_data_34 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(34),
      Q => pb_master_data_34_9962
    );
  pb_master_data_35 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(35),
      Q => pb_master_data_35_9963
    );
  pb_master_data_36 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(36),
      Q => pb_master_data_36_9964
    );
  pb_master_data_37 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(37),
      Q => pb_master_data_37_9965
    );
  pb_master_data_38 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(38),
      Q => pb_master_data_38_9966
    );
  pb_master_data_39 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(39),
      Q => pb_master_data_39_9967
    );
  pb_master_data_40 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(40),
      Q => pb_master_data_40_9969
    );
  pb_master_data_41 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(41),
      Q => pb_master_data_41_9970
    );
  pb_master_data_42 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(42),
      Q => pb_master_data_42_9971
    );
  pb_master_data_43 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(43),
      Q => pb_master_data_43_9972
    );
  pb_master_data_44 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(44),
      Q => pb_master_data_44_9973
    );
  pb_master_data_45 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(45),
      Q => pb_master_data_45_9974
    );
  pb_master_data_46 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(46),
      Q => pb_master_data_46_9975
    );
  pb_master_data_47 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(47),
      Q => pb_master_data_47_9976
    );
  pb_master_data_48 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(48),
      Q => pb_master_data_48_9977
    );
  pb_master_data_49 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(49),
      Q => pb_master_data_49_9978
    );
  pb_master_data_50 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(50),
      Q => pb_master_data_50_9980
    );
  pb_master_data_51 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(51),
      Q => pb_master_data_51_9981
    );
  pb_master_data_52 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(52),
      Q => pb_master_data_52_9982
    );
  pb_master_data_53 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(53),
      Q => pb_master_data_53_9983
    );
  pb_master_data_54 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(54),
      Q => pb_master_data_54_9984
    );
  pb_master_data_55 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(55),
      Q => pb_master_data_55_9985
    );
  pb_master_data_56 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(56),
      Q => pb_master_data_56_9986
    );
  pb_master_data_57 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(57),
      Q => pb_master_data_57_9987
    );
  pb_master_data_58 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(58),
      Q => pb_master_data_58_9988
    );
  pb_master_data_59 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(59),
      Q => pb_master_data_59_9989
    );
  pb_master_data_60 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(60),
      Q => pb_master_data_60_9991
    );
  pb_master_data_61 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(61),
      Q => pb_master_data_61_9992
    );
  pb_master_data_62 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(62),
      Q => pb_master_data_62_9993
    );
  pb_master_data_63 : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data(63),
      Q => pb_master_data_63_9994
    );
  rstpz : FD
    port map (
      C => aclk,
      D => rstp,
      Q => rstpz_10157
    );
  fifo_allow_wr : FD
    port map (
      C => aclk,
      D => fifo_allow_wr_mux0000_9892,
      Q => NlwRenamedSig_OI_fifo_allow_wr
    );
  pb_master_stb1_7511 : FD
    port map (
      C => aclk,
      D => master_stb1,
      Q => pb_master_stb1_9999
    );
  pb_slave_stb1_z : FD
    port map (
      C => aclk,
      D => pb_slave_stb1,
      Q => pb_slave_stb1_z_10074
    );
  ext_fifo_disp_back_data_0 : FD
    port map (
      C => aclk,
      D => pb_slave_data(0),
      Q => ext_fifo_disp_back_data_0_9754
    );
  ext_fifo_disp_back_data_1 : FD
    port map (
      C => aclk,
      D => pb_slave_data(1),
      Q => ext_fifo_disp_back_data_1_9755
    );
  ext_fifo_disp_back_data_2 : FD
    port map (
      C => aclk,
      D => pb_slave_data(2),
      Q => ext_fifo_disp_back_data_2_9766
    );
  ext_fifo_disp_back_data_3 : FD
    port map (
      C => aclk,
      D => pb_slave_data(3),
      Q => ext_fifo_disp_back_data_3_9777
    );
  ext_fifo_disp_back_data_4 : FD
    port map (
      C => aclk,
      D => pb_slave_data(4),
      Q => ext_fifo_disp_back_data_4_9788
    );
  ext_fifo_disp_back_data_5 : FD
    port map (
      C => aclk,
      D => pb_slave_data(5),
      Q => ext_fifo_disp_back_data_5_9799
    );
  ext_fifo_disp_back_data_6 : FD
    port map (
      C => aclk,
      D => pb_slave_data(6),
      Q => ext_fifo_disp_back_data_6_9810
    );
  ext_fifo_disp_back_data_7 : FD
    port map (
      C => aclk,
      D => pb_slave_data(7),
      Q => ext_fifo_disp_back_data_7_9815
    );
  ext_fifo_disp_back_data_8 : FD
    port map (
      C => aclk,
      D => pb_slave_data(8),
      Q => ext_fifo_disp_back_data_8_9816
    );
  ext_fifo_disp_back_data_9 : FD
    port map (
      C => aclk,
      D => pb_slave_data(9),
      Q => ext_fifo_disp_back_data_9_9817
    );
  ext_fifo_disp_back_data_10 : FD
    port map (
      C => aclk,
      D => pb_slave_data(10),
      Q => ext_fifo_disp_back_data_10_9756
    );
  ext_fifo_disp_back_data_11 : FD
    port map (
      C => aclk,
      D => pb_slave_data(11),
      Q => ext_fifo_disp_back_data_11_9757
    );
  ext_fifo_disp_back_data_12 : FD
    port map (
      C => aclk,
      D => pb_slave_data(12),
      Q => ext_fifo_disp_back_data_12_9758
    );
  ext_fifo_disp_back_data_13 : FD
    port map (
      C => aclk,
      D => pb_slave_data(13),
      Q => ext_fifo_disp_back_data_13_9759
    );
  ext_fifo_disp_back_data_14 : FD
    port map (
      C => aclk,
      D => pb_slave_data(14),
      Q => ext_fifo_disp_back_data_14_9760
    );
  ext_fifo_disp_back_data_15 : FD
    port map (
      C => aclk,
      D => pb_slave_data(15),
      Q => ext_fifo_disp_back_data_15_9761
    );
  ext_fifo_disp_back_data_16 : FD
    port map (
      C => aclk,
      D => pb_slave_data(16),
      Q => ext_fifo_disp_back_data_16_9762
    );
  ext_fifo_disp_back_data_17 : FD
    port map (
      C => aclk,
      D => pb_slave_data(17),
      Q => ext_fifo_disp_back_data_17_9763
    );
  ext_fifo_disp_back_data_18 : FD
    port map (
      C => aclk,
      D => pb_slave_data(18),
      Q => ext_fifo_disp_back_data_18_9764
    );
  ext_fifo_disp_back_data_19 : FD
    port map (
      C => aclk,
      D => pb_slave_data(19),
      Q => ext_fifo_disp_back_data_19_9765
    );
  ext_fifo_disp_back_data_20 : FD
    port map (
      C => aclk,
      D => pb_slave_data(20),
      Q => ext_fifo_disp_back_data_20_9767
    );
  ext_fifo_disp_back_data_21 : FD
    port map (
      C => aclk,
      D => pb_slave_data(21),
      Q => ext_fifo_disp_back_data_21_9768
    );
  ext_fifo_disp_back_data_22 : FD
    port map (
      C => aclk,
      D => pb_slave_data(22),
      Q => ext_fifo_disp_back_data_22_9769
    );
  ext_fifo_disp_back_data_23 : FD
    port map (
      C => aclk,
      D => pb_slave_data(23),
      Q => ext_fifo_disp_back_data_23_9770
    );
  ext_fifo_disp_back_data_24 : FD
    port map (
      C => aclk,
      D => pb_slave_data(24),
      Q => ext_fifo_disp_back_data_24_9771
    );
  ext_fifo_disp_back_data_25 : FD
    port map (
      C => aclk,
      D => pb_slave_data(25),
      Q => ext_fifo_disp_back_data_25_9772
    );
  ext_fifo_disp_back_data_26 : FD
    port map (
      C => aclk,
      D => pb_slave_data(26),
      Q => ext_fifo_disp_back_data_26_9773
    );
  ext_fifo_disp_back_data_27 : FD
    port map (
      C => aclk,
      D => pb_slave_data(27),
      Q => ext_fifo_disp_back_data_27_9774
    );
  ext_fifo_disp_back_data_28 : FD
    port map (
      C => aclk,
      D => pb_slave_data(28),
      Q => ext_fifo_disp_back_data_28_9775
    );
  ext_fifo_disp_back_data_29 : FD
    port map (
      C => aclk,
      D => pb_slave_data(29),
      Q => ext_fifo_disp_back_data_29_9776
    );
  ext_fifo_disp_back_data_30 : FD
    port map (
      C => aclk,
      D => pb_slave_data(30),
      Q => ext_fifo_disp_back_data_30_9778
    );
  ext_fifo_disp_back_data_31 : FD
    port map (
      C => aclk,
      D => pb_slave_data(31),
      Q => ext_fifo_disp_back_data_31_9779
    );
  ext_fifo_disp_back_data_32 : FD
    port map (
      C => aclk,
      D => pb_slave_data(32),
      Q => ext_fifo_disp_back_data_32_9780
    );
  ext_fifo_disp_back_data_33 : FD
    port map (
      C => aclk,
      D => pb_slave_data(33),
      Q => ext_fifo_disp_back_data_33_9781
    );
  ext_fifo_disp_back_data_34 : FD
    port map (
      C => aclk,
      D => pb_slave_data(34),
      Q => ext_fifo_disp_back_data_34_9782
    );
  ext_fifo_disp_back_data_35 : FD
    port map (
      C => aclk,
      D => pb_slave_data(35),
      Q => ext_fifo_disp_back_data_35_9783
    );
  ext_fifo_disp_back_data_36 : FD
    port map (
      C => aclk,
      D => pb_slave_data(36),
      Q => ext_fifo_disp_back_data_36_9784
    );
  ext_fifo_disp_back_data_37 : FD
    port map (
      C => aclk,
      D => pb_slave_data(37),
      Q => ext_fifo_disp_back_data_37_9785
    );
  ext_fifo_disp_back_data_38 : FD
    port map (
      C => aclk,
      D => pb_slave_data(38),
      Q => ext_fifo_disp_back_data_38_9786
    );
  ext_fifo_disp_back_data_39 : FD
    port map (
      C => aclk,
      D => pb_slave_data(39),
      Q => ext_fifo_disp_back_data_39_9787
    );
  ext_fifo_disp_back_data_40 : FD
    port map (
      C => aclk,
      D => pb_slave_data(40),
      Q => ext_fifo_disp_back_data_40_9789
    );
  ext_fifo_disp_back_data_41 : FD
    port map (
      C => aclk,
      D => pb_slave_data(41),
      Q => ext_fifo_disp_back_data_41_9790
    );
  ext_fifo_disp_back_data_42 : FD
    port map (
      C => aclk,
      D => pb_slave_data(42),
      Q => ext_fifo_disp_back_data_42_9791
    );
  ext_fifo_disp_back_data_43 : FD
    port map (
      C => aclk,
      D => pb_slave_data(43),
      Q => ext_fifo_disp_back_data_43_9792
    );
  ext_fifo_disp_back_data_44 : FD
    port map (
      C => aclk,
      D => pb_slave_data(44),
      Q => ext_fifo_disp_back_data_44_9793
    );
  ext_fifo_disp_back_data_45 : FD
    port map (
      C => aclk,
      D => pb_slave_data(45),
      Q => ext_fifo_disp_back_data_45_9794
    );
  ext_fifo_disp_back_data_46 : FD
    port map (
      C => aclk,
      D => pb_slave_data(46),
      Q => ext_fifo_disp_back_data_46_9795
    );
  ext_fifo_disp_back_data_47 : FD
    port map (
      C => aclk,
      D => pb_slave_data(47),
      Q => ext_fifo_disp_back_data_47_9796
    );
  ext_fifo_disp_back_data_48 : FD
    port map (
      C => aclk,
      D => pb_slave_data(48),
      Q => ext_fifo_disp_back_data_48_9797
    );
  ext_fifo_disp_back_data_49 : FD
    port map (
      C => aclk,
      D => pb_slave_data(49),
      Q => ext_fifo_disp_back_data_49_9798
    );
  ext_fifo_disp_back_data_50 : FD
    port map (
      C => aclk,
      D => pb_slave_data(50),
      Q => ext_fifo_disp_back_data_50_9800
    );
  ext_fifo_disp_back_data_51 : FD
    port map (
      C => aclk,
      D => pb_slave_data(51),
      Q => ext_fifo_disp_back_data_51_9801
    );
  ext_fifo_disp_back_data_52 : FD
    port map (
      C => aclk,
      D => pb_slave_data(52),
      Q => ext_fifo_disp_back_data_52_9802
    );
  ext_fifo_disp_back_data_53 : FD
    port map (
      C => aclk,
      D => pb_slave_data(53),
      Q => ext_fifo_disp_back_data_53_9803
    );
  ext_fifo_disp_back_data_54 : FD
    port map (
      C => aclk,
      D => pb_slave_data(54),
      Q => ext_fifo_disp_back_data_54_9804
    );
  ext_fifo_disp_back_data_55 : FD
    port map (
      C => aclk,
      D => pb_slave_data(55),
      Q => ext_fifo_disp_back_data_55_9805
    );
  ext_fifo_disp_back_data_56 : FD
    port map (
      C => aclk,
      D => pb_slave_data(56),
      Q => ext_fifo_disp_back_data_56_9806
    );
  ext_fifo_disp_back_data_57 : FD
    port map (
      C => aclk,
      D => pb_slave_data(57),
      Q => ext_fifo_disp_back_data_57_9807
    );
  ext_fifo_disp_back_data_58 : FD
    port map (
      C => aclk,
      D => pb_slave_data(58),
      Q => ext_fifo_disp_back_data_58_9808
    );
  ext_fifo_disp_back_data_59 : FD
    port map (
      C => aclk,
      D => pb_slave_data(59),
      Q => ext_fifo_disp_back_data_59_9809
    );
  ext_fifo_disp_back_data_60 : FD
    port map (
      C => aclk,
      D => pb_slave_data(60),
      Q => ext_fifo_disp_back_data_60_9811
    );
  ext_fifo_disp_back_data_61 : FD
    port map (
      C => aclk,
      D => pb_slave_data(61),
      Q => ext_fifo_disp_back_data_61_9812
    );
  ext_fifo_disp_back_data_62 : FD
    port map (
      C => aclk,
      D => pb_slave_data(62),
      Q => ext_fifo_disp_back_data_62_9813
    );
  ext_fifo_disp_back_data_63 : FD
    port map (
      C => aclk,
      D => pb_slave_data(63),
      Q => ext_fifo_disp_back_data_63_9814
    );
  reg_disp_back_data_0 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(0),
      Q => reg_disp_back_data_0_10083
    );
  reg_disp_back_data_1 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(1),
      Q => reg_disp_back_data_1_10084
    );
  reg_disp_back_data_2 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(2),
      Q => reg_disp_back_data_2_10095
    );
  reg_disp_back_data_3 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(3),
      Q => reg_disp_back_data_3_10106
    );
  reg_disp_back_data_4 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(4),
      Q => reg_disp_back_data_4_10109
    );
  reg_disp_back_data_5 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(5),
      Q => reg_disp_back_data_5_10110
    );
  reg_disp_back_data_6 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(6),
      Q => reg_disp_back_data_6_10111
    );
  reg_disp_back_data_7 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(7),
      Q => reg_disp_back_data_7_10112
    );
  reg_disp_back_data_8 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(8),
      Q => reg_disp_back_data_8_10113
    );
  reg_disp_back_data_9 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(9),
      Q => reg_disp_back_data_9_10114
    );
  reg_disp_back_data_10 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(10),
      Q => reg_disp_back_data_10_10085
    );
  reg_disp_back_data_11 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(11),
      Q => reg_disp_back_data_11_10086
    );
  reg_disp_back_data_12 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(12),
      Q => reg_disp_back_data_12_10087
    );
  reg_disp_back_data_13 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(13),
      Q => reg_disp_back_data_13_10088
    );
  reg_disp_back_data_14 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(14),
      Q => reg_disp_back_data_14_10089
    );
  reg_disp_back_data_15 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(15),
      Q => reg_disp_back_data_15_10090
    );
  reg_disp_back_data_16 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(16),
      Q => reg_disp_back_data_16_10091
    );
  reg_disp_back_data_17 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(17),
      Q => reg_disp_back_data_17_10092
    );
  reg_disp_back_data_18 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(18),
      Q => reg_disp_back_data_18_10093
    );
  reg_disp_back_data_19 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(19),
      Q => reg_disp_back_data_19_10094
    );
  reg_disp_back_data_20 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(20),
      Q => reg_disp_back_data_20_10096
    );
  reg_disp_back_data_21 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(21),
      Q => reg_disp_back_data_21_10097
    );
  reg_disp_back_data_22 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(22),
      Q => reg_disp_back_data_22_10098
    );
  reg_disp_back_data_23 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(23),
      Q => reg_disp_back_data_23_10099
    );
  reg_disp_back_data_24 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(24),
      Q => reg_disp_back_data_24_10100
    );
  reg_disp_back_data_25 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(25),
      Q => reg_disp_back_data_25_10101
    );
  reg_disp_back_data_26 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(26),
      Q => reg_disp_back_data_26_10102
    );
  reg_disp_back_data_27 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(27),
      Q => reg_disp_back_data_27_10103
    );
  reg_disp_back_data_28 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(28),
      Q => reg_disp_back_data_28_10104
    );
  reg_disp_back_data_29 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(29),
      Q => reg_disp_back_data_29_10105
    );
  reg_disp_back_data_30 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(30),
      Q => reg_disp_back_data_30_10107
    );
  reg_disp_back_data_31 : FDE
    port map (
      C => aclk,
      CE => pb_slave_stb1,
      D => pb_slave_data(31),
      Q => reg_disp_back_data_31_10108
    );
  reg_disp_back_complete_7609 : FD
    port map (
      C => aclk,
      D => reg_disp_back_complete_mux0000,
      Q => NlwRenamedSig_OI_reg_disp_back_complete
    );
  reg_stb1 : FD
    port map (
      C => aclk,
      D => reg_stb1_mux0000,
      Q => reg_stb1_10154
    );
  ex_fifo_stb1_z : FD
    port map (
      C => aclk,
      D => ext_fifo_disp_data_we,
      Q => ex_fifo_stb1_z_9746
    );
  ext_fifo_eot : FD
    port map (
      C => aclk,
      D => ext_fifo_eot_or0000,
      Q => ext_fifo_eot_9889
    );
  master_stb0 : FD
    port map (
      C => aclk,
      D => master_stb0_mux0000_9932,
      Q => master_stb0_9931
    );
  pb_master_stb0_7614 : FD
    port map (
      C => aclk,
      D => master_stb0_9931,
      Q => pb_master_stb0_9998
    );
  ext_fifo_disp_back_data_we_7615 : FDR
    port map (
      C => aclk,
      D => fifo_data_en_9893,
      R => pb_slave_stb1_inv,
      Q => ext_fifo_disp_back_data_we_9818
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd3_In_10163,
      R => rstpz_10157,
      Q => stp_FSM_FFd3_10162
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd1_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd1_10158
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd2_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd2_10160
    );
  stp_FSM_FFd4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd4_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd4_10164
    );
  stp_FSM_FFd5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd5_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd5_10166
    );
  stp_FSM_FFd7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd7_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd7_10169
    );
  stp_FSM_FFd8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd8_In,
      R => rstpz_10157,
      Q => stp_FSM_FFd8_10171
    );
  stp_FSM_FFd9 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd9_In_10174,
      S => rstpz_10157,
      Q => stp_FSM_FFd9_10173
    );
  stp_FSM_FFd6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => aclk,
      D => stp_FSM_FFd8_10171,
      R => rstpz_10157,
      Q => stp_FSM_FFd6_10168
    );
  master_stb11 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => reg_stb1_10154,
      I1 => ext_fifo_disp_data_we,
      O => master_stb1
    );
  stp_FSM_FFd8_In1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => stp_FSM_FFd9_10173,
      I1 => reg_req_rd_z_10152,
      I2 => reg_req_wr_z_10153,
      O => stp_FSM_FFd8_In
    );
  stp_FSM_FFd5_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd6_10168,
      I1 => pb_slave_stb0,
      I2 => stp_FSM_FFd5_10166,
      O => stp_FSM_FFd5_In
    );
  stp_FSM_FFd2_In1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => stp_FSM_FFd7_10169,
      I1 => ext_fifo_eot_9889,
      I2 => stp_FSM_FFd2_10160,
      O => stp_FSM_FFd2_In
    );
  ext_fifo_eot_or00001 : LUT4
    generic map(
      INIT => X"22F2"
    )
    port map (
      I0 => pb_slave_stb1_z_10074,
      I1 => pb_slave_stb1,
      I2 => ex_fifo_stb1_z_9746,
      I3 => ext_fifo_disp_data_we,
      O => ext_fifo_eot_or0000
    );
  stp_FSM_FFd4_In1 : LUT5
    generic map(
      INIT => X"80FF8080"
    )
    port map (
      I0 => reg_req_rd_z_10152,
      I1 => stp_FSM_FFd5_10166,
      I2 => pb_slave_stb0,
      I3 => pb_slave_stb1,
      I4 => stp_FSM_FFd4_10164,
      O => stp_FSM_FFd4_In
    );
  master_stb0_mux0000_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => stp_FSM_FFd8_10171,
      I1 => stp_FSM_FFd7_10169,
      O => N02
    );
  master_stb0_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stp_FSM_FFd5_10166,
      I1 => master_stb0_9931,
      I2 => stp_FSM_FFd3_10162,
      I3 => stp_FSM_FFd4_10164,
      I4 => stp_FSM_FFd1_10158,
      I5 => N02,
      O => master_stb0_mux0000_9932
    );
  stp_FSM_FFd3_In_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => pb_slave_stb0,
      I1 => stp_FSM_FFd5_10166,
      O => N2
    );
  stp_FSM_FFd3_In : LUT6
    generic map(
      INIT => X"FAAAFBBBF888FBBB"
    )
    port map (
      I0 => stp_FSM_FFd3_10162,
      I1 => reg_req_rd_z_10152,
      I2 => pb_slave_stb1,
      I3 => stp_FSM_FFd4_10164,
      I4 => N2,
      I5 => reg_req_wr_z_10153,
      O => stp_FSM_FFd3_In_10163
    );
  master_cmd_2_mux00001 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => N01,
      I2 => stp_FSM_FFd7_10169,
      O => master_cmd_2_mux0000
    );
  stp_FSM_FFd7_In1 : LUT5
    generic map(
      INIT => X"10101000"
    )
    port map (
      I0 => reg_req_rd_z_10152,
      I1 => reg_req_wr_z_10153,
      I2 => stp_FSM_FFd9_10173,
      I3 => ext_fifo_disp_request_rd,
      I4 => ext_fifo_disp_request_wr,
      O => stp_FSM_FFd7_In
    );
  stp_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => stp_FSM_FFd1_10158,
      I1 => ext_fifo_disp_request_rd,
      I2 => ext_fifo_disp_request_wr,
      I3 => ext_fifo_eot_9889,
      I4 => stp_FSM_FFd2_10160,
      O => stp_FSM_FFd1_In
    );
  reg_stb1_mux00001 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => reg_stb1_10154,
      I1 => N9,
      I2 => stp_FSM_FFd3_10162,
      I3 => reg_req_wr_z_10153,
      I4 => stp_FSM_FFd6_10168,
      O => reg_stb1_mux0000
    );
  reg_disp_back_data_we_mux0000121 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd4_10164,
      I1 => stp_FSM_FFd2_10160,
      I2 => stp_FSM_FFd1_10158,
      I3 => stp_FSM_FFd8_10171,
      I4 => stp_FSM_FFd7_10169,
      O => N9
    );
  reg_disp_back_complete_mux00001 : LUT5
    generic map(
      INIT => X"FFFFAAA8"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_disp_back_complete,
      I1 => N9,
      I2 => stp_FSM_FFd6_10168,
      I3 => stp_FSM_FFd5_10166,
      I4 => stp_FSM_FFd3_10162,
      O => reg_disp_back_complete_mux0000
    );
  master_cmd_0_mux000011 : LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
    port map (
      I0 => stp_FSM_FFd6_10168,
      I1 => stp_FSM_FFd5_10166,
      I2 => stp_FSM_FFd4_10164,
      I3 => stp_FSM_FFd2_10160,
      I4 => stp_FSM_FFd1_10158,
      O => N01
    );
  reg_disp_back_data_we_mux00001 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg_disp_back_data_we,
      I1 => N9,
      I2 => stp_FSM_FFd6_10168,
      I3 => stp_FSM_FFd5_10166,
      I4 => stp_FSM_FFd4_10164,
      I5 => pb_slave_stb1,
      O => reg_disp_back_data_we_mux0000
    );
  master_cmd_1_mux00001 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => ext_fifo_disp_request_rd,
      I1 => stp_FSM_FFd7_10169,
      I2 => reg_req_rd_z_10152,
      I3 => stp_FSM_FFd8_10171,
      I4 => NlwRenamedSig_OI_master_cmd(1),
      I5 => N01,
      O => master_cmd_1_mux0000
    );
  fifo_data_en_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd4_10164,
      I1 => stp_FSM_FFd8_10171,
      I2 => stp_FSM_FFd1_10158,
      I3 => stp_FSM_FFd7_10169,
      O => N4
    );
  fifo_data_en_mux0000 : LUT6
    generic map(
      INIT => X"FFFFFFFFCCCCCCC8"
    )
    port map (
      I0 => stp_FSM_FFd5_10166,
      I1 => fifo_data_en_9893,
      I2 => stp_FSM_FFd6_10168,
      I3 => stp_FSM_FFd3_10162,
      I4 => N4,
      I5 => stp_FSM_FFd2_10160,
      O => fifo_data_en_mux0000_9894
    );
  fifo_allow_wr_mux0000_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => stp_FSM_FFd3_10162,
      I1 => stp_FSM_FFd4_10164,
      I2 => stp_FSM_FFd8_10171,
      I3 => stp_FSM_FFd7_10169,
      O => N6
    );
  fifo_allow_wr_mux0000 : LUT6
    generic map(
      INIT => X"FFFFAAA8AAA8AAA8"
    )
    port map (
      I0 => NlwRenamedSig_OI_fifo_allow_wr,
      I1 => stp_FSM_FFd5_10166,
      I2 => stp_FSM_FFd6_10168,
      I3 => N6,
      I4 => ext_fifo_disp_request_wr,
      I5 => stp_FSM_FFd2_10160,
      O => fifo_allow_wr_mux0000_9892
    );
  master_adr_17_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(17),
      I2 => ext_fifo_disp_adr(17),
      O => pb_master_adr(17)
    );
  master_adr_16_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(16),
      I2 => ext_fifo_disp_adr(16),
      O => pb_master_adr(16)
    );
  master_adr_15_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(15),
      I2 => ext_fifo_disp_adr(15),
      O => pb_master_adr(15)
    );
  master_adr_14_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(14),
      I2 => ext_fifo_disp_adr(14),
      O => pb_master_adr(14)
    );
  master_adr_13_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(13),
      I2 => ext_fifo_disp_adr(13),
      O => pb_master_adr(13)
    );
  master_adr_12_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(12),
      I2 => ext_fifo_disp_adr(12),
      O => pb_master_adr(12)
    );
  master_adr_11_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_adr(11),
      I2 => ext_fifo_disp_adr(11),
      O => pb_master_adr(11)
    );
  stp_FSM_FFd9_In_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => reg_req_wr_z_10153,
      I1 => reg_req_rd_z_10152,
      O => N8
    );
  stp_FSM_FFd9_In : LUT6
    generic map(
      INIT => X"02FF02FF02030202"
    )
    port map (
      I0 => stp_FSM_FFd1_10158,
      I1 => ext_fifo_disp_request_rd,
      I2 => ext_fifo_disp_request_wr,
      I3 => N8,
      I4 => stp_FSM_FFd9_10173,
      I5 => stp_FSM_FFd3_10162,
      O => stp_FSM_FFd9_In_10174
    );
  master_data_9_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(9),
      I2 => ext_fifo_disp_data(9),
      O => master_data(9)
    );
  master_data_8_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(8),
      I2 => ext_fifo_disp_data(8),
      O => master_data(8)
    );
  master_data_7_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(7),
      I2 => ext_fifo_disp_data(7),
      O => master_data(7)
    );
  master_data_6_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(6),
      I2 => ext_fifo_disp_data(6),
      O => master_data(6)
    );
  master_data_5_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(5),
      I2 => ext_fifo_disp_data(5),
      O => master_data(5)
    );
  master_data_4_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(4),
      I2 => ext_fifo_disp_data(4),
      O => master_data(4)
    );
  master_data_3_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(3),
      I2 => ext_fifo_disp_data(3),
      O => master_data(3)
    );
  master_data_31_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(31),
      I2 => ext_fifo_disp_data(31),
      O => master_data(31)
    );
  master_data_30_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(30),
      I2 => ext_fifo_disp_data(30),
      O => master_data(30)
    );
  master_data_2_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(2),
      I2 => ext_fifo_disp_data(2),
      O => master_data(2)
    );
  master_data_29_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(29),
      I2 => ext_fifo_disp_data(29),
      O => master_data(29)
    );
  master_data_28_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(28),
      I2 => ext_fifo_disp_data(28),
      O => master_data(28)
    );
  master_data_27_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(27),
      I2 => ext_fifo_disp_data(27),
      O => master_data(27)
    );
  master_data_26_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(26),
      I2 => ext_fifo_disp_data(26),
      O => master_data(26)
    );
  master_data_25_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(25),
      I2 => ext_fifo_disp_data(25),
      O => master_data(25)
    );
  master_data_24_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(24),
      I2 => ext_fifo_disp_data(24),
      O => master_data(24)
    );
  master_data_23_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(23),
      I2 => ext_fifo_disp_data(23),
      O => master_data(23)
    );
  master_data_22_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(22),
      I2 => ext_fifo_disp_data(22),
      O => master_data(22)
    );
  master_data_21_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(21),
      I2 => ext_fifo_disp_data(21),
      O => master_data(21)
    );
  master_data_20_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(20),
      I2 => ext_fifo_disp_data(20),
      O => master_data(20)
    );
  master_data_1_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(1),
      I2 => ext_fifo_disp_data(1),
      O => master_data(1)
    );
  master_data_19_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(19),
      I2 => ext_fifo_disp_data(19),
      O => master_data(19)
    );
  master_data_18_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(18),
      I2 => ext_fifo_disp_data(18),
      O => master_data(18)
    );
  master_data_17_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(17),
      I2 => ext_fifo_disp_data(17),
      O => master_data(17)
    );
  master_data_16_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(16),
      I2 => ext_fifo_disp_data(16),
      O => master_data(16)
    );
  master_data_15_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(15),
      I2 => ext_fifo_disp_data(15),
      O => master_data(15)
    );
  master_data_14_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(14),
      I2 => ext_fifo_disp_data(14),
      O => master_data(14)
    );
  master_data_13_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(13),
      I2 => ext_fifo_disp_data(13),
      O => master_data(13)
    );
  master_data_12_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(12),
      I2 => ext_fifo_disp_data(12),
      O => master_data(12)
    );
  master_data_11_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(11),
      I2 => ext_fifo_disp_data(11),
      O => master_data(11)
    );
  master_data_10_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(10),
      I2 => ext_fifo_disp_data(10),
      O => master_data(10)
    );
  master_data_0_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => NlwRenamedSig_OI_master_cmd(2),
      I1 => reg_disp_data(0),
      I2 => ext_fifo_disp_data(0),
      O => master_data(0)
    );
  pb_slave_stb1_inv1_INV_0 : INV
    port map (
      I => pb_slave_stb1,
      O => pb_slave_stb1_inv
    );
  XST_GND : GND
    port map (
      G => N10
    );
  XST_VCC : VCC
    port map (
      P => N11
    );
  Mshreg_reg_req_rd_z : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N10,
      A1 => N10,
      A2 => N10,
      A3 => N10,
      CE => N11,
      CLK => aclk,
      D => reg_disp_request_reg_rd,
      Q => Mshreg_reg_req_rd_z_9734,
      Q15 => NLW_Mshreg_reg_req_rd_z_Q15_UNCONNECTED
    );
  reg_req_rd_z : FDE
    port map (
      C => aclk,
      CE => N11,
      D => Mshreg_reg_req_rd_z_9734,
      Q => reg_req_rd_z_10152
    );
  Mshreg_reg_req_wr_z : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => N10,
      A1 => N10,
      A2 => N10,
      A3 => N10,
      CE => N11,
      CLK => aclk,
      D => reg_disp_request_reg_wr,
      Q => Mshreg_reg_req_wr_z_9735,
      Q15 => NLW_Mshreg_reg_req_wr_z_Q15_UNCONNECTED
    );
  reg_req_wr_z : FDE
    port map (
      C => aclk,
      CE => N11,
      D => Mshreg_reg_req_wr_z_9735,
      Q => reg_req_wr_z_10153
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_reg_access is
  port (
    reg_access_back_data_we : out STD_LOGIC; 
    bp_reg_rd : out STD_LOGIC; 
    reg_ext_fifo_data_we : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    reg_disp_back_data_we : in STD_LOGIC := 'X'; 
    bp_reg_we : out STD_LOGIC; 
    reg_disp_back_complete : in STD_LOGIC := 'X'; 
    reg_disp_request_reg_rd : out STD_LOGIC; 
    bp_irq : in STD_LOGIC := 'X'; 
    reg_disp_request_reg_wr : out STD_LOGIC; 
    rstp : in STD_LOGIC := 'X'; 
    reg_access_back_complete : out STD_LOGIC; 
    reg_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bp_sel : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_disp_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bp_host_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bp_rd : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    reg_ext_fifo_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_ext_fifo_adr : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    bp_we : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    reg_access_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bp_adr : out STD_LOGIC_VECTOR ( 19 downto 0 ); 
    reg_access_req_rd : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    bp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_access_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_access_req_wr : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    reg_ext_fifo_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_disp_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    reg_access_data : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end core64_reg_access;

architecture STRUCTURE of core64_reg_access is
  signal bar0_complete_9406 : STD_LOGIC; 
  signal bar0_complete_mux0000 : STD_LOGIC; 
  signal bar0_read_9440 : STD_LOGIC; 
  signal bar0_write_9441 : STD_LOGIC; 
  signal bar1_complete_9474 : STD_LOGIC; 
  signal bar1_complete_mux0000 : STD_LOGIC; 
  signal bar1_read_9508 : STD_LOGIC; 
  signal bp_we_0_and0000 : STD_LOGIC; 
  signal disp_complete_9564 : STD_LOGIC; 
  signal reg_access_back_complete_9565 : STD_LOGIC; 
  signal reg_access_back_data_we_9566 : STD_LOGIC; 
  signal reg_access_back_complete_or0000 : STD_LOGIC; 
  signal reg_access_back_data_we_or0000 : STD_LOGIC; 
  signal reg_disp_request_reg_rd_9605 : STD_LOGIC; 
  signal reg_disp_request_reg_wr_9606 : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_23_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_24_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_25_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_26_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_27_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_28_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_29_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_30_Q : STD_LOGIC; 
  signal NlwRenamedSignal_reg_disp_adr_31_Q : STD_LOGIC; 
  signal reg_ext_fifo_data_we_9653 : STD_LOGIC; 
  signal reg_ext_fifo_data_we_and0000 : STD_LOGIC; 
  signal st1p_FSM_FFd1_9720 : STD_LOGIC; 
  signal st1p_FSM_FFd1_In : STD_LOGIC; 
  signal st1p_FSM_FFd2_9722 : STD_LOGIC; 
  signal st1p_FSM_FFd2_In : STD_LOGIC; 
  signal st1p_FSM_FFd3_9724 : STD_LOGIC; 
  signal st1p_FSM_FFd3_In : STD_LOGIC; 
  signal st1p_cmp_eq0001_inv : STD_LOGIC; 
  signal stp_FSM_FFd1_9727 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_9729 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_9731 : STD_LOGIC; 
  signal stp_FSM_FFd3_In : STD_LOGIC; 
  signal stp_cmp_eq0001_inv : STD_LOGIC; 
  signal bar0_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal bar0i_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal bar1_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSignal_bp_adr : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal NlwRenamedSignal_reg_ext_fifo_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
begin
  reg_access_back_data_we <= reg_access_back_data_we_9566;
  reg_ext_fifo_data_we <= reg_ext_fifo_data_we_9653;
  reg_disp_request_reg_rd <= reg_disp_request_reg_rd_9605;
  reg_disp_request_reg_wr <= reg_disp_request_reg_wr_9606;
  reg_access_back_complete <= reg_access_back_complete_9565;
  reg_disp_adr(31) <= NlwRenamedSignal_reg_disp_adr_31_Q;
  reg_disp_adr(30) <= NlwRenamedSignal_reg_disp_adr_30_Q;
  reg_disp_adr(29) <= NlwRenamedSignal_reg_disp_adr_29_Q;
  reg_disp_adr(28) <= NlwRenamedSignal_reg_disp_adr_28_Q;
  reg_disp_adr(27) <= NlwRenamedSignal_reg_disp_adr_27_Q;
  reg_disp_adr(26) <= NlwRenamedSignal_reg_disp_adr_26_Q;
  reg_disp_adr(25) <= NlwRenamedSignal_reg_disp_adr_25_Q;
  reg_disp_adr(24) <= NlwRenamedSignal_reg_disp_adr_24_Q;
  reg_disp_adr(23) <= NlwRenamedSignal_reg_disp_adr_23_Q;
  reg_disp_adr(22) <= NlwRenamedSignal_bp_adr(19);
  reg_disp_adr(21) <= NlwRenamedSignal_bp_adr(18);
  reg_disp_adr(20) <= NlwRenamedSignal_bp_adr(17);
  reg_disp_adr(19) <= NlwRenamedSignal_bp_adr(16);
  reg_disp_adr(18) <= NlwRenamedSignal_bp_adr(15);
  reg_disp_adr(17) <= NlwRenamedSignal_bp_adr(14);
  reg_disp_adr(16) <= NlwRenamedSignal_bp_adr(13);
  reg_disp_adr(15) <= NlwRenamedSignal_bp_adr(12);
  reg_disp_adr(14) <= NlwRenamedSignal_bp_adr(11);
  reg_disp_adr(13) <= NlwRenamedSignal_bp_adr(10);
  reg_disp_adr(12) <= NlwRenamedSignal_bp_adr(9);
  reg_disp_adr(11) <= NlwRenamedSignal_bp_adr(8);
  reg_disp_adr(10) <= NlwRenamedSignal_bp_adr(7);
  reg_disp_adr(9) <= NlwRenamedSignal_bp_adr(6);
  reg_disp_adr(8) <= NlwRenamedSignal_bp_adr(5);
  reg_disp_adr(7) <= NlwRenamedSignal_bp_adr(4);
  reg_disp_adr(6) <= NlwRenamedSignal_bp_adr(3);
  reg_disp_adr(5) <= NlwRenamedSignal_bp_adr(2);
  reg_disp_adr(4) <= NlwRenamedSignal_bp_adr(1);
  reg_disp_adr(3) <= NlwRenamedSignal_bp_adr(0);
  reg_disp_adr(2) <= NlwRenamedSignal_reg_disp_adr_2_Q;
  reg_disp_adr(1) <= NlwRenamedSignal_reg_disp_adr_1_Q;
  reg_disp_adr(0) <= NlwRenamedSignal_reg_disp_adr_0_Q;
  bp_sel(1) <= NlwRenamedSignal_bp_adr(6);
  bp_sel(0) <= NlwRenamedSignal_bp_adr(5);
  reg_disp_data(31) <= NlwRenamedSignal_reg_ext_fifo_data(31);
  reg_disp_data(30) <= NlwRenamedSignal_reg_ext_fifo_data(30);
  reg_disp_data(29) <= NlwRenamedSignal_reg_ext_fifo_data(29);
  reg_disp_data(28) <= NlwRenamedSignal_reg_ext_fifo_data(28);
  reg_disp_data(27) <= NlwRenamedSignal_reg_ext_fifo_data(27);
  reg_disp_data(26) <= NlwRenamedSignal_reg_ext_fifo_data(26);
  reg_disp_data(25) <= NlwRenamedSignal_reg_ext_fifo_data(25);
  reg_disp_data(24) <= NlwRenamedSignal_reg_ext_fifo_data(24);
  reg_disp_data(23) <= NlwRenamedSignal_reg_ext_fifo_data(23);
  reg_disp_data(22) <= NlwRenamedSignal_reg_ext_fifo_data(22);
  reg_disp_data(21) <= NlwRenamedSignal_reg_ext_fifo_data(21);
  reg_disp_data(20) <= NlwRenamedSignal_reg_ext_fifo_data(20);
  reg_disp_data(19) <= NlwRenamedSignal_reg_ext_fifo_data(19);
  reg_disp_data(18) <= NlwRenamedSignal_reg_ext_fifo_data(18);
  reg_disp_data(17) <= NlwRenamedSignal_reg_ext_fifo_data(17);
  reg_disp_data(16) <= NlwRenamedSignal_reg_ext_fifo_data(16);
  reg_disp_data(15) <= NlwRenamedSignal_reg_ext_fifo_data(15);
  reg_disp_data(14) <= NlwRenamedSignal_reg_ext_fifo_data(14);
  reg_disp_data(13) <= NlwRenamedSignal_reg_ext_fifo_data(13);
  reg_disp_data(12) <= NlwRenamedSignal_reg_ext_fifo_data(12);
  reg_disp_data(11) <= NlwRenamedSignal_reg_ext_fifo_data(11);
  reg_disp_data(10) <= NlwRenamedSignal_reg_ext_fifo_data(10);
  reg_disp_data(9) <= NlwRenamedSignal_reg_ext_fifo_data(9);
  reg_disp_data(8) <= NlwRenamedSignal_reg_ext_fifo_data(8);
  reg_disp_data(7) <= NlwRenamedSignal_reg_ext_fifo_data(7);
  reg_disp_data(6) <= NlwRenamedSignal_reg_ext_fifo_data(6);
  reg_disp_data(5) <= NlwRenamedSignal_reg_ext_fifo_data(5);
  reg_disp_data(4) <= NlwRenamedSignal_reg_ext_fifo_data(4);
  reg_disp_data(3) <= NlwRenamedSignal_reg_ext_fifo_data(3);
  reg_disp_data(2) <= NlwRenamedSignal_reg_ext_fifo_data(2);
  reg_disp_data(1) <= NlwRenamedSignal_reg_ext_fifo_data(1);
  reg_disp_data(0) <= NlwRenamedSignal_reg_ext_fifo_data(0);
  bp_host_data(31) <= NlwRenamedSignal_reg_ext_fifo_data(31);
  bp_host_data(30) <= NlwRenamedSignal_reg_ext_fifo_data(30);
  bp_host_data(29) <= NlwRenamedSignal_reg_ext_fifo_data(29);
  bp_host_data(28) <= NlwRenamedSignal_reg_ext_fifo_data(28);
  bp_host_data(27) <= NlwRenamedSignal_reg_ext_fifo_data(27);
  bp_host_data(26) <= NlwRenamedSignal_reg_ext_fifo_data(26);
  bp_host_data(25) <= NlwRenamedSignal_reg_ext_fifo_data(25);
  bp_host_data(24) <= NlwRenamedSignal_reg_ext_fifo_data(24);
  bp_host_data(23) <= NlwRenamedSignal_reg_ext_fifo_data(23);
  bp_host_data(22) <= NlwRenamedSignal_reg_ext_fifo_data(22);
  bp_host_data(21) <= NlwRenamedSignal_reg_ext_fifo_data(21);
  bp_host_data(20) <= NlwRenamedSignal_reg_ext_fifo_data(20);
  bp_host_data(19) <= NlwRenamedSignal_reg_ext_fifo_data(19);
  bp_host_data(18) <= NlwRenamedSignal_reg_ext_fifo_data(18);
  bp_host_data(17) <= NlwRenamedSignal_reg_ext_fifo_data(17);
  bp_host_data(16) <= NlwRenamedSignal_reg_ext_fifo_data(16);
  bp_host_data(15) <= NlwRenamedSignal_reg_ext_fifo_data(15);
  bp_host_data(14) <= NlwRenamedSignal_reg_ext_fifo_data(14);
  bp_host_data(13) <= NlwRenamedSignal_reg_ext_fifo_data(13);
  bp_host_data(12) <= NlwRenamedSignal_reg_ext_fifo_data(12);
  bp_host_data(11) <= NlwRenamedSignal_reg_ext_fifo_data(11);
  bp_host_data(10) <= NlwRenamedSignal_reg_ext_fifo_data(10);
  bp_host_data(9) <= NlwRenamedSignal_reg_ext_fifo_data(9);
  bp_host_data(8) <= NlwRenamedSignal_reg_ext_fifo_data(8);
  bp_host_data(7) <= NlwRenamedSignal_reg_ext_fifo_data(7);
  bp_host_data(6) <= NlwRenamedSignal_reg_ext_fifo_data(6);
  bp_host_data(5) <= NlwRenamedSignal_reg_ext_fifo_data(5);
  bp_host_data(4) <= NlwRenamedSignal_reg_ext_fifo_data(4);
  bp_host_data(3) <= NlwRenamedSignal_reg_ext_fifo_data(3);
  bp_host_data(2) <= NlwRenamedSignal_reg_ext_fifo_data(2);
  bp_host_data(1) <= NlwRenamedSignal_reg_ext_fifo_data(1);
  bp_host_data(0) <= NlwRenamedSignal_reg_ext_fifo_data(0);
  reg_ext_fifo_data(31) <= NlwRenamedSignal_reg_ext_fifo_data(31);
  reg_ext_fifo_data(30) <= NlwRenamedSignal_reg_ext_fifo_data(30);
  reg_ext_fifo_data(29) <= NlwRenamedSignal_reg_ext_fifo_data(29);
  reg_ext_fifo_data(28) <= NlwRenamedSignal_reg_ext_fifo_data(28);
  reg_ext_fifo_data(27) <= NlwRenamedSignal_reg_ext_fifo_data(27);
  reg_ext_fifo_data(26) <= NlwRenamedSignal_reg_ext_fifo_data(26);
  reg_ext_fifo_data(25) <= NlwRenamedSignal_reg_ext_fifo_data(25);
  reg_ext_fifo_data(24) <= NlwRenamedSignal_reg_ext_fifo_data(24);
  reg_ext_fifo_data(23) <= NlwRenamedSignal_reg_ext_fifo_data(23);
  reg_ext_fifo_data(22) <= NlwRenamedSignal_reg_ext_fifo_data(22);
  reg_ext_fifo_data(21) <= NlwRenamedSignal_reg_ext_fifo_data(21);
  reg_ext_fifo_data(20) <= NlwRenamedSignal_reg_ext_fifo_data(20);
  reg_ext_fifo_data(19) <= NlwRenamedSignal_reg_ext_fifo_data(19);
  reg_ext_fifo_data(18) <= NlwRenamedSignal_reg_ext_fifo_data(18);
  reg_ext_fifo_data(17) <= NlwRenamedSignal_reg_ext_fifo_data(17);
  reg_ext_fifo_data(16) <= NlwRenamedSignal_reg_ext_fifo_data(16);
  reg_ext_fifo_data(15) <= NlwRenamedSignal_reg_ext_fifo_data(15);
  reg_ext_fifo_data(14) <= NlwRenamedSignal_reg_ext_fifo_data(14);
  reg_ext_fifo_data(13) <= NlwRenamedSignal_reg_ext_fifo_data(13);
  reg_ext_fifo_data(12) <= NlwRenamedSignal_reg_ext_fifo_data(12);
  reg_ext_fifo_data(11) <= NlwRenamedSignal_reg_ext_fifo_data(11);
  reg_ext_fifo_data(10) <= NlwRenamedSignal_reg_ext_fifo_data(10);
  reg_ext_fifo_data(9) <= NlwRenamedSignal_reg_ext_fifo_data(9);
  reg_ext_fifo_data(8) <= NlwRenamedSignal_reg_ext_fifo_data(8);
  reg_ext_fifo_data(7) <= NlwRenamedSignal_reg_ext_fifo_data(7);
  reg_ext_fifo_data(6) <= NlwRenamedSignal_reg_ext_fifo_data(6);
  reg_ext_fifo_data(5) <= NlwRenamedSignal_reg_ext_fifo_data(5);
  reg_ext_fifo_data(4) <= NlwRenamedSignal_reg_ext_fifo_data(4);
  reg_ext_fifo_data(3) <= NlwRenamedSignal_reg_ext_fifo_data(3);
  reg_ext_fifo_data(2) <= NlwRenamedSignal_reg_ext_fifo_data(2);
  reg_ext_fifo_data(1) <= NlwRenamedSignal_reg_ext_fifo_data(1);
  reg_ext_fifo_data(0) <= NlwRenamedSignal_reg_ext_fifo_data(0);
  reg_ext_fifo_adr(6) <= NlwRenamedSignal_bp_adr(6);
  reg_ext_fifo_adr(5) <= NlwRenamedSignal_bp_adr(5);
  reg_ext_fifo_adr(4) <= NlwRenamedSignal_bp_adr(4);
  reg_ext_fifo_adr(3) <= NlwRenamedSignal_bp_adr(3);
  reg_ext_fifo_adr(2) <= NlwRenamedSignal_bp_adr(2);
  reg_ext_fifo_adr(1) <= NlwRenamedSignal_bp_adr(1);
  reg_ext_fifo_adr(0) <= NlwRenamedSignal_bp_adr(0);
  bp_adr(19) <= NlwRenamedSignal_bp_adr(19);
  bp_adr(18) <= NlwRenamedSignal_bp_adr(18);
  bp_adr(17) <= NlwRenamedSignal_bp_adr(17);
  bp_adr(16) <= NlwRenamedSignal_bp_adr(16);
  bp_adr(15) <= NlwRenamedSignal_bp_adr(15);
  bp_adr(14) <= NlwRenamedSignal_bp_adr(14);
  bp_adr(13) <= NlwRenamedSignal_bp_adr(13);
  bp_adr(12) <= NlwRenamedSignal_bp_adr(12);
  bp_adr(11) <= NlwRenamedSignal_bp_adr(11);
  bp_adr(10) <= NlwRenamedSignal_bp_adr(10);
  bp_adr(9) <= NlwRenamedSignal_bp_adr(9);
  bp_adr(8) <= NlwRenamedSignal_bp_adr(8);
  bp_adr(7) <= NlwRenamedSignal_bp_adr(7);
  bp_adr(6) <= NlwRenamedSignal_bp_adr(6);
  bp_adr(5) <= NlwRenamedSignal_bp_adr(5);
  bp_adr(4) <= NlwRenamedSignal_bp_adr(4);
  bp_adr(3) <= NlwRenamedSignal_bp_adr(3);
  bp_adr(2) <= NlwRenamedSignal_bp_adr(2);
  bp_adr(1) <= NlwRenamedSignal_bp_adr(1);
  bp_adr(0) <= NlwRenamedSignal_bp_adr(0);
  NlwRenamedSignal_reg_disp_adr_31_Q <= reg_access_adr(31);
  NlwRenamedSignal_reg_disp_adr_30_Q <= reg_access_adr(30);
  NlwRenamedSignal_reg_disp_adr_29_Q <= reg_access_adr(29);
  NlwRenamedSignal_reg_disp_adr_28_Q <= reg_access_adr(28);
  NlwRenamedSignal_reg_disp_adr_27_Q <= reg_access_adr(27);
  NlwRenamedSignal_reg_disp_adr_26_Q <= reg_access_adr(26);
  NlwRenamedSignal_reg_disp_adr_25_Q <= reg_access_adr(25);
  NlwRenamedSignal_reg_disp_adr_24_Q <= reg_access_adr(24);
  NlwRenamedSignal_reg_disp_adr_23_Q <= reg_access_adr(23);
  NlwRenamedSignal_bp_adr(19) <= reg_access_adr(22);
  NlwRenamedSignal_bp_adr(18) <= reg_access_adr(21);
  NlwRenamedSignal_bp_adr(17) <= reg_access_adr(20);
  NlwRenamedSignal_bp_adr(16) <= reg_access_adr(19);
  NlwRenamedSignal_bp_adr(15) <= reg_access_adr(18);
  NlwRenamedSignal_bp_adr(14) <= reg_access_adr(17);
  NlwRenamedSignal_bp_adr(13) <= reg_access_adr(16);
  NlwRenamedSignal_bp_adr(12) <= reg_access_adr(15);
  NlwRenamedSignal_bp_adr(11) <= reg_access_adr(14);
  NlwRenamedSignal_bp_adr(10) <= reg_access_adr(13);
  NlwRenamedSignal_bp_adr(9) <= reg_access_adr(12);
  NlwRenamedSignal_bp_adr(8) <= reg_access_adr(11);
  NlwRenamedSignal_bp_adr(7) <= reg_access_adr(10);
  NlwRenamedSignal_bp_adr(6) <= reg_access_adr(9);
  NlwRenamedSignal_bp_adr(5) <= reg_access_adr(8);
  NlwRenamedSignal_bp_adr(4) <= reg_access_adr(7);
  NlwRenamedSignal_bp_adr(3) <= reg_access_adr(6);
  NlwRenamedSignal_bp_adr(2) <= reg_access_adr(5);
  NlwRenamedSignal_bp_adr(1) <= reg_access_adr(4);
  NlwRenamedSignal_bp_adr(0) <= reg_access_adr(3);
  NlwRenamedSignal_reg_disp_adr_2_Q <= reg_access_adr(2);
  NlwRenamedSignal_reg_disp_adr_1_Q <= reg_access_adr(1);
  NlwRenamedSignal_reg_disp_adr_0_Q <= reg_access_adr(0);
  NlwRenamedSignal_reg_ext_fifo_data(31) <= reg_access_data(31);
  NlwRenamedSignal_reg_ext_fifo_data(30) <= reg_access_data(30);
  NlwRenamedSignal_reg_ext_fifo_data(29) <= reg_access_data(29);
  NlwRenamedSignal_reg_ext_fifo_data(28) <= reg_access_data(28);
  NlwRenamedSignal_reg_ext_fifo_data(27) <= reg_access_data(27);
  NlwRenamedSignal_reg_ext_fifo_data(26) <= reg_access_data(26);
  NlwRenamedSignal_reg_ext_fifo_data(25) <= reg_access_data(25);
  NlwRenamedSignal_reg_ext_fifo_data(24) <= reg_access_data(24);
  NlwRenamedSignal_reg_ext_fifo_data(23) <= reg_access_data(23);
  NlwRenamedSignal_reg_ext_fifo_data(22) <= reg_access_data(22);
  NlwRenamedSignal_reg_ext_fifo_data(21) <= reg_access_data(21);
  NlwRenamedSignal_reg_ext_fifo_data(20) <= reg_access_data(20);
  NlwRenamedSignal_reg_ext_fifo_data(19) <= reg_access_data(19);
  NlwRenamedSignal_reg_ext_fifo_data(18) <= reg_access_data(18);
  NlwRenamedSignal_reg_ext_fifo_data(17) <= reg_access_data(17);
  NlwRenamedSignal_reg_ext_fifo_data(16) <= reg_access_data(16);
  NlwRenamedSignal_reg_ext_fifo_data(15) <= reg_access_data(15);
  NlwRenamedSignal_reg_ext_fifo_data(14) <= reg_access_data(14);
  NlwRenamedSignal_reg_ext_fifo_data(13) <= reg_access_data(13);
  NlwRenamedSignal_reg_ext_fifo_data(12) <= reg_access_data(12);
  NlwRenamedSignal_reg_ext_fifo_data(11) <= reg_access_data(11);
  NlwRenamedSignal_reg_ext_fifo_data(10) <= reg_access_data(10);
  NlwRenamedSignal_reg_ext_fifo_data(9) <= reg_access_data(9);
  NlwRenamedSignal_reg_ext_fifo_data(8) <= reg_access_data(8);
  NlwRenamedSignal_reg_ext_fifo_data(7) <= reg_access_data(7);
  NlwRenamedSignal_reg_ext_fifo_data(6) <= reg_access_data(6);
  NlwRenamedSignal_reg_ext_fifo_data(5) <= reg_access_data(5);
  NlwRenamedSignal_reg_ext_fifo_data(4) <= reg_access_data(4);
  NlwRenamedSignal_reg_ext_fifo_data(3) <= reg_access_data(3);
  NlwRenamedSignal_reg_ext_fifo_data(2) <= reg_access_data(2);
  NlwRenamedSignal_reg_ext_fifo_data(1) <= reg_access_data(1);
  NlwRenamedSignal_reg_ext_fifo_data(0) <= reg_access_data(0);
  reg_ext_fifo_data_we_7280 : FD
    port map (
      C => clk,
      D => reg_ext_fifo_data_we_and0000,
      Q => reg_ext_fifo_data_we_9653
    );
  disp_complete : FD
    port map (
      C => clk,
      D => reg_disp_back_complete,
      Q => disp_complete_9564
    );
  bp_we_0 : FD
    port map (
      C => clk,
      D => bp_we_0_and0000,
      Q => bp_we(0)
    );
  reg_access_back_complete_7283 : FD
    port map (
      C => clk,
      D => reg_access_back_complete_or0000,
      Q => reg_access_back_complete_9565
    );
  bar1_data_0 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(0),
      Q => bar1_data(0)
    );
  bar1_data_1 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(1),
      Q => bar1_data(1)
    );
  bar1_data_2 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(2),
      Q => bar1_data(2)
    );
  bar1_data_3 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(3),
      Q => bar1_data(3)
    );
  bar1_data_4 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(4),
      Q => bar1_data(4)
    );
  bar1_data_5 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(5),
      Q => bar1_data(5)
    );
  bar1_data_6 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(6),
      Q => bar1_data(6)
    );
  bar1_data_7 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(7),
      Q => bar1_data(7)
    );
  bar1_data_8 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(8),
      Q => bar1_data(8)
    );
  bar1_data_9 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(9),
      Q => bar1_data(9)
    );
  bar1_data_10 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(10),
      Q => bar1_data(10)
    );
  bar1_data_11 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(11),
      Q => bar1_data(11)
    );
  bar1_data_12 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(12),
      Q => bar1_data(12)
    );
  bar1_data_13 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(13),
      Q => bar1_data(13)
    );
  bar1_data_14 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(14),
      Q => bar1_data(14)
    );
  bar1_data_15 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(15),
      Q => bar1_data(15)
    );
  bar1_data_16 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(16),
      Q => bar1_data(16)
    );
  bar1_data_17 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(17),
      Q => bar1_data(17)
    );
  bar1_data_18 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(18),
      Q => bar1_data(18)
    );
  bar1_data_19 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(19),
      Q => bar1_data(19)
    );
  bar1_data_20 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(20),
      Q => bar1_data(20)
    );
  bar1_data_21 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(21),
      Q => bar1_data(21)
    );
  bar1_data_22 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(22),
      Q => bar1_data(22)
    );
  bar1_data_23 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(23),
      Q => bar1_data(23)
    );
  bar1_data_24 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(24),
      Q => bar1_data(24)
    );
  bar1_data_25 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(25),
      Q => bar1_data(25)
    );
  bar1_data_26 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(26),
      Q => bar1_data(26)
    );
  bar1_data_27 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(27),
      Q => bar1_data(27)
    );
  bar1_data_28 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(28),
      Q => bar1_data(28)
    );
  bar1_data_29 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(29),
      Q => bar1_data(29)
    );
  bar1_data_30 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(30),
      Q => bar1_data(30)
    );
  bar1_data_31 : FDE
    port map (
      C => clk,
      CE => reg_disp_back_data_we,
      D => reg_disp_back_data(31),
      Q => bar1_data(31)
    );
  reg_access_back_data_we_7316 : FD
    port map (
      C => clk,
      D => reg_access_back_data_we_or0000,
      Q => reg_access_back_data_we_9566
    );
  bar0_complete : FD
    port map (
      C => clk,
      D => bar0_complete_mux0000,
      Q => bar0_complete_9406
    );
  bar1_complete : FD
    port map (
      C => clk,
      D => bar1_complete_mux0000,
      Q => bar1_complete_9474
    );
  bar0_read : FDR
    port map (
      C => clk,
      D => reg_access_req_rd(0),
      R => stp_cmp_eq0001_inv,
      Q => bar0_read_9440
    );
  bar0_write : FDR
    port map (
      C => clk,
      D => reg_access_req_wr(0),
      R => stp_cmp_eq0001_inv,
      Q => bar0_write_9441
    );
  bar0_data_0 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(0),
      Q => bar0_data(0)
    );
  bar0_data_1 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(1),
      Q => bar0_data(1)
    );
  bar0_data_2 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(2),
      Q => bar0_data(2)
    );
  bar0_data_3 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(3),
      Q => bar0_data(3)
    );
  bar0_data_4 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(4),
      Q => bar0_data(4)
    );
  bar0_data_5 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(5),
      Q => bar0_data(5)
    );
  bar0_data_6 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(6),
      Q => bar0_data(6)
    );
  bar0_data_7 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(7),
      Q => bar0_data(7)
    );
  bar0_data_8 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(8),
      Q => bar0_data(8)
    );
  bar0_data_9 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(9),
      Q => bar0_data(9)
    );
  bar0_data_10 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(10),
      Q => bar0_data(10)
    );
  bar0_data_11 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(11),
      Q => bar0_data(11)
    );
  bar0_data_12 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(12),
      Q => bar0_data(12)
    );
  bar0_data_13 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(13),
      Q => bar0_data(13)
    );
  bar0_data_14 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(14),
      Q => bar0_data(14)
    );
  bar0_data_15 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(15),
      Q => bar0_data(15)
    );
  bar0_data_16 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(16),
      Q => bar0_data(16)
    );
  bar0_data_17 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(17),
      Q => bar0_data(17)
    );
  bar0_data_18 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(18),
      Q => bar0_data(18)
    );
  bar0_data_19 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(19),
      Q => bar0_data(19)
    );
  bar0_data_20 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(20),
      Q => bar0_data(20)
    );
  bar0_data_21 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(21),
      Q => bar0_data(21)
    );
  bar0_data_22 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(22),
      Q => bar0_data(22)
    );
  bar0_data_23 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(23),
      Q => bar0_data(23)
    );
  bar0_data_24 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(24),
      Q => bar0_data(24)
    );
  bar0_data_25 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(25),
      Q => bar0_data(25)
    );
  bar0_data_26 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(26),
      Q => bar0_data(26)
    );
  bar0_data_27 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(27),
      Q => bar0_data(27)
    );
  bar0_data_28 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(28),
      Q => bar0_data(28)
    );
  bar0_data_29 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(29),
      Q => bar0_data(29)
    );
  bar0_data_30 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(30),
      Q => bar0_data(30)
    );
  bar0_data_31 : FDE
    port map (
      C => clk,
      CE => bar0_read_9440,
      D => bar0i_data(31),
      Q => bar0_data(31)
    );
  bar1_read : FD
    port map (
      C => clk,
      D => st1p_FSM_FFd2_9722,
      Q => bar1_read_9508
    );
  reg_disp_request_reg_rd_7354 : FDR
    port map (
      C => clk,
      D => reg_access_req_rd(1),
      R => st1p_cmp_eq0001_inv,
      Q => reg_disp_request_reg_rd_9605
    );
  reg_disp_request_reg_wr_7355 : FDR
    port map (
      C => clk,
      D => reg_access_req_wr(1),
      R => st1p_cmp_eq0001_inv,
      Q => reg_disp_request_reg_wr_9606
    );
  stp_FSM_FFd3 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd3_In,
      S => rstp,
      Q => stp_FSM_FFd3_9731
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd1_In,
      R => rstp,
      Q => stp_FSM_FFd1_9727
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => stp_FSM_FFd2_In,
      R => rstp,
      Q => stp_FSM_FFd2_9729
    );
  st1p_FSM_FFd3 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => st1p_FSM_FFd3_In,
      S => rstp,
      Q => st1p_FSM_FFd3_9724
    );
  st1p_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => st1p_FSM_FFd1_In,
      R => rstp,
      Q => st1p_FSM_FFd1_9720
    );
  st1p_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => st1p_FSM_FFd2_In,
      R => rstp,
      Q => st1p_FSM_FFd2_9722
    );
  reg_access_back_data_we_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => bar0_read_9440,
      I1 => bar1_read_9508,
      O => reg_access_back_data_we_or0000
    );
  reg_access_back_complete_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => bar0_complete_9406,
      I1 => bar1_complete_9474,
      O => reg_access_back_complete_or0000
    );
  bar1_complete_mux00001 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => st1p_FSM_FFd2_9722,
      I1 => bar1_complete_9474,
      I2 => st1p_FSM_FFd1_9720,
      O => bar1_complete_mux0000
    );
  bar0_complete_mux00001 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => stp_FSM_FFd2_9729,
      I1 => bar0_complete_9406,
      I2 => stp_FSM_FFd1_9727,
      O => bar0_complete_mux0000
    );
  bp_we_0_and00001 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => bar0_write_9441,
      I1 => NlwRenamedSignal_bp_adr(5),
      I2 => NlwRenamedSignal_bp_adr(6),
      I3 => NlwRenamedSignal_bp_adr(17),
      I4 => NlwRenamedSignal_bp_adr(7),
      O => bp_we_0_and0000
    );
  stp_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => stp_FSM_FFd2_9729,
      I1 => reg_access_req_wr(0),
      I2 => reg_access_req_rd(0),
      O => stp_FSM_FFd3_In
    );
  stp_FSM_FFd2_In1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => stp_FSM_FFd3_9731,
      I1 => reg_access_req_rd(0),
      I2 => reg_access_req_wr(0),
      O => stp_FSM_FFd2_In
    );
  st1p_FSM_FFd3_In1 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => st1p_FSM_FFd2_9722,
      I1 => reg_access_req_wr(1),
      I2 => reg_access_req_rd(1),
      O => st1p_FSM_FFd3_In
    );
  reg_access_back_data_9_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(9),
      I2 => bar0_data(9),
      O => reg_access_back_data(9)
    );
  reg_access_back_data_8_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(8),
      I2 => bar0_data(8),
      O => reg_access_back_data(8)
    );
  reg_access_back_data_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(7),
      I2 => bar0_data(7),
      O => reg_access_back_data(7)
    );
  reg_access_back_data_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(6),
      I2 => bar0_data(6),
      O => reg_access_back_data(6)
    );
  reg_access_back_data_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(5),
      I2 => bar0_data(5),
      O => reg_access_back_data(5)
    );
  reg_access_back_data_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(4),
      I2 => bar0_data(4),
      O => reg_access_back_data(4)
    );
  reg_access_back_data_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(3),
      I2 => bar0_data(3),
      O => reg_access_back_data(3)
    );
  reg_access_back_data_31_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(31),
      I2 => bar0_data(31),
      O => reg_access_back_data(31)
    );
  reg_access_back_data_30_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(30),
      I2 => bar0_data(30),
      O => reg_access_back_data(30)
    );
  reg_access_back_data_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(2),
      I2 => bar0_data(2),
      O => reg_access_back_data(2)
    );
  reg_access_back_data_29_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(29),
      I2 => bar0_data(29),
      O => reg_access_back_data(29)
    );
  reg_access_back_data_28_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(28),
      I2 => bar0_data(28),
      O => reg_access_back_data(28)
    );
  reg_access_back_data_27_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(27),
      I2 => bar0_data(27),
      O => reg_access_back_data(27)
    );
  reg_access_back_data_26_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(26),
      I2 => bar0_data(26),
      O => reg_access_back_data(26)
    );
  reg_access_back_data_25_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(25),
      I2 => bar0_data(25),
      O => reg_access_back_data(25)
    );
  reg_access_back_data_24_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(24),
      I2 => bar0_data(24),
      O => reg_access_back_data(24)
    );
  reg_access_back_data_23_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(23),
      I2 => bar0_data(23),
      O => reg_access_back_data(23)
    );
  reg_access_back_data_22_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(22),
      I2 => bar0_data(22),
      O => reg_access_back_data(22)
    );
  reg_access_back_data_21_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(21),
      I2 => bar0_data(21),
      O => reg_access_back_data(21)
    );
  reg_access_back_data_20_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(20),
      I2 => bar0_data(20),
      O => reg_access_back_data(20)
    );
  reg_access_back_data_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(1),
      I2 => bar0_data(1),
      O => reg_access_back_data(1)
    );
  reg_access_back_data_19_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(19),
      I2 => bar0_data(19),
      O => reg_access_back_data(19)
    );
  reg_access_back_data_18_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(18),
      I2 => bar0_data(18),
      O => reg_access_back_data(18)
    );
  reg_access_back_data_17_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(17),
      I2 => bar0_data(17),
      O => reg_access_back_data(17)
    );
  reg_access_back_data_16_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(16),
      I2 => bar0_data(16),
      O => reg_access_back_data(16)
    );
  reg_access_back_data_15_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(15),
      I2 => bar0_data(15),
      O => reg_access_back_data(15)
    );
  reg_access_back_data_14_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(14),
      I2 => bar0_data(14),
      O => reg_access_back_data(14)
    );
  reg_access_back_data_13_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(13),
      I2 => bar0_data(13),
      O => reg_access_back_data(13)
    );
  reg_access_back_data_12_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(12),
      I2 => bar0_data(12),
      O => reg_access_back_data(12)
    );
  reg_access_back_data_11_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(11),
      I2 => bar0_data(11),
      O => reg_access_back_data(11)
    );
  reg_access_back_data_10_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(10),
      I2 => bar0_data(10),
      O => reg_access_back_data(10)
    );
  reg_access_back_data_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => bar1_data(0),
      I2 => bar0_data(0),
      O => reg_access_back_data(0)
    );
  stp_FSM_FFd1_In1 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => reg_access_req_rd(0),
      I1 => stp_FSM_FFd1_9727,
      I2 => stp_FSM_FFd2_9729,
      I3 => reg_access_req_wr(0),
      O => stp_FSM_FFd1_In
    );
  st1p_FSM_FFd2_In1 : LUT5
    generic map(
      INIT => X"F2F2F222"
    )
    port map (
      I0 => st1p_FSM_FFd2_9722,
      I1 => disp_complete_9564,
      I2 => st1p_FSM_FFd3_9724,
      I3 => reg_access_req_rd(1),
      I4 => reg_access_req_wr(1),
      O => st1p_FSM_FFd2_In
    );
  st1p_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"FFA8A8A8"
    )
    port map (
      I0 => st1p_FSM_FFd1_9720,
      I1 => reg_access_req_rd(1),
      I2 => reg_access_req_wr(1),
      I3 => disp_complete_9564,
      I4 => st1p_FSM_FFd2_9722,
      O => st1p_FSM_FFd1_In
    );
  reg_ext_fifo_data_we_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => bar0_write_9441,
      I1 => NlwRenamedSignal_bp_adr(7),
      I2 => NlwRenamedSignal_bp_adr(17),
      O => reg_ext_fifo_data_we_and0000
    );
  bar0i_data_31_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(31),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(31),
      O => bar0i_data(31)
    );
  bar0i_data_30_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(30),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(30),
      O => bar0i_data(30)
    );
  bar0i_data_29_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(29),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(29),
      O => bar0i_data(29)
    );
  bar0i_data_28_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(28),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(28),
      O => bar0i_data(28)
    );
  bar0i_data_27_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(27),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(27),
      O => bar0i_data(27)
    );
  bar0i_data_26_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(26),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(26),
      O => bar0i_data(26)
    );
  bar0i_data_25_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(25),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(25),
      O => bar0i_data(25)
    );
  bar0i_data_24_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(24),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(24),
      O => bar0i_data(24)
    );
  bar0i_data_23_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(23),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(23),
      O => bar0i_data(23)
    );
  bar0i_data_22_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(22),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(22),
      O => bar0i_data(22)
    );
  bar0i_data_21_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(21),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(21),
      O => bar0i_data(21)
    );
  bar0i_data_20_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(20),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(20),
      O => bar0i_data(20)
    );
  bar0i_data_19_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(19),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(19),
      O => bar0i_data(19)
    );
  bar0i_data_18_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(18),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(18),
      O => bar0i_data(18)
    );
  bar0i_data_17_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(17),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(17),
      O => bar0i_data(17)
    );
  bar0i_data_16_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(16),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(16),
      O => bar0i_data(16)
    );
  bar0i_data_9_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(9),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(9),
      O => bar0i_data(9)
    );
  bar0i_data_8_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(8),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(8),
      O => bar0i_data(8)
    );
  bar0i_data_7_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(7),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(7),
      O => bar0i_data(7)
    );
  bar0i_data_6_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(6),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(6),
      O => bar0i_data(6)
    );
  bar0i_data_5_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(5),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(5),
      O => bar0i_data(5)
    );
  bar0i_data_4_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(4),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(4),
      O => bar0i_data(4)
    );
  bar0i_data_3_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(3),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(3),
      O => bar0i_data(3)
    );
  bar0i_data_2_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(2),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(2),
      O => bar0i_data(2)
    );
  bar0i_data_1_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(1),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(1),
      O => bar0i_data(1)
    );
  bar0i_data_15_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(15),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(15),
      O => bar0i_data(15)
    );
  bar0i_data_14_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(14),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(14),
      O => bar0i_data(14)
    );
  bar0i_data_13_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(13),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(13),
      O => bar0i_data(13)
    );
  bar0i_data_12_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(12),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(12),
      O => bar0i_data(12)
    );
  bar0i_data_11_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(11),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(11),
      O => bar0i_data(11)
    );
  bar0i_data_10_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(10),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(10),
      O => bar0i_data(10)
    );
  bar0i_data_0_1 : LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      I0 => NlwRenamedSignal_bp_adr(7),
      I1 => bp_data(0),
      I2 => NlwRenamedSignal_bp_adr(17),
      I3 => reg_ext_fifo_back_data(0),
      O => bar0i_data(0)
    );
  stp_cmp_eq0001_inv1_INV_0 : INV
    port map (
      I => stp_FSM_FFd2_9729,
      O => stp_cmp_eq0001_inv
    );
  st1p_cmp_eq0001_inv1_INV_0 : INV
    port map (
      I => st1p_FSM_FFd2_9722,
      O => st1p_cmp_eq0001_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_core64_m1 is
  port (
    bp_reg_rd : out STD_LOGIC; 
    clk_out : out STD_LOGIC; 
    pb_master_stb0 : out STD_LOGIC; 
    pb_master_stb1 : out STD_LOGIC; 
    aclk : in STD_LOGIC := 'X'; 
    bp_reg_we : out STD_LOGIC; 
    mgt250 : in STD_LOGIC := 'X'; 
    aclk_lock : in STD_LOGIC := 'X'; 
    bp_irq : in STD_LOGIC := 'X'; 
    pb_slave_stb0 : in STD_LOGIC := 'X'; 
    pb_slave_stb1 : in STD_LOGIC := 'X'; 
    pcie_link_up : out STD_LOGIC; 
    reset_out : out STD_LOGIC; 
    pb_slave_irq : in STD_LOGIC := 'X'; 
    perst : in STD_LOGIC := 'X'; 
    dcm_rstp : out STD_LOGIC; 
    bp_sel : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    bp_host_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    bp_rd : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    bp_we : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    pb_master_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    px : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pb_master_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    bp_adr : out STD_LOGIC_VECTOR ( 19 downto 0 ); 
    pb_master_cmd : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    pcie_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    bp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pb_slave_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_slave_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end pcie_core64_m1;

architecture STRUCTURE of pcie_core64_m1 is
  component core64_reg_access
    port (
      reg_access_back_data_we : out STD_LOGIC; 
      bp_reg_rd : out STD_LOGIC; 
      reg_ext_fifo_data_we : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      reg_disp_back_data_we : in STD_LOGIC := 'X'; 
      bp_reg_we : out STD_LOGIC; 
      reg_disp_back_complete : in STD_LOGIC := 'X'; 
      reg_disp_request_reg_rd : out STD_LOGIC; 
      bp_irq : in STD_LOGIC := 'X'; 
      reg_disp_request_reg_wr : out STD_LOGIC; 
      rstp : in STD_LOGIC := 'X'; 
      reg_access_back_complete : out STD_LOGIC; 
      reg_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bp_sel : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_disp_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bp_host_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bp_rd : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      reg_ext_fifo_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_ext_fifo_adr : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      bp_we : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      reg_access_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bp_adr : out STD_LOGIC_VECTOR ( 19 downto 0 ); 
      reg_access_req_rd : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      bp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_access_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_access_req_wr : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_ext_fifo_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_disp_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_access_data : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  component core64_pb_disp
    port (
      clk : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_data_we : out STD_LOGIC; 
      reg_disp_back_data_we : out STD_LOGIC; 
      pb_master_stb0 : out STD_LOGIC; 
      pb_master_stb1 : out STD_LOGIC; 
      aclk : in STD_LOGIC := 'X'; 
      reg_disp_back_complete : out STD_LOGIC; 
      reg_disp_request_reg_rd : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_irq : out STD_LOGIC; 
      pb_slave_stb0 : in STD_LOGIC := 'X'; 
      pb_slave_stb1 : in STD_LOGIC := 'X'; 
      reg_disp_request_reg_wr : in STD_LOGIC := 'X'; 
      rstp : in STD_LOGIC := 'X'; 
      ext_fifo_disp_data_we : in STD_LOGIC := 'X'; 
      ext_fifo_disp_request_rd : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_allow_wr : out STD_LOGIC; 
      ext_fifo_disp_request_wr : in STD_LOGIC := 'X'; 
      pb_slave_irq : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_back_dmar : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      pb_master_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_master_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_disp_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      pb_master_cmd : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      ext_fifo_disp_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_disp_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_disp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      pb_slave_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_slave_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      ext_fifo_disp_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component core64_interrupt
    port (
      irq : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      cfg_command10 : in STD_LOGIC := 'X'; 
      cfg_interrupt : out STD_LOGIC; 
      cfg_interrupt_assert : out STD_LOGIC; 
      rstp : in STD_LOGIC := 'X'; 
      cfg_interrupt_rdy : in STD_LOGIC := 'X' 
    );
  end component;
  component core64_rx_engine
    port (
      trn_rx_trn_rerrfwd_n : in STD_LOGIC := 'X'; 
      rx_tx_engine_complete_we : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      tx_rx_engine_complete_reg : in STD_LOGIC := 'X'; 
      trn_rx_trn_rsrc_dsc_n : in STD_LOGIC := 'X'; 
      rx_tx_engine_request_reg_wr : out STD_LOGIC; 
      trn_rx_trn_rsof_n : in STD_LOGIC := 'X'; 
      rstp : in STD_LOGIC := 'X'; 
      trn_rx_trn_rsrc_rdy_n : in STD_LOGIC := 'X'; 
      rx_ext_fifo_data_we : out STD_LOGIC; 
      trn_rx_back_trn_rnp_ok_n : out STD_LOGIC; 
      trn_rx_back_trn_rdst_rdy_n : out STD_LOGIC; 
      trn_rx_back_trn_rcpl_streaming_n : out STD_LOGIC; 
      trn_rx_trn_reof_n : in STD_LOGIC := 'X'; 
      rx_tx_engine_request_reg_rd : out STD_LOGIC; 
      reg_access_req_rd : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_access_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_access_req_wr : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      rx_tx_engine_request_attr : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      rx_tx_engine_request_id : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      rx_ext_fifo_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      rx_tx_engine_request_tc : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      reg_access_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      rx_ext_fifo_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
      rx_tx_engine_request_tag : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rx_tx_engine_lower_adr : out STD_LOGIC_VECTOR ( 6 downto 2 ); 
      trn_rx_trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_rx_trn_rbar_hit_n : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_rx_trn_rfc_npd_av : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rx_trn_rfc_ph_av : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rx_trn_rrem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rx_trn_rfc_pd_av : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
      trn_rx_trn_rfc_nph_av : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  component core64_tx_engine
    port (
      reg_access_back_data_we : in STD_LOGIC := 'X'; 
      rx_tx_engine_complete_we : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      tx_rx_engine_complete_reg : out STD_LOGIC; 
      tx_ext_fifo_back_rd_size : in STD_LOGIC := 'X'; 
      rx_tx_engine_request_reg_wr : in STD_LOGIC := 'X'; 
      trn_tx_trn_tsof_n : out STD_LOGIC; 
      tx_ext_fifo_complete_error : out STD_LOGIC; 
      trn_tx_trn_terrfwd_n : out STD_LOGIC; 
      rstp : in STD_LOGIC := 'X'; 
      tx_ext_fifo_back_req_rd : in STD_LOGIC := 'X'; 
      trn_tx_trn_tsrc_dsc_n : out STD_LOGIC; 
      trn_tx_back_trn_tdst_dsc_n : in STD_LOGIC := 'X'; 
      tx_ext_fifo_back_req_wr : in STD_LOGIC := 'X'; 
      tx_ext_fifo_complete_ok : out STD_LOGIC; 
      reg_access_back_complete : in STD_LOGIC := 'X'; 
      trn_tx_trn_teof_n : out STD_LOGIC; 
      rx_tx_engine_request_reg_rd : in STD_LOGIC := 'X'; 
      trn_tx_trn_tsrc_rdy_n : out STD_LOGIC; 
      trn_tx_back_trn_tdst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tx_trn_td : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trn_tx_trn_trem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      tx_ext_fifo_adr : out STD_LOGIC_VECTOR ( 8 downto 0 ); 
      tx_ext_fifo_back_pci_adr : in STD_LOGIC_VECTOR ( 39 downto 8 ); 
      tx_ext_fifo_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      completer_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      rx_tx_engine_request_attr : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      rx_tx_engine_request_id : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      reg_access_back_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      rx_tx_engine_request_tc : in STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_tx_back_trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
      rx_tx_engine_request_tag : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_tx_back_cfg_dcommand : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      rx_tx_engine_lower_adr : in STD_LOGIC_VECTOR ( 6 downto 2 ) 
    );
  end component;
  component block_pe_fifo_ext
    port (
      irq : out STD_LOGIC; 
      reg_ext_fifo_data_we : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      ext_fifo_disp_back_data_we : in STD_LOGIC := 'X'; 
      aclk : in STD_LOGIC := 'X'; 
      tx_ext_fifo_back_rd_size : out STD_LOGIC; 
      ext_fifo_disp_back_irq : in STD_LOGIC := 'X'; 
      tx_ext_fifo_complete_error : in STD_LOGIC := 'X'; 
      rstp : in STD_LOGIC := 'X'; 
      tx_ext_fifo_back_req_rd : out STD_LOGIC; 
      ext_fifo_disp_data_we : out STD_LOGIC; 
      rx_ext_fifo_data_we : in STD_LOGIC := 'X'; 
      tx_ext_fifo_back_req_wr : out STD_LOGIC; 
      ext_fifo_disp_request_rd : out STD_LOGIC; 
      ext_fifo_disp_back_allow_wr : in STD_LOGIC := 'X'; 
      tx_ext_fifo_complete_ok : in STD_LOGIC := 'X'; 
      ext_fifo_disp_request_wr : out STD_LOGIC; 
      ext_fifo_disp_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      tx_ext_fifo_back_pci_adr : out STD_LOGIC_VECTOR ( 39 downto 8 ); 
      tx_ext_fifo_back_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      reg_ext_fifo_back_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      ext_fifo_disp_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_back_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      ext_fifo_disp_back_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      reg_ext_fifo_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      reg_ext_fifo_adr : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      rx_ext_fifo_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      tx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
      rx_ext_fifo_adr : in STD_LOGIC_VECTOR ( 8 downto 0 ) 
    );
  end component;
  component ctrl_pcie_x8
    port (
      trn_rsrc_rdy_n : out STD_LOGIC; 
      trn_terrfwd_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_abort_n : in STD_LOGIC := 'X'; 
      trn_rerrfwd_n : out STD_LOGIC; 
      cfg_err_cpl_unexpect_n : in STD_LOGIC := 'X'; 
      trn_rnp_ok_n : in STD_LOGIC := 'X'; 
      cfg_to_turnoff_n : out STD_LOGIC; 
      trn_tsrc_dsc_n : in STD_LOGIC := 'X'; 
      refclkout : out STD_LOGIC; 
      cfg_rd_en_n : in STD_LOGIC := 'X'; 
      cfg_err_ecrc_n : in STD_LOGIC := 'X'; 
      trn_tdst_rdy_n : out STD_LOGIC; 
      trn_rsof_n : out STD_LOGIC; 
      cfg_rd_wr_done_n : out STD_LOGIC; 
      trn_teof_n : in STD_LOGIC := 'X'; 
      trn_rcpl_streaming_n : in STD_LOGIC := 'X'; 
      trn_clk : out STD_LOGIC; 
      cfg_err_locked_n : in STD_LOGIC := 'X'; 
      cfg_trn_pending_n : in STD_LOGIC := 'X'; 
      trn_reset_n : out STD_LOGIC; 
      trn_rsrc_dsc_n : out STD_LOGIC; 
      fast_train_simulation_only : in STD_LOGIC := 'X'; 
      cfg_err_cpl_timeout_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_msienable : out STD_LOGIC; 
      trn_rdst_rdy_n : in STD_LOGIC := 'X'; 
      trn_tsrc_rdy_n : in STD_LOGIC := 'X'; 
      cfg_err_ur_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_n : in STD_LOGIC := 'X'; 
      trn_tsof_n : in STD_LOGIC := 'X'; 
      cfg_wr_en_n : in STD_LOGIC := 'X'; 
      cfg_pm_wake_n : in STD_LOGIC := 'X'; 
      cfg_interrupt_rdy_n : out STD_LOGIC; 
      trn_tdst_dsc_n : out STD_LOGIC; 
      cfg_err_posted_n : in STD_LOGIC := 'X'; 
      cfg_err_cpl_rdy_n : out STD_LOGIC; 
      sys_reset_n : in STD_LOGIC := 'X'; 
      trn_reof_n : out STD_LOGIC; 
      cfg_err_cor_n : in STD_LOGIC := 'X'; 
      sys_clk : in STD_LOGIC := 'X'; 
      trn_lnk_up_n : out STD_LOGIC; 
      cfg_interrupt_assert_n : in STD_LOGIC := 'X'; 
      cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
      cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rfc_nph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rfc_ph_av : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_rrem_n : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trn_tbuf_av : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      trn_rbar_hit_n : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trn_rfc_npd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cfg_pcie_link_state_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rfc_pd_av : out STD_LOGIC_VECTOR ( 11 downto 0 ); 
      cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_do : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      cfg_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      trn_trem_n : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      cfg_di : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  signal cfg_err_cpl_timeout_n_c : STD_LOGIC; 
  signal cfg_interrupt_assert_n_c : STD_LOGIC; 
  signal cfg_interrupt_n_c : STD_LOGIC; 
  signal cfg_interrupt_rdy_n_c : STD_LOGIC; 
  signal NlwRenamedSig_OI_clk_out : STD_LOGIC; 
  signal ext_fifo_disp_back_allow_wr : STD_LOGIC; 
  signal ext_fifo_disp_back_data_we : STD_LOGIC; 
  signal ext_fifo_disp_back_irq : STD_LOGIC; 
  signal ext_fifo_disp_data_we : STD_LOGIC; 
  signal ext_fifo_disp_request_rd : STD_LOGIC; 
  signal ext_fifo_disp_request_wr : STD_LOGIC; 
  signal irq : STD_LOGIC; 
  signal pb_rstp_32527 : STD_LOGIC; 
  signal reg_access_back_complete : STD_LOGIC; 
  signal reg_access_back_data_we : STD_LOGIC; 
  signal reg_disp_back_complete : STD_LOGIC; 
  signal reg_disp_back_data_we : STD_LOGIC; 
  signal reg_disp_request_reg_rd : STD_LOGIC; 
  signal reg_disp_request_reg_wr : STD_LOGIC; 
  signal reg_ext_fifo_data_we : STD_LOGIC; 
  signal rstp_32898 : STD_LOGIC; 
  signal rx_ext_fifo_data_we : STD_LOGIC; 
  signal rx_tx_engine_complete_we : STD_LOGIC; 
  signal rx_tx_engine_request_reg_rd : STD_LOGIC; 
  signal rx_tx_engine_request_reg_wr : STD_LOGIC; 
  signal trn_reset_n_c : STD_LOGIC; 
  signal trn_rx_back_trn_rcpl_streaming_n : STD_LOGIC; 
  signal trn_rx_back_trn_rdst_rdy_n : STD_LOGIC; 
  signal trn_rx_trn_reof_n : STD_LOGIC; 
  signal trn_rx_trn_rerrfwd_n : STD_LOGIC; 
  signal trn_rx_trn_rsof_n : STD_LOGIC; 
  signal trn_rx_trn_rsrc_dsc_n : STD_LOGIC; 
  signal trn_rx_trn_rsrc_rdy_n : STD_LOGIC; 
  signal trn_tx_back_trn_tdst_dsc_n : STD_LOGIC; 
  signal trn_tx_back_trn_tdst_rdy_n : STD_LOGIC; 
  signal trn_tx_trn_teof_n : STD_LOGIC; 
  signal trn_tx_trn_terrfwd_n : STD_LOGIC; 
  signal trn_tx_trn_tsof_n : STD_LOGIC; 
  signal trn_tx_trn_tsrc_dsc_n : STD_LOGIC; 
  signal trn_tx_trn_tsrc_rdy_n : STD_LOGIC; 
  signal tx_ext_fifo_back_rd_size : STD_LOGIC; 
  signal tx_ext_fifo_back_req_rd : STD_LOGIC; 
  signal tx_ext_fifo_back_req_wr : STD_LOGIC; 
  signal tx_ext_fifo_complete_error : STD_LOGIC; 
  signal tx_ext_fifo_complete_ok : STD_LOGIC; 
  signal tx_rx_engine_complete_reg : STD_LOGIC; 
  signal NLW_ep_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_to_turnoff_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_refclkout_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_rd_wr_done_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_fast_train_simulation_only_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_msienable_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_posted_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_cpl_rdy_n_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dstatus_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_lcommand_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_status_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_do_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_mmenable_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_mmenable_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_mmenable_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_command_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_pcie_link_state_n_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_pcie_link_state_n_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_pcie_link_state_n_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_do_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_interrupt_di_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dsn_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_err_tlp_cpl_header_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_dwaddr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_ep_cfg_di_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_tx_trn_tx_back_trn_tbuf_av_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_tx_trn_tx_back_trn_tbuf_av_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_rx_trn_rx_back_trn_rnp_ok_n_UNCONNECTED : STD_LOGIC; 
  signal cfg_bus_number_c : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal cfg_command_c : STD_LOGIC_VECTOR ( 10 downto 10 ); 
  signal cfg_device_number_c : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal cfg_function_number_c : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal ext_fifo_disp_adr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal ext_fifo_disp_back_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal ext_fifo_disp_back_dmar : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal ext_fifo_disp_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal reg_access_adr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_access_back_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_access_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_access_req_rd : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal reg_access_req_wr : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal reg_disp_adr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_disp_back_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_disp_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_ext_fifo_adr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal reg_ext_fifo_back_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal reg_ext_fifo_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal rx_ext_fifo_adr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal rx_ext_fifo_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal rx_tx_engine_lower_adr : STD_LOGIC_VECTOR ( 6 downto 2 ); 
  signal rx_tx_engine_request_attr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal rx_tx_engine_request_id : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal rx_tx_engine_request_tag : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal rx_tx_engine_request_tc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal trn_rx_trn_rbar_hit_n : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal trn_rx_trn_rd : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal trn_rx_trn_rfc_npd_av : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal trn_rx_trn_rfc_nph_av : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal trn_rx_trn_rfc_pd_av : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal trn_rx_trn_rfc_ph_av : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal trn_rx_trn_rrem_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal trn_tx_back_cfg_dcommand : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal trn_tx_back_trn_tbuf_av : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal trn_tx_trn_td : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal trn_tx_trn_trem_n : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal tx_ext_fifo_adr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal tx_ext_fifo_back_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal tx_ext_fifo_back_pci_adr : STD_LOGIC_VECTOR ( 39 downto 8 ); 
begin
  clk_out <= NlwRenamedSig_OI_clk_out;
  XST_VCC : VCC
    port map (
      P => cfg_err_cpl_timeout_n_c
    );
  rstp : FDR
    port map (
      C => NlwRenamedSig_OI_clk_out,
      D => cfg_err_cpl_timeout_n_c,
      R => trn_reset_n_c,
      Q => rstp_32898
    );
  pb_rstp : FD
    port map (
      C => NlwRenamedSig_OI_clk_out,
      D => rstp_32898,
      Q => pb_rstp_32527
    );
  reset_out_7278 : FDR
    port map (
      C => NlwRenamedSig_OI_clk_out,
      D => cfg_err_cpl_timeout_n_c,
      R => pb_rstp_32527,
      Q => reset_out
    );
  reg : core64_reg_access
    port map (
      reg_access_back_data_we => reg_access_back_data_we,
      bp_reg_rd => bp_reg_rd,
      reg_ext_fifo_data_we => reg_ext_fifo_data_we,
      clk => NlwRenamedSig_OI_clk_out,
      reg_disp_back_data_we => reg_disp_back_data_we,
      bp_reg_we => bp_reg_we,
      reg_disp_back_complete => reg_disp_back_complete,
      reg_disp_request_reg_rd => reg_disp_request_reg_rd,
      bp_irq => bp_irq,
      reg_disp_request_reg_wr => reg_disp_request_reg_wr,
      rstp => rstp_32898,
      reg_access_back_complete => reg_access_back_complete,
      reg_disp_adr(31) => reg_disp_adr(31),
      reg_disp_adr(30) => reg_disp_adr(30),
      reg_disp_adr(29) => reg_disp_adr(29),
      reg_disp_adr(28) => reg_disp_adr(28),
      reg_disp_adr(27) => reg_disp_adr(27),
      reg_disp_adr(26) => reg_disp_adr(26),
      reg_disp_adr(25) => reg_disp_adr(25),
      reg_disp_adr(24) => reg_disp_adr(24),
      reg_disp_adr(23) => reg_disp_adr(23),
      reg_disp_adr(22) => reg_disp_adr(22),
      reg_disp_adr(21) => reg_disp_adr(21),
      reg_disp_adr(20) => reg_disp_adr(20),
      reg_disp_adr(19) => reg_disp_adr(19),
      reg_disp_adr(18) => reg_disp_adr(18),
      reg_disp_adr(17) => reg_disp_adr(17),
      reg_disp_adr(16) => reg_disp_adr(16),
      reg_disp_adr(15) => reg_disp_adr(15),
      reg_disp_adr(14) => reg_disp_adr(14),
      reg_disp_adr(13) => reg_disp_adr(13),
      reg_disp_adr(12) => reg_disp_adr(12),
      reg_disp_adr(11) => reg_disp_adr(11),
      reg_disp_adr(10) => reg_disp_adr(10),
      reg_disp_adr(9) => reg_disp_adr(9),
      reg_disp_adr(8) => reg_disp_adr(8),
      reg_disp_adr(7) => reg_disp_adr(7),
      reg_disp_adr(6) => reg_disp_adr(6),
      reg_disp_adr(5) => reg_disp_adr(5),
      reg_disp_adr(4) => reg_disp_adr(4),
      reg_disp_adr(3) => reg_disp_adr(3),
      reg_disp_adr(2) => reg_disp_adr(2),
      reg_disp_adr(1) => reg_disp_adr(1),
      reg_disp_adr(0) => reg_disp_adr(0),
      bp_sel(1) => bp_sel(1),
      bp_sel(0) => bp_sel(0),
      reg_disp_data(31) => reg_disp_data(31),
      reg_disp_data(30) => reg_disp_data(30),
      reg_disp_data(29) => reg_disp_data(29),
      reg_disp_data(28) => reg_disp_data(28),
      reg_disp_data(27) => reg_disp_data(27),
      reg_disp_data(26) => reg_disp_data(26),
      reg_disp_data(25) => reg_disp_data(25),
      reg_disp_data(24) => reg_disp_data(24),
      reg_disp_data(23) => reg_disp_data(23),
      reg_disp_data(22) => reg_disp_data(22),
      reg_disp_data(21) => reg_disp_data(21),
      reg_disp_data(20) => reg_disp_data(20),
      reg_disp_data(19) => reg_disp_data(19),
      reg_disp_data(18) => reg_disp_data(18),
      reg_disp_data(17) => reg_disp_data(17),
      reg_disp_data(16) => reg_disp_data(16),
      reg_disp_data(15) => reg_disp_data(15),
      reg_disp_data(14) => reg_disp_data(14),
      reg_disp_data(13) => reg_disp_data(13),
      reg_disp_data(12) => reg_disp_data(12),
      reg_disp_data(11) => reg_disp_data(11),
      reg_disp_data(10) => reg_disp_data(10),
      reg_disp_data(9) => reg_disp_data(9),
      reg_disp_data(8) => reg_disp_data(8),
      reg_disp_data(7) => reg_disp_data(7),
      reg_disp_data(6) => reg_disp_data(6),
      reg_disp_data(5) => reg_disp_data(5),
      reg_disp_data(4) => reg_disp_data(4),
      reg_disp_data(3) => reg_disp_data(3),
      reg_disp_data(2) => reg_disp_data(2),
      reg_disp_data(1) => reg_disp_data(1),
      reg_disp_data(0) => reg_disp_data(0),
      bp_host_data(31) => bp_host_data(31),
      bp_host_data(30) => bp_host_data(30),
      bp_host_data(29) => bp_host_data(29),
      bp_host_data(28) => bp_host_data(28),
      bp_host_data(27) => bp_host_data(27),
      bp_host_data(26) => bp_host_data(26),
      bp_host_data(25) => bp_host_data(25),
      bp_host_data(24) => bp_host_data(24),
      bp_host_data(23) => bp_host_data(23),
      bp_host_data(22) => bp_host_data(22),
      bp_host_data(21) => bp_host_data(21),
      bp_host_data(20) => bp_host_data(20),
      bp_host_data(19) => bp_host_data(19),
      bp_host_data(18) => bp_host_data(18),
      bp_host_data(17) => bp_host_data(17),
      bp_host_data(16) => bp_host_data(16),
      bp_host_data(15) => bp_host_data(15),
      bp_host_data(14) => bp_host_data(14),
      bp_host_data(13) => bp_host_data(13),
      bp_host_data(12) => bp_host_data(12),
      bp_host_data(11) => bp_host_data(11),
      bp_host_data(10) => bp_host_data(10),
      bp_host_data(9) => bp_host_data(9),
      bp_host_data(8) => bp_host_data(8),
      bp_host_data(7) => bp_host_data(7),
      bp_host_data(6) => bp_host_data(6),
      bp_host_data(5) => bp_host_data(5),
      bp_host_data(4) => bp_host_data(4),
      bp_host_data(3) => bp_host_data(3),
      bp_host_data(2) => bp_host_data(2),
      bp_host_data(1) => bp_host_data(1),
      bp_host_data(0) => bp_host_data(0),
      bp_rd(3) => bp_rd(3),
      bp_rd(2) => bp_rd(2),
      bp_rd(1) => bp_rd(1),
      bp_rd(0) => bp_rd(0),
      reg_ext_fifo_data(31) => reg_ext_fifo_data(31),
      reg_ext_fifo_data(30) => reg_ext_fifo_data(30),
      reg_ext_fifo_data(29) => reg_ext_fifo_data(29),
      reg_ext_fifo_data(28) => reg_ext_fifo_data(28),
      reg_ext_fifo_data(27) => reg_ext_fifo_data(27),
      reg_ext_fifo_data(26) => reg_ext_fifo_data(26),
      reg_ext_fifo_data(25) => reg_ext_fifo_data(25),
      reg_ext_fifo_data(24) => reg_ext_fifo_data(24),
      reg_ext_fifo_data(23) => reg_ext_fifo_data(23),
      reg_ext_fifo_data(22) => reg_ext_fifo_data(22),
      reg_ext_fifo_data(21) => reg_ext_fifo_data(21),
      reg_ext_fifo_data(20) => reg_ext_fifo_data(20),
      reg_ext_fifo_data(19) => reg_ext_fifo_data(19),
      reg_ext_fifo_data(18) => reg_ext_fifo_data(18),
      reg_ext_fifo_data(17) => reg_ext_fifo_data(17),
      reg_ext_fifo_data(16) => reg_ext_fifo_data(16),
      reg_ext_fifo_data(15) => reg_ext_fifo_data(15),
      reg_ext_fifo_data(14) => reg_ext_fifo_data(14),
      reg_ext_fifo_data(13) => reg_ext_fifo_data(13),
      reg_ext_fifo_data(12) => reg_ext_fifo_data(12),
      reg_ext_fifo_data(11) => reg_ext_fifo_data(11),
      reg_ext_fifo_data(10) => reg_ext_fifo_data(10),
      reg_ext_fifo_data(9) => reg_ext_fifo_data(9),
      reg_ext_fifo_data(8) => reg_ext_fifo_data(8),
      reg_ext_fifo_data(7) => reg_ext_fifo_data(7),
      reg_ext_fifo_data(6) => reg_ext_fifo_data(6),
      reg_ext_fifo_data(5) => reg_ext_fifo_data(5),
      reg_ext_fifo_data(4) => reg_ext_fifo_data(4),
      reg_ext_fifo_data(3) => reg_ext_fifo_data(3),
      reg_ext_fifo_data(2) => reg_ext_fifo_data(2),
      reg_ext_fifo_data(1) => reg_ext_fifo_data(1),
      reg_ext_fifo_data(0) => reg_ext_fifo_data(0),
      reg_ext_fifo_adr(6) => reg_ext_fifo_adr(6),
      reg_ext_fifo_adr(5) => reg_ext_fifo_adr(5),
      reg_ext_fifo_adr(4) => reg_ext_fifo_adr(4),
      reg_ext_fifo_adr(3) => reg_ext_fifo_adr(3),
      reg_ext_fifo_adr(2) => reg_ext_fifo_adr(2),
      reg_ext_fifo_adr(1) => reg_ext_fifo_adr(1),
      reg_ext_fifo_adr(0) => reg_ext_fifo_adr(0),
      bp_we(3) => bp_we(3),
      bp_we(2) => bp_we(2),
      bp_we(1) => bp_we(1),
      bp_we(0) => bp_we(0),
      reg_access_back_data(31) => reg_access_back_data(31),
      reg_access_back_data(30) => reg_access_back_data(30),
      reg_access_back_data(29) => reg_access_back_data(29),
      reg_access_back_data(28) => reg_access_back_data(28),
      reg_access_back_data(27) => reg_access_back_data(27),
      reg_access_back_data(26) => reg_access_back_data(26),
      reg_access_back_data(25) => reg_access_back_data(25),
      reg_access_back_data(24) => reg_access_back_data(24),
      reg_access_back_data(23) => reg_access_back_data(23),
      reg_access_back_data(22) => reg_access_back_data(22),
      reg_access_back_data(21) => reg_access_back_data(21),
      reg_access_back_data(20) => reg_access_back_data(20),
      reg_access_back_data(19) => reg_access_back_data(19),
      reg_access_back_data(18) => reg_access_back_data(18),
      reg_access_back_data(17) => reg_access_back_data(17),
      reg_access_back_data(16) => reg_access_back_data(16),
      reg_access_back_data(15) => reg_access_back_data(15),
      reg_access_back_data(14) => reg_access_back_data(14),
      reg_access_back_data(13) => reg_access_back_data(13),
      reg_access_back_data(12) => reg_access_back_data(12),
      reg_access_back_data(11) => reg_access_back_data(11),
      reg_access_back_data(10) => reg_access_back_data(10),
      reg_access_back_data(9) => reg_access_back_data(9),
      reg_access_back_data(8) => reg_access_back_data(8),
      reg_access_back_data(7) => reg_access_back_data(7),
      reg_access_back_data(6) => reg_access_back_data(6),
      reg_access_back_data(5) => reg_access_back_data(5),
      reg_access_back_data(4) => reg_access_back_data(4),
      reg_access_back_data(3) => reg_access_back_data(3),
      reg_access_back_data(2) => reg_access_back_data(2),
      reg_access_back_data(1) => reg_access_back_data(1),
      reg_access_back_data(0) => reg_access_back_data(0),
      bp_adr(19) => bp_adr(19),
      bp_adr(18) => bp_adr(18),
      bp_adr(17) => bp_adr(17),
      bp_adr(16) => bp_adr(16),
      bp_adr(15) => bp_adr(15),
      bp_adr(14) => bp_adr(14),
      bp_adr(13) => bp_adr(13),
      bp_adr(12) => bp_adr(12),
      bp_adr(11) => bp_adr(11),
      bp_adr(10) => bp_adr(10),
      bp_adr(9) => bp_adr(9),
      bp_adr(8) => bp_adr(8),
      bp_adr(7) => bp_adr(7),
      bp_adr(6) => bp_adr(6),
      bp_adr(5) => bp_adr(5),
      bp_adr(4) => bp_adr(4),
      bp_adr(3) => bp_adr(3),
      bp_adr(2) => bp_adr(2),
      bp_adr(1) => bp_adr(1),
      bp_adr(0) => bp_adr(0),
      reg_access_req_rd(1) => reg_access_req_rd(1),
      reg_access_req_rd(0) => reg_access_req_rd(0),
      bp_data(31) => bp_data(31),
      bp_data(30) => bp_data(30),
      bp_data(29) => bp_data(29),
      bp_data(28) => bp_data(28),
      bp_data(27) => bp_data(27),
      bp_data(26) => bp_data(26),
      bp_data(25) => bp_data(25),
      bp_data(24) => bp_data(24),
      bp_data(23) => bp_data(23),
      bp_data(22) => bp_data(22),
      bp_data(21) => bp_data(21),
      bp_data(20) => bp_data(20),
      bp_data(19) => bp_data(19),
      bp_data(18) => bp_data(18),
      bp_data(17) => bp_data(17),
      bp_data(16) => bp_data(16),
      bp_data(15) => bp_data(15),
      bp_data(14) => bp_data(14),
      bp_data(13) => bp_data(13),
      bp_data(12) => bp_data(12),
      bp_data(11) => bp_data(11),
      bp_data(10) => bp_data(10),
      bp_data(9) => bp_data(9),
      bp_data(8) => bp_data(8),
      bp_data(7) => bp_data(7),
      bp_data(6) => bp_data(6),
      bp_data(5) => bp_data(5),
      bp_data(4) => bp_data(4),
      bp_data(3) => bp_data(3),
      bp_data(2) => bp_data(2),
      bp_data(1) => bp_data(1),
      bp_data(0) => bp_data(0),
      reg_access_adr(31) => reg_access_adr(31),
      reg_access_adr(30) => reg_access_adr(30),
      reg_access_adr(29) => reg_access_adr(29),
      reg_access_adr(28) => reg_access_adr(28),
      reg_access_adr(27) => reg_access_adr(27),
      reg_access_adr(26) => reg_access_adr(26),
      reg_access_adr(25) => reg_access_adr(25),
      reg_access_adr(24) => reg_access_adr(24),
      reg_access_adr(23) => reg_access_adr(23),
      reg_access_adr(22) => reg_access_adr(22),
      reg_access_adr(21) => reg_access_adr(21),
      reg_access_adr(20) => reg_access_adr(20),
      reg_access_adr(19) => reg_access_adr(19),
      reg_access_adr(18) => reg_access_adr(18),
      reg_access_adr(17) => reg_access_adr(17),
      reg_access_adr(16) => reg_access_adr(16),
      reg_access_adr(15) => reg_access_adr(15),
      reg_access_adr(14) => reg_access_adr(14),
      reg_access_adr(13) => reg_access_adr(13),
      reg_access_adr(12) => reg_access_adr(12),
      reg_access_adr(11) => reg_access_adr(11),
      reg_access_adr(10) => reg_access_adr(10),
      reg_access_adr(9) => reg_access_adr(9),
      reg_access_adr(8) => reg_access_adr(8),
      reg_access_adr(7) => reg_access_adr(7),
      reg_access_adr(6) => reg_access_adr(6),
      reg_access_adr(5) => reg_access_adr(5),
      reg_access_adr(4) => reg_access_adr(4),
      reg_access_adr(3) => reg_access_adr(3),
      reg_access_adr(2) => reg_access_adr(2),
      reg_access_adr(1) => reg_access_adr(1),
      reg_access_adr(0) => reg_access_adr(0),
      reg_access_req_wr(1) => reg_access_req_wr(1),
      reg_access_req_wr(0) => reg_access_req_wr(0),
      reg_ext_fifo_back_data(31) => reg_ext_fifo_back_data(31),
      reg_ext_fifo_back_data(30) => reg_ext_fifo_back_data(30),
      reg_ext_fifo_back_data(29) => reg_ext_fifo_back_data(29),
      reg_ext_fifo_back_data(28) => reg_ext_fifo_back_data(28),
      reg_ext_fifo_back_data(27) => reg_ext_fifo_back_data(27),
      reg_ext_fifo_back_data(26) => reg_ext_fifo_back_data(26),
      reg_ext_fifo_back_data(25) => reg_ext_fifo_back_data(25),
      reg_ext_fifo_back_data(24) => reg_ext_fifo_back_data(24),
      reg_ext_fifo_back_data(23) => reg_ext_fifo_back_data(23),
      reg_ext_fifo_back_data(22) => reg_ext_fifo_back_data(22),
      reg_ext_fifo_back_data(21) => reg_ext_fifo_back_data(21),
      reg_ext_fifo_back_data(20) => reg_ext_fifo_back_data(20),
      reg_ext_fifo_back_data(19) => reg_ext_fifo_back_data(19),
      reg_ext_fifo_back_data(18) => reg_ext_fifo_back_data(18),
      reg_ext_fifo_back_data(17) => reg_ext_fifo_back_data(17),
      reg_ext_fifo_back_data(16) => reg_ext_fifo_back_data(16),
      reg_ext_fifo_back_data(15) => reg_ext_fifo_back_data(15),
      reg_ext_fifo_back_data(14) => reg_ext_fifo_back_data(14),
      reg_ext_fifo_back_data(13) => reg_ext_fifo_back_data(13),
      reg_ext_fifo_back_data(12) => reg_ext_fifo_back_data(12),
      reg_ext_fifo_back_data(11) => reg_ext_fifo_back_data(11),
      reg_ext_fifo_back_data(10) => reg_ext_fifo_back_data(10),
      reg_ext_fifo_back_data(9) => reg_ext_fifo_back_data(9),
      reg_ext_fifo_back_data(8) => reg_ext_fifo_back_data(8),
      reg_ext_fifo_back_data(7) => reg_ext_fifo_back_data(7),
      reg_ext_fifo_back_data(6) => reg_ext_fifo_back_data(6),
      reg_ext_fifo_back_data(5) => reg_ext_fifo_back_data(5),
      reg_ext_fifo_back_data(4) => reg_ext_fifo_back_data(4),
      reg_ext_fifo_back_data(3) => reg_ext_fifo_back_data(3),
      reg_ext_fifo_back_data(2) => reg_ext_fifo_back_data(2),
      reg_ext_fifo_back_data(1) => reg_ext_fifo_back_data(1),
      reg_ext_fifo_back_data(0) => reg_ext_fifo_back_data(0),
      reg_disp_back_data(31) => reg_disp_back_data(31),
      reg_disp_back_data(30) => reg_disp_back_data(30),
      reg_disp_back_data(29) => reg_disp_back_data(29),
      reg_disp_back_data(28) => reg_disp_back_data(28),
      reg_disp_back_data(27) => reg_disp_back_data(27),
      reg_disp_back_data(26) => reg_disp_back_data(26),
      reg_disp_back_data(25) => reg_disp_back_data(25),
      reg_disp_back_data(24) => reg_disp_back_data(24),
      reg_disp_back_data(23) => reg_disp_back_data(23),
      reg_disp_back_data(22) => reg_disp_back_data(22),
      reg_disp_back_data(21) => reg_disp_back_data(21),
      reg_disp_back_data(20) => reg_disp_back_data(20),
      reg_disp_back_data(19) => reg_disp_back_data(19),
      reg_disp_back_data(18) => reg_disp_back_data(18),
      reg_disp_back_data(17) => reg_disp_back_data(17),
      reg_disp_back_data(16) => reg_disp_back_data(16),
      reg_disp_back_data(15) => reg_disp_back_data(15),
      reg_disp_back_data(14) => reg_disp_back_data(14),
      reg_disp_back_data(13) => reg_disp_back_data(13),
      reg_disp_back_data(12) => reg_disp_back_data(12),
      reg_disp_back_data(11) => reg_disp_back_data(11),
      reg_disp_back_data(10) => reg_disp_back_data(10),
      reg_disp_back_data(9) => reg_disp_back_data(9),
      reg_disp_back_data(8) => reg_disp_back_data(8),
      reg_disp_back_data(7) => reg_disp_back_data(7),
      reg_disp_back_data(6) => reg_disp_back_data(6),
      reg_disp_back_data(5) => reg_disp_back_data(5),
      reg_disp_back_data(4) => reg_disp_back_data(4),
      reg_disp_back_data(3) => reg_disp_back_data(3),
      reg_disp_back_data(2) => reg_disp_back_data(2),
      reg_disp_back_data(1) => reg_disp_back_data(1),
      reg_disp_back_data(0) => reg_disp_back_data(0),
      reg_access_data(31) => reg_access_data(31),
      reg_access_data(30) => reg_access_data(30),
      reg_access_data(29) => reg_access_data(29),
      reg_access_data(28) => reg_access_data(28),
      reg_access_data(27) => reg_access_data(27),
      reg_access_data(26) => reg_access_data(26),
      reg_access_data(25) => reg_access_data(25),
      reg_access_data(24) => reg_access_data(24),
      reg_access_data(23) => reg_access_data(23),
      reg_access_data(22) => reg_access_data(22),
      reg_access_data(21) => reg_access_data(21),
      reg_access_data(20) => reg_access_data(20),
      reg_access_data(19) => reg_access_data(19),
      reg_access_data(18) => reg_access_data(18),
      reg_access_data(17) => reg_access_data(17),
      reg_access_data(16) => reg_access_data(16),
      reg_access_data(15) => reg_access_data(15),
      reg_access_data(14) => reg_access_data(14),
      reg_access_data(13) => reg_access_data(13),
      reg_access_data(12) => reg_access_data(12),
      reg_access_data(11) => reg_access_data(11),
      reg_access_data(10) => reg_access_data(10),
      reg_access_data(9) => reg_access_data(9),
      reg_access_data(8) => reg_access_data(8),
      reg_access_data(7) => reg_access_data(7),
      reg_access_data(6) => reg_access_data(6),
      reg_access_data(5) => reg_access_data(5),
      reg_access_data(4) => reg_access_data(4),
      reg_access_data(3) => reg_access_data(3),
      reg_access_data(2) => reg_access_data(2),
      reg_access_data(1) => reg_access_data(1),
      reg_access_data(0) => reg_access_data(0)
    );
  disp : core64_pb_disp
    port map (
      clk => NlwRenamedSig_OI_clk_out,
      ext_fifo_disp_back_data_we => ext_fifo_disp_back_data_we,
      reg_disp_back_data_we => reg_disp_back_data_we,
      pb_master_stb0 => pb_master_stb0,
      pb_master_stb1 => pb_master_stb1,
      aclk => aclk,
      reg_disp_back_complete => reg_disp_back_complete,
      reg_disp_request_reg_rd => reg_disp_request_reg_rd,
      ext_fifo_disp_back_irq => ext_fifo_disp_back_irq,
      pb_slave_stb0 => pb_slave_stb0,
      pb_slave_stb1 => pb_slave_stb1,
      reg_disp_request_reg_wr => reg_disp_request_reg_wr,
      rstp => pb_rstp_32527,
      ext_fifo_disp_data_we => ext_fifo_disp_data_we,
      ext_fifo_disp_request_rd => ext_fifo_disp_request_rd,
      ext_fifo_disp_back_allow_wr => ext_fifo_disp_back_allow_wr,
      ext_fifo_disp_request_wr => ext_fifo_disp_request_wr,
      pb_slave_irq => pb_slave_irq,
      ext_fifo_disp_back_data(63) => ext_fifo_disp_back_data(63),
      ext_fifo_disp_back_data(62) => ext_fifo_disp_back_data(62),
      ext_fifo_disp_back_data(61) => ext_fifo_disp_back_data(61),
      ext_fifo_disp_back_data(60) => ext_fifo_disp_back_data(60),
      ext_fifo_disp_back_data(59) => ext_fifo_disp_back_data(59),
      ext_fifo_disp_back_data(58) => ext_fifo_disp_back_data(58),
      ext_fifo_disp_back_data(57) => ext_fifo_disp_back_data(57),
      ext_fifo_disp_back_data(56) => ext_fifo_disp_back_data(56),
      ext_fifo_disp_back_data(55) => ext_fifo_disp_back_data(55),
      ext_fifo_disp_back_data(54) => ext_fifo_disp_back_data(54),
      ext_fifo_disp_back_data(53) => ext_fifo_disp_back_data(53),
      ext_fifo_disp_back_data(52) => ext_fifo_disp_back_data(52),
      ext_fifo_disp_back_data(51) => ext_fifo_disp_back_data(51),
      ext_fifo_disp_back_data(50) => ext_fifo_disp_back_data(50),
      ext_fifo_disp_back_data(49) => ext_fifo_disp_back_data(49),
      ext_fifo_disp_back_data(48) => ext_fifo_disp_back_data(48),
      ext_fifo_disp_back_data(47) => ext_fifo_disp_back_data(47),
      ext_fifo_disp_back_data(46) => ext_fifo_disp_back_data(46),
      ext_fifo_disp_back_data(45) => ext_fifo_disp_back_data(45),
      ext_fifo_disp_back_data(44) => ext_fifo_disp_back_data(44),
      ext_fifo_disp_back_data(43) => ext_fifo_disp_back_data(43),
      ext_fifo_disp_back_data(42) => ext_fifo_disp_back_data(42),
      ext_fifo_disp_back_data(41) => ext_fifo_disp_back_data(41),
      ext_fifo_disp_back_data(40) => ext_fifo_disp_back_data(40),
      ext_fifo_disp_back_data(39) => ext_fifo_disp_back_data(39),
      ext_fifo_disp_back_data(38) => ext_fifo_disp_back_data(38),
      ext_fifo_disp_back_data(37) => ext_fifo_disp_back_data(37),
      ext_fifo_disp_back_data(36) => ext_fifo_disp_back_data(36),
      ext_fifo_disp_back_data(35) => ext_fifo_disp_back_data(35),
      ext_fifo_disp_back_data(34) => ext_fifo_disp_back_data(34),
      ext_fifo_disp_back_data(33) => ext_fifo_disp_back_data(33),
      ext_fifo_disp_back_data(32) => ext_fifo_disp_back_data(32),
      ext_fifo_disp_back_data(31) => ext_fifo_disp_back_data(31),
      ext_fifo_disp_back_data(30) => ext_fifo_disp_back_data(30),
      ext_fifo_disp_back_data(29) => ext_fifo_disp_back_data(29),
      ext_fifo_disp_back_data(28) => ext_fifo_disp_back_data(28),
      ext_fifo_disp_back_data(27) => ext_fifo_disp_back_data(27),
      ext_fifo_disp_back_data(26) => ext_fifo_disp_back_data(26),
      ext_fifo_disp_back_data(25) => ext_fifo_disp_back_data(25),
      ext_fifo_disp_back_data(24) => ext_fifo_disp_back_data(24),
      ext_fifo_disp_back_data(23) => ext_fifo_disp_back_data(23),
      ext_fifo_disp_back_data(22) => ext_fifo_disp_back_data(22),
      ext_fifo_disp_back_data(21) => ext_fifo_disp_back_data(21),
      ext_fifo_disp_back_data(20) => ext_fifo_disp_back_data(20),
      ext_fifo_disp_back_data(19) => ext_fifo_disp_back_data(19),
      ext_fifo_disp_back_data(18) => ext_fifo_disp_back_data(18),
      ext_fifo_disp_back_data(17) => ext_fifo_disp_back_data(17),
      ext_fifo_disp_back_data(16) => ext_fifo_disp_back_data(16),
      ext_fifo_disp_back_data(15) => ext_fifo_disp_back_data(15),
      ext_fifo_disp_back_data(14) => ext_fifo_disp_back_data(14),
      ext_fifo_disp_back_data(13) => ext_fifo_disp_back_data(13),
      ext_fifo_disp_back_data(12) => ext_fifo_disp_back_data(12),
      ext_fifo_disp_back_data(11) => ext_fifo_disp_back_data(11),
      ext_fifo_disp_back_data(10) => ext_fifo_disp_back_data(10),
      ext_fifo_disp_back_data(9) => ext_fifo_disp_back_data(9),
      ext_fifo_disp_back_data(8) => ext_fifo_disp_back_data(8),
      ext_fifo_disp_back_data(7) => ext_fifo_disp_back_data(7),
      ext_fifo_disp_back_data(6) => ext_fifo_disp_back_data(6),
      ext_fifo_disp_back_data(5) => ext_fifo_disp_back_data(5),
      ext_fifo_disp_back_data(4) => ext_fifo_disp_back_data(4),
      ext_fifo_disp_back_data(3) => ext_fifo_disp_back_data(3),
      ext_fifo_disp_back_data(2) => ext_fifo_disp_back_data(2),
      ext_fifo_disp_back_data(1) => ext_fifo_disp_back_data(1),
      ext_fifo_disp_back_data(0) => ext_fifo_disp_back_data(0),
      ext_fifo_disp_back_dmar(1) => ext_fifo_disp_back_dmar(1),
      ext_fifo_disp_back_dmar(0) => ext_fifo_disp_back_dmar(0),
      pb_master_data(63) => pb_master_data(63),
      pb_master_data(62) => pb_master_data(62),
      pb_master_data(61) => pb_master_data(61),
      pb_master_data(60) => pb_master_data(60),
      pb_master_data(59) => pb_master_data(59),
      pb_master_data(58) => pb_master_data(58),
      pb_master_data(57) => pb_master_data(57),
      pb_master_data(56) => pb_master_data(56),
      pb_master_data(55) => pb_master_data(55),
      pb_master_data(54) => pb_master_data(54),
      pb_master_data(53) => pb_master_data(53),
      pb_master_data(52) => pb_master_data(52),
      pb_master_data(51) => pb_master_data(51),
      pb_master_data(50) => pb_master_data(50),
      pb_master_data(49) => pb_master_data(49),
      pb_master_data(48) => pb_master_data(48),
      pb_master_data(47) => pb_master_data(47),
      pb_master_data(46) => pb_master_data(46),
      pb_master_data(45) => pb_master_data(45),
      pb_master_data(44) => pb_master_data(44),
      pb_master_data(43) => pb_master_data(43),
      pb_master_data(42) => pb_master_data(42),
      pb_master_data(41) => pb_master_data(41),
      pb_master_data(40) => pb_master_data(40),
      pb_master_data(39) => pb_master_data(39),
      pb_master_data(38) => pb_master_data(38),
      pb_master_data(37) => pb_master_data(37),
      pb_master_data(36) => pb_master_data(36),
      pb_master_data(35) => pb_master_data(35),
      pb_master_data(34) => pb_master_data(34),
      pb_master_data(33) => pb_master_data(33),
      pb_master_data(32) => pb_master_data(32),
      pb_master_data(31) => pb_master_data(31),
      pb_master_data(30) => pb_master_data(30),
      pb_master_data(29) => pb_master_data(29),
      pb_master_data(28) => pb_master_data(28),
      pb_master_data(27) => pb_master_data(27),
      pb_master_data(26) => pb_master_data(26),
      pb_master_data(25) => pb_master_data(25),
      pb_master_data(24) => pb_master_data(24),
      pb_master_data(23) => pb_master_data(23),
      pb_master_data(22) => pb_master_data(22),
      pb_master_data(21) => pb_master_data(21),
      pb_master_data(20) => pb_master_data(20),
      pb_master_data(19) => pb_master_data(19),
      pb_master_data(18) => pb_master_data(18),
      pb_master_data(17) => pb_master_data(17),
      pb_master_data(16) => pb_master_data(16),
      pb_master_data(15) => pb_master_data(15),
      pb_master_data(14) => pb_master_data(14),
      pb_master_data(13) => pb_master_data(13),
      pb_master_data(12) => pb_master_data(12),
      pb_master_data(11) => pb_master_data(11),
      pb_master_data(10) => pb_master_data(10),
      pb_master_data(9) => pb_master_data(9),
      pb_master_data(8) => pb_master_data(8),
      pb_master_data(7) => pb_master_data(7),
      pb_master_data(6) => pb_master_data(6),
      pb_master_data(5) => pb_master_data(5),
      pb_master_data(4) => pb_master_data(4),
      pb_master_data(3) => pb_master_data(3),
      pb_master_data(2) => pb_master_data(2),
      pb_master_data(1) => pb_master_data(1),
      pb_master_data(0) => pb_master_data(0),
      pb_master_adr(31) => pb_master_adr(31),
      pb_master_adr(30) => pb_master_adr(30),
      pb_master_adr(29) => pb_master_adr(29),
      pb_master_adr(28) => pb_master_adr(28),
      pb_master_adr(27) => pb_master_adr(27),
      pb_master_adr(26) => pb_master_adr(26),
      pb_master_adr(25) => pb_master_adr(25),
      pb_master_adr(24) => pb_master_adr(24),
      pb_master_adr(23) => pb_master_adr(23),
      pb_master_adr(22) => pb_master_adr(22),
      pb_master_adr(21) => pb_master_adr(21),
      pb_master_adr(20) => pb_master_adr(20),
      pb_master_adr(19) => pb_master_adr(19),
      pb_master_adr(18) => pb_master_adr(18),
      pb_master_adr(17) => pb_master_adr(17),
      pb_master_adr(16) => pb_master_adr(16),
      pb_master_adr(15) => pb_master_adr(15),
      pb_master_adr(14) => pb_master_adr(14),
      pb_master_adr(13) => pb_master_adr(13),
      pb_master_adr(12) => pb_master_adr(12),
      pb_master_adr(11) => pb_master_adr(11),
      pb_master_adr(10) => pb_master_adr(10),
      pb_master_adr(9) => pb_master_adr(9),
      pb_master_adr(8) => pb_master_adr(8),
      pb_master_adr(7) => pb_master_adr(7),
      pb_master_adr(6) => pb_master_adr(6),
      pb_master_adr(5) => pb_master_adr(5),
      pb_master_adr(4) => pb_master_adr(4),
      pb_master_adr(3) => pb_master_adr(3),
      pb_master_adr(2) => pb_master_adr(2),
      pb_master_adr(1) => pb_master_adr(1),
      pb_master_adr(0) => pb_master_adr(0),
      reg_disp_back_data(31) => reg_disp_back_data(31),
      reg_disp_back_data(30) => reg_disp_back_data(30),
      reg_disp_back_data(29) => reg_disp_back_data(29),
      reg_disp_back_data(28) => reg_disp_back_data(28),
      reg_disp_back_data(27) => reg_disp_back_data(27),
      reg_disp_back_data(26) => reg_disp_back_data(26),
      reg_disp_back_data(25) => reg_disp_back_data(25),
      reg_disp_back_data(24) => reg_disp_back_data(24),
      reg_disp_back_data(23) => reg_disp_back_data(23),
      reg_disp_back_data(22) => reg_disp_back_data(22),
      reg_disp_back_data(21) => reg_disp_back_data(21),
      reg_disp_back_data(20) => reg_disp_back_data(20),
      reg_disp_back_data(19) => reg_disp_back_data(19),
      reg_disp_back_data(18) => reg_disp_back_data(18),
      reg_disp_back_data(17) => reg_disp_back_data(17),
      reg_disp_back_data(16) => reg_disp_back_data(16),
      reg_disp_back_data(15) => reg_disp_back_data(15),
      reg_disp_back_data(14) => reg_disp_back_data(14),
      reg_disp_back_data(13) => reg_disp_back_data(13),
      reg_disp_back_data(12) => reg_disp_back_data(12),
      reg_disp_back_data(11) => reg_disp_back_data(11),
      reg_disp_back_data(10) => reg_disp_back_data(10),
      reg_disp_back_data(9) => reg_disp_back_data(9),
      reg_disp_back_data(8) => reg_disp_back_data(8),
      reg_disp_back_data(7) => reg_disp_back_data(7),
      reg_disp_back_data(6) => reg_disp_back_data(6),
      reg_disp_back_data(5) => reg_disp_back_data(5),
      reg_disp_back_data(4) => reg_disp_back_data(4),
      reg_disp_back_data(3) => reg_disp_back_data(3),
      reg_disp_back_data(2) => reg_disp_back_data(2),
      reg_disp_back_data(1) => reg_disp_back_data(1),
      reg_disp_back_data(0) => reg_disp_back_data(0),
      pb_master_cmd(2) => pb_master_cmd(2),
      pb_master_cmd(1) => pb_master_cmd(1),
      pb_master_cmd(0) => pb_master_cmd(0),
      ext_fifo_disp_adr(31) => ext_fifo_disp_adr(31),
      ext_fifo_disp_adr(30) => ext_fifo_disp_adr(30),
      ext_fifo_disp_adr(29) => ext_fifo_disp_adr(29),
      ext_fifo_disp_adr(28) => ext_fifo_disp_adr(28),
      ext_fifo_disp_adr(27) => ext_fifo_disp_adr(27),
      ext_fifo_disp_adr(26) => ext_fifo_disp_adr(26),
      ext_fifo_disp_adr(25) => ext_fifo_disp_adr(25),
      ext_fifo_disp_adr(24) => ext_fifo_disp_adr(24),
      ext_fifo_disp_adr(23) => ext_fifo_disp_adr(23),
      ext_fifo_disp_adr(22) => ext_fifo_disp_adr(22),
      ext_fifo_disp_adr(21) => ext_fifo_disp_adr(21),
      ext_fifo_disp_adr(20) => ext_fifo_disp_adr(20),
      ext_fifo_disp_adr(19) => ext_fifo_disp_adr(19),
      ext_fifo_disp_adr(18) => ext_fifo_disp_adr(18),
      ext_fifo_disp_adr(17) => ext_fifo_disp_adr(17),
      ext_fifo_disp_adr(16) => ext_fifo_disp_adr(16),
      ext_fifo_disp_adr(15) => ext_fifo_disp_adr(15),
      ext_fifo_disp_adr(14) => ext_fifo_disp_adr(14),
      ext_fifo_disp_adr(13) => ext_fifo_disp_adr(13),
      ext_fifo_disp_adr(12) => ext_fifo_disp_adr(12),
      ext_fifo_disp_adr(11) => ext_fifo_disp_adr(11),
      ext_fifo_disp_adr(10) => ext_fifo_disp_adr(10),
      ext_fifo_disp_adr(9) => ext_fifo_disp_adr(9),
      ext_fifo_disp_adr(8) => ext_fifo_disp_adr(8),
      ext_fifo_disp_adr(7) => ext_fifo_disp_adr(7),
      ext_fifo_disp_adr(6) => ext_fifo_disp_adr(6),
      ext_fifo_disp_adr(5) => ext_fifo_disp_adr(5),
      ext_fifo_disp_adr(4) => ext_fifo_disp_adr(4),
      ext_fifo_disp_adr(3) => ext_fifo_disp_adr(3),
      ext_fifo_disp_adr(2) => ext_fifo_disp_adr(2),
      ext_fifo_disp_adr(1) => ext_fifo_disp_adr(1),
      ext_fifo_disp_adr(0) => ext_fifo_disp_adr(0),
      reg_disp_adr(31) => reg_disp_adr(31),
      reg_disp_adr(30) => reg_disp_adr(30),
      reg_disp_adr(29) => reg_disp_adr(29),
      reg_disp_adr(28) => reg_disp_adr(28),
      reg_disp_adr(27) => reg_disp_adr(27),
      reg_disp_adr(26) => reg_disp_adr(26),
      reg_disp_adr(25) => reg_disp_adr(25),
      reg_disp_adr(24) => reg_disp_adr(24),
      reg_disp_adr(23) => reg_disp_adr(23),
      reg_disp_adr(22) => reg_disp_adr(22),
      reg_disp_adr(21) => reg_disp_adr(21),
      reg_disp_adr(20) => reg_disp_adr(20),
      reg_disp_adr(19) => reg_disp_adr(19),
      reg_disp_adr(18) => reg_disp_adr(18),
      reg_disp_adr(17) => reg_disp_adr(17),
      reg_disp_adr(16) => reg_disp_adr(16),
      reg_disp_adr(15) => reg_disp_adr(15),
      reg_disp_adr(14) => reg_disp_adr(14),
      reg_disp_adr(13) => reg_disp_adr(13),
      reg_disp_adr(12) => reg_disp_adr(12),
      reg_disp_adr(11) => reg_disp_adr(11),
      reg_disp_adr(10) => reg_disp_adr(10),
      reg_disp_adr(9) => reg_disp_adr(9),
      reg_disp_adr(8) => reg_disp_adr(8),
      reg_disp_adr(7) => reg_disp_adr(7),
      reg_disp_adr(6) => reg_disp_adr(6),
      reg_disp_adr(5) => reg_disp_adr(5),
      reg_disp_adr(4) => reg_disp_adr(4),
      reg_disp_adr(3) => reg_disp_adr(3),
      reg_disp_adr(2) => reg_disp_adr(2),
      reg_disp_adr(1) => reg_disp_adr(1),
      reg_disp_adr(0) => reg_disp_adr(0),
      reg_disp_data(31) => reg_disp_data(31),
      reg_disp_data(30) => reg_disp_data(30),
      reg_disp_data(29) => reg_disp_data(29),
      reg_disp_data(28) => reg_disp_data(28),
      reg_disp_data(27) => reg_disp_data(27),
      reg_disp_data(26) => reg_disp_data(26),
      reg_disp_data(25) => reg_disp_data(25),
      reg_disp_data(24) => reg_disp_data(24),
      reg_disp_data(23) => reg_disp_data(23),
      reg_disp_data(22) => reg_disp_data(22),
      reg_disp_data(21) => reg_disp_data(21),
      reg_disp_data(20) => reg_disp_data(20),
      reg_disp_data(19) => reg_disp_data(19),
      reg_disp_data(18) => reg_disp_data(18),
      reg_disp_data(17) => reg_disp_data(17),
      reg_disp_data(16) => reg_disp_data(16),
      reg_disp_data(15) => reg_disp_data(15),
      reg_disp_data(14) => reg_disp_data(14),
      reg_disp_data(13) => reg_disp_data(13),
      reg_disp_data(12) => reg_disp_data(12),
      reg_disp_data(11) => reg_disp_data(11),
      reg_disp_data(10) => reg_disp_data(10),
      reg_disp_data(9) => reg_disp_data(9),
      reg_disp_data(8) => reg_disp_data(8),
      reg_disp_data(7) => reg_disp_data(7),
      reg_disp_data(6) => reg_disp_data(6),
      reg_disp_data(5) => reg_disp_data(5),
      reg_disp_data(4) => reg_disp_data(4),
      reg_disp_data(3) => reg_disp_data(3),
      reg_disp_data(2) => reg_disp_data(2),
      reg_disp_data(1) => reg_disp_data(1),
      reg_disp_data(0) => reg_disp_data(0),
      pb_slave_data(63) => pb_slave_data(63),
      pb_slave_data(62) => pb_slave_data(62),
      pb_slave_data(61) => pb_slave_data(61),
      pb_slave_data(60) => pb_slave_data(60),
      pb_slave_data(59) => pb_slave_data(59),
      pb_slave_data(58) => pb_slave_data(58),
      pb_slave_data(57) => pb_slave_data(57),
      pb_slave_data(56) => pb_slave_data(56),
      pb_slave_data(55) => pb_slave_data(55),
      pb_slave_data(54) => pb_slave_data(54),
      pb_slave_data(53) => pb_slave_data(53),
      pb_slave_data(52) => pb_slave_data(52),
      pb_slave_data(51) => pb_slave_data(51),
      pb_slave_data(50) => pb_slave_data(50),
      pb_slave_data(49) => pb_slave_data(49),
      pb_slave_data(48) => pb_slave_data(48),
      pb_slave_data(47) => pb_slave_data(47),
      pb_slave_data(46) => pb_slave_data(46),
      pb_slave_data(45) => pb_slave_data(45),
      pb_slave_data(44) => pb_slave_data(44),
      pb_slave_data(43) => pb_slave_data(43),
      pb_slave_data(42) => pb_slave_data(42),
      pb_slave_data(41) => pb_slave_data(41),
      pb_slave_data(40) => pb_slave_data(40),
      pb_slave_data(39) => pb_slave_data(39),
      pb_slave_data(38) => pb_slave_data(38),
      pb_slave_data(37) => pb_slave_data(37),
      pb_slave_data(36) => pb_slave_data(36),
      pb_slave_data(35) => pb_slave_data(35),
      pb_slave_data(34) => pb_slave_data(34),
      pb_slave_data(33) => pb_slave_data(33),
      pb_slave_data(32) => pb_slave_data(32),
      pb_slave_data(31) => pb_slave_data(31),
      pb_slave_data(30) => pb_slave_data(30),
      pb_slave_data(29) => pb_slave_data(29),
      pb_slave_data(28) => pb_slave_data(28),
      pb_slave_data(27) => pb_slave_data(27),
      pb_slave_data(26) => pb_slave_data(26),
      pb_slave_data(25) => pb_slave_data(25),
      pb_slave_data(24) => pb_slave_data(24),
      pb_slave_data(23) => pb_slave_data(23),
      pb_slave_data(22) => pb_slave_data(22),
      pb_slave_data(21) => pb_slave_data(21),
      pb_slave_data(20) => pb_slave_data(20),
      pb_slave_data(19) => pb_slave_data(19),
      pb_slave_data(18) => pb_slave_data(18),
      pb_slave_data(17) => pb_slave_data(17),
      pb_slave_data(16) => pb_slave_data(16),
      pb_slave_data(15) => pb_slave_data(15),
      pb_slave_data(14) => pb_slave_data(14),
      pb_slave_data(13) => pb_slave_data(13),
      pb_slave_data(12) => pb_slave_data(12),
      pb_slave_data(11) => pb_slave_data(11),
      pb_slave_data(10) => pb_slave_data(10),
      pb_slave_data(9) => pb_slave_data(9),
      pb_slave_data(8) => pb_slave_data(8),
      pb_slave_data(7) => pb_slave_data(7),
      pb_slave_data(6) => pb_slave_data(6),
      pb_slave_data(5) => pb_slave_data(5),
      pb_slave_data(4) => pb_slave_data(4),
      pb_slave_data(3) => pb_slave_data(3),
      pb_slave_data(2) => pb_slave_data(2),
      pb_slave_data(1) => pb_slave_data(1),
      pb_slave_data(0) => pb_slave_data(0),
      pb_slave_dmar(1) => pb_slave_dmar(1),
      pb_slave_dmar(0) => pb_slave_dmar(0),
      ext_fifo_disp_data(63) => ext_fifo_disp_data(63),
      ext_fifo_disp_data(62) => ext_fifo_disp_data(62),
      ext_fifo_disp_data(61) => ext_fifo_disp_data(61),
      ext_fifo_disp_data(60) => ext_fifo_disp_data(60),
      ext_fifo_disp_data(59) => ext_fifo_disp_data(59),
      ext_fifo_disp_data(58) => ext_fifo_disp_data(58),
      ext_fifo_disp_data(57) => ext_fifo_disp_data(57),
      ext_fifo_disp_data(56) => ext_fifo_disp_data(56),
      ext_fifo_disp_data(55) => ext_fifo_disp_data(55),
      ext_fifo_disp_data(54) => ext_fifo_disp_data(54),
      ext_fifo_disp_data(53) => ext_fifo_disp_data(53),
      ext_fifo_disp_data(52) => ext_fifo_disp_data(52),
      ext_fifo_disp_data(51) => ext_fifo_disp_data(51),
      ext_fifo_disp_data(50) => ext_fifo_disp_data(50),
      ext_fifo_disp_data(49) => ext_fifo_disp_data(49),
      ext_fifo_disp_data(48) => ext_fifo_disp_data(48),
      ext_fifo_disp_data(47) => ext_fifo_disp_data(47),
      ext_fifo_disp_data(46) => ext_fifo_disp_data(46),
      ext_fifo_disp_data(45) => ext_fifo_disp_data(45),
      ext_fifo_disp_data(44) => ext_fifo_disp_data(44),
      ext_fifo_disp_data(43) => ext_fifo_disp_data(43),
      ext_fifo_disp_data(42) => ext_fifo_disp_data(42),
      ext_fifo_disp_data(41) => ext_fifo_disp_data(41),
      ext_fifo_disp_data(40) => ext_fifo_disp_data(40),
      ext_fifo_disp_data(39) => ext_fifo_disp_data(39),
      ext_fifo_disp_data(38) => ext_fifo_disp_data(38),
      ext_fifo_disp_data(37) => ext_fifo_disp_data(37),
      ext_fifo_disp_data(36) => ext_fifo_disp_data(36),
      ext_fifo_disp_data(35) => ext_fifo_disp_data(35),
      ext_fifo_disp_data(34) => ext_fifo_disp_data(34),
      ext_fifo_disp_data(33) => ext_fifo_disp_data(33),
      ext_fifo_disp_data(32) => ext_fifo_disp_data(32),
      ext_fifo_disp_data(31) => ext_fifo_disp_data(31),
      ext_fifo_disp_data(30) => ext_fifo_disp_data(30),
      ext_fifo_disp_data(29) => ext_fifo_disp_data(29),
      ext_fifo_disp_data(28) => ext_fifo_disp_data(28),
      ext_fifo_disp_data(27) => ext_fifo_disp_data(27),
      ext_fifo_disp_data(26) => ext_fifo_disp_data(26),
      ext_fifo_disp_data(25) => ext_fifo_disp_data(25),
      ext_fifo_disp_data(24) => ext_fifo_disp_data(24),
      ext_fifo_disp_data(23) => ext_fifo_disp_data(23),
      ext_fifo_disp_data(22) => ext_fifo_disp_data(22),
      ext_fifo_disp_data(21) => ext_fifo_disp_data(21),
      ext_fifo_disp_data(20) => ext_fifo_disp_data(20),
      ext_fifo_disp_data(19) => ext_fifo_disp_data(19),
      ext_fifo_disp_data(18) => ext_fifo_disp_data(18),
      ext_fifo_disp_data(17) => ext_fifo_disp_data(17),
      ext_fifo_disp_data(16) => ext_fifo_disp_data(16),
      ext_fifo_disp_data(15) => ext_fifo_disp_data(15),
      ext_fifo_disp_data(14) => ext_fifo_disp_data(14),
      ext_fifo_disp_data(13) => ext_fifo_disp_data(13),
      ext_fifo_disp_data(12) => ext_fifo_disp_data(12),
      ext_fifo_disp_data(11) => ext_fifo_disp_data(11),
      ext_fifo_disp_data(10) => ext_fifo_disp_data(10),
      ext_fifo_disp_data(9) => ext_fifo_disp_data(9),
      ext_fifo_disp_data(8) => ext_fifo_disp_data(8),
      ext_fifo_disp_data(7) => ext_fifo_disp_data(7),
      ext_fifo_disp_data(6) => ext_fifo_disp_data(6),
      ext_fifo_disp_data(5) => ext_fifo_disp_data(5),
      ext_fifo_disp_data(4) => ext_fifo_disp_data(4),
      ext_fifo_disp_data(3) => ext_fifo_disp_data(3),
      ext_fifo_disp_data(2) => ext_fifo_disp_data(2),
      ext_fifo_disp_data(1) => ext_fifo_disp_data(1),
      ext_fifo_disp_data(0) => ext_fifo_disp_data(0)
    );
  int : core64_interrupt
    port map (
      irq => irq,
      clk => NlwRenamedSig_OI_clk_out,
      cfg_command10 => cfg_command_c(10),
      cfg_interrupt => cfg_interrupt_n_c,
      cfg_interrupt_assert => cfg_interrupt_assert_n_c,
      rstp => pb_rstp_32527,
      cfg_interrupt_rdy => cfg_interrupt_rdy_n_c
    );
  rx : core64_rx_engine
    port map (
      trn_rx_trn_rerrfwd_n => trn_rx_trn_rerrfwd_n,
      rx_tx_engine_complete_we => rx_tx_engine_complete_we,
      clk => NlwRenamedSig_OI_clk_out,
      tx_rx_engine_complete_reg => tx_rx_engine_complete_reg,
      trn_rx_trn_rsrc_dsc_n => trn_rx_trn_rsrc_dsc_n,
      rx_tx_engine_request_reg_wr => rx_tx_engine_request_reg_wr,
      trn_rx_trn_rsof_n => trn_rx_trn_rsof_n,
      rstp => rstp_32898,
      trn_rx_trn_rsrc_rdy_n => trn_rx_trn_rsrc_rdy_n,
      rx_ext_fifo_data_we => rx_ext_fifo_data_we,
      trn_rx_back_trn_rnp_ok_n => NLW_rx_trn_rx_back_trn_rnp_ok_n_UNCONNECTED,
      trn_rx_back_trn_rdst_rdy_n => trn_rx_back_trn_rdst_rdy_n,
      trn_rx_back_trn_rcpl_streaming_n => trn_rx_back_trn_rcpl_streaming_n,
      trn_rx_trn_reof_n => trn_rx_trn_reof_n,
      rx_tx_engine_request_reg_rd => rx_tx_engine_request_reg_rd,
      reg_access_req_rd(1) => reg_access_req_rd(1),
      reg_access_req_rd(0) => reg_access_req_rd(0),
      reg_access_adr(31) => reg_access_adr(31),
      reg_access_adr(30) => reg_access_adr(30),
      reg_access_adr(29) => reg_access_adr(29),
      reg_access_adr(28) => reg_access_adr(28),
      reg_access_adr(27) => reg_access_adr(27),
      reg_access_adr(26) => reg_access_adr(26),
      reg_access_adr(25) => reg_access_adr(25),
      reg_access_adr(24) => reg_access_adr(24),
      reg_access_adr(23) => reg_access_adr(23),
      reg_access_adr(22) => reg_access_adr(22),
      reg_access_adr(21) => reg_access_adr(21),
      reg_access_adr(20) => reg_access_adr(20),
      reg_access_adr(19) => reg_access_adr(19),
      reg_access_adr(18) => reg_access_adr(18),
      reg_access_adr(17) => reg_access_adr(17),
      reg_access_adr(16) => reg_access_adr(16),
      reg_access_adr(15) => reg_access_adr(15),
      reg_access_adr(14) => reg_access_adr(14),
      reg_access_adr(13) => reg_access_adr(13),
      reg_access_adr(12) => reg_access_adr(12),
      reg_access_adr(11) => reg_access_adr(11),
      reg_access_adr(10) => reg_access_adr(10),
      reg_access_adr(9) => reg_access_adr(9),
      reg_access_adr(8) => reg_access_adr(8),
      reg_access_adr(7) => reg_access_adr(7),
      reg_access_adr(6) => reg_access_adr(6),
      reg_access_adr(5) => reg_access_adr(5),
      reg_access_adr(4) => reg_access_adr(4),
      reg_access_adr(3) => reg_access_adr(3),
      reg_access_adr(2) => reg_access_adr(2),
      reg_access_adr(1) => reg_access_adr(1),
      reg_access_adr(0) => reg_access_adr(0),
      reg_access_req_wr(1) => reg_access_req_wr(1),
      reg_access_req_wr(0) => reg_access_req_wr(0),
      rx_tx_engine_request_attr(3) => rx_tx_engine_request_attr(3),
      rx_tx_engine_request_attr(2) => rx_tx_engine_request_attr(2),
      rx_tx_engine_request_attr(1) => rx_tx_engine_request_attr(1),
      rx_tx_engine_request_attr(0) => rx_tx_engine_request_attr(0),
      rx_tx_engine_request_id(15) => rx_tx_engine_request_id(15),
      rx_tx_engine_request_id(14) => rx_tx_engine_request_id(14),
      rx_tx_engine_request_id(13) => rx_tx_engine_request_id(13),
      rx_tx_engine_request_id(12) => rx_tx_engine_request_id(12),
      rx_tx_engine_request_id(11) => rx_tx_engine_request_id(11),
      rx_tx_engine_request_id(10) => rx_tx_engine_request_id(10),
      rx_tx_engine_request_id(9) => rx_tx_engine_request_id(9),
      rx_tx_engine_request_id(8) => rx_tx_engine_request_id(8),
      rx_tx_engine_request_id(7) => rx_tx_engine_request_id(7),
      rx_tx_engine_request_id(6) => rx_tx_engine_request_id(6),
      rx_tx_engine_request_id(5) => rx_tx_engine_request_id(5),
      rx_tx_engine_request_id(4) => rx_tx_engine_request_id(4),
      rx_tx_engine_request_id(3) => rx_tx_engine_request_id(3),
      rx_tx_engine_request_id(2) => rx_tx_engine_request_id(2),
      rx_tx_engine_request_id(1) => rx_tx_engine_request_id(1),
      rx_tx_engine_request_id(0) => rx_tx_engine_request_id(0),
      rx_ext_fifo_data(63) => rx_ext_fifo_data(63),
      rx_ext_fifo_data(62) => rx_ext_fifo_data(62),
      rx_ext_fifo_data(61) => rx_ext_fifo_data(61),
      rx_ext_fifo_data(60) => rx_ext_fifo_data(60),
      rx_ext_fifo_data(59) => rx_ext_fifo_data(59),
      rx_ext_fifo_data(58) => rx_ext_fifo_data(58),
      rx_ext_fifo_data(57) => rx_ext_fifo_data(57),
      rx_ext_fifo_data(56) => rx_ext_fifo_data(56),
      rx_ext_fifo_data(55) => rx_ext_fifo_data(55),
      rx_ext_fifo_data(54) => rx_ext_fifo_data(54),
      rx_ext_fifo_data(53) => rx_ext_fifo_data(53),
      rx_ext_fifo_data(52) => rx_ext_fifo_data(52),
      rx_ext_fifo_data(51) => rx_ext_fifo_data(51),
      rx_ext_fifo_data(50) => rx_ext_fifo_data(50),
      rx_ext_fifo_data(49) => rx_ext_fifo_data(49),
      rx_ext_fifo_data(48) => rx_ext_fifo_data(48),
      rx_ext_fifo_data(47) => rx_ext_fifo_data(47),
      rx_ext_fifo_data(46) => rx_ext_fifo_data(46),
      rx_ext_fifo_data(45) => rx_ext_fifo_data(45),
      rx_ext_fifo_data(44) => rx_ext_fifo_data(44),
      rx_ext_fifo_data(43) => rx_ext_fifo_data(43),
      rx_ext_fifo_data(42) => rx_ext_fifo_data(42),
      rx_ext_fifo_data(41) => rx_ext_fifo_data(41),
      rx_ext_fifo_data(40) => rx_ext_fifo_data(40),
      rx_ext_fifo_data(39) => rx_ext_fifo_data(39),
      rx_ext_fifo_data(38) => rx_ext_fifo_data(38),
      rx_ext_fifo_data(37) => rx_ext_fifo_data(37),
      rx_ext_fifo_data(36) => rx_ext_fifo_data(36),
      rx_ext_fifo_data(35) => rx_ext_fifo_data(35),
      rx_ext_fifo_data(34) => rx_ext_fifo_data(34),
      rx_ext_fifo_data(33) => rx_ext_fifo_data(33),
      rx_ext_fifo_data(32) => rx_ext_fifo_data(32),
      rx_ext_fifo_data(31) => rx_ext_fifo_data(31),
      rx_ext_fifo_data(30) => rx_ext_fifo_data(30),
      rx_ext_fifo_data(29) => rx_ext_fifo_data(29),
      rx_ext_fifo_data(28) => rx_ext_fifo_data(28),
      rx_ext_fifo_data(27) => rx_ext_fifo_data(27),
      rx_ext_fifo_data(26) => rx_ext_fifo_data(26),
      rx_ext_fifo_data(25) => rx_ext_fifo_data(25),
      rx_ext_fifo_data(24) => rx_ext_fifo_data(24),
      rx_ext_fifo_data(23) => rx_ext_fifo_data(23),
      rx_ext_fifo_data(22) => rx_ext_fifo_data(22),
      rx_ext_fifo_data(21) => rx_ext_fifo_data(21),
      rx_ext_fifo_data(20) => rx_ext_fifo_data(20),
      rx_ext_fifo_data(19) => rx_ext_fifo_data(19),
      rx_ext_fifo_data(18) => rx_ext_fifo_data(18),
      rx_ext_fifo_data(17) => rx_ext_fifo_data(17),
      rx_ext_fifo_data(16) => rx_ext_fifo_data(16),
      rx_ext_fifo_data(15) => rx_ext_fifo_data(15),
      rx_ext_fifo_data(14) => rx_ext_fifo_data(14),
      rx_ext_fifo_data(13) => rx_ext_fifo_data(13),
      rx_ext_fifo_data(12) => rx_ext_fifo_data(12),
      rx_ext_fifo_data(11) => rx_ext_fifo_data(11),
      rx_ext_fifo_data(10) => rx_ext_fifo_data(10),
      rx_ext_fifo_data(9) => rx_ext_fifo_data(9),
      rx_ext_fifo_data(8) => rx_ext_fifo_data(8),
      rx_ext_fifo_data(7) => rx_ext_fifo_data(7),
      rx_ext_fifo_data(6) => rx_ext_fifo_data(6),
      rx_ext_fifo_data(5) => rx_ext_fifo_data(5),
      rx_ext_fifo_data(4) => rx_ext_fifo_data(4),
      rx_ext_fifo_data(3) => rx_ext_fifo_data(3),
      rx_ext_fifo_data(2) => rx_ext_fifo_data(2),
      rx_ext_fifo_data(1) => rx_ext_fifo_data(1),
      rx_ext_fifo_data(0) => rx_ext_fifo_data(0),
      rx_tx_engine_request_tc(2) => rx_tx_engine_request_tc(2),
      rx_tx_engine_request_tc(1) => rx_tx_engine_request_tc(1),
      rx_tx_engine_request_tc(0) => rx_tx_engine_request_tc(0),
      reg_access_data(31) => reg_access_data(31),
      reg_access_data(30) => reg_access_data(30),
      reg_access_data(29) => reg_access_data(29),
      reg_access_data(28) => reg_access_data(28),
      reg_access_data(27) => reg_access_data(27),
      reg_access_data(26) => reg_access_data(26),
      reg_access_data(25) => reg_access_data(25),
      reg_access_data(24) => reg_access_data(24),
      reg_access_data(23) => reg_access_data(23),
      reg_access_data(22) => reg_access_data(22),
      reg_access_data(21) => reg_access_data(21),
      reg_access_data(20) => reg_access_data(20),
      reg_access_data(19) => reg_access_data(19),
      reg_access_data(18) => reg_access_data(18),
      reg_access_data(17) => reg_access_data(17),
      reg_access_data(16) => reg_access_data(16),
      reg_access_data(15) => reg_access_data(15),
      reg_access_data(14) => reg_access_data(14),
      reg_access_data(13) => reg_access_data(13),
      reg_access_data(12) => reg_access_data(12),
      reg_access_data(11) => reg_access_data(11),
      reg_access_data(10) => reg_access_data(10),
      reg_access_data(9) => reg_access_data(9),
      reg_access_data(8) => reg_access_data(8),
      reg_access_data(7) => reg_access_data(7),
      reg_access_data(6) => reg_access_data(6),
      reg_access_data(5) => reg_access_data(5),
      reg_access_data(4) => reg_access_data(4),
      reg_access_data(3) => reg_access_data(3),
      reg_access_data(2) => reg_access_data(2),
      reg_access_data(1) => reg_access_data(1),
      reg_access_data(0) => reg_access_data(0),
      rx_ext_fifo_adr(8) => rx_ext_fifo_adr(8),
      rx_ext_fifo_adr(7) => rx_ext_fifo_adr(7),
      rx_ext_fifo_adr(6) => rx_ext_fifo_adr(6),
      rx_ext_fifo_adr(5) => rx_ext_fifo_adr(5),
      rx_ext_fifo_adr(4) => rx_ext_fifo_adr(4),
      rx_ext_fifo_adr(3) => rx_ext_fifo_adr(3),
      rx_ext_fifo_adr(2) => rx_ext_fifo_adr(2),
      rx_ext_fifo_adr(1) => rx_ext_fifo_adr(1),
      rx_ext_fifo_adr(0) => rx_ext_fifo_adr(0),
      rx_tx_engine_request_tag(7) => rx_tx_engine_request_tag(7),
      rx_tx_engine_request_tag(6) => rx_tx_engine_request_tag(6),
      rx_tx_engine_request_tag(5) => rx_tx_engine_request_tag(5),
      rx_tx_engine_request_tag(4) => rx_tx_engine_request_tag(4),
      rx_tx_engine_request_tag(3) => rx_tx_engine_request_tag(3),
      rx_tx_engine_request_tag(2) => rx_tx_engine_request_tag(2),
      rx_tx_engine_request_tag(1) => rx_tx_engine_request_tag(1),
      rx_tx_engine_request_tag(0) => rx_tx_engine_request_tag(0),
      rx_tx_engine_lower_adr(6) => rx_tx_engine_lower_adr(6),
      rx_tx_engine_lower_adr(5) => rx_tx_engine_lower_adr(5),
      rx_tx_engine_lower_adr(4) => rx_tx_engine_lower_adr(4),
      rx_tx_engine_lower_adr(3) => rx_tx_engine_lower_adr(3),
      rx_tx_engine_lower_adr(2) => rx_tx_engine_lower_adr(2),
      trn_rx_trn_rd(63) => trn_rx_trn_rd(63),
      trn_rx_trn_rd(62) => trn_rx_trn_rd(62),
      trn_rx_trn_rd(61) => trn_rx_trn_rd(61),
      trn_rx_trn_rd(60) => trn_rx_trn_rd(60),
      trn_rx_trn_rd(59) => trn_rx_trn_rd(59),
      trn_rx_trn_rd(58) => trn_rx_trn_rd(58),
      trn_rx_trn_rd(57) => trn_rx_trn_rd(57),
      trn_rx_trn_rd(56) => trn_rx_trn_rd(56),
      trn_rx_trn_rd(55) => trn_rx_trn_rd(55),
      trn_rx_trn_rd(54) => trn_rx_trn_rd(54),
      trn_rx_trn_rd(53) => trn_rx_trn_rd(53),
      trn_rx_trn_rd(52) => trn_rx_trn_rd(52),
      trn_rx_trn_rd(51) => trn_rx_trn_rd(51),
      trn_rx_trn_rd(50) => trn_rx_trn_rd(50),
      trn_rx_trn_rd(49) => trn_rx_trn_rd(49),
      trn_rx_trn_rd(48) => trn_rx_trn_rd(48),
      trn_rx_trn_rd(47) => trn_rx_trn_rd(47),
      trn_rx_trn_rd(46) => trn_rx_trn_rd(46),
      trn_rx_trn_rd(45) => trn_rx_trn_rd(45),
      trn_rx_trn_rd(44) => trn_rx_trn_rd(44),
      trn_rx_trn_rd(43) => trn_rx_trn_rd(43),
      trn_rx_trn_rd(42) => trn_rx_trn_rd(42),
      trn_rx_trn_rd(41) => trn_rx_trn_rd(41),
      trn_rx_trn_rd(40) => trn_rx_trn_rd(40),
      trn_rx_trn_rd(39) => trn_rx_trn_rd(39),
      trn_rx_trn_rd(38) => trn_rx_trn_rd(38),
      trn_rx_trn_rd(37) => trn_rx_trn_rd(37),
      trn_rx_trn_rd(36) => trn_rx_trn_rd(36),
      trn_rx_trn_rd(35) => trn_rx_trn_rd(35),
      trn_rx_trn_rd(34) => trn_rx_trn_rd(34),
      trn_rx_trn_rd(33) => trn_rx_trn_rd(33),
      trn_rx_trn_rd(32) => trn_rx_trn_rd(32),
      trn_rx_trn_rd(31) => trn_rx_trn_rd(31),
      trn_rx_trn_rd(30) => trn_rx_trn_rd(30),
      trn_rx_trn_rd(29) => trn_rx_trn_rd(29),
      trn_rx_trn_rd(28) => trn_rx_trn_rd(28),
      trn_rx_trn_rd(27) => trn_rx_trn_rd(27),
      trn_rx_trn_rd(26) => trn_rx_trn_rd(26),
      trn_rx_trn_rd(25) => trn_rx_trn_rd(25),
      trn_rx_trn_rd(24) => trn_rx_trn_rd(24),
      trn_rx_trn_rd(23) => trn_rx_trn_rd(23),
      trn_rx_trn_rd(22) => trn_rx_trn_rd(22),
      trn_rx_trn_rd(21) => trn_rx_trn_rd(21),
      trn_rx_trn_rd(20) => trn_rx_trn_rd(20),
      trn_rx_trn_rd(19) => trn_rx_trn_rd(19),
      trn_rx_trn_rd(18) => trn_rx_trn_rd(18),
      trn_rx_trn_rd(17) => trn_rx_trn_rd(17),
      trn_rx_trn_rd(16) => trn_rx_trn_rd(16),
      trn_rx_trn_rd(15) => trn_rx_trn_rd(15),
      trn_rx_trn_rd(14) => trn_rx_trn_rd(14),
      trn_rx_trn_rd(13) => trn_rx_trn_rd(13),
      trn_rx_trn_rd(12) => trn_rx_trn_rd(12),
      trn_rx_trn_rd(11) => trn_rx_trn_rd(11),
      trn_rx_trn_rd(10) => trn_rx_trn_rd(10),
      trn_rx_trn_rd(9) => trn_rx_trn_rd(9),
      trn_rx_trn_rd(8) => trn_rx_trn_rd(8),
      trn_rx_trn_rd(7) => trn_rx_trn_rd(7),
      trn_rx_trn_rd(6) => trn_rx_trn_rd(6),
      trn_rx_trn_rd(5) => trn_rx_trn_rd(5),
      trn_rx_trn_rd(4) => trn_rx_trn_rd(4),
      trn_rx_trn_rd(3) => trn_rx_trn_rd(3),
      trn_rx_trn_rd(2) => trn_rx_trn_rd(2),
      trn_rx_trn_rd(1) => trn_rx_trn_rd(1),
      trn_rx_trn_rd(0) => trn_rx_trn_rd(0),
      trn_rx_trn_rbar_hit_n(6) => trn_rx_trn_rbar_hit_n(6),
      trn_rx_trn_rbar_hit_n(5) => trn_rx_trn_rbar_hit_n(5),
      trn_rx_trn_rbar_hit_n(4) => trn_rx_trn_rbar_hit_n(4),
      trn_rx_trn_rbar_hit_n(3) => trn_rx_trn_rbar_hit_n(3),
      trn_rx_trn_rbar_hit_n(2) => trn_rx_trn_rbar_hit_n(2),
      trn_rx_trn_rbar_hit_n(1) => trn_rx_trn_rbar_hit_n(1),
      trn_rx_trn_rbar_hit_n(0) => trn_rx_trn_rbar_hit_n(0),
      trn_rx_trn_rfc_npd_av(11) => trn_rx_trn_rfc_npd_av(11),
      trn_rx_trn_rfc_npd_av(10) => trn_rx_trn_rfc_npd_av(10),
      trn_rx_trn_rfc_npd_av(9) => trn_rx_trn_rfc_npd_av(9),
      trn_rx_trn_rfc_npd_av(8) => trn_rx_trn_rfc_npd_av(8),
      trn_rx_trn_rfc_npd_av(7) => trn_rx_trn_rfc_npd_av(7),
      trn_rx_trn_rfc_npd_av(6) => trn_rx_trn_rfc_npd_av(6),
      trn_rx_trn_rfc_npd_av(5) => trn_rx_trn_rfc_npd_av(5),
      trn_rx_trn_rfc_npd_av(4) => trn_rx_trn_rfc_npd_av(4),
      trn_rx_trn_rfc_npd_av(3) => trn_rx_trn_rfc_npd_av(3),
      trn_rx_trn_rfc_npd_av(2) => trn_rx_trn_rfc_npd_av(2),
      trn_rx_trn_rfc_npd_av(1) => trn_rx_trn_rfc_npd_av(1),
      trn_rx_trn_rfc_npd_av(0) => trn_rx_trn_rfc_npd_av(0),
      trn_rx_trn_rfc_ph_av(7) => trn_rx_trn_rfc_ph_av(7),
      trn_rx_trn_rfc_ph_av(6) => trn_rx_trn_rfc_ph_av(6),
      trn_rx_trn_rfc_ph_av(5) => trn_rx_trn_rfc_ph_av(5),
      trn_rx_trn_rfc_ph_av(4) => trn_rx_trn_rfc_ph_av(4),
      trn_rx_trn_rfc_ph_av(3) => trn_rx_trn_rfc_ph_av(3),
      trn_rx_trn_rfc_ph_av(2) => trn_rx_trn_rfc_ph_av(2),
      trn_rx_trn_rfc_ph_av(1) => trn_rx_trn_rfc_ph_av(1),
      trn_rx_trn_rfc_ph_av(0) => trn_rx_trn_rfc_ph_av(0),
      trn_rx_trn_rrem_n(7) => trn_rx_trn_rrem_n(7),
      trn_rx_trn_rrem_n(6) => trn_rx_trn_rrem_n(6),
      trn_rx_trn_rrem_n(5) => trn_rx_trn_rrem_n(5),
      trn_rx_trn_rrem_n(4) => trn_rx_trn_rrem_n(4),
      trn_rx_trn_rrem_n(3) => trn_rx_trn_rrem_n(3),
      trn_rx_trn_rrem_n(2) => trn_rx_trn_rrem_n(2),
      trn_rx_trn_rrem_n(1) => trn_rx_trn_rrem_n(1),
      trn_rx_trn_rrem_n(0) => trn_rx_trn_rrem_n(0),
      trn_rx_trn_rfc_pd_av(11) => trn_rx_trn_rfc_pd_av(11),
      trn_rx_trn_rfc_pd_av(10) => trn_rx_trn_rfc_pd_av(10),
      trn_rx_trn_rfc_pd_av(9) => trn_rx_trn_rfc_pd_av(9),
      trn_rx_trn_rfc_pd_av(8) => trn_rx_trn_rfc_pd_av(8),
      trn_rx_trn_rfc_pd_av(7) => trn_rx_trn_rfc_pd_av(7),
      trn_rx_trn_rfc_pd_av(6) => trn_rx_trn_rfc_pd_av(6),
      trn_rx_trn_rfc_pd_av(5) => trn_rx_trn_rfc_pd_av(5),
      trn_rx_trn_rfc_pd_av(4) => trn_rx_trn_rfc_pd_av(4),
      trn_rx_trn_rfc_pd_av(3) => trn_rx_trn_rfc_pd_av(3),
      trn_rx_trn_rfc_pd_av(2) => trn_rx_trn_rfc_pd_av(2),
      trn_rx_trn_rfc_pd_av(1) => trn_rx_trn_rfc_pd_av(1),
      trn_rx_trn_rfc_pd_av(0) => trn_rx_trn_rfc_pd_av(0),
      trn_rx_trn_rfc_nph_av(7) => trn_rx_trn_rfc_nph_av(7),
      trn_rx_trn_rfc_nph_av(6) => trn_rx_trn_rfc_nph_av(6),
      trn_rx_trn_rfc_nph_av(5) => trn_rx_trn_rfc_nph_av(5),
      trn_rx_trn_rfc_nph_av(4) => trn_rx_trn_rfc_nph_av(4),
      trn_rx_trn_rfc_nph_av(3) => trn_rx_trn_rfc_nph_av(3),
      trn_rx_trn_rfc_nph_av(2) => trn_rx_trn_rfc_nph_av(2),
      trn_rx_trn_rfc_nph_av(1) => trn_rx_trn_rfc_nph_av(1),
      trn_rx_trn_rfc_nph_av(0) => trn_rx_trn_rfc_nph_av(0)
    );
  tx : core64_tx_engine
    port map (
      reg_access_back_data_we => reg_access_back_data_we,
      rx_tx_engine_complete_we => rx_tx_engine_complete_we,
      clk => NlwRenamedSig_OI_clk_out,
      tx_rx_engine_complete_reg => tx_rx_engine_complete_reg,
      tx_ext_fifo_back_rd_size => tx_ext_fifo_back_rd_size,
      rx_tx_engine_request_reg_wr => rx_tx_engine_request_reg_wr,
      trn_tx_trn_tsof_n => trn_tx_trn_tsof_n,
      tx_ext_fifo_complete_error => tx_ext_fifo_complete_error,
      trn_tx_trn_terrfwd_n => trn_tx_trn_terrfwd_n,
      rstp => rstp_32898,
      tx_ext_fifo_back_req_rd => tx_ext_fifo_back_req_rd,
      trn_tx_trn_tsrc_dsc_n => trn_tx_trn_tsrc_dsc_n,
      trn_tx_back_trn_tdst_dsc_n => trn_tx_back_trn_tdst_dsc_n,
      tx_ext_fifo_back_req_wr => tx_ext_fifo_back_req_wr,
      tx_ext_fifo_complete_ok => tx_ext_fifo_complete_ok,
      reg_access_back_complete => reg_access_back_complete,
      trn_tx_trn_teof_n => trn_tx_trn_teof_n,
      rx_tx_engine_request_reg_rd => rx_tx_engine_request_reg_rd,
      trn_tx_trn_tsrc_rdy_n => trn_tx_trn_tsrc_rdy_n,
      trn_tx_back_trn_tdst_rdy_n => trn_tx_back_trn_tdst_rdy_n,
      trn_tx_trn_td(63) => trn_tx_trn_td(63),
      trn_tx_trn_td(62) => trn_tx_trn_td(62),
      trn_tx_trn_td(61) => trn_tx_trn_td(61),
      trn_tx_trn_td(60) => trn_tx_trn_td(60),
      trn_tx_trn_td(59) => trn_tx_trn_td(59),
      trn_tx_trn_td(58) => trn_tx_trn_td(58),
      trn_tx_trn_td(57) => trn_tx_trn_td(57),
      trn_tx_trn_td(56) => trn_tx_trn_td(56),
      trn_tx_trn_td(55) => trn_tx_trn_td(55),
      trn_tx_trn_td(54) => trn_tx_trn_td(54),
      trn_tx_trn_td(53) => trn_tx_trn_td(53),
      trn_tx_trn_td(52) => trn_tx_trn_td(52),
      trn_tx_trn_td(51) => trn_tx_trn_td(51),
      trn_tx_trn_td(50) => trn_tx_trn_td(50),
      trn_tx_trn_td(49) => trn_tx_trn_td(49),
      trn_tx_trn_td(48) => trn_tx_trn_td(48),
      trn_tx_trn_td(47) => trn_tx_trn_td(47),
      trn_tx_trn_td(46) => trn_tx_trn_td(46),
      trn_tx_trn_td(45) => trn_tx_trn_td(45),
      trn_tx_trn_td(44) => trn_tx_trn_td(44),
      trn_tx_trn_td(43) => trn_tx_trn_td(43),
      trn_tx_trn_td(42) => trn_tx_trn_td(42),
      trn_tx_trn_td(41) => trn_tx_trn_td(41),
      trn_tx_trn_td(40) => trn_tx_trn_td(40),
      trn_tx_trn_td(39) => trn_tx_trn_td(39),
      trn_tx_trn_td(38) => trn_tx_trn_td(38),
      trn_tx_trn_td(37) => trn_tx_trn_td(37),
      trn_tx_trn_td(36) => trn_tx_trn_td(36),
      trn_tx_trn_td(35) => trn_tx_trn_td(35),
      trn_tx_trn_td(34) => trn_tx_trn_td(34),
      trn_tx_trn_td(33) => trn_tx_trn_td(33),
      trn_tx_trn_td(32) => trn_tx_trn_td(32),
      trn_tx_trn_td(31) => trn_tx_trn_td(31),
      trn_tx_trn_td(30) => trn_tx_trn_td(30),
      trn_tx_trn_td(29) => trn_tx_trn_td(29),
      trn_tx_trn_td(28) => trn_tx_trn_td(28),
      trn_tx_trn_td(27) => trn_tx_trn_td(27),
      trn_tx_trn_td(26) => trn_tx_trn_td(26),
      trn_tx_trn_td(25) => trn_tx_trn_td(25),
      trn_tx_trn_td(24) => trn_tx_trn_td(24),
      trn_tx_trn_td(23) => trn_tx_trn_td(23),
      trn_tx_trn_td(22) => trn_tx_trn_td(22),
      trn_tx_trn_td(21) => trn_tx_trn_td(21),
      trn_tx_trn_td(20) => trn_tx_trn_td(20),
      trn_tx_trn_td(19) => trn_tx_trn_td(19),
      trn_tx_trn_td(18) => trn_tx_trn_td(18),
      trn_tx_trn_td(17) => trn_tx_trn_td(17),
      trn_tx_trn_td(16) => trn_tx_trn_td(16),
      trn_tx_trn_td(15) => trn_tx_trn_td(15),
      trn_tx_trn_td(14) => trn_tx_trn_td(14),
      trn_tx_trn_td(13) => trn_tx_trn_td(13),
      trn_tx_trn_td(12) => trn_tx_trn_td(12),
      trn_tx_trn_td(11) => trn_tx_trn_td(11),
      trn_tx_trn_td(10) => trn_tx_trn_td(10),
      trn_tx_trn_td(9) => trn_tx_trn_td(9),
      trn_tx_trn_td(8) => trn_tx_trn_td(8),
      trn_tx_trn_td(7) => trn_tx_trn_td(7),
      trn_tx_trn_td(6) => trn_tx_trn_td(6),
      trn_tx_trn_td(5) => trn_tx_trn_td(5),
      trn_tx_trn_td(4) => trn_tx_trn_td(4),
      trn_tx_trn_td(3) => trn_tx_trn_td(3),
      trn_tx_trn_td(2) => trn_tx_trn_td(2),
      trn_tx_trn_td(1) => trn_tx_trn_td(1),
      trn_tx_trn_td(0) => trn_tx_trn_td(0),
      trn_tx_trn_trem_n(7) => trn_tx_trn_trem_n(7),
      trn_tx_trn_trem_n(6) => trn_tx_trn_trem_n(6),
      trn_tx_trn_trem_n(5) => trn_tx_trn_trem_n(5),
      trn_tx_trn_trem_n(4) => trn_tx_trn_trem_n(4),
      trn_tx_trn_trem_n(3) => trn_tx_trn_trem_n(3),
      trn_tx_trn_trem_n(2) => trn_tx_trn_trem_n(2),
      trn_tx_trn_trem_n(1) => trn_tx_trn_trem_n(1),
      trn_tx_trn_trem_n(0) => trn_tx_trn_trem_n(0),
      tx_ext_fifo_adr(8) => tx_ext_fifo_adr(8),
      tx_ext_fifo_adr(7) => tx_ext_fifo_adr(7),
      tx_ext_fifo_adr(6) => tx_ext_fifo_adr(6),
      tx_ext_fifo_adr(5) => tx_ext_fifo_adr(5),
      tx_ext_fifo_adr(4) => tx_ext_fifo_adr(4),
      tx_ext_fifo_adr(3) => tx_ext_fifo_adr(3),
      tx_ext_fifo_adr(2) => tx_ext_fifo_adr(2),
      tx_ext_fifo_adr(1) => tx_ext_fifo_adr(1),
      tx_ext_fifo_adr(0) => tx_ext_fifo_adr(0),
      tx_ext_fifo_back_pci_adr(39) => tx_ext_fifo_back_pci_adr(39),
      tx_ext_fifo_back_pci_adr(38) => tx_ext_fifo_back_pci_adr(38),
      tx_ext_fifo_back_pci_adr(37) => tx_ext_fifo_back_pci_adr(37),
      tx_ext_fifo_back_pci_adr(36) => tx_ext_fifo_back_pci_adr(36),
      tx_ext_fifo_back_pci_adr(35) => tx_ext_fifo_back_pci_adr(35),
      tx_ext_fifo_back_pci_adr(34) => tx_ext_fifo_back_pci_adr(34),
      tx_ext_fifo_back_pci_adr(33) => tx_ext_fifo_back_pci_adr(33),
      tx_ext_fifo_back_pci_adr(32) => tx_ext_fifo_back_pci_adr(32),
      tx_ext_fifo_back_pci_adr(31) => tx_ext_fifo_back_pci_adr(31),
      tx_ext_fifo_back_pci_adr(30) => tx_ext_fifo_back_pci_adr(30),
      tx_ext_fifo_back_pci_adr(29) => tx_ext_fifo_back_pci_adr(29),
      tx_ext_fifo_back_pci_adr(28) => tx_ext_fifo_back_pci_adr(28),
      tx_ext_fifo_back_pci_adr(27) => tx_ext_fifo_back_pci_adr(27),
      tx_ext_fifo_back_pci_adr(26) => tx_ext_fifo_back_pci_adr(26),
      tx_ext_fifo_back_pci_adr(25) => tx_ext_fifo_back_pci_adr(25),
      tx_ext_fifo_back_pci_adr(24) => tx_ext_fifo_back_pci_adr(24),
      tx_ext_fifo_back_pci_adr(23) => tx_ext_fifo_back_pci_adr(23),
      tx_ext_fifo_back_pci_adr(22) => tx_ext_fifo_back_pci_adr(22),
      tx_ext_fifo_back_pci_adr(21) => tx_ext_fifo_back_pci_adr(21),
      tx_ext_fifo_back_pci_adr(20) => tx_ext_fifo_back_pci_adr(20),
      tx_ext_fifo_back_pci_adr(19) => tx_ext_fifo_back_pci_adr(19),
      tx_ext_fifo_back_pci_adr(18) => tx_ext_fifo_back_pci_adr(18),
      tx_ext_fifo_back_pci_adr(17) => tx_ext_fifo_back_pci_adr(17),
      tx_ext_fifo_back_pci_adr(16) => tx_ext_fifo_back_pci_adr(16),
      tx_ext_fifo_back_pci_adr(15) => tx_ext_fifo_back_pci_adr(15),
      tx_ext_fifo_back_pci_adr(14) => tx_ext_fifo_back_pci_adr(14),
      tx_ext_fifo_back_pci_adr(13) => tx_ext_fifo_back_pci_adr(13),
      tx_ext_fifo_back_pci_adr(12) => tx_ext_fifo_back_pci_adr(12),
      tx_ext_fifo_back_pci_adr(11) => tx_ext_fifo_back_pci_adr(11),
      tx_ext_fifo_back_pci_adr(10) => tx_ext_fifo_back_pci_adr(10),
      tx_ext_fifo_back_pci_adr(9) => tx_ext_fifo_back_pci_adr(9),
      tx_ext_fifo_back_pci_adr(8) => tx_ext_fifo_back_pci_adr(8),
      tx_ext_fifo_back_data(63) => tx_ext_fifo_back_data(63),
      tx_ext_fifo_back_data(62) => tx_ext_fifo_back_data(62),
      tx_ext_fifo_back_data(61) => tx_ext_fifo_back_data(61),
      tx_ext_fifo_back_data(60) => tx_ext_fifo_back_data(60),
      tx_ext_fifo_back_data(59) => tx_ext_fifo_back_data(59),
      tx_ext_fifo_back_data(58) => tx_ext_fifo_back_data(58),
      tx_ext_fifo_back_data(57) => tx_ext_fifo_back_data(57),
      tx_ext_fifo_back_data(56) => tx_ext_fifo_back_data(56),
      tx_ext_fifo_back_data(55) => tx_ext_fifo_back_data(55),
      tx_ext_fifo_back_data(54) => tx_ext_fifo_back_data(54),
      tx_ext_fifo_back_data(53) => tx_ext_fifo_back_data(53),
      tx_ext_fifo_back_data(52) => tx_ext_fifo_back_data(52),
      tx_ext_fifo_back_data(51) => tx_ext_fifo_back_data(51),
      tx_ext_fifo_back_data(50) => tx_ext_fifo_back_data(50),
      tx_ext_fifo_back_data(49) => tx_ext_fifo_back_data(49),
      tx_ext_fifo_back_data(48) => tx_ext_fifo_back_data(48),
      tx_ext_fifo_back_data(47) => tx_ext_fifo_back_data(47),
      tx_ext_fifo_back_data(46) => tx_ext_fifo_back_data(46),
      tx_ext_fifo_back_data(45) => tx_ext_fifo_back_data(45),
      tx_ext_fifo_back_data(44) => tx_ext_fifo_back_data(44),
      tx_ext_fifo_back_data(43) => tx_ext_fifo_back_data(43),
      tx_ext_fifo_back_data(42) => tx_ext_fifo_back_data(42),
      tx_ext_fifo_back_data(41) => tx_ext_fifo_back_data(41),
      tx_ext_fifo_back_data(40) => tx_ext_fifo_back_data(40),
      tx_ext_fifo_back_data(39) => tx_ext_fifo_back_data(39),
      tx_ext_fifo_back_data(38) => tx_ext_fifo_back_data(38),
      tx_ext_fifo_back_data(37) => tx_ext_fifo_back_data(37),
      tx_ext_fifo_back_data(36) => tx_ext_fifo_back_data(36),
      tx_ext_fifo_back_data(35) => tx_ext_fifo_back_data(35),
      tx_ext_fifo_back_data(34) => tx_ext_fifo_back_data(34),
      tx_ext_fifo_back_data(33) => tx_ext_fifo_back_data(33),
      tx_ext_fifo_back_data(32) => tx_ext_fifo_back_data(32),
      tx_ext_fifo_back_data(31) => tx_ext_fifo_back_data(31),
      tx_ext_fifo_back_data(30) => tx_ext_fifo_back_data(30),
      tx_ext_fifo_back_data(29) => tx_ext_fifo_back_data(29),
      tx_ext_fifo_back_data(28) => tx_ext_fifo_back_data(28),
      tx_ext_fifo_back_data(27) => tx_ext_fifo_back_data(27),
      tx_ext_fifo_back_data(26) => tx_ext_fifo_back_data(26),
      tx_ext_fifo_back_data(25) => tx_ext_fifo_back_data(25),
      tx_ext_fifo_back_data(24) => tx_ext_fifo_back_data(24),
      tx_ext_fifo_back_data(23) => tx_ext_fifo_back_data(23),
      tx_ext_fifo_back_data(22) => tx_ext_fifo_back_data(22),
      tx_ext_fifo_back_data(21) => tx_ext_fifo_back_data(21),
      tx_ext_fifo_back_data(20) => tx_ext_fifo_back_data(20),
      tx_ext_fifo_back_data(19) => tx_ext_fifo_back_data(19),
      tx_ext_fifo_back_data(18) => tx_ext_fifo_back_data(18),
      tx_ext_fifo_back_data(17) => tx_ext_fifo_back_data(17),
      tx_ext_fifo_back_data(16) => tx_ext_fifo_back_data(16),
      tx_ext_fifo_back_data(15) => tx_ext_fifo_back_data(15),
      tx_ext_fifo_back_data(14) => tx_ext_fifo_back_data(14),
      tx_ext_fifo_back_data(13) => tx_ext_fifo_back_data(13),
      tx_ext_fifo_back_data(12) => tx_ext_fifo_back_data(12),
      tx_ext_fifo_back_data(11) => tx_ext_fifo_back_data(11),
      tx_ext_fifo_back_data(10) => tx_ext_fifo_back_data(10),
      tx_ext_fifo_back_data(9) => tx_ext_fifo_back_data(9),
      tx_ext_fifo_back_data(8) => tx_ext_fifo_back_data(8),
      tx_ext_fifo_back_data(7) => tx_ext_fifo_back_data(7),
      tx_ext_fifo_back_data(6) => tx_ext_fifo_back_data(6),
      tx_ext_fifo_back_data(5) => tx_ext_fifo_back_data(5),
      tx_ext_fifo_back_data(4) => tx_ext_fifo_back_data(4),
      tx_ext_fifo_back_data(3) => tx_ext_fifo_back_data(3),
      tx_ext_fifo_back_data(2) => tx_ext_fifo_back_data(2),
      tx_ext_fifo_back_data(1) => tx_ext_fifo_back_data(1),
      tx_ext_fifo_back_data(0) => tx_ext_fifo_back_data(0),
      completer_id(15) => cfg_bus_number_c(7),
      completer_id(14) => cfg_bus_number_c(6),
      completer_id(13) => cfg_bus_number_c(5),
      completer_id(12) => cfg_bus_number_c(4),
      completer_id(11) => cfg_bus_number_c(3),
      completer_id(10) => cfg_bus_number_c(2),
      completer_id(9) => cfg_bus_number_c(1),
      completer_id(8) => cfg_bus_number_c(0),
      completer_id(7) => cfg_device_number_c(4),
      completer_id(6) => cfg_device_number_c(3),
      completer_id(5) => cfg_device_number_c(2),
      completer_id(4) => cfg_device_number_c(1),
      completer_id(3) => cfg_device_number_c(0),
      completer_id(2) => cfg_function_number_c(2),
      completer_id(1) => cfg_function_number_c(1),
      completer_id(0) => cfg_function_number_c(0),
      rx_tx_engine_request_attr(3) => rx_tx_engine_request_attr(3),
      rx_tx_engine_request_attr(2) => rx_tx_engine_request_attr(2),
      rx_tx_engine_request_attr(1) => rx_tx_engine_request_attr(1),
      rx_tx_engine_request_attr(0) => rx_tx_engine_request_attr(0),
      rx_tx_engine_request_id(15) => rx_tx_engine_request_id(15),
      rx_tx_engine_request_id(14) => rx_tx_engine_request_id(14),
      rx_tx_engine_request_id(13) => rx_tx_engine_request_id(13),
      rx_tx_engine_request_id(12) => rx_tx_engine_request_id(12),
      rx_tx_engine_request_id(11) => rx_tx_engine_request_id(11),
      rx_tx_engine_request_id(10) => rx_tx_engine_request_id(10),
      rx_tx_engine_request_id(9) => rx_tx_engine_request_id(9),
      rx_tx_engine_request_id(8) => rx_tx_engine_request_id(8),
      rx_tx_engine_request_id(7) => rx_tx_engine_request_id(7),
      rx_tx_engine_request_id(6) => rx_tx_engine_request_id(6),
      rx_tx_engine_request_id(5) => rx_tx_engine_request_id(5),
      rx_tx_engine_request_id(4) => rx_tx_engine_request_id(4),
      rx_tx_engine_request_id(3) => rx_tx_engine_request_id(3),
      rx_tx_engine_request_id(2) => rx_tx_engine_request_id(2),
      rx_tx_engine_request_id(1) => rx_tx_engine_request_id(1),
      rx_tx_engine_request_id(0) => rx_tx_engine_request_id(0),
      reg_access_back_data(31) => reg_access_back_data(31),
      reg_access_back_data(30) => reg_access_back_data(30),
      reg_access_back_data(29) => reg_access_back_data(29),
      reg_access_back_data(28) => reg_access_back_data(28),
      reg_access_back_data(27) => reg_access_back_data(27),
      reg_access_back_data(26) => reg_access_back_data(26),
      reg_access_back_data(25) => reg_access_back_data(25),
      reg_access_back_data(24) => reg_access_back_data(24),
      reg_access_back_data(23) => reg_access_back_data(23),
      reg_access_back_data(22) => reg_access_back_data(22),
      reg_access_back_data(21) => reg_access_back_data(21),
      reg_access_back_data(20) => reg_access_back_data(20),
      reg_access_back_data(19) => reg_access_back_data(19),
      reg_access_back_data(18) => reg_access_back_data(18),
      reg_access_back_data(17) => reg_access_back_data(17),
      reg_access_back_data(16) => reg_access_back_data(16),
      reg_access_back_data(15) => reg_access_back_data(15),
      reg_access_back_data(14) => reg_access_back_data(14),
      reg_access_back_data(13) => reg_access_back_data(13),
      reg_access_back_data(12) => reg_access_back_data(12),
      reg_access_back_data(11) => reg_access_back_data(11),
      reg_access_back_data(10) => reg_access_back_data(10),
      reg_access_back_data(9) => reg_access_back_data(9),
      reg_access_back_data(8) => reg_access_back_data(8),
      reg_access_back_data(7) => reg_access_back_data(7),
      reg_access_back_data(6) => reg_access_back_data(6),
      reg_access_back_data(5) => reg_access_back_data(5),
      reg_access_back_data(4) => reg_access_back_data(4),
      reg_access_back_data(3) => reg_access_back_data(3),
      reg_access_back_data(2) => reg_access_back_data(2),
      reg_access_back_data(1) => reg_access_back_data(1),
      reg_access_back_data(0) => reg_access_back_data(0),
      rx_tx_engine_request_tc(2) => rx_tx_engine_request_tc(2),
      rx_tx_engine_request_tc(1) => rx_tx_engine_request_tc(1),
      rx_tx_engine_request_tc(0) => rx_tx_engine_request_tc(0),
      trn_tx_back_trn_tbuf_av(5) => NLW_tx_trn_tx_back_trn_tbuf_av_5_UNCONNECTED,
      trn_tx_back_trn_tbuf_av(4) => NLW_tx_trn_tx_back_trn_tbuf_av_4_UNCONNECTED,
      trn_tx_back_trn_tbuf_av(3) => trn_tx_back_trn_tbuf_av(3),
      trn_tx_back_trn_tbuf_av(2) => trn_tx_back_trn_tbuf_av(2),
      trn_tx_back_trn_tbuf_av(1) => trn_tx_back_trn_tbuf_av(1),
      trn_tx_back_trn_tbuf_av(0) => trn_tx_back_trn_tbuf_av(0),
      rx_tx_engine_request_tag(7) => rx_tx_engine_request_tag(7),
      rx_tx_engine_request_tag(6) => rx_tx_engine_request_tag(6),
      rx_tx_engine_request_tag(5) => rx_tx_engine_request_tag(5),
      rx_tx_engine_request_tag(4) => rx_tx_engine_request_tag(4),
      rx_tx_engine_request_tag(3) => rx_tx_engine_request_tag(3),
      rx_tx_engine_request_tag(2) => rx_tx_engine_request_tag(2),
      rx_tx_engine_request_tag(1) => rx_tx_engine_request_tag(1),
      rx_tx_engine_request_tag(0) => rx_tx_engine_request_tag(0),
      trn_tx_back_cfg_dcommand(15) => trn_tx_back_cfg_dcommand(15),
      trn_tx_back_cfg_dcommand(14) => trn_tx_back_cfg_dcommand(14),
      trn_tx_back_cfg_dcommand(13) => trn_tx_back_cfg_dcommand(13),
      trn_tx_back_cfg_dcommand(12) => trn_tx_back_cfg_dcommand(12),
      trn_tx_back_cfg_dcommand(11) => trn_tx_back_cfg_dcommand(11),
      trn_tx_back_cfg_dcommand(10) => trn_tx_back_cfg_dcommand(10),
      trn_tx_back_cfg_dcommand(9) => trn_tx_back_cfg_dcommand(9),
      trn_tx_back_cfg_dcommand(8) => trn_tx_back_cfg_dcommand(8),
      trn_tx_back_cfg_dcommand(7) => trn_tx_back_cfg_dcommand(7),
      trn_tx_back_cfg_dcommand(6) => trn_tx_back_cfg_dcommand(6),
      trn_tx_back_cfg_dcommand(5) => trn_tx_back_cfg_dcommand(5),
      trn_tx_back_cfg_dcommand(4) => trn_tx_back_cfg_dcommand(4),
      trn_tx_back_cfg_dcommand(3) => trn_tx_back_cfg_dcommand(3),
      trn_tx_back_cfg_dcommand(2) => trn_tx_back_cfg_dcommand(2),
      trn_tx_back_cfg_dcommand(1) => trn_tx_back_cfg_dcommand(1),
      trn_tx_back_cfg_dcommand(0) => trn_tx_back_cfg_dcommand(0),
      rx_tx_engine_lower_adr(6) => rx_tx_engine_lower_adr(6),
      rx_tx_engine_lower_adr(5) => rx_tx_engine_lower_adr(5),
      rx_tx_engine_lower_adr(4) => rx_tx_engine_lower_adr(4),
      rx_tx_engine_lower_adr(3) => rx_tx_engine_lower_adr(3),
      rx_tx_engine_lower_adr(2) => rx_tx_engine_lower_adr(2)
    );
  fifo : block_pe_fifo_ext
    port map (
      irq => irq,
      reg_ext_fifo_data_we => reg_ext_fifo_data_we,
      clk => NlwRenamedSig_OI_clk_out,
      ext_fifo_disp_back_data_we => ext_fifo_disp_back_data_we,
      aclk => aclk,
      tx_ext_fifo_back_rd_size => tx_ext_fifo_back_rd_size,
      ext_fifo_disp_back_irq => ext_fifo_disp_back_irq,
      tx_ext_fifo_complete_error => tx_ext_fifo_complete_error,
      rstp => pb_rstp_32527,
      tx_ext_fifo_back_req_rd => tx_ext_fifo_back_req_rd,
      ext_fifo_disp_data_we => ext_fifo_disp_data_we,
      rx_ext_fifo_data_we => rx_ext_fifo_data_we,
      tx_ext_fifo_back_req_wr => tx_ext_fifo_back_req_wr,
      ext_fifo_disp_request_rd => ext_fifo_disp_request_rd,
      ext_fifo_disp_back_allow_wr => ext_fifo_disp_back_allow_wr,
      tx_ext_fifo_complete_ok => tx_ext_fifo_complete_ok,
      ext_fifo_disp_request_wr => ext_fifo_disp_request_wr,
      ext_fifo_disp_adr(31) => ext_fifo_disp_adr(31),
      ext_fifo_disp_adr(30) => ext_fifo_disp_adr(30),
      ext_fifo_disp_adr(29) => ext_fifo_disp_adr(29),
      ext_fifo_disp_adr(28) => ext_fifo_disp_adr(28),
      ext_fifo_disp_adr(27) => ext_fifo_disp_adr(27),
      ext_fifo_disp_adr(26) => ext_fifo_disp_adr(26),
      ext_fifo_disp_adr(25) => ext_fifo_disp_adr(25),
      ext_fifo_disp_adr(24) => ext_fifo_disp_adr(24),
      ext_fifo_disp_adr(23) => ext_fifo_disp_adr(23),
      ext_fifo_disp_adr(22) => ext_fifo_disp_adr(22),
      ext_fifo_disp_adr(21) => ext_fifo_disp_adr(21),
      ext_fifo_disp_adr(20) => ext_fifo_disp_adr(20),
      ext_fifo_disp_adr(19) => ext_fifo_disp_adr(19),
      ext_fifo_disp_adr(18) => ext_fifo_disp_adr(18),
      ext_fifo_disp_adr(17) => ext_fifo_disp_adr(17),
      ext_fifo_disp_adr(16) => ext_fifo_disp_adr(16),
      ext_fifo_disp_adr(15) => ext_fifo_disp_adr(15),
      ext_fifo_disp_adr(14) => ext_fifo_disp_adr(14),
      ext_fifo_disp_adr(13) => ext_fifo_disp_adr(13),
      ext_fifo_disp_adr(12) => ext_fifo_disp_adr(12),
      ext_fifo_disp_adr(11) => ext_fifo_disp_adr(11),
      ext_fifo_disp_adr(10) => ext_fifo_disp_adr(10),
      ext_fifo_disp_adr(9) => ext_fifo_disp_adr(9),
      ext_fifo_disp_adr(8) => ext_fifo_disp_adr(8),
      ext_fifo_disp_adr(7) => ext_fifo_disp_adr(7),
      ext_fifo_disp_adr(6) => ext_fifo_disp_adr(6),
      ext_fifo_disp_adr(5) => ext_fifo_disp_adr(5),
      ext_fifo_disp_adr(4) => ext_fifo_disp_adr(4),
      ext_fifo_disp_adr(3) => ext_fifo_disp_adr(3),
      ext_fifo_disp_adr(2) => ext_fifo_disp_adr(2),
      ext_fifo_disp_adr(1) => ext_fifo_disp_adr(1),
      ext_fifo_disp_adr(0) => ext_fifo_disp_adr(0),
      tx_ext_fifo_back_pci_adr(39) => tx_ext_fifo_back_pci_adr(39),
      tx_ext_fifo_back_pci_adr(38) => tx_ext_fifo_back_pci_adr(38),
      tx_ext_fifo_back_pci_adr(37) => tx_ext_fifo_back_pci_adr(37),
      tx_ext_fifo_back_pci_adr(36) => tx_ext_fifo_back_pci_adr(36),
      tx_ext_fifo_back_pci_adr(35) => tx_ext_fifo_back_pci_adr(35),
      tx_ext_fifo_back_pci_adr(34) => tx_ext_fifo_back_pci_adr(34),
      tx_ext_fifo_back_pci_adr(33) => tx_ext_fifo_back_pci_adr(33),
      tx_ext_fifo_back_pci_adr(32) => tx_ext_fifo_back_pci_adr(32),
      tx_ext_fifo_back_pci_adr(31) => tx_ext_fifo_back_pci_adr(31),
      tx_ext_fifo_back_pci_adr(30) => tx_ext_fifo_back_pci_adr(30),
      tx_ext_fifo_back_pci_adr(29) => tx_ext_fifo_back_pci_adr(29),
      tx_ext_fifo_back_pci_adr(28) => tx_ext_fifo_back_pci_adr(28),
      tx_ext_fifo_back_pci_adr(27) => tx_ext_fifo_back_pci_adr(27),
      tx_ext_fifo_back_pci_adr(26) => tx_ext_fifo_back_pci_adr(26),
      tx_ext_fifo_back_pci_adr(25) => tx_ext_fifo_back_pci_adr(25),
      tx_ext_fifo_back_pci_adr(24) => tx_ext_fifo_back_pci_adr(24),
      tx_ext_fifo_back_pci_adr(23) => tx_ext_fifo_back_pci_adr(23),
      tx_ext_fifo_back_pci_adr(22) => tx_ext_fifo_back_pci_adr(22),
      tx_ext_fifo_back_pci_adr(21) => tx_ext_fifo_back_pci_adr(21),
      tx_ext_fifo_back_pci_adr(20) => tx_ext_fifo_back_pci_adr(20),
      tx_ext_fifo_back_pci_adr(19) => tx_ext_fifo_back_pci_adr(19),
      tx_ext_fifo_back_pci_adr(18) => tx_ext_fifo_back_pci_adr(18),
      tx_ext_fifo_back_pci_adr(17) => tx_ext_fifo_back_pci_adr(17),
      tx_ext_fifo_back_pci_adr(16) => tx_ext_fifo_back_pci_adr(16),
      tx_ext_fifo_back_pci_adr(15) => tx_ext_fifo_back_pci_adr(15),
      tx_ext_fifo_back_pci_adr(14) => tx_ext_fifo_back_pci_adr(14),
      tx_ext_fifo_back_pci_adr(13) => tx_ext_fifo_back_pci_adr(13),
      tx_ext_fifo_back_pci_adr(12) => tx_ext_fifo_back_pci_adr(12),
      tx_ext_fifo_back_pci_adr(11) => tx_ext_fifo_back_pci_adr(11),
      tx_ext_fifo_back_pci_adr(10) => tx_ext_fifo_back_pci_adr(10),
      tx_ext_fifo_back_pci_adr(9) => tx_ext_fifo_back_pci_adr(9),
      tx_ext_fifo_back_pci_adr(8) => tx_ext_fifo_back_pci_adr(8),
      tx_ext_fifo_back_data(63) => tx_ext_fifo_back_data(63),
      tx_ext_fifo_back_data(62) => tx_ext_fifo_back_data(62),
      tx_ext_fifo_back_data(61) => tx_ext_fifo_back_data(61),
      tx_ext_fifo_back_data(60) => tx_ext_fifo_back_data(60),
      tx_ext_fifo_back_data(59) => tx_ext_fifo_back_data(59),
      tx_ext_fifo_back_data(58) => tx_ext_fifo_back_data(58),
      tx_ext_fifo_back_data(57) => tx_ext_fifo_back_data(57),
      tx_ext_fifo_back_data(56) => tx_ext_fifo_back_data(56),
      tx_ext_fifo_back_data(55) => tx_ext_fifo_back_data(55),
      tx_ext_fifo_back_data(54) => tx_ext_fifo_back_data(54),
      tx_ext_fifo_back_data(53) => tx_ext_fifo_back_data(53),
      tx_ext_fifo_back_data(52) => tx_ext_fifo_back_data(52),
      tx_ext_fifo_back_data(51) => tx_ext_fifo_back_data(51),
      tx_ext_fifo_back_data(50) => tx_ext_fifo_back_data(50),
      tx_ext_fifo_back_data(49) => tx_ext_fifo_back_data(49),
      tx_ext_fifo_back_data(48) => tx_ext_fifo_back_data(48),
      tx_ext_fifo_back_data(47) => tx_ext_fifo_back_data(47),
      tx_ext_fifo_back_data(46) => tx_ext_fifo_back_data(46),
      tx_ext_fifo_back_data(45) => tx_ext_fifo_back_data(45),
      tx_ext_fifo_back_data(44) => tx_ext_fifo_back_data(44),
      tx_ext_fifo_back_data(43) => tx_ext_fifo_back_data(43),
      tx_ext_fifo_back_data(42) => tx_ext_fifo_back_data(42),
      tx_ext_fifo_back_data(41) => tx_ext_fifo_back_data(41),
      tx_ext_fifo_back_data(40) => tx_ext_fifo_back_data(40),
      tx_ext_fifo_back_data(39) => tx_ext_fifo_back_data(39),
      tx_ext_fifo_back_data(38) => tx_ext_fifo_back_data(38),
      tx_ext_fifo_back_data(37) => tx_ext_fifo_back_data(37),
      tx_ext_fifo_back_data(36) => tx_ext_fifo_back_data(36),
      tx_ext_fifo_back_data(35) => tx_ext_fifo_back_data(35),
      tx_ext_fifo_back_data(34) => tx_ext_fifo_back_data(34),
      tx_ext_fifo_back_data(33) => tx_ext_fifo_back_data(33),
      tx_ext_fifo_back_data(32) => tx_ext_fifo_back_data(32),
      tx_ext_fifo_back_data(31) => tx_ext_fifo_back_data(31),
      tx_ext_fifo_back_data(30) => tx_ext_fifo_back_data(30),
      tx_ext_fifo_back_data(29) => tx_ext_fifo_back_data(29),
      tx_ext_fifo_back_data(28) => tx_ext_fifo_back_data(28),
      tx_ext_fifo_back_data(27) => tx_ext_fifo_back_data(27),
      tx_ext_fifo_back_data(26) => tx_ext_fifo_back_data(26),
      tx_ext_fifo_back_data(25) => tx_ext_fifo_back_data(25),
      tx_ext_fifo_back_data(24) => tx_ext_fifo_back_data(24),
      tx_ext_fifo_back_data(23) => tx_ext_fifo_back_data(23),
      tx_ext_fifo_back_data(22) => tx_ext_fifo_back_data(22),
      tx_ext_fifo_back_data(21) => tx_ext_fifo_back_data(21),
      tx_ext_fifo_back_data(20) => tx_ext_fifo_back_data(20),
      tx_ext_fifo_back_data(19) => tx_ext_fifo_back_data(19),
      tx_ext_fifo_back_data(18) => tx_ext_fifo_back_data(18),
      tx_ext_fifo_back_data(17) => tx_ext_fifo_back_data(17),
      tx_ext_fifo_back_data(16) => tx_ext_fifo_back_data(16),
      tx_ext_fifo_back_data(15) => tx_ext_fifo_back_data(15),
      tx_ext_fifo_back_data(14) => tx_ext_fifo_back_data(14),
      tx_ext_fifo_back_data(13) => tx_ext_fifo_back_data(13),
      tx_ext_fifo_back_data(12) => tx_ext_fifo_back_data(12),
      tx_ext_fifo_back_data(11) => tx_ext_fifo_back_data(11),
      tx_ext_fifo_back_data(10) => tx_ext_fifo_back_data(10),
      tx_ext_fifo_back_data(9) => tx_ext_fifo_back_data(9),
      tx_ext_fifo_back_data(8) => tx_ext_fifo_back_data(8),
      tx_ext_fifo_back_data(7) => tx_ext_fifo_back_data(7),
      tx_ext_fifo_back_data(6) => tx_ext_fifo_back_data(6),
      tx_ext_fifo_back_data(5) => tx_ext_fifo_back_data(5),
      tx_ext_fifo_back_data(4) => tx_ext_fifo_back_data(4),
      tx_ext_fifo_back_data(3) => tx_ext_fifo_back_data(3),
      tx_ext_fifo_back_data(2) => tx_ext_fifo_back_data(2),
      tx_ext_fifo_back_data(1) => tx_ext_fifo_back_data(1),
      tx_ext_fifo_back_data(0) => tx_ext_fifo_back_data(0),
      reg_ext_fifo_back_data(31) => reg_ext_fifo_back_data(31),
      reg_ext_fifo_back_data(30) => reg_ext_fifo_back_data(30),
      reg_ext_fifo_back_data(29) => reg_ext_fifo_back_data(29),
      reg_ext_fifo_back_data(28) => reg_ext_fifo_back_data(28),
      reg_ext_fifo_back_data(27) => reg_ext_fifo_back_data(27),
      reg_ext_fifo_back_data(26) => reg_ext_fifo_back_data(26),
      reg_ext_fifo_back_data(25) => reg_ext_fifo_back_data(25),
      reg_ext_fifo_back_data(24) => reg_ext_fifo_back_data(24),
      reg_ext_fifo_back_data(23) => reg_ext_fifo_back_data(23),
      reg_ext_fifo_back_data(22) => reg_ext_fifo_back_data(22),
      reg_ext_fifo_back_data(21) => reg_ext_fifo_back_data(21),
      reg_ext_fifo_back_data(20) => reg_ext_fifo_back_data(20),
      reg_ext_fifo_back_data(19) => reg_ext_fifo_back_data(19),
      reg_ext_fifo_back_data(18) => reg_ext_fifo_back_data(18),
      reg_ext_fifo_back_data(17) => reg_ext_fifo_back_data(17),
      reg_ext_fifo_back_data(16) => reg_ext_fifo_back_data(16),
      reg_ext_fifo_back_data(15) => reg_ext_fifo_back_data(15),
      reg_ext_fifo_back_data(14) => reg_ext_fifo_back_data(14),
      reg_ext_fifo_back_data(13) => reg_ext_fifo_back_data(13),
      reg_ext_fifo_back_data(12) => reg_ext_fifo_back_data(12),
      reg_ext_fifo_back_data(11) => reg_ext_fifo_back_data(11),
      reg_ext_fifo_back_data(10) => reg_ext_fifo_back_data(10),
      reg_ext_fifo_back_data(9) => reg_ext_fifo_back_data(9),
      reg_ext_fifo_back_data(8) => reg_ext_fifo_back_data(8),
      reg_ext_fifo_back_data(7) => reg_ext_fifo_back_data(7),
      reg_ext_fifo_back_data(6) => reg_ext_fifo_back_data(6),
      reg_ext_fifo_back_data(5) => reg_ext_fifo_back_data(5),
      reg_ext_fifo_back_data(4) => reg_ext_fifo_back_data(4),
      reg_ext_fifo_back_data(3) => reg_ext_fifo_back_data(3),
      reg_ext_fifo_back_data(2) => reg_ext_fifo_back_data(2),
      reg_ext_fifo_back_data(1) => reg_ext_fifo_back_data(1),
      reg_ext_fifo_back_data(0) => reg_ext_fifo_back_data(0),
      test(7) => px(7),
      test(6) => px(6),
      test(5) => px(5),
      test(4) => px(4),
      test(3) => px(3),
      test(2) => px(2),
      test(1) => px(1),
      test(0) => px(0),
      ext_fifo_disp_data(63) => ext_fifo_disp_data(63),
      ext_fifo_disp_data(62) => ext_fifo_disp_data(62),
      ext_fifo_disp_data(61) => ext_fifo_disp_data(61),
      ext_fifo_disp_data(60) => ext_fifo_disp_data(60),
      ext_fifo_disp_data(59) => ext_fifo_disp_data(59),
      ext_fifo_disp_data(58) => ext_fifo_disp_data(58),
      ext_fifo_disp_data(57) => ext_fifo_disp_data(57),
      ext_fifo_disp_data(56) => ext_fifo_disp_data(56),
      ext_fifo_disp_data(55) => ext_fifo_disp_data(55),
      ext_fifo_disp_data(54) => ext_fifo_disp_data(54),
      ext_fifo_disp_data(53) => ext_fifo_disp_data(53),
      ext_fifo_disp_data(52) => ext_fifo_disp_data(52),
      ext_fifo_disp_data(51) => ext_fifo_disp_data(51),
      ext_fifo_disp_data(50) => ext_fifo_disp_data(50),
      ext_fifo_disp_data(49) => ext_fifo_disp_data(49),
      ext_fifo_disp_data(48) => ext_fifo_disp_data(48),
      ext_fifo_disp_data(47) => ext_fifo_disp_data(47),
      ext_fifo_disp_data(46) => ext_fifo_disp_data(46),
      ext_fifo_disp_data(45) => ext_fifo_disp_data(45),
      ext_fifo_disp_data(44) => ext_fifo_disp_data(44),
      ext_fifo_disp_data(43) => ext_fifo_disp_data(43),
      ext_fifo_disp_data(42) => ext_fifo_disp_data(42),
      ext_fifo_disp_data(41) => ext_fifo_disp_data(41),
      ext_fifo_disp_data(40) => ext_fifo_disp_data(40),
      ext_fifo_disp_data(39) => ext_fifo_disp_data(39),
      ext_fifo_disp_data(38) => ext_fifo_disp_data(38),
      ext_fifo_disp_data(37) => ext_fifo_disp_data(37),
      ext_fifo_disp_data(36) => ext_fifo_disp_data(36),
      ext_fifo_disp_data(35) => ext_fifo_disp_data(35),
      ext_fifo_disp_data(34) => ext_fifo_disp_data(34),
      ext_fifo_disp_data(33) => ext_fifo_disp_data(33),
      ext_fifo_disp_data(32) => ext_fifo_disp_data(32),
      ext_fifo_disp_data(31) => ext_fifo_disp_data(31),
      ext_fifo_disp_data(30) => ext_fifo_disp_data(30),
      ext_fifo_disp_data(29) => ext_fifo_disp_data(29),
      ext_fifo_disp_data(28) => ext_fifo_disp_data(28),
      ext_fifo_disp_data(27) => ext_fifo_disp_data(27),
      ext_fifo_disp_data(26) => ext_fifo_disp_data(26),
      ext_fifo_disp_data(25) => ext_fifo_disp_data(25),
      ext_fifo_disp_data(24) => ext_fifo_disp_data(24),
      ext_fifo_disp_data(23) => ext_fifo_disp_data(23),
      ext_fifo_disp_data(22) => ext_fifo_disp_data(22),
      ext_fifo_disp_data(21) => ext_fifo_disp_data(21),
      ext_fifo_disp_data(20) => ext_fifo_disp_data(20),
      ext_fifo_disp_data(19) => ext_fifo_disp_data(19),
      ext_fifo_disp_data(18) => ext_fifo_disp_data(18),
      ext_fifo_disp_data(17) => ext_fifo_disp_data(17),
      ext_fifo_disp_data(16) => ext_fifo_disp_data(16),
      ext_fifo_disp_data(15) => ext_fifo_disp_data(15),
      ext_fifo_disp_data(14) => ext_fifo_disp_data(14),
      ext_fifo_disp_data(13) => ext_fifo_disp_data(13),
      ext_fifo_disp_data(12) => ext_fifo_disp_data(12),
      ext_fifo_disp_data(11) => ext_fifo_disp_data(11),
      ext_fifo_disp_data(10) => ext_fifo_disp_data(10),
      ext_fifo_disp_data(9) => ext_fifo_disp_data(9),
      ext_fifo_disp_data(8) => ext_fifo_disp_data(8),
      ext_fifo_disp_data(7) => ext_fifo_disp_data(7),
      ext_fifo_disp_data(6) => ext_fifo_disp_data(6),
      ext_fifo_disp_data(5) => ext_fifo_disp_data(5),
      ext_fifo_disp_data(4) => ext_fifo_disp_data(4),
      ext_fifo_disp_data(3) => ext_fifo_disp_data(3),
      ext_fifo_disp_data(2) => ext_fifo_disp_data(2),
      ext_fifo_disp_data(1) => ext_fifo_disp_data(1),
      ext_fifo_disp_data(0) => ext_fifo_disp_data(0),
      ext_fifo_disp_back_data(63) => ext_fifo_disp_back_data(63),
      ext_fifo_disp_back_data(62) => ext_fifo_disp_back_data(62),
      ext_fifo_disp_back_data(61) => ext_fifo_disp_back_data(61),
      ext_fifo_disp_back_data(60) => ext_fifo_disp_back_data(60),
      ext_fifo_disp_back_data(59) => ext_fifo_disp_back_data(59),
      ext_fifo_disp_back_data(58) => ext_fifo_disp_back_data(58),
      ext_fifo_disp_back_data(57) => ext_fifo_disp_back_data(57),
      ext_fifo_disp_back_data(56) => ext_fifo_disp_back_data(56),
      ext_fifo_disp_back_data(55) => ext_fifo_disp_back_data(55),
      ext_fifo_disp_back_data(54) => ext_fifo_disp_back_data(54),
      ext_fifo_disp_back_data(53) => ext_fifo_disp_back_data(53),
      ext_fifo_disp_back_data(52) => ext_fifo_disp_back_data(52),
      ext_fifo_disp_back_data(51) => ext_fifo_disp_back_data(51),
      ext_fifo_disp_back_data(50) => ext_fifo_disp_back_data(50),
      ext_fifo_disp_back_data(49) => ext_fifo_disp_back_data(49),
      ext_fifo_disp_back_data(48) => ext_fifo_disp_back_data(48),
      ext_fifo_disp_back_data(47) => ext_fifo_disp_back_data(47),
      ext_fifo_disp_back_data(46) => ext_fifo_disp_back_data(46),
      ext_fifo_disp_back_data(45) => ext_fifo_disp_back_data(45),
      ext_fifo_disp_back_data(44) => ext_fifo_disp_back_data(44),
      ext_fifo_disp_back_data(43) => ext_fifo_disp_back_data(43),
      ext_fifo_disp_back_data(42) => ext_fifo_disp_back_data(42),
      ext_fifo_disp_back_data(41) => ext_fifo_disp_back_data(41),
      ext_fifo_disp_back_data(40) => ext_fifo_disp_back_data(40),
      ext_fifo_disp_back_data(39) => ext_fifo_disp_back_data(39),
      ext_fifo_disp_back_data(38) => ext_fifo_disp_back_data(38),
      ext_fifo_disp_back_data(37) => ext_fifo_disp_back_data(37),
      ext_fifo_disp_back_data(36) => ext_fifo_disp_back_data(36),
      ext_fifo_disp_back_data(35) => ext_fifo_disp_back_data(35),
      ext_fifo_disp_back_data(34) => ext_fifo_disp_back_data(34),
      ext_fifo_disp_back_data(33) => ext_fifo_disp_back_data(33),
      ext_fifo_disp_back_data(32) => ext_fifo_disp_back_data(32),
      ext_fifo_disp_back_data(31) => ext_fifo_disp_back_data(31),
      ext_fifo_disp_back_data(30) => ext_fifo_disp_back_data(30),
      ext_fifo_disp_back_data(29) => ext_fifo_disp_back_data(29),
      ext_fifo_disp_back_data(28) => ext_fifo_disp_back_data(28),
      ext_fifo_disp_back_data(27) => ext_fifo_disp_back_data(27),
      ext_fifo_disp_back_data(26) => ext_fifo_disp_back_data(26),
      ext_fifo_disp_back_data(25) => ext_fifo_disp_back_data(25),
      ext_fifo_disp_back_data(24) => ext_fifo_disp_back_data(24),
      ext_fifo_disp_back_data(23) => ext_fifo_disp_back_data(23),
      ext_fifo_disp_back_data(22) => ext_fifo_disp_back_data(22),
      ext_fifo_disp_back_data(21) => ext_fifo_disp_back_data(21),
      ext_fifo_disp_back_data(20) => ext_fifo_disp_back_data(20),
      ext_fifo_disp_back_data(19) => ext_fifo_disp_back_data(19),
      ext_fifo_disp_back_data(18) => ext_fifo_disp_back_data(18),
      ext_fifo_disp_back_data(17) => ext_fifo_disp_back_data(17),
      ext_fifo_disp_back_data(16) => ext_fifo_disp_back_data(16),
      ext_fifo_disp_back_data(15) => ext_fifo_disp_back_data(15),
      ext_fifo_disp_back_data(14) => ext_fifo_disp_back_data(14),
      ext_fifo_disp_back_data(13) => ext_fifo_disp_back_data(13),
      ext_fifo_disp_back_data(12) => ext_fifo_disp_back_data(12),
      ext_fifo_disp_back_data(11) => ext_fifo_disp_back_data(11),
      ext_fifo_disp_back_data(10) => ext_fifo_disp_back_data(10),
      ext_fifo_disp_back_data(9) => ext_fifo_disp_back_data(9),
      ext_fifo_disp_back_data(8) => ext_fifo_disp_back_data(8),
      ext_fifo_disp_back_data(7) => ext_fifo_disp_back_data(7),
      ext_fifo_disp_back_data(6) => ext_fifo_disp_back_data(6),
      ext_fifo_disp_back_data(5) => ext_fifo_disp_back_data(5),
      ext_fifo_disp_back_data(4) => ext_fifo_disp_back_data(4),
      ext_fifo_disp_back_data(3) => ext_fifo_disp_back_data(3),
      ext_fifo_disp_back_data(2) => ext_fifo_disp_back_data(2),
      ext_fifo_disp_back_data(1) => ext_fifo_disp_back_data(1),
      ext_fifo_disp_back_data(0) => ext_fifo_disp_back_data(0),
      ext_fifo_disp_back_dmar(1) => ext_fifo_disp_back_dmar(1),
      ext_fifo_disp_back_dmar(0) => ext_fifo_disp_back_dmar(0),
      reg_ext_fifo_data(31) => reg_ext_fifo_data(31),
      reg_ext_fifo_data(30) => reg_ext_fifo_data(30),
      reg_ext_fifo_data(29) => reg_ext_fifo_data(29),
      reg_ext_fifo_data(28) => reg_ext_fifo_data(28),
      reg_ext_fifo_data(27) => reg_ext_fifo_data(27),
      reg_ext_fifo_data(26) => reg_ext_fifo_data(26),
      reg_ext_fifo_data(25) => reg_ext_fifo_data(25),
      reg_ext_fifo_data(24) => reg_ext_fifo_data(24),
      reg_ext_fifo_data(23) => reg_ext_fifo_data(23),
      reg_ext_fifo_data(22) => reg_ext_fifo_data(22),
      reg_ext_fifo_data(21) => reg_ext_fifo_data(21),
      reg_ext_fifo_data(20) => reg_ext_fifo_data(20),
      reg_ext_fifo_data(19) => reg_ext_fifo_data(19),
      reg_ext_fifo_data(18) => reg_ext_fifo_data(18),
      reg_ext_fifo_data(17) => reg_ext_fifo_data(17),
      reg_ext_fifo_data(16) => reg_ext_fifo_data(16),
      reg_ext_fifo_data(15) => reg_ext_fifo_data(15),
      reg_ext_fifo_data(14) => reg_ext_fifo_data(14),
      reg_ext_fifo_data(13) => reg_ext_fifo_data(13),
      reg_ext_fifo_data(12) => reg_ext_fifo_data(12),
      reg_ext_fifo_data(11) => reg_ext_fifo_data(11),
      reg_ext_fifo_data(10) => reg_ext_fifo_data(10),
      reg_ext_fifo_data(9) => reg_ext_fifo_data(9),
      reg_ext_fifo_data(8) => reg_ext_fifo_data(8),
      reg_ext_fifo_data(7) => reg_ext_fifo_data(7),
      reg_ext_fifo_data(6) => reg_ext_fifo_data(6),
      reg_ext_fifo_data(5) => reg_ext_fifo_data(5),
      reg_ext_fifo_data(4) => reg_ext_fifo_data(4),
      reg_ext_fifo_data(3) => reg_ext_fifo_data(3),
      reg_ext_fifo_data(2) => reg_ext_fifo_data(2),
      reg_ext_fifo_data(1) => reg_ext_fifo_data(1),
      reg_ext_fifo_data(0) => reg_ext_fifo_data(0),
      reg_ext_fifo_adr(6) => reg_ext_fifo_adr(6),
      reg_ext_fifo_adr(5) => reg_ext_fifo_adr(5),
      reg_ext_fifo_adr(4) => reg_ext_fifo_adr(4),
      reg_ext_fifo_adr(3) => reg_ext_fifo_adr(3),
      reg_ext_fifo_adr(2) => reg_ext_fifo_adr(2),
      reg_ext_fifo_adr(1) => reg_ext_fifo_adr(1),
      reg_ext_fifo_adr(0) => reg_ext_fifo_adr(0),
      rx_ext_fifo_data(63) => rx_ext_fifo_data(63),
      rx_ext_fifo_data(62) => rx_ext_fifo_data(62),
      rx_ext_fifo_data(61) => rx_ext_fifo_data(61),
      rx_ext_fifo_data(60) => rx_ext_fifo_data(60),
      rx_ext_fifo_data(59) => rx_ext_fifo_data(59),
      rx_ext_fifo_data(58) => rx_ext_fifo_data(58),
      rx_ext_fifo_data(57) => rx_ext_fifo_data(57),
      rx_ext_fifo_data(56) => rx_ext_fifo_data(56),
      rx_ext_fifo_data(55) => rx_ext_fifo_data(55),
      rx_ext_fifo_data(54) => rx_ext_fifo_data(54),
      rx_ext_fifo_data(53) => rx_ext_fifo_data(53),
      rx_ext_fifo_data(52) => rx_ext_fifo_data(52),
      rx_ext_fifo_data(51) => rx_ext_fifo_data(51),
      rx_ext_fifo_data(50) => rx_ext_fifo_data(50),
      rx_ext_fifo_data(49) => rx_ext_fifo_data(49),
      rx_ext_fifo_data(48) => rx_ext_fifo_data(48),
      rx_ext_fifo_data(47) => rx_ext_fifo_data(47),
      rx_ext_fifo_data(46) => rx_ext_fifo_data(46),
      rx_ext_fifo_data(45) => rx_ext_fifo_data(45),
      rx_ext_fifo_data(44) => rx_ext_fifo_data(44),
      rx_ext_fifo_data(43) => rx_ext_fifo_data(43),
      rx_ext_fifo_data(42) => rx_ext_fifo_data(42),
      rx_ext_fifo_data(41) => rx_ext_fifo_data(41),
      rx_ext_fifo_data(40) => rx_ext_fifo_data(40),
      rx_ext_fifo_data(39) => rx_ext_fifo_data(39),
      rx_ext_fifo_data(38) => rx_ext_fifo_data(38),
      rx_ext_fifo_data(37) => rx_ext_fifo_data(37),
      rx_ext_fifo_data(36) => rx_ext_fifo_data(36),
      rx_ext_fifo_data(35) => rx_ext_fifo_data(35),
      rx_ext_fifo_data(34) => rx_ext_fifo_data(34),
      rx_ext_fifo_data(33) => rx_ext_fifo_data(33),
      rx_ext_fifo_data(32) => rx_ext_fifo_data(32),
      rx_ext_fifo_data(31) => rx_ext_fifo_data(31),
      rx_ext_fifo_data(30) => rx_ext_fifo_data(30),
      rx_ext_fifo_data(29) => rx_ext_fifo_data(29),
      rx_ext_fifo_data(28) => rx_ext_fifo_data(28),
      rx_ext_fifo_data(27) => rx_ext_fifo_data(27),
      rx_ext_fifo_data(26) => rx_ext_fifo_data(26),
      rx_ext_fifo_data(25) => rx_ext_fifo_data(25),
      rx_ext_fifo_data(24) => rx_ext_fifo_data(24),
      rx_ext_fifo_data(23) => rx_ext_fifo_data(23),
      rx_ext_fifo_data(22) => rx_ext_fifo_data(22),
      rx_ext_fifo_data(21) => rx_ext_fifo_data(21),
      rx_ext_fifo_data(20) => rx_ext_fifo_data(20),
      rx_ext_fifo_data(19) => rx_ext_fifo_data(19),
      rx_ext_fifo_data(18) => rx_ext_fifo_data(18),
      rx_ext_fifo_data(17) => rx_ext_fifo_data(17),
      rx_ext_fifo_data(16) => rx_ext_fifo_data(16),
      rx_ext_fifo_data(15) => rx_ext_fifo_data(15),
      rx_ext_fifo_data(14) => rx_ext_fifo_data(14),
      rx_ext_fifo_data(13) => rx_ext_fifo_data(13),
      rx_ext_fifo_data(12) => rx_ext_fifo_data(12),
      rx_ext_fifo_data(11) => rx_ext_fifo_data(11),
      rx_ext_fifo_data(10) => rx_ext_fifo_data(10),
      rx_ext_fifo_data(9) => rx_ext_fifo_data(9),
      rx_ext_fifo_data(8) => rx_ext_fifo_data(8),
      rx_ext_fifo_data(7) => rx_ext_fifo_data(7),
      rx_ext_fifo_data(6) => rx_ext_fifo_data(6),
      rx_ext_fifo_data(5) => rx_ext_fifo_data(5),
      rx_ext_fifo_data(4) => rx_ext_fifo_data(4),
      rx_ext_fifo_data(3) => rx_ext_fifo_data(3),
      rx_ext_fifo_data(2) => rx_ext_fifo_data(2),
      rx_ext_fifo_data(1) => rx_ext_fifo_data(1),
      rx_ext_fifo_data(0) => rx_ext_fifo_data(0),
      tx_ext_fifo_adr(8) => tx_ext_fifo_adr(8),
      tx_ext_fifo_adr(7) => tx_ext_fifo_adr(7),
      tx_ext_fifo_adr(6) => tx_ext_fifo_adr(6),
      tx_ext_fifo_adr(5) => tx_ext_fifo_adr(5),
      tx_ext_fifo_adr(4) => tx_ext_fifo_adr(4),
      tx_ext_fifo_adr(3) => tx_ext_fifo_adr(3),
      tx_ext_fifo_adr(2) => tx_ext_fifo_adr(2),
      tx_ext_fifo_adr(1) => tx_ext_fifo_adr(1),
      tx_ext_fifo_adr(0) => tx_ext_fifo_adr(0),
      rx_ext_fifo_adr(8) => rx_ext_fifo_adr(8),
      rx_ext_fifo_adr(7) => rx_ext_fifo_adr(7),
      rx_ext_fifo_adr(6) => rx_ext_fifo_adr(6),
      rx_ext_fifo_adr(5) => rx_ext_fifo_adr(5),
      rx_ext_fifo_adr(4) => rx_ext_fifo_adr(4),
      rx_ext_fifo_adr(3) => rx_ext_fifo_adr(3),
      rx_ext_fifo_adr(2) => rx_ext_fifo_adr(2),
      rx_ext_fifo_adr(1) => rx_ext_fifo_adr(1),
      rx_ext_fifo_adr(0) => rx_ext_fifo_adr(0)
    );
  ep : ctrl_pcie_x8
    port map (
      trn_rsrc_rdy_n => trn_rx_trn_rsrc_rdy_n,
      trn_terrfwd_n => trn_tx_trn_terrfwd_n,
      cfg_err_cpl_abort_n => cfg_err_cpl_timeout_n_c,
      trn_rerrfwd_n => trn_rx_trn_rerrfwd_n,
      cfg_err_cpl_unexpect_n => cfg_err_cpl_timeout_n_c,
      trn_rnp_ok_n => NLW_ep_trn_rnp_ok_n_UNCONNECTED,
      cfg_to_turnoff_n => NLW_ep_cfg_to_turnoff_n_UNCONNECTED,
      trn_tsrc_dsc_n => trn_tx_trn_tsrc_dsc_n,
      refclkout => NLW_ep_refclkout_UNCONNECTED,
      cfg_rd_en_n => cfg_err_cpl_timeout_n_c,
      cfg_err_ecrc_n => cfg_err_cpl_timeout_n_c,
      trn_tdst_rdy_n => trn_tx_back_trn_tdst_rdy_n,
      trn_rsof_n => trn_rx_trn_rsof_n,
      cfg_rd_wr_done_n => NLW_ep_cfg_rd_wr_done_n_UNCONNECTED,
      trn_teof_n => trn_tx_trn_teof_n,
      trn_rcpl_streaming_n => trn_rx_back_trn_rcpl_streaming_n,
      trn_clk => NlwRenamedSig_OI_clk_out,
      cfg_err_locked_n => cfg_err_cpl_timeout_n_c,
      cfg_trn_pending_n => cfg_err_cpl_timeout_n_c,
      trn_reset_n => trn_reset_n_c,
      trn_rsrc_dsc_n => trn_rx_trn_rsrc_dsc_n,
      fast_train_simulation_only => NLW_ep_fast_train_simulation_only_UNCONNECTED,
      cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n_c,
      cfg_interrupt_msienable => NLW_ep_cfg_interrupt_msienable_UNCONNECTED,
      trn_rdst_rdy_n => trn_rx_back_trn_rdst_rdy_n,
      trn_tsrc_rdy_n => trn_tx_trn_tsrc_rdy_n,
      cfg_err_ur_n => cfg_err_cpl_timeout_n_c,
      cfg_interrupt_n => cfg_interrupt_n_c,
      trn_tsof_n => trn_tx_trn_tsof_n,
      cfg_wr_en_n => cfg_err_cpl_timeout_n_c,
      cfg_pm_wake_n => cfg_err_cpl_timeout_n_c,
      cfg_interrupt_rdy_n => cfg_interrupt_rdy_n_c,
      trn_tdst_dsc_n => trn_tx_back_trn_tdst_dsc_n,
      cfg_err_posted_n => NLW_ep_cfg_err_posted_n_UNCONNECTED,
      cfg_err_cpl_rdy_n => NLW_ep_cfg_err_cpl_rdy_n_UNCONNECTED,
      sys_reset_n => perst,
      trn_reof_n => trn_rx_trn_reof_n,
      cfg_err_cor_n => cfg_err_cpl_timeout_n_c,
      sys_clk => mgt250,
      trn_lnk_up_n => pcie_link_up,
      cfg_interrupt_assert_n => cfg_interrupt_assert_n_c,
      cfg_device_number(4) => cfg_device_number_c(4),
      cfg_device_number(3) => cfg_device_number_c(3),
      cfg_device_number(2) => cfg_device_number_c(2),
      cfg_device_number(1) => cfg_device_number_c(1),
      cfg_device_number(0) => cfg_device_number_c(0),
      cfg_dstatus(15) => NLW_ep_cfg_dstatus_15_UNCONNECTED,
      cfg_dstatus(14) => NLW_ep_cfg_dstatus_14_UNCONNECTED,
      cfg_dstatus(13) => NLW_ep_cfg_dstatus_13_UNCONNECTED,
      cfg_dstatus(12) => NLW_ep_cfg_dstatus_12_UNCONNECTED,
      cfg_dstatus(11) => NLW_ep_cfg_dstatus_11_UNCONNECTED,
      cfg_dstatus(10) => NLW_ep_cfg_dstatus_10_UNCONNECTED,
      cfg_dstatus(9) => NLW_ep_cfg_dstatus_9_UNCONNECTED,
      cfg_dstatus(8) => NLW_ep_cfg_dstatus_8_UNCONNECTED,
      cfg_dstatus(7) => NLW_ep_cfg_dstatus_7_UNCONNECTED,
      cfg_dstatus(6) => NLW_ep_cfg_dstatus_6_UNCONNECTED,
      cfg_dstatus(5) => NLW_ep_cfg_dstatus_5_UNCONNECTED,
      cfg_dstatus(4) => NLW_ep_cfg_dstatus_4_UNCONNECTED,
      cfg_dstatus(3) => NLW_ep_cfg_dstatus_3_UNCONNECTED,
      cfg_dstatus(2) => NLW_ep_cfg_dstatus_2_UNCONNECTED,
      cfg_dstatus(1) => NLW_ep_cfg_dstatus_1_UNCONNECTED,
      cfg_dstatus(0) => NLW_ep_cfg_dstatus_0_UNCONNECTED,
      cfg_lcommand(15) => NLW_ep_cfg_lcommand_15_UNCONNECTED,
      cfg_lcommand(14) => NLW_ep_cfg_lcommand_14_UNCONNECTED,
      cfg_lcommand(13) => NLW_ep_cfg_lcommand_13_UNCONNECTED,
      cfg_lcommand(12) => NLW_ep_cfg_lcommand_12_UNCONNECTED,
      cfg_lcommand(11) => NLW_ep_cfg_lcommand_11_UNCONNECTED,
      cfg_lcommand(10) => NLW_ep_cfg_lcommand_10_UNCONNECTED,
      cfg_lcommand(9) => NLW_ep_cfg_lcommand_9_UNCONNECTED,
      cfg_lcommand(8) => NLW_ep_cfg_lcommand_8_UNCONNECTED,
      cfg_lcommand(7) => NLW_ep_cfg_lcommand_7_UNCONNECTED,
      cfg_lcommand(6) => NLW_ep_cfg_lcommand_6_UNCONNECTED,
      cfg_lcommand(5) => NLW_ep_cfg_lcommand_5_UNCONNECTED,
      cfg_lcommand(4) => NLW_ep_cfg_lcommand_4_UNCONNECTED,
      cfg_lcommand(3) => NLW_ep_cfg_lcommand_3_UNCONNECTED,
      cfg_lcommand(2) => NLW_ep_cfg_lcommand_2_UNCONNECTED,
      cfg_lcommand(1) => NLW_ep_cfg_lcommand_1_UNCONNECTED,
      cfg_lcommand(0) => NLW_ep_cfg_lcommand_0_UNCONNECTED,
      pci_exp_txn(7) => txn(7),
      pci_exp_txn(6) => txn(6),
      pci_exp_txn(5) => txn(5),
      pci_exp_txn(4) => txn(4),
      pci_exp_txn(3) => txn(3),
      pci_exp_txn(2) => txn(2),
      pci_exp_txn(1) => txn(1),
      pci_exp_txn(0) => txn(0),
      pci_exp_txp(7) => txp(7),
      pci_exp_txp(6) => txp(6),
      pci_exp_txp(5) => txp(5),
      pci_exp_txp(4) => txp(4),
      pci_exp_txp(3) => txp(3),
      pci_exp_txp(2) => txp(2),
      pci_exp_txp(1) => txp(1),
      pci_exp_txp(0) => txp(0),
      cfg_status(15) => NLW_ep_cfg_status_15_UNCONNECTED,
      cfg_status(14) => NLW_ep_cfg_status_14_UNCONNECTED,
      cfg_status(13) => NLW_ep_cfg_status_13_UNCONNECTED,
      cfg_status(12) => NLW_ep_cfg_status_12_UNCONNECTED,
      cfg_status(11) => NLW_ep_cfg_status_11_UNCONNECTED,
      cfg_status(10) => NLW_ep_cfg_status_10_UNCONNECTED,
      cfg_status(9) => NLW_ep_cfg_status_9_UNCONNECTED,
      cfg_status(8) => NLW_ep_cfg_status_8_UNCONNECTED,
      cfg_status(7) => NLW_ep_cfg_status_7_UNCONNECTED,
      cfg_status(6) => NLW_ep_cfg_status_6_UNCONNECTED,
      cfg_status(5) => NLW_ep_cfg_status_5_UNCONNECTED,
      cfg_status(4) => NLW_ep_cfg_status_4_UNCONNECTED,
      cfg_status(3) => NLW_ep_cfg_status_3_UNCONNECTED,
      cfg_status(2) => NLW_ep_cfg_status_2_UNCONNECTED,
      cfg_status(1) => NLW_ep_cfg_status_1_UNCONNECTED,
      cfg_status(0) => NLW_ep_cfg_status_0_UNCONNECTED,
      cfg_interrupt_do(7) => NLW_ep_cfg_interrupt_do_7_UNCONNECTED,
      cfg_interrupt_do(6) => NLW_ep_cfg_interrupt_do_6_UNCONNECTED,
      cfg_interrupt_do(5) => NLW_ep_cfg_interrupt_do_5_UNCONNECTED,
      cfg_interrupt_do(4) => NLW_ep_cfg_interrupt_do_4_UNCONNECTED,
      cfg_interrupt_do(3) => NLW_ep_cfg_interrupt_do_3_UNCONNECTED,
      cfg_interrupt_do(2) => NLW_ep_cfg_interrupt_do_2_UNCONNECTED,
      cfg_interrupt_do(1) => NLW_ep_cfg_interrupt_do_1_UNCONNECTED,
      cfg_interrupt_do(0) => NLW_ep_cfg_interrupt_do_0_UNCONNECTED,
      trn_rfc_nph_av(7) => trn_rx_trn_rfc_nph_av(7),
      trn_rfc_nph_av(6) => trn_rx_trn_rfc_nph_av(6),
      trn_rfc_nph_av(5) => trn_rx_trn_rfc_nph_av(5),
      trn_rfc_nph_av(4) => trn_rx_trn_rfc_nph_av(4),
      trn_rfc_nph_av(3) => trn_rx_trn_rfc_nph_av(3),
      trn_rfc_nph_av(2) => trn_rx_trn_rfc_nph_av(2),
      trn_rfc_nph_av(1) => trn_rx_trn_rfc_nph_av(1),
      trn_rfc_nph_av(0) => trn_rx_trn_rfc_nph_av(0),
      cfg_interrupt_mmenable(2) => NLW_ep_cfg_interrupt_mmenable_2_UNCONNECTED,
      cfg_interrupt_mmenable(1) => NLW_ep_cfg_interrupt_mmenable_1_UNCONNECTED,
      cfg_interrupt_mmenable(0) => NLW_ep_cfg_interrupt_mmenable_0_UNCONNECTED,
      trn_rfc_ph_av(7) => trn_rx_trn_rfc_ph_av(7),
      trn_rfc_ph_av(6) => trn_rx_trn_rfc_ph_av(6),
      trn_rfc_ph_av(5) => trn_rx_trn_rfc_ph_av(5),
      trn_rfc_ph_av(4) => trn_rx_trn_rfc_ph_av(4),
      trn_rfc_ph_av(3) => trn_rx_trn_rfc_ph_av(3),
      trn_rfc_ph_av(2) => trn_rx_trn_rfc_ph_av(2),
      trn_rfc_ph_av(1) => trn_rx_trn_rfc_ph_av(1),
      trn_rfc_ph_av(0) => trn_rx_trn_rfc_ph_av(0),
      trn_rrem_n(7) => trn_rx_trn_rrem_n(7),
      trn_rrem_n(6) => trn_rx_trn_rrem_n(6),
      trn_rrem_n(5) => trn_rx_trn_rrem_n(5),
      trn_rrem_n(4) => trn_rx_trn_rrem_n(4),
      trn_rrem_n(3) => trn_rx_trn_rrem_n(3),
      trn_rrem_n(2) => trn_rx_trn_rrem_n(2),
      trn_rrem_n(1) => trn_rx_trn_rrem_n(1),
      trn_rrem_n(0) => trn_rx_trn_rrem_n(0),
      cfg_bus_number(7) => cfg_bus_number_c(7),
      cfg_bus_number(6) => cfg_bus_number_c(6),
      cfg_bus_number(5) => cfg_bus_number_c(5),
      cfg_bus_number(4) => cfg_bus_number_c(4),
      cfg_bus_number(3) => cfg_bus_number_c(3),
      cfg_bus_number(2) => cfg_bus_number_c(2),
      cfg_bus_number(1) => cfg_bus_number_c(1),
      cfg_bus_number(0) => cfg_bus_number_c(0),
      trn_tbuf_av(3) => trn_tx_back_trn_tbuf_av(3),
      trn_tbuf_av(2) => trn_tx_back_trn_tbuf_av(2),
      trn_tbuf_av(1) => trn_tx_back_trn_tbuf_av(1),
      trn_tbuf_av(0) => trn_tx_back_trn_tbuf_av(0),
      cfg_command(15) => NLW_ep_cfg_command_15_UNCONNECTED,
      cfg_command(14) => NLW_ep_cfg_command_14_UNCONNECTED,
      cfg_command(13) => NLW_ep_cfg_command_13_UNCONNECTED,
      cfg_command(12) => NLW_ep_cfg_command_12_UNCONNECTED,
      cfg_command(11) => NLW_ep_cfg_command_11_UNCONNECTED,
      cfg_command(10) => cfg_command_c(10),
      cfg_command(9) => NLW_ep_cfg_command_9_UNCONNECTED,
      cfg_command(8) => NLW_ep_cfg_command_8_UNCONNECTED,
      cfg_command(7) => NLW_ep_cfg_command_7_UNCONNECTED,
      cfg_command(6) => NLW_ep_cfg_command_6_UNCONNECTED,
      cfg_command(5) => NLW_ep_cfg_command_5_UNCONNECTED,
      cfg_command(4) => NLW_ep_cfg_command_4_UNCONNECTED,
      cfg_command(3) => NLW_ep_cfg_command_3_UNCONNECTED,
      cfg_command(2) => NLW_ep_cfg_command_2_UNCONNECTED,
      cfg_command(1) => NLW_ep_cfg_command_1_UNCONNECTED,
      cfg_command(0) => NLW_ep_cfg_command_0_UNCONNECTED,
      cfg_lstatus(15) => pcie_lstatus(15),
      cfg_lstatus(14) => pcie_lstatus(14),
      cfg_lstatus(13) => pcie_lstatus(13),
      cfg_lstatus(12) => pcie_lstatus(12),
      cfg_lstatus(11) => pcie_lstatus(11),
      cfg_lstatus(10) => pcie_lstatus(10),
      cfg_lstatus(9) => pcie_lstatus(9),
      cfg_lstatus(8) => pcie_lstatus(8),
      cfg_lstatus(7) => pcie_lstatus(7),
      cfg_lstatus(6) => pcie_lstatus(6),
      cfg_lstatus(5) => pcie_lstatus(5),
      cfg_lstatus(4) => pcie_lstatus(4),
      cfg_lstatus(3) => pcie_lstatus(3),
      cfg_lstatus(2) => pcie_lstatus(2),
      cfg_lstatus(1) => pcie_lstatus(1),
      cfg_lstatus(0) => pcie_lstatus(0),
      trn_rbar_hit_n(6) => trn_rx_trn_rbar_hit_n(6),
      trn_rbar_hit_n(5) => trn_rx_trn_rbar_hit_n(5),
      trn_rbar_hit_n(4) => trn_rx_trn_rbar_hit_n(4),
      trn_rbar_hit_n(3) => trn_rx_trn_rbar_hit_n(3),
      trn_rbar_hit_n(2) => trn_rx_trn_rbar_hit_n(2),
      trn_rbar_hit_n(1) => trn_rx_trn_rbar_hit_n(1),
      trn_rbar_hit_n(0) => trn_rx_trn_rbar_hit_n(0),
      trn_rfc_npd_av(11) => trn_rx_trn_rfc_npd_av(11),
      trn_rfc_npd_av(10) => trn_rx_trn_rfc_npd_av(10),
      trn_rfc_npd_av(9) => trn_rx_trn_rfc_npd_av(9),
      trn_rfc_npd_av(8) => trn_rx_trn_rfc_npd_av(8),
      trn_rfc_npd_av(7) => trn_rx_trn_rfc_npd_av(7),
      trn_rfc_npd_av(6) => trn_rx_trn_rfc_npd_av(6),
      trn_rfc_npd_av(5) => trn_rx_trn_rfc_npd_av(5),
      trn_rfc_npd_av(4) => trn_rx_trn_rfc_npd_av(4),
      trn_rfc_npd_av(3) => trn_rx_trn_rfc_npd_av(3),
      trn_rfc_npd_av(2) => trn_rx_trn_rfc_npd_av(2),
      trn_rfc_npd_av(1) => trn_rx_trn_rfc_npd_av(1),
      trn_rfc_npd_av(0) => trn_rx_trn_rfc_npd_av(0),
      cfg_dcommand(15) => trn_tx_back_cfg_dcommand(15),
      cfg_dcommand(14) => trn_tx_back_cfg_dcommand(14),
      cfg_dcommand(13) => trn_tx_back_cfg_dcommand(13),
      cfg_dcommand(12) => trn_tx_back_cfg_dcommand(12),
      cfg_dcommand(11) => trn_tx_back_cfg_dcommand(11),
      cfg_dcommand(10) => trn_tx_back_cfg_dcommand(10),
      cfg_dcommand(9) => trn_tx_back_cfg_dcommand(9),
      cfg_dcommand(8) => trn_tx_back_cfg_dcommand(8),
      cfg_dcommand(7) => trn_tx_back_cfg_dcommand(7),
      cfg_dcommand(6) => trn_tx_back_cfg_dcommand(6),
      cfg_dcommand(5) => trn_tx_back_cfg_dcommand(5),
      cfg_dcommand(4) => trn_tx_back_cfg_dcommand(4),
      cfg_dcommand(3) => trn_tx_back_cfg_dcommand(3),
      cfg_dcommand(2) => trn_tx_back_cfg_dcommand(2),
      cfg_dcommand(1) => trn_tx_back_cfg_dcommand(1),
      cfg_dcommand(0) => trn_tx_back_cfg_dcommand(0),
      cfg_pcie_link_state_n(2) => NLW_ep_cfg_pcie_link_state_n_2_UNCONNECTED,
      cfg_pcie_link_state_n(1) => NLW_ep_cfg_pcie_link_state_n_1_UNCONNECTED,
      cfg_pcie_link_state_n(0) => NLW_ep_cfg_pcie_link_state_n_0_UNCONNECTED,
      trn_rfc_pd_av(11) => trn_rx_trn_rfc_pd_av(11),
      trn_rfc_pd_av(10) => trn_rx_trn_rfc_pd_av(10),
      trn_rfc_pd_av(9) => trn_rx_trn_rfc_pd_av(9),
      trn_rfc_pd_av(8) => trn_rx_trn_rfc_pd_av(8),
      trn_rfc_pd_av(7) => trn_rx_trn_rfc_pd_av(7),
      trn_rfc_pd_av(6) => trn_rx_trn_rfc_pd_av(6),
      trn_rfc_pd_av(5) => trn_rx_trn_rfc_pd_av(5),
      trn_rfc_pd_av(4) => trn_rx_trn_rfc_pd_av(4),
      trn_rfc_pd_av(3) => trn_rx_trn_rfc_pd_av(3),
      trn_rfc_pd_av(2) => trn_rx_trn_rfc_pd_av(2),
      trn_rfc_pd_av(1) => trn_rx_trn_rfc_pd_av(1),
      trn_rfc_pd_av(0) => trn_rx_trn_rfc_pd_av(0),
      cfg_function_number(2) => cfg_function_number_c(2),
      cfg_function_number(1) => cfg_function_number_c(1),
      cfg_function_number(0) => cfg_function_number_c(0),
      trn_rd(63) => trn_rx_trn_rd(63),
      trn_rd(62) => trn_rx_trn_rd(62),
      trn_rd(61) => trn_rx_trn_rd(61),
      trn_rd(60) => trn_rx_trn_rd(60),
      trn_rd(59) => trn_rx_trn_rd(59),
      trn_rd(58) => trn_rx_trn_rd(58),
      trn_rd(57) => trn_rx_trn_rd(57),
      trn_rd(56) => trn_rx_trn_rd(56),
      trn_rd(55) => trn_rx_trn_rd(55),
      trn_rd(54) => trn_rx_trn_rd(54),
      trn_rd(53) => trn_rx_trn_rd(53),
      trn_rd(52) => trn_rx_trn_rd(52),
      trn_rd(51) => trn_rx_trn_rd(51),
      trn_rd(50) => trn_rx_trn_rd(50),
      trn_rd(49) => trn_rx_trn_rd(49),
      trn_rd(48) => trn_rx_trn_rd(48),
      trn_rd(47) => trn_rx_trn_rd(47),
      trn_rd(46) => trn_rx_trn_rd(46),
      trn_rd(45) => trn_rx_trn_rd(45),
      trn_rd(44) => trn_rx_trn_rd(44),
      trn_rd(43) => trn_rx_trn_rd(43),
      trn_rd(42) => trn_rx_trn_rd(42),
      trn_rd(41) => trn_rx_trn_rd(41),
      trn_rd(40) => trn_rx_trn_rd(40),
      trn_rd(39) => trn_rx_trn_rd(39),
      trn_rd(38) => trn_rx_trn_rd(38),
      trn_rd(37) => trn_rx_trn_rd(37),
      trn_rd(36) => trn_rx_trn_rd(36),
      trn_rd(35) => trn_rx_trn_rd(35),
      trn_rd(34) => trn_rx_trn_rd(34),
      trn_rd(33) => trn_rx_trn_rd(33),
      trn_rd(32) => trn_rx_trn_rd(32),
      trn_rd(31) => trn_rx_trn_rd(31),
      trn_rd(30) => trn_rx_trn_rd(30),
      trn_rd(29) => trn_rx_trn_rd(29),
      trn_rd(28) => trn_rx_trn_rd(28),
      trn_rd(27) => trn_rx_trn_rd(27),
      trn_rd(26) => trn_rx_trn_rd(26),
      trn_rd(25) => trn_rx_trn_rd(25),
      trn_rd(24) => trn_rx_trn_rd(24),
      trn_rd(23) => trn_rx_trn_rd(23),
      trn_rd(22) => trn_rx_trn_rd(22),
      trn_rd(21) => trn_rx_trn_rd(21),
      trn_rd(20) => trn_rx_trn_rd(20),
      trn_rd(19) => trn_rx_trn_rd(19),
      trn_rd(18) => trn_rx_trn_rd(18),
      trn_rd(17) => trn_rx_trn_rd(17),
      trn_rd(16) => trn_rx_trn_rd(16),
      trn_rd(15) => trn_rx_trn_rd(15),
      trn_rd(14) => trn_rx_trn_rd(14),
      trn_rd(13) => trn_rx_trn_rd(13),
      trn_rd(12) => trn_rx_trn_rd(12),
      trn_rd(11) => trn_rx_trn_rd(11),
      trn_rd(10) => trn_rx_trn_rd(10),
      trn_rd(9) => trn_rx_trn_rd(9),
      trn_rd(8) => trn_rx_trn_rd(8),
      trn_rd(7) => trn_rx_trn_rd(7),
      trn_rd(6) => trn_rx_trn_rd(6),
      trn_rd(5) => trn_rx_trn_rd(5),
      trn_rd(4) => trn_rx_trn_rd(4),
      trn_rd(3) => trn_rx_trn_rd(3),
      trn_rd(2) => trn_rx_trn_rd(2),
      trn_rd(1) => trn_rx_trn_rd(1),
      trn_rd(0) => trn_rx_trn_rd(0),
      cfg_do(31) => NLW_ep_cfg_do_31_UNCONNECTED,
      cfg_do(30) => NLW_ep_cfg_do_30_UNCONNECTED,
      cfg_do(29) => NLW_ep_cfg_do_29_UNCONNECTED,
      cfg_do(28) => NLW_ep_cfg_do_28_UNCONNECTED,
      cfg_do(27) => NLW_ep_cfg_do_27_UNCONNECTED,
      cfg_do(26) => NLW_ep_cfg_do_26_UNCONNECTED,
      cfg_do(25) => NLW_ep_cfg_do_25_UNCONNECTED,
      cfg_do(24) => NLW_ep_cfg_do_24_UNCONNECTED,
      cfg_do(23) => NLW_ep_cfg_do_23_UNCONNECTED,
      cfg_do(22) => NLW_ep_cfg_do_22_UNCONNECTED,
      cfg_do(21) => NLW_ep_cfg_do_21_UNCONNECTED,
      cfg_do(20) => NLW_ep_cfg_do_20_UNCONNECTED,
      cfg_do(19) => NLW_ep_cfg_do_19_UNCONNECTED,
      cfg_do(18) => NLW_ep_cfg_do_18_UNCONNECTED,
      cfg_do(17) => NLW_ep_cfg_do_17_UNCONNECTED,
      cfg_do(16) => NLW_ep_cfg_do_16_UNCONNECTED,
      cfg_do(15) => NLW_ep_cfg_do_15_UNCONNECTED,
      cfg_do(14) => NLW_ep_cfg_do_14_UNCONNECTED,
      cfg_do(13) => NLW_ep_cfg_do_13_UNCONNECTED,
      cfg_do(12) => NLW_ep_cfg_do_12_UNCONNECTED,
      cfg_do(11) => NLW_ep_cfg_do_11_UNCONNECTED,
      cfg_do(10) => NLW_ep_cfg_do_10_UNCONNECTED,
      cfg_do(9) => NLW_ep_cfg_do_9_UNCONNECTED,
      cfg_do(8) => NLW_ep_cfg_do_8_UNCONNECTED,
      cfg_do(7) => NLW_ep_cfg_do_7_UNCONNECTED,
      cfg_do(6) => NLW_ep_cfg_do_6_UNCONNECTED,
      cfg_do(5) => NLW_ep_cfg_do_5_UNCONNECTED,
      cfg_do(4) => NLW_ep_cfg_do_4_UNCONNECTED,
      cfg_do(3) => NLW_ep_cfg_do_3_UNCONNECTED,
      cfg_do(2) => NLW_ep_cfg_do_2_UNCONNECTED,
      cfg_do(1) => NLW_ep_cfg_do_1_UNCONNECTED,
      cfg_do(0) => NLW_ep_cfg_do_0_UNCONNECTED,
      trn_td(63) => trn_tx_trn_td(63),
      trn_td(62) => trn_tx_trn_td(62),
      trn_td(61) => trn_tx_trn_td(61),
      trn_td(60) => trn_tx_trn_td(60),
      trn_td(59) => trn_tx_trn_td(59),
      trn_td(58) => trn_tx_trn_td(58),
      trn_td(57) => trn_tx_trn_td(57),
      trn_td(56) => trn_tx_trn_td(56),
      trn_td(55) => trn_tx_trn_td(55),
      trn_td(54) => trn_tx_trn_td(54),
      trn_td(53) => trn_tx_trn_td(53),
      trn_td(52) => trn_tx_trn_td(52),
      trn_td(51) => trn_tx_trn_td(51),
      trn_td(50) => trn_tx_trn_td(50),
      trn_td(49) => trn_tx_trn_td(49),
      trn_td(48) => trn_tx_trn_td(48),
      trn_td(47) => trn_tx_trn_td(47),
      trn_td(46) => trn_tx_trn_td(46),
      trn_td(45) => trn_tx_trn_td(45),
      trn_td(44) => trn_tx_trn_td(44),
      trn_td(43) => trn_tx_trn_td(43),
      trn_td(42) => trn_tx_trn_td(42),
      trn_td(41) => trn_tx_trn_td(41),
      trn_td(40) => trn_tx_trn_td(40),
      trn_td(39) => trn_tx_trn_td(39),
      trn_td(38) => trn_tx_trn_td(38),
      trn_td(37) => trn_tx_trn_td(37),
      trn_td(36) => trn_tx_trn_td(36),
      trn_td(35) => trn_tx_trn_td(35),
      trn_td(34) => trn_tx_trn_td(34),
      trn_td(33) => trn_tx_trn_td(33),
      trn_td(32) => trn_tx_trn_td(32),
      trn_td(31) => trn_tx_trn_td(31),
      trn_td(30) => trn_tx_trn_td(30),
      trn_td(29) => trn_tx_trn_td(29),
      trn_td(28) => trn_tx_trn_td(28),
      trn_td(27) => trn_tx_trn_td(27),
      trn_td(26) => trn_tx_trn_td(26),
      trn_td(25) => trn_tx_trn_td(25),
      trn_td(24) => trn_tx_trn_td(24),
      trn_td(23) => trn_tx_trn_td(23),
      trn_td(22) => trn_tx_trn_td(22),
      trn_td(21) => trn_tx_trn_td(21),
      trn_td(20) => trn_tx_trn_td(20),
      trn_td(19) => trn_tx_trn_td(19),
      trn_td(18) => trn_tx_trn_td(18),
      trn_td(17) => trn_tx_trn_td(17),
      trn_td(16) => trn_tx_trn_td(16),
      trn_td(15) => trn_tx_trn_td(15),
      trn_td(14) => trn_tx_trn_td(14),
      trn_td(13) => trn_tx_trn_td(13),
      trn_td(12) => trn_tx_trn_td(12),
      trn_td(11) => trn_tx_trn_td(11),
      trn_td(10) => trn_tx_trn_td(10),
      trn_td(9) => trn_tx_trn_td(9),
      trn_td(8) => trn_tx_trn_td(8),
      trn_td(7) => trn_tx_trn_td(7),
      trn_td(6) => trn_tx_trn_td(6),
      trn_td(5) => trn_tx_trn_td(5),
      trn_td(4) => trn_tx_trn_td(4),
      trn_td(3) => trn_tx_trn_td(3),
      trn_td(2) => trn_tx_trn_td(2),
      trn_td(1) => trn_tx_trn_td(1),
      trn_td(0) => trn_tx_trn_td(0),
      cfg_byte_en_n(3) => cfg_err_cpl_timeout_n_c,
      cfg_byte_en_n(2) => cfg_err_cpl_timeout_n_c,
      cfg_byte_en_n(1) => cfg_err_cpl_timeout_n_c,
      cfg_byte_en_n(0) => cfg_err_cpl_timeout_n_c,
      cfg_interrupt_di(7) => NLW_ep_cfg_interrupt_di_7_UNCONNECTED,
      cfg_interrupt_di(6) => NLW_ep_cfg_interrupt_di_6_UNCONNECTED,
      cfg_interrupt_di(5) => NLW_ep_cfg_interrupt_di_5_UNCONNECTED,
      cfg_interrupt_di(4) => NLW_ep_cfg_interrupt_di_4_UNCONNECTED,
      cfg_interrupt_di(3) => NLW_ep_cfg_interrupt_di_3_UNCONNECTED,
      cfg_interrupt_di(2) => NLW_ep_cfg_interrupt_di_2_UNCONNECTED,
      cfg_interrupt_di(1) => NLW_ep_cfg_interrupt_di_1_UNCONNECTED,
      cfg_interrupt_di(0) => NLW_ep_cfg_interrupt_di_0_UNCONNECTED,
      cfg_dsn(63) => NLW_ep_cfg_dsn_63_UNCONNECTED,
      cfg_dsn(62) => NLW_ep_cfg_dsn_62_UNCONNECTED,
      cfg_dsn(61) => NLW_ep_cfg_dsn_61_UNCONNECTED,
      cfg_dsn(60) => NLW_ep_cfg_dsn_60_UNCONNECTED,
      cfg_dsn(59) => NLW_ep_cfg_dsn_59_UNCONNECTED,
      cfg_dsn(58) => NLW_ep_cfg_dsn_58_UNCONNECTED,
      cfg_dsn(57) => NLW_ep_cfg_dsn_57_UNCONNECTED,
      cfg_dsn(56) => NLW_ep_cfg_dsn_56_UNCONNECTED,
      cfg_dsn(55) => NLW_ep_cfg_dsn_55_UNCONNECTED,
      cfg_dsn(54) => NLW_ep_cfg_dsn_54_UNCONNECTED,
      cfg_dsn(53) => NLW_ep_cfg_dsn_53_UNCONNECTED,
      cfg_dsn(52) => NLW_ep_cfg_dsn_52_UNCONNECTED,
      cfg_dsn(51) => NLW_ep_cfg_dsn_51_UNCONNECTED,
      cfg_dsn(50) => NLW_ep_cfg_dsn_50_UNCONNECTED,
      cfg_dsn(49) => NLW_ep_cfg_dsn_49_UNCONNECTED,
      cfg_dsn(48) => NLW_ep_cfg_dsn_48_UNCONNECTED,
      cfg_dsn(47) => NLW_ep_cfg_dsn_47_UNCONNECTED,
      cfg_dsn(46) => NLW_ep_cfg_dsn_46_UNCONNECTED,
      cfg_dsn(45) => NLW_ep_cfg_dsn_45_UNCONNECTED,
      cfg_dsn(44) => NLW_ep_cfg_dsn_44_UNCONNECTED,
      cfg_dsn(43) => NLW_ep_cfg_dsn_43_UNCONNECTED,
      cfg_dsn(42) => NLW_ep_cfg_dsn_42_UNCONNECTED,
      cfg_dsn(41) => NLW_ep_cfg_dsn_41_UNCONNECTED,
      cfg_dsn(40) => NLW_ep_cfg_dsn_40_UNCONNECTED,
      cfg_dsn(39) => NLW_ep_cfg_dsn_39_UNCONNECTED,
      cfg_dsn(38) => NLW_ep_cfg_dsn_38_UNCONNECTED,
      cfg_dsn(37) => NLW_ep_cfg_dsn_37_UNCONNECTED,
      cfg_dsn(36) => NLW_ep_cfg_dsn_36_UNCONNECTED,
      cfg_dsn(35) => NLW_ep_cfg_dsn_35_UNCONNECTED,
      cfg_dsn(34) => NLW_ep_cfg_dsn_34_UNCONNECTED,
      cfg_dsn(33) => NLW_ep_cfg_dsn_33_UNCONNECTED,
      cfg_dsn(32) => NLW_ep_cfg_dsn_32_UNCONNECTED,
      cfg_dsn(31) => NLW_ep_cfg_dsn_31_UNCONNECTED,
      cfg_dsn(30) => NLW_ep_cfg_dsn_30_UNCONNECTED,
      cfg_dsn(29) => NLW_ep_cfg_dsn_29_UNCONNECTED,
      cfg_dsn(28) => NLW_ep_cfg_dsn_28_UNCONNECTED,
      cfg_dsn(27) => NLW_ep_cfg_dsn_27_UNCONNECTED,
      cfg_dsn(26) => NLW_ep_cfg_dsn_26_UNCONNECTED,
      cfg_dsn(25) => NLW_ep_cfg_dsn_25_UNCONNECTED,
      cfg_dsn(24) => NLW_ep_cfg_dsn_24_UNCONNECTED,
      cfg_dsn(23) => NLW_ep_cfg_dsn_23_UNCONNECTED,
      cfg_dsn(22) => NLW_ep_cfg_dsn_22_UNCONNECTED,
      cfg_dsn(21) => NLW_ep_cfg_dsn_21_UNCONNECTED,
      cfg_dsn(20) => NLW_ep_cfg_dsn_20_UNCONNECTED,
      cfg_dsn(19) => NLW_ep_cfg_dsn_19_UNCONNECTED,
      cfg_dsn(18) => NLW_ep_cfg_dsn_18_UNCONNECTED,
      cfg_dsn(17) => NLW_ep_cfg_dsn_17_UNCONNECTED,
      cfg_dsn(16) => NLW_ep_cfg_dsn_16_UNCONNECTED,
      cfg_dsn(15) => NLW_ep_cfg_dsn_15_UNCONNECTED,
      cfg_dsn(14) => NLW_ep_cfg_dsn_14_UNCONNECTED,
      cfg_dsn(13) => NLW_ep_cfg_dsn_13_UNCONNECTED,
      cfg_dsn(12) => NLW_ep_cfg_dsn_12_UNCONNECTED,
      cfg_dsn(11) => NLW_ep_cfg_dsn_11_UNCONNECTED,
      cfg_dsn(10) => NLW_ep_cfg_dsn_10_UNCONNECTED,
      cfg_dsn(9) => NLW_ep_cfg_dsn_9_UNCONNECTED,
      cfg_dsn(8) => NLW_ep_cfg_dsn_8_UNCONNECTED,
      cfg_dsn(7) => NLW_ep_cfg_dsn_7_UNCONNECTED,
      cfg_dsn(6) => NLW_ep_cfg_dsn_6_UNCONNECTED,
      cfg_dsn(5) => NLW_ep_cfg_dsn_5_UNCONNECTED,
      cfg_dsn(4) => NLW_ep_cfg_dsn_4_UNCONNECTED,
      cfg_dsn(3) => NLW_ep_cfg_dsn_3_UNCONNECTED,
      cfg_dsn(2) => NLW_ep_cfg_dsn_2_UNCONNECTED,
      cfg_dsn(1) => NLW_ep_cfg_dsn_1_UNCONNECTED,
      cfg_dsn(0) => NLW_ep_cfg_dsn_0_UNCONNECTED,
      cfg_err_tlp_cpl_header(47) => NLW_ep_cfg_err_tlp_cpl_header_47_UNCONNECTED,
      cfg_err_tlp_cpl_header(46) => NLW_ep_cfg_err_tlp_cpl_header_46_UNCONNECTED,
      cfg_err_tlp_cpl_header(45) => NLW_ep_cfg_err_tlp_cpl_header_45_UNCONNECTED,
      cfg_err_tlp_cpl_header(44) => NLW_ep_cfg_err_tlp_cpl_header_44_UNCONNECTED,
      cfg_err_tlp_cpl_header(43) => NLW_ep_cfg_err_tlp_cpl_header_43_UNCONNECTED,
      cfg_err_tlp_cpl_header(42) => NLW_ep_cfg_err_tlp_cpl_header_42_UNCONNECTED,
      cfg_err_tlp_cpl_header(41) => NLW_ep_cfg_err_tlp_cpl_header_41_UNCONNECTED,
      cfg_err_tlp_cpl_header(40) => NLW_ep_cfg_err_tlp_cpl_header_40_UNCONNECTED,
      cfg_err_tlp_cpl_header(39) => NLW_ep_cfg_err_tlp_cpl_header_39_UNCONNECTED,
      cfg_err_tlp_cpl_header(38) => NLW_ep_cfg_err_tlp_cpl_header_38_UNCONNECTED,
      cfg_err_tlp_cpl_header(37) => NLW_ep_cfg_err_tlp_cpl_header_37_UNCONNECTED,
      cfg_err_tlp_cpl_header(36) => NLW_ep_cfg_err_tlp_cpl_header_36_UNCONNECTED,
      cfg_err_tlp_cpl_header(35) => NLW_ep_cfg_err_tlp_cpl_header_35_UNCONNECTED,
      cfg_err_tlp_cpl_header(34) => NLW_ep_cfg_err_tlp_cpl_header_34_UNCONNECTED,
      cfg_err_tlp_cpl_header(33) => NLW_ep_cfg_err_tlp_cpl_header_33_UNCONNECTED,
      cfg_err_tlp_cpl_header(32) => NLW_ep_cfg_err_tlp_cpl_header_32_UNCONNECTED,
      cfg_err_tlp_cpl_header(31) => NLW_ep_cfg_err_tlp_cpl_header_31_UNCONNECTED,
      cfg_err_tlp_cpl_header(30) => NLW_ep_cfg_err_tlp_cpl_header_30_UNCONNECTED,
      cfg_err_tlp_cpl_header(29) => NLW_ep_cfg_err_tlp_cpl_header_29_UNCONNECTED,
      cfg_err_tlp_cpl_header(28) => NLW_ep_cfg_err_tlp_cpl_header_28_UNCONNECTED,
      cfg_err_tlp_cpl_header(27) => NLW_ep_cfg_err_tlp_cpl_header_27_UNCONNECTED,
      cfg_err_tlp_cpl_header(26) => NLW_ep_cfg_err_tlp_cpl_header_26_UNCONNECTED,
      cfg_err_tlp_cpl_header(25) => NLW_ep_cfg_err_tlp_cpl_header_25_UNCONNECTED,
      cfg_err_tlp_cpl_header(24) => NLW_ep_cfg_err_tlp_cpl_header_24_UNCONNECTED,
      cfg_err_tlp_cpl_header(23) => NLW_ep_cfg_err_tlp_cpl_header_23_UNCONNECTED,
      cfg_err_tlp_cpl_header(22) => NLW_ep_cfg_err_tlp_cpl_header_22_UNCONNECTED,
      cfg_err_tlp_cpl_header(21) => NLW_ep_cfg_err_tlp_cpl_header_21_UNCONNECTED,
      cfg_err_tlp_cpl_header(20) => NLW_ep_cfg_err_tlp_cpl_header_20_UNCONNECTED,
      cfg_err_tlp_cpl_header(19) => NLW_ep_cfg_err_tlp_cpl_header_19_UNCONNECTED,
      cfg_err_tlp_cpl_header(18) => NLW_ep_cfg_err_tlp_cpl_header_18_UNCONNECTED,
      cfg_err_tlp_cpl_header(17) => NLW_ep_cfg_err_tlp_cpl_header_17_UNCONNECTED,
      cfg_err_tlp_cpl_header(16) => NLW_ep_cfg_err_tlp_cpl_header_16_UNCONNECTED,
      cfg_err_tlp_cpl_header(15) => NLW_ep_cfg_err_tlp_cpl_header_15_UNCONNECTED,
      cfg_err_tlp_cpl_header(14) => NLW_ep_cfg_err_tlp_cpl_header_14_UNCONNECTED,
      cfg_err_tlp_cpl_header(13) => NLW_ep_cfg_err_tlp_cpl_header_13_UNCONNECTED,
      cfg_err_tlp_cpl_header(12) => NLW_ep_cfg_err_tlp_cpl_header_12_UNCONNECTED,
      cfg_err_tlp_cpl_header(11) => NLW_ep_cfg_err_tlp_cpl_header_11_UNCONNECTED,
      cfg_err_tlp_cpl_header(10) => NLW_ep_cfg_err_tlp_cpl_header_10_UNCONNECTED,
      cfg_err_tlp_cpl_header(9) => NLW_ep_cfg_err_tlp_cpl_header_9_UNCONNECTED,
      cfg_err_tlp_cpl_header(8) => NLW_ep_cfg_err_tlp_cpl_header_8_UNCONNECTED,
      cfg_err_tlp_cpl_header(7) => NLW_ep_cfg_err_tlp_cpl_header_7_UNCONNECTED,
      cfg_err_tlp_cpl_header(6) => NLW_ep_cfg_err_tlp_cpl_header_6_UNCONNECTED,
      cfg_err_tlp_cpl_header(5) => NLW_ep_cfg_err_tlp_cpl_header_5_UNCONNECTED,
      cfg_err_tlp_cpl_header(4) => NLW_ep_cfg_err_tlp_cpl_header_4_UNCONNECTED,
      cfg_err_tlp_cpl_header(3) => NLW_ep_cfg_err_tlp_cpl_header_3_UNCONNECTED,
      cfg_err_tlp_cpl_header(2) => NLW_ep_cfg_err_tlp_cpl_header_2_UNCONNECTED,
      cfg_err_tlp_cpl_header(1) => NLW_ep_cfg_err_tlp_cpl_header_1_UNCONNECTED,
      cfg_err_tlp_cpl_header(0) => NLW_ep_cfg_err_tlp_cpl_header_0_UNCONNECTED,
      cfg_dwaddr(9) => NLW_ep_cfg_dwaddr_9_UNCONNECTED,
      cfg_dwaddr(8) => NLW_ep_cfg_dwaddr_8_UNCONNECTED,
      cfg_dwaddr(7) => NLW_ep_cfg_dwaddr_7_UNCONNECTED,
      cfg_dwaddr(6) => NLW_ep_cfg_dwaddr_6_UNCONNECTED,
      cfg_dwaddr(5) => NLW_ep_cfg_dwaddr_5_UNCONNECTED,
      cfg_dwaddr(4) => NLW_ep_cfg_dwaddr_4_UNCONNECTED,
      cfg_dwaddr(3) => NLW_ep_cfg_dwaddr_3_UNCONNECTED,
      cfg_dwaddr(2) => NLW_ep_cfg_dwaddr_2_UNCONNECTED,
      cfg_dwaddr(1) => NLW_ep_cfg_dwaddr_1_UNCONNECTED,
      cfg_dwaddr(0) => NLW_ep_cfg_dwaddr_0_UNCONNECTED,
      trn_trem_n(7) => trn_tx_trn_trem_n(7),
      trn_trem_n(6) => trn_tx_trn_trem_n(6),
      trn_trem_n(5) => trn_tx_trn_trem_n(5),
      trn_trem_n(4) => trn_tx_trn_trem_n(4),
      trn_trem_n(3) => trn_tx_trn_trem_n(3),
      trn_trem_n(2) => trn_tx_trn_trem_n(2),
      trn_trem_n(1) => trn_tx_trn_trem_n(1),
      trn_trem_n(0) => trn_tx_trn_trem_n(0),
      pci_exp_rxn(7) => rxn(7),
      pci_exp_rxn(6) => rxn(6),
      pci_exp_rxn(5) => rxn(5),
      pci_exp_rxn(4) => rxn(4),
      pci_exp_rxn(3) => rxn(3),
      pci_exp_rxn(2) => rxn(2),
      pci_exp_rxn(1) => rxn(1),
      pci_exp_rxn(0) => rxn(0),
      pci_exp_rxp(7) => rxp(7),
      pci_exp_rxp(6) => rxp(6),
      pci_exp_rxp(5) => rxp(5),
      pci_exp_rxp(4) => rxp(4),
      pci_exp_rxp(3) => rxp(3),
      pci_exp_rxp(2) => rxp(2),
      pci_exp_rxp(1) => rxp(1),
      pci_exp_rxp(0) => rxp(0),
      cfg_di(31) => NLW_ep_cfg_di_31_UNCONNECTED,
      cfg_di(30) => NLW_ep_cfg_di_30_UNCONNECTED,
      cfg_di(29) => NLW_ep_cfg_di_29_UNCONNECTED,
      cfg_di(28) => NLW_ep_cfg_di_28_UNCONNECTED,
      cfg_di(27) => NLW_ep_cfg_di_27_UNCONNECTED,
      cfg_di(26) => NLW_ep_cfg_di_26_UNCONNECTED,
      cfg_di(25) => NLW_ep_cfg_di_25_UNCONNECTED,
      cfg_di(24) => NLW_ep_cfg_di_24_UNCONNECTED,
      cfg_di(23) => NLW_ep_cfg_di_23_UNCONNECTED,
      cfg_di(22) => NLW_ep_cfg_di_22_UNCONNECTED,
      cfg_di(21) => NLW_ep_cfg_di_21_UNCONNECTED,
      cfg_di(20) => NLW_ep_cfg_di_20_UNCONNECTED,
      cfg_di(19) => NLW_ep_cfg_di_19_UNCONNECTED,
      cfg_di(18) => NLW_ep_cfg_di_18_UNCONNECTED,
      cfg_di(17) => NLW_ep_cfg_di_17_UNCONNECTED,
      cfg_di(16) => NLW_ep_cfg_di_16_UNCONNECTED,
      cfg_di(15) => NLW_ep_cfg_di_15_UNCONNECTED,
      cfg_di(14) => NLW_ep_cfg_di_14_UNCONNECTED,
      cfg_di(13) => NLW_ep_cfg_di_13_UNCONNECTED,
      cfg_di(12) => NLW_ep_cfg_di_12_UNCONNECTED,
      cfg_di(11) => NLW_ep_cfg_di_11_UNCONNECTED,
      cfg_di(10) => NLW_ep_cfg_di_10_UNCONNECTED,
      cfg_di(9) => NLW_ep_cfg_di_9_UNCONNECTED,
      cfg_di(8) => NLW_ep_cfg_di_8_UNCONNECTED,
      cfg_di(7) => NLW_ep_cfg_di_7_UNCONNECTED,
      cfg_di(6) => NLW_ep_cfg_di_6_UNCONNECTED,
      cfg_di(5) => NLW_ep_cfg_di_5_UNCONNECTED,
      cfg_di(4) => NLW_ep_cfg_di_4_UNCONNECTED,
      cfg_di(3) => NLW_ep_cfg_di_3_UNCONNECTED,
      cfg_di(2) => NLW_ep_cfg_di_2_UNCONNECTED,
      cfg_di(1) => NLW_ep_cfg_di_1_UNCONNECTED,
      cfg_di(0) => NLW_ep_cfg_di_0_UNCONNECTED
    );
  dcm_rstp1_INV_0 : INV
    port map (
      I => trn_reset_n_c,
      O => dcm_rstp
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_ram16_v1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    data_we : in STD_LOGIC := 'X'; 
    data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_ram16_v1;

architecture STRUCTURE of ctrl_ram16_v1 is
  signal wr : STD_LOGIC; 
  signal NLW_xram0_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram1_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram2_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram3_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram4_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram5_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram6_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram7_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram8_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram9_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram10_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram11_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram12_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram13_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram14_DPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_xram15_DPO_UNCONNECTED : STD_LOGIC; 
begin
  xram0 : RAM16X1D
    generic map(
      INIT => X"0003"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(0),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(0),
      DPO => NLW_xram0_DPO_UNCONNECTED
    );
  xram1 : RAM16X1D
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(1),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(1),
      DPO => NLW_xram1_DPO_UNCONNECTED
    );
  xram2 : RAM16X1D
    generic map(
      INIT => X"0014"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(2),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(2),
      DPO => NLW_xram2_DPO_UNCONNECTED
    );
  xram3 : RAM16X1D
    generic map(
      INIT => X"0020"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(3),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(3),
      DPO => NLW_xram3_DPO_UNCONNECTED
    );
  xram4 : RAM16X1D
    generic map(
      INIT => X"0009"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(4),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(4),
      DPO => NLW_xram4_DPO_UNCONNECTED
    );
  xram5 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(5),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(5),
      DPO => NLW_xram5_DPO_UNCONNECTED
    );
  xram6 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(6),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(6),
      DPO => NLW_xram6_DPO_UNCONNECTED
    );
  xram7 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(7),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(7),
      DPO => NLW_xram7_DPO_UNCONNECTED
    );
  xram8 : RAM16X1D
    generic map(
      INIT => X"0016"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(8),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(8),
      DPO => NLW_xram8_DPO_UNCONNECTED
    );
  xram9 : RAM16X1D
    generic map(
      INIT => X"0008"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(9),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(9),
      DPO => NLW_xram9_DPO_UNCONNECTED
    );
  xram10 : RAM16X1D
    generic map(
      INIT => X"0004"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(10),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(10),
      DPO => NLW_xram10_DPO_UNCONNECTED
    );
  xram11 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(11),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(11),
      DPO => NLW_xram11_DPO_UNCONNECTED
    );
  xram12 : RAM16X1D
    generic map(
      INIT => X"0005"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(12),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(12),
      DPO => NLW_xram12_DPO_UNCONNECTED
    );
  xram13 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(13),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(13),
      DPO => NLW_xram13_DPO_UNCONNECTED
    );
  xram14 : RAM16X1D
    generic map(
      INIT => X"0004"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(14),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(14),
      DPO => NLW_xram14_DPO_UNCONNECTED
    );
  xram15 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => adr(0),
      A1 => adr(1),
      A2 => adr(2),
      A3 => adr(3),
      D => data_in(15),
      DPRA0 => adr(0),
      DPRA1 => adr(1),
      DPRA2 => adr(2),
      DPRA3 => adr(3),
      WCLK => clk,
      WE => wr,
      SPO => data_out(15),
      DPO => NLW_xram15_DPO_UNCONNECTED
    );
  wr_and00001 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => adr(3),
      I1 => data_we,
      I2 => adr(4),
      O => wr
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity block_pe_main is
  port (
    clk : in STD_LOGIC := 'X'; 
    pb_reset : out STD_LOGIC; 
    bl_data_we : in STD_LOGIC := 'X'; 
    reset_hr1 : in STD_LOGIC := 'X'; 
    bl_data_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    brd_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    bl_adr : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
    bl_data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
  );
end block_pe_main;

architecture STRUCTURE of block_pe_main is
  component ctrl_ram16_v1
    port (
      clk : in STD_LOGIC := 'X'; 
      data_we : in STD_LOGIC := 'X'; 
      data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  signal bl_data_out_0_mux0002 : STD_LOGIC; 
  signal bl_data_out_10_mux0002 : STD_LOGIC; 
  signal bl_data_out_11_mux0002 : STD_LOGIC; 
  signal bl_data_out_12_mux0002 : STD_LOGIC; 
  signal bl_data_out_13_mux0002 : STD_LOGIC; 
  signal bl_data_out_14_mux0002 : STD_LOGIC; 
  signal bl_data_out_15_mux0002 : STD_LOGIC; 
  signal bl_data_out_1_mux0002 : STD_LOGIC; 
  signal bl_data_out_20_mux0001 : STD_LOGIC; 
  signal bl_data_out_2_mux0002 : STD_LOGIC; 
  signal bl_data_out_3_mux0002 : STD_LOGIC; 
  signal bl_data_out_4_mux0002 : STD_LOGIC; 
  signal bl_data_out_5_mux0002 : STD_LOGIC; 
  signal bl_data_out_6_mux0002 : STD_LOGIC; 
  signal bl_data_out_7_mux0002 : STD_LOGIC; 
  signal bl_data_out_8_mux0002 : STD_LOGIC; 
  signal bl_data_out_9_mux0002 : STD_LOGIC; 
  signal c_brd_mode_not0001 : STD_LOGIC; 
  signal reset_hr1_inv : STD_LOGIC; 
  signal bl_ram_out : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_c_brd_mode : STD_LOGIC_VECTOR ( 9 downto 8 ); 
begin
  brd_mode(9) <= NlwRenamedSig_OI_c_brd_mode(9);
  brd_mode(8) <= NlwRenamedSig_OI_c_brd_mode(8);
  bl_data_out_1 : FD
    port map (
      C => clk,
      D => bl_data_out_1_mux0002,
      Q => bl_data_out(1)
    );
  bl_data_out_0 : FD
    port map (
      C => clk,
      D => bl_data_out_0_mux0002,
      Q => bl_data_out(0)
    );
  bl_data_out_2 : FD
    port map (
      C => clk,
      D => bl_data_out_2_mux0002,
      Q => bl_data_out(2)
    );
  bl_data_out_10 : FD
    port map (
      C => clk,
      D => bl_data_out_10_mux0002,
      Q => bl_data_out(10)
    );
  bl_data_out_3 : FD
    port map (
      C => clk,
      D => bl_data_out_3_mux0002,
      Q => bl_data_out(3)
    );
  bl_data_out_11 : FD
    port map (
      C => clk,
      D => bl_data_out_11_mux0002,
      Q => bl_data_out(11)
    );
  bl_data_out_4 : FD
    port map (
      C => clk,
      D => bl_data_out_4_mux0002,
      Q => bl_data_out(4)
    );
  bl_data_out_12 : FD
    port map (
      C => clk,
      D => bl_data_out_12_mux0002,
      Q => bl_data_out(12)
    );
  bl_data_out_5 : FD
    port map (
      C => clk,
      D => bl_data_out_5_mux0002,
      Q => bl_data_out(5)
    );
  bl_data_out_13 : FD
    port map (
      C => clk,
      D => bl_data_out_13_mux0002,
      Q => bl_data_out(13)
    );
  bl_data_out_6 : FD
    port map (
      C => clk,
      D => bl_data_out_6_mux0002,
      Q => bl_data_out(6)
    );
  bl_data_out_14 : FD
    port map (
      C => clk,
      D => bl_data_out_14_mux0002,
      Q => bl_data_out(14)
    );
  bl_data_out_7 : FD
    port map (
      C => clk,
      D => bl_data_out_7_mux0002,
      Q => bl_data_out(7)
    );
  bl_data_out_15 : FD
    port map (
      C => clk,
      D => bl_data_out_15_mux0002,
      Q => bl_data_out(15)
    );
  bl_data_out_20 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(20)
    );
  bl_data_out_8 : FD
    port map (
      C => clk,
      D => bl_data_out_8_mux0002,
      Q => bl_data_out(8)
    );
  bl_data_out_9 : FD
    port map (
      C => clk,
      D => bl_data_out_9_mux0002,
      Q => bl_data_out(9)
    );
  bl_data_out_21 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(21)
    );
  bl_data_out_16 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(16)
    );
  bl_data_out_22 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(22)
    );
  bl_data_out_17 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(17)
    );
  bl_data_out_23 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(23)
    );
  bl_data_out_18 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(18)
    );
  bl_data_out_24 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(24)
    );
  bl_data_out_19 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(19)
    );
  bl_data_out_30 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(30)
    );
  bl_data_out_25 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(25)
    );
  c_brd_mode_8 : FDCE
    port map (
      C => clk,
      CE => c_brd_mode_not0001,
      CLR => reset_hr1_inv,
      D => bl_data_in(8),
      Q => NlwRenamedSig_OI_c_brd_mode(8)
    );
  c_brd_mode_9 : FDCE
    port map (
      C => clk,
      CE => c_brd_mode_not0001,
      CLR => reset_hr1_inv,
      D => bl_data_in(9),
      Q => NlwRenamedSig_OI_c_brd_mode(9)
    );
  bl_data_out_31 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(31)
    );
  bl_data_out_26 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(26)
    );
  bl_data_out_27 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(27)
    );
  bl_data_out_28 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(28)
    );
  bl_data_out_29 : FD
    port map (
      C => clk,
      D => bl_data_out_20_mux0001,
      Q => bl_data_out(29)
    );
  bl_ram : ctrl_ram16_v1
    port map (
      clk => clk,
      data_we => bl_data_we,
      data_out(15) => bl_ram_out(15),
      data_out(14) => bl_ram_out(14),
      data_out(13) => bl_ram_out(13),
      data_out(12) => bl_ram_out(12),
      data_out(11) => bl_ram_out(11),
      data_out(10) => bl_ram_out(10),
      data_out(9) => bl_ram_out(9),
      data_out(8) => bl_ram_out(8),
      data_out(7) => bl_ram_out(7),
      data_out(6) => bl_ram_out(6),
      data_out(5) => bl_ram_out(5),
      data_out(4) => bl_ram_out(4),
      data_out(3) => bl_ram_out(3),
      data_out(2) => bl_ram_out(2),
      data_out(1) => bl_ram_out(1),
      data_out(0) => bl_ram_out(0),
      data_in(15) => bl_data_in(15),
      data_in(14) => bl_data_in(14),
      data_in(13) => bl_data_in(13),
      data_in(12) => bl_data_in(12),
      data_in(11) => bl_data_in(11),
      data_in(10) => bl_data_in(10),
      data_in(9) => bl_data_in(9),
      data_in(8) => bl_data_in(8),
      data_in(7) => bl_data_in(7),
      data_in(6) => bl_data_in(6),
      data_in(5) => bl_data_in(5),
      data_in(4) => bl_data_in(4),
      data_in(3) => bl_data_in(3),
      data_in(2) => bl_data_in(2),
      data_in(1) => bl_data_in(1),
      data_in(0) => bl_data_in(0),
      adr(4) => bl_adr(4),
      adr(3) => bl_adr(3),
      adr(2) => bl_adr(2),
      adr(1) => bl_adr(1),
      adr(0) => bl_adr(0)
    );
  c_brd_mode_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => bl_data_we,
      I1 => bl_adr(3),
      I2 => bl_adr(0),
      I3 => bl_adr(4),
      I4 => bl_adr(2),
      I5 => bl_adr(1),
      O => c_brd_mode_not0001
    );
  bl_data_out_10_mux000221 : LUT4
    generic map(
      INIT => X"0280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      O => bl_data_out_20_mux0001
    );
  bl_data_out_15_mux00021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => bl_ram_out(15),
      I1 => bl_adr(4),
      O => bl_data_out_15_mux0002
    );
  bl_data_out_0_mux00021 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => bl_ram_out(0),
      I1 => bl_adr(4),
      O => bl_data_out_0_mux0002
    );
  bl_data_out_9_mux00021 : LUT6
    generic map(
      INIT => X"57D757D502820280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => NlwRenamedSig_OI_c_brd_mode(9),
      I5 => bl_ram_out(9),
      O => bl_data_out_9_mux0002
    );
  bl_data_out_8_mux00021 : LUT6
    generic map(
      INIT => X"57D757D502820280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => NlwRenamedSig_OI_c_brd_mode(8),
      I5 => bl_ram_out(8),
      O => bl_data_out_8_mux0002
    );
  bl_data_out_7_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(7),
      O => bl_data_out_7_mux0002
    );
  bl_data_out_6_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(6),
      O => bl_data_out_6_mux0002
    );
  bl_data_out_5_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(5),
      O => bl_data_out_5_mux0002
    );
  bl_data_out_4_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(4),
      O => bl_data_out_4_mux0002
    );
  bl_data_out_3_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(3),
      O => bl_data_out_3_mux0002
    );
  bl_data_out_2_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(2),
      O => bl_data_out_2_mux0002
    );
  bl_data_out_1_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(1),
      O => bl_data_out_1_mux0002
    );
  bl_data_out_14_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(14),
      O => bl_data_out_14_mux0002
    );
  bl_data_out_13_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(13),
      O => bl_data_out_13_mux0002
    );
  bl_data_out_12_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(12),
      O => bl_data_out_12_mux0002
    );
  bl_data_out_11_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(11),
      O => bl_data_out_11_mux0002
    );
  bl_data_out_10_mux00021 : LUT5
    generic map(
      INIT => X"57D50280"
    )
    port map (
      I0 => bl_adr(4),
      I1 => bl_adr(1),
      I2 => bl_adr(2),
      I3 => bl_adr(3),
      I4 => bl_ram_out(10),
      O => bl_data_out_10_mux0002
    );
  reset_hr1_inv1_INV_0 : INV
    port map (
      I => reset_hr1,
      O => reset_hr1_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity core64_pb_transaction is
  port (
    clk : in STD_LOGIC := 'X'; 
    lc_irq : in STD_LOGIC := 'X'; 
    pb_master_stb0 : in STD_LOGIC := 'X'; 
    pb_master_stb1 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    lc_rd : out STD_LOGIC; 
    pb_slave_stb0 : out STD_LOGIC; 
    pb_slave_stb1 : out STD_LOGIC; 
    lc_wr : out STD_LOGIC; 
    pb_slave_irq : out STD_LOGIC; 
    lc_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    lc_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    pb_slave_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_slave_dmar : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    lc_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_master_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    pb_master_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    lc_dma_req : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pb_master_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end core64_pb_transaction;

architecture STRUCTURE of core64_pb_transaction is
  signal Mcount_cnt_cy_1_rt_8941 : STD_LOGIC; 
  signal Mcount_cnt_cy_2_rt_8943 : STD_LOGIC; 
  signal Mcount_cnt_cy_3_rt_8945 : STD_LOGIC; 
  signal Mcount_cnt_cy_4_rt_8947 : STD_LOGIC; 
  signal Mcount_cnt_cy_5_rt_8949 : STD_LOGIC; 
  signal Mcount_cnt_cy_6_rt_8951 : STD_LOGIC; 
  signal Mcount_cnt_cy_7_rt_8953 : STD_LOGIC; 
  signal Mcount_cnt_cy_8_rt_8955 : STD_LOGIC; 
  signal Mcount_cnt_val : STD_LOGIC; 
  signal Mcount_cnt_xor_9_rt_8958 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal cnt_and0000 : STD_LOGIC; 
  signal cnt_cst : STD_LOGIC; 
  signal cnt_start_8983 : STD_LOGIC; 
  signal cnt_start_and0000 : STD_LOGIC; 
  signal cnt_start_or0000 : STD_LOGIC; 
  signal pb_slave_data_0_9198 : STD_LOGIC; 
  signal pb_slave_data_1_9199 : STD_LOGIC; 
  signal pb_slave_data_10_9200 : STD_LOGIC; 
  signal pb_slave_data_11_9201 : STD_LOGIC; 
  signal pb_slave_data_12_9202 : STD_LOGIC; 
  signal pb_slave_data_13_9203 : STD_LOGIC; 
  signal pb_slave_data_14_9204 : STD_LOGIC; 
  signal pb_slave_data_15_9205 : STD_LOGIC; 
  signal pb_slave_data_16_9206 : STD_LOGIC; 
  signal pb_slave_data_17_9207 : STD_LOGIC; 
  signal pb_slave_data_18_9208 : STD_LOGIC; 
  signal pb_slave_data_19_9209 : STD_LOGIC; 
  signal pb_slave_data_2_9210 : STD_LOGIC; 
  signal pb_slave_data_20_9211 : STD_LOGIC; 
  signal pb_slave_data_21_9212 : STD_LOGIC; 
  signal pb_slave_data_22_9213 : STD_LOGIC; 
  signal pb_slave_data_23_9214 : STD_LOGIC; 
  signal pb_slave_data_24_9215 : STD_LOGIC; 
  signal pb_slave_data_25_9216 : STD_LOGIC; 
  signal pb_slave_data_26_9217 : STD_LOGIC; 
  signal pb_slave_data_27_9218 : STD_LOGIC; 
  signal pb_slave_data_28_9219 : STD_LOGIC; 
  signal pb_slave_data_29_9220 : STD_LOGIC; 
  signal pb_slave_data_3_9221 : STD_LOGIC; 
  signal pb_slave_data_30_9222 : STD_LOGIC; 
  signal pb_slave_data_31_9223 : STD_LOGIC; 
  signal pb_slave_data_32_9224 : STD_LOGIC; 
  signal pb_slave_data_33_9225 : STD_LOGIC; 
  signal pb_slave_data_34_9226 : STD_LOGIC; 
  signal pb_slave_data_35_9227 : STD_LOGIC; 
  signal pb_slave_data_36_9228 : STD_LOGIC; 
  signal pb_slave_data_37_9229 : STD_LOGIC; 
  signal pb_slave_data_38_9230 : STD_LOGIC; 
  signal pb_slave_data_39_9231 : STD_LOGIC; 
  signal pb_slave_data_4_9232 : STD_LOGIC; 
  signal pb_slave_data_40_9233 : STD_LOGIC; 
  signal pb_slave_data_41_9234 : STD_LOGIC; 
  signal pb_slave_data_42_9235 : STD_LOGIC; 
  signal pb_slave_data_43_9236 : STD_LOGIC; 
  signal pb_slave_data_44_9237 : STD_LOGIC; 
  signal pb_slave_data_45_9238 : STD_LOGIC; 
  signal pb_slave_data_46_9239 : STD_LOGIC; 
  signal pb_slave_data_47_9240 : STD_LOGIC; 
  signal pb_slave_data_48_9241 : STD_LOGIC; 
  signal pb_slave_data_49_9242 : STD_LOGIC; 
  signal pb_slave_data_5_9243 : STD_LOGIC; 
  signal pb_slave_data_50_9244 : STD_LOGIC; 
  signal pb_slave_data_51_9245 : STD_LOGIC; 
  signal pb_slave_data_52_9246 : STD_LOGIC; 
  signal pb_slave_data_53_9247 : STD_LOGIC; 
  signal pb_slave_data_54_9248 : STD_LOGIC; 
  signal pb_slave_data_55_9249 : STD_LOGIC; 
  signal pb_slave_data_56_9250 : STD_LOGIC; 
  signal pb_slave_data_57_9251 : STD_LOGIC; 
  signal pb_slave_data_58_9252 : STD_LOGIC; 
  signal pb_slave_data_59_9253 : STD_LOGIC; 
  signal pb_slave_data_6_9254 : STD_LOGIC; 
  signal pb_slave_data_60_9255 : STD_LOGIC; 
  signal pb_slave_data_61_9256 : STD_LOGIC; 
  signal pb_slave_data_62_9257 : STD_LOGIC; 
  signal pb_slave_data_63_9258 : STD_LOGIC; 
  signal pb_slave_data_7_9259 : STD_LOGIC; 
  signal pb_slave_data_8_9260 : STD_LOGIC; 
  signal pb_slave_data_9_9261 : STD_LOGIC; 
  signal pb_slave_stb0_9262 : STD_LOGIC; 
  signal pb_slave_stb1_9263 : STD_LOGIC; 
  signal NlwRenamedSignal_pb_slave_irq : STD_LOGIC; 
  signal rd_start : STD_LOGIC; 
  signal rd_start_norst : STD_LOGIC; 
  signal rd_start_z : STD_LOGIC; 
  signal rstp_9271 : STD_LOGIC; 
  signal rstp_not0001_norst : STD_LOGIC; 
  signal Mcount_cnt_cy : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Mcount_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal cnt : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal NlwRenamedSignal_pb_slave_dmar : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  NlwRenamedSignal_pb_slave_irq <= lc_irq;
  pb_slave_stb0 <= pb_slave_stb0_9262;
  pb_slave_stb1 <= pb_slave_stb1_9263;
  pb_slave_irq <= NlwRenamedSignal_pb_slave_irq;
  pb_slave_data(63) <= pb_slave_data_63_9258;
  pb_slave_data(62) <= pb_slave_data_62_9257;
  pb_slave_data(61) <= pb_slave_data_61_9256;
  pb_slave_data(60) <= pb_slave_data_60_9255;
  pb_slave_data(59) <= pb_slave_data_59_9253;
  pb_slave_data(58) <= pb_slave_data_58_9252;
  pb_slave_data(57) <= pb_slave_data_57_9251;
  pb_slave_data(56) <= pb_slave_data_56_9250;
  pb_slave_data(55) <= pb_slave_data_55_9249;
  pb_slave_data(54) <= pb_slave_data_54_9248;
  pb_slave_data(53) <= pb_slave_data_53_9247;
  pb_slave_data(52) <= pb_slave_data_52_9246;
  pb_slave_data(51) <= pb_slave_data_51_9245;
  pb_slave_data(50) <= pb_slave_data_50_9244;
  pb_slave_data(49) <= pb_slave_data_49_9242;
  pb_slave_data(48) <= pb_slave_data_48_9241;
  pb_slave_data(47) <= pb_slave_data_47_9240;
  pb_slave_data(46) <= pb_slave_data_46_9239;
  pb_slave_data(45) <= pb_slave_data_45_9238;
  pb_slave_data(44) <= pb_slave_data_44_9237;
  pb_slave_data(43) <= pb_slave_data_43_9236;
  pb_slave_data(42) <= pb_slave_data_42_9235;
  pb_slave_data(41) <= pb_slave_data_41_9234;
  pb_slave_data(40) <= pb_slave_data_40_9233;
  pb_slave_data(39) <= pb_slave_data_39_9231;
  pb_slave_data(38) <= pb_slave_data_38_9230;
  pb_slave_data(37) <= pb_slave_data_37_9229;
  pb_slave_data(36) <= pb_slave_data_36_9228;
  pb_slave_data(35) <= pb_slave_data_35_9227;
  pb_slave_data(34) <= pb_slave_data_34_9226;
  pb_slave_data(33) <= pb_slave_data_33_9225;
  pb_slave_data(32) <= pb_slave_data_32_9224;
  pb_slave_data(31) <= pb_slave_data_31_9223;
  pb_slave_data(30) <= pb_slave_data_30_9222;
  pb_slave_data(29) <= pb_slave_data_29_9220;
  pb_slave_data(28) <= pb_slave_data_28_9219;
  pb_slave_data(27) <= pb_slave_data_27_9218;
  pb_slave_data(26) <= pb_slave_data_26_9217;
  pb_slave_data(25) <= pb_slave_data_25_9216;
  pb_slave_data(24) <= pb_slave_data_24_9215;
  pb_slave_data(23) <= pb_slave_data_23_9214;
  pb_slave_data(22) <= pb_slave_data_22_9213;
  pb_slave_data(21) <= pb_slave_data_21_9212;
  pb_slave_data(20) <= pb_slave_data_20_9211;
  pb_slave_data(19) <= pb_slave_data_19_9209;
  pb_slave_data(18) <= pb_slave_data_18_9208;
  pb_slave_data(17) <= pb_slave_data_17_9207;
  pb_slave_data(16) <= pb_slave_data_16_9206;
  pb_slave_data(15) <= pb_slave_data_15_9205;
  pb_slave_data(14) <= pb_slave_data_14_9204;
  pb_slave_data(13) <= pb_slave_data_13_9203;
  pb_slave_data(12) <= pb_slave_data_12_9202;
  pb_slave_data(11) <= pb_slave_data_11_9201;
  pb_slave_data(10) <= pb_slave_data_10_9200;
  pb_slave_data(9) <= pb_slave_data_9_9261;
  pb_slave_data(8) <= pb_slave_data_8_9260;
  pb_slave_data(7) <= pb_slave_data_7_9259;
  pb_slave_data(6) <= pb_slave_data_6_9254;
  pb_slave_data(5) <= pb_slave_data_5_9243;
  pb_slave_data(4) <= pb_slave_data_4_9232;
  pb_slave_data(3) <= pb_slave_data_3_9221;
  pb_slave_data(2) <= pb_slave_data_2_9210;
  pb_slave_data(1) <= pb_slave_data_1_9199;
  pb_slave_data(0) <= pb_slave_data_0_9198;
  pb_slave_dmar(1) <= NlwRenamedSignal_pb_slave_dmar(1);
  pb_slave_dmar(0) <= NlwRenamedSignal_pb_slave_dmar(0);
  NlwRenamedSignal_pb_slave_dmar(1) <= lc_dma_req(1);
  NlwRenamedSignal_pb_slave_dmar(0) <= lc_dma_req(0);
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => rstp_not0001_norst
    );
  pb_slave_data_0 : FD
    port map (
      C => clk,
      D => lc_data(0),
      Q => pb_slave_data_0_9198
    );
  pb_slave_data_1 : FD
    port map (
      C => clk,
      D => lc_data(1),
      Q => pb_slave_data_1_9199
    );
  pb_slave_data_2 : FD
    port map (
      C => clk,
      D => lc_data(2),
      Q => pb_slave_data_2_9210
    );
  pb_slave_data_3 : FD
    port map (
      C => clk,
      D => lc_data(3),
      Q => pb_slave_data_3_9221
    );
  pb_slave_data_4 : FD
    port map (
      C => clk,
      D => lc_data(4),
      Q => pb_slave_data_4_9232
    );
  pb_slave_data_5 : FD
    port map (
      C => clk,
      D => lc_data(5),
      Q => pb_slave_data_5_9243
    );
  pb_slave_data_6 : FD
    port map (
      C => clk,
      D => lc_data(6),
      Q => pb_slave_data_6_9254
    );
  pb_slave_data_7 : FD
    port map (
      C => clk,
      D => lc_data(7),
      Q => pb_slave_data_7_9259
    );
  pb_slave_data_8 : FD
    port map (
      C => clk,
      D => lc_data(8),
      Q => pb_slave_data_8_9260
    );
  pb_slave_data_9 : FD
    port map (
      C => clk,
      D => lc_data(9),
      Q => pb_slave_data_9_9261
    );
  pb_slave_data_10 : FD
    port map (
      C => clk,
      D => lc_data(10),
      Q => pb_slave_data_10_9200
    );
  pb_slave_data_11 : FD
    port map (
      C => clk,
      D => lc_data(11),
      Q => pb_slave_data_11_9201
    );
  pb_slave_data_12 : FD
    port map (
      C => clk,
      D => lc_data(12),
      Q => pb_slave_data_12_9202
    );
  pb_slave_data_13 : FD
    port map (
      C => clk,
      D => lc_data(13),
      Q => pb_slave_data_13_9203
    );
  pb_slave_data_14 : FD
    port map (
      C => clk,
      D => lc_data(14),
      Q => pb_slave_data_14_9204
    );
  pb_slave_data_15 : FD
    port map (
      C => clk,
      D => lc_data(15),
      Q => pb_slave_data_15_9205
    );
  pb_slave_data_16 : FD
    port map (
      C => clk,
      D => lc_data(16),
      Q => pb_slave_data_16_9206
    );
  pb_slave_data_17 : FD
    port map (
      C => clk,
      D => lc_data(17),
      Q => pb_slave_data_17_9207
    );
  pb_slave_data_18 : FD
    port map (
      C => clk,
      D => lc_data(18),
      Q => pb_slave_data_18_9208
    );
  pb_slave_data_19 : FD
    port map (
      C => clk,
      D => lc_data(19),
      Q => pb_slave_data_19_9209
    );
  pb_slave_data_20 : FD
    port map (
      C => clk,
      D => lc_data(20),
      Q => pb_slave_data_20_9211
    );
  pb_slave_data_21 : FD
    port map (
      C => clk,
      D => lc_data(21),
      Q => pb_slave_data_21_9212
    );
  pb_slave_data_22 : FD
    port map (
      C => clk,
      D => lc_data(22),
      Q => pb_slave_data_22_9213
    );
  pb_slave_data_23 : FD
    port map (
      C => clk,
      D => lc_data(23),
      Q => pb_slave_data_23_9214
    );
  pb_slave_data_24 : FD
    port map (
      C => clk,
      D => lc_data(24),
      Q => pb_slave_data_24_9215
    );
  pb_slave_data_25 : FD
    port map (
      C => clk,
      D => lc_data(25),
      Q => pb_slave_data_25_9216
    );
  pb_slave_data_26 : FD
    port map (
      C => clk,
      D => lc_data(26),
      Q => pb_slave_data_26_9217
    );
  pb_slave_data_27 : FD
    port map (
      C => clk,
      D => lc_data(27),
      Q => pb_slave_data_27_9218
    );
  pb_slave_data_28 : FD
    port map (
      C => clk,
      D => lc_data(28),
      Q => pb_slave_data_28_9219
    );
  pb_slave_data_29 : FD
    port map (
      C => clk,
      D => lc_data(29),
      Q => pb_slave_data_29_9220
    );
  pb_slave_data_30 : FD
    port map (
      C => clk,
      D => lc_data(30),
      Q => pb_slave_data_30_9222
    );
  pb_slave_data_31 : FD
    port map (
      C => clk,
      D => lc_data(31),
      Q => pb_slave_data_31_9223
    );
  pb_slave_data_32 : FD
    port map (
      C => clk,
      D => lc_data(32),
      Q => pb_slave_data_32_9224
    );
  pb_slave_data_33 : FD
    port map (
      C => clk,
      D => lc_data(33),
      Q => pb_slave_data_33_9225
    );
  pb_slave_data_34 : FD
    port map (
      C => clk,
      D => lc_data(34),
      Q => pb_slave_data_34_9226
    );
  pb_slave_data_35 : FD
    port map (
      C => clk,
      D => lc_data(35),
      Q => pb_slave_data_35_9227
    );
  pb_slave_data_36 : FD
    port map (
      C => clk,
      D => lc_data(36),
      Q => pb_slave_data_36_9228
    );
  pb_slave_data_37 : FD
    port map (
      C => clk,
      D => lc_data(37),
      Q => pb_slave_data_37_9229
    );
  pb_slave_data_38 : FD
    port map (
      C => clk,
      D => lc_data(38),
      Q => pb_slave_data_38_9230
    );
  pb_slave_data_39 : FD
    port map (
      C => clk,
      D => lc_data(39),
      Q => pb_slave_data_39_9231
    );
  pb_slave_data_40 : FD
    port map (
      C => clk,
      D => lc_data(40),
      Q => pb_slave_data_40_9233
    );
  pb_slave_data_41 : FD
    port map (
      C => clk,
      D => lc_data(41),
      Q => pb_slave_data_41_9234
    );
  pb_slave_data_42 : FD
    port map (
      C => clk,
      D => lc_data(42),
      Q => pb_slave_data_42_9235
    );
  pb_slave_data_43 : FD
    port map (
      C => clk,
      D => lc_data(43),
      Q => pb_slave_data_43_9236
    );
  pb_slave_data_44 : FD
    port map (
      C => clk,
      D => lc_data(44),
      Q => pb_slave_data_44_9237
    );
  pb_slave_data_45 : FD
    port map (
      C => clk,
      D => lc_data(45),
      Q => pb_slave_data_45_9238
    );
  pb_slave_data_46 : FD
    port map (
      C => clk,
      D => lc_data(46),
      Q => pb_slave_data_46_9239
    );
  pb_slave_data_47 : FD
    port map (
      C => clk,
      D => lc_data(47),
      Q => pb_slave_data_47_9240
    );
  pb_slave_data_48 : FD
    port map (
      C => clk,
      D => lc_data(48),
      Q => pb_slave_data_48_9241
    );
  pb_slave_data_49 : FD
    port map (
      C => clk,
      D => lc_data(49),
      Q => pb_slave_data_49_9242
    );
  pb_slave_data_50 : FD
    port map (
      C => clk,
      D => lc_data(50),
      Q => pb_slave_data_50_9244
    );
  pb_slave_data_51 : FD
    port map (
      C => clk,
      D => lc_data(51),
      Q => pb_slave_data_51_9245
    );
  pb_slave_data_52 : FD
    port map (
      C => clk,
      D => lc_data(52),
      Q => pb_slave_data_52_9246
    );
  pb_slave_data_53 : FD
    port map (
      C => clk,
      D => lc_data(53),
      Q => pb_slave_data_53_9247
    );
  pb_slave_data_54 : FD
    port map (
      C => clk,
      D => lc_data(54),
      Q => pb_slave_data_54_9248
    );
  pb_slave_data_55 : FD
    port map (
      C => clk,
      D => lc_data(55),
      Q => pb_slave_data_55_9249
    );
  pb_slave_data_56 : FD
    port map (
      C => clk,
      D => lc_data(56),
      Q => pb_slave_data_56_9250
    );
  pb_slave_data_57 : FD
    port map (
      C => clk,
      D => lc_data(57),
      Q => pb_slave_data_57_9251
    );
  pb_slave_data_58 : FD
    port map (
      C => clk,
      D => lc_data(58),
      Q => pb_slave_data_58_9252
    );
  pb_slave_data_59 : FD
    port map (
      C => clk,
      D => lc_data(59),
      Q => pb_slave_data_59_9253
    );
  pb_slave_data_60 : FD
    port map (
      C => clk,
      D => lc_data(60),
      Q => pb_slave_data_60_9255
    );
  pb_slave_data_61 : FD
    port map (
      C => clk,
      D => lc_data(61),
      Q => pb_slave_data_61_9256
    );
  pb_slave_data_62 : FD
    port map (
      C => clk,
      D => lc_data(62),
      Q => pb_slave_data_62_9257
    );
  pb_slave_data_63 : FD
    port map (
      C => clk,
      D => lc_data(63),
      Q => pb_slave_data_63_9258
    );
  lc_adr_11 : FD
    port map (
      C => clk,
      D => pb_master_adr(11),
      Q => lc_adr(11)
    );
  lc_adr_12 : FD
    port map (
      C => clk,
      D => pb_master_adr(12),
      Q => lc_adr(12)
    );
  lc_adr_13 : FD
    port map (
      C => clk,
      D => pb_master_adr(13),
      Q => lc_adr(13)
    );
  lc_adr_14 : FD
    port map (
      C => clk,
      D => pb_master_adr(14),
      Q => lc_adr(14)
    );
  lc_adr_15 : FD
    port map (
      C => clk,
      D => pb_master_adr(15),
      Q => lc_adr(15)
    );
  lc_adr_16 : FD
    port map (
      C => clk,
      D => pb_master_adr(16),
      Q => lc_adr(16)
    );
  lc_adr_17 : FD
    port map (
      C => clk,
      D => pb_master_adr(17),
      Q => lc_adr(17)
    );
  pb_slave_stb0_7085 : FD
    port map (
      C => clk,
      D => pb_master_stb0,
      Q => pb_slave_stb0_9262
    );
  lc_host_data_0 : FD
    port map (
      C => clk,
      D => pb_master_data(0),
      Q => lc_host_data(0)
    );
  lc_host_data_1 : FD
    port map (
      C => clk,
      D => pb_master_data(1),
      Q => lc_host_data(1)
    );
  lc_host_data_2 : FD
    port map (
      C => clk,
      D => pb_master_data(2),
      Q => lc_host_data(2)
    );
  lc_host_data_3 : FD
    port map (
      C => clk,
      D => pb_master_data(3),
      Q => lc_host_data(3)
    );
  lc_host_data_4 : FD
    port map (
      C => clk,
      D => pb_master_data(4),
      Q => lc_host_data(4)
    );
  lc_host_data_5 : FD
    port map (
      C => clk,
      D => pb_master_data(5),
      Q => lc_host_data(5)
    );
  lc_host_data_6 : FD
    port map (
      C => clk,
      D => pb_master_data(6),
      Q => lc_host_data(6)
    );
  lc_host_data_7 : FD
    port map (
      C => clk,
      D => pb_master_data(7),
      Q => lc_host_data(7)
    );
  lc_host_data_8 : FD
    port map (
      C => clk,
      D => pb_master_data(8),
      Q => lc_host_data(8)
    );
  lc_host_data_9 : FD
    port map (
      C => clk,
      D => pb_master_data(9),
      Q => lc_host_data(9)
    );
  lc_host_data_10 : FD
    port map (
      C => clk,
      D => pb_master_data(10),
      Q => lc_host_data(10)
    );
  lc_host_data_11 : FD
    port map (
      C => clk,
      D => pb_master_data(11),
      Q => lc_host_data(11)
    );
  lc_host_data_12 : FD
    port map (
      C => clk,
      D => pb_master_data(12),
      Q => lc_host_data(12)
    );
  lc_host_data_13 : FD
    port map (
      C => clk,
      D => pb_master_data(13),
      Q => lc_host_data(13)
    );
  lc_host_data_14 : FD
    port map (
      C => clk,
      D => pb_master_data(14),
      Q => lc_host_data(14)
    );
  lc_host_data_15 : FD
    port map (
      C => clk,
      D => pb_master_data(15),
      Q => lc_host_data(15)
    );
  lc_host_data_16 : FD
    port map (
      C => clk,
      D => pb_master_data(16),
      Q => lc_host_data(16)
    );
  lc_host_data_17 : FD
    port map (
      C => clk,
      D => pb_master_data(17),
      Q => lc_host_data(17)
    );
  lc_host_data_18 : FD
    port map (
      C => clk,
      D => pb_master_data(18),
      Q => lc_host_data(18)
    );
  lc_host_data_19 : FD
    port map (
      C => clk,
      D => pb_master_data(19),
      Q => lc_host_data(19)
    );
  lc_host_data_20 : FD
    port map (
      C => clk,
      D => pb_master_data(20),
      Q => lc_host_data(20)
    );
  lc_host_data_21 : FD
    port map (
      C => clk,
      D => pb_master_data(21),
      Q => lc_host_data(21)
    );
  lc_host_data_22 : FD
    port map (
      C => clk,
      D => pb_master_data(22),
      Q => lc_host_data(22)
    );
  lc_host_data_23 : FD
    port map (
      C => clk,
      D => pb_master_data(23),
      Q => lc_host_data(23)
    );
  lc_host_data_24 : FD
    port map (
      C => clk,
      D => pb_master_data(24),
      Q => lc_host_data(24)
    );
  lc_host_data_25 : FD
    port map (
      C => clk,
      D => pb_master_data(25),
      Q => lc_host_data(25)
    );
  lc_host_data_26 : FD
    port map (
      C => clk,
      D => pb_master_data(26),
      Q => lc_host_data(26)
    );
  lc_host_data_27 : FD
    port map (
      C => clk,
      D => pb_master_data(27),
      Q => lc_host_data(27)
    );
  lc_host_data_28 : FD
    port map (
      C => clk,
      D => pb_master_data(28),
      Q => lc_host_data(28)
    );
  lc_host_data_29 : FD
    port map (
      C => clk,
      D => pb_master_data(29),
      Q => lc_host_data(29)
    );
  lc_host_data_30 : FD
    port map (
      C => clk,
      D => pb_master_data(30),
      Q => lc_host_data(30)
    );
  lc_host_data_31 : FD
    port map (
      C => clk,
      D => pb_master_data(31),
      Q => lc_host_data(31)
    );
  lc_host_data_32 : FD
    port map (
      C => clk,
      D => pb_master_data(32),
      Q => lc_host_data(32)
    );
  lc_host_data_33 : FD
    port map (
      C => clk,
      D => pb_master_data(33),
      Q => lc_host_data(33)
    );
  lc_host_data_34 : FD
    port map (
      C => clk,
      D => pb_master_data(34),
      Q => lc_host_data(34)
    );
  lc_host_data_35 : FD
    port map (
      C => clk,
      D => pb_master_data(35),
      Q => lc_host_data(35)
    );
  lc_host_data_36 : FD
    port map (
      C => clk,
      D => pb_master_data(36),
      Q => lc_host_data(36)
    );
  lc_host_data_37 : FD
    port map (
      C => clk,
      D => pb_master_data(37),
      Q => lc_host_data(37)
    );
  lc_host_data_38 : FD
    port map (
      C => clk,
      D => pb_master_data(38),
      Q => lc_host_data(38)
    );
  lc_host_data_39 : FD
    port map (
      C => clk,
      D => pb_master_data(39),
      Q => lc_host_data(39)
    );
  lc_host_data_40 : FD
    port map (
      C => clk,
      D => pb_master_data(40),
      Q => lc_host_data(40)
    );
  lc_host_data_41 : FD
    port map (
      C => clk,
      D => pb_master_data(41),
      Q => lc_host_data(41)
    );
  lc_host_data_42 : FD
    port map (
      C => clk,
      D => pb_master_data(42),
      Q => lc_host_data(42)
    );
  lc_host_data_43 : FD
    port map (
      C => clk,
      D => pb_master_data(43),
      Q => lc_host_data(43)
    );
  lc_host_data_44 : FD
    port map (
      C => clk,
      D => pb_master_data(44),
      Q => lc_host_data(44)
    );
  lc_host_data_45 : FD
    port map (
      C => clk,
      D => pb_master_data(45),
      Q => lc_host_data(45)
    );
  lc_host_data_46 : FD
    port map (
      C => clk,
      D => pb_master_data(46),
      Q => lc_host_data(46)
    );
  lc_host_data_47 : FD
    port map (
      C => clk,
      D => pb_master_data(47),
      Q => lc_host_data(47)
    );
  lc_host_data_48 : FD
    port map (
      C => clk,
      D => pb_master_data(48),
      Q => lc_host_data(48)
    );
  lc_host_data_49 : FD
    port map (
      C => clk,
      D => pb_master_data(49),
      Q => lc_host_data(49)
    );
  lc_host_data_50 : FD
    port map (
      C => clk,
      D => pb_master_data(50),
      Q => lc_host_data(50)
    );
  lc_host_data_51 : FD
    port map (
      C => clk,
      D => pb_master_data(51),
      Q => lc_host_data(51)
    );
  lc_host_data_52 : FD
    port map (
      C => clk,
      D => pb_master_data(52),
      Q => lc_host_data(52)
    );
  lc_host_data_53 : FD
    port map (
      C => clk,
      D => pb_master_data(53),
      Q => lc_host_data(53)
    );
  lc_host_data_54 : FD
    port map (
      C => clk,
      D => pb_master_data(54),
      Q => lc_host_data(54)
    );
  lc_host_data_55 : FD
    port map (
      C => clk,
      D => pb_master_data(55),
      Q => lc_host_data(55)
    );
  lc_host_data_56 : FD
    port map (
      C => clk,
      D => pb_master_data(56),
      Q => lc_host_data(56)
    );
  lc_host_data_57 : FD
    port map (
      C => clk,
      D => pb_master_data(57),
      Q => lc_host_data(57)
    );
  lc_host_data_58 : FD
    port map (
      C => clk,
      D => pb_master_data(58),
      Q => lc_host_data(58)
    );
  lc_host_data_59 : FD
    port map (
      C => clk,
      D => pb_master_data(59),
      Q => lc_host_data(59)
    );
  lc_host_data_60 : FD
    port map (
      C => clk,
      D => pb_master_data(60),
      Q => lc_host_data(60)
    );
  lc_host_data_61 : FD
    port map (
      C => clk,
      D => pb_master_data(61),
      Q => lc_host_data(61)
    );
  lc_host_data_62 : FD
    port map (
      C => clk,
      D => pb_master_data(62),
      Q => lc_host_data(62)
    );
  lc_host_data_63 : FD
    port map (
      C => clk,
      D => pb_master_data(63),
      Q => lc_host_data(63)
    );
  cnt_start : FDRE
    port map (
      C => clk,
      CE => cnt_start_and0000,
      D => rstp_not0001_norst,
      R => cnt_start_or0000,
      Q => cnt_start_8983
    );
  lc_wr_7151 : FD
    port map (
      C => clk,
      D => pb_master_stb1,
      Q => lc_wr
    );
  rstp : FDR
    port map (
      C => clk,
      D => rstp_not0001_norst,
      R => reset,
      Q => rstp_9271
    );
  pb_slave_stb1_7153 : FD
    port map (
      C => clk,
      D => rd_start_z,
      Q => pb_slave_stb1_9263
    );
  lc_rd_7154 : FDR
    port map (
      C => clk,
      D => rd_start_norst,
      R => Mcount_cnt_val,
      Q => lc_rd
    );
  cnt_0 : FDRS
    port map (
      C => clk,
      D => Result(0),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(0)
    );
  cnt_3 : FDRS
    port map (
      C => clk,
      D => Result(3),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(3)
    );
  cnt_1 : FDRS
    port map (
      C => clk,
      D => Result(1),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(1)
    );
  cnt_2 : FDRS
    port map (
      C => clk,
      D => Result(2),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(2)
    );
  cnt_6 : FDRS
    port map (
      C => clk,
      D => Result(6),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(6)
    );
  cnt_4 : FDRS
    port map (
      C => clk,
      D => Result(4),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(4)
    );
  cnt_5 : FDRS
    port map (
      C => clk,
      D => Result(5),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(5)
    );
  cnt_9 : FDR
    port map (
      C => clk,
      D => Result(9),
      R => Mcount_cnt_val,
      Q => cnt(9)
    );
  cnt_7 : FDRS
    port map (
      C => clk,
      D => Result(7),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(7)
    );
  cnt_8 : FDRS
    port map (
      C => clk,
      D => Result(8),
      R => cnt_and0000,
      S => cnt_cst,
      Q => cnt(8)
    );
  Mcount_cnt_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => rstp_not0001_norst,
      S => Mcount_cnt_lut(0),
      O => Mcount_cnt_cy(0)
    );
  Mcount_cnt_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_cnt_lut(0),
      O => Result(0)
    );
  Mcount_cnt_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(0),
      DI => N0,
      S => Mcount_cnt_cy_1_rt_8941,
      O => Mcount_cnt_cy(1)
    );
  Mcount_cnt_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(0),
      LI => Mcount_cnt_cy_1_rt_8941,
      O => Result(1)
    );
  Mcount_cnt_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(1),
      DI => N0,
      S => Mcount_cnt_cy_2_rt_8943,
      O => Mcount_cnt_cy(2)
    );
  Mcount_cnt_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(1),
      LI => Mcount_cnt_cy_2_rt_8943,
      O => Result(2)
    );
  Mcount_cnt_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(2),
      DI => N0,
      S => Mcount_cnt_cy_3_rt_8945,
      O => Mcount_cnt_cy(3)
    );
  Mcount_cnt_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(2),
      LI => Mcount_cnt_cy_3_rt_8945,
      O => Result(3)
    );
  Mcount_cnt_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(3),
      DI => N0,
      S => Mcount_cnt_cy_4_rt_8947,
      O => Mcount_cnt_cy(4)
    );
  Mcount_cnt_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(3),
      LI => Mcount_cnt_cy_4_rt_8947,
      O => Result(4)
    );
  Mcount_cnt_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(4),
      DI => N0,
      S => Mcount_cnt_cy_5_rt_8949,
      O => Mcount_cnt_cy(5)
    );
  Mcount_cnt_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(4),
      LI => Mcount_cnt_cy_5_rt_8949,
      O => Result(5)
    );
  Mcount_cnt_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(5),
      DI => N0,
      S => Mcount_cnt_cy_6_rt_8951,
      O => Mcount_cnt_cy(6)
    );
  Mcount_cnt_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(5),
      LI => Mcount_cnt_cy_6_rt_8951,
      O => Result(6)
    );
  Mcount_cnt_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(6),
      DI => N0,
      S => Mcount_cnt_cy_7_rt_8953,
      O => Mcount_cnt_cy(7)
    );
  Mcount_cnt_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(6),
      LI => Mcount_cnt_cy_7_rt_8953,
      O => Result(7)
    );
  Mcount_cnt_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt_cy(7),
      DI => N0,
      S => Mcount_cnt_cy_8_rt_8955,
      O => Mcount_cnt_cy(8)
    );
  Mcount_cnt_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(7),
      LI => Mcount_cnt_cy_8_rt_8955,
      O => Result(8)
    );
  Mcount_cnt_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt_cy(8),
      LI => Mcount_cnt_xor_9_rt_8958,
      O => Result(9)
    );
  xrdz : SRL16
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => rstp_not0001_norst,
      A1 => N0,
      A2 => rstp_not0001_norst,
      A3 => N0,
      CLK => clk,
      D => rd_start,
      Q => rd_start_z
    );
  cnt_start_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => pb_master_cmd(1),
      I1 => pb_master_stb0,
      O => cnt_start_and0000
    );
  rd_start1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cnt(9),
      I1 => cnt_start_8983,
      O => rd_start
    );
  cnt_start_or00001 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => rstp_9271,
      I1 => cnt(9),
      O => cnt_start_or0000
    );
  cnt_cst1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => pb_master_cmd(2),
      I1 => cnt_start_8983,
      O => cnt_cst
    );
  cnt_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cnt_start_8983,
      I1 => pb_master_cmd(2),
      O => cnt_and0000
    );
  Mcount_cnt_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(1),
      O => Mcount_cnt_cy_1_rt_8941
    );
  Mcount_cnt_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(2),
      O => Mcount_cnt_cy_2_rt_8943
    );
  Mcount_cnt_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(3),
      O => Mcount_cnt_cy_3_rt_8945
    );
  Mcount_cnt_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(4),
      O => Mcount_cnt_cy_4_rt_8947
    );
  Mcount_cnt_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(5),
      O => Mcount_cnt_cy_5_rt_8949
    );
  Mcount_cnt_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(6),
      O => Mcount_cnt_cy_6_rt_8951
    );
  Mcount_cnt_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(7),
      O => Mcount_cnt_cy_7_rt_8953
    );
  Mcount_cnt_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(8),
      O => Mcount_cnt_cy_8_rt_8955
    );
  Mcount_cnt_xor_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt(9),
      O => Mcount_cnt_xor_9_rt_8958
    );
  Mcount_cnt_lut_0_INV_0 : INV
    port map (
      I => cnt(0),
      O => Mcount_cnt_lut(0)
    );
  rd_start_norst1_INV_0 : INV
    port map (
      I => cnt(9),
      O => rd_start_norst
    );
  Mcount_cnt_val1_INV_0 : INV
    port map (
      I => cnt_start_8983,
      O => Mcount_cnt_val
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pcie_core64_m2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    lc_irq : in STD_LOGIC := 'X'; 
    mgt250 : in STD_LOGIC := 'X'; 
    lc_rd : out STD_LOGIC; 
    clk250_out : out STD_LOGIC; 
    lc_wr : out STD_LOGIC; 
    pcie_link_up : out STD_LOGIC; 
    clk_lock : in STD_LOGIC := 'X'; 
    reset_out : out STD_LOGIC; 
    perst : in STD_LOGIC := 'X'; 
    dcm_rstp : out STD_LOGIC; 
    lc_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    px : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    lc_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    pcie_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    lc_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    lc_dma_req : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end pcie_core64_m2;

architecture STRUCTURE of pcie_core64_m2 is
  component core64_pb_transaction
    port (
      clk : in STD_LOGIC := 'X'; 
      lc_irq : in STD_LOGIC := 'X'; 
      pb_master_stb0 : in STD_LOGIC := 'X'; 
      pb_master_stb1 : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      lc_rd : out STD_LOGIC; 
      pb_slave_stb0 : out STD_LOGIC; 
      pb_slave_stb1 : out STD_LOGIC; 
      lc_wr : out STD_LOGIC; 
      pb_slave_irq : out STD_LOGIC; 
      lc_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      lc_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      pb_slave_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_slave_dmar : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      lc_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_master_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_master_adr : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      lc_dma_req : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
      pb_master_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component block_pe_main
    port (
      clk : in STD_LOGIC := 'X'; 
      pb_reset : out STD_LOGIC; 
      bl_data_we : in STD_LOGIC := 'X'; 
      reset_hr1 : in STD_LOGIC := 'X'; 
      bl_data_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      brd_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      bl_adr : in STD_LOGIC_VECTOR ( 4 downto 0 ); 
      bl_data_in : in STD_LOGIC_VECTOR ( 31 downto 0 ) 
    );
  end component;
  component pcie_core64_m1
    port (
      bp_reg_rd : out STD_LOGIC; 
      clk_out : out STD_LOGIC; 
      pb_master_stb0 : out STD_LOGIC; 
      pb_master_stb1 : out STD_LOGIC; 
      aclk : in STD_LOGIC := 'X'; 
      bp_reg_we : out STD_LOGIC; 
      mgt250 : in STD_LOGIC := 'X'; 
      aclk_lock : in STD_LOGIC := 'X'; 
      bp_irq : in STD_LOGIC := 'X'; 
      pb_slave_stb0 : in STD_LOGIC := 'X'; 
      pb_slave_stb1 : in STD_LOGIC := 'X'; 
      pcie_link_up : out STD_LOGIC; 
      reset_out : out STD_LOGIC; 
      pb_slave_irq : in STD_LOGIC := 'X'; 
      perst : in STD_LOGIC := 'X'; 
      dcm_rstp : out STD_LOGIC; 
      bp_sel : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      bp_host_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      bp_rd : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      bp_we : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
      pb_master_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      px : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pb_master_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      bp_adr : out STD_LOGIC_VECTOR ( 19 downto 0 ); 
      pb_master_cmd : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
      pcie_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      bp_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      pb_slave_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      pb_slave_dmar : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_clk250_out : STD_LOGIC; 
  signal pb_master_stb0 : STD_LOGIC; 
  signal pb_master_stb1 : STD_LOGIC; 
  signal pb_slave_irq : STD_LOGIC; 
  signal pb_slave_stb0 : STD_LOGIC; 
  signal pb_slave_stb1 : STD_LOGIC; 
  signal NlwRenamedSig_OI_reset_out : STD_LOGIC; 
  signal NLW_core_bp_reg_rd_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_reg_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_aclk_lock_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_irq_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_rd_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_rd_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_rd_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_rd_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_we_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_we_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_we_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_core_bp_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_pb_reset_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_brd_mode_0_UNCONNECTED : STD_LOGIC; 
  signal bp0_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal bp_adr : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal bp_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal bp_host_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal bp_sel : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal bp_we : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal pb_master_adr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal pb_master_cmd : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal pb_master_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pb_slave_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pb_slave_dmar : STD_LOGIC_VECTOR ( 1 downto 0 ); 
begin
  clk250_out <= NlwRenamedSig_OI_clk250_out;
  reset_out <= NlwRenamedSig_OI_reset_out;
  tz : core64_pb_transaction
    port map (
      clk => clk,
      lc_irq => lc_irq,
      pb_master_stb0 => pb_master_stb0,
      pb_master_stb1 => pb_master_stb1,
      reset => NlwRenamedSig_OI_reset_out,
      lc_rd => lc_rd,
      pb_slave_stb0 => pb_slave_stb0,
      pb_slave_stb1 => pb_slave_stb1,
      lc_wr => lc_wr,
      pb_slave_irq => pb_slave_irq,
      lc_host_data(63) => lc_host_data(63),
      lc_host_data(62) => lc_host_data(62),
      lc_host_data(61) => lc_host_data(61),
      lc_host_data(60) => lc_host_data(60),
      lc_host_data(59) => lc_host_data(59),
      lc_host_data(58) => lc_host_data(58),
      lc_host_data(57) => lc_host_data(57),
      lc_host_data(56) => lc_host_data(56),
      lc_host_data(55) => lc_host_data(55),
      lc_host_data(54) => lc_host_data(54),
      lc_host_data(53) => lc_host_data(53),
      lc_host_data(52) => lc_host_data(52),
      lc_host_data(51) => lc_host_data(51),
      lc_host_data(50) => lc_host_data(50),
      lc_host_data(49) => lc_host_data(49),
      lc_host_data(48) => lc_host_data(48),
      lc_host_data(47) => lc_host_data(47),
      lc_host_data(46) => lc_host_data(46),
      lc_host_data(45) => lc_host_data(45),
      lc_host_data(44) => lc_host_data(44),
      lc_host_data(43) => lc_host_data(43),
      lc_host_data(42) => lc_host_data(42),
      lc_host_data(41) => lc_host_data(41),
      lc_host_data(40) => lc_host_data(40),
      lc_host_data(39) => lc_host_data(39),
      lc_host_data(38) => lc_host_data(38),
      lc_host_data(37) => lc_host_data(37),
      lc_host_data(36) => lc_host_data(36),
      lc_host_data(35) => lc_host_data(35),
      lc_host_data(34) => lc_host_data(34),
      lc_host_data(33) => lc_host_data(33),
      lc_host_data(32) => lc_host_data(32),
      lc_host_data(31) => lc_host_data(31),
      lc_host_data(30) => lc_host_data(30),
      lc_host_data(29) => lc_host_data(29),
      lc_host_data(28) => lc_host_data(28),
      lc_host_data(27) => lc_host_data(27),
      lc_host_data(26) => lc_host_data(26),
      lc_host_data(25) => lc_host_data(25),
      lc_host_data(24) => lc_host_data(24),
      lc_host_data(23) => lc_host_data(23),
      lc_host_data(22) => lc_host_data(22),
      lc_host_data(21) => lc_host_data(21),
      lc_host_data(20) => lc_host_data(20),
      lc_host_data(19) => lc_host_data(19),
      lc_host_data(18) => lc_host_data(18),
      lc_host_data(17) => lc_host_data(17),
      lc_host_data(16) => lc_host_data(16),
      lc_host_data(15) => lc_host_data(15),
      lc_host_data(14) => lc_host_data(14),
      lc_host_data(13) => lc_host_data(13),
      lc_host_data(12) => lc_host_data(12),
      lc_host_data(11) => lc_host_data(11),
      lc_host_data(10) => lc_host_data(10),
      lc_host_data(9) => lc_host_data(9),
      lc_host_data(8) => lc_host_data(8),
      lc_host_data(7) => lc_host_data(7),
      lc_host_data(6) => lc_host_data(6),
      lc_host_data(5) => lc_host_data(5),
      lc_host_data(4) => lc_host_data(4),
      lc_host_data(3) => lc_host_data(3),
      lc_host_data(2) => lc_host_data(2),
      lc_host_data(1) => lc_host_data(1),
      lc_host_data(0) => lc_host_data(0),
      lc_adr(31) => lc_adr(31),
      lc_adr(30) => lc_adr(30),
      lc_adr(29) => lc_adr(29),
      lc_adr(28) => lc_adr(28),
      lc_adr(27) => lc_adr(27),
      lc_adr(26) => lc_adr(26),
      lc_adr(25) => lc_adr(25),
      lc_adr(24) => lc_adr(24),
      lc_adr(23) => lc_adr(23),
      lc_adr(22) => lc_adr(22),
      lc_adr(21) => lc_adr(21),
      lc_adr(20) => lc_adr(20),
      lc_adr(19) => lc_adr(19),
      lc_adr(18) => lc_adr(18),
      lc_adr(17) => lc_adr(17),
      lc_adr(16) => lc_adr(16),
      lc_adr(15) => lc_adr(15),
      lc_adr(14) => lc_adr(14),
      lc_adr(13) => lc_adr(13),
      lc_adr(12) => lc_adr(12),
      lc_adr(11) => lc_adr(11),
      lc_adr(10) => lc_adr(10),
      lc_adr(9) => lc_adr(9),
      lc_adr(8) => lc_adr(8),
      lc_adr(7) => lc_adr(7),
      lc_adr(6) => lc_adr(6),
      lc_adr(5) => lc_adr(5),
      lc_adr(4) => lc_adr(4),
      lc_adr(3) => lc_adr(3),
      lc_adr(2) => lc_adr(2),
      lc_adr(1) => lc_adr(1),
      lc_adr(0) => lc_adr(0),
      pb_slave_data(63) => pb_slave_data(63),
      pb_slave_data(62) => pb_slave_data(62),
      pb_slave_data(61) => pb_slave_data(61),
      pb_slave_data(60) => pb_slave_data(60),
      pb_slave_data(59) => pb_slave_data(59),
      pb_slave_data(58) => pb_slave_data(58),
      pb_slave_data(57) => pb_slave_data(57),
      pb_slave_data(56) => pb_slave_data(56),
      pb_slave_data(55) => pb_slave_data(55),
      pb_slave_data(54) => pb_slave_data(54),
      pb_slave_data(53) => pb_slave_data(53),
      pb_slave_data(52) => pb_slave_data(52),
      pb_slave_data(51) => pb_slave_data(51),
      pb_slave_data(50) => pb_slave_data(50),
      pb_slave_data(49) => pb_slave_data(49),
      pb_slave_data(48) => pb_slave_data(48),
      pb_slave_data(47) => pb_slave_data(47),
      pb_slave_data(46) => pb_slave_data(46),
      pb_slave_data(45) => pb_slave_data(45),
      pb_slave_data(44) => pb_slave_data(44),
      pb_slave_data(43) => pb_slave_data(43),
      pb_slave_data(42) => pb_slave_data(42),
      pb_slave_data(41) => pb_slave_data(41),
      pb_slave_data(40) => pb_slave_data(40),
      pb_slave_data(39) => pb_slave_data(39),
      pb_slave_data(38) => pb_slave_data(38),
      pb_slave_data(37) => pb_slave_data(37),
      pb_slave_data(36) => pb_slave_data(36),
      pb_slave_data(35) => pb_slave_data(35),
      pb_slave_data(34) => pb_slave_data(34),
      pb_slave_data(33) => pb_slave_data(33),
      pb_slave_data(32) => pb_slave_data(32),
      pb_slave_data(31) => pb_slave_data(31),
      pb_slave_data(30) => pb_slave_data(30),
      pb_slave_data(29) => pb_slave_data(29),
      pb_slave_data(28) => pb_slave_data(28),
      pb_slave_data(27) => pb_slave_data(27),
      pb_slave_data(26) => pb_slave_data(26),
      pb_slave_data(25) => pb_slave_data(25),
      pb_slave_data(24) => pb_slave_data(24),
      pb_slave_data(23) => pb_slave_data(23),
      pb_slave_data(22) => pb_slave_data(22),
      pb_slave_data(21) => pb_slave_data(21),
      pb_slave_data(20) => pb_slave_data(20),
      pb_slave_data(19) => pb_slave_data(19),
      pb_slave_data(18) => pb_slave_data(18),
      pb_slave_data(17) => pb_slave_data(17),
      pb_slave_data(16) => pb_slave_data(16),
      pb_slave_data(15) => pb_slave_data(15),
      pb_slave_data(14) => pb_slave_data(14),
      pb_slave_data(13) => pb_slave_data(13),
      pb_slave_data(12) => pb_slave_data(12),
      pb_slave_data(11) => pb_slave_data(11),
      pb_slave_data(10) => pb_slave_data(10),
      pb_slave_data(9) => pb_slave_data(9),
      pb_slave_data(8) => pb_slave_data(8),
      pb_slave_data(7) => pb_slave_data(7),
      pb_slave_data(6) => pb_slave_data(6),
      pb_slave_data(5) => pb_slave_data(5),
      pb_slave_data(4) => pb_slave_data(4),
      pb_slave_data(3) => pb_slave_data(3),
      pb_slave_data(2) => pb_slave_data(2),
      pb_slave_data(1) => pb_slave_data(1),
      pb_slave_data(0) => pb_slave_data(0),
      pb_slave_dmar(1) => pb_slave_dmar(1),
      pb_slave_dmar(0) => pb_slave_dmar(0),
      lc_data(63) => lc_data(63),
      lc_data(62) => lc_data(62),
      lc_data(61) => lc_data(61),
      lc_data(60) => lc_data(60),
      lc_data(59) => lc_data(59),
      lc_data(58) => lc_data(58),
      lc_data(57) => lc_data(57),
      lc_data(56) => lc_data(56),
      lc_data(55) => lc_data(55),
      lc_data(54) => lc_data(54),
      lc_data(53) => lc_data(53),
      lc_data(52) => lc_data(52),
      lc_data(51) => lc_data(51),
      lc_data(50) => lc_data(50),
      lc_data(49) => lc_data(49),
      lc_data(48) => lc_data(48),
      lc_data(47) => lc_data(47),
      lc_data(46) => lc_data(46),
      lc_data(45) => lc_data(45),
      lc_data(44) => lc_data(44),
      lc_data(43) => lc_data(43),
      lc_data(42) => lc_data(42),
      lc_data(41) => lc_data(41),
      lc_data(40) => lc_data(40),
      lc_data(39) => lc_data(39),
      lc_data(38) => lc_data(38),
      lc_data(37) => lc_data(37),
      lc_data(36) => lc_data(36),
      lc_data(35) => lc_data(35),
      lc_data(34) => lc_data(34),
      lc_data(33) => lc_data(33),
      lc_data(32) => lc_data(32),
      lc_data(31) => lc_data(31),
      lc_data(30) => lc_data(30),
      lc_data(29) => lc_data(29),
      lc_data(28) => lc_data(28),
      lc_data(27) => lc_data(27),
      lc_data(26) => lc_data(26),
      lc_data(25) => lc_data(25),
      lc_data(24) => lc_data(24),
      lc_data(23) => lc_data(23),
      lc_data(22) => lc_data(22),
      lc_data(21) => lc_data(21),
      lc_data(20) => lc_data(20),
      lc_data(19) => lc_data(19),
      lc_data(18) => lc_data(18),
      lc_data(17) => lc_data(17),
      lc_data(16) => lc_data(16),
      lc_data(15) => lc_data(15),
      lc_data(14) => lc_data(14),
      lc_data(13) => lc_data(13),
      lc_data(12) => lc_data(12),
      lc_data(11) => lc_data(11),
      lc_data(10) => lc_data(10),
      lc_data(9) => lc_data(9),
      lc_data(8) => lc_data(8),
      lc_data(7) => lc_data(7),
      lc_data(6) => lc_data(6),
      lc_data(5) => lc_data(5),
      lc_data(4) => lc_data(4),
      lc_data(3) => lc_data(3),
      lc_data(2) => lc_data(2),
      lc_data(1) => lc_data(1),
      lc_data(0) => lc_data(0),
      pb_master_data(63) => pb_master_data(63),
      pb_master_data(62) => pb_master_data(62),
      pb_master_data(61) => pb_master_data(61),
      pb_master_data(60) => pb_master_data(60),
      pb_master_data(59) => pb_master_data(59),
      pb_master_data(58) => pb_master_data(58),
      pb_master_data(57) => pb_master_data(57),
      pb_master_data(56) => pb_master_data(56),
      pb_master_data(55) => pb_master_data(55),
      pb_master_data(54) => pb_master_data(54),
      pb_master_data(53) => pb_master_data(53),
      pb_master_data(52) => pb_master_data(52),
      pb_master_data(51) => pb_master_data(51),
      pb_master_data(50) => pb_master_data(50),
      pb_master_data(49) => pb_master_data(49),
      pb_master_data(48) => pb_master_data(48),
      pb_master_data(47) => pb_master_data(47),
      pb_master_data(46) => pb_master_data(46),
      pb_master_data(45) => pb_master_data(45),
      pb_master_data(44) => pb_master_data(44),
      pb_master_data(43) => pb_master_data(43),
      pb_master_data(42) => pb_master_data(42),
      pb_master_data(41) => pb_master_data(41),
      pb_master_data(40) => pb_master_data(40),
      pb_master_data(39) => pb_master_data(39),
      pb_master_data(38) => pb_master_data(38),
      pb_master_data(37) => pb_master_data(37),
      pb_master_data(36) => pb_master_data(36),
      pb_master_data(35) => pb_master_data(35),
      pb_master_data(34) => pb_master_data(34),
      pb_master_data(33) => pb_master_data(33),
      pb_master_data(32) => pb_master_data(32),
      pb_master_data(31) => pb_master_data(31),
      pb_master_data(30) => pb_master_data(30),
      pb_master_data(29) => pb_master_data(29),
      pb_master_data(28) => pb_master_data(28),
      pb_master_data(27) => pb_master_data(27),
      pb_master_data(26) => pb_master_data(26),
      pb_master_data(25) => pb_master_data(25),
      pb_master_data(24) => pb_master_data(24),
      pb_master_data(23) => pb_master_data(23),
      pb_master_data(22) => pb_master_data(22),
      pb_master_data(21) => pb_master_data(21),
      pb_master_data(20) => pb_master_data(20),
      pb_master_data(19) => pb_master_data(19),
      pb_master_data(18) => pb_master_data(18),
      pb_master_data(17) => pb_master_data(17),
      pb_master_data(16) => pb_master_data(16),
      pb_master_data(15) => pb_master_data(15),
      pb_master_data(14) => pb_master_data(14),
      pb_master_data(13) => pb_master_data(13),
      pb_master_data(12) => pb_master_data(12),
      pb_master_data(11) => pb_master_data(11),
      pb_master_data(10) => pb_master_data(10),
      pb_master_data(9) => pb_master_data(9),
      pb_master_data(8) => pb_master_data(8),
      pb_master_data(7) => pb_master_data(7),
      pb_master_data(6) => pb_master_data(6),
      pb_master_data(5) => pb_master_data(5),
      pb_master_data(4) => pb_master_data(4),
      pb_master_data(3) => pb_master_data(3),
      pb_master_data(2) => pb_master_data(2),
      pb_master_data(1) => pb_master_data(1),
      pb_master_data(0) => pb_master_data(0),
      pb_master_adr(31) => pb_master_adr(31),
      pb_master_adr(30) => pb_master_adr(30),
      pb_master_adr(29) => pb_master_adr(29),
      pb_master_adr(28) => pb_master_adr(28),
      pb_master_adr(27) => pb_master_adr(27),
      pb_master_adr(26) => pb_master_adr(26),
      pb_master_adr(25) => pb_master_adr(25),
      pb_master_adr(24) => pb_master_adr(24),
      pb_master_adr(23) => pb_master_adr(23),
      pb_master_adr(22) => pb_master_adr(22),
      pb_master_adr(21) => pb_master_adr(21),
      pb_master_adr(20) => pb_master_adr(20),
      pb_master_adr(19) => pb_master_adr(19),
      pb_master_adr(18) => pb_master_adr(18),
      pb_master_adr(17) => pb_master_adr(17),
      pb_master_adr(16) => pb_master_adr(16),
      pb_master_adr(15) => pb_master_adr(15),
      pb_master_adr(14) => pb_master_adr(14),
      pb_master_adr(13) => pb_master_adr(13),
      pb_master_adr(12) => pb_master_adr(12),
      pb_master_adr(11) => pb_master_adr(11),
      pb_master_adr(10) => pb_master_adr(10),
      pb_master_adr(9) => pb_master_adr(9),
      pb_master_adr(8) => pb_master_adr(8),
      pb_master_adr(7) => pb_master_adr(7),
      pb_master_adr(6) => pb_master_adr(6),
      pb_master_adr(5) => pb_master_adr(5),
      pb_master_adr(4) => pb_master_adr(4),
      pb_master_adr(3) => pb_master_adr(3),
      pb_master_adr(2) => pb_master_adr(2),
      pb_master_adr(1) => pb_master_adr(1),
      pb_master_adr(0) => pb_master_adr(0),
      lc_dma_req(1) => lc_dma_req(1),
      lc_dma_req(0) => lc_dma_req(0),
      pb_master_cmd(2) => pb_master_cmd(2),
      pb_master_cmd(1) => pb_master_cmd(1),
      pb_master_cmd(0) => pb_master_cmd(0)
    );
  main : block_pe_main
    port map (
      clk => NlwRenamedSig_OI_clk250_out,
      pb_reset => NLW_main_pb_reset_UNCONNECTED,
      bl_data_we => bp_we(0),
      reset_hr1 => NlwRenamedSig_OI_reset_out,
      bl_data_out(31) => bp0_data(31),
      bl_data_out(30) => bp0_data(30),
      bl_data_out(29) => bp0_data(29),
      bl_data_out(28) => bp0_data(28),
      bl_data_out(27) => bp0_data(27),
      bl_data_out(26) => bp0_data(26),
      bl_data_out(25) => bp0_data(25),
      bl_data_out(24) => bp0_data(24),
      bl_data_out(23) => bp0_data(23),
      bl_data_out(22) => bp0_data(22),
      bl_data_out(21) => bp0_data(21),
      bl_data_out(20) => bp0_data(20),
      bl_data_out(19) => bp0_data(19),
      bl_data_out(18) => bp0_data(18),
      bl_data_out(17) => bp0_data(17),
      bl_data_out(16) => bp0_data(16),
      bl_data_out(15) => bp0_data(15),
      bl_data_out(14) => bp0_data(14),
      bl_data_out(13) => bp0_data(13),
      bl_data_out(12) => bp0_data(12),
      bl_data_out(11) => bp0_data(11),
      bl_data_out(10) => bp0_data(10),
      bl_data_out(9) => bp0_data(9),
      bl_data_out(8) => bp0_data(8),
      bl_data_out(7) => bp0_data(7),
      bl_data_out(6) => bp0_data(6),
      bl_data_out(5) => bp0_data(5),
      bl_data_out(4) => bp0_data(4),
      bl_data_out(3) => bp0_data(3),
      bl_data_out(2) => bp0_data(2),
      bl_data_out(1) => bp0_data(1),
      bl_data_out(0) => bp0_data(0),
      brd_mode(15) => NLW_main_brd_mode_15_UNCONNECTED,
      brd_mode(14) => NLW_main_brd_mode_14_UNCONNECTED,
      brd_mode(13) => NLW_main_brd_mode_13_UNCONNECTED,
      brd_mode(12) => NLW_main_brd_mode_12_UNCONNECTED,
      brd_mode(11) => NLW_main_brd_mode_11_UNCONNECTED,
      brd_mode(10) => NLW_main_brd_mode_10_UNCONNECTED,
      brd_mode(9) => NLW_main_brd_mode_9_UNCONNECTED,
      brd_mode(8) => NLW_main_brd_mode_8_UNCONNECTED,
      brd_mode(7) => NLW_main_brd_mode_7_UNCONNECTED,
      brd_mode(6) => NLW_main_brd_mode_6_UNCONNECTED,
      brd_mode(5) => NLW_main_brd_mode_5_UNCONNECTED,
      brd_mode(4) => NLW_main_brd_mode_4_UNCONNECTED,
      brd_mode(3) => NLW_main_brd_mode_3_UNCONNECTED,
      brd_mode(2) => NLW_main_brd_mode_2_UNCONNECTED,
      brd_mode(1) => NLW_main_brd_mode_1_UNCONNECTED,
      brd_mode(0) => NLW_main_brd_mode_0_UNCONNECTED,
      bl_adr(4) => bp_adr(4),
      bl_adr(3) => bp_adr(3),
      bl_adr(2) => bp_adr(2),
      bl_adr(1) => bp_adr(1),
      bl_adr(0) => bp_adr(0),
      bl_data_in(31) => bp_host_data(31),
      bl_data_in(30) => bp_host_data(30),
      bl_data_in(29) => bp_host_data(29),
      bl_data_in(28) => bp_host_data(28),
      bl_data_in(27) => bp_host_data(27),
      bl_data_in(26) => bp_host_data(26),
      bl_data_in(25) => bp_host_data(25),
      bl_data_in(24) => bp_host_data(24),
      bl_data_in(23) => bp_host_data(23),
      bl_data_in(22) => bp_host_data(22),
      bl_data_in(21) => bp_host_data(21),
      bl_data_in(20) => bp_host_data(20),
      bl_data_in(19) => bp_host_data(19),
      bl_data_in(18) => bp_host_data(18),
      bl_data_in(17) => bp_host_data(17),
      bl_data_in(16) => bp_host_data(16),
      bl_data_in(15) => bp_host_data(15),
      bl_data_in(14) => bp_host_data(14),
      bl_data_in(13) => bp_host_data(13),
      bl_data_in(12) => bp_host_data(12),
      bl_data_in(11) => bp_host_data(11),
      bl_data_in(10) => bp_host_data(10),
      bl_data_in(9) => bp_host_data(9),
      bl_data_in(8) => bp_host_data(8),
      bl_data_in(7) => bp_host_data(7),
      bl_data_in(6) => bp_host_data(6),
      bl_data_in(5) => bp_host_data(5),
      bl_data_in(4) => bp_host_data(4),
      bl_data_in(3) => bp_host_data(3),
      bl_data_in(2) => bp_host_data(2),
      bl_data_in(1) => bp_host_data(1),
      bl_data_in(0) => bp_host_data(0)
    );
  core : pcie_core64_m1
    port map (
      bp_reg_rd => NLW_core_bp_reg_rd_UNCONNECTED,
      clk_out => NlwRenamedSig_OI_clk250_out,
      pb_master_stb0 => pb_master_stb0,
      pb_master_stb1 => pb_master_stb1,
      aclk => clk,
      bp_reg_we => NLW_core_bp_reg_we_UNCONNECTED,
      mgt250 => mgt250,
      aclk_lock => NLW_core_aclk_lock_UNCONNECTED,
      bp_irq => NLW_core_bp_irq_UNCONNECTED,
      pb_slave_stb0 => pb_slave_stb0,
      pb_slave_stb1 => pb_slave_stb1,
      pcie_link_up => pcie_link_up,
      reset_out => NlwRenamedSig_OI_reset_out,
      pb_slave_irq => pb_slave_irq,
      perst => perst,
      dcm_rstp => dcm_rstp,
      bp_sel(1) => bp_sel(1),
      bp_sel(0) => bp_sel(0),
      bp_host_data(31) => bp_host_data(31),
      bp_host_data(30) => bp_host_data(30),
      bp_host_data(29) => bp_host_data(29),
      bp_host_data(28) => bp_host_data(28),
      bp_host_data(27) => bp_host_data(27),
      bp_host_data(26) => bp_host_data(26),
      bp_host_data(25) => bp_host_data(25),
      bp_host_data(24) => bp_host_data(24),
      bp_host_data(23) => bp_host_data(23),
      bp_host_data(22) => bp_host_data(22),
      bp_host_data(21) => bp_host_data(21),
      bp_host_data(20) => bp_host_data(20),
      bp_host_data(19) => bp_host_data(19),
      bp_host_data(18) => bp_host_data(18),
      bp_host_data(17) => bp_host_data(17),
      bp_host_data(16) => bp_host_data(16),
      bp_host_data(15) => bp_host_data(15),
      bp_host_data(14) => bp_host_data(14),
      bp_host_data(13) => bp_host_data(13),
      bp_host_data(12) => bp_host_data(12),
      bp_host_data(11) => bp_host_data(11),
      bp_host_data(10) => bp_host_data(10),
      bp_host_data(9) => bp_host_data(9),
      bp_host_data(8) => bp_host_data(8),
      bp_host_data(7) => bp_host_data(7),
      bp_host_data(6) => bp_host_data(6),
      bp_host_data(5) => bp_host_data(5),
      bp_host_data(4) => bp_host_data(4),
      bp_host_data(3) => bp_host_data(3),
      bp_host_data(2) => bp_host_data(2),
      bp_host_data(1) => bp_host_data(1),
      bp_host_data(0) => bp_host_data(0),
      bp_rd(3) => NLW_core_bp_rd_3_UNCONNECTED,
      bp_rd(2) => NLW_core_bp_rd_2_UNCONNECTED,
      bp_rd(1) => NLW_core_bp_rd_1_UNCONNECTED,
      bp_rd(0) => NLW_core_bp_rd_0_UNCONNECTED,
      bp_we(3) => NLW_core_bp_we_3_UNCONNECTED,
      bp_we(2) => NLW_core_bp_we_2_UNCONNECTED,
      bp_we(1) => NLW_core_bp_we_1_UNCONNECTED,
      bp_we(0) => bp_we(0),
      pb_master_data(63) => pb_master_data(63),
      pb_master_data(62) => pb_master_data(62),
      pb_master_data(61) => pb_master_data(61),
      pb_master_data(60) => pb_master_data(60),
      pb_master_data(59) => pb_master_data(59),
      pb_master_data(58) => pb_master_data(58),
      pb_master_data(57) => pb_master_data(57),
      pb_master_data(56) => pb_master_data(56),
      pb_master_data(55) => pb_master_data(55),
      pb_master_data(54) => pb_master_data(54),
      pb_master_data(53) => pb_master_data(53),
      pb_master_data(52) => pb_master_data(52),
      pb_master_data(51) => pb_master_data(51),
      pb_master_data(50) => pb_master_data(50),
      pb_master_data(49) => pb_master_data(49),
      pb_master_data(48) => pb_master_data(48),
      pb_master_data(47) => pb_master_data(47),
      pb_master_data(46) => pb_master_data(46),
      pb_master_data(45) => pb_master_data(45),
      pb_master_data(44) => pb_master_data(44),
      pb_master_data(43) => pb_master_data(43),
      pb_master_data(42) => pb_master_data(42),
      pb_master_data(41) => pb_master_data(41),
      pb_master_data(40) => pb_master_data(40),
      pb_master_data(39) => pb_master_data(39),
      pb_master_data(38) => pb_master_data(38),
      pb_master_data(37) => pb_master_data(37),
      pb_master_data(36) => pb_master_data(36),
      pb_master_data(35) => pb_master_data(35),
      pb_master_data(34) => pb_master_data(34),
      pb_master_data(33) => pb_master_data(33),
      pb_master_data(32) => pb_master_data(32),
      pb_master_data(31) => pb_master_data(31),
      pb_master_data(30) => pb_master_data(30),
      pb_master_data(29) => pb_master_data(29),
      pb_master_data(28) => pb_master_data(28),
      pb_master_data(27) => pb_master_data(27),
      pb_master_data(26) => pb_master_data(26),
      pb_master_data(25) => pb_master_data(25),
      pb_master_data(24) => pb_master_data(24),
      pb_master_data(23) => pb_master_data(23),
      pb_master_data(22) => pb_master_data(22),
      pb_master_data(21) => pb_master_data(21),
      pb_master_data(20) => pb_master_data(20),
      pb_master_data(19) => pb_master_data(19),
      pb_master_data(18) => pb_master_data(18),
      pb_master_data(17) => pb_master_data(17),
      pb_master_data(16) => pb_master_data(16),
      pb_master_data(15) => pb_master_data(15),
      pb_master_data(14) => pb_master_data(14),
      pb_master_data(13) => pb_master_data(13),
      pb_master_data(12) => pb_master_data(12),
      pb_master_data(11) => pb_master_data(11),
      pb_master_data(10) => pb_master_data(10),
      pb_master_data(9) => pb_master_data(9),
      pb_master_data(8) => pb_master_data(8),
      pb_master_data(7) => pb_master_data(7),
      pb_master_data(6) => pb_master_data(6),
      pb_master_data(5) => pb_master_data(5),
      pb_master_data(4) => pb_master_data(4),
      pb_master_data(3) => pb_master_data(3),
      pb_master_data(2) => pb_master_data(2),
      pb_master_data(1) => pb_master_data(1),
      pb_master_data(0) => pb_master_data(0),
      px(7) => px(7),
      px(6) => px(6),
      px(5) => px(5),
      px(4) => px(4),
      px(3) => px(3),
      px(2) => px(2),
      px(1) => px(1),
      px(0) => px(0),
      pb_master_adr(31) => pb_master_adr(31),
      pb_master_adr(30) => pb_master_adr(30),
      pb_master_adr(29) => pb_master_adr(29),
      pb_master_adr(28) => pb_master_adr(28),
      pb_master_adr(27) => pb_master_adr(27),
      pb_master_adr(26) => pb_master_adr(26),
      pb_master_adr(25) => pb_master_adr(25),
      pb_master_adr(24) => pb_master_adr(24),
      pb_master_adr(23) => pb_master_adr(23),
      pb_master_adr(22) => pb_master_adr(22),
      pb_master_adr(21) => pb_master_adr(21),
      pb_master_adr(20) => pb_master_adr(20),
      pb_master_adr(19) => pb_master_adr(19),
      pb_master_adr(18) => pb_master_adr(18),
      pb_master_adr(17) => pb_master_adr(17),
      pb_master_adr(16) => pb_master_adr(16),
      pb_master_adr(15) => pb_master_adr(15),
      pb_master_adr(14) => pb_master_adr(14),
      pb_master_adr(13) => pb_master_adr(13),
      pb_master_adr(12) => pb_master_adr(12),
      pb_master_adr(11) => pb_master_adr(11),
      pb_master_adr(10) => pb_master_adr(10),
      pb_master_adr(9) => pb_master_adr(9),
      pb_master_adr(8) => pb_master_adr(8),
      pb_master_adr(7) => pb_master_adr(7),
      pb_master_adr(6) => pb_master_adr(6),
      pb_master_adr(5) => pb_master_adr(5),
      pb_master_adr(4) => pb_master_adr(4),
      pb_master_adr(3) => pb_master_adr(3),
      pb_master_adr(2) => pb_master_adr(2),
      pb_master_adr(1) => pb_master_adr(1),
      pb_master_adr(0) => pb_master_adr(0),
      txn(7) => txn(7),
      txn(6) => txn(6),
      txn(5) => txn(5),
      txn(4) => txn(4),
      txn(3) => txn(3),
      txn(2) => txn(2),
      txn(1) => txn(1),
      txn(0) => txn(0),
      txp(7) => txp(7),
      txp(6) => txp(6),
      txp(5) => txp(5),
      txp(4) => txp(4),
      txp(3) => txp(3),
      txp(2) => txp(2),
      txp(1) => txp(1),
      txp(0) => txp(0),
      bp_adr(19) => NLW_core_bp_adr_19_UNCONNECTED,
      bp_adr(18) => NLW_core_bp_adr_18_UNCONNECTED,
      bp_adr(17) => NLW_core_bp_adr_17_UNCONNECTED,
      bp_adr(16) => NLW_core_bp_adr_16_UNCONNECTED,
      bp_adr(15) => NLW_core_bp_adr_15_UNCONNECTED,
      bp_adr(14) => NLW_core_bp_adr_14_UNCONNECTED,
      bp_adr(13) => NLW_core_bp_adr_13_UNCONNECTED,
      bp_adr(12) => NLW_core_bp_adr_12_UNCONNECTED,
      bp_adr(11) => NLW_core_bp_adr_11_UNCONNECTED,
      bp_adr(10) => NLW_core_bp_adr_10_UNCONNECTED,
      bp_adr(9) => NLW_core_bp_adr_9_UNCONNECTED,
      bp_adr(8) => NLW_core_bp_adr_8_UNCONNECTED,
      bp_adr(7) => NLW_core_bp_adr_7_UNCONNECTED,
      bp_adr(6) => NLW_core_bp_adr_6_UNCONNECTED,
      bp_adr(5) => NLW_core_bp_adr_5_UNCONNECTED,
      bp_adr(4) => bp_adr(4),
      bp_adr(3) => bp_adr(3),
      bp_adr(2) => bp_adr(2),
      bp_adr(1) => bp_adr(1),
      bp_adr(0) => bp_adr(0),
      pb_master_cmd(2) => pb_master_cmd(2),
      pb_master_cmd(1) => pb_master_cmd(1),
      pb_master_cmd(0) => pb_master_cmd(0),
      pcie_lstatus(15) => pcie_lstatus(15),
      pcie_lstatus(14) => pcie_lstatus(14),
      pcie_lstatus(13) => pcie_lstatus(13),
      pcie_lstatus(12) => pcie_lstatus(12),
      pcie_lstatus(11) => pcie_lstatus(11),
      pcie_lstatus(10) => pcie_lstatus(10),
      pcie_lstatus(9) => pcie_lstatus(9),
      pcie_lstatus(8) => pcie_lstatus(8),
      pcie_lstatus(7) => pcie_lstatus(7),
      pcie_lstatus(6) => pcie_lstatus(6),
      pcie_lstatus(5) => pcie_lstatus(5),
      pcie_lstatus(4) => pcie_lstatus(4),
      pcie_lstatus(3) => pcie_lstatus(3),
      pcie_lstatus(2) => pcie_lstatus(2),
      pcie_lstatus(1) => pcie_lstatus(1),
      pcie_lstatus(0) => pcie_lstatus(0),
      bp_data(31) => bp_data(31),
      bp_data(30) => bp_data(30),
      bp_data(29) => bp_data(29),
      bp_data(28) => bp_data(28),
      bp_data(27) => bp_data(27),
      bp_data(26) => bp_data(26),
      bp_data(25) => bp_data(25),
      bp_data(24) => bp_data(24),
      bp_data(23) => bp_data(23),
      bp_data(22) => bp_data(22),
      bp_data(21) => bp_data(21),
      bp_data(20) => bp_data(20),
      bp_data(19) => bp_data(19),
      bp_data(18) => bp_data(18),
      bp_data(17) => bp_data(17),
      bp_data(16) => bp_data(16),
      bp_data(15) => bp_data(15),
      bp_data(14) => bp_data(14),
      bp_data(13) => bp_data(13),
      bp_data(12) => bp_data(12),
      bp_data(11) => bp_data(11),
      bp_data(10) => bp_data(10),
      bp_data(9) => bp_data(9),
      bp_data(8) => bp_data(8),
      bp_data(7) => bp_data(7),
      bp_data(6) => bp_data(6),
      bp_data(5) => bp_data(5),
      bp_data(4) => bp_data(4),
      bp_data(3) => bp_data(3),
      bp_data(2) => bp_data(2),
      bp_data(1) => bp_data(1),
      bp_data(0) => bp_data(0),
      rxn(7) => rxn(7),
      rxn(6) => rxn(6),
      rxn(5) => rxn(5),
      rxn(4) => rxn(4),
      rxn(3) => rxn(3),
      rxn(2) => rxn(2),
      rxn(1) => rxn(1),
      rxn(0) => rxn(0),
      rxp(7) => rxp(7),
      rxp(6) => rxp(6),
      rxp(5) => rxp(5),
      rxp(4) => rxp(4),
      rxp(3) => rxp(3),
      rxp(2) => rxp(2),
      rxp(1) => rxp(1),
      rxp(0) => rxp(0),
      pb_slave_data(63) => pb_slave_data(63),
      pb_slave_data(62) => pb_slave_data(62),
      pb_slave_data(61) => pb_slave_data(61),
      pb_slave_data(60) => pb_slave_data(60),
      pb_slave_data(59) => pb_slave_data(59),
      pb_slave_data(58) => pb_slave_data(58),
      pb_slave_data(57) => pb_slave_data(57),
      pb_slave_data(56) => pb_slave_data(56),
      pb_slave_data(55) => pb_slave_data(55),
      pb_slave_data(54) => pb_slave_data(54),
      pb_slave_data(53) => pb_slave_data(53),
      pb_slave_data(52) => pb_slave_data(52),
      pb_slave_data(51) => pb_slave_data(51),
      pb_slave_data(50) => pb_slave_data(50),
      pb_slave_data(49) => pb_slave_data(49),
      pb_slave_data(48) => pb_slave_data(48),
      pb_slave_data(47) => pb_slave_data(47),
      pb_slave_data(46) => pb_slave_data(46),
      pb_slave_data(45) => pb_slave_data(45),
      pb_slave_data(44) => pb_slave_data(44),
      pb_slave_data(43) => pb_slave_data(43),
      pb_slave_data(42) => pb_slave_data(42),
      pb_slave_data(41) => pb_slave_data(41),
      pb_slave_data(40) => pb_slave_data(40),
      pb_slave_data(39) => pb_slave_data(39),
      pb_slave_data(38) => pb_slave_data(38),
      pb_slave_data(37) => pb_slave_data(37),
      pb_slave_data(36) => pb_slave_data(36),
      pb_slave_data(35) => pb_slave_data(35),
      pb_slave_data(34) => pb_slave_data(34),
      pb_slave_data(33) => pb_slave_data(33),
      pb_slave_data(32) => pb_slave_data(32),
      pb_slave_data(31) => pb_slave_data(31),
      pb_slave_data(30) => pb_slave_data(30),
      pb_slave_data(29) => pb_slave_data(29),
      pb_slave_data(28) => pb_slave_data(28),
      pb_slave_data(27) => pb_slave_data(27),
      pb_slave_data(26) => pb_slave_data(26),
      pb_slave_data(25) => pb_slave_data(25),
      pb_slave_data(24) => pb_slave_data(24),
      pb_slave_data(23) => pb_slave_data(23),
      pb_slave_data(22) => pb_slave_data(22),
      pb_slave_data(21) => pb_slave_data(21),
      pb_slave_data(20) => pb_slave_data(20),
      pb_slave_data(19) => pb_slave_data(19),
      pb_slave_data(18) => pb_slave_data(18),
      pb_slave_data(17) => pb_slave_data(17),
      pb_slave_data(16) => pb_slave_data(16),
      pb_slave_data(15) => pb_slave_data(15),
      pb_slave_data(14) => pb_slave_data(14),
      pb_slave_data(13) => pb_slave_data(13),
      pb_slave_data(12) => pb_slave_data(12),
      pb_slave_data(11) => pb_slave_data(11),
      pb_slave_data(10) => pb_slave_data(10),
      pb_slave_data(9) => pb_slave_data(9),
      pb_slave_data(8) => pb_slave_data(8),
      pb_slave_data(7) => pb_slave_data(7),
      pb_slave_data(6) => pb_slave_data(6),
      pb_slave_data(5) => pb_slave_data(5),
      pb_slave_data(4) => pb_slave_data(4),
      pb_slave_data(3) => pb_slave_data(3),
      pb_slave_data(2) => pb_slave_data(2),
      pb_slave_data(1) => pb_slave_data(1),
      pb_slave_data(0) => pb_slave_data(0),
      pb_slave_dmar(1) => pb_slave_dmar(1),
      pb_slave_dmar(0) => pb_slave_dmar(0)
    );
  bp_data_9_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(9),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(9)
    );
  bp_data_8_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(8),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(8)
    );
  bp_data_7_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(7),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(7)
    );
  bp_data_6_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(6),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(6)
    );
  bp_data_5_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(5),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(5)
    );
  bp_data_4_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(4),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(4)
    );
  bp_data_3_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(3),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(3)
    );
  bp_data_31_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(31),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(31)
    );
  bp_data_30_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(30),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(30)
    );
  bp_data_2_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(2),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(2)
    );
  bp_data_29_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(29),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(29)
    );
  bp_data_28_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(28),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(28)
    );
  bp_data_27_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(27),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(27)
    );
  bp_data_26_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(26),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(26)
    );
  bp_data_25_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(25),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(25)
    );
  bp_data_24_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(24),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(24)
    );
  bp_data_23_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(23),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(23)
    );
  bp_data_22_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(22),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(22)
    );
  bp_data_21_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(21),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(21)
    );
  bp_data_20_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(20),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(20)
    );
  bp_data_1_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(1),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(1)
    );
  bp_data_19_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(19),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(19)
    );
  bp_data_18_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(18),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(18)
    );
  bp_data_17_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(17),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(17)
    );
  bp_data_16_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(16),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(16)
    );
  bp_data_15_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(15),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(15)
    );
  bp_data_14_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(14),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(14)
    );
  bp_data_13_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(13),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(13)
    );
  bp_data_12_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(12),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(12)
    );
  bp_data_11_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(11),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(11)
    );
  bp_data_10_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(10),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(10)
    );
  bp_data_0_1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => bp0_data(0),
      I1 => bp_sel(0),
      I2 => bp_sel(1),
      O => bp_data(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_cmd_adr_cs is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_cmd_adr_cs;

architecture STRUCTURE of ctrl_adsp_v2_decode_cmd_adr_cs is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => adr(1),
      I1 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_ram_cs_2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    rd : in STD_LOGIC := 'X'; 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 8 ); 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_ram_cs_2;

architecture STRUCTURE of ctrl_adsp_v2_decode_ram_cs_2 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => cmd_adr(8),
      I1 => adr(0),
      I2 => adr(1),
      I3 => cmd_adr(9),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_ram_cs_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    rd : in STD_LOGIC := 'X'; 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 8 ); 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_ram_cs_1;

architecture STRUCTURE of ctrl_adsp_v2_decode_ram_cs_1 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => cmd_adr(8),
      I1 => adr(0),
      I2 => adr(1),
      I3 => cmd_adr(9),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_24 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_24;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_24 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => adr(2),
      I1 => adr(0),
      I2 => adr(1),
      I3 => wr,
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_23 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_23;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_23 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => adr(3),
      I1 => adr(4),
      I2 => adr(1),
      I3 => adr(2),
      I4 => wr,
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_22 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_22;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_22 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => adr(3),
      I1 => adr(4),
      I2 => adr(0),
      I3 => adr(2),
      I4 => wr,
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_24 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_24;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_24 is
  signal N01 : STD_LOGIC; 
  signal cs1_7848 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7848,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(4),
      I2 => adr(2),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7848
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_23 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_23;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_23 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(3),
      I3 => adr(4),
      I4 => adr(0),
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_22 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_22;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_22 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(1),
      I2 => rd,
      I3 => adr(3),
      I4 => adr(4),
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_21 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_21;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_21 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => adr(3),
      I1 => adr(4),
      I2 => adr(1),
      I3 => adr(0),
      I4 => wr,
      I5 => adr(2),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_20 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_20;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_20 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(4),
      I1 => adr(3),
      I2 => wr,
      I3 => adr(1),
      I4 => adr(0),
      I5 => adr(2),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_19 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_19;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_19 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(4),
      I1 => adr(3),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(1),
      I5 => adr(2),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_21 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_21;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_21 is
  signal N01 : STD_LOGIC; 
  signal cs1_7792 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7792,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFFFFFBFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(4),
      I2 => adr(3),
      I3 => adr(2),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7792
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_20 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_20;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_20 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => adr(3),
      I1 => adr(2),
      I2 => rd,
      I3 => adr(4),
      I4 => adr(0),
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_19 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_19;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_19 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(3),
      I1 => adr(1),
      I2 => adr(4),
      I3 => adr(2),
      I4 => rd,
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_18 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_18;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_18 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => adr(0),
      I1 => adr(4),
      I2 => adr(1),
      I3 => adr(2),
      I4 => wr,
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_17 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_17;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_17 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(4),
      I1 => adr(1),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(0),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_16 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_16;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_16 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(4),
      I1 => adr(0),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(1),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_18 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_18;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_18 is
  signal N01 : STD_LOGIC; 
  signal cs1_7736 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7736,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFBFFFFFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(4),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7736
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_17 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_17;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_17 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(1),
      I2 => rd,
      I3 => adr(4),
      I4 => adr(0),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_16 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_16;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_16 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(3),
      I2 => adr(4),
      I3 => adr(1),
      I4 => rd,
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_15 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_15;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_15 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(4),
      I1 => adr(1),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(2),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_14 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_14;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_14 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(1),
      I1 => adr(4),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(2),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_13 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_13;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_13 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(0),
      I1 => adr(4),
      I2 => wr,
      I3 => adr(1),
      I4 => adr(2),
      I5 => adr(3),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_15 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_15;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_15 is
  signal N01 : STD_LOGIC; 
  signal cs1_7680 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7680,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFFFFFFBFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(4),
      I2 => adr(2),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7680
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_14 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_14;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_14 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(4),
      I1 => adr(3),
      I2 => adr(0),
      I3 => adr(1),
      I4 => rd,
      I5 => adr(2),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_13 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_13;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_13 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(3),
      I3 => adr(1),
      I4 => adr(4),
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_12 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_12;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_12 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => adr(3),
      I1 => adr(0),
      I2 => adr(1),
      I3 => adr(2),
      I4 => wr,
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_11 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_11;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_11 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(1),
      I1 => adr(3),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(0),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_10 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_10;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_10 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(0),
      I1 => adr(3),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(1),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_12 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_12;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_12 is
  signal N01 : STD_LOGIC; 
  signal cs1_7624 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7624,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FBFFFFFFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(4),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7624
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_11 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_11;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_11 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFDFFFFFF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(4),
      I2 => rd,
      I3 => adr(3),
      I4 => adr(0),
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_10 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_10;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_10 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(1),
      I2 => adr(3),
      I3 => adr(4),
      I4 => rd,
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_9 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_9;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_9 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(1),
      I1 => adr(3),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(2),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_8 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_8;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_8 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(3),
      I1 => adr(1),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(2),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_7 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_7;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_7 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(3),
      I1 => adr(0),
      I2 => wr,
      I3 => adr(1),
      I4 => adr(2),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_9 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_9;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_9 is
  signal N01 : STD_LOGIC; 
  signal cs1_7568 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7568,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFFFFEFFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(4),
      I2 => adr(2),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7568
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_8 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_8;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_8 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(3),
      I1 => adr(1),
      I2 => adr(0),
      I3 => adr(4),
      I4 => rd,
      I5 => adr(2),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_7 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_7;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_7 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(1),
      I3 => adr(4),
      I4 => adr(3),
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_6 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_6;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_6 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => adr(1),
      I1 => adr(0),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_5 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_5;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_5 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(1),
      I1 => adr(2),
      I2 => wr,
      I3 => adr(0),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_4;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_4 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(0),
      I1 => adr(2),
      I2 => wr,
      I3 => adr(1),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_6 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_6;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_6 is
  signal N01 : STD_LOGIC; 
  signal cs1_7512 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7512,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFEFFFFFFFFFFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(4),
      I2 => adr(2),
      I3 => adr(3),
      I4 => N01,
      I5 => cmd_data_en,
      O => cs1_7512
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_5 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_5;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_5 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFDF"
    )
    port map (
      I0 => adr(2),
      I1 => adr(3),
      I2 => adr(0),
      I3 => adr(4),
      I4 => rd,
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_4;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_4 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(1),
      I2 => adr(3),
      I3 => adr(4),
      I4 => adr(2),
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_3 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_3;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_3 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => adr(1),
      I1 => adr(0),
      I2 => wr,
      I3 => adr(2),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_2;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_2 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => adr(1),
      I1 => wr,
      I2 => adr(0),
      I3 => adr(2),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_we_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    data_we : out STD_LOGIC; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_we_1;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_we_1 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_we
    );
  cs1_and00001 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => adr(0),
      I1 => wr,
      I2 => adr(1),
      I3 => adr(2),
      I4 => adr(3),
      I5 => adr(4),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_3 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_3;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_3 is
  signal N01 : STD_LOGIC; 
  signal cs1_7456 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1_7456,
      Q => data_cs
    );
  cs1_SW0 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => adr(0),
      I1 => adr(1),
      O => N01
    );
  cs1 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => adr(2),
      I1 => rd,
      I2 => adr(4),
      I3 => adr(3),
      I4 => cmd_data_en,
      I5 => N01,
      O => cs1_7456
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_2;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_2 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFEFFFF"
    )
    port map (
      I0 => rd,
      I1 => adr(2),
      I2 => adr(3),
      I3 => adr(4),
      I4 => adr(0),
      I5 => adr(1),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_adsp_v2_decode_data_cs_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : out STD_LOGIC; 
    cmd_data_en : in STD_LOGIC := 'X'; 
    rd : in STD_LOGIC := 'X'; 
    adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end ctrl_adsp_v2_decode_data_cs_1;

architecture STRUCTURE of ctrl_adsp_v2_decode_data_cs_1 is
  signal cs1 : STD_LOGIC; 
begin
  xd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => cs1,
      Q => data_cs
    );
  cs11 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => adr(1),
      I1 => adr(2),
      I2 => adr(3),
      I3 => adr(4),
      I4 => rd,
      I5 => adr(0),
      O => cs1
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity pb_adm_ctrl_m2 is
  port (
    trd_host_cmd_11_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_13_data_oe : out STD_LOGIC; 
    trd_host_cmd_6_cmd_data_cs : out STD_LOGIC; 
    trd_drq_14_req : in STD_LOGIC := 'X'; 
    trd_drq_14_en : in STD_LOGIC := 'X'; 
    drq1_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_2_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_9_data_cs : out STD_LOGIC; 
    trd_host_cmd_12_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_15_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_2_data_we : out STD_LOGIC; 
    trd_drq_15_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_cs : out STD_LOGIC; 
    trd_host_cmd_1_data_oe : out STD_LOGIC; 
    lc_wr : in STD_LOGIC := 'X'; 
    drq1_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_2_status_cs : out STD_LOGIC; 
    trd_host_cmd_13_data_we : out STD_LOGIC; 
    trd_host_cmd_11_data_cs : out STD_LOGIC; 
    trd_drq_3_en : in STD_LOGIC := 'X'; 
    trd_drq_0_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_data_oe : out STD_LOGIC; 
    trd_host_cmd_9_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_8_status_cs : out STD_LOGIC; 
    trd_drq_8_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_11_status_cs : out STD_LOGIC; 
    trd_drq_1_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_8_data_cs : out STD_LOGIC; 
    trd_host_cmd_9_data_oe : out STD_LOGIC; 
    trd_host_cmd_4_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_1_data_we : out STD_LOGIC; 
    drq3_ack : in STD_LOGIC := 'X'; 
    trd_drq_2_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_oe : out STD_LOGIC; 
    trd_host_cmd_15_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_14_cmd_adr_we : out STD_LOGIC; 
    trd_drq_3_ack : in STD_LOGIC := 'X'; 
    trd_drq_11_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_12_data_we : out STD_LOGIC; 
    trd_host_cmd_10_data_cs : out STD_LOGIC; 
    trd_host_cmd_11_data_oe : out STD_LOGIC; 
    trd_host_cmd_6_cmd_data_we : out STD_LOGIC; 
    trd_drq_4_ack : in STD_LOGIC := 'X'; 
    trd_drq_0_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_data_we : out STD_LOGIC; 
    trd_host_cmd_3_status_cs : out STD_LOGIC; 
    trd_host_cmd_7_data_cs : out STD_LOGIC; 
    trd_host_cmd_12_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_8_data_oe : out STD_LOGIC; 
    trd_drq_5_ack : in STD_LOGIC := 'X'; 
    trd_drq_1_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_we : out STD_LOGIC; 
    trd_host_cmd_7_cmd_data_cs : out STD_LOGIC; 
    trd_drq_0_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_status_cs : out STD_LOGIC; 
    drq3_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_cmd_adr_we : out STD_LOGIC; 
    trd_drq_6_ack : in STD_LOGIC := 'X'; 
    trd_drq_2_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_status_cs : out STD_LOGIC; 
    trd_host_cmd_3_cmd_data_we : out STD_LOGIC; 
    trd_drq_5_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_11_data_we : out STD_LOGIC; 
    trd_host_cmd_13_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_10_data_oe : out STD_LOGIC; 
    trd_drq_7_ack : in STD_LOGIC := 'X'; 
    trd_drq_3_req : in STD_LOGIC := 'X'; 
    dmar0 : out STD_LOGIC; 
    drq0_ack : in STD_LOGIC := 'X'; 
    dmar1 : out STD_LOGIC; 
    drq2_en : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    dmar2 : out STD_LOGIC; 
    trd_host_cmd_13_cmd_data_cs : out STD_LOGIC; 
    dmar3 : out STD_LOGIC; 
    trd_host_cmd_8_data_we : out STD_LOGIC; 
    trd_drq_4_req : in STD_LOGIC := 'X'; 
    trd_drq_8_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_6_data_cs : out STD_LOGIC; 
    trd_host_cmd_7_data_oe : out STD_LOGIC; 
    trd_host_cmd_4_cmd_data_cs : out STD_LOGIC; 
    trd_drq_9_ack : in STD_LOGIC := 'X'; 
    trd_drq_5_req : in STD_LOGIC := 'X'; 
    trd_drq_13_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_4_status_cs : out STD_LOGIC; 
    trd_host_cmd_10_data_we : out STD_LOGIC; 
    trd_host_cmd_9_cmd_adr_we : out STD_LOGIC; 
    trd_drq_6_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_2_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_12_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_10_cmd_data_cs : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    trd_drq_7_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_13_status_cs : out STD_LOGIC; 
    drq0_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_7_data_we : out STD_LOGIC; 
    trd_host_cmd_5_data_cs : out STD_LOGIC; 
    trd_host_cmd_6_data_oe : out STD_LOGIC; 
    trd_drq_2_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_7_cmd_data_we : out STD_LOGIC; 
    trd_drq_8_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_cmd_data_cs : out STD_LOGIC; 
    trd_drq_7_en : in STD_LOGIC := 'X'; 
    trd_drq_9_req : in STD_LOGIC := 'X'; 
    drq2_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_13_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_8_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_1_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_8_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_6_data_we : out STD_LOGIC; 
    trd_drq_10_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_4_data_cs : out STD_LOGIC; 
    trd_host_cmd_5_status_cs : out STD_LOGIC; 
    trd_host_cmd_5_data_oe : out STD_LOGIC; 
    trd_host_cmd_4_cmd_data_we : out STD_LOGIC; 
    trd_drq_15_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_11_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_15_data_cs : out STD_LOGIC; 
    trd_host_cmd_14_status_cs : out STD_LOGIC; 
    trd_host_cmd_14_cmd_data_cs : out STD_LOGIC; 
    int1 : in STD_LOGIC := 'X'; 
    drq3_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_10_cmd_data_we : out STD_LOGIC; 
    drq2_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_data_cs : out STD_LOGIC; 
    drq0_en : in STD_LOGIC := 'X'; 
    trd_drq_4_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_data_we : out STD_LOGIC; 
    trd_host_cmd_7_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_3_data_cs : out STD_LOGIC; 
    trd_host_cmd_0_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_4_data_oe : out STD_LOGIC; 
    test_mode : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_cmd_data_we : out STD_LOGIC; 
    trd_drq_9_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_status_cs : out STD_LOGIC; 
    trd_drq_10_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_14_data_cs : out STD_LOGIC; 
    trd_host_cmd_15_data_oe : out STD_LOGIC; 
    trd_host_cmd_11_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_10_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_6_status_cs : out STD_LOGIC; 
    trd_drq_11_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_8_cmd_data_we : out STD_LOGIC; 
    trd_drq_12_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_2_cmd_data_cs : out STD_LOGIC; 
    trd_drq_12_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_status_cs : out STD_LOGIC; 
    trd_host_cmd_4_data_we : out STD_LOGIC; 
    trd_host_cmd_2_data_cs : out STD_LOGIC; 
    trd_host_cmd_3_data_oe : out STD_LOGIC; 
    trd_drq_13_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_data_we : out STD_LOGIC; 
    trd_host_cmd_13_data_cs : out STD_LOGIC; 
    trd_host_cmd_14_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_14_data_oe : out STD_LOGIC; 
    trd_drq_10_req : in STD_LOGIC := 'X'; 
    irq1 : out STD_LOGIC; 
    trd_host_cmd_6_cmd_adr_we : out STD_LOGIC; 
    trd_drq_14_ack : in STD_LOGIC := 'X'; 
    trd_drq_1_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_1_status_cs : out STD_LOGIC; 
    trd_drq_11_req : in STD_LOGIC := 'X'; 
    trd_drq_15_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_data_we : out STD_LOGIC; 
    trd_drq_6_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_data_we : out STD_LOGIC; 
    trd_host_cmd_1_data_cs : out STD_LOGIC; 
    trd_host_cmd_2_data_oe : out STD_LOGIC; 
    trd_host_cmd_7_status_cs : out STD_LOGIC; 
    trd_drq_12_req : in STD_LOGIC := 'X'; 
    drq1_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_cmd_data_cs : out STD_LOGIC; 
    lc_rd : in STD_LOGIC := 'X'; 
    trd_host_cmd_10_status_cs : out STD_LOGIC; 
    trd_host_cmd_14_data_we : out STD_LOGIC; 
    trd_drq_13_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_data_cs : out STD_LOGIC; 
    trd_host_cmd_5_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_0_Q : out STD_LOGIC; 
    trd_host_adr : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    trd4_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trd_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    lc_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
    trd_cmd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
    lc_host_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    trd_reset_fifo : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    lc_adr : in STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end pb_adm_ctrl_m2;

architecture STRUCTURE of pb_adm_ctrl_m2 is
  component ctrl_mux8x48
    port (
      o : out STD_LOGIC_VECTOR ( 47 downto 0 ); 
      ma : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mb : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mc : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      md : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      me : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mf : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mg : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      mh : in STD_LOGIC_VECTOR ( 47 downto 0 ); 
      s : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component ctrl_mux16x16
    port (
      o : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mab : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mac : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mad : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mae : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      maf : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mag : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mah : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      ma : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mb : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mc : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      md : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      me : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mf : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mg : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mh : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      s : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      maa : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component ctrl_mux8x16r
    port (
      clk : in STD_LOGIC := 'X'; 
      q : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      ma : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mb : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mc : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      md : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      me : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mf : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mg : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mh : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      s : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_1
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_2
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_3
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_1
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_2
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_3
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_4
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_5
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_6
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_4
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_5
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_6
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_7
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_8
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_9
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_7
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_8
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_9
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_10
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_11
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_12
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_10
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_11
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_12
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_13
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_14
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_15
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_13
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_14
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_15
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_16
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_17
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_18
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_16
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_17
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_18
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_19
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_20
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_21
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_19
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_20
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_21
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_22
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_23
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_cs_24
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      cmd_data_en : in STD_LOGIC := 'X'; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_22
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_23
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_data_we_24
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      wr : in STD_LOGIC := 'X'; 
      data_we : out STD_LOGIC; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_ram_cs_1
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      rd : in STD_LOGIC := 'X'; 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 8 ); 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_ram_cs_2
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      rd : in STD_LOGIC := 'X'; 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 8 ); 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  component ctrl_adsp_v2_decode_cmd_adr_cs
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : out STD_LOGIC; 
      rd : in STD_LOGIC := 'X'; 
      adr : in STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  signal Mmux_addra_0_mux0001_3_7897 : STD_LOGIC; 
  signal Mmux_addra_0_mux0001_4_7898 : STD_LOGIC; 
  signal Mmux_addra_1_mux0001_3_7899 : STD_LOGIC; 
  signal Mmux_addra_1_mux0001_4_7900 : STD_LOGIC; 
  signal Mmux_addra_2_mux0001_3_7901 : STD_LOGIC; 
  signal Mmux_addra_2_mux0001_4_7902 : STD_LOGIC; 
  signal Mmux_addra_3_mux0001_3_7903 : STD_LOGIC; 
  signal Mmux_addra_3_mux0001_4_7904 : STD_LOGIC; 
  signal Mmux_addra_4_mux0001_3_7905 : STD_LOGIC; 
  signal Mmux_addra_4_mux0001_4_7906 : STD_LOGIC; 
  signal Mmux_addra_8_mux0001_3_7907 : STD_LOGIC; 
  signal Mmux_addra_8_mux0001_4_7908 : STD_LOGIC; 
  signal Mmux_sel_cmd_data_3_7909 : STD_LOGIC; 
  signal Mmux_sel_cmd_data_4_7910 : STD_LOGIC; 
  signal Mrom_mux_sel_3_mux0001 : STD_LOGIC; 
  signal Mshreg_mac_0_7912 : STD_LOGIC; 
  signal Mshreg_mac_1_7913 : STD_LOGIC; 
  signal Mshreg_mac_2_7914 : STD_LOGIC; 
  signal Mshreg_mac_3_7915 : STD_LOGIC; 
  signal Mshreg_mac_4_7916 : STD_LOGIC; 
  signal Mshreg_mac_8_7917 : STD_LOGIC; 
  signal Mshreg_mac_9_7918 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal addra_0_mux0001 : STD_LOGIC; 
  signal addra_1_mux0001 : STD_LOGIC; 
  signal addra_2_mux0001 : STD_LOGIC; 
  signal addra_3_mux0001 : STD_LOGIC; 
  signal addra_4_mux0001 : STD_LOGIC; 
  signal addra_8_mux0001 : STD_LOGIC; 
  signal bl_data_cs_0_inv : STD_LOGIC; 
  signal bl_data_cs_6_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd0_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd1_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd2_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd3_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd4_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd5_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd6_adr_9_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_3_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_8_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_cmd7_adr_9_Q : STD_LOGIC; 
  signal dpram_en : STD_LOGIC; 
  signal dpram_en0_8098 : STD_LOGIC; 
  signal dpram_en0_or0000 : STD_LOGIC; 
  signal flag_data_we_0_Q : STD_LOGIC; 
  signal flag_data_we_4_Q : STD_LOGIC; 
  signal flag_rd_block_0_Q : STD_LOGIC; 
  signal flag_rd_block_0_not0001 : STD_LOGIC; 
  signal flag_rd_block_6_Q : STD_LOGIC; 
  signal flag_rd_block_6_not0001 : STD_LOGIC; 
  signal flag_rd_repack_0_Q : STD_LOGIC; 
  signal flag_rd_repack_0_not0001 : STD_LOGIC; 
  signal flag_rd_repack_0_or0000 : STD_LOGIC; 
  signal flag_rd_repack_6_Q : STD_LOGIC; 
  signal flag_rd_repack_6_not0001 : STD_LOGIC; 
  signal flag_rd_repack_6_or0000 : STD_LOGIC; 
  signal mac_0_Q : STD_LOGIC; 
  signal mac_1_Q : STD_LOGIC; 
  signal mac_2_Q : STD_LOGIC; 
  signal mac_3_Q : STD_LOGIC; 
  signal mac_4_Q : STD_LOGIC; 
  signal mac_8_Q : STD_LOGIC; 
  signal mac_9_Q : STD_LOGIC; 
  signal main_mode2_4_8422 : STD_LOGIC; 
  signal main_mode2_4_and0000_8423 : STD_LOGIC; 
  signal main_mode2_4_inv : STD_LOGIC; 
  signal mux_sel_0_mux0001 : STD_LOGIC; 
  signal mux_sel_1_mux0001 : STD_LOGIC; 
  signal na_0_Q : STD_LOGIC; 
  signal na_1_Q : STD_LOGIC; 
  signal na_15_Q : STD_LOGIC; 
  signal na_2_Q : STD_LOGIC; 
  signal na_3_Q : STD_LOGIC; 
  signal na_5_Q : STD_LOGIC; 
  signal na_6_Q : STD_LOGIC; 
  signal rd1 : STD_LOGIC; 
  signal rd2_8534 : STD_LOGIC; 
  signal rd2z_8535 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal sel_cmd_data : STD_LOGIC; 
  signal trd4i_host_data_10_and0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_trd_host_cmd_0_cmd_data_we : STD_LOGIC; 
  signal NlwRenamedSig_OI_trd_host_cmd_0_data_oe : STD_LOGIC; 
  signal NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_trd_host_cmd_6_data_oe : STD_LOGIC; 
  signal trd_repack_data_0_0_Q : STD_LOGIC; 
  signal trd_repack_data_0_10_Q : STD_LOGIC; 
  signal trd_repack_data_0_11_Q : STD_LOGIC; 
  signal trd_repack_data_0_12_Q : STD_LOGIC; 
  signal trd_repack_data_0_13_Q : STD_LOGIC; 
  signal trd_repack_data_0_14_Q : STD_LOGIC; 
  signal trd_repack_data_0_15_Q : STD_LOGIC; 
  signal trd_repack_data_0_16_Q : STD_LOGIC; 
  signal trd_repack_data_0_17_Q : STD_LOGIC; 
  signal trd_repack_data_0_18_Q : STD_LOGIC; 
  signal trd_repack_data_0_19_Q : STD_LOGIC; 
  signal trd_repack_data_0_1_Q : STD_LOGIC; 
  signal trd_repack_data_0_20_Q : STD_LOGIC; 
  signal trd_repack_data_0_21_Q : STD_LOGIC; 
  signal trd_repack_data_0_22_Q : STD_LOGIC; 
  signal trd_repack_data_0_23_Q : STD_LOGIC; 
  signal trd_repack_data_0_24_Q : STD_LOGIC; 
  signal trd_repack_data_0_25_Q : STD_LOGIC; 
  signal trd_repack_data_0_26_Q : STD_LOGIC; 
  signal trd_repack_data_0_27_Q : STD_LOGIC; 
  signal trd_repack_data_0_28_Q : STD_LOGIC; 
  signal trd_repack_data_0_29_Q : STD_LOGIC; 
  signal trd_repack_data_0_2_Q : STD_LOGIC; 
  signal trd_repack_data_0_30_Q : STD_LOGIC; 
  signal trd_repack_data_0_31_Q : STD_LOGIC; 
  signal trd_repack_data_0_3_Q : STD_LOGIC; 
  signal trd_repack_data_0_4_Q : STD_LOGIC; 
  signal trd_repack_data_0_5_Q : STD_LOGIC; 
  signal trd_repack_data_0_6_Q : STD_LOGIC; 
  signal trd_repack_data_0_7_Q : STD_LOGIC; 
  signal trd_repack_data_0_8_Q : STD_LOGIC; 
  signal trd_repack_data_0_9_Q : STD_LOGIC; 
  signal trd_repack_data_6_0_Q : STD_LOGIC; 
  signal trd_repack_data_6_10_Q : STD_LOGIC; 
  signal trd_repack_data_6_11_Q : STD_LOGIC; 
  signal trd_repack_data_6_12_Q : STD_LOGIC; 
  signal trd_repack_data_6_13_Q : STD_LOGIC; 
  signal trd_repack_data_6_14_Q : STD_LOGIC; 
  signal trd_repack_data_6_15_Q : STD_LOGIC; 
  signal trd_repack_data_6_16_Q : STD_LOGIC; 
  signal trd_repack_data_6_17_Q : STD_LOGIC; 
  signal trd_repack_data_6_18_Q : STD_LOGIC; 
  signal trd_repack_data_6_19_Q : STD_LOGIC; 
  signal trd_repack_data_6_1_Q : STD_LOGIC; 
  signal trd_repack_data_6_20_Q : STD_LOGIC; 
  signal trd_repack_data_6_21_Q : STD_LOGIC; 
  signal trd_repack_data_6_22_Q : STD_LOGIC; 
  signal trd_repack_data_6_23_Q : STD_LOGIC; 
  signal trd_repack_data_6_24_Q : STD_LOGIC; 
  signal trd_repack_data_6_25_Q : STD_LOGIC; 
  signal trd_repack_data_6_26_Q : STD_LOGIC; 
  signal trd_repack_data_6_27_Q : STD_LOGIC; 
  signal trd_repack_data_6_28_Q : STD_LOGIC; 
  signal trd_repack_data_6_29_Q : STD_LOGIC; 
  signal trd_repack_data_6_2_Q : STD_LOGIC; 
  signal trd_repack_data_6_30_Q : STD_LOGIC; 
  signal trd_repack_data_6_31_Q : STD_LOGIC; 
  signal trd_repack_data_6_3_Q : STD_LOGIC; 
  signal trd_repack_data_6_4_Q : STD_LOGIC; 
  signal trd_repack_data_6_5_Q : STD_LOGIC; 
  signal trd_repack_data_6_6_Q : STD_LOGIC; 
  signal trd_repack_data_6_7_Q : STD_LOGIC; 
  signal trd_repack_data_6_8_Q : STD_LOGIC; 
  signal trd_repack_data_6_9_Q : STD_LOGIC; 
  signal trd_reset_fifo_0_inv : STD_LOGIC; 
  signal trd_reset_fifo_6_inv : STD_LOGIC; 
  signal wrl1 : STD_LOGIC; 
  signal NLW_xcmd_adr_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_xcmd_rom_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_xcmd_ram_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_CASCADEINA_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_CASCADEINB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_CLKB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_REGCEB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ENB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_SSRB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_CASCADEOUTA_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_CASCADEOUTB_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRA_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_ADDRB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DIPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_WEB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_WEB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_WEB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_WEB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOA_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPA_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPA_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPA_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPA_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPB_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPB_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPB_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_rom_DOPB_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_0_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_1_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_3_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_9_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_4_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_mac_8_Q15_UNCONNECTED : STD_LOGIC; 
  signal addra : STD_LOGIC_VECTOR ( 9 downto 0 ); 
  signal adr1 : STD_LOGIC_VECTOR ( 5 downto 1 ); 
  signal adr2 : STD_LOGIC_VECTOR ( 5 downto 1 ); 
  signal bl_cmd_adr_we : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal bl_data_we : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal cmd1_adr : STD_LOGIC_VECTOR ( 5 downto 5 ); 
  signal cmd_data2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_data2 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal lc_data_i : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal ma : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal maa : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal mab : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal mg : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal mux_sel : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal nb : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal ng : STD_LOGIC_VECTOR ( 8 downto 1 ); 
  signal nh : STD_LOGIC_VECTOR ( 8 downto 2 ); 
  signal rom_data2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal trd4i_host_data : STD_LOGIC_VECTOR ( 31 downto 0 ); 
begin
  trd_host_cmd_11_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_0_data_oe <= NlwRenamedSig_OI_trd_host_cmd_0_data_oe;
  trd_host_cmd_15_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_0_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_0_cmd_data_we;
  trd_host_cmd_10_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_6_data_oe <= NlwRenamedSig_OI_trd_host_cmd_6_data_oe;
  trd_host_cmd_13_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_data_oe <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_status_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_data_we <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_data_cs <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_5_adr_9_Q <= NlwRenamedSig_OI_cmd5_adr_9_Q;
  trd_host_cmd_5_adr_8_Q <= NlwRenamedSig_OI_cmd5_adr_8_Q;
  trd_host_cmd_5_adr_4_Q <= NlwRenamedSig_OI_cmd5_adr_4_Q;
  trd_host_cmd_5_adr_3_Q <= NlwRenamedSig_OI_cmd5_adr_3_Q;
  trd_host_cmd_5_adr_2_Q <= NlwRenamedSig_OI_cmd5_adr_2_Q;
  trd_host_cmd_5_adr_1_Q <= NlwRenamedSig_OI_cmd5_adr_1_Q;
  trd_host_cmd_5_adr_0_Q <= NlwRenamedSig_OI_cmd5_adr_0_Q;
  trd_host_cmd_6_adr_9_Q <= NlwRenamedSig_OI_cmd6_adr_9_Q;
  trd_host_cmd_6_adr_8_Q <= NlwRenamedSig_OI_cmd6_adr_8_Q;
  trd_host_cmd_6_adr_4_Q <= NlwRenamedSig_OI_cmd6_adr_4_Q;
  trd_host_cmd_6_adr_3_Q <= NlwRenamedSig_OI_cmd6_adr_3_Q;
  trd_host_cmd_6_adr_2_Q <= NlwRenamedSig_OI_cmd6_adr_2_Q;
  trd_host_cmd_6_adr_1_Q <= NlwRenamedSig_OI_cmd6_adr_1_Q;
  trd_host_cmd_6_adr_0_Q <= NlwRenamedSig_OI_cmd6_adr_0_Q;
  trd_host_cmd_7_adr_9_Q <= NlwRenamedSig_OI_cmd7_adr_9_Q;
  trd_host_cmd_7_adr_8_Q <= NlwRenamedSig_OI_cmd7_adr_8_Q;
  trd_host_cmd_7_adr_4_Q <= NlwRenamedSig_OI_cmd7_adr_4_Q;
  trd_host_cmd_7_adr_3_Q <= NlwRenamedSig_OI_cmd7_adr_3_Q;
  trd_host_cmd_7_adr_2_Q <= NlwRenamedSig_OI_cmd7_adr_2_Q;
  trd_host_cmd_7_adr_1_Q <= NlwRenamedSig_OI_cmd7_adr_1_Q;
  trd_host_cmd_7_adr_0_Q <= NlwRenamedSig_OI_cmd7_adr_0_Q;
  trd_host_cmd_8_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_8_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_9_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_10_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_11_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_12_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_13_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_14_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_data(63) <= NlwRenamedSig_OI_data2(63);
  trd_host_data(62) <= NlwRenamedSig_OI_data2(62);
  trd_host_data(61) <= NlwRenamedSig_OI_data2(61);
  trd_host_data(60) <= NlwRenamedSig_OI_data2(60);
  trd_host_data(59) <= NlwRenamedSig_OI_data2(59);
  trd_host_data(58) <= NlwRenamedSig_OI_data2(58);
  trd_host_data(57) <= NlwRenamedSig_OI_data2(57);
  trd_host_data(56) <= NlwRenamedSig_OI_data2(56);
  trd_host_data(55) <= NlwRenamedSig_OI_data2(55);
  trd_host_data(54) <= NlwRenamedSig_OI_data2(54);
  trd_host_data(53) <= NlwRenamedSig_OI_data2(53);
  trd_host_data(52) <= NlwRenamedSig_OI_data2(52);
  trd_host_data(51) <= NlwRenamedSig_OI_data2(51);
  trd_host_data(50) <= NlwRenamedSig_OI_data2(50);
  trd_host_data(49) <= NlwRenamedSig_OI_data2(49);
  trd_host_data(48) <= NlwRenamedSig_OI_data2(48);
  trd_host_data(47) <= NlwRenamedSig_OI_data2(47);
  trd_host_data(46) <= NlwRenamedSig_OI_data2(46);
  trd_host_data(45) <= NlwRenamedSig_OI_data2(45);
  trd_host_data(44) <= NlwRenamedSig_OI_data2(44);
  trd_host_data(43) <= NlwRenamedSig_OI_data2(43);
  trd_host_data(42) <= NlwRenamedSig_OI_data2(42);
  trd_host_data(41) <= NlwRenamedSig_OI_data2(41);
  trd_host_data(40) <= NlwRenamedSig_OI_data2(40);
  trd_host_data(39) <= NlwRenamedSig_OI_data2(39);
  trd_host_data(38) <= NlwRenamedSig_OI_data2(38);
  trd_host_data(37) <= NlwRenamedSig_OI_data2(37);
  trd_host_data(36) <= NlwRenamedSig_OI_data2(36);
  trd_host_data(35) <= NlwRenamedSig_OI_data2(35);
  trd_host_data(34) <= NlwRenamedSig_OI_data2(34);
  trd_host_data(33) <= NlwRenamedSig_OI_data2(33);
  trd_host_data(32) <= NlwRenamedSig_OI_data2(32);
  trd_host_data(31) <= NlwRenamedSig_OI_data2(31);
  trd_host_data(30) <= NlwRenamedSig_OI_data2(30);
  trd_host_data(29) <= NlwRenamedSig_OI_data2(29);
  trd_host_data(28) <= NlwRenamedSig_OI_data2(28);
  trd_host_data(27) <= NlwRenamedSig_OI_data2(27);
  trd_host_data(26) <= NlwRenamedSig_OI_data2(26);
  trd_host_data(25) <= NlwRenamedSig_OI_data2(25);
  trd_host_data(24) <= NlwRenamedSig_OI_data2(24);
  trd_host_data(23) <= NlwRenamedSig_OI_data2(23);
  trd_host_data(22) <= NlwRenamedSig_OI_data2(22);
  trd_host_data(21) <= NlwRenamedSig_OI_data2(21);
  trd_host_data(20) <= NlwRenamedSig_OI_data2(20);
  trd_host_data(19) <= NlwRenamedSig_OI_data2(19);
  trd_host_data(18) <= NlwRenamedSig_OI_data2(18);
  trd_host_data(17) <= NlwRenamedSig_OI_data2(17);
  trd_host_data(16) <= NlwRenamedSig_OI_data2(16);
  trd_host_data(15) <= NlwRenamedSig_OI_data2(15);
  trd_host_data(14) <= NlwRenamedSig_OI_data2(14);
  trd_host_data(13) <= NlwRenamedSig_OI_data2(13);
  trd_host_data(12) <= NlwRenamedSig_OI_data2(12);
  trd_host_data(11) <= NlwRenamedSig_OI_data2(11);
  trd_host_data(10) <= NlwRenamedSig_OI_data2(10);
  trd_host_data(9) <= NlwRenamedSig_OI_data2(9);
  trd_host_data(8) <= NlwRenamedSig_OI_data2(8);
  trd_host_data(7) <= NlwRenamedSig_OI_data2(7);
  trd_host_data(6) <= NlwRenamedSig_OI_data2(6);
  trd_host_data(5) <= NlwRenamedSig_OI_data2(5);
  trd_host_data(4) <= NlwRenamedSig_OI_data2(4);
  trd_host_data(3) <= NlwRenamedSig_OI_data2(3);
  trd_host_data(2) <= NlwRenamedSig_OI_data2(2);
  trd_host_data(1) <= NlwRenamedSig_OI_data2(1);
  trd_host_data(0) <= NlwRenamedSig_OI_data2(0);
  trd_host_cmd_15_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_15_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q;
  trd_host_cmd_0_adr_9_Q <= NlwRenamedSig_OI_cmd0_adr_9_Q;
  trd_host_cmd_0_adr_8_Q <= NlwRenamedSig_OI_cmd0_adr_8_Q;
  trd_host_cmd_0_adr_4_Q <= NlwRenamedSig_OI_cmd0_adr_4_Q;
  trd_host_cmd_0_adr_3_Q <= NlwRenamedSig_OI_cmd0_adr_3_Q;
  trd_host_cmd_0_adr_2_Q <= NlwRenamedSig_OI_cmd0_adr_2_Q;
  trd_host_cmd_0_adr_1_Q <= NlwRenamedSig_OI_cmd0_adr_1_Q;
  trd_host_cmd_0_adr_0_Q <= NlwRenamedSig_OI_cmd0_adr_0_Q;
  trd_host_cmd_1_adr_9_Q <= NlwRenamedSig_OI_cmd1_adr_9_Q;
  trd_host_cmd_1_adr_8_Q <= NlwRenamedSig_OI_cmd1_adr_8_Q;
  trd_host_cmd_1_adr_5_Q <= cmd1_adr(5);
  trd_host_cmd_1_adr_4_Q <= NlwRenamedSig_OI_cmd1_adr_4_Q;
  trd_host_cmd_1_adr_3_Q <= NlwRenamedSig_OI_cmd1_adr_3_Q;
  trd_host_cmd_1_adr_2_Q <= NlwRenamedSig_OI_cmd1_adr_2_Q;
  trd_host_cmd_1_adr_1_Q <= NlwRenamedSig_OI_cmd1_adr_1_Q;
  trd_host_cmd_1_adr_0_Q <= NlwRenamedSig_OI_cmd1_adr_0_Q;
  trd_host_cmd_2_adr_9_Q <= NlwRenamedSig_OI_cmd2_adr_9_Q;
  trd_host_cmd_2_adr_8_Q <= NlwRenamedSig_OI_cmd2_adr_8_Q;
  trd_host_cmd_2_adr_4_Q <= NlwRenamedSig_OI_cmd2_adr_4_Q;
  trd_host_cmd_2_adr_3_Q <= NlwRenamedSig_OI_cmd2_adr_3_Q;
  trd_host_cmd_2_adr_2_Q <= NlwRenamedSig_OI_cmd2_adr_2_Q;
  trd_host_cmd_2_adr_1_Q <= NlwRenamedSig_OI_cmd2_adr_1_Q;
  trd_host_cmd_2_adr_0_Q <= NlwRenamedSig_OI_cmd2_adr_0_Q;
  trd_host_cmd_3_adr_9_Q <= NlwRenamedSig_OI_cmd3_adr_9_Q;
  trd_host_cmd_3_adr_8_Q <= NlwRenamedSig_OI_cmd3_adr_8_Q;
  trd_host_cmd_3_adr_4_Q <= NlwRenamedSig_OI_cmd3_adr_4_Q;
  trd_host_cmd_3_adr_3_Q <= NlwRenamedSig_OI_cmd3_adr_3_Q;
  trd_host_cmd_3_adr_2_Q <= NlwRenamedSig_OI_cmd3_adr_2_Q;
  trd_host_cmd_3_adr_1_Q <= NlwRenamedSig_OI_cmd3_adr_1_Q;
  trd_host_cmd_3_adr_0_Q <= NlwRenamedSig_OI_cmd3_adr_0_Q;
  trd_host_cmd_4_adr_9_Q <= NlwRenamedSig_OI_cmd4_adr_9_Q;
  trd_host_cmd_4_adr_8_Q <= NlwRenamedSig_OI_cmd4_adr_8_Q;
  trd_host_cmd_4_adr_4_Q <= NlwRenamedSig_OI_cmd4_adr_4_Q;
  trd_host_cmd_4_adr_3_Q <= NlwRenamedSig_OI_cmd4_adr_3_Q;
  trd_host_cmd_4_adr_2_Q <= NlwRenamedSig_OI_cmd4_adr_2_Q;
  trd_host_cmd_4_adr_1_Q <= NlwRenamedSig_OI_cmd4_adr_1_Q;
  trd_host_cmd_4_adr_0_Q <= NlwRenamedSig_OI_cmd4_adr_0_Q;
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q
    );
  XST_VCC : VCC
    port map (
      P => flag_data_we_0_Q
    );
  mux_sel_0 : FD
    port map (
      C => clk,
      D => mux_sel_0_mux0001,
      Q => mux_sel(0)
    );
  mux_sel_1 : FD
    port map (
      C => clk,
      D => mux_sel_1_mux0001,
      Q => mux_sel(1)
    );
  rd2 : FDP
    port map (
      C => clk,
      D => rd1,
      PRE => reset_inv,
      Q => rd2_8534
    );
  ma_0 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_0_Q,
      Q => ma(0)
    );
  ma_1 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_1_Q,
      Q => ma(1)
    );
  ma_2 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_2_Q,
      Q => ma(2)
    );
  ma_3 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_3_Q,
      Q => ma(3)
    );
  ma_4 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_4_Q,
      Q => ma(4)
    );
  ma_5 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_5_Q,
      Q => ma(5)
    );
  ma_6 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_6_Q,
      Q => ma(6)
    );
  ma_7 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_7_Q,
      Q => ma(7)
    );
  ma_8 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_8_Q,
      Q => ma(8)
    );
  ma_9 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_9_Q,
      Q => ma(9)
    );
  ma_10 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_10_Q,
      Q => ma(10)
    );
  ma_11 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_11_Q,
      Q => ma(11)
    );
  ma_12 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_12_Q,
      Q => ma(12)
    );
  ma_13 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_13_Q,
      Q => ma(13)
    );
  ma_14 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_14_Q,
      Q => ma(14)
    );
  ma_15 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_15_Q,
      Q => ma(15)
    );
  ma_16 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_16_Q,
      Q => ma(16)
    );
  ma_17 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_17_Q,
      Q => ma(17)
    );
  ma_18 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_18_Q,
      Q => ma(18)
    );
  ma_19 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_19_Q,
      Q => ma(19)
    );
  ma_20 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_20_Q,
      Q => ma(20)
    );
  ma_21 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_21_Q,
      Q => ma(21)
    );
  ma_22 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_22_Q,
      Q => ma(22)
    );
  ma_23 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_23_Q,
      Q => ma(23)
    );
  ma_24 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_24_Q,
      Q => ma(24)
    );
  ma_25 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_25_Q,
      Q => ma(25)
    );
  ma_26 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_26_Q,
      Q => ma(26)
    );
  ma_27 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_27_Q,
      Q => ma(27)
    );
  ma_28 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_28_Q,
      Q => ma(28)
    );
  ma_29 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_29_Q,
      Q => ma(29)
    );
  ma_30 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_30_Q,
      Q => ma(30)
    );
  ma_31 : FD
    port map (
      C => clk,
      D => trd_repack_data_0_31_Q,
      Q => ma(31)
    );
  ma_32 : FD
    port map (
      C => clk,
      D => trd_data(0, 32),
      Q => ma(32)
    );
  ma_33 : FD
    port map (
      C => clk,
      D => trd_data(0, 33),
      Q => ma(33)
    );
  ma_34 : FD
    port map (
      C => clk,
      D => trd_data(0, 34),
      Q => ma(34)
    );
  ma_35 : FD
    port map (
      C => clk,
      D => trd_data(0, 35),
      Q => ma(35)
    );
  ma_36 : FD
    port map (
      C => clk,
      D => trd_data(0, 36),
      Q => ma(36)
    );
  ma_37 : FD
    port map (
      C => clk,
      D => trd_data(0, 37),
      Q => ma(37)
    );
  ma_38 : FD
    port map (
      C => clk,
      D => trd_data(0, 38),
      Q => ma(38)
    );
  ma_39 : FD
    port map (
      C => clk,
      D => trd_data(0, 39),
      Q => ma(39)
    );
  ma_40 : FD
    port map (
      C => clk,
      D => trd_data(0, 40),
      Q => ma(40)
    );
  ma_41 : FD
    port map (
      C => clk,
      D => trd_data(0, 41),
      Q => ma(41)
    );
  ma_42 : FD
    port map (
      C => clk,
      D => trd_data(0, 42),
      Q => ma(42)
    );
  ma_43 : FD
    port map (
      C => clk,
      D => trd_data(0, 43),
      Q => ma(43)
    );
  ma_44 : FD
    port map (
      C => clk,
      D => trd_data(0, 44),
      Q => ma(44)
    );
  ma_45 : FD
    port map (
      C => clk,
      D => trd_data(0, 45),
      Q => ma(45)
    );
  ma_46 : FD
    port map (
      C => clk,
      D => trd_data(0, 46),
      Q => ma(46)
    );
  ma_47 : FD
    port map (
      C => clk,
      D => trd_data(0, 47),
      Q => ma(47)
    );
  ma_48 : FD
    port map (
      C => clk,
      D => trd_data(0, 48),
      Q => ma(48)
    );
  ma_49 : FD
    port map (
      C => clk,
      D => trd_data(0, 49),
      Q => ma(49)
    );
  ma_50 : FD
    port map (
      C => clk,
      D => trd_data(0, 50),
      Q => ma(50)
    );
  ma_51 : FD
    port map (
      C => clk,
      D => trd_data(0, 51),
      Q => ma(51)
    );
  ma_52 : FD
    port map (
      C => clk,
      D => trd_data(0, 52),
      Q => ma(52)
    );
  ma_53 : FD
    port map (
      C => clk,
      D => trd_data(0, 53),
      Q => ma(53)
    );
  ma_54 : FD
    port map (
      C => clk,
      D => trd_data(0, 54),
      Q => ma(54)
    );
  ma_55 : FD
    port map (
      C => clk,
      D => trd_data(0, 55),
      Q => ma(55)
    );
  ma_56 : FD
    port map (
      C => clk,
      D => trd_data(0, 56),
      Q => ma(56)
    );
  ma_57 : FD
    port map (
      C => clk,
      D => trd_data(0, 57),
      Q => ma(57)
    );
  ma_58 : FD
    port map (
      C => clk,
      D => trd_data(0, 58),
      Q => ma(58)
    );
  ma_59 : FD
    port map (
      C => clk,
      D => trd_data(0, 59),
      Q => ma(59)
    );
  ma_60 : FD
    port map (
      C => clk,
      D => trd_data(0, 60),
      Q => ma(60)
    );
  ma_61 : FD
    port map (
      C => clk,
      D => trd_data(0, 61),
      Q => ma(61)
    );
  ma_62 : FD
    port map (
      C => clk,
      D => trd_data(0, 62),
      Q => ma(62)
    );
  ma_63 : FD
    port map (
      C => clk,
      D => trd_data(0, 63),
      Q => ma(63)
    );
  mg_0 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_0_Q,
      Q => mg(0)
    );
  mg_1 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_1_Q,
      Q => mg(1)
    );
  mg_2 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_2_Q,
      Q => mg(2)
    );
  mg_3 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_3_Q,
      Q => mg(3)
    );
  mg_4 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_4_Q,
      Q => mg(4)
    );
  mg_5 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_5_Q,
      Q => mg(5)
    );
  mg_6 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_6_Q,
      Q => mg(6)
    );
  mg_7 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_7_Q,
      Q => mg(7)
    );
  mg_8 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_8_Q,
      Q => mg(8)
    );
  mg_9 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_9_Q,
      Q => mg(9)
    );
  mg_10 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_10_Q,
      Q => mg(10)
    );
  mg_11 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_11_Q,
      Q => mg(11)
    );
  mg_12 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_12_Q,
      Q => mg(12)
    );
  mg_13 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_13_Q,
      Q => mg(13)
    );
  mg_14 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_14_Q,
      Q => mg(14)
    );
  mg_15 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_15_Q,
      Q => mg(15)
    );
  mg_16 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_16_Q,
      Q => mg(16)
    );
  mg_17 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_17_Q,
      Q => mg(17)
    );
  mg_18 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_18_Q,
      Q => mg(18)
    );
  mg_19 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_19_Q,
      Q => mg(19)
    );
  mg_20 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_20_Q,
      Q => mg(20)
    );
  mg_21 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_21_Q,
      Q => mg(21)
    );
  mg_22 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_22_Q,
      Q => mg(22)
    );
  mg_23 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_23_Q,
      Q => mg(23)
    );
  mg_24 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_24_Q,
      Q => mg(24)
    );
  mg_25 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_25_Q,
      Q => mg(25)
    );
  mg_26 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_26_Q,
      Q => mg(26)
    );
  mg_27 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_27_Q,
      Q => mg(27)
    );
  mg_28 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_28_Q,
      Q => mg(28)
    );
  mg_29 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_29_Q,
      Q => mg(29)
    );
  mg_30 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_30_Q,
      Q => mg(30)
    );
  mg_31 : FD
    port map (
      C => clk,
      D => trd_repack_data_6_31_Q,
      Q => mg(31)
    );
  mg_32 : FD
    port map (
      C => clk,
      D => trd_data(6, 32),
      Q => mg(32)
    );
  mg_33 : FD
    port map (
      C => clk,
      D => trd_data(6, 33),
      Q => mg(33)
    );
  mg_34 : FD
    port map (
      C => clk,
      D => trd_data(6, 34),
      Q => mg(34)
    );
  mg_35 : FD
    port map (
      C => clk,
      D => trd_data(6, 35),
      Q => mg(35)
    );
  mg_36 : FD
    port map (
      C => clk,
      D => trd_data(6, 36),
      Q => mg(36)
    );
  mg_37 : FD
    port map (
      C => clk,
      D => trd_data(6, 37),
      Q => mg(37)
    );
  mg_38 : FD
    port map (
      C => clk,
      D => trd_data(6, 38),
      Q => mg(38)
    );
  mg_39 : FD
    port map (
      C => clk,
      D => trd_data(6, 39),
      Q => mg(39)
    );
  mg_40 : FD
    port map (
      C => clk,
      D => trd_data(6, 40),
      Q => mg(40)
    );
  mg_41 : FD
    port map (
      C => clk,
      D => trd_data(6, 41),
      Q => mg(41)
    );
  mg_42 : FD
    port map (
      C => clk,
      D => trd_data(6, 42),
      Q => mg(42)
    );
  mg_43 : FD
    port map (
      C => clk,
      D => trd_data(6, 43),
      Q => mg(43)
    );
  mg_44 : FD
    port map (
      C => clk,
      D => trd_data(6, 44),
      Q => mg(44)
    );
  mg_45 : FD
    port map (
      C => clk,
      D => trd_data(6, 45),
      Q => mg(45)
    );
  mg_46 : FD
    port map (
      C => clk,
      D => trd_data(6, 46),
      Q => mg(46)
    );
  mg_47 : FD
    port map (
      C => clk,
      D => trd_data(6, 47),
      Q => mg(47)
    );
  mg_48 : FD
    port map (
      C => clk,
      D => trd_data(6, 48),
      Q => mg(48)
    );
  mg_49 : FD
    port map (
      C => clk,
      D => trd_data(6, 49),
      Q => mg(49)
    );
  mg_50 : FD
    port map (
      C => clk,
      D => trd_data(6, 50),
      Q => mg(50)
    );
  mg_51 : FD
    port map (
      C => clk,
      D => trd_data(6, 51),
      Q => mg(51)
    );
  mg_52 : FD
    port map (
      C => clk,
      D => trd_data(6, 52),
      Q => mg(52)
    );
  mg_53 : FD
    port map (
      C => clk,
      D => trd_data(6, 53),
      Q => mg(53)
    );
  mg_54 : FD
    port map (
      C => clk,
      D => trd_data(6, 54),
      Q => mg(54)
    );
  mg_55 : FD
    port map (
      C => clk,
      D => trd_data(6, 55),
      Q => mg(55)
    );
  mg_56 : FD
    port map (
      C => clk,
      D => trd_data(6, 56),
      Q => mg(56)
    );
  mg_57 : FD
    port map (
      C => clk,
      D => trd_data(6, 57),
      Q => mg(57)
    );
  mg_58 : FD
    port map (
      C => clk,
      D => trd_data(6, 58),
      Q => mg(58)
    );
  mg_59 : FD
    port map (
      C => clk,
      D => trd_data(6, 59),
      Q => mg(59)
    );
  mg_60 : FD
    port map (
      C => clk,
      D => trd_data(6, 60),
      Q => mg(60)
    );
  mg_61 : FD
    port map (
      C => clk,
      D => trd_data(6, 61),
      Q => mg(61)
    );
  mg_62 : FD
    port map (
      C => clk,
      D => trd_data(6, 62),
      Q => mg(62)
    );
  mg_63 : FD
    port map (
      C => clk,
      D => trd_data(6, 63),
      Q => mg(63)
    );
  na_0 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 0),
      Q => na_0_Q
    );
  na_1 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 1),
      Q => na_1_Q
    );
  na_2 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 2),
      Q => na_2_Q
    );
  na_3 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 3),
      Q => na_3_Q
    );
  na_5 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 5),
      Q => na_5_Q
    );
  na_6 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 6),
      Q => na_6_Q
    );
  na_15 : FD
    port map (
      C => clk,
      D => trd_cmd_data(0, 15),
      Q => na_15_Q
    );
  nb_0 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 0),
      Q => nb(0)
    );
  nb_1 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 1),
      Q => nb(1)
    );
  nb_2 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 2),
      Q => nb(2)
    );
  nb_3 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 3),
      Q => nb(3)
    );
  nb_4 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 4),
      Q => nb(4)
    );
  nb_5 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 5),
      Q => nb(5)
    );
  nb_6 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 6),
      Q => nb(6)
    );
  nb_7 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 7),
      Q => nb(7)
    );
  nb_8 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 8),
      Q => nb(8)
    );
  nb_9 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 9),
      Q => nb(9)
    );
  nb_10 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 10),
      Q => nb(10)
    );
  nb_11 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 11),
      Q => nb(11)
    );
  nb_12 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 12),
      Q => nb(12)
    );
  nb_13 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 13),
      Q => nb(13)
    );
  nb_14 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 14),
      Q => nb(14)
    );
  nb_15 : FD
    port map (
      C => clk,
      D => trd_cmd_data(1, 15),
      Q => nb(15)
    );
  ng_1 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 1),
      Q => ng(1)
    );
  ng_2 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 2),
      Q => ng(2)
    );
  ng_3 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 3),
      Q => ng(3)
    );
  ng_4 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 4),
      Q => ng(4)
    );
  ng_5 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 5),
      Q => ng(5)
    );
  ng_6 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 6),
      Q => ng(6)
    );
  ng_7 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 7),
      Q => ng(7)
    );
  ng_8 : FD
    port map (
      C => clk,
      D => trd_cmd_data(6, 8),
      Q => ng(8)
    );
  nh_2 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 2),
      Q => nh(2)
    );
  nh_3 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 3),
      Q => nh(3)
    );
  nh_4 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 4),
      Q => nh(4)
    );
  nh_5 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 5),
      Q => nh(5)
    );
  nh_6 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 6),
      Q => nh(6)
    );
  nh_7 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 7),
      Q => nh(7)
    );
  nh_8 : FD
    port map (
      C => clk,
      D => trd_cmd_data(7, 8),
      Q => nh(8)
    );
  dpram_en0 : FDR
    port map (
      C => clk,
      D => flag_data_we_0_Q,
      R => dpram_en0_or0000,
      Q => dpram_en0_8098
    );
  data2_0 : FD
    port map (
      C => clk,
      D => lc_host_data(0),
      Q => NlwRenamedSig_OI_data2(0)
    );
  data2_1 : FD
    port map (
      C => clk,
      D => lc_host_data(1),
      Q => NlwRenamedSig_OI_data2(1)
    );
  data2_2 : FD
    port map (
      C => clk,
      D => lc_host_data(2),
      Q => NlwRenamedSig_OI_data2(2)
    );
  data2_3 : FD
    port map (
      C => clk,
      D => lc_host_data(3),
      Q => NlwRenamedSig_OI_data2(3)
    );
  data2_4 : FD
    port map (
      C => clk,
      D => lc_host_data(4),
      Q => NlwRenamedSig_OI_data2(4)
    );
  data2_5 : FD
    port map (
      C => clk,
      D => lc_host_data(5),
      Q => NlwRenamedSig_OI_data2(5)
    );
  data2_6 : FD
    port map (
      C => clk,
      D => lc_host_data(6),
      Q => NlwRenamedSig_OI_data2(6)
    );
  data2_7 : FD
    port map (
      C => clk,
      D => lc_host_data(7),
      Q => NlwRenamedSig_OI_data2(7)
    );
  data2_8 : FD
    port map (
      C => clk,
      D => lc_host_data(8),
      Q => NlwRenamedSig_OI_data2(8)
    );
  data2_9 : FD
    port map (
      C => clk,
      D => lc_host_data(9),
      Q => NlwRenamedSig_OI_data2(9)
    );
  data2_10 : FD
    port map (
      C => clk,
      D => lc_host_data(10),
      Q => NlwRenamedSig_OI_data2(10)
    );
  data2_11 : FD
    port map (
      C => clk,
      D => lc_host_data(11),
      Q => NlwRenamedSig_OI_data2(11)
    );
  data2_12 : FD
    port map (
      C => clk,
      D => lc_host_data(12),
      Q => NlwRenamedSig_OI_data2(12)
    );
  data2_13 : FD
    port map (
      C => clk,
      D => lc_host_data(13),
      Q => NlwRenamedSig_OI_data2(13)
    );
  data2_14 : FD
    port map (
      C => clk,
      D => lc_host_data(14),
      Q => NlwRenamedSig_OI_data2(14)
    );
  data2_15 : FD
    port map (
      C => clk,
      D => lc_host_data(15),
      Q => NlwRenamedSig_OI_data2(15)
    );
  data2_16 : FD
    port map (
      C => clk,
      D => lc_host_data(16),
      Q => NlwRenamedSig_OI_data2(16)
    );
  data2_17 : FD
    port map (
      C => clk,
      D => lc_host_data(17),
      Q => NlwRenamedSig_OI_data2(17)
    );
  data2_18 : FD
    port map (
      C => clk,
      D => lc_host_data(18),
      Q => NlwRenamedSig_OI_data2(18)
    );
  data2_19 : FD
    port map (
      C => clk,
      D => lc_host_data(19),
      Q => NlwRenamedSig_OI_data2(19)
    );
  data2_20 : FD
    port map (
      C => clk,
      D => lc_host_data(20),
      Q => NlwRenamedSig_OI_data2(20)
    );
  data2_21 : FD
    port map (
      C => clk,
      D => lc_host_data(21),
      Q => NlwRenamedSig_OI_data2(21)
    );
  data2_22 : FD
    port map (
      C => clk,
      D => lc_host_data(22),
      Q => NlwRenamedSig_OI_data2(22)
    );
  data2_23 : FD
    port map (
      C => clk,
      D => lc_host_data(23),
      Q => NlwRenamedSig_OI_data2(23)
    );
  data2_24 : FD
    port map (
      C => clk,
      D => lc_host_data(24),
      Q => NlwRenamedSig_OI_data2(24)
    );
  data2_25 : FD
    port map (
      C => clk,
      D => lc_host_data(25),
      Q => NlwRenamedSig_OI_data2(25)
    );
  data2_26 : FD
    port map (
      C => clk,
      D => lc_host_data(26),
      Q => NlwRenamedSig_OI_data2(26)
    );
  data2_27 : FD
    port map (
      C => clk,
      D => lc_host_data(27),
      Q => NlwRenamedSig_OI_data2(27)
    );
  data2_28 : FD
    port map (
      C => clk,
      D => lc_host_data(28),
      Q => NlwRenamedSig_OI_data2(28)
    );
  data2_29 : FD
    port map (
      C => clk,
      D => lc_host_data(29),
      Q => NlwRenamedSig_OI_data2(29)
    );
  data2_30 : FD
    port map (
      C => clk,
      D => lc_host_data(30),
      Q => NlwRenamedSig_OI_data2(30)
    );
  data2_31 : FD
    port map (
      C => clk,
      D => lc_host_data(31),
      Q => NlwRenamedSig_OI_data2(31)
    );
  data2_32 : FD
    port map (
      C => clk,
      D => lc_host_data(32),
      Q => NlwRenamedSig_OI_data2(32)
    );
  data2_33 : FD
    port map (
      C => clk,
      D => lc_host_data(33),
      Q => NlwRenamedSig_OI_data2(33)
    );
  data2_34 : FD
    port map (
      C => clk,
      D => lc_host_data(34),
      Q => NlwRenamedSig_OI_data2(34)
    );
  data2_35 : FD
    port map (
      C => clk,
      D => lc_host_data(35),
      Q => NlwRenamedSig_OI_data2(35)
    );
  data2_36 : FD
    port map (
      C => clk,
      D => lc_host_data(36),
      Q => NlwRenamedSig_OI_data2(36)
    );
  data2_37 : FD
    port map (
      C => clk,
      D => lc_host_data(37),
      Q => NlwRenamedSig_OI_data2(37)
    );
  data2_38 : FD
    port map (
      C => clk,
      D => lc_host_data(38),
      Q => NlwRenamedSig_OI_data2(38)
    );
  data2_39 : FD
    port map (
      C => clk,
      D => lc_host_data(39),
      Q => NlwRenamedSig_OI_data2(39)
    );
  data2_40 : FD
    port map (
      C => clk,
      D => lc_host_data(40),
      Q => NlwRenamedSig_OI_data2(40)
    );
  data2_41 : FD
    port map (
      C => clk,
      D => lc_host_data(41),
      Q => NlwRenamedSig_OI_data2(41)
    );
  data2_42 : FD
    port map (
      C => clk,
      D => lc_host_data(42),
      Q => NlwRenamedSig_OI_data2(42)
    );
  data2_43 : FD
    port map (
      C => clk,
      D => lc_host_data(43),
      Q => NlwRenamedSig_OI_data2(43)
    );
  data2_44 : FD
    port map (
      C => clk,
      D => lc_host_data(44),
      Q => NlwRenamedSig_OI_data2(44)
    );
  data2_45 : FD
    port map (
      C => clk,
      D => lc_host_data(45),
      Q => NlwRenamedSig_OI_data2(45)
    );
  data2_46 : FD
    port map (
      C => clk,
      D => lc_host_data(46),
      Q => NlwRenamedSig_OI_data2(46)
    );
  data2_47 : FD
    port map (
      C => clk,
      D => lc_host_data(47),
      Q => NlwRenamedSig_OI_data2(47)
    );
  data2_48 : FD
    port map (
      C => clk,
      D => lc_host_data(48),
      Q => NlwRenamedSig_OI_data2(48)
    );
  data2_49 : FD
    port map (
      C => clk,
      D => lc_host_data(49),
      Q => NlwRenamedSig_OI_data2(49)
    );
  data2_50 : FD
    port map (
      C => clk,
      D => lc_host_data(50),
      Q => NlwRenamedSig_OI_data2(50)
    );
  data2_51 : FD
    port map (
      C => clk,
      D => lc_host_data(51),
      Q => NlwRenamedSig_OI_data2(51)
    );
  data2_52 : FD
    port map (
      C => clk,
      D => lc_host_data(52),
      Q => NlwRenamedSig_OI_data2(52)
    );
  data2_53 : FD
    port map (
      C => clk,
      D => lc_host_data(53),
      Q => NlwRenamedSig_OI_data2(53)
    );
  data2_54 : FD
    port map (
      C => clk,
      D => lc_host_data(54),
      Q => NlwRenamedSig_OI_data2(54)
    );
  data2_55 : FD
    port map (
      C => clk,
      D => lc_host_data(55),
      Q => NlwRenamedSig_OI_data2(55)
    );
  data2_56 : FD
    port map (
      C => clk,
      D => lc_host_data(56),
      Q => NlwRenamedSig_OI_data2(56)
    );
  data2_57 : FD
    port map (
      C => clk,
      D => lc_host_data(57),
      Q => NlwRenamedSig_OI_data2(57)
    );
  data2_58 : FD
    port map (
      C => clk,
      D => lc_host_data(58),
      Q => NlwRenamedSig_OI_data2(58)
    );
  data2_59 : FD
    port map (
      C => clk,
      D => lc_host_data(59),
      Q => NlwRenamedSig_OI_data2(59)
    );
  data2_60 : FD
    port map (
      C => clk,
      D => lc_host_data(60),
      Q => NlwRenamedSig_OI_data2(60)
    );
  data2_61 : FD
    port map (
      C => clk,
      D => lc_host_data(61),
      Q => NlwRenamedSig_OI_data2(61)
    );
  data2_62 : FD
    port map (
      C => clk,
      D => lc_host_data(62),
      Q => NlwRenamedSig_OI_data2(62)
    );
  data2_63 : FD
    port map (
      C => clk,
      D => lc_host_data(63),
      Q => NlwRenamedSig_OI_data2(63)
    );
  irq1_6434 : FD
    port map (
      C => clk,
      D => int1,
      Q => irq1
    );
  adr2_1 : FD
    port map (
      C => clk,
      D => adr1(1),
      Q => adr2(1)
    );
  adr2_2 : FD
    port map (
      C => clk,
      D => adr1(2),
      Q => adr2(2)
    );
  adr2_3 : FD
    port map (
      C => clk,
      D => adr1(3),
      Q => adr2(3)
    );
  adr2_4 : FD
    port map (
      C => clk,
      D => adr1(4),
      Q => adr2(4)
    );
  adr2_5 : FD
    port map (
      C => clk,
      D => adr1(5),
      Q => adr2(5)
    );
  trd_host_adr_0 : FD
    port map (
      C => clk,
      D => lc_adr(0),
      Q => trd_host_adr(0)
    );
  trd_host_adr_1 : FD
    port map (
      C => clk,
      D => lc_adr(1),
      Q => trd_host_adr(1)
    );
  trd_host_adr_2 : FD
    port map (
      C => clk,
      D => lc_adr(2),
      Q => trd_host_adr(2)
    );
  trd_host_adr_3 : FD
    port map (
      C => clk,
      D => lc_adr(3),
      Q => trd_host_adr(3)
    );
  trd_host_adr_4 : FD
    port map (
      C => clk,
      D => lc_adr(4),
      Q => trd_host_adr(4)
    );
  trd_host_adr_5 : FD
    port map (
      C => clk,
      D => lc_adr(5),
      Q => trd_host_adr(5)
    );
  trd_host_adr_6 : FD
    port map (
      C => clk,
      D => lc_adr(6),
      Q => trd_host_adr(6)
    );
  addra_7 : FDR
    port map (
      C => clk,
      D => lc_adr(5),
      R => test_mode,
      Q => addra(7)
    );
  addra_5 : FDR
    port map (
      C => clk,
      D => lc_adr(3),
      R => test_mode,
      Q => addra(5)
    );
  addra_6 : FDR
    port map (
      C => clk,
      D => lc_adr(4),
      R => test_mode,
      Q => addra(6)
    );
  cmd3_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd3_adr_1_Q
    );
  cmd3_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd3_adr_0_Q
    );
  cmd3_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd3_adr_2_Q
    );
  cmd3_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd3_adr_3_Q
    );
  cmd3_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd3_adr_4_Q
    );
  cmd3_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd3_adr_8_Q
    );
  cmd3_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(3),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd3_adr_9_Q
    );
  rd2z : FD
    port map (
      C => clk,
      D => rd2_8534,
      Q => rd2z_8535
    );
  cmd0_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd0_adr_0_Q
    );
  cmd0_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd0_adr_2_Q
    );
  cmd0_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd0_adr_1_Q
    );
  cmd0_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd0_adr_3_Q
    );
  cmd0_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd0_adr_4_Q
    );
  cmd0_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd0_adr_8_Q
    );
  cmd0_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(0),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd0_adr_9_Q
    );
  main_mode2_4 : FDRE
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CE => main_mode2_4_and0000_8423,
      D => NlwRenamedSig_OI_data2(4),
      R => reset_inv,
      Q => main_mode2_4_8422
    );
  cmd5_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd5_adr_2_Q
    );
  cmd5_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd5_adr_0_Q
    );
  cmd5_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd5_adr_1_Q
    );
  cmd5_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd5_adr_3_Q
    );
  cmd5_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd5_adr_4_Q
    );
  cmd5_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd5_adr_9_Q
    );
  cmd5_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(5),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd5_adr_8_Q
    );
  cmd2_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd2_adr_0_Q
    );
  cmd2_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd2_adr_1_Q
    );
  cmd2_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd2_adr_2_Q
    );
  cmd2_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd2_adr_3_Q
    );
  cmd2_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd2_adr_4_Q
    );
  trd4i_host_data_10 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(10),
      Q => trd4i_host_data(10)
    );
  trd4i_host_data_11 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(11),
      Q => trd4i_host_data(11)
    );
  cmd2_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd2_adr_9_Q
    );
  cmd2_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(2),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd2_adr_8_Q
    );
  trd4i_host_data_12 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(12),
      Q => trd4i_host_data(12)
    );
  trd4i_host_data_13 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(13),
      Q => trd4i_host_data(13)
    );
  trd4i_host_data_14 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(14),
      Q => trd4i_host_data(14)
    );
  trd4i_host_data_15 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(15),
      Q => trd4i_host_data(15)
    );
  trd4i_host_data_20 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(20),
      Q => trd4i_host_data(20)
    );
  trd4i_host_data_16 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(16),
      Q => trd4i_host_data(16)
    );
  trd4i_host_data_21 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(21),
      Q => trd4i_host_data(21)
    );
  trd4i_host_data_22 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(22),
      Q => trd4i_host_data(22)
    );
  trd4i_host_data_17 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(17),
      Q => trd4i_host_data(17)
    );
  trd4i_host_data_23 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(23),
      Q => trd4i_host_data(23)
    );
  trd4i_host_data_18 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(18),
      Q => trd4i_host_data(18)
    );
  trd4i_host_data_24 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(24),
      Q => trd4i_host_data(24)
    );
  trd4i_host_data_19 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(19),
      Q => trd4i_host_data(19)
    );
  trd4i_host_data_31 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(31),
      Q => trd4i_host_data(31)
    );
  trd4i_host_data_30 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(30),
      Q => trd4i_host_data(30)
    );
  trd4i_host_data_25 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(25),
      Q => trd4i_host_data(25)
    );
  trd4i_host_data_26 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(26),
      Q => trd4i_host_data(26)
    );
  trd4i_host_data_27 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(27),
      Q => trd4i_host_data(27)
    );
  trd4i_host_data_28 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(28),
      Q => trd4i_host_data(28)
    );
  cmd7_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd7_adr_1_Q
    );
  trd4i_host_data_29 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(29),
      Q => trd4i_host_data(29)
    );
  cmd7_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd7_adr_0_Q
    );
  cmd7_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd7_adr_2_Q
    );
  cmd7_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd7_adr_3_Q
    );
  cmd7_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd7_adr_4_Q
    );
  cmd7_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd7_adr_8_Q
    );
  cmd7_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(7),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd7_adr_9_Q
    );
  cmd4_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd4_adr_0_Q
    );
  cmd4_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd4_adr_1_Q
    );
  cmd4_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd4_adr_3_Q
    );
  cmd4_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd4_adr_2_Q
    );
  cmd4_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd4_adr_4_Q
    );
  cmd4_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd4_adr_8_Q
    );
  cmd4_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(4),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd4_adr_9_Q
    );
  cmd1_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd1_adr_0_Q
    );
  cmd1_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd1_adr_1_Q
    );
  cmd1_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd1_adr_2_Q
    );
  cmd1_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd1_adr_4_Q
    );
  cmd1_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd1_adr_3_Q
    );
  cmd1_adr_5 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(5),
      Q => cmd1_adr(5)
    );
  cmd1_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd1_adr_9_Q
    );
  cmd1_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(1),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd1_adr_8_Q
    );
  trd4i_host_data_0 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(0),
      Q => trd4i_host_data(0)
    );
  trd4i_host_data_1 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(1),
      Q => trd4i_host_data(1)
    );
  trd4i_host_data_2 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(2),
      Q => trd4i_host_data(2)
    );
  trd4i_host_data_5 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(5),
      Q => trd4i_host_data(5)
    );
  trd4i_host_data_3 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(3),
      Q => trd4i_host_data(3)
    );
  trd4i_host_data_4 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(4),
      Q => trd4i_host_data(4)
    );
  trd4i_host_data_6 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(6),
      Q => trd4i_host_data(6)
    );
  trd4i_host_data_7 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(7),
      Q => trd4i_host_data(7)
    );
  trd4i_host_data_8 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(8),
      Q => trd4i_host_data(8)
    );
  cmd6_adr_1 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(1),
      Q => NlwRenamedSig_OI_cmd6_adr_1_Q
    );
  trd4i_host_data_9 : FDE
    port map (
      C => clk,
      CE => trd4i_host_data_10_and0000,
      D => NlwRenamedSig_OI_data2(9),
      Q => trd4i_host_data(9)
    );
  cmd6_adr_0 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(0),
      Q => NlwRenamedSig_OI_cmd6_adr_0_Q
    );
  cmd6_adr_2 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(2),
      Q => NlwRenamedSig_OI_cmd6_adr_2_Q
    );
  cmd6_adr_3 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(3),
      Q => NlwRenamedSig_OI_cmd6_adr_3_Q
    );
  cmd6_adr_4 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(4),
      Q => NlwRenamedSig_OI_cmd6_adr_4_Q
    );
  cmd6_adr_8 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(8),
      Q => NlwRenamedSig_OI_cmd6_adr_8_Q
    );
  cmd6_adr_9 : FDCE
    port map (
      C => clk,
      CE => bl_cmd_adr_we(6),
      CLR => reset_inv,
      D => NlwRenamedSig_OI_data2(9),
      Q => NlwRenamedSig_OI_cmd6_adr_9_Q
    );
  mux_sel_2 : FDR
    port map (
      C => clk,
      D => adr2(5),
      R => Mrom_mux_sel_3_mux0001,
      Q => mux_sel(2)
    );
  mux_sel_3 : FD
    port map (
      C => clk,
      D => Mrom_mux_sel_3_mux0001,
      Q => mux_sel(3)
    );
  mab_0 : FD
    port map (
      C => clk,
      D => cmd_data2(0),
      Q => mab(0)
    );
  mab_1 : FD
    port map (
      C => clk,
      D => cmd_data2(1),
      Q => mab(1)
    );
  mab_2 : FD
    port map (
      C => clk,
      D => cmd_data2(2),
      Q => mab(2)
    );
  mab_3 : FD
    port map (
      C => clk,
      D => cmd_data2(3),
      Q => mab(3)
    );
  mab_4 : FD
    port map (
      C => clk,
      D => cmd_data2(4),
      Q => mab(4)
    );
  mab_5 : FD
    port map (
      C => clk,
      D => cmd_data2(5),
      Q => mab(5)
    );
  mab_6 : FD
    port map (
      C => clk,
      D => cmd_data2(6),
      Q => mab(6)
    );
  mab_7 : FD
    port map (
      C => clk,
      D => cmd_data2(7),
      Q => mab(7)
    );
  mab_8 : FD
    port map (
      C => clk,
      D => cmd_data2(8),
      Q => mab(8)
    );
  mab_9 : FD
    port map (
      C => clk,
      D => cmd_data2(9),
      Q => mab(9)
    );
  mab_10 : FD
    port map (
      C => clk,
      D => cmd_data2(10),
      Q => mab(10)
    );
  mab_11 : FD
    port map (
      C => clk,
      D => cmd_data2(11),
      Q => mab(11)
    );
  mab_12 : FD
    port map (
      C => clk,
      D => cmd_data2(12),
      Q => mab(12)
    );
  mab_13 : FD
    port map (
      C => clk,
      D => cmd_data2(13),
      Q => mab(13)
    );
  mab_14 : FD
    port map (
      C => clk,
      D => cmd_data2(14),
      Q => mab(14)
    );
  mab_15 : FD
    port map (
      C => clk,
      D => cmd_data2(15),
      Q => mab(15)
    );
  flag_data_we_4 : FDSE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      S => main_mode2_4_inv,
      Q => flag_data_we_4_Q
    );
  addra_0 : FD
    port map (
      C => clk,
      D => addra_0_mux0001,
      Q => addra(0)
    );
  addra_1 : FD
    port map (
      C => clk,
      D => addra_1_mux0001,
      Q => addra(1)
    );
  addra_2 : FD
    port map (
      C => clk,
      D => addra_2_mux0001,
      Q => addra(2)
    );
  addra_3 : FD
    port map (
      C => clk,
      D => addra_3_mux0001,
      Q => addra(3)
    );
  addra_4 : FD
    port map (
      C => clk,
      D => addra_4_mux0001,
      Q => addra(4)
    );
  flag_rd_repack_0 : FDRE
    port map (
      C => clk,
      CE => bl_data_cs_0_inv,
      D => flag_rd_repack_0_not0001,
      R => flag_rd_repack_0_or0000,
      Q => flag_rd_repack_0_Q
    );
  addra_8 : FD
    port map (
      C => clk,
      D => addra_8_mux0001,
      Q => addra(8)
    );
  addra_9 : FD
    port map (
      C => clk,
      D => sel_cmd_data,
      Q => addra(9)
    );
  flag_rd_repack_6 : FDRE
    port map (
      C => clk,
      CE => bl_data_cs_6_inv,
      D => flag_rd_repack_6_not0001,
      R => flag_rd_repack_6_or0000,
      Q => flag_rd_repack_6_Q
    );
  flag_rd_block_0 : FDRSE
    port map (
      C => clk,
      CE => bl_data_cs_0_inv,
      D => flag_rd_block_0_not0001,
      R => trd_drq_0_en,
      S => trd_reset_fifo_0_inv,
      Q => flag_rd_block_0_Q
    );
  flag_rd_block_6 : FDRSE
    port map (
      C => clk,
      CE => bl_data_cs_6_inv,
      D => flag_rd_block_6_not0001,
      R => trd_drq_6_en,
      S => trd_reset_fifo_6_inv,
      Q => flag_rd_block_6_Q
    );
  maa_0 : FD
    port map (
      C => clk,
      D => rom_data2(0),
      Q => maa(0)
    );
  maa_1 : FD
    port map (
      C => clk,
      D => rom_data2(1),
      Q => maa(1)
    );
  maa_2 : FD
    port map (
      C => clk,
      D => rom_data2(2),
      Q => maa(2)
    );
  maa_3 : FD
    port map (
      C => clk,
      D => rom_data2(3),
      Q => maa(3)
    );
  maa_4 : FD
    port map (
      C => clk,
      D => rom_data2(4),
      Q => maa(4)
    );
  maa_5 : FD
    port map (
      C => clk,
      D => rom_data2(5),
      Q => maa(5)
    );
  maa_6 : FD
    port map (
      C => clk,
      D => rom_data2(6),
      Q => maa(6)
    );
  maa_7 : FD
    port map (
      C => clk,
      D => rom_data2(7),
      Q => maa(7)
    );
  maa_8 : FD
    port map (
      C => clk,
      D => rom_data2(8),
      Q => maa(8)
    );
  maa_9 : FD
    port map (
      C => clk,
      D => rom_data2(9),
      Q => maa(9)
    );
  maa_10 : FD
    port map (
      C => clk,
      D => rom_data2(10),
      Q => maa(10)
    );
  maa_11 : FD
    port map (
      C => clk,
      D => rom_data2(11),
      Q => maa(11)
    );
  maa_12 : FD
    port map (
      C => clk,
      D => rom_data2(12),
      Q => maa(12)
    );
  maa_13 : FD
    port map (
      C => clk,
      D => rom_data2(13),
      Q => maa(13)
    );
  maa_14 : FD
    port map (
      C => clk,
      D => rom_data2(14),
      Q => maa(14)
    );
  maa_15 : FD
    port map (
      C => clk,
      D => rom_data2(15),
      Q => maa(15)
    );
  lc_data_0 : FD
    port map (
      C => clk,
      D => lc_data_i(0),
      Q => lc_data(0)
    );
  lc_data_1 : FD
    port map (
      C => clk,
      D => lc_data_i(1),
      Q => lc_data(1)
    );
  lc_data_2 : FD
    port map (
      C => clk,
      D => lc_data_i(2),
      Q => lc_data(2)
    );
  lc_data_3 : FD
    port map (
      C => clk,
      D => lc_data_i(3),
      Q => lc_data(3)
    );
  lc_data_4 : FD
    port map (
      C => clk,
      D => lc_data_i(4),
      Q => lc_data(4)
    );
  lc_data_5 : FD
    port map (
      C => clk,
      D => lc_data_i(5),
      Q => lc_data(5)
    );
  lc_data_6 : FD
    port map (
      C => clk,
      D => lc_data_i(6),
      Q => lc_data(6)
    );
  lc_data_7 : FD
    port map (
      C => clk,
      D => lc_data_i(7),
      Q => lc_data(7)
    );
  lc_data_8 : FD
    port map (
      C => clk,
      D => lc_data_i(8),
      Q => lc_data(8)
    );
  lc_data_9 : FD
    port map (
      C => clk,
      D => lc_data_i(9),
      Q => lc_data(9)
    );
  lc_data_10 : FD
    port map (
      C => clk,
      D => lc_data_i(10),
      Q => lc_data(10)
    );
  lc_data_11 : FD
    port map (
      C => clk,
      D => lc_data_i(11),
      Q => lc_data(11)
    );
  lc_data_12 : FD
    port map (
      C => clk,
      D => lc_data_i(12),
      Q => lc_data(12)
    );
  lc_data_13 : FD
    port map (
      C => clk,
      D => lc_data_i(13),
      Q => lc_data(13)
    );
  lc_data_14 : FD
    port map (
      C => clk,
      D => lc_data_i(14),
      Q => lc_data(14)
    );
  lc_data_15 : FD
    port map (
      C => clk,
      D => lc_data_i(15),
      Q => lc_data(15)
    );
  lc_data_16 : FD
    port map (
      C => clk,
      D => lc_data_i(16),
      Q => lc_data(16)
    );
  lc_data_17 : FD
    port map (
      C => clk,
      D => lc_data_i(17),
      Q => lc_data(17)
    );
  lc_data_18 : FD
    port map (
      C => clk,
      D => lc_data_i(18),
      Q => lc_data(18)
    );
  lc_data_19 : FD
    port map (
      C => clk,
      D => lc_data_i(19),
      Q => lc_data(19)
    );
  lc_data_20 : FD
    port map (
      C => clk,
      D => lc_data_i(20),
      Q => lc_data(20)
    );
  lc_data_21 : FD
    port map (
      C => clk,
      D => lc_data_i(21),
      Q => lc_data(21)
    );
  lc_data_22 : FD
    port map (
      C => clk,
      D => lc_data_i(22),
      Q => lc_data(22)
    );
  lc_data_23 : FD
    port map (
      C => clk,
      D => lc_data_i(23),
      Q => lc_data(23)
    );
  lc_data_24 : FD
    port map (
      C => clk,
      D => lc_data_i(24),
      Q => lc_data(24)
    );
  lc_data_25 : FD
    port map (
      C => clk,
      D => lc_data_i(25),
      Q => lc_data(25)
    );
  lc_data_26 : FD
    port map (
      C => clk,
      D => lc_data_i(26),
      Q => lc_data(26)
    );
  lc_data_27 : FD
    port map (
      C => clk,
      D => lc_data_i(27),
      Q => lc_data(27)
    );
  lc_data_28 : FD
    port map (
      C => clk,
      D => lc_data_i(28),
      Q => lc_data(28)
    );
  lc_data_29 : FD
    port map (
      C => clk,
      D => lc_data_i(29),
      Q => lc_data(29)
    );
  lc_data_30 : FD
    port map (
      C => clk,
      D => lc_data_i(30),
      Q => lc_data(30)
    );
  lc_data_31 : FD
    port map (
      C => clk,
      D => lc_data_i(31),
      Q => lc_data(31)
    );
  lc_data_32 : FD
    port map (
      C => clk,
      D => lc_data_i(32),
      Q => lc_data(32)
    );
  lc_data_33 : FD
    port map (
      C => clk,
      D => lc_data_i(33),
      Q => lc_data(33)
    );
  lc_data_34 : FD
    port map (
      C => clk,
      D => lc_data_i(34),
      Q => lc_data(34)
    );
  lc_data_35 : FD
    port map (
      C => clk,
      D => lc_data_i(35),
      Q => lc_data(35)
    );
  lc_data_36 : FD
    port map (
      C => clk,
      D => lc_data_i(36),
      Q => lc_data(36)
    );
  lc_data_37 : FD
    port map (
      C => clk,
      D => lc_data_i(37),
      Q => lc_data(37)
    );
  lc_data_38 : FD
    port map (
      C => clk,
      D => lc_data_i(38),
      Q => lc_data(38)
    );
  lc_data_39 : FD
    port map (
      C => clk,
      D => lc_data_i(39),
      Q => lc_data(39)
    );
  lc_data_40 : FD
    port map (
      C => clk,
      D => lc_data_i(40),
      Q => lc_data(40)
    );
  lc_data_41 : FD
    port map (
      C => clk,
      D => lc_data_i(41),
      Q => lc_data(41)
    );
  lc_data_42 : FD
    port map (
      C => clk,
      D => lc_data_i(42),
      Q => lc_data(42)
    );
  lc_data_43 : FD
    port map (
      C => clk,
      D => lc_data_i(43),
      Q => lc_data(43)
    );
  lc_data_44 : FD
    port map (
      C => clk,
      D => lc_data_i(44),
      Q => lc_data(44)
    );
  lc_data_45 : FD
    port map (
      C => clk,
      D => lc_data_i(45),
      Q => lc_data(45)
    );
  lc_data_46 : FD
    port map (
      C => clk,
      D => lc_data_i(46),
      Q => lc_data(46)
    );
  lc_data_47 : FD
    port map (
      C => clk,
      D => lc_data_i(47),
      Q => lc_data(47)
    );
  lc_data_48 : FD
    port map (
      C => clk,
      D => lc_data_i(48),
      Q => lc_data(48)
    );
  lc_data_49 : FD
    port map (
      C => clk,
      D => lc_data_i(49),
      Q => lc_data(49)
    );
  lc_data_50 : FD
    port map (
      C => clk,
      D => lc_data_i(50),
      Q => lc_data(50)
    );
  lc_data_51 : FD
    port map (
      C => clk,
      D => lc_data_i(51),
      Q => lc_data(51)
    );
  lc_data_52 : FD
    port map (
      C => clk,
      D => lc_data_i(52),
      Q => lc_data(52)
    );
  lc_data_53 : FD
    port map (
      C => clk,
      D => lc_data_i(53),
      Q => lc_data(53)
    );
  lc_data_54 : FD
    port map (
      C => clk,
      D => lc_data_i(54),
      Q => lc_data(54)
    );
  lc_data_55 : FD
    port map (
      C => clk,
      D => lc_data_i(55),
      Q => lc_data(55)
    );
  lc_data_56 : FD
    port map (
      C => clk,
      D => lc_data_i(56),
      Q => lc_data(56)
    );
  lc_data_57 : FD
    port map (
      C => clk,
      D => lc_data_i(57),
      Q => lc_data(57)
    );
  lc_data_58 : FD
    port map (
      C => clk,
      D => lc_data_i(58),
      Q => lc_data(58)
    );
  lc_data_59 : FD
    port map (
      C => clk,
      D => lc_data_i(59),
      Q => lc_data(59)
    );
  lc_data_60 : FD
    port map (
      C => clk,
      D => lc_data_i(60),
      Q => lc_data(60)
    );
  lc_data_61 : FD
    port map (
      C => clk,
      D => lc_data_i(61),
      Q => lc_data(61)
    );
  lc_data_62 : FD
    port map (
      C => clk,
      D => lc_data_i(62),
      Q => lc_data(62)
    );
  lc_data_63 : FD
    port map (
      C => clk,
      D => lc_data_i(63),
      Q => lc_data(63)
    );
  Mmux_sel_cmd_data_4 : LUT6
    generic map(
      INIT => X"AAAACCCCFF00F0F0"
    )
    port map (
      I0 => NlwRenamedSig_OI_cmd3_adr_9_Q,
      I1 => NlwRenamedSig_OI_cmd2_adr_9_Q,
      I2 => NlwRenamedSig_OI_cmd0_adr_9_Q,
      I3 => NlwRenamedSig_OI_cmd1_adr_9_Q,
      I4 => adr1(3),
      I5 => adr1(4),
      O => Mmux_sel_cmd_data_4_7910
    );
  Mmux_sel_cmd_data_3 : LUT6
    generic map(
      INIT => X"F0F0FF00CCCCAAAA"
    )
    port map (
      I0 => NlwRenamedSig_OI_cmd4_adr_9_Q,
      I1 => NlwRenamedSig_OI_cmd5_adr_9_Q,
      I2 => NlwRenamedSig_OI_cmd7_adr_9_Q,
      I3 => NlwRenamedSig_OI_cmd6_adr_9_Q,
      I4 => adr1(3),
      I5 => adr1(4),
      O => Mmux_sel_cmd_data_3_7909
    );
  Mmux_addra_0_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_0_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_0_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_0_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_0_Q,
      O => Mmux_addra_0_mux0001_4_7898
    );
  Mmux_addra_0_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_0_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_0_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_0_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_0_Q,
      O => Mmux_addra_0_mux0001_3_7897
    );
  Mmux_addra_1_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_1_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_1_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_1_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_1_Q,
      O => Mmux_addra_1_mux0001_4_7900
    );
  Mmux_addra_1_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_1_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_1_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_1_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_1_Q,
      O => Mmux_addra_1_mux0001_3_7899
    );
  Mmux_addra_2_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_2_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_2_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_2_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_2_Q,
      O => Mmux_addra_2_mux0001_4_7902
    );
  Mmux_addra_2_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_2_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_2_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_2_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_2_Q,
      O => Mmux_addra_2_mux0001_3_7901
    );
  Mmux_addra_8_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_8_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_8_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_8_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_8_Q,
      O => Mmux_addra_8_mux0001_4_7908
    );
  Mmux_addra_8_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_8_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_8_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_8_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_8_Q,
      O => Mmux_addra_8_mux0001_3_7907
    );
  Mmux_addra_3_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_3_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_3_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_3_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_3_Q,
      O => Mmux_addra_3_mux0001_4_7904
    );
  Mmux_addra_3_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_3_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_3_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_3_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_3_Q,
      O => Mmux_addra_3_mux0001_3_7903
    );
  Mmux_addra_4_mux0001_4 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd2_adr_4_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd1_adr_4_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_4_Q,
      I5 => NlwRenamedSig_OI_cmd3_adr_4_Q,
      O => Mmux_addra_4_mux0001_4_7906
    );
  Mmux_addra_4_mux0001_3 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => adr1(3),
      I1 => NlwRenamedSig_OI_cmd6_adr_4_Q,
      I2 => adr1(4),
      I3 => NlwRenamedSig_OI_cmd5_adr_4_Q,
      I4 => NlwRenamedSig_OI_cmd4_adr_4_Q,
      I5 => NlwRenamedSig_OI_cmd7_adr_4_Q,
      O => Mmux_addra_4_mux0001_3_7905
    );
  mux8 : ctrl_mux8x48
    port map (
      o(47) => lc_data_i(63),
      o(46) => lc_data_i(62),
      o(45) => lc_data_i(61),
      o(44) => lc_data_i(60),
      o(43) => lc_data_i(59),
      o(42) => lc_data_i(58),
      o(41) => lc_data_i(57),
      o(40) => lc_data_i(56),
      o(39) => lc_data_i(55),
      o(38) => lc_data_i(54),
      o(37) => lc_data_i(53),
      o(36) => lc_data_i(52),
      o(35) => lc_data_i(51),
      o(34) => lc_data_i(50),
      o(33) => lc_data_i(49),
      o(32) => lc_data_i(48),
      o(31) => lc_data_i(47),
      o(30) => lc_data_i(46),
      o(29) => lc_data_i(45),
      o(28) => lc_data_i(44),
      o(27) => lc_data_i(43),
      o(26) => lc_data_i(42),
      o(25) => lc_data_i(41),
      o(24) => lc_data_i(40),
      o(23) => lc_data_i(39),
      o(22) => lc_data_i(38),
      o(21) => lc_data_i(37),
      o(20) => lc_data_i(36),
      o(19) => lc_data_i(35),
      o(18) => lc_data_i(34),
      o(17) => lc_data_i(33),
      o(16) => lc_data_i(32),
      o(15) => lc_data_i(31),
      o(14) => lc_data_i(30),
      o(13) => lc_data_i(29),
      o(12) => lc_data_i(28),
      o(11) => lc_data_i(27),
      o(10) => lc_data_i(26),
      o(9) => lc_data_i(25),
      o(8) => lc_data_i(24),
      o(7) => lc_data_i(23),
      o(6) => lc_data_i(22),
      o(5) => lc_data_i(21),
      o(4) => lc_data_i(20),
      o(3) => lc_data_i(19),
      o(2) => lc_data_i(18),
      o(1) => lc_data_i(17),
      o(0) => lc_data_i(16),
      ma(47) => ma(63),
      ma(46) => ma(62),
      ma(45) => ma(61),
      ma(44) => ma(60),
      ma(43) => ma(59),
      ma(42) => ma(58),
      ma(41) => ma(57),
      ma(40) => ma(56),
      ma(39) => ma(55),
      ma(38) => ma(54),
      ma(37) => ma(53),
      ma(36) => ma(52),
      ma(35) => ma(51),
      ma(34) => ma(50),
      ma(33) => ma(49),
      ma(32) => ma(48),
      ma(31) => ma(47),
      ma(30) => ma(46),
      ma(29) => ma(45),
      ma(28) => ma(44),
      ma(27) => ma(43),
      ma(26) => ma(42),
      ma(25) => ma(41),
      ma(24) => ma(40),
      ma(23) => ma(39),
      ma(22) => ma(38),
      ma(21) => ma(37),
      ma(20) => ma(36),
      ma(19) => ma(35),
      ma(18) => ma(34),
      ma(17) => ma(33),
      ma(16) => ma(32),
      ma(15) => ma(31),
      ma(14) => ma(30),
      ma(13) => ma(29),
      ma(12) => ma(28),
      ma(11) => ma(27),
      ma(10) => ma(26),
      ma(9) => ma(25),
      ma(8) => ma(24),
      ma(7) => ma(23),
      ma(6) => ma(22),
      ma(5) => ma(21),
      ma(4) => ma(20),
      ma(3) => ma(19),
      ma(2) => ma(18),
      ma(1) => ma(17),
      ma(0) => ma(16),
      mb(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(47) => mg(63),
      mg(46) => mg(62),
      mg(45) => mg(61),
      mg(44) => mg(60),
      mg(43) => mg(59),
      mg(42) => mg(58),
      mg(41) => mg(57),
      mg(40) => mg(56),
      mg(39) => mg(55),
      mg(38) => mg(54),
      mg(37) => mg(53),
      mg(36) => mg(52),
      mg(35) => mg(51),
      mg(34) => mg(50),
      mg(33) => mg(49),
      mg(32) => mg(48),
      mg(31) => mg(47),
      mg(30) => mg(46),
      mg(29) => mg(45),
      mg(28) => mg(44),
      mg(27) => mg(43),
      mg(26) => mg(42),
      mg(25) => mg(41),
      mg(24) => mg(40),
      mg(23) => mg(39),
      mg(22) => mg(38),
      mg(21) => mg(37),
      mg(20) => mg(36),
      mg(19) => mg(35),
      mg(18) => mg(34),
      mg(17) => mg(33),
      mg(16) => mg(32),
      mg(15) => mg(31),
      mg(14) => mg(30),
      mg(13) => mg(29),
      mg(12) => mg(28),
      mg(11) => mg(27),
      mg(10) => mg(26),
      mg(9) => mg(25),
      mg(8) => mg(24),
      mg(7) => mg(23),
      mg(6) => mg(22),
      mg(5) => mg(21),
      mg(4) => mg(20),
      mg(3) => mg(19),
      mg(2) => mg(18),
      mg(1) => mg(17),
      mg(0) => mg(16),
      mh(47) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(46) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(45) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(44) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(43) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(42) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(41) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(40) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(39) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(38) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(37) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(36) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(35) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(34) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(33) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(32) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(31) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(30) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(29) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(28) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(27) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(26) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(25) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(24) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(23) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(22) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(21) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(20) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(19) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(18) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(17) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(16) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      s(2) => mux_sel(2),
      s(1) => mux_sel(1),
      s(0) => mux_sel(0)
    );
  mux16 : ctrl_mux16x16
    port map (
      o(15) => lc_data_i(15),
      o(14) => lc_data_i(14),
      o(13) => lc_data_i(13),
      o(12) => lc_data_i(12),
      o(11) => lc_data_i(11),
      o(10) => lc_data_i(10),
      o(9) => lc_data_i(9),
      o(8) => lc_data_i(8),
      o(7) => lc_data_i(7),
      o(6) => lc_data_i(6),
      o(5) => lc_data_i(5),
      o(4) => lc_data_i(4),
      o(3) => lc_data_i(3),
      o(2) => lc_data_i(2),
      o(1) => lc_data_i(1),
      o(0) => lc_data_i(0),
      mab(15) => mab(15),
      mab(14) => mab(14),
      mab(13) => mab(13),
      mab(12) => mab(12),
      mab(11) => mab(11),
      mab(10) => mab(10),
      mab(9) => mab(9),
      mab(8) => mab(8),
      mab(7) => mab(7),
      mab(6) => mab(6),
      mab(5) => mab(5),
      mab(4) => mab(4),
      mab(3) => mab(3),
      mab(2) => mab(2),
      mab(1) => mab(1),
      mab(0) => mab(0),
      mac(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(9) => mac_9_Q,
      mac(8) => mac_8_Q,
      mac(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mac(4) => mac_4_Q,
      mac(3) => mac_3_Q,
      mac(2) => mac_2_Q,
      mac(1) => mac_1_Q,
      mac(0) => mac_0_Q,
      mad(15) => flag_data_we_0_Q,
      mad(14) => flag_data_we_0_Q,
      mad(13) => flag_data_we_0_Q,
      mad(12) => flag_data_we_0_Q,
      mad(11) => flag_data_we_0_Q,
      mad(10) => flag_data_we_0_Q,
      mad(9) => flag_data_we_0_Q,
      mad(8) => flag_data_we_0_Q,
      mad(7) => flag_data_we_0_Q,
      mad(6) => flag_data_we_0_Q,
      mad(5) => flag_data_we_0_Q,
      mad(4) => flag_data_we_0_Q,
      mad(3) => flag_data_we_0_Q,
      mad(2) => flag_data_we_0_Q,
      mad(1) => flag_data_we_0_Q,
      mad(0) => flag_data_we_0_Q,
      mae(15) => flag_data_we_0_Q,
      mae(14) => flag_data_we_0_Q,
      mae(13) => flag_data_we_0_Q,
      mae(12) => flag_data_we_0_Q,
      mae(11) => flag_data_we_0_Q,
      mae(10) => flag_data_we_0_Q,
      mae(9) => flag_data_we_0_Q,
      mae(8) => flag_data_we_0_Q,
      mae(7) => flag_data_we_0_Q,
      mae(6) => flag_data_we_0_Q,
      mae(5) => flag_data_we_0_Q,
      mae(4) => flag_data_we_0_Q,
      mae(3) => flag_data_we_0_Q,
      mae(2) => flag_data_we_0_Q,
      mae(1) => flag_data_we_0_Q,
      mae(0) => flag_data_we_0_Q,
      maf(15) => flag_data_we_0_Q,
      maf(14) => flag_data_we_0_Q,
      maf(13) => flag_data_we_0_Q,
      maf(12) => flag_data_we_0_Q,
      maf(11) => flag_data_we_0_Q,
      maf(10) => flag_data_we_0_Q,
      maf(9) => flag_data_we_0_Q,
      maf(8) => flag_data_we_0_Q,
      maf(7) => flag_data_we_0_Q,
      maf(6) => flag_data_we_0_Q,
      maf(5) => flag_data_we_0_Q,
      maf(4) => flag_data_we_0_Q,
      maf(3) => flag_data_we_0_Q,
      maf(2) => flag_data_we_0_Q,
      maf(1) => flag_data_we_0_Q,
      maf(0) => flag_data_we_0_Q,
      mag(15) => flag_data_we_0_Q,
      mag(14) => flag_data_we_0_Q,
      mag(13) => flag_data_we_0_Q,
      mag(12) => flag_data_we_0_Q,
      mag(11) => flag_data_we_0_Q,
      mag(10) => flag_data_we_0_Q,
      mag(9) => flag_data_we_0_Q,
      mag(8) => flag_data_we_0_Q,
      mag(7) => flag_data_we_0_Q,
      mag(6) => flag_data_we_0_Q,
      mag(5) => flag_data_we_0_Q,
      mag(4) => flag_data_we_0_Q,
      mag(3) => flag_data_we_0_Q,
      mag(2) => flag_data_we_0_Q,
      mag(1) => flag_data_we_0_Q,
      mag(0) => flag_data_we_0_Q,
      mah(15) => flag_data_we_0_Q,
      mah(14) => flag_data_we_0_Q,
      mah(13) => flag_data_we_0_Q,
      mah(12) => flag_data_we_0_Q,
      mah(11) => flag_data_we_0_Q,
      mah(10) => flag_data_we_0_Q,
      mah(9) => flag_data_we_0_Q,
      mah(8) => flag_data_we_0_Q,
      mah(7) => flag_data_we_0_Q,
      mah(6) => flag_data_we_0_Q,
      mah(5) => flag_data_we_0_Q,
      mah(4) => flag_data_we_0_Q,
      mah(3) => flag_data_we_0_Q,
      mah(2) => flag_data_we_0_Q,
      mah(1) => flag_data_we_0_Q,
      mah(0) => flag_data_we_0_Q,
      ma(15) => ma(15),
      ma(14) => ma(14),
      ma(13) => ma(13),
      ma(12) => ma(12),
      ma(11) => ma(11),
      ma(10) => ma(10),
      ma(9) => ma(9),
      ma(8) => ma(8),
      ma(7) => ma(7),
      ma(6) => ma(6),
      ma(5) => ma(5),
      ma(4) => ma(4),
      ma(3) => ma(3),
      ma(2) => ma(2),
      ma(1) => ma(1),
      ma(0) => ma(0),
      mb(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mb(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mc(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      md(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      me(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mf(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(15) => mg(15),
      mg(14) => mg(14),
      mg(13) => mg(13),
      mg(12) => mg(12),
      mg(11) => mg(11),
      mg(10) => mg(10),
      mg(9) => mg(9),
      mg(8) => mg(8),
      mg(7) => mg(7),
      mg(6) => mg(6),
      mg(5) => mg(5),
      mg(4) => mg(4),
      mg(3) => mg(3),
      mg(2) => mg(2),
      mg(1) => mg(1),
      mg(0) => mg(0),
      mh(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(6) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(5) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(3) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(2) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      s(3) => mux_sel(3),
      s(2) => mux_sel(2),
      s(1) => mux_sel(1),
      s(0) => mux_sel(0),
      maa(15) => maa(15),
      maa(14) => maa(14),
      maa(13) => maa(13),
      maa(12) => maa(12),
      maa(11) => maa(11),
      maa(10) => maa(10),
      maa(9) => maa(9),
      maa(8) => maa(8),
      maa(7) => maa(7),
      maa(6) => maa(6),
      maa(5) => maa(5),
      maa(4) => maa(4),
      maa(3) => maa(3),
      maa(2) => maa(2),
      maa(1) => maa(1),
      maa(0) => maa(0)
    );
  mux_cmd : ctrl_mux8x16r
    port map (
      clk => clk,
      q(15) => cmd_data2(15),
      q(14) => cmd_data2(14),
      q(13) => cmd_data2(13),
      q(12) => cmd_data2(12),
      q(11) => cmd_data2(11),
      q(10) => cmd_data2(10),
      q(9) => cmd_data2(9),
      q(8) => cmd_data2(8),
      q(7) => cmd_data2(7),
      q(6) => cmd_data2(6),
      q(5) => cmd_data2(5),
      q(4) => cmd_data2(4),
      q(3) => cmd_data2(3),
      q(2) => cmd_data2(2),
      q(1) => cmd_data2(1),
      q(0) => cmd_data2(0),
      ma(15) => na_15_Q,
      ma(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(8) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(7) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(6) => na_6_Q,
      ma(5) => na_5_Q,
      ma(4) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ma(3) => na_3_Q,
      ma(2) => na_2_Q,
      ma(1) => na_1_Q,
      ma(0) => na_0_Q,
      mb(15) => nb(15),
      mb(14) => nb(14),
      mb(13) => nb(13),
      mb(12) => nb(12),
      mb(11) => nb(11),
      mb(10) => nb(10),
      mb(9) => nb(9),
      mb(8) => nb(8),
      mb(7) => nb(7),
      mb(6) => nb(6),
      mb(5) => nb(5),
      mb(4) => nb(4),
      mb(3) => nb(3),
      mb(2) => nb(2),
      mb(1) => nb(1),
      mb(0) => nb(0),
      mc(15) => flag_data_we_0_Q,
      mc(14) => flag_data_we_0_Q,
      mc(13) => flag_data_we_0_Q,
      mc(12) => flag_data_we_0_Q,
      mc(11) => flag_data_we_0_Q,
      mc(10) => flag_data_we_0_Q,
      mc(9) => flag_data_we_0_Q,
      mc(8) => flag_data_we_0_Q,
      mc(7) => flag_data_we_0_Q,
      mc(6) => flag_data_we_0_Q,
      mc(5) => flag_data_we_0_Q,
      mc(4) => flag_data_we_0_Q,
      mc(3) => flag_data_we_0_Q,
      mc(2) => flag_data_we_0_Q,
      mc(1) => flag_data_we_0_Q,
      mc(0) => flag_data_we_0_Q,
      md(15) => flag_data_we_0_Q,
      md(14) => flag_data_we_0_Q,
      md(13) => flag_data_we_0_Q,
      md(12) => flag_data_we_0_Q,
      md(11) => flag_data_we_0_Q,
      md(10) => flag_data_we_0_Q,
      md(9) => flag_data_we_0_Q,
      md(8) => flag_data_we_0_Q,
      md(7) => flag_data_we_0_Q,
      md(6) => flag_data_we_0_Q,
      md(5) => flag_data_we_0_Q,
      md(4) => flag_data_we_0_Q,
      md(3) => flag_data_we_0_Q,
      md(2) => flag_data_we_0_Q,
      md(1) => flag_data_we_0_Q,
      md(0) => flag_data_we_0_Q,
      me(15) => flag_data_we_0_Q,
      me(14) => flag_data_we_0_Q,
      me(13) => flag_data_we_0_Q,
      me(12) => flag_data_we_0_Q,
      me(11) => flag_data_we_0_Q,
      me(10) => flag_data_we_0_Q,
      me(9) => flag_data_we_0_Q,
      me(8) => flag_data_we_0_Q,
      me(7) => flag_data_we_0_Q,
      me(6) => flag_data_we_0_Q,
      me(5) => flag_data_we_0_Q,
      me(4) => flag_data_we_0_Q,
      me(3) => flag_data_we_0_Q,
      me(2) => flag_data_we_0_Q,
      me(1) => flag_data_we_0_Q,
      me(0) => flag_data_we_0_Q,
      mf(15) => flag_data_we_0_Q,
      mf(14) => flag_data_we_0_Q,
      mf(13) => flag_data_we_0_Q,
      mf(12) => flag_data_we_0_Q,
      mf(11) => flag_data_we_0_Q,
      mf(10) => flag_data_we_0_Q,
      mf(9) => flag_data_we_0_Q,
      mf(8) => flag_data_we_0_Q,
      mf(7) => flag_data_we_0_Q,
      mf(6) => flag_data_we_0_Q,
      mf(5) => flag_data_we_0_Q,
      mf(4) => flag_data_we_0_Q,
      mf(3) => flag_data_we_0_Q,
      mf(2) => flag_data_we_0_Q,
      mf(1) => flag_data_we_0_Q,
      mf(0) => flag_data_we_0_Q,
      mg(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mg(8) => ng(8),
      mg(7) => ng(7),
      mg(6) => ng(6),
      mg(5) => ng(5),
      mg(4) => ng(4),
      mg(3) => ng(3),
      mg(2) => ng(2),
      mg(1) => ng(1),
      mg(0) => flag_data_we_0_Q,
      mh(15) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(14) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(12) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(11) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(10) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(9) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      mh(8) => nh(8),
      mh(7) => nh(7),
      mh(6) => nh(6),
      mh(5) => nh(5),
      mh(4) => nh(4),
      mh(3) => nh(3),
      mh(2) => nh(2),
      mh(1) => flag_data_we_0_Q,
      mh(0) => flag_data_we_0_Q,
      s(2) => adr2(5),
      s(1) => adr2(4),
      s(0) => adr2(3)
    );
  gen_data_cs_0_xstatus : ctrl_adsp_v2_decode_data_cs_1
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_0_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_0_xdata : ctrl_adsp_v2_decode_data_cs_2
    port map (
      clk => clk,
      reset => reset,
      data_cs => NlwRenamedSig_OI_trd_host_cmd_0_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_0_xcmd_data : ctrl_adsp_v2_decode_data_cs_3
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_0_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_0_xdata_we : ctrl_adsp_v2_decode_data_we_1
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_0_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_0_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_2
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(0),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_0_xcmd_data_we : ctrl_adsp_v2_decode_data_we_3
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => NlwRenamedSig_OI_trd_host_cmd_0_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_1_xstatus : ctrl_adsp_v2_decode_data_cs_4
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_1_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_1_xdata : ctrl_adsp_v2_decode_data_cs_5
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_1_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_1_xcmd_data : ctrl_adsp_v2_decode_data_cs_6
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_1_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_1_xdata_we : ctrl_adsp_v2_decode_data_we_4
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_1_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_1_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_5
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(1),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_1_xcmd_data_we : ctrl_adsp_v2_decode_data_we_6
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_1_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_2_xstatus : ctrl_adsp_v2_decode_data_cs_7
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_2_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_2_xdata : ctrl_adsp_v2_decode_data_cs_8
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_2_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_2_xcmd_data : ctrl_adsp_v2_decode_data_cs_9
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_2_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_2_xdata_we : ctrl_adsp_v2_decode_data_we_7
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_2_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_2_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_8
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(2),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_2_xcmd_data_we : ctrl_adsp_v2_decode_data_we_9
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_2_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_3_xstatus : ctrl_adsp_v2_decode_data_cs_10
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_3_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_3_xdata : ctrl_adsp_v2_decode_data_cs_11
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_3_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_3_xcmd_data : ctrl_adsp_v2_decode_data_cs_12
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_3_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_3_xdata_we : ctrl_adsp_v2_decode_data_we_10
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_3_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_3_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_11
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(3),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_3_xcmd_data_we : ctrl_adsp_v2_decode_data_we_12
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_3_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_4_xstatus : ctrl_adsp_v2_decode_data_cs_13
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_4_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_4_xdata : ctrl_adsp_v2_decode_data_cs_14
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_4_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_4_xcmd_data : ctrl_adsp_v2_decode_data_cs_15
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_4_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_4_xdata_we : ctrl_adsp_v2_decode_data_we_13
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_data_we(4),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_4_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_14
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(4),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_4_xcmd_data_we : ctrl_adsp_v2_decode_data_we_15
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_4_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_5_xstatus : ctrl_adsp_v2_decode_data_cs_16
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_5_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_5_xdata : ctrl_adsp_v2_decode_data_cs_17
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_5_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_5_xcmd_data : ctrl_adsp_v2_decode_data_cs_18
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_5_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_5_xdata_we : ctrl_adsp_v2_decode_data_we_16
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_5_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_5_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_17
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(5),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_5_xcmd_data_we : ctrl_adsp_v2_decode_data_we_18
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_5_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_6_xstatus : ctrl_adsp_v2_decode_data_cs_19
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_6_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_6_xdata : ctrl_adsp_v2_decode_data_cs_20
    port map (
      clk => clk,
      reset => reset,
      data_cs => NlwRenamedSig_OI_trd_host_cmd_6_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_6_xcmd_data : ctrl_adsp_v2_decode_data_cs_21
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_6_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_6_xdata_we : ctrl_adsp_v2_decode_data_we_19
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_6_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_6_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_20
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(6),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_6_xcmd_data_we : ctrl_adsp_v2_decode_data_we_21
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_6_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_7_xstatus : ctrl_adsp_v2_decode_data_cs_22
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_7_status_cs,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_7_xdata : ctrl_adsp_v2_decode_data_cs_23
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_7_data_oe,
      cmd_data_en => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      rd => rd2z_8535,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  gen_data_cs_7_xcmd_data : ctrl_adsp_v2_decode_data_cs_24
    port map (
      clk => clk,
      reset => reset,
      data_cs => trd_host_cmd_7_cmd_data_cs,
      cmd_data_en => sel_cmd_data,
      rd => rd1,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_7_xdata_we : ctrl_adsp_v2_decode_data_we_22
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_7_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_7_xcmd_adr_we : ctrl_adsp_v2_decode_data_we_23
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => bl_cmd_adr_we(7),
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  gen_data_cs_7_xcmd_data_we : ctrl_adsp_v2_decode_data_we_24
    port map (
      clk => clk,
      reset => reset,
      wr => wrl1,
      data_we => trd_host_cmd_7_cmd_data_we,
      adr(4) => adr1(5),
      adr(3) => adr1(4),
      adr(2) => adr1(3),
      adr(1) => adr1(2),
      adr(0) => adr1(1)
    );
  xcmd_ram : ctrl_adsp_v2_decode_ram_cs_1
    port map (
      clk => clk,
      reset => reset,
      data_cs => NLW_xcmd_ram_data_cs_UNCONNECTED,
      rd => rd2_8534,
      cmd_adr(9) => addra(9),
      cmd_adr(8) => addra(8),
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  xcmd_rom : ctrl_adsp_v2_decode_ram_cs_2
    port map (
      clk => clk,
      reset => reset,
      data_cs => NLW_xcmd_rom_data_cs_UNCONNECTED,
      rd => rd2_8534,
      cmd_adr(9) => addra(9),
      cmd_adr(8) => addra(8),
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  xcmd_adr : ctrl_adsp_v2_decode_cmd_adr_cs
    port map (
      clk => clk,
      reset => reset,
      data_cs => NLW_xcmd_adr_data_cs_UNCONNECTED,
      rd => rd2_8534,
      adr(4) => adr2(5),
      adr(3) => adr2(4),
      adr(2) => adr2(3),
      adr(1) => adr2(2),
      adr(0) => adr2(1)
    );
  trd4_host_data_9_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(9),
      I2 => trd4i_host_data(9),
      O => trd4_host_data(9)
    );
  trd4_host_data_8_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(8),
      I2 => trd4i_host_data(8),
      O => trd4_host_data(8)
    );
  trd4_host_data_7_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(7),
      I2 => trd4i_host_data(7),
      O => trd4_host_data(7)
    );
  trd4_host_data_6_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(6),
      I2 => trd4i_host_data(6),
      O => trd4_host_data(6)
    );
  trd4_host_data_63_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(63),
      I2 => NlwRenamedSig_OI_data2(31),
      O => trd4_host_data(63)
    );
  trd4_host_data_62_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(62),
      I2 => NlwRenamedSig_OI_data2(30),
      O => trd4_host_data(62)
    );
  trd4_host_data_61_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(61),
      I2 => NlwRenamedSig_OI_data2(29),
      O => trd4_host_data(61)
    );
  trd4_host_data_60_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(60),
      I2 => NlwRenamedSig_OI_data2(28),
      O => trd4_host_data(60)
    );
  trd4_host_data_5_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(5),
      I2 => trd4i_host_data(5),
      O => trd4_host_data(5)
    );
  trd4_host_data_59_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(59),
      I2 => NlwRenamedSig_OI_data2(27),
      O => trd4_host_data(59)
    );
  trd4_host_data_58_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(58),
      I2 => NlwRenamedSig_OI_data2(26),
      O => trd4_host_data(58)
    );
  trd4_host_data_57_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(57),
      I2 => NlwRenamedSig_OI_data2(25),
      O => trd4_host_data(57)
    );
  trd4_host_data_56_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(56),
      I2 => NlwRenamedSig_OI_data2(24),
      O => trd4_host_data(56)
    );
  trd4_host_data_55_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(55),
      I2 => NlwRenamedSig_OI_data2(23),
      O => trd4_host_data(55)
    );
  trd4_host_data_54_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(54),
      I2 => NlwRenamedSig_OI_data2(22),
      O => trd4_host_data(54)
    );
  trd4_host_data_53_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(53),
      I2 => NlwRenamedSig_OI_data2(21),
      O => trd4_host_data(53)
    );
  trd4_host_data_52_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(52),
      I2 => NlwRenamedSig_OI_data2(20),
      O => trd4_host_data(52)
    );
  trd4_host_data_51_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(51),
      I2 => NlwRenamedSig_OI_data2(19),
      O => trd4_host_data(51)
    );
  trd4_host_data_50_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(50),
      I2 => NlwRenamedSig_OI_data2(18),
      O => trd4_host_data(50)
    );
  trd4_host_data_4_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(4),
      I2 => trd4i_host_data(4),
      O => trd4_host_data(4)
    );
  trd4_host_data_49_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(49),
      I2 => NlwRenamedSig_OI_data2(17),
      O => trd4_host_data(49)
    );
  trd4_host_data_48_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(48),
      I2 => NlwRenamedSig_OI_data2(16),
      O => trd4_host_data(48)
    );
  trd4_host_data_47_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(47),
      I2 => NlwRenamedSig_OI_data2(15),
      O => trd4_host_data(47)
    );
  trd4_host_data_46_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(46),
      I2 => NlwRenamedSig_OI_data2(14),
      O => trd4_host_data(46)
    );
  trd4_host_data_45_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(45),
      I2 => NlwRenamedSig_OI_data2(13),
      O => trd4_host_data(45)
    );
  trd4_host_data_44_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(44),
      I2 => NlwRenamedSig_OI_data2(12),
      O => trd4_host_data(44)
    );
  trd4_host_data_43_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(43),
      I2 => NlwRenamedSig_OI_data2(11),
      O => trd4_host_data(43)
    );
  trd4_host_data_42_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(42),
      I2 => NlwRenamedSig_OI_data2(10),
      O => trd4_host_data(42)
    );
  trd4_host_data_41_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(41),
      I2 => NlwRenamedSig_OI_data2(9),
      O => trd4_host_data(41)
    );
  trd4_host_data_40_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(40),
      I2 => NlwRenamedSig_OI_data2(8),
      O => trd4_host_data(40)
    );
  trd4_host_data_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(3),
      I2 => trd4i_host_data(3),
      O => trd4_host_data(3)
    );
  trd4_host_data_39_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(39),
      I2 => NlwRenamedSig_OI_data2(7),
      O => trd4_host_data(39)
    );
  trd4_host_data_38_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(38),
      I2 => NlwRenamedSig_OI_data2(6),
      O => trd4_host_data(38)
    );
  trd4_host_data_37_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(37),
      I2 => NlwRenamedSig_OI_data2(5),
      O => trd4_host_data(37)
    );
  trd4_host_data_36_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(36),
      I2 => NlwRenamedSig_OI_data2(4),
      O => trd4_host_data(36)
    );
  trd4_host_data_35_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(35),
      I2 => NlwRenamedSig_OI_data2(3),
      O => trd4_host_data(35)
    );
  trd4_host_data_34_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(34),
      I2 => NlwRenamedSig_OI_data2(2),
      O => trd4_host_data(34)
    );
  trd4_host_data_33_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(33),
      I2 => NlwRenamedSig_OI_data2(1),
      O => trd4_host_data(33)
    );
  trd4_host_data_32_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(32),
      I2 => NlwRenamedSig_OI_data2(0),
      O => trd4_host_data(32)
    );
  trd4_host_data_31_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(31),
      I2 => trd4i_host_data(31),
      O => trd4_host_data(31)
    );
  trd4_host_data_30_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(30),
      I2 => trd4i_host_data(30),
      O => trd4_host_data(30)
    );
  trd4_host_data_2_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(2),
      I2 => trd4i_host_data(2),
      O => trd4_host_data(2)
    );
  trd4_host_data_29_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(29),
      I2 => trd4i_host_data(29),
      O => trd4_host_data(29)
    );
  trd4_host_data_28_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(28),
      I2 => trd4i_host_data(28),
      O => trd4_host_data(28)
    );
  trd4_host_data_27_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(27),
      I2 => trd4i_host_data(27),
      O => trd4_host_data(27)
    );
  trd4_host_data_26_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(26),
      I2 => trd4i_host_data(26),
      O => trd4_host_data(26)
    );
  trd4_host_data_25_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(25),
      I2 => trd4i_host_data(25),
      O => trd4_host_data(25)
    );
  trd4_host_data_24_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(24),
      I2 => trd4i_host_data(24),
      O => trd4_host_data(24)
    );
  trd4_host_data_23_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(23),
      I2 => trd4i_host_data(23),
      O => trd4_host_data(23)
    );
  trd4_host_data_22_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(22),
      I2 => trd4i_host_data(22),
      O => trd4_host_data(22)
    );
  trd4_host_data_21_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(21),
      I2 => trd4i_host_data(21),
      O => trd4_host_data(21)
    );
  trd4_host_data_20_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(20),
      I2 => trd4i_host_data(20),
      O => trd4_host_data(20)
    );
  trd4_host_data_1_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(1),
      I2 => trd4i_host_data(1),
      O => trd4_host_data(1)
    );
  trd4_host_data_19_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(19),
      I2 => trd4i_host_data(19),
      O => trd4_host_data(19)
    );
  trd4_host_data_18_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(18),
      I2 => trd4i_host_data(18),
      O => trd4_host_data(18)
    );
  trd4_host_data_17_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(17),
      I2 => trd4i_host_data(17),
      O => trd4_host_data(17)
    );
  trd4_host_data_16_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(16),
      I2 => trd4i_host_data(16),
      O => trd4_host_data(16)
    );
  trd4_host_data_15_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(15),
      I2 => trd4i_host_data(15),
      O => trd4_host_data(15)
    );
  trd4_host_data_14_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(14),
      I2 => trd4i_host_data(14),
      O => trd4_host_data(14)
    );
  trd4_host_data_13_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(13),
      I2 => trd4i_host_data(13),
      O => trd4_host_data(13)
    );
  trd4_host_data_12_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(12),
      I2 => trd4i_host_data(12),
      O => trd4_host_data(12)
    );
  trd4_host_data_11_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(11),
      I2 => trd4i_host_data(11),
      O => trd4_host_data(11)
    );
  trd4_host_data_10_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(10),
      I2 => trd4i_host_data(10),
      O => trd4_host_data(10)
    );
  trd4_host_data_0_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => main_mode2_4_8422,
      I1 => NlwRenamedSig_OI_data2(0),
      I2 => trd4i_host_data(0),
      O => trd4_host_data(0)
    );
  Q_mux00951 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 9),
      I2 => trd_data(6, 41),
      O => trd_repack_data_6_9_Q
    );
  Q_mux00941 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 8),
      I2 => trd_data(6, 40),
      O => trd_repack_data_6_8_Q
    );
  Q_mux00931 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 7),
      I2 => trd_data(6, 39),
      O => trd_repack_data_6_7_Q
    );
  Q_mux00921 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 6),
      I2 => trd_data(6, 38),
      O => trd_repack_data_6_6_Q
    );
  Q_mux00911 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 5),
      I2 => trd_data(6, 37),
      O => trd_repack_data_6_5_Q
    );
  Q_mux00901 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 4),
      I2 => trd_data(6, 36),
      O => trd_repack_data_6_4_Q
    );
  Q_mux00891 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 3),
      I2 => trd_data(6, 35),
      O => trd_repack_data_6_3_Q
    );
  Q_mux00881 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 2),
      I2 => trd_data(6, 34),
      O => trd_repack_data_6_2_Q
    );
  Q_mux00871 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 1),
      I2 => trd_data(6, 33),
      O => trd_repack_data_6_1_Q
    );
  Q_mux00861 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 0),
      I2 => trd_data(6, 32),
      O => trd_repack_data_6_0_Q
    );
  Q_mux00851 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 9),
      I2 => trd_data(0, 41),
      O => trd_repack_data_0_9_Q
    );
  Q_mux00841 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 8),
      I2 => trd_data(0, 40),
      O => trd_repack_data_0_8_Q
    );
  Q_mux00831 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 7),
      I2 => trd_data(0, 39),
      O => trd_repack_data_0_7_Q
    );
  Q_mux00821 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 6),
      I2 => trd_data(0, 38),
      O => trd_repack_data_0_6_Q
    );
  Q_mux00811 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 5),
      I2 => trd_data(0, 37),
      O => trd_repack_data_0_5_Q
    );
  Q_mux00801 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 4),
      I2 => trd_data(0, 36),
      O => trd_repack_data_0_4_Q
    );
  Q_mux00791 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 3),
      I2 => trd_data(0, 35),
      O => trd_repack_data_0_3_Q
    );
  Q_mux00781 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 2),
      I2 => trd_data(0, 34),
      O => trd_repack_data_0_2_Q
    );
  Q_mux00771 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 1),
      I2 => trd_data(0, 33),
      O => trd_repack_data_0_1_Q
    );
  Q_mux00761 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 0),
      I2 => trd_data(0, 32),
      O => trd_repack_data_0_0_Q
    );
  Q_mux00621 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 29),
      I2 => trd_data(6, 61),
      O => trd_repack_data_6_29_Q
    );
  Q_mux00591 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 28),
      I2 => trd_data(6, 60),
      O => trd_repack_data_6_28_Q
    );
  Q_mux00561 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 27),
      I2 => trd_data(6, 59),
      O => trd_repack_data_6_27_Q
    );
  Q_mux00541 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 26),
      I2 => trd_data(6, 58),
      O => trd_repack_data_6_26_Q
    );
  Q_mux00531 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 31),
      I2 => trd_data(6, 63),
      O => trd_repack_data_6_31_Q
    );
  Q_mux00501 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 25),
      I2 => trd_data(6, 57),
      O => trd_repack_data_6_25_Q
    );
  Q_mux00491 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 30),
      I2 => trd_data(6, 62),
      O => trd_repack_data_6_30_Q
    );
  Q_mux00461 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 24),
      I2 => trd_data(6, 56),
      O => trd_repack_data_6_24_Q
    );
  Q_mux00451 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 19),
      I2 => trd_data(6, 51),
      O => trd_repack_data_6_19_Q
    );
  Q_mux00421 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 23),
      I2 => trd_data(6, 55),
      O => trd_repack_data_6_23_Q
    );
  Q_mux00411 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 18),
      I2 => trd_data(6, 50),
      O => trd_repack_data_6_18_Q
    );
  Q_mux00381 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 22),
      I2 => trd_data(6, 54),
      O => trd_repack_data_6_22_Q
    );
  Q_mux00371 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 17),
      I2 => trd_data(6, 49),
      O => trd_repack_data_6_17_Q
    );
  Q_mux00351 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 21),
      I2 => trd_data(6, 53),
      O => trd_repack_data_6_21_Q
    );
  Q_mux00341 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 16),
      I2 => trd_data(6, 48),
      O => trd_repack_data_6_16_Q
    );
  Q_mux00321 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 20),
      I2 => trd_data(6, 52),
      O => trd_repack_data_6_20_Q
    );
  Q_mux00311 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 15),
      I2 => trd_data(6, 47),
      O => trd_repack_data_6_15_Q
    );
  Q_mux00291 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 14),
      I2 => trd_data(6, 46),
      O => trd_repack_data_6_14_Q
    );
  Q_mux00271 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 13),
      I2 => trd_data(6, 45),
      O => trd_repack_data_6_13_Q
    );
  Q_mux00251 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 12),
      I2 => trd_data(6, 44),
      O => trd_repack_data_6_12_Q
    );
  Q_mux00231 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 11),
      I2 => trd_data(6, 43),
      O => trd_repack_data_6_11_Q
    );
  Q_mux00221 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_6_Q,
      I1 => trd_data(6, 10),
      I2 => trd_data(6, 42),
      O => trd_repack_data_6_10_Q
    );
  Q_mux00211 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 29),
      I2 => trd_data(0, 61),
      O => trd_repack_data_0_29_Q
    );
  Q_mux00201 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 28),
      I2 => trd_data(0, 60),
      O => trd_repack_data_0_28_Q
    );
  Q_mux00191 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 27),
      I2 => trd_data(0, 59),
      O => trd_repack_data_0_27_Q
    );
  Q_mux00181 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 26),
      I2 => trd_data(0, 58),
      O => trd_repack_data_0_26_Q
    );
  Q_mux00171 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 31),
      I2 => trd_data(0, 63),
      O => trd_repack_data_0_31_Q
    );
  Q_mux00161 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 25),
      I2 => trd_data(0, 57),
      O => trd_repack_data_0_25_Q
    );
  Q_mux00151 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 30),
      I2 => trd_data(0, 62),
      O => trd_repack_data_0_30_Q
    );
  Q_mux00141 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 24),
      I2 => trd_data(0, 56),
      O => trd_repack_data_0_24_Q
    );
  Q_mux00131 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 19),
      I2 => trd_data(0, 51),
      O => trd_repack_data_0_19_Q
    );
  Q_mux00121 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 18),
      I2 => trd_data(0, 50),
      O => trd_repack_data_0_18_Q
    );
  Q_mux00111 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 23),
      I2 => trd_data(0, 55),
      O => trd_repack_data_0_23_Q
    );
  Q_mux00101 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 17),
      I2 => trd_data(0, 49),
      O => trd_repack_data_0_17_Q
    );
  Q_mux00091 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 22),
      I2 => trd_data(0, 54),
      O => trd_repack_data_0_22_Q
    );
  Q_mux00081 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 16),
      I2 => trd_data(0, 48),
      O => trd_repack_data_0_16_Q
    );
  Q_mux00071 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 21),
      I2 => trd_data(0, 53),
      O => trd_repack_data_0_21_Q
    );
  Q_mux00061 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 15),
      I2 => trd_data(0, 47),
      O => trd_repack_data_0_15_Q
    );
  Q_mux00051 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 20),
      I2 => trd_data(0, 52),
      O => trd_repack_data_0_20_Q
    );
  Q_mux00041 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 14),
      I2 => trd_data(0, 46),
      O => trd_repack_data_0_14_Q
    );
  Q_mux00031 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 13),
      I2 => trd_data(0, 45),
      O => trd_repack_data_0_13_Q
    );
  Q_mux00021 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 12),
      I2 => trd_data(0, 44),
      O => trd_repack_data_0_12_Q
    );
  Q_mux00011 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 11),
      I2 => trd_data(0, 43),
      O => trd_repack_data_0_11_Q
    );
  Q_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => flag_rd_repack_0_Q,
      I1 => trd_data(0, 10),
      I2 => trd_data(0, 42),
      O => trd_repack_data_0_10_Q
    );
  mux_sel_1_mux00011 : LUT3
    generic map(
      INIT => X"64"
    )
    port map (
      I0 => adr2(1),
      I1 => adr2(2),
      I2 => adr2(4),
      O => mux_sel_1_mux0001
    );
  mux_sel_0_mux00011 : LUT4
    generic map(
      INIT => X"E545"
    )
    port map (
      I0 => adr2(2),
      I1 => adr2(3),
      I2 => adr2(1),
      I3 => addra(9),
      O => mux_sel_0_mux0001
    );
  trd4i_host_data_10_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => flag_data_we_4_Q,
      I1 => bl_data_we(4),
      O => trd4i_host_data_10_and0000
    );
  adr1_2_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => test_mode,
      I1 => lc_adr(2),
      O => adr1(2)
    );
  flag_rd_repack_6_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => trd_reset_fifo(6),
      I1 => trd_drq_6_en,
      O => flag_rd_repack_6_or0000
    );
  flag_rd_repack_0_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => trd_reset_fifo(0),
      I1 => trd_drq_0_en,
      O => flag_rd_repack_0_or0000
    );
  Mrom_mux_sel_3_mux00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => adr2(1),
      I1 => adr2(2),
      O => Mrom_mux_sel_3_mux0001
    );
  dpram_en0_or00001 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => lc_wr,
      I1 => lc_adr(2),
      I2 => lc_adr(1),
      I3 => test_mode,
      O => dpram_en0_or0000
    );
  dpram_en_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => dpram_en0_8098,
      I1 => addra(9),
      I2 => addra(8),
      O => dpram_en
    );
  main_mode2_4_and0000_SW0 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => NlwRenamedSig_OI_cmd0_adr_4_Q,
      I1 => NlwRenamedSig_OI_cmd0_adr_2_Q,
      I2 => NlwRenamedSig_OI_cmd0_adr_0_Q,
      O => N0
    );
  main_mode2_4_and0000 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => NlwRenamedSig_OI_trd_host_cmd_0_cmd_data_we,
      I1 => NlwRenamedSig_OI_cmd0_adr_1_Q,
      I2 => NlwRenamedSig_OI_cmd0_adr_9_Q,
      I3 => NlwRenamedSig_OI_cmd0_adr_3_Q,
      I4 => NlwRenamedSig_OI_cmd0_adr_8_Q,
      I5 => N0,
      O => main_mode2_4_and0000_8423
    );
  trd_host_cmd_6_data_cs1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => NlwRenamedSig_OI_trd_host_cmd_6_data_oe,
      I1 => flag_rd_block_6_Q,
      O => trd_host_cmd_6_data_cs
    );
  trd_host_cmd_0_data_cs1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => NlwRenamedSig_OI_trd_host_cmd_0_data_oe,
      I1 => flag_rd_block_0_Q,
      O => trd_host_cmd_0_data_cs
    );
  adr1_1_1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => lc_adr(1),
      I1 => test_mode,
      O => adr1(1)
    );
  adr1_5_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => test_mode,
      I1 => lc_adr(5),
      O => adr1(5)
    );
  adr1_4_1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lc_adr(4),
      I1 => test_mode,
      O => adr1(4)
    );
  adr1_3_1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => lc_adr(3),
      I1 => test_mode,
      O => adr1(3)
    );
  dmar1_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => drq1_en,
      I1 => drq1_req,
      O => dmar1
    );
  dmar0_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => drq0_en,
      I1 => drq0_req,
      O => dmar0
    );
  Mmux_sel_cmd_data_2_f7 : MUXF7
    port map (
      I0 => Mmux_sel_cmd_data_4_7910,
      I1 => Mmux_sel_cmd_data_3_7909,
      S => adr1(5),
      O => sel_cmd_data
    );
  Mmux_addra_0_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_0_mux0001_4_7898,
      I1 => Mmux_addra_0_mux0001_3_7897,
      S => adr1(5),
      O => addra_0_mux0001
    );
  Mmux_addra_2_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_2_mux0001_4_7902,
      I1 => Mmux_addra_2_mux0001_3_7901,
      S => adr1(5),
      O => addra_2_mux0001
    );
  Mmux_addra_8_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_8_mux0001_4_7908,
      I1 => Mmux_addra_8_mux0001_3_7907,
      S => adr1(5),
      O => addra_8_mux0001
    );
  Mmux_addra_1_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_1_mux0001_4_7900,
      I1 => Mmux_addra_1_mux0001_3_7899,
      S => adr1(5),
      O => addra_1_mux0001
    );
  Mmux_addra_3_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_3_mux0001_4_7904,
      I1 => Mmux_addra_3_mux0001_3_7903,
      S => adr1(5),
      O => addra_3_mux0001
    );
  Mmux_addra_4_mux0001_2_f7 : MUXF7
    port map (
      I0 => Mmux_addra_4_mux0001_4_7906,
      I1 => Mmux_addra_4_mux0001_3_7905,
      S => adr1(5),
      O => addra_4_mux0001
    );
  flag_rd_repack_6_not00011_INV_0 : INV
    port map (
      I => flag_rd_repack_6_Q,
      O => flag_rd_repack_6_not0001
    );
  flag_rd_repack_0_not00011_INV_0 : INV
    port map (
      I => flag_rd_repack_0_Q,
      O => flag_rd_repack_0_not0001
    );
  flag_rd_block_6_not00011_INV_0 : INV
    port map (
      I => flag_rd_block_6_Q,
      O => flag_rd_block_6_not0001
    );
  flag_rd_block_0_not00011_INV_0 : INV
    port map (
      I => flag_rd_block_0_Q,
      O => flag_rd_block_0_not0001
    );
  bl_data_cs_6_inv1_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_trd_host_cmd_6_data_oe,
      O => bl_data_cs_6_inv
    );
  bl_data_cs_0_inv1_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_trd_host_cmd_0_data_oe,
      O => bl_data_cs_0_inv
    );
  wrl11_INV_0 : INV
    port map (
      I => lc_wr,
      O => wrl1
    );
  trd_reset_fifo_6_inv1_INV_0 : INV
    port map (
      I => trd_reset_fifo(6),
      O => trd_reset_fifo_6_inv
    );
  trd_reset_fifo_0_inv1_INV_0 : INV
    port map (
      I => trd_reset_fifo(0),
      O => trd_reset_fifo_0_inv
    );
  reset_inv821_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );
  main_mode2_4_inv1_INV_0 : INV
    port map (
      I => main_mode2_4_8422,
      O => main_mode2_4_inv
    );
  rd11_INV_0 : INV
    port map (
      I => lc_rd,
      O => rd1
    );
  rom : RAMB16
    generic map(
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"00000000000000CB000001000200495300010100004001000010010400080001",
      INIT_11 => X"0000000000000000000000000000000000000000000001090000000002005507",
      INIT_12 => X"000000000000000000000000000000000001000000000000000001030001004F",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"000000000000000000000000000000000001010D004004000010010200060013",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      DOA_REG => 0,
      DOB_REG => 0,
      READ_WIDTH_A => 18,
      WRITE_WIDTH_A => 18,
      WRITE_MODE_B => "WRITE_FIRST",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000010C01004004000020010300010012",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_B => X"000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      WRITE_MODE_A => "WRITE_FIRST",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      READ_WIDTH_B => 0,
      WRITE_WIDTH_B => 0,
      INIT_A => X"000000000",
      INVERT_CLK_DOA_REG => FALSE,
      INVERT_CLK_DOB_REG => FALSE,
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000"
    )
    port map (
      CASCADEINA => NLW_rom_CASCADEINA_UNCONNECTED,
      CASCADEINB => NLW_rom_CASCADEINB_UNCONNECTED,
      CLKA => clk,
      CLKB => NLW_rom_CLKB_UNCONNECTED,
      ENA => flag_data_we_0_Q,
      REGCEA => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      REGCEB => NLW_rom_REGCEB_UNCONNECTED,
      ENB => NLW_rom_ENB_UNCONNECTED,
      SSRA => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      SSRB => NLW_rom_SSRB_UNCONNECTED,
      CASCADEOUTA => NLW_rom_CASCADEOUTA_UNCONNECTED,
      CASCADEOUTB => NLW_rom_CASCADEOUTB_UNCONNECTED,
      ADDRA(14) => NLW_rom_ADDRA_14_UNCONNECTED,
      ADDRA(13) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      ADDRA(12) => addra(8),
      ADDRA(11) => addra(7),
      ADDRA(10) => addra(6),
      ADDRA(9) => addra(5),
      ADDRA(8) => addra(4),
      ADDRA(7) => addra(3),
      ADDRA(6) => addra(2),
      ADDRA(5) => addra(1),
      ADDRA(4) => addra(0),
      ADDRA(3) => NLW_rom_ADDRA_3_UNCONNECTED,
      ADDRA(2) => NLW_rom_ADDRA_2_UNCONNECTED,
      ADDRA(1) => NLW_rom_ADDRA_1_UNCONNECTED,
      ADDRA(0) => NLW_rom_ADDRA_0_UNCONNECTED,
      ADDRB(14) => NLW_rom_ADDRB_14_UNCONNECTED,
      ADDRB(13) => NLW_rom_ADDRB_13_UNCONNECTED,
      ADDRB(12) => NLW_rom_ADDRB_12_UNCONNECTED,
      ADDRB(11) => NLW_rom_ADDRB_11_UNCONNECTED,
      ADDRB(10) => NLW_rom_ADDRB_10_UNCONNECTED,
      ADDRB(9) => NLW_rom_ADDRB_9_UNCONNECTED,
      ADDRB(8) => NLW_rom_ADDRB_8_UNCONNECTED,
      ADDRB(7) => NLW_rom_ADDRB_7_UNCONNECTED,
      ADDRB(6) => NLW_rom_ADDRB_6_UNCONNECTED,
      ADDRB(5) => NLW_rom_ADDRB_5_UNCONNECTED,
      ADDRB(4) => NLW_rom_ADDRB_4_UNCONNECTED,
      ADDRB(3) => NLW_rom_ADDRB_3_UNCONNECTED,
      ADDRB(2) => NLW_rom_ADDRB_2_UNCONNECTED,
      ADDRB(1) => NLW_rom_ADDRB_1_UNCONNECTED,
      ADDRB(0) => NLW_rom_ADDRB_0_UNCONNECTED,
      DIA(31) => NLW_rom_DIA_31_UNCONNECTED,
      DIA(30) => NLW_rom_DIA_30_UNCONNECTED,
      DIA(29) => NLW_rom_DIA_29_UNCONNECTED,
      DIA(28) => NLW_rom_DIA_28_UNCONNECTED,
      DIA(27) => NLW_rom_DIA_27_UNCONNECTED,
      DIA(26) => NLW_rom_DIA_26_UNCONNECTED,
      DIA(25) => NLW_rom_DIA_25_UNCONNECTED,
      DIA(24) => NLW_rom_DIA_24_UNCONNECTED,
      DIA(23) => NLW_rom_DIA_23_UNCONNECTED,
      DIA(22) => NLW_rom_DIA_22_UNCONNECTED,
      DIA(21) => NLW_rom_DIA_21_UNCONNECTED,
      DIA(20) => NLW_rom_DIA_20_UNCONNECTED,
      DIA(19) => NLW_rom_DIA_19_UNCONNECTED,
      DIA(18) => NLW_rom_DIA_18_UNCONNECTED,
      DIA(17) => NLW_rom_DIA_17_UNCONNECTED,
      DIA(16) => NLW_rom_DIA_16_UNCONNECTED,
      DIA(15) => NlwRenamedSig_OI_data2(15),
      DIA(14) => NlwRenamedSig_OI_data2(14),
      DIA(13) => NlwRenamedSig_OI_data2(13),
      DIA(12) => NlwRenamedSig_OI_data2(12),
      DIA(11) => NlwRenamedSig_OI_data2(11),
      DIA(10) => NlwRenamedSig_OI_data2(10),
      DIA(9) => NlwRenamedSig_OI_data2(9),
      DIA(8) => NlwRenamedSig_OI_data2(8),
      DIA(7) => NlwRenamedSig_OI_data2(7),
      DIA(6) => NlwRenamedSig_OI_data2(6),
      DIA(5) => NlwRenamedSig_OI_data2(5),
      DIA(4) => NlwRenamedSig_OI_data2(4),
      DIA(3) => NlwRenamedSig_OI_data2(3),
      DIA(2) => NlwRenamedSig_OI_data2(2),
      DIA(1) => NlwRenamedSig_OI_data2(1),
      DIA(0) => NlwRenamedSig_OI_data2(0),
      DIB(31) => NLW_rom_DIB_31_UNCONNECTED,
      DIB(30) => NLW_rom_DIB_30_UNCONNECTED,
      DIB(29) => NLW_rom_DIB_29_UNCONNECTED,
      DIB(28) => NLW_rom_DIB_28_UNCONNECTED,
      DIB(27) => NLW_rom_DIB_27_UNCONNECTED,
      DIB(26) => NLW_rom_DIB_26_UNCONNECTED,
      DIB(25) => NLW_rom_DIB_25_UNCONNECTED,
      DIB(24) => NLW_rom_DIB_24_UNCONNECTED,
      DIB(23) => NLW_rom_DIB_23_UNCONNECTED,
      DIB(22) => NLW_rom_DIB_22_UNCONNECTED,
      DIB(21) => NLW_rom_DIB_21_UNCONNECTED,
      DIB(20) => NLW_rom_DIB_20_UNCONNECTED,
      DIB(19) => NLW_rom_DIB_19_UNCONNECTED,
      DIB(18) => NLW_rom_DIB_18_UNCONNECTED,
      DIB(17) => NLW_rom_DIB_17_UNCONNECTED,
      DIB(16) => NLW_rom_DIB_16_UNCONNECTED,
      DIB(15) => NLW_rom_DIB_15_UNCONNECTED,
      DIB(14) => NLW_rom_DIB_14_UNCONNECTED,
      DIB(13) => NLW_rom_DIB_13_UNCONNECTED,
      DIB(12) => NLW_rom_DIB_12_UNCONNECTED,
      DIB(11) => NLW_rom_DIB_11_UNCONNECTED,
      DIB(10) => NLW_rom_DIB_10_UNCONNECTED,
      DIB(9) => NLW_rom_DIB_9_UNCONNECTED,
      DIB(8) => NLW_rom_DIB_8_UNCONNECTED,
      DIB(7) => NLW_rom_DIB_7_UNCONNECTED,
      DIB(6) => NLW_rom_DIB_6_UNCONNECTED,
      DIB(5) => NLW_rom_DIB_5_UNCONNECTED,
      DIB(4) => NLW_rom_DIB_4_UNCONNECTED,
      DIB(3) => NLW_rom_DIB_3_UNCONNECTED,
      DIB(2) => NLW_rom_DIB_2_UNCONNECTED,
      DIB(1) => NLW_rom_DIB_1_UNCONNECTED,
      DIB(0) => NLW_rom_DIB_0_UNCONNECTED,
      DIPA(3) => NLW_rom_DIPA_3_UNCONNECTED,
      DIPA(2) => NLW_rom_DIPA_2_UNCONNECTED,
      DIPA(1) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      DIPA(0) => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      DIPB(3) => NLW_rom_DIPB_3_UNCONNECTED,
      DIPB(2) => NLW_rom_DIPB_2_UNCONNECTED,
      DIPB(1) => NLW_rom_DIPB_1_UNCONNECTED,
      DIPB(0) => NLW_rom_DIPB_0_UNCONNECTED,
      WEA(3) => dpram_en,
      WEA(2) => dpram_en,
      WEA(1) => dpram_en,
      WEA(0) => dpram_en,
      WEB(3) => NLW_rom_WEB_3_UNCONNECTED,
      WEB(2) => NLW_rom_WEB_2_UNCONNECTED,
      WEB(1) => NLW_rom_WEB_1_UNCONNECTED,
      WEB(0) => NLW_rom_WEB_0_UNCONNECTED,
      DOA(31) => NLW_rom_DOA_31_UNCONNECTED,
      DOA(30) => NLW_rom_DOA_30_UNCONNECTED,
      DOA(29) => NLW_rom_DOA_29_UNCONNECTED,
      DOA(28) => NLW_rom_DOA_28_UNCONNECTED,
      DOA(27) => NLW_rom_DOA_27_UNCONNECTED,
      DOA(26) => NLW_rom_DOA_26_UNCONNECTED,
      DOA(25) => NLW_rom_DOA_25_UNCONNECTED,
      DOA(24) => NLW_rom_DOA_24_UNCONNECTED,
      DOA(23) => NLW_rom_DOA_23_UNCONNECTED,
      DOA(22) => NLW_rom_DOA_22_UNCONNECTED,
      DOA(21) => NLW_rom_DOA_21_UNCONNECTED,
      DOA(20) => NLW_rom_DOA_20_UNCONNECTED,
      DOA(19) => NLW_rom_DOA_19_UNCONNECTED,
      DOA(18) => NLW_rom_DOA_18_UNCONNECTED,
      DOA(17) => NLW_rom_DOA_17_UNCONNECTED,
      DOA(16) => NLW_rom_DOA_16_UNCONNECTED,
      DOA(15) => rom_data2(15),
      DOA(14) => rom_data2(14),
      DOA(13) => rom_data2(13),
      DOA(12) => rom_data2(12),
      DOA(11) => rom_data2(11),
      DOA(10) => rom_data2(10),
      DOA(9) => rom_data2(9),
      DOA(8) => rom_data2(8),
      DOA(7) => rom_data2(7),
      DOA(6) => rom_data2(6),
      DOA(5) => rom_data2(5),
      DOA(4) => rom_data2(4),
      DOA(3) => rom_data2(3),
      DOA(2) => rom_data2(2),
      DOA(1) => rom_data2(1),
      DOA(0) => rom_data2(0),
      DOB(31) => NLW_rom_DOB_31_UNCONNECTED,
      DOB(30) => NLW_rom_DOB_30_UNCONNECTED,
      DOB(29) => NLW_rom_DOB_29_UNCONNECTED,
      DOB(28) => NLW_rom_DOB_28_UNCONNECTED,
      DOB(27) => NLW_rom_DOB_27_UNCONNECTED,
      DOB(26) => NLW_rom_DOB_26_UNCONNECTED,
      DOB(25) => NLW_rom_DOB_25_UNCONNECTED,
      DOB(24) => NLW_rom_DOB_24_UNCONNECTED,
      DOB(23) => NLW_rom_DOB_23_UNCONNECTED,
      DOB(22) => NLW_rom_DOB_22_UNCONNECTED,
      DOB(21) => NLW_rom_DOB_21_UNCONNECTED,
      DOB(20) => NLW_rom_DOB_20_UNCONNECTED,
      DOB(19) => NLW_rom_DOB_19_UNCONNECTED,
      DOB(18) => NLW_rom_DOB_18_UNCONNECTED,
      DOB(17) => NLW_rom_DOB_17_UNCONNECTED,
      DOB(16) => NLW_rom_DOB_16_UNCONNECTED,
      DOB(15) => NLW_rom_DOB_15_UNCONNECTED,
      DOB(14) => NLW_rom_DOB_14_UNCONNECTED,
      DOB(13) => NLW_rom_DOB_13_UNCONNECTED,
      DOB(12) => NLW_rom_DOB_12_UNCONNECTED,
      DOB(11) => NLW_rom_DOB_11_UNCONNECTED,
      DOB(10) => NLW_rom_DOB_10_UNCONNECTED,
      DOB(9) => NLW_rom_DOB_9_UNCONNECTED,
      DOB(8) => NLW_rom_DOB_8_UNCONNECTED,
      DOB(7) => NLW_rom_DOB_7_UNCONNECTED,
      DOB(6) => NLW_rom_DOB_6_UNCONNECTED,
      DOB(5) => NLW_rom_DOB_5_UNCONNECTED,
      DOB(4) => NLW_rom_DOB_4_UNCONNECTED,
      DOB(3) => NLW_rom_DOB_3_UNCONNECTED,
      DOB(2) => NLW_rom_DOB_2_UNCONNECTED,
      DOB(1) => NLW_rom_DOB_1_UNCONNECTED,
      DOB(0) => NLW_rom_DOB_0_UNCONNECTED,
      DOPA(3) => NLW_rom_DOPA_3_UNCONNECTED,
      DOPA(2) => NLW_rom_DOPA_2_UNCONNECTED,
      DOPA(1) => NLW_rom_DOPA_1_UNCONNECTED,
      DOPA(0) => NLW_rom_DOPA_0_UNCONNECTED,
      DOPB(3) => NLW_rom_DOPB_3_UNCONNECTED,
      DOPB(2) => NLW_rom_DOPB_2_UNCONNECTED,
      DOPB(1) => NLW_rom_DOPB_1_UNCONNECTED,
      DOPB(0) => NLW_rom_DOPB_0_UNCONNECTED
    );
  Mshreg_mac_0 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(0),
      Q => Mshreg_mac_0_7912,
      Q15 => NLW_Mshreg_mac_0_Q15_UNCONNECTED
    );
  mac_0 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_0_7912,
      Q => mac_0_Q
    );
  Mshreg_mac_1 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(1),
      Q => Mshreg_mac_1_7913,
      Q15 => NLW_Mshreg_mac_1_Q15_UNCONNECTED
    );
  mac_1 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_1_7913,
      Q => mac_1_Q
    );
  Mshreg_mac_2 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(2),
      Q => Mshreg_mac_2_7914,
      Q15 => NLW_Mshreg_mac_2_Q15_UNCONNECTED
    );
  mac_2 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_2_7914,
      Q => mac_2_Q
    );
  Mshreg_mac_3 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(3),
      Q => Mshreg_mac_3_7915,
      Q15 => NLW_Mshreg_mac_3_Q15_UNCONNECTED
    );
  mac_3 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_3_7915,
      Q => mac_3_Q
    );
  Mshreg_mac_9 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(9),
      Q => Mshreg_mac_9_7918,
      Q15 => NLW_Mshreg_mac_9_Q15_UNCONNECTED
    );
  mac_9 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_9_7918,
      Q => mac_9_Q
    );
  Mshreg_mac_4 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(4),
      Q => Mshreg_mac_4_7916,
      Q15 => NLW_Mshreg_mac_4_Q15_UNCONNECTED
    );
  mac_4 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_4_7916,
      Q => mac_4_Q
    );
  Mshreg_mac_8 : SRLC16E
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A1 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A2 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      A3 => NlwRenamedSig_OI_trd_host_cmd_15_adr_0_Q,
      CE => flag_data_we_0_Q,
      CLK => clk,
      D => addra(8),
      Q => Mshreg_mac_8_7917,
      Q15 => NLW_Mshreg_mac_8_Q15_UNCONNECTED
    );
  mac_8 : FDE
    port map (
      C => clk,
      CE => flag_data_we_0_Q,
      D => Mshreg_mac_8_7917,
      Q => mac_8_Q
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_blink is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    led_h1 : out STD_LOGIC; 
    pcie_link_up : in STD_LOGIC := 'X'; 
    clk30k : in STD_LOGIC := 'X'; 
    pcie_lstatus : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end ctrl_blink;

architecture STRUCTURE of ctrl_blink is
  signal N01 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal clk_blink : STD_LOGIC; 
  signal clk_z1_7381 : STD_LOGIC; 
  signal clk_z2_7382 : STD_LOGIC; 
  signal cnt_and0000 : STD_LOGIC; 
  signal cnt_and0001 : STD_LOGIC; 
  signal mask_7404 : STD_LOGIC; 
  signal mask_mux0000 : STD_LOGIC; 
  signal mask_not0001_7406 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal stp_7427 : STD_LOGIC; 
  signal stp_mux0000 : STD_LOGIC; 
  signal stp_not0001 : STD_LOGIC; 
  signal Result : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal cnt30k : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal ncnt30k : STD_LOGIC_VECTOR ( 13 downto 0 ); 
begin
  stp : FDRE
    port map (
      C => clk,
      CE => stp_not0001,
      D => stp_mux0000,
      R => reset_inv,
      Q => stp_7427
    );
  clk_z1 : FD
    port map (
      C => clk,
      D => clk_blink,
      Q => clk_z1_7381
    );
  cnt30k_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => clk30k,
      D => ncnt30k(0),
      Q => cnt30k(0)
    );
  mask : FDRE
    port map (
      C => clk,
      CE => mask_not0001_7406,
      D => mask_mux0000,
      R => reset_inv,
      Q => mask_7404
    );
  clk_z2 : FD
    port map (
      C => clk,
      D => clk_z1_7381,
      Q => clk_z2_7382
    );
  gen_30k_1_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(0),
      D => ncnt30k(1),
      Q => cnt30k(1)
    );
  gen_30k_2_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(1),
      D => ncnt30k(2),
      Q => cnt30k(2)
    );
  gen_30k_3_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(2),
      D => ncnt30k(3),
      Q => cnt30k(3)
    );
  gen_30k_4_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(3),
      D => ncnt30k(4),
      Q => cnt30k(4)
    );
  gen_30k_5_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(4),
      D => ncnt30k(5),
      Q => cnt30k(5)
    );
  gen_30k_6_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(5),
      D => ncnt30k(6),
      Q => cnt30k(6)
    );
  gen_30k_7_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(6),
      D => ncnt30k(7),
      Q => cnt30k(7)
    );
  gen_30k_8_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(7),
      D => ncnt30k(8),
      Q => cnt30k(8)
    );
  gen_30k_9_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(8),
      D => ncnt30k(9),
      Q => cnt30k(9)
    );
  gen_30k_10_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(9),
      D => ncnt30k(10),
      Q => cnt30k(10)
    );
  gen_30k_11_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(10),
      D => ncnt30k(11),
      Q => cnt30k(11)
    );
  gen_30k_12_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(11),
      D => ncnt30k(12),
      Q => cnt30k(12)
    );
  gen_30k_13_fd30k : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => cnt30k(12),
      D => ncnt30k(13),
      Q => cnt30k(13)
    );
  cnt_0 : FDRE
    port map (
      C => clk,
      CE => cnt_and0001,
      D => Result(0),
      R => cnt_and0000,
      Q => cnt(0)
    );
  cnt_1 : FDRE
    port map (
      C => clk,
      CE => cnt_and0001,
      D => Result(1),
      R => cnt_and0000,
      Q => cnt(1)
    );
  cnt_2 : FDRE
    port map (
      C => clk,
      CE => cnt_and0001,
      D => Result(2),
      R => cnt_and0000,
      Q => cnt(2)
    );
  cnt_3 : FDRE
    port map (
      C => clk,
      CE => cnt_and0001,
      D => Result(3),
      R => cnt_and0000,
      Q => cnt(3)
    );
  Mcount_cnt_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => cnt(1),
      I1 => cnt(0),
      O => Result(1)
    );
  Mcount_cnt_xor_2_11 : LUT3
    generic map(
      INIT => X"6C"
    )
    port map (
      I0 => cnt(0),
      I1 => cnt(2),
      I2 => cnt(1),
      O => Result(2)
    );
  Mcount_cnt_xor_3_11 : LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      I0 => cnt(0),
      I1 => cnt(3),
      I2 => cnt(1),
      I3 => cnt(2),
      O => Result(3)
    );
  mask_mux00001 : LUT5
    generic map(
      INIT => X"CCCCCCC8"
    )
    port map (
      I0 => cnt(0),
      I1 => stp_7427,
      I2 => cnt(1),
      I3 => cnt(2),
      I4 => cnt(3),
      O => mask_mux0000
    );
  cnt_and000011 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => clk_z2_7382,
      I1 => clk_z1_7381,
      O => cnt_and0001
    );
  mask_not0001_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFF6F6CF6F4"
    )
    port map (
      I0 => pcie_lstatus(5),
      I1 => cnt(1),
      I2 => cnt(0),
      I3 => cnt(3),
      I4 => pcie_lstatus(4),
      I5 => cnt(2),
      O => N01
    );
  mask_not0001_SW1 : LUT6
    generic map(
      INIT => X"8081202108090203"
    )
    port map (
      I0 => cnt(2),
      I1 => cnt(0),
      I2 => cnt(1),
      I3 => cnt(3),
      I4 => pcie_lstatus(4),
      I5 => pcie_lstatus(5),
      O => N11
    );
  clk_blink1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => stp_7427,
      I1 => cnt30k(12),
      I2 => cnt30k(13),
      O => clk_blink
    );
  cnt_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => clk_z1_7381,
      I1 => stp_7427,
      I2 => clk_z2_7382,
      O => cnt_and0000
    );
  stp_not00011 : LUT4
    generic map(
      INIT => X"0090"
    )
    port map (
      I0 => pcie_link_up,
      I1 => stp_7427,
      I2 => clk_z1_7381,
      I3 => clk_z2_7382,
      O => stp_not0001
    );
  mask_not0001 : LUT6
    generic map(
      INIT => X"4404040444440444"
    )
    port map (
      I0 => clk_z2_7382,
      I1 => clk_z1_7381,
      I2 => stp_7427,
      I3 => pcie_lstatus(6),
      I4 => N11,
      I5 => N01,
      O => mask_not0001_7406
    );
  led_h11 : LUT5
    generic map(
      INIT => X"AAAAA280"
    )
    port map (
      I0 => reset,
      I1 => stp_7427,
      I2 => cnt30k(13),
      I3 => cnt30k(12),
      I4 => mask_7404,
      O => led_h1
    );
  stp_mux00001_INV_0 : INV
    port map (
      I => stp_7427,
      O => stp_mux0000
    );
  ncnt30k_9_1_INV_0 : INV
    port map (
      I => cnt30k(9),
      O => ncnt30k(9)
    );
  ncnt30k_8_1_INV_0 : INV
    port map (
      I => cnt30k(8),
      O => ncnt30k(8)
    );
  ncnt30k_7_1_INV_0 : INV
    port map (
      I => cnt30k(7),
      O => ncnt30k(7)
    );
  ncnt30k_6_1_INV_0 : INV
    port map (
      I => cnt30k(6),
      O => ncnt30k(6)
    );
  ncnt30k_5_1_INV_0 : INV
    port map (
      I => cnt30k(5),
      O => ncnt30k(5)
    );
  ncnt30k_4_1_INV_0 : INV
    port map (
      I => cnt30k(4),
      O => ncnt30k(4)
    );
  ncnt30k_3_1_INV_0 : INV
    port map (
      I => cnt30k(3),
      O => ncnt30k(3)
    );
  ncnt30k_2_1_INV_0 : INV
    port map (
      I => cnt30k(2),
      O => ncnt30k(2)
    );
  ncnt30k_1_1_INV_0 : INV
    port map (
      I => cnt30k(1),
      O => ncnt30k(1)
    );
  ncnt30k_13_1_INV_0 : INV
    port map (
      I => cnt30k(13),
      O => ncnt30k(13)
    );
  ncnt30k_12_1_INV_0 : INV
    port map (
      I => cnt30k(12),
      O => ncnt30k(12)
    );
  ncnt30k_11_1_INV_0 : INV
    port map (
      I => cnt30k(11),
      O => ncnt30k(11)
    );
  ncnt30k_10_1_INV_0 : INV
    port map (
      I => cnt30k(10),
      O => ncnt30k(10)
    );
  ncnt30k_0_1_INV_0 : INV
    port map (
      I => cnt30k(0),
      O => ncnt30k(0)
    );
  Mcount_cnt_xor_0_11_INV_0 : INV
    port map (
      I => cnt(0),
      O => Result(0)
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_ambpex5_m5 is
  port (
    trd_host_cmd_11_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_13_data_oe : out STD_LOGIC; 
    trd_host_cmd_6_cmd_data_cs : out STD_LOGIC; 
    trd_drq_14_req : in STD_LOGIC := 'X'; 
    trd_drq_14_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_2_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_9_data_cs : out STD_LOGIC; 
    trd_host_cmd_12_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_15_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_2_data_we : out STD_LOGIC; 
    trd_drq_15_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_cs : out STD_LOGIC; 
    trd_host_cmd_1_data_oe : out STD_LOGIC; 
    trd_main_drq_0_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_3_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_2_status_cs : out STD_LOGIC; 
    trd_host_cmd_13_data_we : out STD_LOGIC; 
    trd_host_cmd_11_data_cs : out STD_LOGIC; 
    trd_main_drq_1_ack : in STD_LOGIC := 'X'; 
    trd_drq_3_en : in STD_LOGIC := 'X'; 
    trd_drq_0_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_data_oe : out STD_LOGIC; 
    trd_host_cmd_9_cmd_data_we : out STD_LOGIC; 
    trd_main_drq_8_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_8_status_cs : out STD_LOGIC; 
    trd_host_cmd_11_status_cs : out STD_LOGIC; 
    trd_main_drq_2_ack : in STD_LOGIC := 'X'; 
    trd_drq_8_en : in STD_LOGIC := 'X'; 
    trd_drq_1_ack : in STD_LOGIC := 'X'; 
    clk_out : out STD_LOGIC; 
    trd_host_cmd_8_data_cs : out STD_LOGIC; 
    trd_host_cmd_9_data_oe : out STD_LOGIC; 
    trd_host_cmd_4_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_1_data_we : out STD_LOGIC; 
    clk5_pll : out STD_LOGIC; 
    trd_main_drq_3_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_11_en : in STD_LOGIC := 'X'; 
    trd_drq_2_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_oe : out STD_LOGIC; 
    trd_host_cmd_15_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_14_cmd_adr_we : out STD_LOGIC; 
    trd_main_drq_4_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_0_req : in STD_LOGIC := 'X'; 
    trd_drq_3_ack : in STD_LOGIC := 'X'; 
    trd_drq_11_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_12_data_we : out STD_LOGIC; 
    trd_host_cmd_10_data_cs : out STD_LOGIC; 
    trd_host_cmd_11_data_oe : out STD_LOGIC; 
    trd_host_cmd_6_cmd_data_we : out STD_LOGIC; 
    reset_out : out STD_LOGIC; 
    trd_main_drq_1_req : in STD_LOGIC := 'X'; 
    trd_main_drq_5_ack : in STD_LOGIC := 'X'; 
    trd_drq_4_ack : in STD_LOGIC := 'X'; 
    trd_drq_0_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_data_we : out STD_LOGIC; 
    trd_host_cmd_3_status_cs : out STD_LOGIC; 
    trd_main_drq_0_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_7_data_cs : out STD_LOGIC; 
    clk_lock_out : out STD_LOGIC; 
    trd_host_cmd_12_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_8_data_oe : out STD_LOGIC; 
    trd_main_drq_2_req : in STD_LOGIC := 'X'; 
    trd_main_drq_6_ack : in STD_LOGIC := 'X'; 
    trd_drq_5_ack : in STD_LOGIC := 'X'; 
    trd_drq_1_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_data_we : out STD_LOGIC; 
    trd_host_cmd_7_cmd_data_cs : out STD_LOGIC; 
    trd_drq_0_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_status_cs : out STD_LOGIC; 
    trd_main_drq_5_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_cmd_adr_we : out STD_LOGIC; 
    trd_main_drq_3_req : in STD_LOGIC := 'X'; 
    trd_main_drq_7_ack : in STD_LOGIC := 'X'; 
    trd_drq_6_ack : in STD_LOGIC := 'X'; 
    trd_drq_2_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_status_cs : out STD_LOGIC; 
    trd_host_cmd_3_cmd_data_we : out STD_LOGIC; 
    trd_drq_5_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_11_data_we : out STD_LOGIC; 
    trd_host_cmd_13_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_10_data_oe : out STD_LOGIC; 
    trd_main_drq_8_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_4_req : in STD_LOGIC := 'X'; 
    trd_drq_7_ack : in STD_LOGIC := 'X'; 
    trd_drq_3_req : in STD_LOGIC := 'X'; 
    clk2_pll : out STD_LOGIC; 
    trd_host_cmd_13_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_9_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_5_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_8_data_we : out STD_LOGIC; 
    trd_drq_4_req : in STD_LOGIC := 'X'; 
    trd_drq_8_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_6_data_cs : out STD_LOGIC; 
    trd_host_cmd_7_data_oe : out STD_LOGIC; 
    trd_main_drq_13_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_4_cmd_data_cs : out STD_LOGIC; 
    led_h1 : out STD_LOGIC; 
    led_h2 : out STD_LOGIC; 
    trd_main_drq_6_req : in STD_LOGIC := 'X'; 
    led_h3 : out STD_LOGIC; 
    trd_drq_5_req : in STD_LOGIC := 'X'; 
    trd_drq_9_ack : in STD_LOGIC := 'X'; 
    led_h4 : out STD_LOGIC; 
    trd_drq_13_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_4_status_cs : out STD_LOGIC; 
    trd_host_cmd_10_data_we : out STD_LOGIC; 
    trd_main_drq_7_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_cmd_adr_we : out STD_LOGIC; 
    trd_drq_6_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_2_cmd_adr_we : out STD_LOGIC; 
    bperst : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_10_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_8_req : in STD_LOGIC := 'X'; 
    trd_drq_7_req : in STD_LOGIC := 'X'; 
    trd_main_drq_2_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_13_status_cs : out STD_LOGIC; 
    trd_host_cmd_7_data_we : out STD_LOGIC; 
    trd_host_cmd_5_data_cs : out STD_LOGIC; 
    trd_host_cmd_6_data_oe : out STD_LOGIC; 
    trd_drq_2_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_7_cmd_data_we : out STD_LOGIC; 
    trd_main_drq_9_req : in STD_LOGIC := 'X'; 
    trd_drq_8_req : in STD_LOGIC := 'X'; 
    trd_main_drq_7_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_cmd_data_cs : out STD_LOGIC; 
    clk30k : out STD_LOGIC; 
    trd_drq_7_en : in STD_LOGIC := 'X'; 
    trd_drq_9_req : in STD_LOGIC := 'X'; 
    clk200_out : out STD_LOGIC; 
    clk4_pll : out STD_LOGIC; 
    trd_main_drq_10_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_13_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_8_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_1_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_8_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_15_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_6_data_we : out STD_LOGIC; 
    trd_drq_10_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_4_data_cs : out STD_LOGIC; 
    trd_host_cmd_5_status_cs : out STD_LOGIC; 
    trd_host_cmd_5_data_oe : out STD_LOGIC; 
    trd_host_cmd_4_cmd_data_we : out STD_LOGIC; 
    trd_drq_15_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_11_cmd_adr_we : out STD_LOGIC; 
    trd_main_drq_10_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_data_cs : out STD_LOGIC; 
    trd_host_cmd_14_status_cs : out STD_LOGIC; 
    trd_host_cmd_14_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_11_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_10_cmd_data_we : out STD_LOGIC; 
    trd_main_drq_4_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_12_ack : in STD_LOGIC := 'X'; 
    trd_drq_4_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_data_we : out STD_LOGIC; 
    trd_host_cmd_7_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_3_data_cs : out STD_LOGIC; 
    trd_host_cmd_0_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_4_data_oe : out STD_LOGIC; 
    trd_main_drq_9_en : in STD_LOGIC := 'X'; 
    test_mode : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_cmd_data_we : out STD_LOGIC; 
    trd_main_drq_13_ack : in STD_LOGIC := 'X'; 
    trd_drq_9_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_0_status_cs : out STD_LOGIC; 
    trd_drq_10_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_14_data_cs : out STD_LOGIC; 
    trd_host_cmd_15_data_oe : out STD_LOGIC; 
    trd_host_cmd_11_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_10_req : in STD_LOGIC := 'X'; 
    trd_main_drq_14_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_12_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_10_cmd_adr_we : out STD_LOGIC; 
    trd_host_cmd_6_status_cs : out STD_LOGIC; 
    trd_drq_11_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_8_cmd_data_we : out STD_LOGIC; 
    trd_main_drq_11_req : in STD_LOGIC := 'X'; 
    trd_main_drq_15_ack : in STD_LOGIC := 'X'; 
    trd_drq_12_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_2_cmd_data_cs : out STD_LOGIC; 
    trd_drq_12_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_status_cs : out STD_LOGIC; 
    trd_host_cmd_4_data_we : out STD_LOGIC; 
    trd_host_cmd_2_data_cs : out STD_LOGIC; 
    trd_host_cmd_3_data_oe : out STD_LOGIC; 
    trd_main_drq_12_req : in STD_LOGIC := 'X'; 
    trd_drq_13_ack : in STD_LOGIC := 'X'; 
    trd_main_drq_1_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_15_data_we : out STD_LOGIC; 
    trd_main_drq_13_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_13_data_cs : out STD_LOGIC; 
    trd_host_cmd_14_cmd_data_we : out STD_LOGIC; 
    trd_host_cmd_14_data_oe : out STD_LOGIC; 
    trd_host_cmd_6_cmd_adr_we : out STD_LOGIC; 
    trd_drq_10_req : in STD_LOGIC := 'X'; 
    trd_drq_14_ack : in STD_LOGIC := 'X'; 
    trd_drq_1_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_9_cmd_data_cs : out STD_LOGIC; 
    trd_main_drq_6_en : in STD_LOGIC := 'X'; 
    trd_main_drq_14_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_status_cs : out STD_LOGIC; 
    trd_drq_11_req : in STD_LOGIC := 'X'; 
    trd_drq_15_ack : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_cmd_data_we : out STD_LOGIC; 
    trd_drq_6_en : in STD_LOGIC := 'X'; 
    mgt251_n : in STD_LOGIC := 'X'; 
    mgt251_p : in STD_LOGIC := 'X'; 
    trd_host_cmd_3_data_we : out STD_LOGIC; 
    trd_main_drq_15_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_1_data_cs : out STD_LOGIC; 
    trd_host_cmd_2_data_oe : out STD_LOGIC; 
    trd_host_cmd_7_status_cs : out STD_LOGIC; 
    trd_drq_12_req : in STD_LOGIC := 'X'; 
    clk3_pll : out STD_LOGIC; 
    trd_host_cmd_15_cmd_data_cs : out STD_LOGIC; 
    trd_host_cmd_10_status_cs : out STD_LOGIC; 
    trd_host_cmd_14_data_we : out STD_LOGIC; 
    trd_drq_13_req : in STD_LOGIC := 'X'; 
    trd_host_cmd_12_data_cs : out STD_LOGIC; 
    trd_main_drq_14_en : in STD_LOGIC := 'X'; 
    trd_host_cmd_5_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_5_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_6_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_7_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_8_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_9_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_10_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_11_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_12_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_13_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_14_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_15_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_0_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_1_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_2_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_3_adr_0_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_9_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_8_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_7_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_6_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_5_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_4_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_3_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_2_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_1_Q : out STD_LOGIC; 
    trd_host_cmd_4_adr_0_Q : out STD_LOGIC; 
    trd_host_adr : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    p : out STD_LOGIC_VECTOR ( 3 downto 1 ); 
    trd_host_data : out STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
    txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trd_host_cmd_data : out STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
    trd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
    trd_cmd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
    rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    trd_main_sel_drq : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 6 downto 0 ); 
    trd_main_irq : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    trd_reset_fifo : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end cl_ambpex5_m5;

architecture STRUCTURE of cl_ambpex5_m5 is
  component ctrl_blink
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      led_h1 : out STD_LOGIC; 
      pcie_link_up : in STD_LOGIC := 'X'; 
      clk30k : in STD_LOGIC := 'X'; 
      pcie_lstatus : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component pb_adm_ctrl_m2
    port (
      trd_host_cmd_11_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_13_data_oe : out STD_LOGIC; 
      trd_host_cmd_6_cmd_data_cs : out STD_LOGIC; 
      trd_drq_14_req : in STD_LOGIC := 'X'; 
      trd_drq_14_en : in STD_LOGIC := 'X'; 
      drq1_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_2_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_9_data_cs : out STD_LOGIC; 
      trd_host_cmd_12_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_15_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_2_data_we : out STD_LOGIC; 
      trd_drq_15_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_cs : out STD_LOGIC; 
      trd_host_cmd_1_data_oe : out STD_LOGIC; 
      lc_wr : in STD_LOGIC := 'X'; 
      drq1_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_2_status_cs : out STD_LOGIC; 
      trd_host_cmd_13_data_we : out STD_LOGIC; 
      trd_host_cmd_11_data_cs : out STD_LOGIC; 
      trd_drq_3_en : in STD_LOGIC := 'X'; 
      trd_drq_0_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_data_oe : out STD_LOGIC; 
      trd_host_cmd_9_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_8_status_cs : out STD_LOGIC; 
      trd_drq_8_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_11_status_cs : out STD_LOGIC; 
      trd_drq_1_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_8_data_cs : out STD_LOGIC; 
      trd_host_cmd_9_data_oe : out STD_LOGIC; 
      trd_host_cmd_4_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_1_data_we : out STD_LOGIC; 
      drq3_ack : in STD_LOGIC := 'X'; 
      trd_drq_2_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_oe : out STD_LOGIC; 
      trd_host_cmd_15_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_14_cmd_adr_we : out STD_LOGIC; 
      trd_drq_3_ack : in STD_LOGIC := 'X'; 
      trd_drq_11_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_12_data_we : out STD_LOGIC; 
      trd_host_cmd_10_data_cs : out STD_LOGIC; 
      trd_host_cmd_11_data_oe : out STD_LOGIC; 
      trd_host_cmd_6_cmd_data_we : out STD_LOGIC; 
      trd_drq_4_ack : in STD_LOGIC := 'X'; 
      trd_drq_0_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_data_we : out STD_LOGIC; 
      trd_host_cmd_3_status_cs : out STD_LOGIC; 
      trd_host_cmd_7_data_cs : out STD_LOGIC; 
      trd_host_cmd_12_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_8_data_oe : out STD_LOGIC; 
      trd_drq_5_ack : in STD_LOGIC := 'X'; 
      trd_drq_1_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_we : out STD_LOGIC; 
      trd_host_cmd_7_cmd_data_cs : out STD_LOGIC; 
      trd_drq_0_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_status_cs : out STD_LOGIC; 
      drq3_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_cmd_adr_we : out STD_LOGIC; 
      trd_drq_6_ack : in STD_LOGIC := 'X'; 
      trd_drq_2_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_status_cs : out STD_LOGIC; 
      trd_host_cmd_3_cmd_data_we : out STD_LOGIC; 
      trd_drq_5_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_11_data_we : out STD_LOGIC; 
      trd_host_cmd_13_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_10_data_oe : out STD_LOGIC; 
      trd_drq_7_ack : in STD_LOGIC := 'X'; 
      trd_drq_3_req : in STD_LOGIC := 'X'; 
      dmar0 : out STD_LOGIC; 
      drq0_ack : in STD_LOGIC := 'X'; 
      dmar1 : out STD_LOGIC; 
      drq2_en : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      dmar2 : out STD_LOGIC; 
      trd_host_cmd_13_cmd_data_cs : out STD_LOGIC; 
      dmar3 : out STD_LOGIC; 
      trd_host_cmd_8_data_we : out STD_LOGIC; 
      trd_drq_4_req : in STD_LOGIC := 'X'; 
      trd_drq_8_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_6_data_cs : out STD_LOGIC; 
      trd_host_cmd_7_data_oe : out STD_LOGIC; 
      trd_host_cmd_4_cmd_data_cs : out STD_LOGIC; 
      trd_drq_9_ack : in STD_LOGIC := 'X'; 
      trd_drq_5_req : in STD_LOGIC := 'X'; 
      trd_drq_13_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_4_status_cs : out STD_LOGIC; 
      trd_host_cmd_10_data_we : out STD_LOGIC; 
      trd_host_cmd_9_cmd_adr_we : out STD_LOGIC; 
      trd_drq_6_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_2_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_12_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_10_cmd_data_cs : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      trd_drq_7_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_13_status_cs : out STD_LOGIC; 
      drq0_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_7_data_we : out STD_LOGIC; 
      trd_host_cmd_5_data_cs : out STD_LOGIC; 
      trd_host_cmd_6_data_oe : out STD_LOGIC; 
      trd_drq_2_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_7_cmd_data_we : out STD_LOGIC; 
      trd_drq_8_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_cmd_data_cs : out STD_LOGIC; 
      trd_drq_7_en : in STD_LOGIC := 'X'; 
      trd_drq_9_req : in STD_LOGIC := 'X'; 
      drq2_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_13_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_8_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_1_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_8_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_6_data_we : out STD_LOGIC; 
      trd_drq_10_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_4_data_cs : out STD_LOGIC; 
      trd_host_cmd_5_status_cs : out STD_LOGIC; 
      trd_host_cmd_5_data_oe : out STD_LOGIC; 
      trd_host_cmd_4_cmd_data_we : out STD_LOGIC; 
      trd_drq_15_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_11_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_15_data_cs : out STD_LOGIC; 
      trd_host_cmd_14_status_cs : out STD_LOGIC; 
      trd_host_cmd_14_cmd_data_cs : out STD_LOGIC; 
      int1 : in STD_LOGIC := 'X'; 
      drq3_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_10_cmd_data_we : out STD_LOGIC; 
      drq2_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_data_cs : out STD_LOGIC; 
      drq0_en : in STD_LOGIC := 'X'; 
      trd_drq_4_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_data_we : out STD_LOGIC; 
      trd_host_cmd_7_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_3_data_cs : out STD_LOGIC; 
      trd_host_cmd_0_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_4_data_oe : out STD_LOGIC; 
      test_mode : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_cmd_data_we : out STD_LOGIC; 
      trd_drq_9_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_status_cs : out STD_LOGIC; 
      trd_drq_10_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_14_data_cs : out STD_LOGIC; 
      trd_host_cmd_15_data_oe : out STD_LOGIC; 
      trd_host_cmd_11_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_10_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_6_status_cs : out STD_LOGIC; 
      trd_drq_11_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_8_cmd_data_we : out STD_LOGIC; 
      trd_drq_12_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_2_cmd_data_cs : out STD_LOGIC; 
      trd_drq_12_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_status_cs : out STD_LOGIC; 
      trd_host_cmd_4_data_we : out STD_LOGIC; 
      trd_host_cmd_2_data_cs : out STD_LOGIC; 
      trd_host_cmd_3_data_oe : out STD_LOGIC; 
      trd_drq_13_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_data_we : out STD_LOGIC; 
      trd_host_cmd_13_data_cs : out STD_LOGIC; 
      trd_host_cmd_14_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_14_data_oe : out STD_LOGIC; 
      trd_drq_10_req : in STD_LOGIC := 'X'; 
      irq1 : out STD_LOGIC; 
      trd_host_cmd_6_cmd_adr_we : out STD_LOGIC; 
      trd_drq_14_ack : in STD_LOGIC := 'X'; 
      trd_drq_1_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_1_status_cs : out STD_LOGIC; 
      trd_drq_11_req : in STD_LOGIC := 'X'; 
      trd_drq_15_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_data_we : out STD_LOGIC; 
      trd_drq_6_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_data_we : out STD_LOGIC; 
      trd_host_cmd_1_data_cs : out STD_LOGIC; 
      trd_host_cmd_2_data_oe : out STD_LOGIC; 
      trd_host_cmd_7_status_cs : out STD_LOGIC; 
      trd_drq_12_req : in STD_LOGIC := 'X'; 
      drq1_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_cmd_data_cs : out STD_LOGIC; 
      lc_rd : in STD_LOGIC := 'X'; 
      trd_host_cmd_10_status_cs : out STD_LOGIC; 
      trd_host_cmd_14_data_we : out STD_LOGIC; 
      trd_drq_13_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_data_cs : out STD_LOGIC; 
      trd_host_cmd_5_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_0_Q : out STD_LOGIC; 
      trd_host_adr : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      trd4_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trd_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      lc_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
      trd_cmd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
      lc_host_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      trd_reset_fifo : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      lc_adr : in STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  component pcie_core64_m2
    port (
      clk : in STD_LOGIC := 'X'; 
      lc_irq : in STD_LOGIC := 'X'; 
      mgt250 : in STD_LOGIC := 'X'; 
      lc_rd : out STD_LOGIC; 
      clk250_out : out STD_LOGIC; 
      lc_wr : out STD_LOGIC; 
      pcie_link_up : out STD_LOGIC; 
      clk_lock : in STD_LOGIC := 'X'; 
      reset_out : out STD_LOGIC; 
      perst : in STD_LOGIC := 'X'; 
      dcm_rstp : out STD_LOGIC; 
      lc_host_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      px : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      lc_adr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      pcie_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      lc_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      lc_dma_req : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_clk : STD_LOGIC; 
  signal NlwRenamedSig_OI_clk30k : STD_LOGIC; 
  signal NlwRenamedSig_OI_clk_lock_out : STD_LOGIC; 
  signal cnt30ce1 : STD_LOGIC; 
  signal cnt30ce2 : STD_LOGIC; 
  signal cnt30i0 : STD_LOGIC; 
  signal cnt30i1 : STD_LOGIC; 
  signal cnt30i2 : STD_LOGIC; 
  signal cnt30k0 : STD_LOGIC; 
  signal cnt30k1 : STD_LOGIC; 
  signal cnt30start_33895 : STD_LOGIC; 
  signal cnt30start1_33896 : STD_LOGIC; 
  signal dcm_rstp : STD_LOGIC; 
  signal dmar0 : STD_LOGIC; 
  signal dmar1 : STD_LOGIC; 
  signal irq1 : STD_LOGIC; 
  signal lc_rd : STD_LOGIC; 
  signal lc_wr : STD_LOGIC; 
  signal NlwRenamedSig_OI_led_h4 : STD_LOGIC; 
  signal mgt250 : STD_LOGIC; 
  signal pcie_link_up : STD_LOGIC; 
  signal perst : STD_LOGIC; 
  signal trd_host_cmd_0_cmd_data_we_35483 : STD_LOGIC; 
  signal trd_host_cmd_0_data_we_35484 : STD_LOGIC; 
  signal trd_host_cmd_1_cmd_data_we_35498 : STD_LOGIC; 
  signal trd_host_cmd_6_cmd_data_we_35564 : STD_LOGIC; 
  signal trd_host_cmd_7_cmd_data_we_35578 : STD_LOGIC; 
  signal trd_host_cmd_7_data_we_35579 : STD_LOGIC; 
  signal trd_host_cmd_data_0_0_35594 : STD_LOGIC; 
  signal trd_host_cmd_data_0_1_35595 : STD_LOGIC; 
  signal trd_host_cmd_data_0_10_35596 : STD_LOGIC; 
  signal trd_host_cmd_data_0_11_35597 : STD_LOGIC; 
  signal trd_host_cmd_data_0_12_35598 : STD_LOGIC; 
  signal trd_host_cmd_data_0_13_35599 : STD_LOGIC; 
  signal trd_host_cmd_data_0_14_35600 : STD_LOGIC; 
  signal trd_host_cmd_data_0_15_35601 : STD_LOGIC; 
  signal trd_host_cmd_data_0_2_35602 : STD_LOGIC; 
  signal trd_host_cmd_data_0_3_35603 : STD_LOGIC; 
  signal trd_host_cmd_data_0_4_35604 : STD_LOGIC; 
  signal trd_host_cmd_data_0_5_35605 : STD_LOGIC; 
  signal trd_host_cmd_data_0_6_35606 : STD_LOGIC; 
  signal trd_host_cmd_data_0_7_35607 : STD_LOGIC; 
  signal trd_host_cmd_data_0_8_35608 : STD_LOGIC; 
  signal trd_host_cmd_data_0_9_35609 : STD_LOGIC; 
  signal trd_host_cmd_data_1_0_35610 : STD_LOGIC; 
  signal trd_host_cmd_data_1_1_35611 : STD_LOGIC; 
  signal trd_host_cmd_data_1_10_35612 : STD_LOGIC; 
  signal trd_host_cmd_data_1_11_35613 : STD_LOGIC; 
  signal trd_host_cmd_data_1_12_35614 : STD_LOGIC; 
  signal trd_host_cmd_data_1_13_35615 : STD_LOGIC; 
  signal trd_host_cmd_data_1_14_35616 : STD_LOGIC; 
  signal trd_host_cmd_data_1_15_35617 : STD_LOGIC; 
  signal trd_host_cmd_data_1_2_35618 : STD_LOGIC; 
  signal trd_host_cmd_data_1_3_35619 : STD_LOGIC; 
  signal trd_host_cmd_data_1_4_35620 : STD_LOGIC; 
  signal trd_host_cmd_data_1_5_35621 : STD_LOGIC; 
  signal trd_host_cmd_data_1_6_35622 : STD_LOGIC; 
  signal trd_host_cmd_data_1_7_35623 : STD_LOGIC; 
  signal trd_host_cmd_data_1_8_35624 : STD_LOGIC; 
  signal trd_host_cmd_data_1_9_35625 : STD_LOGIC; 
  signal trd_host_cmd_data_6_0_35626 : STD_LOGIC; 
  signal trd_host_cmd_data_6_1_35627 : STD_LOGIC; 
  signal trd_host_cmd_data_6_10_35628 : STD_LOGIC; 
  signal trd_host_cmd_data_6_11_35629 : STD_LOGIC; 
  signal trd_host_cmd_data_6_12_35630 : STD_LOGIC; 
  signal trd_host_cmd_data_6_13_35631 : STD_LOGIC; 
  signal trd_host_cmd_data_6_14_35632 : STD_LOGIC; 
  signal trd_host_cmd_data_6_15_35633 : STD_LOGIC; 
  signal trd_host_cmd_data_6_2_35634 : STD_LOGIC; 
  signal trd_host_cmd_data_6_3_35635 : STD_LOGIC; 
  signal trd_host_cmd_data_6_4_35636 : STD_LOGIC; 
  signal trd_host_cmd_data_6_5_35637 : STD_LOGIC; 
  signal trd_host_cmd_data_6_6_35638 : STD_LOGIC; 
  signal trd_host_cmd_data_6_7_35639 : STD_LOGIC; 
  signal trd_host_cmd_data_6_8_35640 : STD_LOGIC; 
  signal trd_host_cmd_data_6_9_35641 : STD_LOGIC; 
  signal trd_host_cmd_data_7_0_35642 : STD_LOGIC; 
  signal trd_host_cmd_data_7_1_35643 : STD_LOGIC; 
  signal trd_host_cmd_data_7_10_35644 : STD_LOGIC; 
  signal trd_host_cmd_data_7_11_35645 : STD_LOGIC; 
  signal trd_host_cmd_data_7_12_35646 : STD_LOGIC; 
  signal trd_host_cmd_data_7_13_35647 : STD_LOGIC; 
  signal trd_host_cmd_data_7_14_35648 : STD_LOGIC; 
  signal trd_host_cmd_data_7_15_35649 : STD_LOGIC; 
  signal trd_host_cmd_data_7_2_35650 : STD_LOGIC; 
  signal trd_host_cmd_data_7_3_35651 : STD_LOGIC; 
  signal trd_host_cmd_data_7_4_35652 : STD_LOGIC; 
  signal trd_host_cmd_data_7_5_35653 : STD_LOGIC; 
  signal trd_host_cmd_data_7_6_35654 : STD_LOGIC; 
  signal trd_host_cmd_data_7_7_35655 : STD_LOGIC; 
  signal trd_host_cmd_data_7_8_35656 : STD_LOGIC; 
  signal trd_host_cmd_data_7_9_35657 : STD_LOGIC; 
  signal trdi_host_cmd_0_cmd_data_we : STD_LOGIC; 
  signal trdi_host_cmd_0_data_we : STD_LOGIC; 
  signal trdi_host_cmd_1_cmd_data_we : STD_LOGIC; 
  signal trdi_host_cmd_6_cmd_data_we : STD_LOGIC; 
  signal trdi_host_cmd_7_cmd_data_we : STD_LOGIC; 
  signal trdi_host_cmd_7_data_we : STD_LOGIC; 
  signal NLW_gen_syn_pcie_px_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_px_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_px_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_px_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_px_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_pcie_lc_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_5_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_2_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_2_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_1_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_4_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_1_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_0_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_3_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_3_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_dmar2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_dmar3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_7_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_2_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_6_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_1_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_6_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_5_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_4_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_5_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_7_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_0_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_4_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_4_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_3_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_6_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_5_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_3_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_2_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_8_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_9_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_10_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_11_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_12_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_13_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_14_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_syn_ad_trd_host_cmd_15_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_xcnt0_Q_UNCONNECTED : STD_LOGIC; 
  signal NLW_xcnt1_Q_UNCONNECTED : STD_LOGIC; 
  signal NLW_xcnt2_Q31_UNCONNECTED : STD_LOGIC; 
  signal lc_adr : STD_LOGIC_VECTOR ( 17 downto 11 ); 
  signal lc_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal lc_host_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal pcie_lstatus : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal trd4_host_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal NlwRenamedSig_OI_trd_host_cmd_data : STD_LOGIC_VECTOR2 ( 8 downto 8 , 0 downto 0 ); 
  signal trdi_host_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  trd_host_cmd_11_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_1_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  clk_out <= NlwRenamedSig_OI_clk;
  trd_host_cmd_8_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  clk5_pll <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_0_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_6_cmd_data_we <= trd_host_cmd_6_cmd_data_we_35564;
  trd_host_cmd_9_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  clk_lock_out <= NlwRenamedSig_OI_clk_lock_out;
  trd_host_cmd_12_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_0_data_we <= trd_host_cmd_0_data_we_35484;
  trd_host_cmd_9_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  clk2_pll <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_7_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  led_h4 <= NlwRenamedSig_OI_led_h4;
  trd_host_cmd_0_cmd_data_we <= trd_host_cmd_0_cmd_data_we_35483;
  trd_host_cmd_10_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_7_data_we <= trd_host_cmd_7_data_we_35579;
  trd_host_cmd_6_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_7_cmd_data_we <= trd_host_cmd_7_cmd_data_we_35578;
  clk30k <= NlwRenamedSig_OI_clk30k;
  clk4_pll <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_5_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_4_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_1_cmd_data_we <= trd_host_cmd_1_cmd_data_we_35498;
  trd_host_cmd_14_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_cmd_adr_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_3_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_cmd_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_2_data_oe <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  clk3_pll <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_cmd_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_status_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_data_we <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_data_cs <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_adr(7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_8_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_9_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_10_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_11_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_12_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_13_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_14_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(15, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(14, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(13, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(12, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(11, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(10, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(9, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 63) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 62) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 61) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 60) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 59) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 58) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 57) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 56) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 55) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 54) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 53) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 52) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 51) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 50) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 49) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 48) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 47) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 46) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 45) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 44) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 43) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 42) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 41) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 40) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 39) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 38) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 37) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 36) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 35) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 34) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 33) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 32) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 31) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 30) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 29) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 28) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 27) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 26) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 25) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 24) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 23) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 22) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 21) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 20) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 19) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 18) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 17) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 16) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_data(8, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_9_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_8_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_7_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_6_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_5_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_4_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_3_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_2_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_1_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_15_adr_0_Q <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(15, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(14, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(13, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(12, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(11, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(10, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(9, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 15) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 14) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 13) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 12) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 11) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 10) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 9) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 8) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 7) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 6) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 5) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 4) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 3) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 2) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 1) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(8, 0) <= NlwRenamedSig_OI_trd_host_cmd_data(8, 0);
  trd_host_cmd_data(7, 15) <= trd_host_cmd_data_7_15_35649;
  trd_host_cmd_data(7, 14) <= trd_host_cmd_data_7_14_35648;
  trd_host_cmd_data(7, 13) <= trd_host_cmd_data_7_13_35647;
  trd_host_cmd_data(7, 12) <= trd_host_cmd_data_7_12_35646;
  trd_host_cmd_data(7, 11) <= trd_host_cmd_data_7_11_35645;
  trd_host_cmd_data(7, 10) <= trd_host_cmd_data_7_10_35644;
  trd_host_cmd_data(7, 9) <= trd_host_cmd_data_7_9_35657;
  trd_host_cmd_data(7, 8) <= trd_host_cmd_data_7_8_35656;
  trd_host_cmd_data(7, 7) <= trd_host_cmd_data_7_7_35655;
  trd_host_cmd_data(7, 6) <= trd_host_cmd_data_7_6_35654;
  trd_host_cmd_data(7, 5) <= trd_host_cmd_data_7_5_35653;
  trd_host_cmd_data(7, 4) <= trd_host_cmd_data_7_4_35652;
  trd_host_cmd_data(7, 3) <= trd_host_cmd_data_7_3_35651;
  trd_host_cmd_data(7, 2) <= trd_host_cmd_data_7_2_35650;
  trd_host_cmd_data(7, 1) <= trd_host_cmd_data_7_1_35643;
  trd_host_cmd_data(7, 0) <= trd_host_cmd_data_7_0_35642;
  trd_host_cmd_data(6, 15) <= trd_host_cmd_data_6_15_35633;
  trd_host_cmd_data(6, 14) <= trd_host_cmd_data_6_14_35632;
  trd_host_cmd_data(6, 13) <= trd_host_cmd_data_6_13_35631;
  trd_host_cmd_data(6, 12) <= trd_host_cmd_data_6_12_35630;
  trd_host_cmd_data(6, 11) <= trd_host_cmd_data_6_11_35629;
  trd_host_cmd_data(6, 10) <= trd_host_cmd_data_6_10_35628;
  trd_host_cmd_data(6, 9) <= trd_host_cmd_data_6_9_35641;
  trd_host_cmd_data(6, 8) <= trd_host_cmd_data_6_8_35640;
  trd_host_cmd_data(6, 7) <= trd_host_cmd_data_6_7_35639;
  trd_host_cmd_data(6, 6) <= trd_host_cmd_data_6_6_35638;
  trd_host_cmd_data(6, 5) <= trd_host_cmd_data_6_5_35637;
  trd_host_cmd_data(6, 4) <= trd_host_cmd_data_6_4_35636;
  trd_host_cmd_data(6, 3) <= trd_host_cmd_data_6_3_35635;
  trd_host_cmd_data(6, 2) <= trd_host_cmd_data_6_2_35634;
  trd_host_cmd_data(6, 1) <= trd_host_cmd_data_6_1_35627;
  trd_host_cmd_data(6, 0) <= trd_host_cmd_data_6_0_35626;
  trd_host_cmd_data(1, 15) <= trd_host_cmd_data_1_15_35617;
  trd_host_cmd_data(1, 14) <= trd_host_cmd_data_1_14_35616;
  trd_host_cmd_data(1, 13) <= trd_host_cmd_data_1_13_35615;
  trd_host_cmd_data(1, 12) <= trd_host_cmd_data_1_12_35614;
  trd_host_cmd_data(1, 11) <= trd_host_cmd_data_1_11_35613;
  trd_host_cmd_data(1, 10) <= trd_host_cmd_data_1_10_35612;
  trd_host_cmd_data(1, 9) <= trd_host_cmd_data_1_9_35625;
  trd_host_cmd_data(1, 8) <= trd_host_cmd_data_1_8_35624;
  trd_host_cmd_data(1, 7) <= trd_host_cmd_data_1_7_35623;
  trd_host_cmd_data(1, 6) <= trd_host_cmd_data_1_6_35622;
  trd_host_cmd_data(1, 5) <= trd_host_cmd_data_1_5_35621;
  trd_host_cmd_data(1, 4) <= trd_host_cmd_data_1_4_35620;
  trd_host_cmd_data(1, 3) <= trd_host_cmd_data_1_3_35619;
  trd_host_cmd_data(1, 2) <= trd_host_cmd_data_1_2_35618;
  trd_host_cmd_data(1, 1) <= trd_host_cmd_data_1_1_35611;
  trd_host_cmd_data(1, 0) <= trd_host_cmd_data_1_0_35610;
  trd_host_cmd_data(0, 15) <= trd_host_cmd_data_0_15_35601;
  trd_host_cmd_data(0, 14) <= trd_host_cmd_data_0_14_35600;
  trd_host_cmd_data(0, 13) <= trd_host_cmd_data_0_13_35599;
  trd_host_cmd_data(0, 12) <= trd_host_cmd_data_0_12_35598;
  trd_host_cmd_data(0, 11) <= trd_host_cmd_data_0_11_35597;
  trd_host_cmd_data(0, 10) <= trd_host_cmd_data_0_10_35596;
  trd_host_cmd_data(0, 9) <= trd_host_cmd_data_0_9_35609;
  trd_host_cmd_data(0, 8) <= trd_host_cmd_data_0_8_35608;
  trd_host_cmd_data(0, 7) <= trd_host_cmd_data_0_7_35607;
  trd_host_cmd_data(0, 6) <= trd_host_cmd_data_0_6_35606;
  trd_host_cmd_data(0, 5) <= trd_host_cmd_data_0_5_35605;
  trd_host_cmd_data(0, 4) <= trd_host_cmd_data_0_4_35604;
  trd_host_cmd_data(0, 3) <= trd_host_cmd_data_0_3_35603;
  trd_host_cmd_data(0, 2) <= trd_host_cmd_data_0_2_35602;
  trd_host_cmd_data(0, 1) <= trd_host_cmd_data_0_1_35595;
  trd_host_cmd_data(0, 0) <= trd_host_cmd_data_0_0_35594;
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_trd_host_cmd_data(8, 0)
    );
  XST_VCC : VCC
    port map (
      P => NlwRenamedSig_OI_clk_lock_out
    );
  trd_host_cmd_7_data_we_5554 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_7_data_we,
      Q => trd_host_cmd_7_data_we_35579
    );
  trd_host_cmd_7_cmd_data_we_5555 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_7_cmd_data_we,
      Q => trd_host_cmd_7_cmd_data_we_35578
    );
  trd_host_cmd_1_cmd_data_we_5556 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_1_cmd_data_we,
      Q => trd_host_cmd_1_cmd_data_we_35498
    );
  trd_host_cmd_0_data_we_5557 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_0_data_we,
      Q => trd_host_cmd_0_data_we_35484
    );
  trd_host_cmd_6_cmd_data_we_5558 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_6_cmd_data_we,
      Q => trd_host_cmd_6_cmd_data_we_35564
    );
  trd_host_cmd_0_cmd_data_we_5559 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_cmd_0_cmd_data_we,
      Q => trd_host_cmd_0_cmd_data_we_35483
    );
  reset_out_5560 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => NlwRenamedSig_OI_led_h4,
      Q => reset_out
    );
  cnt30start : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => dcm_rstp,
      Q => cnt30start_33895
    );
  trd_host_cmd_data_0_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_cmd_data_0_0_35594
    );
  trd_host_cmd_data_0_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_cmd_data_0_1_35595
    );
  trd_host_cmd_data_0_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_cmd_data_0_2_35602
    );
  trd_host_cmd_data_0_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_cmd_data_0_3_35603
    );
  trd_host_cmd_data_0_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_cmd_data_0_4_35604
    );
  trd_host_cmd_data_0_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_cmd_data_0_5_35605
    );
  trd_host_cmd_data_0_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_cmd_data_0_6_35606
    );
  trd_host_cmd_data_0_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_cmd_data_0_7_35607
    );
  trd_host_cmd_data_0_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_cmd_data_0_8_35608
    );
  trd_host_cmd_data_0_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_cmd_data_0_9_35609
    );
  trd_host_cmd_data_0_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_cmd_data_0_10_35596
    );
  trd_host_cmd_data_0_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_cmd_data_0_11_35597
    );
  trd_host_cmd_data_0_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_cmd_data_0_12_35598
    );
  trd_host_cmd_data_0_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_cmd_data_0_13_35599
    );
  trd_host_cmd_data_0_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_cmd_data_0_14_35600
    );
  trd_host_cmd_data_0_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_cmd_data_0_15_35601
    );
  trd_host_cmd_data_1_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_cmd_data_1_0_35610
    );
  trd_host_cmd_data_1_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_cmd_data_1_1_35611
    );
  trd_host_cmd_data_1_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_cmd_data_1_2_35618
    );
  trd_host_cmd_data_1_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_cmd_data_1_3_35619
    );
  trd_host_cmd_data_1_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_cmd_data_1_4_35620
    );
  trd_host_cmd_data_1_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_cmd_data_1_5_35621
    );
  trd_host_cmd_data_1_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_cmd_data_1_6_35622
    );
  trd_host_cmd_data_1_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_cmd_data_1_7_35623
    );
  trd_host_cmd_data_1_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_cmd_data_1_8_35624
    );
  trd_host_cmd_data_1_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_cmd_data_1_9_35625
    );
  trd_host_cmd_data_1_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_cmd_data_1_10_35612
    );
  trd_host_cmd_data_1_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_cmd_data_1_11_35613
    );
  trd_host_cmd_data_1_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_cmd_data_1_12_35614
    );
  trd_host_cmd_data_1_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_cmd_data_1_13_35615
    );
  trd_host_cmd_data_1_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_cmd_data_1_14_35616
    );
  trd_host_cmd_data_1_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_cmd_data_1_15_35617
    );
  trd_host_cmd_data_6_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_cmd_data_6_0_35626
    );
  trd_host_cmd_data_6_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_cmd_data_6_1_35627
    );
  trd_host_cmd_data_6_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_cmd_data_6_2_35634
    );
  trd_host_cmd_data_6_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_cmd_data_6_3_35635
    );
  trd_host_cmd_data_6_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_cmd_data_6_4_35636
    );
  trd_host_cmd_data_6_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_cmd_data_6_5_35637
    );
  trd_host_cmd_data_6_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_cmd_data_6_6_35638
    );
  trd_host_cmd_data_6_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_cmd_data_6_7_35639
    );
  trd_host_cmd_data_6_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_cmd_data_6_8_35640
    );
  trd_host_cmd_data_6_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_cmd_data_6_9_35641
    );
  trd_host_cmd_data_6_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_cmd_data_6_10_35628
    );
  trd_host_cmd_data_6_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_cmd_data_6_11_35629
    );
  trd_host_cmd_data_6_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_cmd_data_6_12_35630
    );
  trd_host_cmd_data_6_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_cmd_data_6_13_35631
    );
  trd_host_cmd_data_6_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_cmd_data_6_14_35632
    );
  trd_host_cmd_data_6_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_cmd_data_6_15_35633
    );
  trd_host_cmd_data_7_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_cmd_data_7_0_35642
    );
  trd_host_cmd_data_7_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_cmd_data_7_1_35643
    );
  trd_host_cmd_data_7_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_cmd_data_7_2_35650
    );
  trd_host_cmd_data_7_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_cmd_data_7_3_35651
    );
  trd_host_cmd_data_7_4 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_cmd_data_7_4_35652
    );
  trd_host_cmd_data_7_5 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_cmd_data_7_5_35653
    );
  trd_host_cmd_data_7_6 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_cmd_data_7_6_35654
    );
  trd_host_cmd_data_7_7 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_cmd_data_7_7_35655
    );
  trd_host_cmd_data_7_8 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_cmd_data_7_8_35656
    );
  trd_host_cmd_data_7_9 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_cmd_data_7_9_35657
    );
  trd_host_cmd_data_7_10 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_cmd_data_7_10_35644
    );
  trd_host_cmd_data_7_11 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_cmd_data_7_11_35645
    );
  trd_host_cmd_data_7_12 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_cmd_data_7_12_35646
    );
  trd_host_cmd_data_7_13 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_cmd_data_7_13_35647
    );
  trd_host_cmd_data_7_14 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_cmd_data_7_14_35648
    );
  trd_host_cmd_data_7_15 : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_cmd_data_7_15_35649
    );
  cnt30start1 : FD
    port map (
      C => NlwRenamedSig_OI_clk,
      D => cnt30start_33895,
      Q => cnt30start1_33896
    );
  gen_cmd_0_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(0, 0)
    );
  gen_cmd_0_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(0, 1)
    );
  gen_cmd_0_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(0, 2)
    );
  gen_cmd_0_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(0, 3)
    );
  gen_cmd_0_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(0, 4)
    );
  gen_cmd_0_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(0, 5)
    );
  gen_cmd_0_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(0, 6)
    );
  gen_cmd_0_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(0, 7)
    );
  gen_cmd_0_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(0, 8)
    );
  gen_cmd_0_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(0, 9)
    );
  gen_cmd_0_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(0, 10)
    );
  gen_cmd_0_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(0, 11)
    );
  gen_cmd_0_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(0, 12)
    );
  gen_cmd_0_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(0, 13)
    );
  gen_cmd_0_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(0, 14)
    );
  gen_cmd_0_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(0, 15)
    );
  gen_cmd_0_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(0, 16)
    );
  gen_cmd_0_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(0, 17)
    );
  gen_cmd_0_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(0, 18)
    );
  gen_cmd_0_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(0, 19)
    );
  gen_cmd_0_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(0, 20)
    );
  gen_cmd_0_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(0, 21)
    );
  gen_cmd_0_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(0, 22)
    );
  gen_cmd_0_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(0, 23)
    );
  gen_cmd_0_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(0, 24)
    );
  gen_cmd_0_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(0, 25)
    );
  gen_cmd_0_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(0, 26)
    );
  gen_cmd_0_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(0, 27)
    );
  gen_cmd_0_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(0, 28)
    );
  gen_cmd_0_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(0, 29)
    );
  gen_cmd_0_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(0, 30)
    );
  gen_cmd_0_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(0, 31)
    );
  gen_cmd_0_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(0, 32)
    );
  gen_cmd_0_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(0, 33)
    );
  gen_cmd_0_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(0, 34)
    );
  gen_cmd_0_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(0, 35)
    );
  gen_cmd_0_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(0, 36)
    );
  gen_cmd_0_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(0, 37)
    );
  gen_cmd_0_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(0, 38)
    );
  gen_cmd_0_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(0, 39)
    );
  gen_cmd_0_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(0, 40)
    );
  gen_cmd_0_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(0, 41)
    );
  gen_cmd_0_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(0, 42)
    );
  gen_cmd_0_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(0, 43)
    );
  gen_cmd_0_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(0, 44)
    );
  gen_cmd_0_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(0, 45)
    );
  gen_cmd_0_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(0, 46)
    );
  gen_cmd_0_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(0, 47)
    );
  gen_cmd_0_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(0, 48)
    );
  gen_cmd_0_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(0, 49)
    );
  gen_cmd_0_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(0, 50)
    );
  gen_cmd_0_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(0, 51)
    );
  gen_cmd_0_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(0, 52)
    );
  gen_cmd_0_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(0, 53)
    );
  gen_cmd_0_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(0, 54)
    );
  gen_cmd_0_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(0, 55)
    );
  gen_cmd_0_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(0, 56)
    );
  gen_cmd_0_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(0, 57)
    );
  gen_cmd_0_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(0, 58)
    );
  gen_cmd_0_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(0, 59)
    );
  gen_cmd_0_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(0, 60)
    );
  gen_cmd_0_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(0, 61)
    );
  gen_cmd_0_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(0, 62)
    );
  gen_cmd_0_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(0, 63)
    );
  gen_cmd_1_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(1, 0)
    );
  gen_cmd_1_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(1, 1)
    );
  gen_cmd_1_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(1, 2)
    );
  gen_cmd_1_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(1, 3)
    );
  gen_cmd_1_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(1, 4)
    );
  gen_cmd_1_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(1, 5)
    );
  gen_cmd_1_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(1, 6)
    );
  gen_cmd_1_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(1, 7)
    );
  gen_cmd_1_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(1, 8)
    );
  gen_cmd_1_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(1, 9)
    );
  gen_cmd_1_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(1, 10)
    );
  gen_cmd_1_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(1, 11)
    );
  gen_cmd_1_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(1, 12)
    );
  gen_cmd_1_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(1, 13)
    );
  gen_cmd_1_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(1, 14)
    );
  gen_cmd_1_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(1, 15)
    );
  gen_cmd_1_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(1, 16)
    );
  gen_cmd_1_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(1, 17)
    );
  gen_cmd_1_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(1, 18)
    );
  gen_cmd_1_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(1, 19)
    );
  gen_cmd_1_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(1, 20)
    );
  gen_cmd_1_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(1, 21)
    );
  gen_cmd_1_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(1, 22)
    );
  gen_cmd_1_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(1, 23)
    );
  gen_cmd_1_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(1, 24)
    );
  gen_cmd_1_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(1, 25)
    );
  gen_cmd_1_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(1, 26)
    );
  gen_cmd_1_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(1, 27)
    );
  gen_cmd_1_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(1, 28)
    );
  gen_cmd_1_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(1, 29)
    );
  gen_cmd_1_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(1, 30)
    );
  gen_cmd_1_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(1, 31)
    );
  gen_cmd_1_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(1, 32)
    );
  gen_cmd_1_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(1, 33)
    );
  gen_cmd_1_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(1, 34)
    );
  gen_cmd_1_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(1, 35)
    );
  gen_cmd_1_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(1, 36)
    );
  gen_cmd_1_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(1, 37)
    );
  gen_cmd_1_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(1, 38)
    );
  gen_cmd_1_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(1, 39)
    );
  gen_cmd_1_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(1, 40)
    );
  gen_cmd_1_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(1, 41)
    );
  gen_cmd_1_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(1, 42)
    );
  gen_cmd_1_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(1, 43)
    );
  gen_cmd_1_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(1, 44)
    );
  gen_cmd_1_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(1, 45)
    );
  gen_cmd_1_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(1, 46)
    );
  gen_cmd_1_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(1, 47)
    );
  gen_cmd_1_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(1, 48)
    );
  gen_cmd_1_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(1, 49)
    );
  gen_cmd_1_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(1, 50)
    );
  gen_cmd_1_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(1, 51)
    );
  gen_cmd_1_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(1, 52)
    );
  gen_cmd_1_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(1, 53)
    );
  gen_cmd_1_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(1, 54)
    );
  gen_cmd_1_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(1, 55)
    );
  gen_cmd_1_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(1, 56)
    );
  gen_cmd_1_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(1, 57)
    );
  gen_cmd_1_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(1, 58)
    );
  gen_cmd_1_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(1, 59)
    );
  gen_cmd_1_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(1, 60)
    );
  gen_cmd_1_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(1, 61)
    );
  gen_cmd_1_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(1, 62)
    );
  gen_cmd_1_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(1, 63)
    );
  gen_cmd_2_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(2, 0)
    );
  gen_cmd_2_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(2, 1)
    );
  gen_cmd_2_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(2, 2)
    );
  gen_cmd_2_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(2, 3)
    );
  gen_cmd_2_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(2, 4)
    );
  gen_cmd_2_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(2, 5)
    );
  gen_cmd_2_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(2, 6)
    );
  gen_cmd_2_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(2, 7)
    );
  gen_cmd_2_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(2, 8)
    );
  gen_cmd_2_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(2, 9)
    );
  gen_cmd_2_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(2, 10)
    );
  gen_cmd_2_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(2, 11)
    );
  gen_cmd_2_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(2, 12)
    );
  gen_cmd_2_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(2, 13)
    );
  gen_cmd_2_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(2, 14)
    );
  gen_cmd_2_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(2, 15)
    );
  gen_cmd_2_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(2, 16)
    );
  gen_cmd_2_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(2, 17)
    );
  gen_cmd_2_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(2, 18)
    );
  gen_cmd_2_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(2, 19)
    );
  gen_cmd_2_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(2, 20)
    );
  gen_cmd_2_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(2, 21)
    );
  gen_cmd_2_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(2, 22)
    );
  gen_cmd_2_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(2, 23)
    );
  gen_cmd_2_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(2, 24)
    );
  gen_cmd_2_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(2, 25)
    );
  gen_cmd_2_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(2, 26)
    );
  gen_cmd_2_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(2, 27)
    );
  gen_cmd_2_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(2, 28)
    );
  gen_cmd_2_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(2, 29)
    );
  gen_cmd_2_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(2, 30)
    );
  gen_cmd_2_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(2, 31)
    );
  gen_cmd_2_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(2, 32)
    );
  gen_cmd_2_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(2, 33)
    );
  gen_cmd_2_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(2, 34)
    );
  gen_cmd_2_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(2, 35)
    );
  gen_cmd_2_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(2, 36)
    );
  gen_cmd_2_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(2, 37)
    );
  gen_cmd_2_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(2, 38)
    );
  gen_cmd_2_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(2, 39)
    );
  gen_cmd_2_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(2, 40)
    );
  gen_cmd_2_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(2, 41)
    );
  gen_cmd_2_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(2, 42)
    );
  gen_cmd_2_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(2, 43)
    );
  gen_cmd_2_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(2, 44)
    );
  gen_cmd_2_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(2, 45)
    );
  gen_cmd_2_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(2, 46)
    );
  gen_cmd_2_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(2, 47)
    );
  gen_cmd_2_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(2, 48)
    );
  gen_cmd_2_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(2, 49)
    );
  gen_cmd_2_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(2, 50)
    );
  gen_cmd_2_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(2, 51)
    );
  gen_cmd_2_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(2, 52)
    );
  gen_cmd_2_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(2, 53)
    );
  gen_cmd_2_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(2, 54)
    );
  gen_cmd_2_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(2, 55)
    );
  gen_cmd_2_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(2, 56)
    );
  gen_cmd_2_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(2, 57)
    );
  gen_cmd_2_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(2, 58)
    );
  gen_cmd_2_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(2, 59)
    );
  gen_cmd_2_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(2, 60)
    );
  gen_cmd_2_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(2, 61)
    );
  gen_cmd_2_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(2, 62)
    );
  gen_cmd_2_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(2, 63)
    );
  gen_cmd_3_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(3, 0)
    );
  gen_cmd_3_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(3, 1)
    );
  gen_cmd_3_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(3, 2)
    );
  gen_cmd_3_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(3, 3)
    );
  gen_cmd_3_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(3, 4)
    );
  gen_cmd_3_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(3, 5)
    );
  gen_cmd_3_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(3, 6)
    );
  gen_cmd_3_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(3, 7)
    );
  gen_cmd_3_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(3, 8)
    );
  gen_cmd_3_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(3, 9)
    );
  gen_cmd_3_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(3, 10)
    );
  gen_cmd_3_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(3, 11)
    );
  gen_cmd_3_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(3, 12)
    );
  gen_cmd_3_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(3, 13)
    );
  gen_cmd_3_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(3, 14)
    );
  gen_cmd_3_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(3, 15)
    );
  gen_cmd_3_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(3, 16)
    );
  gen_cmd_3_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(3, 17)
    );
  gen_cmd_3_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(3, 18)
    );
  gen_cmd_3_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(3, 19)
    );
  gen_cmd_3_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(3, 20)
    );
  gen_cmd_3_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(3, 21)
    );
  gen_cmd_3_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(3, 22)
    );
  gen_cmd_3_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(3, 23)
    );
  gen_cmd_3_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(3, 24)
    );
  gen_cmd_3_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(3, 25)
    );
  gen_cmd_3_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(3, 26)
    );
  gen_cmd_3_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(3, 27)
    );
  gen_cmd_3_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(3, 28)
    );
  gen_cmd_3_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(3, 29)
    );
  gen_cmd_3_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(3, 30)
    );
  gen_cmd_3_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(3, 31)
    );
  gen_cmd_3_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(3, 32)
    );
  gen_cmd_3_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(3, 33)
    );
  gen_cmd_3_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(3, 34)
    );
  gen_cmd_3_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(3, 35)
    );
  gen_cmd_3_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(3, 36)
    );
  gen_cmd_3_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(3, 37)
    );
  gen_cmd_3_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(3, 38)
    );
  gen_cmd_3_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(3, 39)
    );
  gen_cmd_3_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(3, 40)
    );
  gen_cmd_3_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(3, 41)
    );
  gen_cmd_3_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(3, 42)
    );
  gen_cmd_3_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(3, 43)
    );
  gen_cmd_3_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(3, 44)
    );
  gen_cmd_3_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(3, 45)
    );
  gen_cmd_3_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(3, 46)
    );
  gen_cmd_3_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(3, 47)
    );
  gen_cmd_3_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(3, 48)
    );
  gen_cmd_3_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(3, 49)
    );
  gen_cmd_3_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(3, 50)
    );
  gen_cmd_3_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(3, 51)
    );
  gen_cmd_3_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(3, 52)
    );
  gen_cmd_3_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(3, 53)
    );
  gen_cmd_3_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(3, 54)
    );
  gen_cmd_3_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(3, 55)
    );
  gen_cmd_3_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(3, 56)
    );
  gen_cmd_3_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(3, 57)
    );
  gen_cmd_3_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(3, 58)
    );
  gen_cmd_3_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(3, 59)
    );
  gen_cmd_3_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(3, 60)
    );
  gen_cmd_3_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(3, 61)
    );
  gen_cmd_3_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(3, 62)
    );
  gen_cmd_3_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(3, 63)
    );
  gen_cmd_4_gen_data_t4_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(0),
      Q => trd_host_data(4, 0)
    );
  gen_cmd_4_gen_data_t4_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(1),
      Q => trd_host_data(4, 1)
    );
  gen_cmd_4_gen_data_t4_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(2),
      Q => trd_host_data(4, 2)
    );
  gen_cmd_4_gen_data_t4_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(3),
      Q => trd_host_data(4, 3)
    );
  gen_cmd_4_gen_data_t4_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(4),
      Q => trd_host_data(4, 4)
    );
  gen_cmd_4_gen_data_t4_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(5),
      Q => trd_host_data(4, 5)
    );
  gen_cmd_4_gen_data_t4_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(6),
      Q => trd_host_data(4, 6)
    );
  gen_cmd_4_gen_data_t4_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(7),
      Q => trd_host_data(4, 7)
    );
  gen_cmd_4_gen_data_t4_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(8),
      Q => trd_host_data(4, 8)
    );
  gen_cmd_4_gen_data_t4_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(9),
      Q => trd_host_data(4, 9)
    );
  gen_cmd_4_gen_data_t4_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(10),
      Q => trd_host_data(4, 10)
    );
  gen_cmd_4_gen_data_t4_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(11),
      Q => trd_host_data(4, 11)
    );
  gen_cmd_4_gen_data_t4_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(12),
      Q => trd_host_data(4, 12)
    );
  gen_cmd_4_gen_data_t4_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(13),
      Q => trd_host_data(4, 13)
    );
  gen_cmd_4_gen_data_t4_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(14),
      Q => trd_host_data(4, 14)
    );
  gen_cmd_4_gen_data_t4_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(15),
      Q => trd_host_data(4, 15)
    );
  gen_cmd_4_gen_data_t4_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(16),
      Q => trd_host_data(4, 16)
    );
  gen_cmd_4_gen_data_t4_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(17),
      Q => trd_host_data(4, 17)
    );
  gen_cmd_4_gen_data_t4_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(18),
      Q => trd_host_data(4, 18)
    );
  gen_cmd_4_gen_data_t4_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(19),
      Q => trd_host_data(4, 19)
    );
  gen_cmd_4_gen_data_t4_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(20),
      Q => trd_host_data(4, 20)
    );
  gen_cmd_4_gen_data_t4_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(21),
      Q => trd_host_data(4, 21)
    );
  gen_cmd_4_gen_data_t4_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(22),
      Q => trd_host_data(4, 22)
    );
  gen_cmd_4_gen_data_t4_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(23),
      Q => trd_host_data(4, 23)
    );
  gen_cmd_4_gen_data_t4_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(24),
      Q => trd_host_data(4, 24)
    );
  gen_cmd_4_gen_data_t4_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(25),
      Q => trd_host_data(4, 25)
    );
  gen_cmd_4_gen_data_t4_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(26),
      Q => trd_host_data(4, 26)
    );
  gen_cmd_4_gen_data_t4_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(27),
      Q => trd_host_data(4, 27)
    );
  gen_cmd_4_gen_data_t4_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(28),
      Q => trd_host_data(4, 28)
    );
  gen_cmd_4_gen_data_t4_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(29),
      Q => trd_host_data(4, 29)
    );
  gen_cmd_4_gen_data_t4_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(30),
      Q => trd_host_data(4, 30)
    );
  gen_cmd_4_gen_data_t4_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(31),
      Q => trd_host_data(4, 31)
    );
  gen_cmd_4_gen_data_t4_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(32),
      Q => trd_host_data(4, 32)
    );
  gen_cmd_4_gen_data_t4_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(33),
      Q => trd_host_data(4, 33)
    );
  gen_cmd_4_gen_data_t4_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(34),
      Q => trd_host_data(4, 34)
    );
  gen_cmd_4_gen_data_t4_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(35),
      Q => trd_host_data(4, 35)
    );
  gen_cmd_4_gen_data_t4_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(36),
      Q => trd_host_data(4, 36)
    );
  gen_cmd_4_gen_data_t4_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(37),
      Q => trd_host_data(4, 37)
    );
  gen_cmd_4_gen_data_t4_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(38),
      Q => trd_host_data(4, 38)
    );
  gen_cmd_4_gen_data_t4_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(39),
      Q => trd_host_data(4, 39)
    );
  gen_cmd_4_gen_data_t4_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(40),
      Q => trd_host_data(4, 40)
    );
  gen_cmd_4_gen_data_t4_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(41),
      Q => trd_host_data(4, 41)
    );
  gen_cmd_4_gen_data_t4_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(42),
      Q => trd_host_data(4, 42)
    );
  gen_cmd_4_gen_data_t4_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(43),
      Q => trd_host_data(4, 43)
    );
  gen_cmd_4_gen_data_t4_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(44),
      Q => trd_host_data(4, 44)
    );
  gen_cmd_4_gen_data_t4_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(45),
      Q => trd_host_data(4, 45)
    );
  gen_cmd_4_gen_data_t4_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(46),
      Q => trd_host_data(4, 46)
    );
  gen_cmd_4_gen_data_t4_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(47),
      Q => trd_host_data(4, 47)
    );
  gen_cmd_4_gen_data_t4_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(48),
      Q => trd_host_data(4, 48)
    );
  gen_cmd_4_gen_data_t4_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(49),
      Q => trd_host_data(4, 49)
    );
  gen_cmd_4_gen_data_t4_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(50),
      Q => trd_host_data(4, 50)
    );
  gen_cmd_4_gen_data_t4_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(51),
      Q => trd_host_data(4, 51)
    );
  gen_cmd_4_gen_data_t4_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(52),
      Q => trd_host_data(4, 52)
    );
  gen_cmd_4_gen_data_t4_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(53),
      Q => trd_host_data(4, 53)
    );
  gen_cmd_4_gen_data_t4_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(54),
      Q => trd_host_data(4, 54)
    );
  gen_cmd_4_gen_data_t4_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(55),
      Q => trd_host_data(4, 55)
    );
  gen_cmd_4_gen_data_t4_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(56),
      Q => trd_host_data(4, 56)
    );
  gen_cmd_4_gen_data_t4_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(57),
      Q => trd_host_data(4, 57)
    );
  gen_cmd_4_gen_data_t4_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(58),
      Q => trd_host_data(4, 58)
    );
  gen_cmd_4_gen_data_t4_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(59),
      Q => trd_host_data(4, 59)
    );
  gen_cmd_4_gen_data_t4_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(60),
      Q => trd_host_data(4, 60)
    );
  gen_cmd_4_gen_data_t4_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(61),
      Q => trd_host_data(4, 61)
    );
  gen_cmd_4_gen_data_t4_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(62),
      Q => trd_host_data(4, 62)
    );
  gen_cmd_4_gen_data_t4_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trd4_host_data(63),
      Q => trd_host_data(4, 63)
    );
  gen_cmd_5_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(5, 0)
    );
  gen_cmd_5_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(5, 1)
    );
  gen_cmd_5_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(5, 2)
    );
  gen_cmd_5_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(5, 3)
    );
  gen_cmd_5_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(5, 4)
    );
  gen_cmd_5_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(5, 5)
    );
  gen_cmd_5_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(5, 6)
    );
  gen_cmd_5_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(5, 7)
    );
  gen_cmd_5_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(5, 8)
    );
  gen_cmd_5_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(5, 9)
    );
  gen_cmd_5_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(5, 10)
    );
  gen_cmd_5_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(5, 11)
    );
  gen_cmd_5_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(5, 12)
    );
  gen_cmd_5_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(5, 13)
    );
  gen_cmd_5_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(5, 14)
    );
  gen_cmd_5_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(5, 15)
    );
  gen_cmd_5_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(5, 16)
    );
  gen_cmd_5_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(5, 17)
    );
  gen_cmd_5_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(5, 18)
    );
  gen_cmd_5_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(5, 19)
    );
  gen_cmd_5_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(5, 20)
    );
  gen_cmd_5_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(5, 21)
    );
  gen_cmd_5_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(5, 22)
    );
  gen_cmd_5_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(5, 23)
    );
  gen_cmd_5_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(5, 24)
    );
  gen_cmd_5_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(5, 25)
    );
  gen_cmd_5_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(5, 26)
    );
  gen_cmd_5_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(5, 27)
    );
  gen_cmd_5_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(5, 28)
    );
  gen_cmd_5_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(5, 29)
    );
  gen_cmd_5_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(5, 30)
    );
  gen_cmd_5_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(5, 31)
    );
  gen_cmd_5_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(5, 32)
    );
  gen_cmd_5_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(5, 33)
    );
  gen_cmd_5_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(5, 34)
    );
  gen_cmd_5_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(5, 35)
    );
  gen_cmd_5_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(5, 36)
    );
  gen_cmd_5_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(5, 37)
    );
  gen_cmd_5_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(5, 38)
    );
  gen_cmd_5_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(5, 39)
    );
  gen_cmd_5_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(5, 40)
    );
  gen_cmd_5_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(5, 41)
    );
  gen_cmd_5_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(5, 42)
    );
  gen_cmd_5_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(5, 43)
    );
  gen_cmd_5_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(5, 44)
    );
  gen_cmd_5_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(5, 45)
    );
  gen_cmd_5_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(5, 46)
    );
  gen_cmd_5_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(5, 47)
    );
  gen_cmd_5_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(5, 48)
    );
  gen_cmd_5_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(5, 49)
    );
  gen_cmd_5_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(5, 50)
    );
  gen_cmd_5_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(5, 51)
    );
  gen_cmd_5_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(5, 52)
    );
  gen_cmd_5_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(5, 53)
    );
  gen_cmd_5_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(5, 54)
    );
  gen_cmd_5_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(5, 55)
    );
  gen_cmd_5_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(5, 56)
    );
  gen_cmd_5_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(5, 57)
    );
  gen_cmd_5_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(5, 58)
    );
  gen_cmd_5_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(5, 59)
    );
  gen_cmd_5_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(5, 60)
    );
  gen_cmd_5_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(5, 61)
    );
  gen_cmd_5_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(5, 62)
    );
  gen_cmd_5_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(5, 63)
    );
  gen_cmd_6_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(6, 0)
    );
  gen_cmd_6_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(6, 1)
    );
  gen_cmd_6_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(6, 2)
    );
  gen_cmd_6_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(6, 3)
    );
  gen_cmd_6_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(6, 4)
    );
  gen_cmd_6_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(6, 5)
    );
  gen_cmd_6_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(6, 6)
    );
  gen_cmd_6_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(6, 7)
    );
  gen_cmd_6_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(6, 8)
    );
  gen_cmd_6_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(6, 9)
    );
  gen_cmd_6_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(6, 10)
    );
  gen_cmd_6_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(6, 11)
    );
  gen_cmd_6_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(6, 12)
    );
  gen_cmd_6_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(6, 13)
    );
  gen_cmd_6_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(6, 14)
    );
  gen_cmd_6_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(6, 15)
    );
  gen_cmd_6_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(6, 16)
    );
  gen_cmd_6_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(6, 17)
    );
  gen_cmd_6_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(6, 18)
    );
  gen_cmd_6_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(6, 19)
    );
  gen_cmd_6_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(6, 20)
    );
  gen_cmd_6_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(6, 21)
    );
  gen_cmd_6_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(6, 22)
    );
  gen_cmd_6_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(6, 23)
    );
  gen_cmd_6_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(6, 24)
    );
  gen_cmd_6_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(6, 25)
    );
  gen_cmd_6_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(6, 26)
    );
  gen_cmd_6_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(6, 27)
    );
  gen_cmd_6_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(6, 28)
    );
  gen_cmd_6_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(6, 29)
    );
  gen_cmd_6_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(6, 30)
    );
  gen_cmd_6_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(6, 31)
    );
  gen_cmd_6_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(6, 32)
    );
  gen_cmd_6_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(6, 33)
    );
  gen_cmd_6_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(6, 34)
    );
  gen_cmd_6_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(6, 35)
    );
  gen_cmd_6_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(6, 36)
    );
  gen_cmd_6_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(6, 37)
    );
  gen_cmd_6_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(6, 38)
    );
  gen_cmd_6_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(6, 39)
    );
  gen_cmd_6_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(6, 40)
    );
  gen_cmd_6_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(6, 41)
    );
  gen_cmd_6_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(6, 42)
    );
  gen_cmd_6_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(6, 43)
    );
  gen_cmd_6_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(6, 44)
    );
  gen_cmd_6_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(6, 45)
    );
  gen_cmd_6_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(6, 46)
    );
  gen_cmd_6_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(6, 47)
    );
  gen_cmd_6_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(6, 48)
    );
  gen_cmd_6_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(6, 49)
    );
  gen_cmd_6_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(6, 50)
    );
  gen_cmd_6_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(6, 51)
    );
  gen_cmd_6_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(6, 52)
    );
  gen_cmd_6_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(6, 53)
    );
  gen_cmd_6_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(6, 54)
    );
  gen_cmd_6_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(6, 55)
    );
  gen_cmd_6_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(6, 56)
    );
  gen_cmd_6_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(6, 57)
    );
  gen_cmd_6_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(6, 58)
    );
  gen_cmd_6_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(6, 59)
    );
  gen_cmd_6_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(6, 60)
    );
  gen_cmd_6_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(6, 61)
    );
  gen_cmd_6_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(6, 62)
    );
  gen_cmd_6_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(6, 63)
    );
  gen_cmd_7_gen_data_gen_bus_0_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(0),
      Q => trd_host_data(7, 0)
    );
  gen_cmd_7_gen_data_gen_bus_1_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(1),
      Q => trd_host_data(7, 1)
    );
  gen_cmd_7_gen_data_gen_bus_2_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(2),
      Q => trd_host_data(7, 2)
    );
  gen_cmd_7_gen_data_gen_bus_3_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(3),
      Q => trd_host_data(7, 3)
    );
  gen_cmd_7_gen_data_gen_bus_4_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(4),
      Q => trd_host_data(7, 4)
    );
  gen_cmd_7_gen_data_gen_bus_5_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(5),
      Q => trd_host_data(7, 5)
    );
  gen_cmd_7_gen_data_gen_bus_6_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(6),
      Q => trd_host_data(7, 6)
    );
  gen_cmd_7_gen_data_gen_bus_7_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(7),
      Q => trd_host_data(7, 7)
    );
  gen_cmd_7_gen_data_gen_bus_8_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(8),
      Q => trd_host_data(7, 8)
    );
  gen_cmd_7_gen_data_gen_bus_9_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(9),
      Q => trd_host_data(7, 9)
    );
  gen_cmd_7_gen_data_gen_bus_10_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(10),
      Q => trd_host_data(7, 10)
    );
  gen_cmd_7_gen_data_gen_bus_11_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(11),
      Q => trd_host_data(7, 11)
    );
  gen_cmd_7_gen_data_gen_bus_12_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(12),
      Q => trd_host_data(7, 12)
    );
  gen_cmd_7_gen_data_gen_bus_13_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(13),
      Q => trd_host_data(7, 13)
    );
  gen_cmd_7_gen_data_gen_bus_14_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(14),
      Q => trd_host_data(7, 14)
    );
  gen_cmd_7_gen_data_gen_bus_15_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(15),
      Q => trd_host_data(7, 15)
    );
  gen_cmd_7_gen_data_gen_bus_16_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(16),
      Q => trd_host_data(7, 16)
    );
  gen_cmd_7_gen_data_gen_bus_17_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(17),
      Q => trd_host_data(7, 17)
    );
  gen_cmd_7_gen_data_gen_bus_18_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(18),
      Q => trd_host_data(7, 18)
    );
  gen_cmd_7_gen_data_gen_bus_19_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(19),
      Q => trd_host_data(7, 19)
    );
  gen_cmd_7_gen_data_gen_bus_20_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(20),
      Q => trd_host_data(7, 20)
    );
  gen_cmd_7_gen_data_gen_bus_21_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(21),
      Q => trd_host_data(7, 21)
    );
  gen_cmd_7_gen_data_gen_bus_22_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(22),
      Q => trd_host_data(7, 22)
    );
  gen_cmd_7_gen_data_gen_bus_23_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(23),
      Q => trd_host_data(7, 23)
    );
  gen_cmd_7_gen_data_gen_bus_24_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(24),
      Q => trd_host_data(7, 24)
    );
  gen_cmd_7_gen_data_gen_bus_25_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(25),
      Q => trd_host_data(7, 25)
    );
  gen_cmd_7_gen_data_gen_bus_26_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(26),
      Q => trd_host_data(7, 26)
    );
  gen_cmd_7_gen_data_gen_bus_27_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(27),
      Q => trd_host_data(7, 27)
    );
  gen_cmd_7_gen_data_gen_bus_28_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(28),
      Q => trd_host_data(7, 28)
    );
  gen_cmd_7_gen_data_gen_bus_29_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(29),
      Q => trd_host_data(7, 29)
    );
  gen_cmd_7_gen_data_gen_bus_30_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(30),
      Q => trd_host_data(7, 30)
    );
  gen_cmd_7_gen_data_gen_bus_31_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(31),
      Q => trd_host_data(7, 31)
    );
  gen_cmd_7_gen_data_gen_bus_32_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(32),
      Q => trd_host_data(7, 32)
    );
  gen_cmd_7_gen_data_gen_bus_33_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(33),
      Q => trd_host_data(7, 33)
    );
  gen_cmd_7_gen_data_gen_bus_34_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(34),
      Q => trd_host_data(7, 34)
    );
  gen_cmd_7_gen_data_gen_bus_35_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(35),
      Q => trd_host_data(7, 35)
    );
  gen_cmd_7_gen_data_gen_bus_36_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(36),
      Q => trd_host_data(7, 36)
    );
  gen_cmd_7_gen_data_gen_bus_37_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(37),
      Q => trd_host_data(7, 37)
    );
  gen_cmd_7_gen_data_gen_bus_38_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(38),
      Q => trd_host_data(7, 38)
    );
  gen_cmd_7_gen_data_gen_bus_39_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(39),
      Q => trd_host_data(7, 39)
    );
  gen_cmd_7_gen_data_gen_bus_40_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(40),
      Q => trd_host_data(7, 40)
    );
  gen_cmd_7_gen_data_gen_bus_41_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(41),
      Q => trd_host_data(7, 41)
    );
  gen_cmd_7_gen_data_gen_bus_42_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(42),
      Q => trd_host_data(7, 42)
    );
  gen_cmd_7_gen_data_gen_bus_43_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(43),
      Q => trd_host_data(7, 43)
    );
  gen_cmd_7_gen_data_gen_bus_44_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(44),
      Q => trd_host_data(7, 44)
    );
  gen_cmd_7_gen_data_gen_bus_45_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(45),
      Q => trd_host_data(7, 45)
    );
  gen_cmd_7_gen_data_gen_bus_46_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(46),
      Q => trd_host_data(7, 46)
    );
  gen_cmd_7_gen_data_gen_bus_47_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(47),
      Q => trd_host_data(7, 47)
    );
  gen_cmd_7_gen_data_gen_bus_48_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(48),
      Q => trd_host_data(7, 48)
    );
  gen_cmd_7_gen_data_gen_bus_49_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(49),
      Q => trd_host_data(7, 49)
    );
  gen_cmd_7_gen_data_gen_bus_50_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(50),
      Q => trd_host_data(7, 50)
    );
  gen_cmd_7_gen_data_gen_bus_51_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(51),
      Q => trd_host_data(7, 51)
    );
  gen_cmd_7_gen_data_gen_bus_52_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(52),
      Q => trd_host_data(7, 52)
    );
  gen_cmd_7_gen_data_gen_bus_53_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(53),
      Q => trd_host_data(7, 53)
    );
  gen_cmd_7_gen_data_gen_bus_54_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(54),
      Q => trd_host_data(7, 54)
    );
  gen_cmd_7_gen_data_gen_bus_55_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(55),
      Q => trd_host_data(7, 55)
    );
  gen_cmd_7_gen_data_gen_bus_56_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(56),
      Q => trd_host_data(7, 56)
    );
  gen_cmd_7_gen_data_gen_bus_57_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(57),
      Q => trd_host_data(7, 57)
    );
  gen_cmd_7_gen_data_gen_bus_58_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(58),
      Q => trd_host_data(7, 58)
    );
  gen_cmd_7_gen_data_gen_bus_59_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(59),
      Q => trd_host_data(7, 59)
    );
  gen_cmd_7_gen_data_gen_bus_60_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(60),
      Q => trd_host_data(7, 60)
    );
  gen_cmd_7_gen_data_gen_bus_61_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(61),
      Q => trd_host_data(7, 61)
    );
  gen_cmd_7_gen_data_gen_bus_62_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(62),
      Q => trd_host_data(7, 62)
    );
  gen_cmd_7_gen_data_gen_bus_63_xfd : FD
    generic map(
      INIT => '0'
    )
    port map (
      C => NlwRenamedSig_OI_clk,
      D => trdi_host_data(63),
      Q => trd_host_data(7, 63)
    );
  xclk200 : BUFG
    port map (
      I => NlwRenamedSig_OI_trd_host_cmd_data(8, 0),
      O => clk200_out
    );
  gen_syn_xmgtclk : IBUFDS
    generic map(
      CAPACITANCE => "DONT_CARE",
      DIFF_TERM => FALSE,
      IBUF_DELAY_VALUE => "0",
      IBUF_LOW_PWR => TRUE,
      IFD_DELAY_VALUE => "AUTO",
      IOSTANDARD => "DEFAULT"
    )
    port map (
      I => mgt251_p,
      IB => mgt251_n,
      O => mgt250
    );
  gen_syn_xmperst : IBUF
    generic map(
      CAPACITANCE => "DONT_CARE",
      IBUF_DELAY_VALUE => "0",
      IBUF_LOW_PWR => TRUE,
      IFD_DELAY_VALUE => "AUTO",
      IOSTANDARD => "DEFAULT"
    )
    port map (
      I => bperst,
      O => perst
    );
  xcnt0 : SRLC32E
    generic map(
      INIT => X"00000000"
    )
    port map (
      CLK => NlwRenamedSig_OI_clk,
      D => cnt30i0,
      CE => NlwRenamedSig_OI_clk_lock_out,
      Q => NLW_xcnt0_Q_UNCONNECTED,
      Q31 => cnt30k0,
      A(4) => NlwRenamedSig_OI_clk_lock_out,
      A(3) => NlwRenamedSig_OI_clk_lock_out,
      A(2) => NlwRenamedSig_OI_clk_lock_out,
      A(1) => NlwRenamedSig_OI_clk_lock_out,
      A(0) => NlwRenamedSig_OI_clk_lock_out
    );
  xcnt1 : SRLC32E
    generic map(
      INIT => X"00000000"
    )
    port map (
      CLK => NlwRenamedSig_OI_clk,
      D => cnt30i1,
      CE => cnt30ce1,
      Q => NLW_xcnt1_Q_UNCONNECTED,
      Q31 => cnt30k1,
      A(4) => NlwRenamedSig_OI_clk_lock_out,
      A(3) => NlwRenamedSig_OI_clk_lock_out,
      A(2) => NlwRenamedSig_OI_clk_lock_out,
      A(1) => NlwRenamedSig_OI_clk_lock_out,
      A(0) => NlwRenamedSig_OI_clk_lock_out
    );
  xcnt2 : SRLC32E
    generic map(
      INIT => X"00000000"
    )
    port map (
      CLK => NlwRenamedSig_OI_clk,
      D => cnt30i2,
      CE => cnt30ce2,
      Q => NlwRenamedSig_OI_clk30k,
      Q31 => NLW_xcnt2_Q31_UNCONNECTED,
      A(4) => NlwRenamedSig_OI_trd_host_cmd_data(8, 0),
      A(3) => NlwRenamedSig_OI_clk_lock_out,
      A(2) => NlwRenamedSig_OI_trd_host_cmd_data(8, 0),
      A(1) => NlwRenamedSig_OI_trd_host_cmd_data(8, 0),
      A(0) => NlwRenamedSig_OI_clk_lock_out
    );
  gen_syn_blink : ctrl_blink
    port map (
      clk => NlwRenamedSig_OI_clk,
      reset => NlwRenamedSig_OI_led_h4,
      led_h1 => led_h1,
      pcie_link_up => pcie_link_up,
      clk30k => NlwRenamedSig_OI_clk30k,
      pcie_lstatus(15) => pcie_lstatus(15),
      pcie_lstatus(14) => pcie_lstatus(14),
      pcie_lstatus(13) => pcie_lstatus(13),
      pcie_lstatus(12) => pcie_lstatus(12),
      pcie_lstatus(11) => pcie_lstatus(11),
      pcie_lstatus(10) => pcie_lstatus(10),
      pcie_lstatus(9) => pcie_lstatus(9),
      pcie_lstatus(8) => pcie_lstatus(8),
      pcie_lstatus(7) => pcie_lstatus(7),
      pcie_lstatus(6) => pcie_lstatus(6),
      pcie_lstatus(5) => pcie_lstatus(5),
      pcie_lstatus(4) => pcie_lstatus(4),
      pcie_lstatus(3) => pcie_lstatus(3),
      pcie_lstatus(2) => pcie_lstatus(2),
      pcie_lstatus(1) => pcie_lstatus(1),
      pcie_lstatus(0) => pcie_lstatus(0)
    );
  gen_syn_ad : pb_adm_ctrl_m2
    port map (
      trd_host_cmd_11_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_11_cmd_data_we_UNCONNECTED,
      trd_host_cmd_13_data_oe => NLW_gen_syn_ad_trd_host_cmd_13_data_oe_UNCONNECTED,
      trd_host_cmd_6_cmd_data_cs => trd_host_cmd_6_cmd_data_cs,
      trd_drq_14_req => trd_drq_14_req,
      trd_drq_14_en => trd_drq_14_en,
      drq1_en => trd_main_drq_1_en,
      trd_host_cmd_5_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_5_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_2_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_2_cmd_data_we_UNCONNECTED,
      trd_host_cmd_9_data_cs => NLW_gen_syn_ad_trd_host_cmd_9_data_cs_UNCONNECTED,
      trd_host_cmd_12_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_12_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_15_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_15_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_2_data_we => NLW_gen_syn_ad_trd_host_cmd_2_data_we_UNCONNECTED,
      trd_drq_15_req => trd_drq_15_req,
      trd_host_cmd_0_data_cs => trd_host_cmd_0_data_cs,
      trd_host_cmd_1_data_oe => NLW_gen_syn_ad_trd_host_cmd_1_data_oe_UNCONNECTED,
      lc_wr => lc_wr,
      drq1_req => trd_main_drq_1_req,
      trd_host_cmd_3_cmd_data_cs => trd_host_cmd_3_cmd_data_cs,
      trd_host_cmd_2_status_cs => trd_host_cmd_2_status_cs,
      trd_host_cmd_13_data_we => NLW_gen_syn_ad_trd_host_cmd_13_data_we_UNCONNECTED,
      trd_host_cmd_11_data_cs => NLW_gen_syn_ad_trd_host_cmd_11_data_cs_UNCONNECTED,
      trd_drq_3_en => trd_drq_3_en,
      trd_drq_0_ack => trd_drq_0_ack,
      trd_host_cmd_12_data_oe => NLW_gen_syn_ad_trd_host_cmd_12_data_oe_UNCONNECTED,
      trd_host_cmd_9_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_9_cmd_data_we_UNCONNECTED,
      trd_host_cmd_8_status_cs => NLW_gen_syn_ad_trd_host_cmd_8_status_cs_UNCONNECTED,
      trd_drq_8_en => trd_drq_8_en,
      trd_host_cmd_11_status_cs => NLW_gen_syn_ad_trd_host_cmd_11_status_cs_UNCONNECTED,
      trd_drq_1_ack => trd_drq_1_ack,
      trd_host_cmd_8_data_cs => NLW_gen_syn_ad_trd_host_cmd_8_data_cs_UNCONNECTED,
      trd_host_cmd_9_data_oe => NLW_gen_syn_ad_trd_host_cmd_9_data_oe_UNCONNECTED,
      trd_host_cmd_4_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_4_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_1_data_we => NLW_gen_syn_ad_trd_host_cmd_1_data_we_UNCONNECTED,
      drq3_ack => trd_main_drq_3_ack,
      trd_drq_2_ack => trd_drq_2_ack,
      trd_host_cmd_0_data_oe => NLW_gen_syn_ad_trd_host_cmd_0_data_oe_UNCONNECTED,
      trd_host_cmd_15_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_15_cmd_data_we_UNCONNECTED,
      trd_host_cmd_14_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_14_cmd_adr_we_UNCONNECTED,
      trd_drq_3_ack => trd_drq_3_ack,
      trd_drq_11_en => trd_drq_11_en,
      trd_host_cmd_0_cmd_data_cs => trd_host_cmd_0_cmd_data_cs,
      trd_host_cmd_12_data_we => NLW_gen_syn_ad_trd_host_cmd_12_data_we_UNCONNECTED,
      trd_host_cmd_10_data_cs => NLW_gen_syn_ad_trd_host_cmd_10_data_cs_UNCONNECTED,
      trd_host_cmd_11_data_oe => NLW_gen_syn_ad_trd_host_cmd_11_data_oe_UNCONNECTED,
      trd_host_cmd_6_cmd_data_we => trdi_host_cmd_6_cmd_data_we,
      trd_drq_4_ack => trd_drq_4_ack,
      trd_drq_0_req => trd_drq_0_req,
      trd_host_cmd_9_data_we => NLW_gen_syn_ad_trd_host_cmd_9_data_we_UNCONNECTED,
      trd_host_cmd_3_status_cs => trd_host_cmd_3_status_cs,
      trd_host_cmd_7_data_cs => trd_host_cmd_7_data_cs,
      trd_host_cmd_12_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_12_cmd_data_we_UNCONNECTED,
      trd_host_cmd_8_data_oe => NLW_gen_syn_ad_trd_host_cmd_8_data_oe_UNCONNECTED,
      trd_drq_5_ack => trd_drq_5_ack,
      trd_drq_1_req => trd_drq_1_req,
      trd_host_cmd_0_data_we => trdi_host_cmd_0_data_we,
      trd_host_cmd_7_cmd_data_cs => trd_host_cmd_7_cmd_data_cs,
      trd_drq_0_en => trd_drq_0_en,
      trd_host_cmd_9_status_cs => NLW_gen_syn_ad_trd_host_cmd_9_status_cs_UNCONNECTED,
      drq3_req => trd_main_drq_3_req,
      trd_host_cmd_3_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_3_cmd_adr_we_UNCONNECTED,
      trd_drq_6_ack => trd_drq_6_ack,
      trd_drq_2_req => trd_drq_2_req,
      trd_host_cmd_12_status_cs => NLW_gen_syn_ad_trd_host_cmd_12_status_cs_UNCONNECTED,
      trd_host_cmd_3_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_3_cmd_data_we_UNCONNECTED,
      trd_drq_5_en => trd_drq_5_en,
      trd_host_cmd_11_data_we => NLW_gen_syn_ad_trd_host_cmd_11_data_we_UNCONNECTED,
      trd_host_cmd_13_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_13_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_10_data_oe => NLW_gen_syn_ad_trd_host_cmd_10_data_oe_UNCONNECTED,
      trd_drq_7_ack => trd_drq_7_ack,
      trd_drq_3_req => trd_drq_3_req,
      dmar0 => dmar0,
      drq0_ack => trd_main_drq_0_ack,
      dmar1 => dmar1,
      drq2_en => trd_main_drq_2_en,
      reset => NlwRenamedSig_OI_led_h4,
      dmar2 => NLW_gen_syn_ad_dmar2_UNCONNECTED,
      trd_host_cmd_13_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_13_cmd_data_cs_UNCONNECTED,
      dmar3 => NLW_gen_syn_ad_dmar3_UNCONNECTED,
      trd_host_cmd_8_data_we => NLW_gen_syn_ad_trd_host_cmd_8_data_we_UNCONNECTED,
      trd_drq_4_req => trd_drq_4_req,
      trd_drq_8_ack => trd_drq_8_ack,
      trd_host_cmd_6_data_cs => trd_host_cmd_6_data_cs,
      trd_host_cmd_7_data_oe => NLW_gen_syn_ad_trd_host_cmd_7_data_oe_UNCONNECTED,
      trd_host_cmd_4_cmd_data_cs => trd_host_cmd_4_cmd_data_cs,
      trd_drq_9_ack => trd_drq_9_ack,
      trd_drq_5_req => trd_drq_5_req,
      trd_drq_13_en => trd_drq_13_en,
      trd_host_cmd_0_cmd_data_we => trdi_host_cmd_0_cmd_data_we,
      trd_host_cmd_4_status_cs => trd_host_cmd_4_status_cs,
      trd_host_cmd_10_data_we => NLW_gen_syn_ad_trd_host_cmd_10_data_we_UNCONNECTED,
      trd_host_cmd_9_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_9_cmd_adr_we_UNCONNECTED,
      trd_drq_6_req => trd_drq_6_req,
      trd_host_cmd_2_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_2_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_12_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_12_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_10_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_10_cmd_data_cs_UNCONNECTED,
      clk => NlwRenamedSig_OI_clk,
      trd_drq_7_req => trd_drq_7_req,
      trd_host_cmd_13_status_cs => NLW_gen_syn_ad_trd_host_cmd_13_status_cs_UNCONNECTED,
      drq0_req => trd_main_drq_0_req,
      trd_host_cmd_7_data_we => trdi_host_cmd_7_data_we,
      trd_host_cmd_5_data_cs => trd_host_cmd_5_data_cs,
      trd_host_cmd_6_data_oe => NLW_gen_syn_ad_trd_host_cmd_6_data_oe_UNCONNECTED,
      trd_drq_2_en => trd_drq_2_en,
      trd_host_cmd_7_cmd_data_we => trdi_host_cmd_7_cmd_data_we,
      trd_drq_8_req => trd_drq_8_req,
      trd_host_cmd_1_cmd_data_cs => trd_host_cmd_1_cmd_data_cs,
      trd_drq_7_en => trd_drq_7_en,
      trd_drq_9_req => trd_drq_9_req,
      drq2_ack => trd_main_drq_2_ack,
      trd_host_cmd_13_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_13_cmd_data_we_UNCONNECTED,
      trd_host_cmd_8_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_8_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_1_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_1_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_8_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_8_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_6_data_we => NLW_gen_syn_ad_trd_host_cmd_6_data_we_UNCONNECTED,
      trd_drq_10_en => trd_drq_10_en,
      trd_host_cmd_4_data_cs => trd_host_cmd_4_data_cs,
      trd_host_cmd_5_status_cs => trd_host_cmd_5_status_cs,
      trd_host_cmd_5_data_oe => NLW_gen_syn_ad_trd_host_cmd_5_data_oe_UNCONNECTED,
      trd_host_cmd_4_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_4_cmd_data_we_UNCONNECTED,
      trd_drq_15_en => trd_drq_15_en,
      trd_host_cmd_11_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_11_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_15_data_cs => NLW_gen_syn_ad_trd_host_cmd_15_data_cs_UNCONNECTED,
      trd_host_cmd_14_status_cs => NLW_gen_syn_ad_trd_host_cmd_14_status_cs_UNCONNECTED,
      trd_host_cmd_14_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_14_cmd_data_cs_UNCONNECTED,
      int1 => trd_main_irq(1),
      drq3_en => trd_main_drq_3_en,
      trd_host_cmd_10_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_10_cmd_data_we_UNCONNECTED,
      drq2_req => trd_main_drq_2_req,
      trd_host_cmd_5_cmd_data_cs => trd_host_cmd_5_cmd_data_cs,
      drq0_en => trd_main_drq_0_en,
      trd_drq_4_en => trd_drq_4_en,
      trd_host_cmd_5_data_we => NLW_gen_syn_ad_trd_host_cmd_5_data_we_UNCONNECTED,
      trd_host_cmd_7_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_7_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_3_data_cs => trd_host_cmd_3_data_cs,
      trd_host_cmd_0_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_0_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_4_data_oe => NLW_gen_syn_ad_trd_host_cmd_4_data_oe_UNCONNECTED,
      test_mode => test_mode,
      trd_host_cmd_1_cmd_data_we => trdi_host_cmd_1_cmd_data_we,
      trd_drq_9_en => trd_drq_9_en,
      trd_host_cmd_0_status_cs => trd_host_cmd_0_status_cs,
      trd_drq_10_ack => trd_drq_10_ack,
      trd_host_cmd_14_data_cs => NLW_gen_syn_ad_trd_host_cmd_14_data_cs_UNCONNECTED,
      trd_host_cmd_15_data_oe => NLW_gen_syn_ad_trd_host_cmd_15_data_oe_UNCONNECTED,
      trd_host_cmd_11_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_11_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_10_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_10_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_6_status_cs => trd_host_cmd_6_status_cs,
      trd_drq_11_ack => trd_drq_11_ack,
      trd_host_cmd_8_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_8_cmd_data_we_UNCONNECTED,
      trd_drq_12_en => trd_drq_12_en,
      trd_host_cmd_2_cmd_data_cs => trd_host_cmd_2_cmd_data_cs,
      trd_drq_12_ack => trd_drq_12_ack,
      trd_host_cmd_15_status_cs => NLW_gen_syn_ad_trd_host_cmd_15_status_cs_UNCONNECTED,
      trd_host_cmd_4_data_we => NLW_gen_syn_ad_trd_host_cmd_4_data_we_UNCONNECTED,
      trd_host_cmd_2_data_cs => trd_host_cmd_2_data_cs,
      trd_host_cmd_3_data_oe => NLW_gen_syn_ad_trd_host_cmd_3_data_oe_UNCONNECTED,
      trd_drq_13_ack => trd_drq_13_ack,
      trd_host_cmd_15_data_we => NLW_gen_syn_ad_trd_host_cmd_15_data_we_UNCONNECTED,
      trd_host_cmd_13_data_cs => NLW_gen_syn_ad_trd_host_cmd_13_data_cs_UNCONNECTED,
      trd_host_cmd_14_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_14_cmd_data_we_UNCONNECTED,
      trd_host_cmd_14_data_oe => NLW_gen_syn_ad_trd_host_cmd_14_data_oe_UNCONNECTED,
      trd_drq_10_req => trd_drq_10_req,
      irq1 => irq1,
      trd_host_cmd_6_cmd_adr_we => NLW_gen_syn_ad_trd_host_cmd_6_cmd_adr_we_UNCONNECTED,
      trd_drq_14_ack => trd_drq_14_ack,
      trd_drq_1_en => trd_drq_1_en,
      trd_host_cmd_9_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_9_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_1_status_cs => trd_host_cmd_1_status_cs,
      trd_drq_11_req => trd_drq_11_req,
      trd_drq_15_ack => trd_drq_15_ack,
      trd_host_cmd_5_cmd_data_we => NLW_gen_syn_ad_trd_host_cmd_5_cmd_data_we_UNCONNECTED,
      trd_drq_6_en => trd_drq_6_en,
      trd_host_cmd_3_data_we => NLW_gen_syn_ad_trd_host_cmd_3_data_we_UNCONNECTED,
      trd_host_cmd_1_data_cs => trd_host_cmd_1_data_cs,
      trd_host_cmd_2_data_oe => NLW_gen_syn_ad_trd_host_cmd_2_data_oe_UNCONNECTED,
      trd_host_cmd_7_status_cs => trd_host_cmd_7_status_cs,
      trd_drq_12_req => trd_drq_12_req,
      drq1_ack => trd_main_drq_1_ack,
      trd_host_cmd_15_cmd_data_cs => NLW_gen_syn_ad_trd_host_cmd_15_cmd_data_cs_UNCONNECTED,
      lc_rd => lc_rd,
      trd_host_cmd_10_status_cs => NLW_gen_syn_ad_trd_host_cmd_10_status_cs_UNCONNECTED,
      trd_host_cmd_14_data_we => NLW_gen_syn_ad_trd_host_cmd_14_data_we_UNCONNECTED,
      trd_drq_13_req => trd_drq_13_req,
      trd_host_cmd_12_data_cs => NLW_gen_syn_ad_trd_host_cmd_12_data_cs_UNCONNECTED,
      trd_host_cmd_5_adr_9_Q => trd_host_cmd_5_adr_9_Q,
      trd_host_cmd_5_adr_8_Q => trd_host_cmd_5_adr_8_Q,
      trd_host_cmd_5_adr_7_Q => trd_host_cmd_5_adr_7_Q,
      trd_host_cmd_5_adr_6_Q => trd_host_cmd_5_adr_6_Q,
      trd_host_cmd_5_adr_5_Q => trd_host_cmd_5_adr_5_Q,
      trd_host_cmd_5_adr_4_Q => trd_host_cmd_5_adr_4_Q,
      trd_host_cmd_5_adr_3_Q => trd_host_cmd_5_adr_3_Q,
      trd_host_cmd_5_adr_2_Q => trd_host_cmd_5_adr_2_Q,
      trd_host_cmd_5_adr_1_Q => trd_host_cmd_5_adr_1_Q,
      trd_host_cmd_5_adr_0_Q => trd_host_cmd_5_adr_0_Q,
      trd_host_cmd_6_adr_9_Q => trd_host_cmd_6_adr_9_Q,
      trd_host_cmd_6_adr_8_Q => trd_host_cmd_6_adr_8_Q,
      trd_host_cmd_6_adr_7_Q => trd_host_cmd_6_adr_7_Q,
      trd_host_cmd_6_adr_6_Q => trd_host_cmd_6_adr_6_Q,
      trd_host_cmd_6_adr_5_Q => trd_host_cmd_6_adr_5_Q,
      trd_host_cmd_6_adr_4_Q => trd_host_cmd_6_adr_4_Q,
      trd_host_cmd_6_adr_3_Q => trd_host_cmd_6_adr_3_Q,
      trd_host_cmd_6_adr_2_Q => trd_host_cmd_6_adr_2_Q,
      trd_host_cmd_6_adr_1_Q => trd_host_cmd_6_adr_1_Q,
      trd_host_cmd_6_adr_0_Q => trd_host_cmd_6_adr_0_Q,
      trd_host_cmd_7_adr_9_Q => trd_host_cmd_7_adr_9_Q,
      trd_host_cmd_7_adr_8_Q => trd_host_cmd_7_adr_8_Q,
      trd_host_cmd_7_adr_7_Q => trd_host_cmd_7_adr_7_Q,
      trd_host_cmd_7_adr_6_Q => trd_host_cmd_7_adr_6_Q,
      trd_host_cmd_7_adr_5_Q => trd_host_cmd_7_adr_5_Q,
      trd_host_cmd_7_adr_4_Q => trd_host_cmd_7_adr_4_Q,
      trd_host_cmd_7_adr_3_Q => trd_host_cmd_7_adr_3_Q,
      trd_host_cmd_7_adr_2_Q => trd_host_cmd_7_adr_2_Q,
      trd_host_cmd_7_adr_1_Q => trd_host_cmd_7_adr_1_Q,
      trd_host_cmd_7_adr_0_Q => trd_host_cmd_7_adr_0_Q,
      trd_host_cmd_8_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_9_UNCONNECTED,
      trd_host_cmd_8_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_8_UNCONNECTED,
      trd_host_cmd_8_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_7_UNCONNECTED,
      trd_host_cmd_8_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_6_UNCONNECTED,
      trd_host_cmd_8_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_5_UNCONNECTED,
      trd_host_cmd_8_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_4_UNCONNECTED,
      trd_host_cmd_8_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_3_UNCONNECTED,
      trd_host_cmd_8_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_2_UNCONNECTED,
      trd_host_cmd_8_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_1_UNCONNECTED,
      trd_host_cmd_8_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_8_adr_0_UNCONNECTED,
      trd_host_cmd_9_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_9_UNCONNECTED,
      trd_host_cmd_9_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_8_UNCONNECTED,
      trd_host_cmd_9_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_7_UNCONNECTED,
      trd_host_cmd_9_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_6_UNCONNECTED,
      trd_host_cmd_9_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_5_UNCONNECTED,
      trd_host_cmd_9_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_4_UNCONNECTED,
      trd_host_cmd_9_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_3_UNCONNECTED,
      trd_host_cmd_9_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_2_UNCONNECTED,
      trd_host_cmd_9_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_1_UNCONNECTED,
      trd_host_cmd_9_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_9_adr_0_UNCONNECTED,
      trd_host_cmd_10_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_9_UNCONNECTED,
      trd_host_cmd_10_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_8_UNCONNECTED,
      trd_host_cmd_10_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_7_UNCONNECTED,
      trd_host_cmd_10_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_6_UNCONNECTED,
      trd_host_cmd_10_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_5_UNCONNECTED,
      trd_host_cmd_10_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_4_UNCONNECTED,
      trd_host_cmd_10_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_3_UNCONNECTED,
      trd_host_cmd_10_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_2_UNCONNECTED,
      trd_host_cmd_10_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_1_UNCONNECTED,
      trd_host_cmd_10_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_10_adr_0_UNCONNECTED,
      trd_host_cmd_11_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_9_UNCONNECTED,
      trd_host_cmd_11_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_8_UNCONNECTED,
      trd_host_cmd_11_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_7_UNCONNECTED,
      trd_host_cmd_11_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_6_UNCONNECTED,
      trd_host_cmd_11_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_5_UNCONNECTED,
      trd_host_cmd_11_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_4_UNCONNECTED,
      trd_host_cmd_11_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_3_UNCONNECTED,
      trd_host_cmd_11_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_2_UNCONNECTED,
      trd_host_cmd_11_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_1_UNCONNECTED,
      trd_host_cmd_11_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_11_adr_0_UNCONNECTED,
      trd_host_cmd_12_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_9_UNCONNECTED,
      trd_host_cmd_12_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_8_UNCONNECTED,
      trd_host_cmd_12_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_7_UNCONNECTED,
      trd_host_cmd_12_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_6_UNCONNECTED,
      trd_host_cmd_12_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_5_UNCONNECTED,
      trd_host_cmd_12_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_4_UNCONNECTED,
      trd_host_cmd_12_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_3_UNCONNECTED,
      trd_host_cmd_12_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_2_UNCONNECTED,
      trd_host_cmd_12_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_1_UNCONNECTED,
      trd_host_cmd_12_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_12_adr_0_UNCONNECTED,
      trd_host_cmd_13_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_9_UNCONNECTED,
      trd_host_cmd_13_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_8_UNCONNECTED,
      trd_host_cmd_13_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_7_UNCONNECTED,
      trd_host_cmd_13_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_6_UNCONNECTED,
      trd_host_cmd_13_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_5_UNCONNECTED,
      trd_host_cmd_13_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_4_UNCONNECTED,
      trd_host_cmd_13_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_3_UNCONNECTED,
      trd_host_cmd_13_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_2_UNCONNECTED,
      trd_host_cmd_13_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_1_UNCONNECTED,
      trd_host_cmd_13_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_13_adr_0_UNCONNECTED,
      trd_host_cmd_14_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_9_UNCONNECTED,
      trd_host_cmd_14_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_8_UNCONNECTED,
      trd_host_cmd_14_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_7_UNCONNECTED,
      trd_host_cmd_14_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_6_UNCONNECTED,
      trd_host_cmd_14_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_5_UNCONNECTED,
      trd_host_cmd_14_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_4_UNCONNECTED,
      trd_host_cmd_14_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_3_UNCONNECTED,
      trd_host_cmd_14_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_2_UNCONNECTED,
      trd_host_cmd_14_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_1_UNCONNECTED,
      trd_host_cmd_14_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_14_adr_0_UNCONNECTED,
      trd_host_cmd_15_adr_9_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_9_UNCONNECTED,
      trd_host_cmd_15_adr_8_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_8_UNCONNECTED,
      trd_host_cmd_15_adr_7_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_7_UNCONNECTED,
      trd_host_cmd_15_adr_6_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_6_UNCONNECTED,
      trd_host_cmd_15_adr_5_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_5_UNCONNECTED,
      trd_host_cmd_15_adr_4_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_4_UNCONNECTED,
      trd_host_cmd_15_adr_3_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_3_UNCONNECTED,
      trd_host_cmd_15_adr_2_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_2_UNCONNECTED,
      trd_host_cmd_15_adr_1_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_1_UNCONNECTED,
      trd_host_cmd_15_adr_0_Q => NLW_gen_syn_ad_trd_host_cmd_15_adr_0_UNCONNECTED,
      trd_host_cmd_0_adr_9_Q => trd_host_cmd_0_adr_9_Q,
      trd_host_cmd_0_adr_8_Q => trd_host_cmd_0_adr_8_Q,
      trd_host_cmd_0_adr_7_Q => trd_host_cmd_0_adr_7_Q,
      trd_host_cmd_0_adr_6_Q => trd_host_cmd_0_adr_6_Q,
      trd_host_cmd_0_adr_5_Q => trd_host_cmd_0_adr_5_Q,
      trd_host_cmd_0_adr_4_Q => trd_host_cmd_0_adr_4_Q,
      trd_host_cmd_0_adr_3_Q => trd_host_cmd_0_adr_3_Q,
      trd_host_cmd_0_adr_2_Q => trd_host_cmd_0_adr_2_Q,
      trd_host_cmd_0_adr_1_Q => trd_host_cmd_0_adr_1_Q,
      trd_host_cmd_0_adr_0_Q => trd_host_cmd_0_adr_0_Q,
      trd_host_cmd_1_adr_9_Q => trd_host_cmd_1_adr_9_Q,
      trd_host_cmd_1_adr_8_Q => trd_host_cmd_1_adr_8_Q,
      trd_host_cmd_1_adr_7_Q => trd_host_cmd_1_adr_7_Q,
      trd_host_cmd_1_adr_6_Q => trd_host_cmd_1_adr_6_Q,
      trd_host_cmd_1_adr_5_Q => trd_host_cmd_1_adr_5_Q,
      trd_host_cmd_1_adr_4_Q => trd_host_cmd_1_adr_4_Q,
      trd_host_cmd_1_adr_3_Q => trd_host_cmd_1_adr_3_Q,
      trd_host_cmd_1_adr_2_Q => trd_host_cmd_1_adr_2_Q,
      trd_host_cmd_1_adr_1_Q => trd_host_cmd_1_adr_1_Q,
      trd_host_cmd_1_adr_0_Q => trd_host_cmd_1_adr_0_Q,
      trd_host_cmd_2_adr_9_Q => trd_host_cmd_2_adr_9_Q,
      trd_host_cmd_2_adr_8_Q => trd_host_cmd_2_adr_8_Q,
      trd_host_cmd_2_adr_7_Q => trd_host_cmd_2_adr_7_Q,
      trd_host_cmd_2_adr_6_Q => trd_host_cmd_2_adr_6_Q,
      trd_host_cmd_2_adr_5_Q => trd_host_cmd_2_adr_5_Q,
      trd_host_cmd_2_adr_4_Q => trd_host_cmd_2_adr_4_Q,
      trd_host_cmd_2_adr_3_Q => trd_host_cmd_2_adr_3_Q,
      trd_host_cmd_2_adr_2_Q => trd_host_cmd_2_adr_2_Q,
      trd_host_cmd_2_adr_1_Q => trd_host_cmd_2_adr_1_Q,
      trd_host_cmd_2_adr_0_Q => trd_host_cmd_2_adr_0_Q,
      trd_host_cmd_3_adr_9_Q => trd_host_cmd_3_adr_9_Q,
      trd_host_cmd_3_adr_8_Q => trd_host_cmd_3_adr_8_Q,
      trd_host_cmd_3_adr_7_Q => trd_host_cmd_3_adr_7_Q,
      trd_host_cmd_3_adr_6_Q => trd_host_cmd_3_adr_6_Q,
      trd_host_cmd_3_adr_5_Q => trd_host_cmd_3_adr_5_Q,
      trd_host_cmd_3_adr_4_Q => trd_host_cmd_3_adr_4_Q,
      trd_host_cmd_3_adr_3_Q => trd_host_cmd_3_adr_3_Q,
      trd_host_cmd_3_adr_2_Q => trd_host_cmd_3_adr_2_Q,
      trd_host_cmd_3_adr_1_Q => trd_host_cmd_3_adr_1_Q,
      trd_host_cmd_3_adr_0_Q => trd_host_cmd_3_adr_0_Q,
      trd_host_cmd_4_adr_9_Q => trd_host_cmd_4_adr_9_Q,
      trd_host_cmd_4_adr_8_Q => trd_host_cmd_4_adr_8_Q,
      trd_host_cmd_4_adr_7_Q => trd_host_cmd_4_adr_7_Q,
      trd_host_cmd_4_adr_6_Q => trd_host_cmd_4_adr_6_Q,
      trd_host_cmd_4_adr_5_Q => trd_host_cmd_4_adr_5_Q,
      trd_host_cmd_4_adr_4_Q => trd_host_cmd_4_adr_4_Q,
      trd_host_cmd_4_adr_3_Q => trd_host_cmd_4_adr_3_Q,
      trd_host_cmd_4_adr_2_Q => trd_host_cmd_4_adr_2_Q,
      trd_host_cmd_4_adr_1_Q => trd_host_cmd_4_adr_1_Q,
      trd_host_cmd_4_adr_0_Q => trd_host_cmd_4_adr_0_Q,
      trd_host_adr(6) => trd_host_adr(6),
      trd_host_adr(5) => trd_host_adr(5),
      trd_host_adr(4) => trd_host_adr(4),
      trd_host_adr(3) => trd_host_adr(3),
      trd_host_adr(2) => trd_host_adr(2),
      trd_host_adr(1) => trd_host_adr(1),
      trd_host_adr(0) => trd_host_adr(0),
      trd4_host_data(63) => trd4_host_data(63),
      trd4_host_data(62) => trd4_host_data(62),
      trd4_host_data(61) => trd4_host_data(61),
      trd4_host_data(60) => trd4_host_data(60),
      trd4_host_data(59) => trd4_host_data(59),
      trd4_host_data(58) => trd4_host_data(58),
      trd4_host_data(57) => trd4_host_data(57),
      trd4_host_data(56) => trd4_host_data(56),
      trd4_host_data(55) => trd4_host_data(55),
      trd4_host_data(54) => trd4_host_data(54),
      trd4_host_data(53) => trd4_host_data(53),
      trd4_host_data(52) => trd4_host_data(52),
      trd4_host_data(51) => trd4_host_data(51),
      trd4_host_data(50) => trd4_host_data(50),
      trd4_host_data(49) => trd4_host_data(49),
      trd4_host_data(48) => trd4_host_data(48),
      trd4_host_data(47) => trd4_host_data(47),
      trd4_host_data(46) => trd4_host_data(46),
      trd4_host_data(45) => trd4_host_data(45),
      trd4_host_data(44) => trd4_host_data(44),
      trd4_host_data(43) => trd4_host_data(43),
      trd4_host_data(42) => trd4_host_data(42),
      trd4_host_data(41) => trd4_host_data(41),
      trd4_host_data(40) => trd4_host_data(40),
      trd4_host_data(39) => trd4_host_data(39),
      trd4_host_data(38) => trd4_host_data(38),
      trd4_host_data(37) => trd4_host_data(37),
      trd4_host_data(36) => trd4_host_data(36),
      trd4_host_data(35) => trd4_host_data(35),
      trd4_host_data(34) => trd4_host_data(34),
      trd4_host_data(33) => trd4_host_data(33),
      trd4_host_data(32) => trd4_host_data(32),
      trd4_host_data(31) => trd4_host_data(31),
      trd4_host_data(30) => trd4_host_data(30),
      trd4_host_data(29) => trd4_host_data(29),
      trd4_host_data(28) => trd4_host_data(28),
      trd4_host_data(27) => trd4_host_data(27),
      trd4_host_data(26) => trd4_host_data(26),
      trd4_host_data(25) => trd4_host_data(25),
      trd4_host_data(24) => trd4_host_data(24),
      trd4_host_data(23) => trd4_host_data(23),
      trd4_host_data(22) => trd4_host_data(22),
      trd4_host_data(21) => trd4_host_data(21),
      trd4_host_data(20) => trd4_host_data(20),
      trd4_host_data(19) => trd4_host_data(19),
      trd4_host_data(18) => trd4_host_data(18),
      trd4_host_data(17) => trd4_host_data(17),
      trd4_host_data(16) => trd4_host_data(16),
      trd4_host_data(15) => trd4_host_data(15),
      trd4_host_data(14) => trd4_host_data(14),
      trd4_host_data(13) => trd4_host_data(13),
      trd4_host_data(12) => trd4_host_data(12),
      trd4_host_data(11) => trd4_host_data(11),
      trd4_host_data(10) => trd4_host_data(10),
      trd4_host_data(9) => trd4_host_data(9),
      trd4_host_data(8) => trd4_host_data(8),
      trd4_host_data(7) => trd4_host_data(7),
      trd4_host_data(6) => trd4_host_data(6),
      trd4_host_data(5) => trd4_host_data(5),
      trd4_host_data(4) => trd4_host_data(4),
      trd4_host_data(3) => trd4_host_data(3),
      trd4_host_data(2) => trd4_host_data(2),
      trd4_host_data(1) => trd4_host_data(1),
      trd4_host_data(0) => trd4_host_data(0),
      trd_host_data(63) => trdi_host_data(63),
      trd_host_data(62) => trdi_host_data(62),
      trd_host_data(61) => trdi_host_data(61),
      trd_host_data(60) => trdi_host_data(60),
      trd_host_data(59) => trdi_host_data(59),
      trd_host_data(58) => trdi_host_data(58),
      trd_host_data(57) => trdi_host_data(57),
      trd_host_data(56) => trdi_host_data(56),
      trd_host_data(55) => trdi_host_data(55),
      trd_host_data(54) => trdi_host_data(54),
      trd_host_data(53) => trdi_host_data(53),
      trd_host_data(52) => trdi_host_data(52),
      trd_host_data(51) => trdi_host_data(51),
      trd_host_data(50) => trdi_host_data(50),
      trd_host_data(49) => trdi_host_data(49),
      trd_host_data(48) => trdi_host_data(48),
      trd_host_data(47) => trdi_host_data(47),
      trd_host_data(46) => trdi_host_data(46),
      trd_host_data(45) => trdi_host_data(45),
      trd_host_data(44) => trdi_host_data(44),
      trd_host_data(43) => trdi_host_data(43),
      trd_host_data(42) => trdi_host_data(42),
      trd_host_data(41) => trdi_host_data(41),
      trd_host_data(40) => trdi_host_data(40),
      trd_host_data(39) => trdi_host_data(39),
      trd_host_data(38) => trdi_host_data(38),
      trd_host_data(37) => trdi_host_data(37),
      trd_host_data(36) => trdi_host_data(36),
      trd_host_data(35) => trdi_host_data(35),
      trd_host_data(34) => trdi_host_data(34),
      trd_host_data(33) => trdi_host_data(33),
      trd_host_data(32) => trdi_host_data(32),
      trd_host_data(31) => trdi_host_data(31),
      trd_host_data(30) => trdi_host_data(30),
      trd_host_data(29) => trdi_host_data(29),
      trd_host_data(28) => trdi_host_data(28),
      trd_host_data(27) => trdi_host_data(27),
      trd_host_data(26) => trdi_host_data(26),
      trd_host_data(25) => trdi_host_data(25),
      trd_host_data(24) => trdi_host_data(24),
      trd_host_data(23) => trdi_host_data(23),
      trd_host_data(22) => trdi_host_data(22),
      trd_host_data(21) => trdi_host_data(21),
      trd_host_data(20) => trdi_host_data(20),
      trd_host_data(19) => trdi_host_data(19),
      trd_host_data(18) => trdi_host_data(18),
      trd_host_data(17) => trdi_host_data(17),
      trd_host_data(16) => trdi_host_data(16),
      trd_host_data(15) => trdi_host_data(15),
      trd_host_data(14) => trdi_host_data(14),
      trd_host_data(13) => trdi_host_data(13),
      trd_host_data(12) => trdi_host_data(12),
      trd_host_data(11) => trdi_host_data(11),
      trd_host_data(10) => trdi_host_data(10),
      trd_host_data(9) => trdi_host_data(9),
      trd_host_data(8) => trdi_host_data(8),
      trd_host_data(7) => trdi_host_data(7),
      trd_host_data(6) => trdi_host_data(6),
      trd_host_data(5) => trdi_host_data(5),
      trd_host_data(4) => trdi_host_data(4),
      trd_host_data(3) => trdi_host_data(3),
      trd_host_data(2) => trdi_host_data(2),
      trd_host_data(1) => trdi_host_data(1),
      trd_host_data(0) => trdi_host_data(0),
      lc_data(63) => lc_data(63),
      lc_data(62) => lc_data(62),
      lc_data(61) => lc_data(61),
      lc_data(60) => lc_data(60),
      lc_data(59) => lc_data(59),
      lc_data(58) => lc_data(58),
      lc_data(57) => lc_data(57),
      lc_data(56) => lc_data(56),
      lc_data(55) => lc_data(55),
      lc_data(54) => lc_data(54),
      lc_data(53) => lc_data(53),
      lc_data(52) => lc_data(52),
      lc_data(51) => lc_data(51),
      lc_data(50) => lc_data(50),
      lc_data(49) => lc_data(49),
      lc_data(48) => lc_data(48),
      lc_data(47) => lc_data(47),
      lc_data(46) => lc_data(46),
      lc_data(45) => lc_data(45),
      lc_data(44) => lc_data(44),
      lc_data(43) => lc_data(43),
      lc_data(42) => lc_data(42),
      lc_data(41) => lc_data(41),
      lc_data(40) => lc_data(40),
      lc_data(39) => lc_data(39),
      lc_data(38) => lc_data(38),
      lc_data(37) => lc_data(37),
      lc_data(36) => lc_data(36),
      lc_data(35) => lc_data(35),
      lc_data(34) => lc_data(34),
      lc_data(33) => lc_data(33),
      lc_data(32) => lc_data(32),
      lc_data(31) => lc_data(31),
      lc_data(30) => lc_data(30),
      lc_data(29) => lc_data(29),
      lc_data(28) => lc_data(28),
      lc_data(27) => lc_data(27),
      lc_data(26) => lc_data(26),
      lc_data(25) => lc_data(25),
      lc_data(24) => lc_data(24),
      lc_data(23) => lc_data(23),
      lc_data(22) => lc_data(22),
      lc_data(21) => lc_data(21),
      lc_data(20) => lc_data(20),
      lc_data(19) => lc_data(19),
      lc_data(18) => lc_data(18),
      lc_data(17) => lc_data(17),
      lc_data(16) => lc_data(16),
      lc_data(15) => lc_data(15),
      lc_data(14) => lc_data(14),
      lc_data(13) => lc_data(13),
      lc_data(12) => lc_data(12),
      lc_data(11) => lc_data(11),
      lc_data(10) => lc_data(10),
      lc_data(9) => lc_data(9),
      lc_data(8) => lc_data(8),
      lc_data(7) => lc_data(7),
      lc_data(6) => lc_data(6),
      lc_data(5) => lc_data(5),
      lc_data(4) => lc_data(4),
      lc_data(3) => lc_data(3),
      lc_data(2) => lc_data(2),
      lc_data(1) => lc_data(1),
      lc_data(0) => lc_data(0),
      trd_data(15, 63) => trd_data(15, 63),
      trd_data(15, 62) => trd_data(15, 62),
      trd_data(15, 61) => trd_data(15, 61),
      trd_data(15, 60) => trd_data(15, 60),
      trd_data(15, 59) => trd_data(15, 59),
      trd_data(15, 58) => trd_data(15, 58),
      trd_data(15, 57) => trd_data(15, 57),
      trd_data(15, 56) => trd_data(15, 56),
      trd_data(15, 55) => trd_data(15, 55),
      trd_data(15, 54) => trd_data(15, 54),
      trd_data(15, 53) => trd_data(15, 53),
      trd_data(15, 52) => trd_data(15, 52),
      trd_data(15, 51) => trd_data(15, 51),
      trd_data(15, 50) => trd_data(15, 50),
      trd_data(15, 49) => trd_data(15, 49),
      trd_data(15, 48) => trd_data(15, 48),
      trd_data(15, 47) => trd_data(15, 47),
      trd_data(15, 46) => trd_data(15, 46),
      trd_data(15, 45) => trd_data(15, 45),
      trd_data(15, 44) => trd_data(15, 44),
      trd_data(15, 43) => trd_data(15, 43),
      trd_data(15, 42) => trd_data(15, 42),
      trd_data(15, 41) => trd_data(15, 41),
      trd_data(15, 40) => trd_data(15, 40),
      trd_data(15, 39) => trd_data(15, 39),
      trd_data(15, 38) => trd_data(15, 38),
      trd_data(15, 37) => trd_data(15, 37),
      trd_data(15, 36) => trd_data(15, 36),
      trd_data(15, 35) => trd_data(15, 35),
      trd_data(15, 34) => trd_data(15, 34),
      trd_data(15, 33) => trd_data(15, 33),
      trd_data(15, 32) => trd_data(15, 32),
      trd_data(15, 31) => trd_data(15, 31),
      trd_data(15, 30) => trd_data(15, 30),
      trd_data(15, 29) => trd_data(15, 29),
      trd_data(15, 28) => trd_data(15, 28),
      trd_data(15, 27) => trd_data(15, 27),
      trd_data(15, 26) => trd_data(15, 26),
      trd_data(15, 25) => trd_data(15, 25),
      trd_data(15, 24) => trd_data(15, 24),
      trd_data(15, 23) => trd_data(15, 23),
      trd_data(15, 22) => trd_data(15, 22),
      trd_data(15, 21) => trd_data(15, 21),
      trd_data(15, 20) => trd_data(15, 20),
      trd_data(15, 19) => trd_data(15, 19),
      trd_data(15, 18) => trd_data(15, 18),
      trd_data(15, 17) => trd_data(15, 17),
      trd_data(15, 16) => trd_data(15, 16),
      trd_data(15, 15) => trd_data(15, 15),
      trd_data(15, 14) => trd_data(15, 14),
      trd_data(15, 13) => trd_data(15, 13),
      trd_data(15, 12) => trd_data(15, 12),
      trd_data(15, 11) => trd_data(15, 11),
      trd_data(15, 10) => trd_data(15, 10),
      trd_data(15, 9) => trd_data(15, 9),
      trd_data(15, 8) => trd_data(15, 8),
      trd_data(15, 7) => trd_data(15, 7),
      trd_data(15, 6) => trd_data(15, 6),
      trd_data(15, 5) => trd_data(15, 5),
      trd_data(15, 4) => trd_data(15, 4),
      trd_data(15, 3) => trd_data(15, 3),
      trd_data(15, 2) => trd_data(15, 2),
      trd_data(15, 1) => trd_data(15, 1),
      trd_data(15, 0) => trd_data(15, 0),
      trd_data(14, 63) => trd_data(14, 63),
      trd_data(14, 62) => trd_data(14, 62),
      trd_data(14, 61) => trd_data(14, 61),
      trd_data(14, 60) => trd_data(14, 60),
      trd_data(14, 59) => trd_data(14, 59),
      trd_data(14, 58) => trd_data(14, 58),
      trd_data(14, 57) => trd_data(14, 57),
      trd_data(14, 56) => trd_data(14, 56),
      trd_data(14, 55) => trd_data(14, 55),
      trd_data(14, 54) => trd_data(14, 54),
      trd_data(14, 53) => trd_data(14, 53),
      trd_data(14, 52) => trd_data(14, 52),
      trd_data(14, 51) => trd_data(14, 51),
      trd_data(14, 50) => trd_data(14, 50),
      trd_data(14, 49) => trd_data(14, 49),
      trd_data(14, 48) => trd_data(14, 48),
      trd_data(14, 47) => trd_data(14, 47),
      trd_data(14, 46) => trd_data(14, 46),
      trd_data(14, 45) => trd_data(14, 45),
      trd_data(14, 44) => trd_data(14, 44),
      trd_data(14, 43) => trd_data(14, 43),
      trd_data(14, 42) => trd_data(14, 42),
      trd_data(14, 41) => trd_data(14, 41),
      trd_data(14, 40) => trd_data(14, 40),
      trd_data(14, 39) => trd_data(14, 39),
      trd_data(14, 38) => trd_data(14, 38),
      trd_data(14, 37) => trd_data(14, 37),
      trd_data(14, 36) => trd_data(14, 36),
      trd_data(14, 35) => trd_data(14, 35),
      trd_data(14, 34) => trd_data(14, 34),
      trd_data(14, 33) => trd_data(14, 33),
      trd_data(14, 32) => trd_data(14, 32),
      trd_data(14, 31) => trd_data(14, 31),
      trd_data(14, 30) => trd_data(14, 30),
      trd_data(14, 29) => trd_data(14, 29),
      trd_data(14, 28) => trd_data(14, 28),
      trd_data(14, 27) => trd_data(14, 27),
      trd_data(14, 26) => trd_data(14, 26),
      trd_data(14, 25) => trd_data(14, 25),
      trd_data(14, 24) => trd_data(14, 24),
      trd_data(14, 23) => trd_data(14, 23),
      trd_data(14, 22) => trd_data(14, 22),
      trd_data(14, 21) => trd_data(14, 21),
      trd_data(14, 20) => trd_data(14, 20),
      trd_data(14, 19) => trd_data(14, 19),
      trd_data(14, 18) => trd_data(14, 18),
      trd_data(14, 17) => trd_data(14, 17),
      trd_data(14, 16) => trd_data(14, 16),
      trd_data(14, 15) => trd_data(14, 15),
      trd_data(14, 14) => trd_data(14, 14),
      trd_data(14, 13) => trd_data(14, 13),
      trd_data(14, 12) => trd_data(14, 12),
      trd_data(14, 11) => trd_data(14, 11),
      trd_data(14, 10) => trd_data(14, 10),
      trd_data(14, 9) => trd_data(14, 9),
      trd_data(14, 8) => trd_data(14, 8),
      trd_data(14, 7) => trd_data(14, 7),
      trd_data(14, 6) => trd_data(14, 6),
      trd_data(14, 5) => trd_data(14, 5),
      trd_data(14, 4) => trd_data(14, 4),
      trd_data(14, 3) => trd_data(14, 3),
      trd_data(14, 2) => trd_data(14, 2),
      trd_data(14, 1) => trd_data(14, 1),
      trd_data(14, 0) => trd_data(14, 0),
      trd_data(13, 63) => trd_data(13, 63),
      trd_data(13, 62) => trd_data(13, 62),
      trd_data(13, 61) => trd_data(13, 61),
      trd_data(13, 60) => trd_data(13, 60),
      trd_data(13, 59) => trd_data(13, 59),
      trd_data(13, 58) => trd_data(13, 58),
      trd_data(13, 57) => trd_data(13, 57),
      trd_data(13, 56) => trd_data(13, 56),
      trd_data(13, 55) => trd_data(13, 55),
      trd_data(13, 54) => trd_data(13, 54),
      trd_data(13, 53) => trd_data(13, 53),
      trd_data(13, 52) => trd_data(13, 52),
      trd_data(13, 51) => trd_data(13, 51),
      trd_data(13, 50) => trd_data(13, 50),
      trd_data(13, 49) => trd_data(13, 49),
      trd_data(13, 48) => trd_data(13, 48),
      trd_data(13, 47) => trd_data(13, 47),
      trd_data(13, 46) => trd_data(13, 46),
      trd_data(13, 45) => trd_data(13, 45),
      trd_data(13, 44) => trd_data(13, 44),
      trd_data(13, 43) => trd_data(13, 43),
      trd_data(13, 42) => trd_data(13, 42),
      trd_data(13, 41) => trd_data(13, 41),
      trd_data(13, 40) => trd_data(13, 40),
      trd_data(13, 39) => trd_data(13, 39),
      trd_data(13, 38) => trd_data(13, 38),
      trd_data(13, 37) => trd_data(13, 37),
      trd_data(13, 36) => trd_data(13, 36),
      trd_data(13, 35) => trd_data(13, 35),
      trd_data(13, 34) => trd_data(13, 34),
      trd_data(13, 33) => trd_data(13, 33),
      trd_data(13, 32) => trd_data(13, 32),
      trd_data(13, 31) => trd_data(13, 31),
      trd_data(13, 30) => trd_data(13, 30),
      trd_data(13, 29) => trd_data(13, 29),
      trd_data(13, 28) => trd_data(13, 28),
      trd_data(13, 27) => trd_data(13, 27),
      trd_data(13, 26) => trd_data(13, 26),
      trd_data(13, 25) => trd_data(13, 25),
      trd_data(13, 24) => trd_data(13, 24),
      trd_data(13, 23) => trd_data(13, 23),
      trd_data(13, 22) => trd_data(13, 22),
      trd_data(13, 21) => trd_data(13, 21),
      trd_data(13, 20) => trd_data(13, 20),
      trd_data(13, 19) => trd_data(13, 19),
      trd_data(13, 18) => trd_data(13, 18),
      trd_data(13, 17) => trd_data(13, 17),
      trd_data(13, 16) => trd_data(13, 16),
      trd_data(13, 15) => trd_data(13, 15),
      trd_data(13, 14) => trd_data(13, 14),
      trd_data(13, 13) => trd_data(13, 13),
      trd_data(13, 12) => trd_data(13, 12),
      trd_data(13, 11) => trd_data(13, 11),
      trd_data(13, 10) => trd_data(13, 10),
      trd_data(13, 9) => trd_data(13, 9),
      trd_data(13, 8) => trd_data(13, 8),
      trd_data(13, 7) => trd_data(13, 7),
      trd_data(13, 6) => trd_data(13, 6),
      trd_data(13, 5) => trd_data(13, 5),
      trd_data(13, 4) => trd_data(13, 4),
      trd_data(13, 3) => trd_data(13, 3),
      trd_data(13, 2) => trd_data(13, 2),
      trd_data(13, 1) => trd_data(13, 1),
      trd_data(13, 0) => trd_data(13, 0),
      trd_data(12, 63) => trd_data(12, 63),
      trd_data(12, 62) => trd_data(12, 62),
      trd_data(12, 61) => trd_data(12, 61),
      trd_data(12, 60) => trd_data(12, 60),
      trd_data(12, 59) => trd_data(12, 59),
      trd_data(12, 58) => trd_data(12, 58),
      trd_data(12, 57) => trd_data(12, 57),
      trd_data(12, 56) => trd_data(12, 56),
      trd_data(12, 55) => trd_data(12, 55),
      trd_data(12, 54) => trd_data(12, 54),
      trd_data(12, 53) => trd_data(12, 53),
      trd_data(12, 52) => trd_data(12, 52),
      trd_data(12, 51) => trd_data(12, 51),
      trd_data(12, 50) => trd_data(12, 50),
      trd_data(12, 49) => trd_data(12, 49),
      trd_data(12, 48) => trd_data(12, 48),
      trd_data(12, 47) => trd_data(12, 47),
      trd_data(12, 46) => trd_data(12, 46),
      trd_data(12, 45) => trd_data(12, 45),
      trd_data(12, 44) => trd_data(12, 44),
      trd_data(12, 43) => trd_data(12, 43),
      trd_data(12, 42) => trd_data(12, 42),
      trd_data(12, 41) => trd_data(12, 41),
      trd_data(12, 40) => trd_data(12, 40),
      trd_data(12, 39) => trd_data(12, 39),
      trd_data(12, 38) => trd_data(12, 38),
      trd_data(12, 37) => trd_data(12, 37),
      trd_data(12, 36) => trd_data(12, 36),
      trd_data(12, 35) => trd_data(12, 35),
      trd_data(12, 34) => trd_data(12, 34),
      trd_data(12, 33) => trd_data(12, 33),
      trd_data(12, 32) => trd_data(12, 32),
      trd_data(12, 31) => trd_data(12, 31),
      trd_data(12, 30) => trd_data(12, 30),
      trd_data(12, 29) => trd_data(12, 29),
      trd_data(12, 28) => trd_data(12, 28),
      trd_data(12, 27) => trd_data(12, 27),
      trd_data(12, 26) => trd_data(12, 26),
      trd_data(12, 25) => trd_data(12, 25),
      trd_data(12, 24) => trd_data(12, 24),
      trd_data(12, 23) => trd_data(12, 23),
      trd_data(12, 22) => trd_data(12, 22),
      trd_data(12, 21) => trd_data(12, 21),
      trd_data(12, 20) => trd_data(12, 20),
      trd_data(12, 19) => trd_data(12, 19),
      trd_data(12, 18) => trd_data(12, 18),
      trd_data(12, 17) => trd_data(12, 17),
      trd_data(12, 16) => trd_data(12, 16),
      trd_data(12, 15) => trd_data(12, 15),
      trd_data(12, 14) => trd_data(12, 14),
      trd_data(12, 13) => trd_data(12, 13),
      trd_data(12, 12) => trd_data(12, 12),
      trd_data(12, 11) => trd_data(12, 11),
      trd_data(12, 10) => trd_data(12, 10),
      trd_data(12, 9) => trd_data(12, 9),
      trd_data(12, 8) => trd_data(12, 8),
      trd_data(12, 7) => trd_data(12, 7),
      trd_data(12, 6) => trd_data(12, 6),
      trd_data(12, 5) => trd_data(12, 5),
      trd_data(12, 4) => trd_data(12, 4),
      trd_data(12, 3) => trd_data(12, 3),
      trd_data(12, 2) => trd_data(12, 2),
      trd_data(12, 1) => trd_data(12, 1),
      trd_data(12, 0) => trd_data(12, 0),
      trd_data(11, 63) => trd_data(11, 63),
      trd_data(11, 62) => trd_data(11, 62),
      trd_data(11, 61) => trd_data(11, 61),
      trd_data(11, 60) => trd_data(11, 60),
      trd_data(11, 59) => trd_data(11, 59),
      trd_data(11, 58) => trd_data(11, 58),
      trd_data(11, 57) => trd_data(11, 57),
      trd_data(11, 56) => trd_data(11, 56),
      trd_data(11, 55) => trd_data(11, 55),
      trd_data(11, 54) => trd_data(11, 54),
      trd_data(11, 53) => trd_data(11, 53),
      trd_data(11, 52) => trd_data(11, 52),
      trd_data(11, 51) => trd_data(11, 51),
      trd_data(11, 50) => trd_data(11, 50),
      trd_data(11, 49) => trd_data(11, 49),
      trd_data(11, 48) => trd_data(11, 48),
      trd_data(11, 47) => trd_data(11, 47),
      trd_data(11, 46) => trd_data(11, 46),
      trd_data(11, 45) => trd_data(11, 45),
      trd_data(11, 44) => trd_data(11, 44),
      trd_data(11, 43) => trd_data(11, 43),
      trd_data(11, 42) => trd_data(11, 42),
      trd_data(11, 41) => trd_data(11, 41),
      trd_data(11, 40) => trd_data(11, 40),
      trd_data(11, 39) => trd_data(11, 39),
      trd_data(11, 38) => trd_data(11, 38),
      trd_data(11, 37) => trd_data(11, 37),
      trd_data(11, 36) => trd_data(11, 36),
      trd_data(11, 35) => trd_data(11, 35),
      trd_data(11, 34) => trd_data(11, 34),
      trd_data(11, 33) => trd_data(11, 33),
      trd_data(11, 32) => trd_data(11, 32),
      trd_data(11, 31) => trd_data(11, 31),
      trd_data(11, 30) => trd_data(11, 30),
      trd_data(11, 29) => trd_data(11, 29),
      trd_data(11, 28) => trd_data(11, 28),
      trd_data(11, 27) => trd_data(11, 27),
      trd_data(11, 26) => trd_data(11, 26),
      trd_data(11, 25) => trd_data(11, 25),
      trd_data(11, 24) => trd_data(11, 24),
      trd_data(11, 23) => trd_data(11, 23),
      trd_data(11, 22) => trd_data(11, 22),
      trd_data(11, 21) => trd_data(11, 21),
      trd_data(11, 20) => trd_data(11, 20),
      trd_data(11, 19) => trd_data(11, 19),
      trd_data(11, 18) => trd_data(11, 18),
      trd_data(11, 17) => trd_data(11, 17),
      trd_data(11, 16) => trd_data(11, 16),
      trd_data(11, 15) => trd_data(11, 15),
      trd_data(11, 14) => trd_data(11, 14),
      trd_data(11, 13) => trd_data(11, 13),
      trd_data(11, 12) => trd_data(11, 12),
      trd_data(11, 11) => trd_data(11, 11),
      trd_data(11, 10) => trd_data(11, 10),
      trd_data(11, 9) => trd_data(11, 9),
      trd_data(11, 8) => trd_data(11, 8),
      trd_data(11, 7) => trd_data(11, 7),
      trd_data(11, 6) => trd_data(11, 6),
      trd_data(11, 5) => trd_data(11, 5),
      trd_data(11, 4) => trd_data(11, 4),
      trd_data(11, 3) => trd_data(11, 3),
      trd_data(11, 2) => trd_data(11, 2),
      trd_data(11, 1) => trd_data(11, 1),
      trd_data(11, 0) => trd_data(11, 0),
      trd_data(10, 63) => trd_data(10, 63),
      trd_data(10, 62) => trd_data(10, 62),
      trd_data(10, 61) => trd_data(10, 61),
      trd_data(10, 60) => trd_data(10, 60),
      trd_data(10, 59) => trd_data(10, 59),
      trd_data(10, 58) => trd_data(10, 58),
      trd_data(10, 57) => trd_data(10, 57),
      trd_data(10, 56) => trd_data(10, 56),
      trd_data(10, 55) => trd_data(10, 55),
      trd_data(10, 54) => trd_data(10, 54),
      trd_data(10, 53) => trd_data(10, 53),
      trd_data(10, 52) => trd_data(10, 52),
      trd_data(10, 51) => trd_data(10, 51),
      trd_data(10, 50) => trd_data(10, 50),
      trd_data(10, 49) => trd_data(10, 49),
      trd_data(10, 48) => trd_data(10, 48),
      trd_data(10, 47) => trd_data(10, 47),
      trd_data(10, 46) => trd_data(10, 46),
      trd_data(10, 45) => trd_data(10, 45),
      trd_data(10, 44) => trd_data(10, 44),
      trd_data(10, 43) => trd_data(10, 43),
      trd_data(10, 42) => trd_data(10, 42),
      trd_data(10, 41) => trd_data(10, 41),
      trd_data(10, 40) => trd_data(10, 40),
      trd_data(10, 39) => trd_data(10, 39),
      trd_data(10, 38) => trd_data(10, 38),
      trd_data(10, 37) => trd_data(10, 37),
      trd_data(10, 36) => trd_data(10, 36),
      trd_data(10, 35) => trd_data(10, 35),
      trd_data(10, 34) => trd_data(10, 34),
      trd_data(10, 33) => trd_data(10, 33),
      trd_data(10, 32) => trd_data(10, 32),
      trd_data(10, 31) => trd_data(10, 31),
      trd_data(10, 30) => trd_data(10, 30),
      trd_data(10, 29) => trd_data(10, 29),
      trd_data(10, 28) => trd_data(10, 28),
      trd_data(10, 27) => trd_data(10, 27),
      trd_data(10, 26) => trd_data(10, 26),
      trd_data(10, 25) => trd_data(10, 25),
      trd_data(10, 24) => trd_data(10, 24),
      trd_data(10, 23) => trd_data(10, 23),
      trd_data(10, 22) => trd_data(10, 22),
      trd_data(10, 21) => trd_data(10, 21),
      trd_data(10, 20) => trd_data(10, 20),
      trd_data(10, 19) => trd_data(10, 19),
      trd_data(10, 18) => trd_data(10, 18),
      trd_data(10, 17) => trd_data(10, 17),
      trd_data(10, 16) => trd_data(10, 16),
      trd_data(10, 15) => trd_data(10, 15),
      trd_data(10, 14) => trd_data(10, 14),
      trd_data(10, 13) => trd_data(10, 13),
      trd_data(10, 12) => trd_data(10, 12),
      trd_data(10, 11) => trd_data(10, 11),
      trd_data(10, 10) => trd_data(10, 10),
      trd_data(10, 9) => trd_data(10, 9),
      trd_data(10, 8) => trd_data(10, 8),
      trd_data(10, 7) => trd_data(10, 7),
      trd_data(10, 6) => trd_data(10, 6),
      trd_data(10, 5) => trd_data(10, 5),
      trd_data(10, 4) => trd_data(10, 4),
      trd_data(10, 3) => trd_data(10, 3),
      trd_data(10, 2) => trd_data(10, 2),
      trd_data(10, 1) => trd_data(10, 1),
      trd_data(10, 0) => trd_data(10, 0),
      trd_data(9, 63) => trd_data(9, 63),
      trd_data(9, 62) => trd_data(9, 62),
      trd_data(9, 61) => trd_data(9, 61),
      trd_data(9, 60) => trd_data(9, 60),
      trd_data(9, 59) => trd_data(9, 59),
      trd_data(9, 58) => trd_data(9, 58),
      trd_data(9, 57) => trd_data(9, 57),
      trd_data(9, 56) => trd_data(9, 56),
      trd_data(9, 55) => trd_data(9, 55),
      trd_data(9, 54) => trd_data(9, 54),
      trd_data(9, 53) => trd_data(9, 53),
      trd_data(9, 52) => trd_data(9, 52),
      trd_data(9, 51) => trd_data(9, 51),
      trd_data(9, 50) => trd_data(9, 50),
      trd_data(9, 49) => trd_data(9, 49),
      trd_data(9, 48) => trd_data(9, 48),
      trd_data(9, 47) => trd_data(9, 47),
      trd_data(9, 46) => trd_data(9, 46),
      trd_data(9, 45) => trd_data(9, 45),
      trd_data(9, 44) => trd_data(9, 44),
      trd_data(9, 43) => trd_data(9, 43),
      trd_data(9, 42) => trd_data(9, 42),
      trd_data(9, 41) => trd_data(9, 41),
      trd_data(9, 40) => trd_data(9, 40),
      trd_data(9, 39) => trd_data(9, 39),
      trd_data(9, 38) => trd_data(9, 38),
      trd_data(9, 37) => trd_data(9, 37),
      trd_data(9, 36) => trd_data(9, 36),
      trd_data(9, 35) => trd_data(9, 35),
      trd_data(9, 34) => trd_data(9, 34),
      trd_data(9, 33) => trd_data(9, 33),
      trd_data(9, 32) => trd_data(9, 32),
      trd_data(9, 31) => trd_data(9, 31),
      trd_data(9, 30) => trd_data(9, 30),
      trd_data(9, 29) => trd_data(9, 29),
      trd_data(9, 28) => trd_data(9, 28),
      trd_data(9, 27) => trd_data(9, 27),
      trd_data(9, 26) => trd_data(9, 26),
      trd_data(9, 25) => trd_data(9, 25),
      trd_data(9, 24) => trd_data(9, 24),
      trd_data(9, 23) => trd_data(9, 23),
      trd_data(9, 22) => trd_data(9, 22),
      trd_data(9, 21) => trd_data(9, 21),
      trd_data(9, 20) => trd_data(9, 20),
      trd_data(9, 19) => trd_data(9, 19),
      trd_data(9, 18) => trd_data(9, 18),
      trd_data(9, 17) => trd_data(9, 17),
      trd_data(9, 16) => trd_data(9, 16),
      trd_data(9, 15) => trd_data(9, 15),
      trd_data(9, 14) => trd_data(9, 14),
      trd_data(9, 13) => trd_data(9, 13),
      trd_data(9, 12) => trd_data(9, 12),
      trd_data(9, 11) => trd_data(9, 11),
      trd_data(9, 10) => trd_data(9, 10),
      trd_data(9, 9) => trd_data(9, 9),
      trd_data(9, 8) => trd_data(9, 8),
      trd_data(9, 7) => trd_data(9, 7),
      trd_data(9, 6) => trd_data(9, 6),
      trd_data(9, 5) => trd_data(9, 5),
      trd_data(9, 4) => trd_data(9, 4),
      trd_data(9, 3) => trd_data(9, 3),
      trd_data(9, 2) => trd_data(9, 2),
      trd_data(9, 1) => trd_data(9, 1),
      trd_data(9, 0) => trd_data(9, 0),
      trd_data(8, 63) => trd_data(8, 63),
      trd_data(8, 62) => trd_data(8, 62),
      trd_data(8, 61) => trd_data(8, 61),
      trd_data(8, 60) => trd_data(8, 60),
      trd_data(8, 59) => trd_data(8, 59),
      trd_data(8, 58) => trd_data(8, 58),
      trd_data(8, 57) => trd_data(8, 57),
      trd_data(8, 56) => trd_data(8, 56),
      trd_data(8, 55) => trd_data(8, 55),
      trd_data(8, 54) => trd_data(8, 54),
      trd_data(8, 53) => trd_data(8, 53),
      trd_data(8, 52) => trd_data(8, 52),
      trd_data(8, 51) => trd_data(8, 51),
      trd_data(8, 50) => trd_data(8, 50),
      trd_data(8, 49) => trd_data(8, 49),
      trd_data(8, 48) => trd_data(8, 48),
      trd_data(8, 47) => trd_data(8, 47),
      trd_data(8, 46) => trd_data(8, 46),
      trd_data(8, 45) => trd_data(8, 45),
      trd_data(8, 44) => trd_data(8, 44),
      trd_data(8, 43) => trd_data(8, 43),
      trd_data(8, 42) => trd_data(8, 42),
      trd_data(8, 41) => trd_data(8, 41),
      trd_data(8, 40) => trd_data(8, 40),
      trd_data(8, 39) => trd_data(8, 39),
      trd_data(8, 38) => trd_data(8, 38),
      trd_data(8, 37) => trd_data(8, 37),
      trd_data(8, 36) => trd_data(8, 36),
      trd_data(8, 35) => trd_data(8, 35),
      trd_data(8, 34) => trd_data(8, 34),
      trd_data(8, 33) => trd_data(8, 33),
      trd_data(8, 32) => trd_data(8, 32),
      trd_data(8, 31) => trd_data(8, 31),
      trd_data(8, 30) => trd_data(8, 30),
      trd_data(8, 29) => trd_data(8, 29),
      trd_data(8, 28) => trd_data(8, 28),
      trd_data(8, 27) => trd_data(8, 27),
      trd_data(8, 26) => trd_data(8, 26),
      trd_data(8, 25) => trd_data(8, 25),
      trd_data(8, 24) => trd_data(8, 24),
      trd_data(8, 23) => trd_data(8, 23),
      trd_data(8, 22) => trd_data(8, 22),
      trd_data(8, 21) => trd_data(8, 21),
      trd_data(8, 20) => trd_data(8, 20),
      trd_data(8, 19) => trd_data(8, 19),
      trd_data(8, 18) => trd_data(8, 18),
      trd_data(8, 17) => trd_data(8, 17),
      trd_data(8, 16) => trd_data(8, 16),
      trd_data(8, 15) => trd_data(8, 15),
      trd_data(8, 14) => trd_data(8, 14),
      trd_data(8, 13) => trd_data(8, 13),
      trd_data(8, 12) => trd_data(8, 12),
      trd_data(8, 11) => trd_data(8, 11),
      trd_data(8, 10) => trd_data(8, 10),
      trd_data(8, 9) => trd_data(8, 9),
      trd_data(8, 8) => trd_data(8, 8),
      trd_data(8, 7) => trd_data(8, 7),
      trd_data(8, 6) => trd_data(8, 6),
      trd_data(8, 5) => trd_data(8, 5),
      trd_data(8, 4) => trd_data(8, 4),
      trd_data(8, 3) => trd_data(8, 3),
      trd_data(8, 2) => trd_data(8, 2),
      trd_data(8, 1) => trd_data(8, 1),
      trd_data(8, 0) => trd_data(8, 0),
      trd_data(7, 63) => trd_data(7, 63),
      trd_data(7, 62) => trd_data(7, 62),
      trd_data(7, 61) => trd_data(7, 61),
      trd_data(7, 60) => trd_data(7, 60),
      trd_data(7, 59) => trd_data(7, 59),
      trd_data(7, 58) => trd_data(7, 58),
      trd_data(7, 57) => trd_data(7, 57),
      trd_data(7, 56) => trd_data(7, 56),
      trd_data(7, 55) => trd_data(7, 55),
      trd_data(7, 54) => trd_data(7, 54),
      trd_data(7, 53) => trd_data(7, 53),
      trd_data(7, 52) => trd_data(7, 52),
      trd_data(7, 51) => trd_data(7, 51),
      trd_data(7, 50) => trd_data(7, 50),
      trd_data(7, 49) => trd_data(7, 49),
      trd_data(7, 48) => trd_data(7, 48),
      trd_data(7, 47) => trd_data(7, 47),
      trd_data(7, 46) => trd_data(7, 46),
      trd_data(7, 45) => trd_data(7, 45),
      trd_data(7, 44) => trd_data(7, 44),
      trd_data(7, 43) => trd_data(7, 43),
      trd_data(7, 42) => trd_data(7, 42),
      trd_data(7, 41) => trd_data(7, 41),
      trd_data(7, 40) => trd_data(7, 40),
      trd_data(7, 39) => trd_data(7, 39),
      trd_data(7, 38) => trd_data(7, 38),
      trd_data(7, 37) => trd_data(7, 37),
      trd_data(7, 36) => trd_data(7, 36),
      trd_data(7, 35) => trd_data(7, 35),
      trd_data(7, 34) => trd_data(7, 34),
      trd_data(7, 33) => trd_data(7, 33),
      trd_data(7, 32) => trd_data(7, 32),
      trd_data(7, 31) => trd_data(7, 31),
      trd_data(7, 30) => trd_data(7, 30),
      trd_data(7, 29) => trd_data(7, 29),
      trd_data(7, 28) => trd_data(7, 28),
      trd_data(7, 27) => trd_data(7, 27),
      trd_data(7, 26) => trd_data(7, 26),
      trd_data(7, 25) => trd_data(7, 25),
      trd_data(7, 24) => trd_data(7, 24),
      trd_data(7, 23) => trd_data(7, 23),
      trd_data(7, 22) => trd_data(7, 22),
      trd_data(7, 21) => trd_data(7, 21),
      trd_data(7, 20) => trd_data(7, 20),
      trd_data(7, 19) => trd_data(7, 19),
      trd_data(7, 18) => trd_data(7, 18),
      trd_data(7, 17) => trd_data(7, 17),
      trd_data(7, 16) => trd_data(7, 16),
      trd_data(7, 15) => trd_data(7, 15),
      trd_data(7, 14) => trd_data(7, 14),
      trd_data(7, 13) => trd_data(7, 13),
      trd_data(7, 12) => trd_data(7, 12),
      trd_data(7, 11) => trd_data(7, 11),
      trd_data(7, 10) => trd_data(7, 10),
      trd_data(7, 9) => trd_data(7, 9),
      trd_data(7, 8) => trd_data(7, 8),
      trd_data(7, 7) => trd_data(7, 7),
      trd_data(7, 6) => trd_data(7, 6),
      trd_data(7, 5) => trd_data(7, 5),
      trd_data(7, 4) => trd_data(7, 4),
      trd_data(7, 3) => trd_data(7, 3),
      trd_data(7, 2) => trd_data(7, 2),
      trd_data(7, 1) => trd_data(7, 1),
      trd_data(7, 0) => trd_data(7, 0),
      trd_data(6, 63) => trd_data(6, 63),
      trd_data(6, 62) => trd_data(6, 62),
      trd_data(6, 61) => trd_data(6, 61),
      trd_data(6, 60) => trd_data(6, 60),
      trd_data(6, 59) => trd_data(6, 59),
      trd_data(6, 58) => trd_data(6, 58),
      trd_data(6, 57) => trd_data(6, 57),
      trd_data(6, 56) => trd_data(6, 56),
      trd_data(6, 55) => trd_data(6, 55),
      trd_data(6, 54) => trd_data(6, 54),
      trd_data(6, 53) => trd_data(6, 53),
      trd_data(6, 52) => trd_data(6, 52),
      trd_data(6, 51) => trd_data(6, 51),
      trd_data(6, 50) => trd_data(6, 50),
      trd_data(6, 49) => trd_data(6, 49),
      trd_data(6, 48) => trd_data(6, 48),
      trd_data(6, 47) => trd_data(6, 47),
      trd_data(6, 46) => trd_data(6, 46),
      trd_data(6, 45) => trd_data(6, 45),
      trd_data(6, 44) => trd_data(6, 44),
      trd_data(6, 43) => trd_data(6, 43),
      trd_data(6, 42) => trd_data(6, 42),
      trd_data(6, 41) => trd_data(6, 41),
      trd_data(6, 40) => trd_data(6, 40),
      trd_data(6, 39) => trd_data(6, 39),
      trd_data(6, 38) => trd_data(6, 38),
      trd_data(6, 37) => trd_data(6, 37),
      trd_data(6, 36) => trd_data(6, 36),
      trd_data(6, 35) => trd_data(6, 35),
      trd_data(6, 34) => trd_data(6, 34),
      trd_data(6, 33) => trd_data(6, 33),
      trd_data(6, 32) => trd_data(6, 32),
      trd_data(6, 31) => trd_data(6, 31),
      trd_data(6, 30) => trd_data(6, 30),
      trd_data(6, 29) => trd_data(6, 29),
      trd_data(6, 28) => trd_data(6, 28),
      trd_data(6, 27) => trd_data(6, 27),
      trd_data(6, 26) => trd_data(6, 26),
      trd_data(6, 25) => trd_data(6, 25),
      trd_data(6, 24) => trd_data(6, 24),
      trd_data(6, 23) => trd_data(6, 23),
      trd_data(6, 22) => trd_data(6, 22),
      trd_data(6, 21) => trd_data(6, 21),
      trd_data(6, 20) => trd_data(6, 20),
      trd_data(6, 19) => trd_data(6, 19),
      trd_data(6, 18) => trd_data(6, 18),
      trd_data(6, 17) => trd_data(6, 17),
      trd_data(6, 16) => trd_data(6, 16),
      trd_data(6, 15) => trd_data(6, 15),
      trd_data(6, 14) => trd_data(6, 14),
      trd_data(6, 13) => trd_data(6, 13),
      trd_data(6, 12) => trd_data(6, 12),
      trd_data(6, 11) => trd_data(6, 11),
      trd_data(6, 10) => trd_data(6, 10),
      trd_data(6, 9) => trd_data(6, 9),
      trd_data(6, 8) => trd_data(6, 8),
      trd_data(6, 7) => trd_data(6, 7),
      trd_data(6, 6) => trd_data(6, 6),
      trd_data(6, 5) => trd_data(6, 5),
      trd_data(6, 4) => trd_data(6, 4),
      trd_data(6, 3) => trd_data(6, 3),
      trd_data(6, 2) => trd_data(6, 2),
      trd_data(6, 1) => trd_data(6, 1),
      trd_data(6, 0) => trd_data(6, 0),
      trd_data(5, 63) => trd_data(5, 63),
      trd_data(5, 62) => trd_data(5, 62),
      trd_data(5, 61) => trd_data(5, 61),
      trd_data(5, 60) => trd_data(5, 60),
      trd_data(5, 59) => trd_data(5, 59),
      trd_data(5, 58) => trd_data(5, 58),
      trd_data(5, 57) => trd_data(5, 57),
      trd_data(5, 56) => trd_data(5, 56),
      trd_data(5, 55) => trd_data(5, 55),
      trd_data(5, 54) => trd_data(5, 54),
      trd_data(5, 53) => trd_data(5, 53),
      trd_data(5, 52) => trd_data(5, 52),
      trd_data(5, 51) => trd_data(5, 51),
      trd_data(5, 50) => trd_data(5, 50),
      trd_data(5, 49) => trd_data(5, 49),
      trd_data(5, 48) => trd_data(5, 48),
      trd_data(5, 47) => trd_data(5, 47),
      trd_data(5, 46) => trd_data(5, 46),
      trd_data(5, 45) => trd_data(5, 45),
      trd_data(5, 44) => trd_data(5, 44),
      trd_data(5, 43) => trd_data(5, 43),
      trd_data(5, 42) => trd_data(5, 42),
      trd_data(5, 41) => trd_data(5, 41),
      trd_data(5, 40) => trd_data(5, 40),
      trd_data(5, 39) => trd_data(5, 39),
      trd_data(5, 38) => trd_data(5, 38),
      trd_data(5, 37) => trd_data(5, 37),
      trd_data(5, 36) => trd_data(5, 36),
      trd_data(5, 35) => trd_data(5, 35),
      trd_data(5, 34) => trd_data(5, 34),
      trd_data(5, 33) => trd_data(5, 33),
      trd_data(5, 32) => trd_data(5, 32),
      trd_data(5, 31) => trd_data(5, 31),
      trd_data(5, 30) => trd_data(5, 30),
      trd_data(5, 29) => trd_data(5, 29),
      trd_data(5, 28) => trd_data(5, 28),
      trd_data(5, 27) => trd_data(5, 27),
      trd_data(5, 26) => trd_data(5, 26),
      trd_data(5, 25) => trd_data(5, 25),
      trd_data(5, 24) => trd_data(5, 24),
      trd_data(5, 23) => trd_data(5, 23),
      trd_data(5, 22) => trd_data(5, 22),
      trd_data(5, 21) => trd_data(5, 21),
      trd_data(5, 20) => trd_data(5, 20),
      trd_data(5, 19) => trd_data(5, 19),
      trd_data(5, 18) => trd_data(5, 18),
      trd_data(5, 17) => trd_data(5, 17),
      trd_data(5, 16) => trd_data(5, 16),
      trd_data(5, 15) => trd_data(5, 15),
      trd_data(5, 14) => trd_data(5, 14),
      trd_data(5, 13) => trd_data(5, 13),
      trd_data(5, 12) => trd_data(5, 12),
      trd_data(5, 11) => trd_data(5, 11),
      trd_data(5, 10) => trd_data(5, 10),
      trd_data(5, 9) => trd_data(5, 9),
      trd_data(5, 8) => trd_data(5, 8),
      trd_data(5, 7) => trd_data(5, 7),
      trd_data(5, 6) => trd_data(5, 6),
      trd_data(5, 5) => trd_data(5, 5),
      trd_data(5, 4) => trd_data(5, 4),
      trd_data(5, 3) => trd_data(5, 3),
      trd_data(5, 2) => trd_data(5, 2),
      trd_data(5, 1) => trd_data(5, 1),
      trd_data(5, 0) => trd_data(5, 0),
      trd_data(4, 63) => trd_data(4, 63),
      trd_data(4, 62) => trd_data(4, 62),
      trd_data(4, 61) => trd_data(4, 61),
      trd_data(4, 60) => trd_data(4, 60),
      trd_data(4, 59) => trd_data(4, 59),
      trd_data(4, 58) => trd_data(4, 58),
      trd_data(4, 57) => trd_data(4, 57),
      trd_data(4, 56) => trd_data(4, 56),
      trd_data(4, 55) => trd_data(4, 55),
      trd_data(4, 54) => trd_data(4, 54),
      trd_data(4, 53) => trd_data(4, 53),
      trd_data(4, 52) => trd_data(4, 52),
      trd_data(4, 51) => trd_data(4, 51),
      trd_data(4, 50) => trd_data(4, 50),
      trd_data(4, 49) => trd_data(4, 49),
      trd_data(4, 48) => trd_data(4, 48),
      trd_data(4, 47) => trd_data(4, 47),
      trd_data(4, 46) => trd_data(4, 46),
      trd_data(4, 45) => trd_data(4, 45),
      trd_data(4, 44) => trd_data(4, 44),
      trd_data(4, 43) => trd_data(4, 43),
      trd_data(4, 42) => trd_data(4, 42),
      trd_data(4, 41) => trd_data(4, 41),
      trd_data(4, 40) => trd_data(4, 40),
      trd_data(4, 39) => trd_data(4, 39),
      trd_data(4, 38) => trd_data(4, 38),
      trd_data(4, 37) => trd_data(4, 37),
      trd_data(4, 36) => trd_data(4, 36),
      trd_data(4, 35) => trd_data(4, 35),
      trd_data(4, 34) => trd_data(4, 34),
      trd_data(4, 33) => trd_data(4, 33),
      trd_data(4, 32) => trd_data(4, 32),
      trd_data(4, 31) => trd_data(4, 31),
      trd_data(4, 30) => trd_data(4, 30),
      trd_data(4, 29) => trd_data(4, 29),
      trd_data(4, 28) => trd_data(4, 28),
      trd_data(4, 27) => trd_data(4, 27),
      trd_data(4, 26) => trd_data(4, 26),
      trd_data(4, 25) => trd_data(4, 25),
      trd_data(4, 24) => trd_data(4, 24),
      trd_data(4, 23) => trd_data(4, 23),
      trd_data(4, 22) => trd_data(4, 22),
      trd_data(4, 21) => trd_data(4, 21),
      trd_data(4, 20) => trd_data(4, 20),
      trd_data(4, 19) => trd_data(4, 19),
      trd_data(4, 18) => trd_data(4, 18),
      trd_data(4, 17) => trd_data(4, 17),
      trd_data(4, 16) => trd_data(4, 16),
      trd_data(4, 15) => trd_data(4, 15),
      trd_data(4, 14) => trd_data(4, 14),
      trd_data(4, 13) => trd_data(4, 13),
      trd_data(4, 12) => trd_data(4, 12),
      trd_data(4, 11) => trd_data(4, 11),
      trd_data(4, 10) => trd_data(4, 10),
      trd_data(4, 9) => trd_data(4, 9),
      trd_data(4, 8) => trd_data(4, 8),
      trd_data(4, 7) => trd_data(4, 7),
      trd_data(4, 6) => trd_data(4, 6),
      trd_data(4, 5) => trd_data(4, 5),
      trd_data(4, 4) => trd_data(4, 4),
      trd_data(4, 3) => trd_data(4, 3),
      trd_data(4, 2) => trd_data(4, 2),
      trd_data(4, 1) => trd_data(4, 1),
      trd_data(4, 0) => trd_data(4, 0),
      trd_data(3, 63) => trd_data(3, 63),
      trd_data(3, 62) => trd_data(3, 62),
      trd_data(3, 61) => trd_data(3, 61),
      trd_data(3, 60) => trd_data(3, 60),
      trd_data(3, 59) => trd_data(3, 59),
      trd_data(3, 58) => trd_data(3, 58),
      trd_data(3, 57) => trd_data(3, 57),
      trd_data(3, 56) => trd_data(3, 56),
      trd_data(3, 55) => trd_data(3, 55),
      trd_data(3, 54) => trd_data(3, 54),
      trd_data(3, 53) => trd_data(3, 53),
      trd_data(3, 52) => trd_data(3, 52),
      trd_data(3, 51) => trd_data(3, 51),
      trd_data(3, 50) => trd_data(3, 50),
      trd_data(3, 49) => trd_data(3, 49),
      trd_data(3, 48) => trd_data(3, 48),
      trd_data(3, 47) => trd_data(3, 47),
      trd_data(3, 46) => trd_data(3, 46),
      trd_data(3, 45) => trd_data(3, 45),
      trd_data(3, 44) => trd_data(3, 44),
      trd_data(3, 43) => trd_data(3, 43),
      trd_data(3, 42) => trd_data(3, 42),
      trd_data(3, 41) => trd_data(3, 41),
      trd_data(3, 40) => trd_data(3, 40),
      trd_data(3, 39) => trd_data(3, 39),
      trd_data(3, 38) => trd_data(3, 38),
      trd_data(3, 37) => trd_data(3, 37),
      trd_data(3, 36) => trd_data(3, 36),
      trd_data(3, 35) => trd_data(3, 35),
      trd_data(3, 34) => trd_data(3, 34),
      trd_data(3, 33) => trd_data(3, 33),
      trd_data(3, 32) => trd_data(3, 32),
      trd_data(3, 31) => trd_data(3, 31),
      trd_data(3, 30) => trd_data(3, 30),
      trd_data(3, 29) => trd_data(3, 29),
      trd_data(3, 28) => trd_data(3, 28),
      trd_data(3, 27) => trd_data(3, 27),
      trd_data(3, 26) => trd_data(3, 26),
      trd_data(3, 25) => trd_data(3, 25),
      trd_data(3, 24) => trd_data(3, 24),
      trd_data(3, 23) => trd_data(3, 23),
      trd_data(3, 22) => trd_data(3, 22),
      trd_data(3, 21) => trd_data(3, 21),
      trd_data(3, 20) => trd_data(3, 20),
      trd_data(3, 19) => trd_data(3, 19),
      trd_data(3, 18) => trd_data(3, 18),
      trd_data(3, 17) => trd_data(3, 17),
      trd_data(3, 16) => trd_data(3, 16),
      trd_data(3, 15) => trd_data(3, 15),
      trd_data(3, 14) => trd_data(3, 14),
      trd_data(3, 13) => trd_data(3, 13),
      trd_data(3, 12) => trd_data(3, 12),
      trd_data(3, 11) => trd_data(3, 11),
      trd_data(3, 10) => trd_data(3, 10),
      trd_data(3, 9) => trd_data(3, 9),
      trd_data(3, 8) => trd_data(3, 8),
      trd_data(3, 7) => trd_data(3, 7),
      trd_data(3, 6) => trd_data(3, 6),
      trd_data(3, 5) => trd_data(3, 5),
      trd_data(3, 4) => trd_data(3, 4),
      trd_data(3, 3) => trd_data(3, 3),
      trd_data(3, 2) => trd_data(3, 2),
      trd_data(3, 1) => trd_data(3, 1),
      trd_data(3, 0) => trd_data(3, 0),
      trd_data(2, 63) => trd_data(2, 63),
      trd_data(2, 62) => trd_data(2, 62),
      trd_data(2, 61) => trd_data(2, 61),
      trd_data(2, 60) => trd_data(2, 60),
      trd_data(2, 59) => trd_data(2, 59),
      trd_data(2, 58) => trd_data(2, 58),
      trd_data(2, 57) => trd_data(2, 57),
      trd_data(2, 56) => trd_data(2, 56),
      trd_data(2, 55) => trd_data(2, 55),
      trd_data(2, 54) => trd_data(2, 54),
      trd_data(2, 53) => trd_data(2, 53),
      trd_data(2, 52) => trd_data(2, 52),
      trd_data(2, 51) => trd_data(2, 51),
      trd_data(2, 50) => trd_data(2, 50),
      trd_data(2, 49) => trd_data(2, 49),
      trd_data(2, 48) => trd_data(2, 48),
      trd_data(2, 47) => trd_data(2, 47),
      trd_data(2, 46) => trd_data(2, 46),
      trd_data(2, 45) => trd_data(2, 45),
      trd_data(2, 44) => trd_data(2, 44),
      trd_data(2, 43) => trd_data(2, 43),
      trd_data(2, 42) => trd_data(2, 42),
      trd_data(2, 41) => trd_data(2, 41),
      trd_data(2, 40) => trd_data(2, 40),
      trd_data(2, 39) => trd_data(2, 39),
      trd_data(2, 38) => trd_data(2, 38),
      trd_data(2, 37) => trd_data(2, 37),
      trd_data(2, 36) => trd_data(2, 36),
      trd_data(2, 35) => trd_data(2, 35),
      trd_data(2, 34) => trd_data(2, 34),
      trd_data(2, 33) => trd_data(2, 33),
      trd_data(2, 32) => trd_data(2, 32),
      trd_data(2, 31) => trd_data(2, 31),
      trd_data(2, 30) => trd_data(2, 30),
      trd_data(2, 29) => trd_data(2, 29),
      trd_data(2, 28) => trd_data(2, 28),
      trd_data(2, 27) => trd_data(2, 27),
      trd_data(2, 26) => trd_data(2, 26),
      trd_data(2, 25) => trd_data(2, 25),
      trd_data(2, 24) => trd_data(2, 24),
      trd_data(2, 23) => trd_data(2, 23),
      trd_data(2, 22) => trd_data(2, 22),
      trd_data(2, 21) => trd_data(2, 21),
      trd_data(2, 20) => trd_data(2, 20),
      trd_data(2, 19) => trd_data(2, 19),
      trd_data(2, 18) => trd_data(2, 18),
      trd_data(2, 17) => trd_data(2, 17),
      trd_data(2, 16) => trd_data(2, 16),
      trd_data(2, 15) => trd_data(2, 15),
      trd_data(2, 14) => trd_data(2, 14),
      trd_data(2, 13) => trd_data(2, 13),
      trd_data(2, 12) => trd_data(2, 12),
      trd_data(2, 11) => trd_data(2, 11),
      trd_data(2, 10) => trd_data(2, 10),
      trd_data(2, 9) => trd_data(2, 9),
      trd_data(2, 8) => trd_data(2, 8),
      trd_data(2, 7) => trd_data(2, 7),
      trd_data(2, 6) => trd_data(2, 6),
      trd_data(2, 5) => trd_data(2, 5),
      trd_data(2, 4) => trd_data(2, 4),
      trd_data(2, 3) => trd_data(2, 3),
      trd_data(2, 2) => trd_data(2, 2),
      trd_data(2, 1) => trd_data(2, 1),
      trd_data(2, 0) => trd_data(2, 0),
      trd_data(1, 63) => trd_data(1, 63),
      trd_data(1, 62) => trd_data(1, 62),
      trd_data(1, 61) => trd_data(1, 61),
      trd_data(1, 60) => trd_data(1, 60),
      trd_data(1, 59) => trd_data(1, 59),
      trd_data(1, 58) => trd_data(1, 58),
      trd_data(1, 57) => trd_data(1, 57),
      trd_data(1, 56) => trd_data(1, 56),
      trd_data(1, 55) => trd_data(1, 55),
      trd_data(1, 54) => trd_data(1, 54),
      trd_data(1, 53) => trd_data(1, 53),
      trd_data(1, 52) => trd_data(1, 52),
      trd_data(1, 51) => trd_data(1, 51),
      trd_data(1, 50) => trd_data(1, 50),
      trd_data(1, 49) => trd_data(1, 49),
      trd_data(1, 48) => trd_data(1, 48),
      trd_data(1, 47) => trd_data(1, 47),
      trd_data(1, 46) => trd_data(1, 46),
      trd_data(1, 45) => trd_data(1, 45),
      trd_data(1, 44) => trd_data(1, 44),
      trd_data(1, 43) => trd_data(1, 43),
      trd_data(1, 42) => trd_data(1, 42),
      trd_data(1, 41) => trd_data(1, 41),
      trd_data(1, 40) => trd_data(1, 40),
      trd_data(1, 39) => trd_data(1, 39),
      trd_data(1, 38) => trd_data(1, 38),
      trd_data(1, 37) => trd_data(1, 37),
      trd_data(1, 36) => trd_data(1, 36),
      trd_data(1, 35) => trd_data(1, 35),
      trd_data(1, 34) => trd_data(1, 34),
      trd_data(1, 33) => trd_data(1, 33),
      trd_data(1, 32) => trd_data(1, 32),
      trd_data(1, 31) => trd_data(1, 31),
      trd_data(1, 30) => trd_data(1, 30),
      trd_data(1, 29) => trd_data(1, 29),
      trd_data(1, 28) => trd_data(1, 28),
      trd_data(1, 27) => trd_data(1, 27),
      trd_data(1, 26) => trd_data(1, 26),
      trd_data(1, 25) => trd_data(1, 25),
      trd_data(1, 24) => trd_data(1, 24),
      trd_data(1, 23) => trd_data(1, 23),
      trd_data(1, 22) => trd_data(1, 22),
      trd_data(1, 21) => trd_data(1, 21),
      trd_data(1, 20) => trd_data(1, 20),
      trd_data(1, 19) => trd_data(1, 19),
      trd_data(1, 18) => trd_data(1, 18),
      trd_data(1, 17) => trd_data(1, 17),
      trd_data(1, 16) => trd_data(1, 16),
      trd_data(1, 15) => trd_data(1, 15),
      trd_data(1, 14) => trd_data(1, 14),
      trd_data(1, 13) => trd_data(1, 13),
      trd_data(1, 12) => trd_data(1, 12),
      trd_data(1, 11) => trd_data(1, 11),
      trd_data(1, 10) => trd_data(1, 10),
      trd_data(1, 9) => trd_data(1, 9),
      trd_data(1, 8) => trd_data(1, 8),
      trd_data(1, 7) => trd_data(1, 7),
      trd_data(1, 6) => trd_data(1, 6),
      trd_data(1, 5) => trd_data(1, 5),
      trd_data(1, 4) => trd_data(1, 4),
      trd_data(1, 3) => trd_data(1, 3),
      trd_data(1, 2) => trd_data(1, 2),
      trd_data(1, 1) => trd_data(1, 1),
      trd_data(1, 0) => trd_data(1, 0),
      trd_data(0, 63) => trd_data(0, 63),
      trd_data(0, 62) => trd_data(0, 62),
      trd_data(0, 61) => trd_data(0, 61),
      trd_data(0, 60) => trd_data(0, 60),
      trd_data(0, 59) => trd_data(0, 59),
      trd_data(0, 58) => trd_data(0, 58),
      trd_data(0, 57) => trd_data(0, 57),
      trd_data(0, 56) => trd_data(0, 56),
      trd_data(0, 55) => trd_data(0, 55),
      trd_data(0, 54) => trd_data(0, 54),
      trd_data(0, 53) => trd_data(0, 53),
      trd_data(0, 52) => trd_data(0, 52),
      trd_data(0, 51) => trd_data(0, 51),
      trd_data(0, 50) => trd_data(0, 50),
      trd_data(0, 49) => trd_data(0, 49),
      trd_data(0, 48) => trd_data(0, 48),
      trd_data(0, 47) => trd_data(0, 47),
      trd_data(0, 46) => trd_data(0, 46),
      trd_data(0, 45) => trd_data(0, 45),
      trd_data(0, 44) => trd_data(0, 44),
      trd_data(0, 43) => trd_data(0, 43),
      trd_data(0, 42) => trd_data(0, 42),
      trd_data(0, 41) => trd_data(0, 41),
      trd_data(0, 40) => trd_data(0, 40),
      trd_data(0, 39) => trd_data(0, 39),
      trd_data(0, 38) => trd_data(0, 38),
      trd_data(0, 37) => trd_data(0, 37),
      trd_data(0, 36) => trd_data(0, 36),
      trd_data(0, 35) => trd_data(0, 35),
      trd_data(0, 34) => trd_data(0, 34),
      trd_data(0, 33) => trd_data(0, 33),
      trd_data(0, 32) => trd_data(0, 32),
      trd_data(0, 31) => trd_data(0, 31),
      trd_data(0, 30) => trd_data(0, 30),
      trd_data(0, 29) => trd_data(0, 29),
      trd_data(0, 28) => trd_data(0, 28),
      trd_data(0, 27) => trd_data(0, 27),
      trd_data(0, 26) => trd_data(0, 26),
      trd_data(0, 25) => trd_data(0, 25),
      trd_data(0, 24) => trd_data(0, 24),
      trd_data(0, 23) => trd_data(0, 23),
      trd_data(0, 22) => trd_data(0, 22),
      trd_data(0, 21) => trd_data(0, 21),
      trd_data(0, 20) => trd_data(0, 20),
      trd_data(0, 19) => trd_data(0, 19),
      trd_data(0, 18) => trd_data(0, 18),
      trd_data(0, 17) => trd_data(0, 17),
      trd_data(0, 16) => trd_data(0, 16),
      trd_data(0, 15) => trd_data(0, 15),
      trd_data(0, 14) => trd_data(0, 14),
      trd_data(0, 13) => trd_data(0, 13),
      trd_data(0, 12) => trd_data(0, 12),
      trd_data(0, 11) => trd_data(0, 11),
      trd_data(0, 10) => trd_data(0, 10),
      trd_data(0, 9) => trd_data(0, 9),
      trd_data(0, 8) => trd_data(0, 8),
      trd_data(0, 7) => trd_data(0, 7),
      trd_data(0, 6) => trd_data(0, 6),
      trd_data(0, 5) => trd_data(0, 5),
      trd_data(0, 4) => trd_data(0, 4),
      trd_data(0, 3) => trd_data(0, 3),
      trd_data(0, 2) => trd_data(0, 2),
      trd_data(0, 1) => trd_data(0, 1),
      trd_data(0, 0) => trd_data(0, 0),
      trd_cmd_data(15, 15) => trd_cmd_data(15, 15),
      trd_cmd_data(15, 14) => trd_cmd_data(15, 14),
      trd_cmd_data(15, 13) => trd_cmd_data(15, 13),
      trd_cmd_data(15, 12) => trd_cmd_data(15, 12),
      trd_cmd_data(15, 11) => trd_cmd_data(15, 11),
      trd_cmd_data(15, 10) => trd_cmd_data(15, 10),
      trd_cmd_data(15, 9) => trd_cmd_data(15, 9),
      trd_cmd_data(15, 8) => trd_cmd_data(15, 8),
      trd_cmd_data(15, 7) => trd_cmd_data(15, 7),
      trd_cmd_data(15, 6) => trd_cmd_data(15, 6),
      trd_cmd_data(15, 5) => trd_cmd_data(15, 5),
      trd_cmd_data(15, 4) => trd_cmd_data(15, 4),
      trd_cmd_data(15, 3) => trd_cmd_data(15, 3),
      trd_cmd_data(15, 2) => trd_cmd_data(15, 2),
      trd_cmd_data(15, 1) => trd_cmd_data(15, 1),
      trd_cmd_data(15, 0) => trd_cmd_data(15, 0),
      trd_cmd_data(14, 15) => trd_cmd_data(14, 15),
      trd_cmd_data(14, 14) => trd_cmd_data(14, 14),
      trd_cmd_data(14, 13) => trd_cmd_data(14, 13),
      trd_cmd_data(14, 12) => trd_cmd_data(14, 12),
      trd_cmd_data(14, 11) => trd_cmd_data(14, 11),
      trd_cmd_data(14, 10) => trd_cmd_data(14, 10),
      trd_cmd_data(14, 9) => trd_cmd_data(14, 9),
      trd_cmd_data(14, 8) => trd_cmd_data(14, 8),
      trd_cmd_data(14, 7) => trd_cmd_data(14, 7),
      trd_cmd_data(14, 6) => trd_cmd_data(14, 6),
      trd_cmd_data(14, 5) => trd_cmd_data(14, 5),
      trd_cmd_data(14, 4) => trd_cmd_data(14, 4),
      trd_cmd_data(14, 3) => trd_cmd_data(14, 3),
      trd_cmd_data(14, 2) => trd_cmd_data(14, 2),
      trd_cmd_data(14, 1) => trd_cmd_data(14, 1),
      trd_cmd_data(14, 0) => trd_cmd_data(14, 0),
      trd_cmd_data(13, 15) => trd_cmd_data(13, 15),
      trd_cmd_data(13, 14) => trd_cmd_data(13, 14),
      trd_cmd_data(13, 13) => trd_cmd_data(13, 13),
      trd_cmd_data(13, 12) => trd_cmd_data(13, 12),
      trd_cmd_data(13, 11) => trd_cmd_data(13, 11),
      trd_cmd_data(13, 10) => trd_cmd_data(13, 10),
      trd_cmd_data(13, 9) => trd_cmd_data(13, 9),
      trd_cmd_data(13, 8) => trd_cmd_data(13, 8),
      trd_cmd_data(13, 7) => trd_cmd_data(13, 7),
      trd_cmd_data(13, 6) => trd_cmd_data(13, 6),
      trd_cmd_data(13, 5) => trd_cmd_data(13, 5),
      trd_cmd_data(13, 4) => trd_cmd_data(13, 4),
      trd_cmd_data(13, 3) => trd_cmd_data(13, 3),
      trd_cmd_data(13, 2) => trd_cmd_data(13, 2),
      trd_cmd_data(13, 1) => trd_cmd_data(13, 1),
      trd_cmd_data(13, 0) => trd_cmd_data(13, 0),
      trd_cmd_data(12, 15) => trd_cmd_data(12, 15),
      trd_cmd_data(12, 14) => trd_cmd_data(12, 14),
      trd_cmd_data(12, 13) => trd_cmd_data(12, 13),
      trd_cmd_data(12, 12) => trd_cmd_data(12, 12),
      trd_cmd_data(12, 11) => trd_cmd_data(12, 11),
      trd_cmd_data(12, 10) => trd_cmd_data(12, 10),
      trd_cmd_data(12, 9) => trd_cmd_data(12, 9),
      trd_cmd_data(12, 8) => trd_cmd_data(12, 8),
      trd_cmd_data(12, 7) => trd_cmd_data(12, 7),
      trd_cmd_data(12, 6) => trd_cmd_data(12, 6),
      trd_cmd_data(12, 5) => trd_cmd_data(12, 5),
      trd_cmd_data(12, 4) => trd_cmd_data(12, 4),
      trd_cmd_data(12, 3) => trd_cmd_data(12, 3),
      trd_cmd_data(12, 2) => trd_cmd_data(12, 2),
      trd_cmd_data(12, 1) => trd_cmd_data(12, 1),
      trd_cmd_data(12, 0) => trd_cmd_data(12, 0),
      trd_cmd_data(11, 15) => trd_cmd_data(11, 15),
      trd_cmd_data(11, 14) => trd_cmd_data(11, 14),
      trd_cmd_data(11, 13) => trd_cmd_data(11, 13),
      trd_cmd_data(11, 12) => trd_cmd_data(11, 12),
      trd_cmd_data(11, 11) => trd_cmd_data(11, 11),
      trd_cmd_data(11, 10) => trd_cmd_data(11, 10),
      trd_cmd_data(11, 9) => trd_cmd_data(11, 9),
      trd_cmd_data(11, 8) => trd_cmd_data(11, 8),
      trd_cmd_data(11, 7) => trd_cmd_data(11, 7),
      trd_cmd_data(11, 6) => trd_cmd_data(11, 6),
      trd_cmd_data(11, 5) => trd_cmd_data(11, 5),
      trd_cmd_data(11, 4) => trd_cmd_data(11, 4),
      trd_cmd_data(11, 3) => trd_cmd_data(11, 3),
      trd_cmd_data(11, 2) => trd_cmd_data(11, 2),
      trd_cmd_data(11, 1) => trd_cmd_data(11, 1),
      trd_cmd_data(11, 0) => trd_cmd_data(11, 0),
      trd_cmd_data(10, 15) => trd_cmd_data(10, 15),
      trd_cmd_data(10, 14) => trd_cmd_data(10, 14),
      trd_cmd_data(10, 13) => trd_cmd_data(10, 13),
      trd_cmd_data(10, 12) => trd_cmd_data(10, 12),
      trd_cmd_data(10, 11) => trd_cmd_data(10, 11),
      trd_cmd_data(10, 10) => trd_cmd_data(10, 10),
      trd_cmd_data(10, 9) => trd_cmd_data(10, 9),
      trd_cmd_data(10, 8) => trd_cmd_data(10, 8),
      trd_cmd_data(10, 7) => trd_cmd_data(10, 7),
      trd_cmd_data(10, 6) => trd_cmd_data(10, 6),
      trd_cmd_data(10, 5) => trd_cmd_data(10, 5),
      trd_cmd_data(10, 4) => trd_cmd_data(10, 4),
      trd_cmd_data(10, 3) => trd_cmd_data(10, 3),
      trd_cmd_data(10, 2) => trd_cmd_data(10, 2),
      trd_cmd_data(10, 1) => trd_cmd_data(10, 1),
      trd_cmd_data(10, 0) => trd_cmd_data(10, 0),
      trd_cmd_data(9, 15) => trd_cmd_data(9, 15),
      trd_cmd_data(9, 14) => trd_cmd_data(9, 14),
      trd_cmd_data(9, 13) => trd_cmd_data(9, 13),
      trd_cmd_data(9, 12) => trd_cmd_data(9, 12),
      trd_cmd_data(9, 11) => trd_cmd_data(9, 11),
      trd_cmd_data(9, 10) => trd_cmd_data(9, 10),
      trd_cmd_data(9, 9) => trd_cmd_data(9, 9),
      trd_cmd_data(9, 8) => trd_cmd_data(9, 8),
      trd_cmd_data(9, 7) => trd_cmd_data(9, 7),
      trd_cmd_data(9, 6) => trd_cmd_data(9, 6),
      trd_cmd_data(9, 5) => trd_cmd_data(9, 5),
      trd_cmd_data(9, 4) => trd_cmd_data(9, 4),
      trd_cmd_data(9, 3) => trd_cmd_data(9, 3),
      trd_cmd_data(9, 2) => trd_cmd_data(9, 2),
      trd_cmd_data(9, 1) => trd_cmd_data(9, 1),
      trd_cmd_data(9, 0) => trd_cmd_data(9, 0),
      trd_cmd_data(8, 15) => trd_cmd_data(8, 15),
      trd_cmd_data(8, 14) => trd_cmd_data(8, 14),
      trd_cmd_data(8, 13) => trd_cmd_data(8, 13),
      trd_cmd_data(8, 12) => trd_cmd_data(8, 12),
      trd_cmd_data(8, 11) => trd_cmd_data(8, 11),
      trd_cmd_data(8, 10) => trd_cmd_data(8, 10),
      trd_cmd_data(8, 9) => trd_cmd_data(8, 9),
      trd_cmd_data(8, 8) => trd_cmd_data(8, 8),
      trd_cmd_data(8, 7) => trd_cmd_data(8, 7),
      trd_cmd_data(8, 6) => trd_cmd_data(8, 6),
      trd_cmd_data(8, 5) => trd_cmd_data(8, 5),
      trd_cmd_data(8, 4) => trd_cmd_data(8, 4),
      trd_cmd_data(8, 3) => trd_cmd_data(8, 3),
      trd_cmd_data(8, 2) => trd_cmd_data(8, 2),
      trd_cmd_data(8, 1) => trd_cmd_data(8, 1),
      trd_cmd_data(8, 0) => trd_cmd_data(8, 0),
      trd_cmd_data(7, 15) => trd_cmd_data(7, 15),
      trd_cmd_data(7, 14) => trd_cmd_data(7, 14),
      trd_cmd_data(7, 13) => trd_cmd_data(7, 13),
      trd_cmd_data(7, 12) => trd_cmd_data(7, 12),
      trd_cmd_data(7, 11) => trd_cmd_data(7, 11),
      trd_cmd_data(7, 10) => trd_cmd_data(7, 10),
      trd_cmd_data(7, 9) => trd_cmd_data(7, 9),
      trd_cmd_data(7, 8) => trd_cmd_data(7, 8),
      trd_cmd_data(7, 7) => trd_cmd_data(7, 7),
      trd_cmd_data(7, 6) => trd_cmd_data(7, 6),
      trd_cmd_data(7, 5) => trd_cmd_data(7, 5),
      trd_cmd_data(7, 4) => trd_cmd_data(7, 4),
      trd_cmd_data(7, 3) => trd_cmd_data(7, 3),
      trd_cmd_data(7, 2) => trd_cmd_data(7, 2),
      trd_cmd_data(7, 1) => trd_cmd_data(7, 1),
      trd_cmd_data(7, 0) => trd_cmd_data(7, 0),
      trd_cmd_data(6, 15) => trd_cmd_data(6, 15),
      trd_cmd_data(6, 14) => trd_cmd_data(6, 14),
      trd_cmd_data(6, 13) => trd_cmd_data(6, 13),
      trd_cmd_data(6, 12) => trd_cmd_data(6, 12),
      trd_cmd_data(6, 11) => trd_cmd_data(6, 11),
      trd_cmd_data(6, 10) => trd_cmd_data(6, 10),
      trd_cmd_data(6, 9) => trd_cmd_data(6, 9),
      trd_cmd_data(6, 8) => trd_cmd_data(6, 8),
      trd_cmd_data(6, 7) => trd_cmd_data(6, 7),
      trd_cmd_data(6, 6) => trd_cmd_data(6, 6),
      trd_cmd_data(6, 5) => trd_cmd_data(6, 5),
      trd_cmd_data(6, 4) => trd_cmd_data(6, 4),
      trd_cmd_data(6, 3) => trd_cmd_data(6, 3),
      trd_cmd_data(6, 2) => trd_cmd_data(6, 2),
      trd_cmd_data(6, 1) => trd_cmd_data(6, 1),
      trd_cmd_data(6, 0) => trd_cmd_data(6, 0),
      trd_cmd_data(5, 15) => trd_cmd_data(5, 15),
      trd_cmd_data(5, 14) => trd_cmd_data(5, 14),
      trd_cmd_data(5, 13) => trd_cmd_data(5, 13),
      trd_cmd_data(5, 12) => trd_cmd_data(5, 12),
      trd_cmd_data(5, 11) => trd_cmd_data(5, 11),
      trd_cmd_data(5, 10) => trd_cmd_data(5, 10),
      trd_cmd_data(5, 9) => trd_cmd_data(5, 9),
      trd_cmd_data(5, 8) => trd_cmd_data(5, 8),
      trd_cmd_data(5, 7) => trd_cmd_data(5, 7),
      trd_cmd_data(5, 6) => trd_cmd_data(5, 6),
      trd_cmd_data(5, 5) => trd_cmd_data(5, 5),
      trd_cmd_data(5, 4) => trd_cmd_data(5, 4),
      trd_cmd_data(5, 3) => trd_cmd_data(5, 3),
      trd_cmd_data(5, 2) => trd_cmd_data(5, 2),
      trd_cmd_data(5, 1) => trd_cmd_data(5, 1),
      trd_cmd_data(5, 0) => trd_cmd_data(5, 0),
      trd_cmd_data(4, 15) => trd_cmd_data(4, 15),
      trd_cmd_data(4, 14) => trd_cmd_data(4, 14),
      trd_cmd_data(4, 13) => trd_cmd_data(4, 13),
      trd_cmd_data(4, 12) => trd_cmd_data(4, 12),
      trd_cmd_data(4, 11) => trd_cmd_data(4, 11),
      trd_cmd_data(4, 10) => trd_cmd_data(4, 10),
      trd_cmd_data(4, 9) => trd_cmd_data(4, 9),
      trd_cmd_data(4, 8) => trd_cmd_data(4, 8),
      trd_cmd_data(4, 7) => trd_cmd_data(4, 7),
      trd_cmd_data(4, 6) => trd_cmd_data(4, 6),
      trd_cmd_data(4, 5) => trd_cmd_data(4, 5),
      trd_cmd_data(4, 4) => trd_cmd_data(4, 4),
      trd_cmd_data(4, 3) => trd_cmd_data(4, 3),
      trd_cmd_data(4, 2) => trd_cmd_data(4, 2),
      trd_cmd_data(4, 1) => trd_cmd_data(4, 1),
      trd_cmd_data(4, 0) => trd_cmd_data(4, 0),
      trd_cmd_data(3, 15) => trd_cmd_data(3, 15),
      trd_cmd_data(3, 14) => trd_cmd_data(3, 14),
      trd_cmd_data(3, 13) => trd_cmd_data(3, 13),
      trd_cmd_data(3, 12) => trd_cmd_data(3, 12),
      trd_cmd_data(3, 11) => trd_cmd_data(3, 11),
      trd_cmd_data(3, 10) => trd_cmd_data(3, 10),
      trd_cmd_data(3, 9) => trd_cmd_data(3, 9),
      trd_cmd_data(3, 8) => trd_cmd_data(3, 8),
      trd_cmd_data(3, 7) => trd_cmd_data(3, 7),
      trd_cmd_data(3, 6) => trd_cmd_data(3, 6),
      trd_cmd_data(3, 5) => trd_cmd_data(3, 5),
      trd_cmd_data(3, 4) => trd_cmd_data(3, 4),
      trd_cmd_data(3, 3) => trd_cmd_data(3, 3),
      trd_cmd_data(3, 2) => trd_cmd_data(3, 2),
      trd_cmd_data(3, 1) => trd_cmd_data(3, 1),
      trd_cmd_data(3, 0) => trd_cmd_data(3, 0),
      trd_cmd_data(2, 15) => trd_cmd_data(2, 15),
      trd_cmd_data(2, 14) => trd_cmd_data(2, 14),
      trd_cmd_data(2, 13) => trd_cmd_data(2, 13),
      trd_cmd_data(2, 12) => trd_cmd_data(2, 12),
      trd_cmd_data(2, 11) => trd_cmd_data(2, 11),
      trd_cmd_data(2, 10) => trd_cmd_data(2, 10),
      trd_cmd_data(2, 9) => trd_cmd_data(2, 9),
      trd_cmd_data(2, 8) => trd_cmd_data(2, 8),
      trd_cmd_data(2, 7) => trd_cmd_data(2, 7),
      trd_cmd_data(2, 6) => trd_cmd_data(2, 6),
      trd_cmd_data(2, 5) => trd_cmd_data(2, 5),
      trd_cmd_data(2, 4) => trd_cmd_data(2, 4),
      trd_cmd_data(2, 3) => trd_cmd_data(2, 3),
      trd_cmd_data(2, 2) => trd_cmd_data(2, 2),
      trd_cmd_data(2, 1) => trd_cmd_data(2, 1),
      trd_cmd_data(2, 0) => trd_cmd_data(2, 0),
      trd_cmd_data(1, 15) => trd_cmd_data(1, 15),
      trd_cmd_data(1, 14) => trd_cmd_data(1, 14),
      trd_cmd_data(1, 13) => trd_cmd_data(1, 13),
      trd_cmd_data(1, 12) => trd_cmd_data(1, 12),
      trd_cmd_data(1, 11) => trd_cmd_data(1, 11),
      trd_cmd_data(1, 10) => trd_cmd_data(1, 10),
      trd_cmd_data(1, 9) => trd_cmd_data(1, 9),
      trd_cmd_data(1, 8) => trd_cmd_data(1, 8),
      trd_cmd_data(1, 7) => trd_cmd_data(1, 7),
      trd_cmd_data(1, 6) => trd_cmd_data(1, 6),
      trd_cmd_data(1, 5) => trd_cmd_data(1, 5),
      trd_cmd_data(1, 4) => trd_cmd_data(1, 4),
      trd_cmd_data(1, 3) => trd_cmd_data(1, 3),
      trd_cmd_data(1, 2) => trd_cmd_data(1, 2),
      trd_cmd_data(1, 1) => trd_cmd_data(1, 1),
      trd_cmd_data(1, 0) => trd_cmd_data(1, 0),
      trd_cmd_data(0, 15) => trd_cmd_data(0, 15),
      trd_cmd_data(0, 14) => trd_cmd_data(0, 14),
      trd_cmd_data(0, 13) => trd_cmd_data(0, 13),
      trd_cmd_data(0, 12) => trd_cmd_data(0, 12),
      trd_cmd_data(0, 11) => trd_cmd_data(0, 11),
      trd_cmd_data(0, 10) => trd_cmd_data(0, 10),
      trd_cmd_data(0, 9) => trd_cmd_data(0, 9),
      trd_cmd_data(0, 8) => trd_cmd_data(0, 8),
      trd_cmd_data(0, 7) => trd_cmd_data(0, 7),
      trd_cmd_data(0, 6) => trd_cmd_data(0, 6),
      trd_cmd_data(0, 5) => trd_cmd_data(0, 5),
      trd_cmd_data(0, 4) => trd_cmd_data(0, 4),
      trd_cmd_data(0, 3) => trd_cmd_data(0, 3),
      trd_cmd_data(0, 2) => trd_cmd_data(0, 2),
      trd_cmd_data(0, 1) => trd_cmd_data(0, 1),
      trd_cmd_data(0, 0) => trd_cmd_data(0, 0),
      lc_host_data(63) => lc_host_data(63),
      lc_host_data(62) => lc_host_data(62),
      lc_host_data(61) => lc_host_data(61),
      lc_host_data(60) => lc_host_data(60),
      lc_host_data(59) => lc_host_data(59),
      lc_host_data(58) => lc_host_data(58),
      lc_host_data(57) => lc_host_data(57),
      lc_host_data(56) => lc_host_data(56),
      lc_host_data(55) => lc_host_data(55),
      lc_host_data(54) => lc_host_data(54),
      lc_host_data(53) => lc_host_data(53),
      lc_host_data(52) => lc_host_data(52),
      lc_host_data(51) => lc_host_data(51),
      lc_host_data(50) => lc_host_data(50),
      lc_host_data(49) => lc_host_data(49),
      lc_host_data(48) => lc_host_data(48),
      lc_host_data(47) => lc_host_data(47),
      lc_host_data(46) => lc_host_data(46),
      lc_host_data(45) => lc_host_data(45),
      lc_host_data(44) => lc_host_data(44),
      lc_host_data(43) => lc_host_data(43),
      lc_host_data(42) => lc_host_data(42),
      lc_host_data(41) => lc_host_data(41),
      lc_host_data(40) => lc_host_data(40),
      lc_host_data(39) => lc_host_data(39),
      lc_host_data(38) => lc_host_data(38),
      lc_host_data(37) => lc_host_data(37),
      lc_host_data(36) => lc_host_data(36),
      lc_host_data(35) => lc_host_data(35),
      lc_host_data(34) => lc_host_data(34),
      lc_host_data(33) => lc_host_data(33),
      lc_host_data(32) => lc_host_data(32),
      lc_host_data(31) => lc_host_data(31),
      lc_host_data(30) => lc_host_data(30),
      lc_host_data(29) => lc_host_data(29),
      lc_host_data(28) => lc_host_data(28),
      lc_host_data(27) => lc_host_data(27),
      lc_host_data(26) => lc_host_data(26),
      lc_host_data(25) => lc_host_data(25),
      lc_host_data(24) => lc_host_data(24),
      lc_host_data(23) => lc_host_data(23),
      lc_host_data(22) => lc_host_data(22),
      lc_host_data(21) => lc_host_data(21),
      lc_host_data(20) => lc_host_data(20),
      lc_host_data(19) => lc_host_data(19),
      lc_host_data(18) => lc_host_data(18),
      lc_host_data(17) => lc_host_data(17),
      lc_host_data(16) => lc_host_data(16),
      lc_host_data(15) => lc_host_data(15),
      lc_host_data(14) => lc_host_data(14),
      lc_host_data(13) => lc_host_data(13),
      lc_host_data(12) => lc_host_data(12),
      lc_host_data(11) => lc_host_data(11),
      lc_host_data(10) => lc_host_data(10),
      lc_host_data(9) => lc_host_data(9),
      lc_host_data(8) => lc_host_data(8),
      lc_host_data(7) => lc_host_data(7),
      lc_host_data(6) => lc_host_data(6),
      lc_host_data(5) => lc_host_data(5),
      lc_host_data(4) => lc_host_data(4),
      lc_host_data(3) => lc_host_data(3),
      lc_host_data(2) => lc_host_data(2),
      lc_host_data(1) => lc_host_data(1),
      lc_host_data(0) => lc_host_data(0),
      trd_reset_fifo(15) => trd_reset_fifo(15),
      trd_reset_fifo(14) => trd_reset_fifo(14),
      trd_reset_fifo(13) => trd_reset_fifo(13),
      trd_reset_fifo(12) => trd_reset_fifo(12),
      trd_reset_fifo(11) => trd_reset_fifo(11),
      trd_reset_fifo(10) => trd_reset_fifo(10),
      trd_reset_fifo(9) => trd_reset_fifo(9),
      trd_reset_fifo(8) => trd_reset_fifo(8),
      trd_reset_fifo(7) => trd_reset_fifo(7),
      trd_reset_fifo(6) => trd_reset_fifo(6),
      trd_reset_fifo(5) => trd_reset_fifo(5),
      trd_reset_fifo(4) => trd_reset_fifo(4),
      trd_reset_fifo(3) => trd_reset_fifo(3),
      trd_reset_fifo(2) => trd_reset_fifo(2),
      trd_reset_fifo(1) => trd_reset_fifo(1),
      trd_reset_fifo(0) => trd_reset_fifo(0),
      lc_adr(6) => lc_adr(17),
      lc_adr(5) => lc_adr(16),
      lc_adr(4) => lc_adr(15),
      lc_adr(3) => lc_adr(14),
      lc_adr(2) => lc_adr(13),
      lc_adr(1) => lc_adr(12),
      lc_adr(0) => lc_adr(11)
    );
  gen_syn_pcie : pcie_core64_m2
    port map (
      clk => NlwRenamedSig_OI_clk,
      lc_irq => irq1,
      mgt250 => mgt250,
      lc_rd => lc_rd,
      clk250_out => NlwRenamedSig_OI_clk,
      lc_wr => lc_wr,
      pcie_link_up => pcie_link_up,
      clk_lock => NlwRenamedSig_OI_clk_lock_out,
      reset_out => NlwRenamedSig_OI_led_h4,
      perst => perst,
      dcm_rstp => dcm_rstp,
      lc_host_data(63) => lc_host_data(63),
      lc_host_data(62) => lc_host_data(62),
      lc_host_data(61) => lc_host_data(61),
      lc_host_data(60) => lc_host_data(60),
      lc_host_data(59) => lc_host_data(59),
      lc_host_data(58) => lc_host_data(58),
      lc_host_data(57) => lc_host_data(57),
      lc_host_data(56) => lc_host_data(56),
      lc_host_data(55) => lc_host_data(55),
      lc_host_data(54) => lc_host_data(54),
      lc_host_data(53) => lc_host_data(53),
      lc_host_data(52) => lc_host_data(52),
      lc_host_data(51) => lc_host_data(51),
      lc_host_data(50) => lc_host_data(50),
      lc_host_data(49) => lc_host_data(49),
      lc_host_data(48) => lc_host_data(48),
      lc_host_data(47) => lc_host_data(47),
      lc_host_data(46) => lc_host_data(46),
      lc_host_data(45) => lc_host_data(45),
      lc_host_data(44) => lc_host_data(44),
      lc_host_data(43) => lc_host_data(43),
      lc_host_data(42) => lc_host_data(42),
      lc_host_data(41) => lc_host_data(41),
      lc_host_data(40) => lc_host_data(40),
      lc_host_data(39) => lc_host_data(39),
      lc_host_data(38) => lc_host_data(38),
      lc_host_data(37) => lc_host_data(37),
      lc_host_data(36) => lc_host_data(36),
      lc_host_data(35) => lc_host_data(35),
      lc_host_data(34) => lc_host_data(34),
      lc_host_data(33) => lc_host_data(33),
      lc_host_data(32) => lc_host_data(32),
      lc_host_data(31) => lc_host_data(31),
      lc_host_data(30) => lc_host_data(30),
      lc_host_data(29) => lc_host_data(29),
      lc_host_data(28) => lc_host_data(28),
      lc_host_data(27) => lc_host_data(27),
      lc_host_data(26) => lc_host_data(26),
      lc_host_data(25) => lc_host_data(25),
      lc_host_data(24) => lc_host_data(24),
      lc_host_data(23) => lc_host_data(23),
      lc_host_data(22) => lc_host_data(22),
      lc_host_data(21) => lc_host_data(21),
      lc_host_data(20) => lc_host_data(20),
      lc_host_data(19) => lc_host_data(19),
      lc_host_data(18) => lc_host_data(18),
      lc_host_data(17) => lc_host_data(17),
      lc_host_data(16) => lc_host_data(16),
      lc_host_data(15) => lc_host_data(15),
      lc_host_data(14) => lc_host_data(14),
      lc_host_data(13) => lc_host_data(13),
      lc_host_data(12) => lc_host_data(12),
      lc_host_data(11) => lc_host_data(11),
      lc_host_data(10) => lc_host_data(10),
      lc_host_data(9) => lc_host_data(9),
      lc_host_data(8) => lc_host_data(8),
      lc_host_data(7) => lc_host_data(7),
      lc_host_data(6) => lc_host_data(6),
      lc_host_data(5) => lc_host_data(5),
      lc_host_data(4) => lc_host_data(4),
      lc_host_data(3) => lc_host_data(3),
      lc_host_data(2) => lc_host_data(2),
      lc_host_data(1) => lc_host_data(1),
      lc_host_data(0) => lc_host_data(0),
      px(7) => NLW_gen_syn_pcie_px_7_UNCONNECTED,
      px(6) => NLW_gen_syn_pcie_px_6_UNCONNECTED,
      px(5) => NLW_gen_syn_pcie_px_5_UNCONNECTED,
      px(4) => NLW_gen_syn_pcie_px_4_UNCONNECTED,
      px(3) => NLW_gen_syn_pcie_px_3_UNCONNECTED,
      px(2) => p(3),
      px(1) => p(2),
      px(0) => p(1),
      txn(7) => txn(7),
      txn(6) => txn(6),
      txn(5) => txn(5),
      txn(4) => txn(4),
      txn(3) => txn(3),
      txn(2) => txn(2),
      txn(1) => txn(1),
      txn(0) => txn(0),
      txp(7) => txp(7),
      txp(6) => txp(6),
      txp(5) => txp(5),
      txp(4) => txp(4),
      txp(3) => txp(3),
      txp(2) => txp(2),
      txp(1) => txp(1),
      txp(0) => txp(0),
      lc_adr(31) => NLW_gen_syn_pcie_lc_adr_31_UNCONNECTED,
      lc_adr(30) => NLW_gen_syn_pcie_lc_adr_30_UNCONNECTED,
      lc_adr(29) => NLW_gen_syn_pcie_lc_adr_29_UNCONNECTED,
      lc_adr(28) => NLW_gen_syn_pcie_lc_adr_28_UNCONNECTED,
      lc_adr(27) => NLW_gen_syn_pcie_lc_adr_27_UNCONNECTED,
      lc_adr(26) => NLW_gen_syn_pcie_lc_adr_26_UNCONNECTED,
      lc_adr(25) => NLW_gen_syn_pcie_lc_adr_25_UNCONNECTED,
      lc_adr(24) => NLW_gen_syn_pcie_lc_adr_24_UNCONNECTED,
      lc_adr(23) => NLW_gen_syn_pcie_lc_adr_23_UNCONNECTED,
      lc_adr(22) => NLW_gen_syn_pcie_lc_adr_22_UNCONNECTED,
      lc_adr(21) => NLW_gen_syn_pcie_lc_adr_21_UNCONNECTED,
      lc_adr(20) => NLW_gen_syn_pcie_lc_adr_20_UNCONNECTED,
      lc_adr(19) => NLW_gen_syn_pcie_lc_adr_19_UNCONNECTED,
      lc_adr(18) => NLW_gen_syn_pcie_lc_adr_18_UNCONNECTED,
      lc_adr(17) => lc_adr(17),
      lc_adr(16) => lc_adr(16),
      lc_adr(15) => lc_adr(15),
      lc_adr(14) => lc_adr(14),
      lc_adr(13) => lc_adr(13),
      lc_adr(12) => lc_adr(12),
      lc_adr(11) => lc_adr(11),
      lc_adr(10) => NLW_gen_syn_pcie_lc_adr_10_UNCONNECTED,
      lc_adr(9) => NLW_gen_syn_pcie_lc_adr_9_UNCONNECTED,
      lc_adr(8) => NLW_gen_syn_pcie_lc_adr_8_UNCONNECTED,
      lc_adr(7) => NLW_gen_syn_pcie_lc_adr_7_UNCONNECTED,
      lc_adr(6) => NLW_gen_syn_pcie_lc_adr_6_UNCONNECTED,
      lc_adr(5) => NLW_gen_syn_pcie_lc_adr_5_UNCONNECTED,
      lc_adr(4) => NLW_gen_syn_pcie_lc_adr_4_UNCONNECTED,
      lc_adr(3) => NLW_gen_syn_pcie_lc_adr_3_UNCONNECTED,
      lc_adr(2) => NLW_gen_syn_pcie_lc_adr_2_UNCONNECTED,
      lc_adr(1) => NLW_gen_syn_pcie_lc_adr_1_UNCONNECTED,
      lc_adr(0) => NLW_gen_syn_pcie_lc_adr_0_UNCONNECTED,
      pcie_lstatus(15) => pcie_lstatus(15),
      pcie_lstatus(14) => pcie_lstatus(14),
      pcie_lstatus(13) => pcie_lstatus(13),
      pcie_lstatus(12) => pcie_lstatus(12),
      pcie_lstatus(11) => pcie_lstatus(11),
      pcie_lstatus(10) => pcie_lstatus(10),
      pcie_lstatus(9) => pcie_lstatus(9),
      pcie_lstatus(8) => pcie_lstatus(8),
      pcie_lstatus(7) => pcie_lstatus(7),
      pcie_lstatus(6) => pcie_lstatus(6),
      pcie_lstatus(5) => pcie_lstatus(5),
      pcie_lstatus(4) => pcie_lstatus(4),
      pcie_lstatus(3) => pcie_lstatus(3),
      pcie_lstatus(2) => pcie_lstatus(2),
      pcie_lstatus(1) => pcie_lstatus(1),
      pcie_lstatus(0) => pcie_lstatus(0),
      rxn(7) => rxn(7),
      rxn(6) => rxn(6),
      rxn(5) => rxn(5),
      rxn(4) => rxn(4),
      rxn(3) => rxn(3),
      rxn(2) => rxn(2),
      rxn(1) => rxn(1),
      rxn(0) => rxn(0),
      lc_data(63) => lc_data(63),
      lc_data(62) => lc_data(62),
      lc_data(61) => lc_data(61),
      lc_data(60) => lc_data(60),
      lc_data(59) => lc_data(59),
      lc_data(58) => lc_data(58),
      lc_data(57) => lc_data(57),
      lc_data(56) => lc_data(56),
      lc_data(55) => lc_data(55),
      lc_data(54) => lc_data(54),
      lc_data(53) => lc_data(53),
      lc_data(52) => lc_data(52),
      lc_data(51) => lc_data(51),
      lc_data(50) => lc_data(50),
      lc_data(49) => lc_data(49),
      lc_data(48) => lc_data(48),
      lc_data(47) => lc_data(47),
      lc_data(46) => lc_data(46),
      lc_data(45) => lc_data(45),
      lc_data(44) => lc_data(44),
      lc_data(43) => lc_data(43),
      lc_data(42) => lc_data(42),
      lc_data(41) => lc_data(41),
      lc_data(40) => lc_data(40),
      lc_data(39) => lc_data(39),
      lc_data(38) => lc_data(38),
      lc_data(37) => lc_data(37),
      lc_data(36) => lc_data(36),
      lc_data(35) => lc_data(35),
      lc_data(34) => lc_data(34),
      lc_data(33) => lc_data(33),
      lc_data(32) => lc_data(32),
      lc_data(31) => lc_data(31),
      lc_data(30) => lc_data(30),
      lc_data(29) => lc_data(29),
      lc_data(28) => lc_data(28),
      lc_data(27) => lc_data(27),
      lc_data(26) => lc_data(26),
      lc_data(25) => lc_data(25),
      lc_data(24) => lc_data(24),
      lc_data(23) => lc_data(23),
      lc_data(22) => lc_data(22),
      lc_data(21) => lc_data(21),
      lc_data(20) => lc_data(20),
      lc_data(19) => lc_data(19),
      lc_data(18) => lc_data(18),
      lc_data(17) => lc_data(17),
      lc_data(16) => lc_data(16),
      lc_data(15) => lc_data(15),
      lc_data(14) => lc_data(14),
      lc_data(13) => lc_data(13),
      lc_data(12) => lc_data(12),
      lc_data(11) => lc_data(11),
      lc_data(10) => lc_data(10),
      lc_data(9) => lc_data(9),
      lc_data(8) => lc_data(8),
      lc_data(7) => lc_data(7),
      lc_data(6) => lc_data(6),
      lc_data(5) => lc_data(5),
      lc_data(4) => lc_data(4),
      lc_data(3) => lc_data(3),
      lc_data(2) => lc_data(2),
      lc_data(1) => lc_data(1),
      lc_data(0) => lc_data(0),
      rxp(7) => rxp(7),
      rxp(6) => rxp(6),
      rxp(5) => rxp(5),
      rxp(4) => rxp(4),
      rxp(3) => rxp(3),
      rxp(2) => rxp(2),
      rxp(1) => rxp(1),
      rxp(0) => rxp(0),
      lc_dma_req(1) => dmar1,
      lc_dma_req(0) => dmar0
    );
  cnt30ce11 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => cnt30k0,
      I1 => cnt30start1_33896,
      I2 => cnt30start_33895,
      O => cnt30ce1
    );
  cnt30ce21 : LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      I0 => cnt30k0,
      I1 => cnt30k1,
      I2 => cnt30start_33895,
      I3 => cnt30start1_33896,
      O => cnt30ce2
    );
  cnt30i21 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => NlwRenamedSig_OI_clk30k,
      I1 => cnt30start_33895,
      O => cnt30i2
    );
  cnt30i11 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => cnt30k1,
      I1 => cnt30start_33895,
      I2 => cnt30start1_33896,
      O => cnt30i1
    );
  cnt30i01 : LUT3
    generic map(
      INIT => X"32"
    )
    port map (
      I0 => cnt30k0,
      I1 => cnt30start_33895,
      I2 => cnt30start1_33896,
      O => cnt30i0
    );
  led_h31 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => dmar0,
      I1 => NlwRenamedSig_OI_led_h4,
      O => led_h3
    );
  led_h21 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => dmar1,
      I1 => NlwRenamedSig_OI_led_h4,
      O => led_h2
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_fifo_control_v2_INST_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    read : in STD_LOGIC := 'X'; 
    ef : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    empty : in STD_LOGIC := 'X'; 
    rd : out STD_LOGIC; 
    we : out STD_LOGIC 
  );
end cl_fifo_control_v2_INST_1;

architecture STRUCTURE of cl_fifo_control_v2_INST_1 is
  signal N2 : STD_LOGIC; 
  signal empty1_6869 : STD_LOGIC; 
  signal rd1_6871 : STD_LOGIC; 
  signal st_FSM_Acst_FSM_inv : STD_LOGIC; 
  signal st_FSM_FFd1_6875 : STD_LOGIC; 
  signal st_FSM_FFd1_In : STD_LOGIC; 
  signal st_FSM_FFd2_6877 : STD_LOGIC; 
  signal st_FSM_FFd2_In : STD_LOGIC; 
  signal st_FSM_FFd3_6879 : STD_LOGIC; 
  signal st_FSM_FFd4_6880 : STD_LOGIC; 
  signal st_FSM_FFd5_6881 : STD_LOGIC; 
  signal st_FSM_FFd5_In : STD_LOGIC; 
  signal st_FSM_FFd6_6883 : STD_LOGIC; 
  signal st_FSM_FFd6_In : STD_LOGIC; 
begin
  empty1 : FD
    port map (
      C => clk,
      D => empty,
      Q => empty1_6869
    );
  st_FSM_FFd1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd1_In,
      Q => st_FSM_FFd1_6875
    );
  st_FSM_FFd2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd2_In,
      Q => st_FSM_FFd2_6877
    );
  st_FSM_FFd6 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => st_FSM_FFd6_In,
      PRE => st_FSM_Acst_FSM_inv,
      Q => st_FSM_FFd6_6883
    );
  st_FSM_FFd5 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd5_In,
      Q => st_FSM_FFd5_6881
    );
  st_FSM_FFd4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd5_6881,
      Q => st_FSM_FFd4_6880
    );
  st_FSM_FFd3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd4_6880,
      Q => st_FSM_FFd3_6879
    );
  st_FSM_FFd5_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => empty,
      I1 => st_FSM_FFd6_6883,
      O => st_FSM_FFd5_In
    );
  st_FSM_FFd6_In1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => empty,
      I1 => st_FSM_FFd6_6883,
      I2 => read,
      I3 => st_FSM_FFd1_6875,
      O => st_FSM_FFd6_In
    );
  st_FSM_FFd2_In1 : LUT6
    generic map(
      INIT => X"DD55FF55CC40FF40"
    )
    port map (
      I0 => empty1_6869,
      I1 => read,
      I2 => st_FSM_FFd1_6875,
      I3 => st_FSM_FFd2_6877,
      I4 => empty,
      I5 => st_FSM_FFd3_6879,
      O => st_FSM_FFd2_In
    );
  st_FSM_FFd1_In1 : LUT6
    generic map(
      INIT => X"AF8FA888A888A888"
    )
    port map (
      I0 => empty1_6869,
      I1 => st_FSM_FFd3_6879,
      I2 => read,
      I3 => st_FSM_FFd1_6875,
      I4 => st_FSM_FFd2_6877,
      I5 => empty,
      O => st_FSM_FFd1_In
    );
  we1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => st_FSM_FFd4_6880,
      I1 => read,
      I2 => st_FSM_FFd2_6877,
      O => we
    );
  ef1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => st_FSM_FFd1_6875,
      I1 => st_FSM_FFd2_6877,
      O => ef
    );
  st_FSM_Acst_FSM_inv1_INV_0 : INV
    port map (
      I => reset,
      O => st_FSM_Acst_FSM_inv
    );
  XST_VCC : VCC
    port map (
      P => N2
    );
  rd1 : LUT6
    generic map(
      INIT => X"0F085F5D0F080F08"
    )
    port map (
      I0 => read,
      I1 => st_FSM_FFd1_6875,
      I2 => empty1_6869,
      I3 => st_FSM_FFd3_6879,
      I4 => empty,
      I5 => st_FSM_FFd2_6877,
      O => rd1_6871
    );
  rd_f7 : MUXF7
    port map (
      I0 => rd1_6871,
      I1 => N2,
      S => st_FSM_FFd5_6881,
      O => rd
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_fifo1024x65_v5_INST_1 is
  port (
    flag_rd_ef : out STD_LOGIC; 
    flag_rd_ff : out STD_LOGIC; 
    flag_rd_hf : out STD_LOGIC; 
    flag_wr_und : out STD_LOGIC; 
    flag_wr_pae : out STD_LOGIC; 
    flag_wr_paf : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : in STD_LOGIC := 'X'; 
    data_en : in STD_LOGIC := 'X'; 
    data_inx : in STD_LOGIC := 'X'; 
    flag_wr_ef : out STD_LOGIC; 
    clk_rd : in STD_LOGIC := 'X'; 
    flag_wr_ff : out STD_LOGIC; 
    flag_rd_ovr : out STD_LOGIC; 
    flag_wr_hf : out STD_LOGIC; 
    data_outx : out STD_LOGIC; 
    clk_wr : in STD_LOGIC := 'X'; 
    flag_wr_ovr : out STD_LOGIC; 
    flag_empty : out STD_LOGIC; 
    flag_rd_und : out STD_LOGIC; 
    flag_rd_pae : out STD_LOGIC; 
    flag_rd_paf : out STD_LOGIC; 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end cl_fifo1024x65_v5_INST_1;

architecture STRUCTURE of cl_fifo1024x65_v5_INST_1 is
  component ctrl_fifo1024x65_v5
    port (
      rd_en : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      empty : out STD_LOGIC; 
      wr_en : in STD_LOGIC := 'X'; 
      rd_clk : in STD_LOGIC := 'X'; 
      full : out STD_LOGIC; 
      prog_empty : out STD_LOGIC; 
      wr_clk : in STD_LOGIC := 'X'; 
      prog_full : out STD_LOGIC; 
      wr_data_count : out STD_LOGIC_VECTOR ( 0 downto 0 ); 
      dout : out STD_LOGIC_VECTOR ( 64 downto 0 ); 
      rd_data_count : out STD_LOGIC_VECTOR ( 0 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 64 downto 0 ) 
    );
  end component;
  component cl_fifo_control_v2_INST_1
    port (
      clk : in STD_LOGIC := 'X'; 
      read : in STD_LOGIC := 'X'; 
      ef : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      empty : in STD_LOGIC := 'X'; 
      rd : out STD_LOGIC; 
      we : out STD_LOGIC 
    );
  end component;
  signal N1 : STD_LOGIC; 
  signal data_out_we : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_empty : STD_LOGIC; 
  signal flag_rd_pae_7086 : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_ef : STD_LOGIC; 
  signal flag_rd_pae_not0001 : STD_LOGIC; 
  signal flag_wr_ef_7089 : STD_LOGIC; 
  signal flag_wr_hf_7090 : STD_LOGIC; 
  signal flag_wr_pae_7091 : STD_LOGIC; 
  signal flag_wr_paf_7092 : STD_LOGIC; 
  signal flag_wr_hf_not0001 : STD_LOGIC; 
  signal flag_wr_paf_or0000 : STD_LOGIC; 
  signal full : STD_LOGIC; 
  signal prog_empty : STD_LOGIC; 
  signal prog_full : STD_LOGIC; 
  signal r_en : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NlwRenamedSignal_s_ovr : STD_LOGIC; 
  signal s_ovr_not0001 : STD_LOGIC; 
  signal NlwRenamedSignal_s_und : STD_LOGIC; 
  signal s_und_or0000_inv : STD_LOGIC; 
  signal w_cnt : STD_LOGIC; 
  signal NLW_ctrl_fifo_dout_64_UNCONNECTED : STD_LOGIC; 
  signal NLW_ctrl_fifo_rd_data_count_0_UNCONNECTED : STD_LOGIC; 
  signal fifo_out : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  flag_rd_ef <= NlwRenamedSig_OI_flag_rd_ef;
  flag_wr_und <= NlwRenamedSignal_s_und;
  flag_wr_pae <= flag_wr_pae_7091;
  flag_wr_paf <= flag_wr_paf_7092;
  flag_wr_ef <= flag_wr_ef_7089;
  flag_rd_ovr <= NlwRenamedSignal_s_ovr;
  flag_wr_hf <= flag_wr_hf_7090;
  flag_wr_ovr <= NlwRenamedSignal_s_ovr;
  flag_empty <= NlwRenamedSig_OI_flag_empty;
  flag_rd_und <= NlwRenamedSignal_s_und;
  flag_rd_pae <= flag_rd_pae_7086;
  XST_VCC : VCC
    port map (
      P => N1
    );
  flag_rd_pae_5454 : FDC
    port map (
      C => clk_rd,
      CLR => reset_inv,
      D => flag_rd_pae_not0001,
      Q => flag_rd_pae_7086
    );
  flag_wr_pae_5455 : FDC
    port map (
      C => clk_wr,
      CLR => reset_inv,
      D => flag_rd_pae_not0001,
      Q => flag_wr_pae_7091
    );
  flag_wr_paf_5456 : FDP
    port map (
      C => clk_wr,
      D => flag_wr_paf_or0000,
      PRE => reset_inv,
      Q => flag_wr_paf_7092
    );
  s_und : FDCE
    port map (
      C => clk_rd,
      CE => s_und_or0000_inv,
      CLR => reset_inv,
      D => N1,
      Q => NlwRenamedSignal_s_und
    );
  s_ovr : FDCE
    port map (
      C => clk_wr,
      CE => s_ovr_not0001,
      CLR => reset_inv,
      D => N1,
      Q => NlwRenamedSignal_s_ovr
    );
  flag_wr_hf_5459 : FDP
    port map (
      C => clk_wr,
      D => flag_wr_hf_not0001,
      PRE => reset_inv,
      Q => flag_wr_hf_7090
    );
  flag_wr_ef_5460 : FDC
    port map (
      C => clk_wr,
      CLR => reset_inv,
      D => NlwRenamedSig_OI_flag_rd_ef,
      Q => flag_wr_ef_7089
    );
  data_out_0 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(0),
      Q => data_out(0)
    );
  data_out_1 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(1),
      Q => data_out(1)
    );
  data_out_2 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(2),
      Q => data_out(2)
    );
  data_out_3 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(3),
      Q => data_out(3)
    );
  data_out_4 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(4),
      Q => data_out(4)
    );
  data_out_5 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(5),
      Q => data_out(5)
    );
  data_out_6 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(6),
      Q => data_out(6)
    );
  data_out_7 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(7),
      Q => data_out(7)
    );
  data_out_8 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(8),
      Q => data_out(8)
    );
  data_out_9 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(9),
      Q => data_out(9)
    );
  data_out_10 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(10),
      Q => data_out(10)
    );
  data_out_11 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(11),
      Q => data_out(11)
    );
  data_out_12 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(12),
      Q => data_out(12)
    );
  data_out_13 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(13),
      Q => data_out(13)
    );
  data_out_14 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(14),
      Q => data_out(14)
    );
  data_out_15 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(15),
      Q => data_out(15)
    );
  data_out_16 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(16),
      Q => data_out(16)
    );
  data_out_17 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(17),
      Q => data_out(17)
    );
  data_out_18 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(18),
      Q => data_out(18)
    );
  data_out_19 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(19),
      Q => data_out(19)
    );
  data_out_20 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(20),
      Q => data_out(20)
    );
  data_out_21 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(21),
      Q => data_out(21)
    );
  data_out_22 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(22),
      Q => data_out(22)
    );
  data_out_23 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(23),
      Q => data_out(23)
    );
  data_out_24 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(24),
      Q => data_out(24)
    );
  data_out_25 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(25),
      Q => data_out(25)
    );
  data_out_26 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(26),
      Q => data_out(26)
    );
  data_out_27 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(27),
      Q => data_out(27)
    );
  data_out_28 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(28),
      Q => data_out(28)
    );
  data_out_29 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(29),
      Q => data_out(29)
    );
  data_out_30 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(30),
      Q => data_out(30)
    );
  data_out_31 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(31),
      Q => data_out(31)
    );
  data_out_32 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(32),
      Q => data_out(32)
    );
  data_out_33 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(33),
      Q => data_out(33)
    );
  data_out_34 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(34),
      Q => data_out(34)
    );
  data_out_35 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(35),
      Q => data_out(35)
    );
  data_out_36 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(36),
      Q => data_out(36)
    );
  data_out_37 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(37),
      Q => data_out(37)
    );
  data_out_38 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(38),
      Q => data_out(38)
    );
  data_out_39 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(39),
      Q => data_out(39)
    );
  data_out_40 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(40),
      Q => data_out(40)
    );
  data_out_41 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(41),
      Q => data_out(41)
    );
  data_out_42 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(42),
      Q => data_out(42)
    );
  data_out_43 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(43),
      Q => data_out(43)
    );
  data_out_44 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(44),
      Q => data_out(44)
    );
  data_out_45 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(45),
      Q => data_out(45)
    );
  data_out_46 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(46),
      Q => data_out(46)
    );
  data_out_47 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(47),
      Q => data_out(47)
    );
  data_out_48 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(48),
      Q => data_out(48)
    );
  data_out_49 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(49),
      Q => data_out(49)
    );
  data_out_50 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(50),
      Q => data_out(50)
    );
  data_out_51 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(51),
      Q => data_out(51)
    );
  data_out_52 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(52),
      Q => data_out(52)
    );
  data_out_53 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(53),
      Q => data_out(53)
    );
  data_out_54 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(54),
      Q => data_out(54)
    );
  data_out_55 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(55),
      Q => data_out(55)
    );
  data_out_56 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(56),
      Q => data_out(56)
    );
  data_out_57 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(57),
      Q => data_out(57)
    );
  data_out_58 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(58),
      Q => data_out(58)
    );
  data_out_59 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(59),
      Q => data_out(59)
    );
  data_out_60 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(60),
      Q => data_out(60)
    );
  data_out_61 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(61),
      Q => data_out(61)
    );
  data_out_62 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(62),
      Q => data_out(62)
    );
  data_out_63 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(63),
      Q => data_out(63)
    );
  ctrl_fifo : ctrl_fifo1024x65_v5
    port map (
      rd_en => r_en,
      rst => reset_inv,
      empty => NlwRenamedSig_OI_flag_empty,
      wr_en => data_en,
      rd_clk => clk_rd,
      full => full,
      prog_empty => prog_empty,
      wr_clk => clk_wr,
      prog_full => prog_full,
      wr_data_count(0) => w_cnt,
      dout(64) => NLW_ctrl_fifo_dout_64_UNCONNECTED,
      dout(63) => fifo_out(63),
      dout(62) => fifo_out(62),
      dout(61) => fifo_out(61),
      dout(60) => fifo_out(60),
      dout(59) => fifo_out(59),
      dout(58) => fifo_out(58),
      dout(57) => fifo_out(57),
      dout(56) => fifo_out(56),
      dout(55) => fifo_out(55),
      dout(54) => fifo_out(54),
      dout(53) => fifo_out(53),
      dout(52) => fifo_out(52),
      dout(51) => fifo_out(51),
      dout(50) => fifo_out(50),
      dout(49) => fifo_out(49),
      dout(48) => fifo_out(48),
      dout(47) => fifo_out(47),
      dout(46) => fifo_out(46),
      dout(45) => fifo_out(45),
      dout(44) => fifo_out(44),
      dout(43) => fifo_out(43),
      dout(42) => fifo_out(42),
      dout(41) => fifo_out(41),
      dout(40) => fifo_out(40),
      dout(39) => fifo_out(39),
      dout(38) => fifo_out(38),
      dout(37) => fifo_out(37),
      dout(36) => fifo_out(36),
      dout(35) => fifo_out(35),
      dout(34) => fifo_out(34),
      dout(33) => fifo_out(33),
      dout(32) => fifo_out(32),
      dout(31) => fifo_out(31),
      dout(30) => fifo_out(30),
      dout(29) => fifo_out(29),
      dout(28) => fifo_out(28),
      dout(27) => fifo_out(27),
      dout(26) => fifo_out(26),
      dout(25) => fifo_out(25),
      dout(24) => fifo_out(24),
      dout(23) => fifo_out(23),
      dout(22) => fifo_out(22),
      dout(21) => fifo_out(21),
      dout(20) => fifo_out(20),
      dout(19) => fifo_out(19),
      dout(18) => fifo_out(18),
      dout(17) => fifo_out(17),
      dout(16) => fifo_out(16),
      dout(15) => fifo_out(15),
      dout(14) => fifo_out(14),
      dout(13) => fifo_out(13),
      dout(12) => fifo_out(12),
      dout(11) => fifo_out(11),
      dout(10) => fifo_out(10),
      dout(9) => fifo_out(9),
      dout(8) => fifo_out(8),
      dout(7) => fifo_out(7),
      dout(6) => fifo_out(6),
      dout(5) => fifo_out(5),
      dout(4) => fifo_out(4),
      dout(3) => fifo_out(3),
      dout(2) => fifo_out(2),
      dout(1) => fifo_out(1),
      dout(0) => fifo_out(0),
      rd_data_count(0) => NLW_ctrl_fifo_rd_data_count_0_UNCONNECTED,
      din(64) => data_inx,
      din(63) => data_in(63),
      din(62) => data_in(62),
      din(61) => data_in(61),
      din(60) => data_in(60),
      din(59) => data_in(59),
      din(58) => data_in(58),
      din(57) => data_in(57),
      din(56) => data_in(56),
      din(55) => data_in(55),
      din(54) => data_in(54),
      din(53) => data_in(53),
      din(52) => data_in(52),
      din(51) => data_in(51),
      din(50) => data_in(50),
      din(49) => data_in(49),
      din(48) => data_in(48),
      din(47) => data_in(47),
      din(46) => data_in(46),
      din(45) => data_in(45),
      din(44) => data_in(44),
      din(43) => data_in(43),
      din(42) => data_in(42),
      din(41) => data_in(41),
      din(40) => data_in(40),
      din(39) => data_in(39),
      din(38) => data_in(38),
      din(37) => data_in(37),
      din(36) => data_in(36),
      din(35) => data_in(35),
      din(34) => data_in(34),
      din(33) => data_in(33),
      din(32) => data_in(32),
      din(31) => data_in(31),
      din(30) => data_in(30),
      din(29) => data_in(29),
      din(28) => data_in(28),
      din(27) => data_in(27),
      din(26) => data_in(26),
      din(25) => data_in(25),
      din(24) => data_in(24),
      din(23) => data_in(23),
      din(22) => data_in(22),
      din(21) => data_in(21),
      din(20) => data_in(20),
      din(19) => data_in(19),
      din(18) => data_in(18),
      din(17) => data_in(17),
      din(16) => data_in(16),
      din(15) => data_in(15),
      din(14) => data_in(14),
      din(13) => data_in(13),
      din(12) => data_in(12),
      din(11) => data_in(11),
      din(10) => data_in(10),
      din(9) => data_in(9),
      din(8) => data_in(8),
      din(7) => data_in(7),
      din(6) => data_in(6),
      din(5) => data_in(5),
      din(4) => data_in(4),
      din(3) => data_in(3),
      din(2) => data_in(2),
      din(1) => data_in(1),
      din(0) => data_in(0)
    );
  flag_wr_paf_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => prog_full,
      I1 => w_cnt,
      O => flag_wr_paf_or0000
    );
  flag_wr_ff1 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => full,
      I1 => w_cnt,
      O => flag_wr_ff
    );
  s_und_or0000_inv1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => data_cs,
      I1 => NlwRenamedSig_OI_flag_rd_ef,
      O => s_und_or0000_inv
    );
  s_ovr_not00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data_en,
      I1 => full,
      O => s_ovr_not0001
    );
  crl : cl_fifo_control_v2_INST_1
    port map (
      clk => clk_rd,
      read => data_cs,
      ef => NlwRenamedSig_OI_flag_rd_ef,
      reset => reset,
      empty => NlwRenamedSig_OI_flag_empty,
      rd => r_en,
      we => data_out_we
    );
  flag_wr_hf_not00011_INV_0 : INV
    port map (
      I => w_cnt,
      O => flag_wr_hf_not0001
    );
  flag_rd_pae_not00011_INV_0 : INV
    port map (
      I => prog_empty,
      O => flag_rd_pae_not0001
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_chn_v4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    fifo_flag_und : in STD_LOGIC := 'X'; 
    fifo_flag_pae : in STD_LOGIC := 'X'; 
    fifo_flag_paf : in STD_LOGIC := 'X'; 
    fdiv_we : out STD_LOGIC; 
    st10 : in STD_LOGIC := 'X'; 
    bx_irq : out STD_LOGIC; 
    st11 : in STD_LOGIC := 'X'; 
    st12 : in STD_LOGIC := 'X'; 
    st13 : in STD_LOGIC := 'X'; 
    st14 : in STD_LOGIC := 'X'; 
    st15 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    rst : out STD_LOGIC; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    st9 : in STD_LOGIC := 'X'; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    fifo_rst : out STD_LOGIC; 
    format : out STD_LOGIC; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    cmd_rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ovr : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    prt_wr_start : in STD_LOGIC := 'X'; 
    bx_drq_ack : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ef : in STD_LOGIC := 'X'; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    fifo_flag_ff : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    fifo_flag_hf : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    chan1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    sflag_pae : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    sflag_paf : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    tl_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    prt_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end cl_chn_v4;

architecture STRUCTURE of cl_chn_v4 is
  signal N0 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal bx_irq_or0000_inv : STD_LOGIC; 
  signal bx_irq_or0000_inv126_6772 : STD_LOGIC; 
  signal bx_irq_or0000_inv171_6773 : STD_LOGIC; 
  signal bx_irq_or0000_inv179_6774 : STD_LOGIC; 
  signal bx_irq_or0000_inv254_6775 : STD_LOGIC; 
  signal bx_irq_or0000_inv307_6776 : STD_LOGIC; 
  signal bx_irq_or0000_inv36_6777 : STD_LOGIC; 
  signal bx_irq_or0000_inv74_6778 : STD_LOGIC; 
  signal c_inv_not0001 : STD_LOGIC; 
  signal c_mask_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_12_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_13_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_3_Q : STD_LOGIC; 
  signal c_mode0_not0001 : STD_LOGIC; 
  signal c_rst_inv : STD_LOGIC; 
  signal fifo_rst_and0000 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal c_inv : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mask : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mode0 : STD_LOGIC_VECTOR ( 5 downto 5 ); 
  signal NlwRenamedSig_OI_c_status : STD_LOGIC_VECTOR ( 8 downto 2 ); 
begin
  bx_drq_en <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(13) <= NlwRenamedSig_OI_c_mode0_13_Q;
  mode0(12) <= NlwRenamedSig_OI_c_mode0_12_Q;
  mode0(5) <= c_mode0(5);
  mode0(3) <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(2) <= NlwRenamedSig_OI_c_mode0_2_Q;
  mode0(1) <= NlwRenamedSig_OI_c_mode0_1_Q;
  mode0(0) <= NlwRenamedSig_OI_c_mode0_0_Q;
  status(8) <= NlwRenamedSig_OI_c_status(8);
  status(7) <= NlwRenamedSig_OI_c_status(7);
  status(6) <= NlwRenamedSig_OI_c_status(6);
  status(5) <= NlwRenamedSig_OI_c_status(5);
  status(4) <= NlwRenamedSig_OI_c_status(4);
  status(3) <= NlwRenamedSig_OI_c_status(3);
  status(2) <= NlwRenamedSig_OI_c_status(2);
  c_inv_0 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_inv(0)
    );
  c_inv_1 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_inv(1)
    );
  c_inv_2 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_inv(2)
    );
  c_inv_3 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_inv(3)
    );
  c_inv_4 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_inv(4)
    );
  c_inv_5 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_inv(5)
    );
  c_inv_6 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_inv(6)
    );
  c_inv_7 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_inv(7)
    );
  c_inv_8 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_inv(8)
    );
  c_inv_9 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_inv(9)
    );
  c_inv_10 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_inv(10)
    );
  c_inv_11 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_inv(11)
    );
  c_inv_12 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_inv(12)
    );
  c_inv_13 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_inv(13)
    );
  c_inv_14 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_inv(14)
    );
  c_inv_15 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_inv(15)
    );
  c_mask_0 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_mask(0)
    );
  c_mask_1 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_mask(1)
    );
  c_mask_2 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_mask(2)
    );
  c_mask_3 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_mask(3)
    );
  c_mask_4 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_mask(4)
    );
  c_mask_5 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_mask(5)
    );
  c_mask_6 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_mask(6)
    );
  c_mask_7 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_mask(7)
    );
  c_mask_8 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_mask(8)
    );
  c_mask_9 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_mask(9)
    );
  c_mask_10 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_mask(10)
    );
  c_mask_11 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_mask(11)
    );
  c_mask_12 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_mask(12)
    );
  c_mask_13 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_mask(13)
    );
  c_mask_14 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_mask(14)
    );
  c_mask_15 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_mask(15)
    );
  fifo_rst_5419 : FD
    port map (
      C => clk,
      D => fifo_rst_and0000,
      Q => fifo_rst
    );
  c_status_2 : FD
    port map (
      C => clk,
      D => fifo_flag_ef,
      Q => NlwRenamedSig_OI_c_status(2)
    );
  c_status_3 : FD
    port map (
      C => clk,
      D => fifo_flag_pae,
      Q => NlwRenamedSig_OI_c_status(3)
    );
  c_mode0_0 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(0),
      Q => NlwRenamedSig_OI_c_mode0_0_Q
    );
  c_mode0_1 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(1),
      Q => NlwRenamedSig_OI_c_mode0_1_Q
    );
  c_mode0_2 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(2),
      Q => NlwRenamedSig_OI_c_mode0_2_Q
    );
  c_mode0_3 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(3),
      Q => NlwRenamedSig_OI_c_mode0_3_Q
    );
  c_mode0_5 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(5),
      Q => c_mode0(5)
    );
  c_mode0_12 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(12),
      Q => NlwRenamedSig_OI_c_mode0_12_Q
    );
  c_mode0_13 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(13),
      Q => NlwRenamedSig_OI_c_mode0_13_Q
    );
  c_status_4 : FD
    port map (
      C => clk,
      D => fifo_flag_hf,
      Q => NlwRenamedSig_OI_c_status(4)
    );
  c_status_7 : FD
    port map (
      C => clk,
      D => fifo_flag_ovr,
      Q => NlwRenamedSig_OI_c_status(7)
    );
  c_status_5 : FD
    port map (
      C => clk,
      D => fifo_flag_paf,
      Q => NlwRenamedSig_OI_c_status(5)
    );
  c_status_6 : FD
    port map (
      C => clk,
      D => fifo_flag_ff,
      Q => NlwRenamedSig_OI_c_status(6)
    );
  c_status_8 : FD
    port map (
      C => clk,
      D => fifo_flag_und,
      Q => NlwRenamedSig_OI_c_status(8)
    );
  bx_irq_5434 : FDR
    port map (
      C => clk,
      D => NlwRenamedSig_OI_c_mode0_2_Q,
      R => bx_irq_or0000_inv,
      Q => bx_irq
    );
  c_rst_inv1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0_0_Q,
      O => c_rst_inv
    );
  fifo_rst_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0_0_Q,
      I2 => NlwRenamedSig_OI_c_mode0_1_Q,
      O => fifo_rst_and0000
    );
  chan1_not0001121 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => cmd_cmd_data_we,
      I1 => cmd_adr(9),
      I2 => cmd_adr(8),
      O => N35
    );
  c_mode0_not00011 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => N35,
      I1 => cmd_adr(3),
      I2 => cmd_adr(2),
      I3 => cmd_adr(0),
      I4 => cmd_adr(1),
      I5 => cmd_adr(4),
      O => c_mode0_not0001
    );
  c_mask_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => N35,
      I2 => cmd_adr(3),
      I3 => cmd_adr(2),
      I4 => cmd_adr(1),
      I5 => cmd_adr(4),
      O => c_mask_not0001
    );
  c_inv_not00011 : LUT6
    generic map(
      INIT => X"0000000000000008"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => N35,
      I2 => cmd_adr(3),
      I3 => cmd_adr(2),
      I4 => cmd_adr(0),
      I5 => cmd_adr(4),
      O => c_inv_not0001
    );
  bx_irq_or0000_inv36 : LUT5
    generic map(
      INIT => X"09990FFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(3),
      I1 => c_inv(3),
      I2 => c_mask(12),
      I3 => c_inv(12),
      I4 => c_mask(3),
      O => bx_irq_or0000_inv36_6777
    );
  bx_irq_or0000_inv74 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(14),
      I1 => c_mask(15),
      I2 => c_mask(11),
      I3 => c_inv(15),
      I4 => c_inv(11),
      I5 => c_inv(14),
      O => bx_irq_or0000_inv74_6778
    );
  bx_irq_or0000_inv126 : LUT5
    generic map(
      INIT => X"9909FF0F"
    )
    port map (
      I0 => c_inv(8),
      I1 => NlwRenamedSig_OI_c_status(8),
      I2 => c_mask(0),
      I3 => c_inv(0),
      I4 => c_mask(8),
      O => bx_irq_or0000_inv126_6772
    );
  bx_irq_or0000_inv171 : LUT4
    generic map(
      INIT => X"135F"
    )
    port map (
      I0 => c_mask(10),
      I1 => c_mask(9),
      I2 => c_inv(10),
      I3 => c_inv(9),
      O => bx_irq_or0000_inv171_6773
    );
  bx_irq_or0000_inv179 : LUT4
    generic map(
      INIT => X"D700"
    )
    port map (
      I0 => c_mask(2),
      I1 => c_inv(2),
      I2 => NlwRenamedSig_OI_c_status(2),
      I3 => bx_irq_or0000_inv171_6773,
      O => bx_irq_or0000_inv179_6774
    );
  bx_irq_or0000_inv254 : LUT6
    generic map(
      INIT => X"90099999F00FFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(6),
      I1 => c_inv(6),
      I2 => NlwRenamedSig_OI_c_status(7),
      I3 => c_inv(7),
      I4 => c_mask(7),
      I5 => c_mask(6),
      O => bx_irq_or0000_inv254_6775
    );
  bx_irq_or0000_inv307 : LUT6
    generic map(
      INIT => X"90099999F00FFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(4),
      I1 => c_inv(4),
      I2 => NlwRenamedSig_OI_c_status(5),
      I3 => c_inv(5),
      I4 => c_mask(5),
      I5 => c_mask(4),
      O => bx_irq_or0000_inv307_6776
    );
  drq_req1 : LUT5
    generic map(
      INIT => X"22A82220"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_mode0_3_Q,
      I1 => NlwRenamedSig_OI_c_mode0_13_Q,
      I2 => fifo_flag_paf,
      I3 => NlwRenamedSig_OI_c_mode0_12_Q,
      I4 => fifo_flag_hf,
      O => bx_drq_req
    );
  bx_irq_or0000_inv343_SW0 : LUT5
    generic map(
      INIT => X"8F88FFFF"
    )
    port map (
      I0 => c_mask(13),
      I1 => c_inv(13),
      I2 => c_inv(1),
      I3 => c_mask(1),
      I4 => bx_irq_or0000_inv74_6778,
      O => N0
    );
  bx_irq_or0000_inv343 : LUT6
    generic map(
      INIT => X"0000000080000000"
    )
    port map (
      I0 => bx_irq_or0000_inv126_6772,
      I1 => bx_irq_or0000_inv36_6777,
      I2 => bx_irq_or0000_inv307_6776,
      I3 => bx_irq_or0000_inv254_6775,
      I4 => bx_irq_or0000_inv179_6774,
      I5 => N0,
      O => bx_irq_or0000_inv
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity trd_admdio64_out_v4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    flag_rd_ef : out STD_LOGIC; 
    flag_rd_ff : out STD_LOGIC; 
    flag_rd_hf : out STD_LOGIC; 
    bx_irq : out STD_LOGIC; 
    start : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    data_cs : in STD_LOGIC := 'X'; 
    clk_rd : in STD_LOGIC := 'X'; 
    flag_rd_ovr : out STD_LOGIC; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    fifo_rst : out STD_LOGIC; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    bx_drq_ack : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    flag_rd_und : out STD_LOGIC; 
    flag_rd_pae : out STD_LOGIC; 
    flag_rd_paf : out STD_LOGIC; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fifo_cnt : out STD_LOGIC_VECTOR ( 12 downto 0 ); 
    cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end trd_admdio64_out_v4;

architecture STRUCTURE of trd_admdio64_out_v4 is
  component cl_chn_v4
    port (
      clk : in STD_LOGIC := 'X'; 
      fifo_flag_und : in STD_LOGIC := 'X'; 
      fifo_flag_pae : in STD_LOGIC := 'X'; 
      fifo_flag_paf : in STD_LOGIC := 'X'; 
      fdiv_we : out STD_LOGIC; 
      st10 : in STD_LOGIC := 'X'; 
      bx_irq : out STD_LOGIC; 
      st11 : in STD_LOGIC := 'X'; 
      st12 : in STD_LOGIC := 'X'; 
      st13 : in STD_LOGIC := 'X'; 
      st14 : in STD_LOGIC := 'X'; 
      st15 : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      rst : out STD_LOGIC; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      st9 : in STD_LOGIC := 'X'; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      fifo_rst : out STD_LOGIC; 
      format : out STD_LOGIC; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      cmd_rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ovr : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      prt_wr_start : in STD_LOGIC := 'X'; 
      bx_drq_ack : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ef : in STD_LOGIC := 'X'; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      fifo_flag_ff : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      fifo_flag_hf : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      chan1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      sflag_pae : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      sflag_paf : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      tl_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      prt_mode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component cl_fifo1024x65_v5_INST_1
    port (
      flag_rd_ef : out STD_LOGIC; 
      flag_rd_ff : out STD_LOGIC; 
      flag_rd_hf : out STD_LOGIC; 
      flag_wr_und : out STD_LOGIC; 
      flag_wr_pae : out STD_LOGIC; 
      flag_wr_paf : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : in STD_LOGIC := 'X'; 
      data_en : in STD_LOGIC := 'X'; 
      data_inx : in STD_LOGIC := 'X'; 
      flag_wr_ef : out STD_LOGIC; 
      clk_rd : in STD_LOGIC := 'X'; 
      flag_wr_ff : out STD_LOGIC; 
      flag_rd_ovr : out STD_LOGIC; 
      flag_wr_hf : out STD_LOGIC; 
      data_outx : out STD_LOGIC; 
      clk_wr : in STD_LOGIC := 'X'; 
      flag_wr_ovr : out STD_LOGIC; 
      flag_empty : out STD_LOGIC; 
      flag_rd_und : out STD_LOGIC; 
      flag_rd_pae : out STD_LOGIC; 
      flag_rd_paf : out STD_LOGIC; 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_fifo_rst : STD_LOGIC; 
  signal flag_wr_ef : STD_LOGIC; 
  signal flag_wr_ff : STD_LOGIC; 
  signal flag_wr_hf : STD_LOGIC; 
  signal flag_wr_ovr : STD_LOGIC; 
  signal flag_wr_pae : STD_LOGIC; 
  signal flag_wr_paf : STD_LOGIC; 
  signal flag_wr_und : STD_LOGIC; 
  signal NLW_x_fifo_data_outx_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_fifo_flag_empty_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_rst_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_format_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cmd_rdy_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_wr_start_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_rdy_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_chan1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_chan1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_pae_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_paf_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_tl_mode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_prt_mode_0_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSignal_mode0 : STD_LOGIC_VECTOR ( 5 downto 5 ); 
  signal NlwRenamedSig_OI_test : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  start <= NlwRenamedSignal_mode0(5);
  fifo_rst <= NlwRenamedSig_OI_fifo_rst;
  mode0(5) <= NlwRenamedSignal_mode0(5);
  fifo_cnt(12) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(11) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(10) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(9) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(8) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(7) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(6) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(5) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(4) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(3) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(2) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(1) <= NlwRenamedSig_OI_test(0);
  fifo_cnt(0) <= NlwRenamedSig_OI_test(0);
  test(7) <= NlwRenamedSig_OI_test(0);
  test(6) <= NlwRenamedSig_OI_test(0);
  test(5) <= NlwRenamedSig_OI_test(0);
  test(4) <= NlwRenamedSig_OI_test(0);
  test(3) <= NlwRenamedSig_OI_test(0);
  test(2) <= NlwRenamedSig_OI_test(0);
  test(1) <= NlwRenamedSig_OI_test(0);
  test(0) <= NlwRenamedSig_OI_test(0);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_test(0)
    );
  chn : cl_chn_v4
    port map (
      clk => clk,
      fifo_flag_und => flag_wr_und,
      fifo_flag_pae => flag_wr_pae,
      fifo_flag_paf => flag_wr_paf,
      fdiv_we => NLW_chn_fdiv_we_UNCONNECTED,
      st10 => NlwRenamedSig_OI_test(0),
      bx_irq => bx_irq,
      st11 => NlwRenamedSig_OI_test(0),
      st12 => NlwRenamedSig_OI_test(0),
      st13 => NlwRenamedSig_OI_test(0),
      st14 => NlwRenamedSig_OI_test(0),
      st15 => NlwRenamedSig_OI_test(0),
      reset => reset,
      rst => NLW_chn_rst_UNCONNECTED,
      cmd_cmd_data_we => cmd_cmd_data_we,
      st9 => NlwRenamedSig_OI_test(0),
      cmd_status_cs => cmd_status_cs,
      fifo_rst => NlwRenamedSig_OI_fifo_rst,
      format => NLW_chn_format_UNCONNECTED,
      cmd_data_cs => cmd_data_cs,
      cmd_rdy => NLW_chn_cmd_rdy_UNCONNECTED,
      fifo_flag_ovr => flag_wr_ovr,
      bx_drq_en => bx_drq_en,
      prt_wr_start => NLW_chn_prt_wr_start_UNCONNECTED,
      bx_drq_ack => bx_drq_ack,
      cmd_data_oe => cmd_data_oe,
      cmd_cmd_data_cs => cmd_cmd_data_cs,
      rdy => NLW_chn_rdy_UNCONNECTED,
      fifo_flag_ef => flag_wr_ef,
      cmd_cmd_adr_we => cmd_cmd_adr_we,
      fifo_flag_ff => flag_wr_ff,
      cmd_data_we => cmd_data_we,
      fifo_flag_hf => flag_wr_hf,
      bx_drq_req => bx_drq_req,
      stmode(15) => NLW_chn_stmode_15_UNCONNECTED,
      stmode(14) => NLW_chn_stmode_14_UNCONNECTED,
      stmode(13) => NLW_chn_stmode_13_UNCONNECTED,
      stmode(12) => NLW_chn_stmode_12_UNCONNECTED,
      stmode(11) => NLW_chn_stmode_11_UNCONNECTED,
      stmode(10) => NLW_chn_stmode_10_UNCONNECTED,
      stmode(9) => NLW_chn_stmode_9_UNCONNECTED,
      stmode(8) => NLW_chn_stmode_8_UNCONNECTED,
      stmode(7) => NLW_chn_stmode_7_UNCONNECTED,
      stmode(6) => NLW_chn_stmode_6_UNCONNECTED,
      stmode(5) => NLW_chn_stmode_5_UNCONNECTED,
      stmode(4) => NLW_chn_stmode_4_UNCONNECTED,
      stmode(3) => NLW_chn_stmode_3_UNCONNECTED,
      stmode(2) => NLW_chn_stmode_2_UNCONNECTED,
      stmode(1) => NLW_chn_stmode_1_UNCONNECTED,
      stmode(0) => NLW_chn_stmode_0_UNCONNECTED,
      chan1(1) => NLW_chn_chan1_1_UNCONNECTED,
      chan1(0) => NLW_chn_chan1_0_UNCONNECTED,
      mode0(15) => mode0(15),
      mode0(14) => mode0(14),
      mode0(13) => mode0(13),
      mode0(12) => mode0(12),
      mode0(11) => mode0(11),
      mode0(10) => mode0(10),
      mode0(9) => mode0(9),
      mode0(8) => mode0(8),
      mode0(7) => mode0(7),
      mode0(6) => mode0(6),
      mode0(5) => NlwRenamedSignal_mode0(5),
      mode0(4) => mode0(4),
      mode0(3) => mode0(3),
      mode0(2) => mode0(2),
      mode0(1) => mode0(1),
      mode0(0) => mode0(0),
      mode1(15) => mode1(15),
      mode1(14) => mode1(14),
      mode1(13) => mode1(13),
      mode1(12) => mode1(12),
      mode1(11) => mode1(11),
      mode1(10) => mode1(10),
      mode1(9) => mode1(9),
      mode1(8) => mode1(8),
      mode1(7) => mode1(7),
      mode1(6) => mode1(6),
      mode1(5) => mode1(5),
      mode1(4) => mode1(4),
      mode1(3) => mode1(3),
      mode1(2) => mode1(2),
      mode1(1) => mode1(1),
      mode1(0) => mode1(0),
      mode2(15) => mode2(15),
      mode2(14) => mode2(14),
      mode2(13) => mode2(13),
      mode2(12) => mode2(12),
      mode2(11) => mode2(11),
      mode2(10) => mode2(10),
      mode2(9) => mode2(9),
      mode2(8) => mode2(8),
      mode2(7) => mode2(7),
      mode2(6) => mode2(6),
      mode2(5) => mode2(5),
      mode2(4) => mode2(4),
      mode2(3) => mode2(3),
      mode2(2) => mode2(2),
      mode2(1) => mode2(1),
      mode2(0) => mode2(0),
      mode3(15) => mode3(15),
      mode3(14) => mode3(14),
      mode3(13) => mode3(13),
      mode3(12) => mode3(12),
      mode3(11) => mode3(11),
      mode3(10) => mode3(10),
      mode3(9) => mode3(9),
      mode3(8) => mode3(8),
      mode3(7) => mode3(7),
      mode3(6) => mode3(6),
      mode3(5) => mode3(5),
      mode3(4) => mode3(4),
      mode3(3) => mode3(3),
      mode3(2) => mode3(2),
      mode3(1) => mode3(1),
      mode3(0) => mode3(0),
      fdiv(15) => NLW_chn_fdiv_15_UNCONNECTED,
      fdiv(14) => NLW_chn_fdiv_14_UNCONNECTED,
      fdiv(13) => NLW_chn_fdiv_13_UNCONNECTED,
      fdiv(12) => NLW_chn_fdiv_12_UNCONNECTED,
      fdiv(11) => NLW_chn_fdiv_11_UNCONNECTED,
      fdiv(10) => NLW_chn_fdiv_10_UNCONNECTED,
      fdiv(9) => NLW_chn_fdiv_9_UNCONNECTED,
      fdiv(8) => NLW_chn_fdiv_8_UNCONNECTED,
      fdiv(7) => NLW_chn_fdiv_7_UNCONNECTED,
      fdiv(6) => NLW_chn_fdiv_6_UNCONNECTED,
      fdiv(5) => NLW_chn_fdiv_5_UNCONNECTED,
      fdiv(4) => NLW_chn_fdiv_4_UNCONNECTED,
      fdiv(3) => NLW_chn_fdiv_3_UNCONNECTED,
      fdiv(2) => NLW_chn_fdiv_2_UNCONNECTED,
      fdiv(1) => NLW_chn_fdiv_1_UNCONNECTED,
      fdiv(0) => NLW_chn_fdiv_0_UNCONNECTED,
      status(15) => cmd_data_out2(15),
      status(14) => cmd_data_out2(14),
      status(13) => cmd_data_out2(13),
      status(12) => cmd_data_out2(12),
      status(11) => cmd_data_out2(11),
      status(10) => cmd_data_out2(10),
      status(9) => cmd_data_out2(9),
      status(8) => cmd_data_out2(8),
      status(7) => cmd_data_out2(7),
      status(6) => cmd_data_out2(6),
      status(5) => cmd_data_out2(5),
      status(4) => cmd_data_out2(4),
      status(3) => cmd_data_out2(3),
      status(2) => cmd_data_out2(2),
      status(1) => cmd_data_out2(1),
      status(0) => cmd_data_out2(0),
      sflag_pae(15) => NLW_chn_sflag_pae_15_UNCONNECTED,
      sflag_pae(14) => NLW_chn_sflag_pae_14_UNCONNECTED,
      sflag_pae(13) => NLW_chn_sflag_pae_13_UNCONNECTED,
      sflag_pae(12) => NLW_chn_sflag_pae_12_UNCONNECTED,
      sflag_pae(11) => NLW_chn_sflag_pae_11_UNCONNECTED,
      sflag_pae(10) => NLW_chn_sflag_pae_10_UNCONNECTED,
      sflag_pae(9) => NLW_chn_sflag_pae_9_UNCONNECTED,
      sflag_pae(8) => NLW_chn_sflag_pae_8_UNCONNECTED,
      sflag_pae(7) => NLW_chn_sflag_pae_7_UNCONNECTED,
      sflag_pae(6) => NLW_chn_sflag_pae_6_UNCONNECTED,
      sflag_pae(5) => NLW_chn_sflag_pae_5_UNCONNECTED,
      sflag_pae(4) => NLW_chn_sflag_pae_4_UNCONNECTED,
      sflag_pae(3) => NLW_chn_sflag_pae_3_UNCONNECTED,
      sflag_pae(2) => NLW_chn_sflag_pae_2_UNCONNECTED,
      sflag_pae(1) => NLW_chn_sflag_pae_1_UNCONNECTED,
      sflag_pae(0) => NLW_chn_sflag_pae_0_UNCONNECTED,
      sflag_paf(15) => NLW_chn_sflag_paf_15_UNCONNECTED,
      sflag_paf(14) => NLW_chn_sflag_paf_14_UNCONNECTED,
      sflag_paf(13) => NLW_chn_sflag_paf_13_UNCONNECTED,
      sflag_paf(12) => NLW_chn_sflag_paf_12_UNCONNECTED,
      sflag_paf(11) => NLW_chn_sflag_paf_11_UNCONNECTED,
      sflag_paf(10) => NLW_chn_sflag_paf_10_UNCONNECTED,
      sflag_paf(9) => NLW_chn_sflag_paf_9_UNCONNECTED,
      sflag_paf(8) => NLW_chn_sflag_paf_8_UNCONNECTED,
      sflag_paf(7) => NLW_chn_sflag_paf_7_UNCONNECTED,
      sflag_paf(6) => NLW_chn_sflag_paf_6_UNCONNECTED,
      sflag_paf(5) => NLW_chn_sflag_paf_5_UNCONNECTED,
      sflag_paf(4) => NLW_chn_sflag_paf_4_UNCONNECTED,
      sflag_paf(3) => NLW_chn_sflag_paf_3_UNCONNECTED,
      sflag_paf(2) => NLW_chn_sflag_paf_2_UNCONNECTED,
      sflag_paf(1) => NLW_chn_sflag_paf_1_UNCONNECTED,
      sflag_paf(0) => NLW_chn_sflag_paf_0_UNCONNECTED,
      fmode(15) => NLW_chn_fmode_15_UNCONNECTED,
      fmode(14) => NLW_chn_fmode_14_UNCONNECTED,
      fmode(13) => NLW_chn_fmode_13_UNCONNECTED,
      fmode(12) => NLW_chn_fmode_12_UNCONNECTED,
      fmode(11) => NLW_chn_fmode_11_UNCONNECTED,
      fmode(10) => NLW_chn_fmode_10_UNCONNECTED,
      fmode(9) => NLW_chn_fmode_9_UNCONNECTED,
      fmode(8) => NLW_chn_fmode_8_UNCONNECTED,
      fmode(7) => NLW_chn_fmode_7_UNCONNECTED,
      fmode(6) => NLW_chn_fmode_6_UNCONNECTED,
      fmode(5) => NLW_chn_fmode_5_UNCONNECTED,
      fmode(4) => NLW_chn_fmode_4_UNCONNECTED,
      fmode(3) => NLW_chn_fmode_3_UNCONNECTED,
      fmode(2) => NLW_chn_fmode_2_UNCONNECTED,
      fmode(1) => NLW_chn_fmode_1_UNCONNECTED,
      fmode(0) => NLW_chn_fmode_0_UNCONNECTED,
      cnt0(15) => NLW_chn_cnt0_15_UNCONNECTED,
      cnt0(14) => NLW_chn_cnt0_14_UNCONNECTED,
      cnt0(13) => NLW_chn_cnt0_13_UNCONNECTED,
      cnt0(12) => NLW_chn_cnt0_12_UNCONNECTED,
      cnt0(11) => NLW_chn_cnt0_11_UNCONNECTED,
      cnt0(10) => NLW_chn_cnt0_10_UNCONNECTED,
      cnt0(9) => NLW_chn_cnt0_9_UNCONNECTED,
      cnt0(8) => NLW_chn_cnt0_8_UNCONNECTED,
      cnt0(7) => NLW_chn_cnt0_7_UNCONNECTED,
      cnt0(6) => NLW_chn_cnt0_6_UNCONNECTED,
      cnt0(5) => NLW_chn_cnt0_5_UNCONNECTED,
      cnt0(4) => NLW_chn_cnt0_4_UNCONNECTED,
      cnt0(3) => NLW_chn_cnt0_3_UNCONNECTED,
      cnt0(2) => NLW_chn_cnt0_2_UNCONNECTED,
      cnt0(1) => NLW_chn_cnt0_1_UNCONNECTED,
      cnt0(0) => NLW_chn_cnt0_0_UNCONNECTED,
      cnt1(15) => NLW_chn_cnt1_15_UNCONNECTED,
      cnt1(14) => NLW_chn_cnt1_14_UNCONNECTED,
      cnt1(13) => NLW_chn_cnt1_13_UNCONNECTED,
      cnt1(12) => NLW_chn_cnt1_12_UNCONNECTED,
      cnt1(11) => NLW_chn_cnt1_11_UNCONNECTED,
      cnt1(10) => NLW_chn_cnt1_10_UNCONNECTED,
      cnt1(9) => NLW_chn_cnt1_9_UNCONNECTED,
      cnt1(8) => NLW_chn_cnt1_8_UNCONNECTED,
      cnt1(7) => NLW_chn_cnt1_7_UNCONNECTED,
      cnt1(6) => NLW_chn_cnt1_6_UNCONNECTED,
      cnt1(5) => NLW_chn_cnt1_5_UNCONNECTED,
      cnt1(4) => NLW_chn_cnt1_4_UNCONNECTED,
      cnt1(3) => NLW_chn_cnt1_3_UNCONNECTED,
      cnt1(2) => NLW_chn_cnt1_2_UNCONNECTED,
      cnt1(1) => NLW_chn_cnt1_1_UNCONNECTED,
      cnt1(0) => NLW_chn_cnt1_0_UNCONNECTED,
      cnt2(15) => NLW_chn_cnt2_15_UNCONNECTED,
      cnt2(14) => NLW_chn_cnt2_14_UNCONNECTED,
      cnt2(13) => NLW_chn_cnt2_13_UNCONNECTED,
      cnt2(12) => NLW_chn_cnt2_12_UNCONNECTED,
      cnt2(11) => NLW_chn_cnt2_11_UNCONNECTED,
      cnt2(10) => NLW_chn_cnt2_10_UNCONNECTED,
      cnt2(9) => NLW_chn_cnt2_9_UNCONNECTED,
      cnt2(8) => NLW_chn_cnt2_8_UNCONNECTED,
      cnt2(7) => NLW_chn_cnt2_7_UNCONNECTED,
      cnt2(6) => NLW_chn_cnt2_6_UNCONNECTED,
      cnt2(5) => NLW_chn_cnt2_5_UNCONNECTED,
      cnt2(4) => NLW_chn_cnt2_4_UNCONNECTED,
      cnt2(3) => NLW_chn_cnt2_3_UNCONNECTED,
      cnt2(2) => NLW_chn_cnt2_2_UNCONNECTED,
      cnt2(1) => NLW_chn_cnt2_1_UNCONNECTED,
      cnt2(0) => NLW_chn_cnt2_0_UNCONNECTED,
      tl_mode(15) => NLW_chn_tl_mode_15_UNCONNECTED,
      tl_mode(14) => NLW_chn_tl_mode_14_UNCONNECTED,
      tl_mode(13) => NLW_chn_tl_mode_13_UNCONNECTED,
      tl_mode(12) => NLW_chn_tl_mode_12_UNCONNECTED,
      tl_mode(11) => NLW_chn_tl_mode_11_UNCONNECTED,
      tl_mode(10) => NLW_chn_tl_mode_10_UNCONNECTED,
      tl_mode(9) => NLW_chn_tl_mode_9_UNCONNECTED,
      tl_mode(8) => NLW_chn_tl_mode_8_UNCONNECTED,
      tl_mode(7) => NLW_chn_tl_mode_7_UNCONNECTED,
      tl_mode(6) => NLW_chn_tl_mode_6_UNCONNECTED,
      tl_mode(5) => NLW_chn_tl_mode_5_UNCONNECTED,
      tl_mode(4) => NLW_chn_tl_mode_4_UNCONNECTED,
      tl_mode(3) => NLW_chn_tl_mode_3_UNCONNECTED,
      tl_mode(2) => NLW_chn_tl_mode_2_UNCONNECTED,
      tl_mode(1) => NLW_chn_tl_mode_1_UNCONNECTED,
      tl_mode(0) => NLW_chn_tl_mode_0_UNCONNECTED,
      prt_mode(15) => NLW_chn_prt_mode_15_UNCONNECTED,
      prt_mode(14) => NLW_chn_prt_mode_14_UNCONNECTED,
      prt_mode(13) => NLW_chn_prt_mode_13_UNCONNECTED,
      prt_mode(12) => NLW_chn_prt_mode_12_UNCONNECTED,
      prt_mode(11) => NLW_chn_prt_mode_11_UNCONNECTED,
      prt_mode(10) => NLW_chn_prt_mode_10_UNCONNECTED,
      prt_mode(9) => NLW_chn_prt_mode_9_UNCONNECTED,
      prt_mode(8) => NLW_chn_prt_mode_8_UNCONNECTED,
      prt_mode(7) => NLW_chn_prt_mode_7_UNCONNECTED,
      prt_mode(6) => NLW_chn_prt_mode_6_UNCONNECTED,
      prt_mode(5) => NLW_chn_prt_mode_5_UNCONNECTED,
      prt_mode(4) => NLW_chn_prt_mode_4_UNCONNECTED,
      prt_mode(3) => NLW_chn_prt_mode_3_UNCONNECTED,
      prt_mode(2) => NLW_chn_prt_mode_2_UNCONNECTED,
      prt_mode(1) => NLW_chn_prt_mode_1_UNCONNECTED,
      prt_mode(0) => NLW_chn_prt_mode_0_UNCONNECTED,
      data_in(15) => cmd_data_in(15),
      data_in(14) => cmd_data_in(14),
      data_in(13) => cmd_data_in(13),
      data_in(12) => cmd_data_in(12),
      data_in(11) => cmd_data_in(11),
      data_in(10) => cmd_data_in(10),
      data_in(9) => cmd_data_in(9),
      data_in(8) => cmd_data_in(8),
      data_in(7) => cmd_data_in(7),
      data_in(6) => cmd_data_in(6),
      data_in(5) => cmd_data_in(5),
      data_in(4) => cmd_data_in(4),
      data_in(3) => cmd_data_in(3),
      data_in(2) => cmd_data_in(2),
      data_in(1) => cmd_data_in(1),
      data_in(0) => cmd_data_in(0),
      cmd_adr(9) => cmd_adr(9),
      cmd_adr(8) => cmd_adr(8),
      cmd_adr(7) => cmd_adr(7),
      cmd_adr(6) => cmd_adr(6),
      cmd_adr(5) => cmd_adr(5),
      cmd_adr(4) => cmd_adr(4),
      cmd_adr(3) => cmd_adr(3),
      cmd_adr(2) => cmd_adr(2),
      cmd_adr(1) => cmd_adr(1),
      cmd_adr(0) => cmd_adr(0)
    );
  x_fifo : cl_fifo1024x65_v5_INST_1
    port map (
      flag_rd_ef => flag_rd_ef,
      flag_rd_ff => flag_rd_ff,
      flag_rd_hf => flag_rd_hf,
      flag_wr_und => flag_wr_und,
      flag_wr_pae => flag_wr_pae,
      flag_wr_paf => flag_wr_paf,
      reset => NlwRenamedSig_OI_fifo_rst,
      data_cs => data_cs,
      data_en => cmd_data_we,
      data_inx => NlwRenamedSig_OI_test(0),
      flag_wr_ef => flag_wr_ef,
      clk_rd => clk_rd,
      flag_wr_ff => flag_wr_ff,
      flag_rd_ovr => flag_rd_ovr,
      flag_wr_hf => flag_wr_hf,
      data_outx => NLW_x_fifo_data_outx_UNCONNECTED,
      clk_wr => clk,
      flag_wr_ovr => flag_wr_ovr,
      flag_empty => NLW_x_fifo_flag_empty_UNCONNECTED,
      flag_rd_und => flag_rd_und,
      flag_rd_pae => flag_rd_pae,
      flag_rd_paf => flag_rd_paf,
      data_out(63) => data_out(63),
      data_out(62) => data_out(62),
      data_out(61) => data_out(61),
      data_out(60) => data_out(60),
      data_out(59) => data_out(59),
      data_out(58) => data_out(58),
      data_out(57) => data_out(57),
      data_out(56) => data_out(56),
      data_out(55) => data_out(55),
      data_out(54) => data_out(54),
      data_out(53) => data_out(53),
      data_out(52) => data_out(52),
      data_out(51) => data_out(51),
      data_out(50) => data_out(50),
      data_out(49) => data_out(49),
      data_out(48) => data_out(48),
      data_out(47) => data_out(47),
      data_out(46) => data_out(46),
      data_out(45) => data_out(45),
      data_out(44) => data_out(44),
      data_out(43) => data_out(43),
      data_out(42) => data_out(42),
      data_out(41) => data_out(41),
      data_out(40) => data_out(40),
      data_out(39) => data_out(39),
      data_out(38) => data_out(38),
      data_out(37) => data_out(37),
      data_out(36) => data_out(36),
      data_out(35) => data_out(35),
      data_out(34) => data_out(34),
      data_out(33) => data_out(33),
      data_out(32) => data_out(32),
      data_out(31) => data_out(31),
      data_out(30) => data_out(30),
      data_out(29) => data_out(29),
      data_out(28) => data_out(28),
      data_out(27) => data_out(27),
      data_out(26) => data_out(26),
      data_out(25) => data_out(25),
      data_out(24) => data_out(24),
      data_out(23) => data_out(23),
      data_out(22) => data_out(22),
      data_out(21) => data_out(21),
      data_out(20) => data_out(20),
      data_out(19) => data_out(19),
      data_out(18) => data_out(18),
      data_out(17) => data_out(17),
      data_out(16) => data_out(16),
      data_out(15) => data_out(15),
      data_out(14) => data_out(14),
      data_out(13) => data_out(13),
      data_out(12) => data_out(12),
      data_out(11) => data_out(11),
      data_out(10) => data_out(10),
      data_out(9) => data_out(9),
      data_out(8) => data_out(8),
      data_out(7) => data_out(7),
      data_out(6) => data_out(6),
      data_out(5) => data_out(5),
      data_out(4) => data_out(4),
      data_out(3) => data_out(3),
      data_out(2) => data_out(2),
      data_out(1) => data_out(1),
      data_out(0) => data_out(0),
      data_in(63) => data_in(63),
      data_in(62) => data_in(62),
      data_in(61) => data_in(61),
      data_in(60) => data_in(60),
      data_in(59) => data_in(59),
      data_in(58) => data_in(58),
      data_in(57) => data_in(57),
      data_in(56) => data_in(56),
      data_in(55) => data_in(55),
      data_in(54) => data_in(54),
      data_in(53) => data_in(53),
      data_in(52) => data_in(52),
      data_in(51) => data_in(51),
      data_in(50) => data_in(50),
      data_in(49) => data_in(49),
      data_in(48) => data_in(48),
      data_in(47) => data_in(47),
      data_in(46) => data_in(46),
      data_in(45) => data_in(45),
      data_in(44) => data_in(44),
      data_in(43) => data_in(43),
      data_in(42) => data_in(42),
      data_in(41) => data_in(41),
      data_in(40) => data_in(40),
      data_in(39) => data_in(39),
      data_in(38) => data_in(38),
      data_in(37) => data_in(37),
      data_in(36) => data_in(36),
      data_in(35) => data_in(35),
      data_in(34) => data_in(34),
      data_in(33) => data_in(33),
      data_in(32) => data_in(32),
      data_in(31) => data_in(31),
      data_in(30) => data_in(30),
      data_in(29) => data_in(29),
      data_in(28) => data_in(28),
      data_in(27) => data_in(27),
      data_in(26) => data_in(26),
      data_in(25) => data_in(25),
      data_in(24) => data_in(24),
      data_in(23) => data_in(23),
      data_in(22) => data_in(22),
      data_in(21) => data_in(21),
      data_in(20) => data_in(20),
      data_in(19) => data_in(19),
      data_in(18) => data_in(18),
      data_in(17) => data_in(17),
      data_in(16) => data_in(16),
      data_in(15) => data_in(15),
      data_in(14) => data_in(14),
      data_in(13) => data_in(13),
      data_in(12) => data_in(12),
      data_in(11) => data_in(11),
      data_in(10) => data_in(10),
      data_in(9) => data_in(9),
      data_in(8) => data_in(8),
      data_in(7) => data_in(7),
      data_in(6) => data_in(6),
      data_in(5) => data_in(5),
      data_in(4) => data_in(4),
      data_in(3) => data_in(3),
      data_in(2) => data_in(2),
      data_in(1) => data_in(1),
      data_in(0) => data_in(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_fifo_control_v2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    read : in STD_LOGIC := 'X'; 
    ef : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    empty : in STD_LOGIC := 'X'; 
    rd : out STD_LOGIC; 
    we : out STD_LOGIC 
  );
end cl_fifo_control_v2;

architecture STRUCTURE of cl_fifo_control_v2 is
  signal N2 : STD_LOGIC; 
  signal empty1_6262 : STD_LOGIC; 
  signal rd1_6264 : STD_LOGIC; 
  signal st_FSM_Acst_FSM_inv : STD_LOGIC; 
  signal st_FSM_FFd1_6268 : STD_LOGIC; 
  signal st_FSM_FFd1_In : STD_LOGIC; 
  signal st_FSM_FFd2_6270 : STD_LOGIC; 
  signal st_FSM_FFd2_In : STD_LOGIC; 
  signal st_FSM_FFd3_6272 : STD_LOGIC; 
  signal st_FSM_FFd4_6273 : STD_LOGIC; 
  signal st_FSM_FFd5_6274 : STD_LOGIC; 
  signal st_FSM_FFd5_In : STD_LOGIC; 
  signal st_FSM_FFd6_6276 : STD_LOGIC; 
  signal st_FSM_FFd6_In : STD_LOGIC; 
begin
  empty1 : FD
    port map (
      C => clk,
      D => empty,
      Q => empty1_6262
    );
  st_FSM_FFd1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd1_In,
      Q => st_FSM_FFd1_6268
    );
  st_FSM_FFd2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd2_In,
      Q => st_FSM_FFd2_6270
    );
  st_FSM_FFd6 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => clk,
      D => st_FSM_FFd6_In,
      PRE => st_FSM_Acst_FSM_inv,
      Q => st_FSM_FFd6_6276
    );
  st_FSM_FFd5 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd5_In,
      Q => st_FSM_FFd5_6274
    );
  st_FSM_FFd4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd5_6274,
      Q => st_FSM_FFd4_6273
    );
  st_FSM_FFd3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      CLR => st_FSM_Acst_FSM_inv,
      D => st_FSM_FFd4_6273,
      Q => st_FSM_FFd3_6272
    );
  st_FSM_FFd5_In1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => empty,
      I1 => st_FSM_FFd6_6276,
      O => st_FSM_FFd5_In
    );
  st_FSM_FFd6_In1 : LUT4
    generic map(
      INIT => X"8F88"
    )
    port map (
      I0 => empty,
      I1 => st_FSM_FFd6_6276,
      I2 => read,
      I3 => st_FSM_FFd1_6268,
      O => st_FSM_FFd6_In
    );
  st_FSM_FFd2_In1 : LUT6
    generic map(
      INIT => X"DD55FF55CC40FF40"
    )
    port map (
      I0 => empty1_6262,
      I1 => read,
      I2 => st_FSM_FFd1_6268,
      I3 => st_FSM_FFd2_6270,
      I4 => empty,
      I5 => st_FSM_FFd3_6272,
      O => st_FSM_FFd2_In
    );
  st_FSM_FFd1_In1 : LUT6
    generic map(
      INIT => X"AF8FA888A888A888"
    )
    port map (
      I0 => empty1_6262,
      I1 => st_FSM_FFd3_6272,
      I2 => read,
      I3 => st_FSM_FFd1_6268,
      I4 => st_FSM_FFd2_6270,
      I5 => empty,
      O => st_FSM_FFd1_In
    );
  we1 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => st_FSM_FFd4_6273,
      I1 => read,
      I2 => st_FSM_FFd2_6270,
      O => we
    );
  ef1 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => st_FSM_FFd1_6268,
      I1 => st_FSM_FFd2_6270,
      O => ef
    );
  st_FSM_Acst_FSM_inv1_INV_0 : INV
    port map (
      I => reset,
      O => st_FSM_Acst_FSM_inv
    );
  XST_VCC : VCC
    port map (
      P => N2
    );
  rd1 : LUT6
    generic map(
      INIT => X"0F085F5D0F080F08"
    )
    port map (
      I0 => read,
      I1 => st_FSM_FFd1_6268,
      I2 => empty1_6262,
      I3 => st_FSM_FFd3_6272,
      I4 => empty,
      I5 => st_FSM_FFd2_6270,
      O => rd1_6264
    );
  rd_f7 : MUXF7
    port map (
      I0 => rd1_6264,
      I1 => N2,
      S => st_FSM_FFd5_6274,
      O => rd
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_fifo1024x65_v5 is
  port (
    flag_rd_ef : out STD_LOGIC; 
    flag_rd_ff : out STD_LOGIC; 
    flag_rd_hf : out STD_LOGIC; 
    flag_wr_und : out STD_LOGIC; 
    flag_wr_pae : out STD_LOGIC; 
    flag_wr_paf : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : in STD_LOGIC := 'X'; 
    data_en : in STD_LOGIC := 'X'; 
    data_inx : in STD_LOGIC := 'X'; 
    flag_wr_ef : out STD_LOGIC; 
    clk_rd : in STD_LOGIC := 'X'; 
    flag_wr_ff : out STD_LOGIC; 
    flag_rd_ovr : out STD_LOGIC; 
    flag_wr_hf : out STD_LOGIC; 
    data_outx : out STD_LOGIC; 
    clk_wr : in STD_LOGIC := 'X'; 
    flag_wr_ovr : out STD_LOGIC; 
    flag_empty : out STD_LOGIC; 
    flag_rd_und : out STD_LOGIC; 
    flag_rd_pae : out STD_LOGIC; 
    flag_rd_paf : out STD_LOGIC; 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end cl_fifo1024x65_v5;

architecture STRUCTURE of cl_fifo1024x65_v5 is
  component ctrl_fifo1024x65_v5
    port (
      rd_en : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      empty : out STD_LOGIC; 
      wr_en : in STD_LOGIC := 'X'; 
      rd_clk : in STD_LOGIC := 'X'; 
      full : out STD_LOGIC; 
      prog_empty : out STD_LOGIC; 
      wr_clk : in STD_LOGIC := 'X'; 
      prog_full : out STD_LOGIC; 
      wr_data_count : out STD_LOGIC_VECTOR ( 0 downto 0 ); 
      dout : out STD_LOGIC_VECTOR ( 64 downto 0 ); 
      rd_data_count : out STD_LOGIC_VECTOR ( 0 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 64 downto 0 ) 
    );
  end component;
  component cl_fifo_control_v2
    port (
      clk : in STD_LOGIC := 'X'; 
      read : in STD_LOGIC := 'X'; 
      ef : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      empty : in STD_LOGIC := 'X'; 
      rd : out STD_LOGIC; 
      we : out STD_LOGIC 
    );
  end component;
  signal N1 : STD_LOGIC; 
  signal data_out_we : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_empty : STD_LOGIC; 
  signal flag_rd_ff_6479 : STD_LOGIC; 
  signal flag_rd_hf_6480 : STD_LOGIC; 
  signal flag_rd_pae_6481 : STD_LOGIC; 
  signal flag_rd_paf_6482 : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_ef : STD_LOGIC; 
  signal flag_rd_ff_or0000 : STD_LOGIC; 
  signal flag_rd_hf_not0001 : STD_LOGIC; 
  signal flag_rd_pae_not0001 : STD_LOGIC; 
  signal flag_rd_paf_or0000 : STD_LOGIC; 
  signal flag_wr_paf_6488 : STD_LOGIC; 
  signal flag_wr_paf_or0000 : STD_LOGIC; 
  signal full : STD_LOGIC; 
  signal prog_empty : STD_LOGIC; 
  signal prog_full : STD_LOGIC; 
  signal r_cnt : STD_LOGIC; 
  signal r_en : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NlwRenamedSignal_s_ovr : STD_LOGIC; 
  signal s_ovr_not0001 : STD_LOGIC; 
  signal NlwRenamedSignal_s_und : STD_LOGIC; 
  signal s_und_or0000_inv : STD_LOGIC; 
  signal w_cnt : STD_LOGIC; 
  signal NLW_ctrl_fifo_dout_64_UNCONNECTED : STD_LOGIC; 
  signal fifo_out : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  flag_rd_ef <= NlwRenamedSig_OI_flag_rd_ef;
  flag_rd_ff <= flag_rd_ff_6479;
  flag_rd_hf <= flag_rd_hf_6480;
  flag_wr_und <= NlwRenamedSignal_s_und;
  flag_wr_paf <= flag_wr_paf_6488;
  flag_rd_ovr <= NlwRenamedSignal_s_ovr;
  flag_wr_ovr <= NlwRenamedSignal_s_ovr;
  flag_empty <= NlwRenamedSig_OI_flag_empty;
  flag_rd_und <= NlwRenamedSignal_s_und;
  flag_rd_pae <= flag_rd_pae_6481;
  flag_rd_paf <= flag_rd_paf_6482;
  XST_VCC : VCC
    port map (
      P => N1
    );
  flag_rd_pae_5286 : FDC
    port map (
      C => clk_rd,
      CLR => reset_inv,
      D => flag_rd_pae_not0001,
      Q => flag_rd_pae_6481
    );
  flag_rd_paf_5287 : FDP
    port map (
      C => clk_rd,
      D => flag_rd_paf_or0000,
      PRE => reset_inv,
      Q => flag_rd_paf_6482
    );
  flag_wr_paf_5288 : FDP
    port map (
      C => clk_wr,
      D => flag_wr_paf_or0000,
      PRE => reset_inv,
      Q => flag_wr_paf_6488
    );
  s_und : FDCE
    port map (
      C => clk_rd,
      CE => s_und_or0000_inv,
      CLR => reset_inv,
      D => N1,
      Q => NlwRenamedSignal_s_und
    );
  flag_rd_ff_5290 : FDP
    port map (
      C => clk_rd,
      D => flag_rd_ff_or0000,
      PRE => reset_inv,
      Q => flag_rd_ff_6479
    );
  flag_rd_hf_5291 : FDP
    port map (
      C => clk_rd,
      D => flag_rd_hf_not0001,
      PRE => reset_inv,
      Q => flag_rd_hf_6480
    );
  s_ovr : FDCE
    port map (
      C => clk_wr,
      CE => s_ovr_not0001,
      CLR => reset_inv,
      D => N1,
      Q => NlwRenamedSignal_s_ovr
    );
  data_out_0 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(0),
      Q => data_out(0)
    );
  data_out_1 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(1),
      Q => data_out(1)
    );
  data_out_2 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(2),
      Q => data_out(2)
    );
  data_out_3 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(3),
      Q => data_out(3)
    );
  data_out_4 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(4),
      Q => data_out(4)
    );
  data_out_5 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(5),
      Q => data_out(5)
    );
  data_out_6 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(6),
      Q => data_out(6)
    );
  data_out_7 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(7),
      Q => data_out(7)
    );
  data_out_8 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(8),
      Q => data_out(8)
    );
  data_out_9 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(9),
      Q => data_out(9)
    );
  data_out_10 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(10),
      Q => data_out(10)
    );
  data_out_11 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(11),
      Q => data_out(11)
    );
  data_out_12 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(12),
      Q => data_out(12)
    );
  data_out_13 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(13),
      Q => data_out(13)
    );
  data_out_14 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(14),
      Q => data_out(14)
    );
  data_out_15 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(15),
      Q => data_out(15)
    );
  data_out_16 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(16),
      Q => data_out(16)
    );
  data_out_17 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(17),
      Q => data_out(17)
    );
  data_out_18 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(18),
      Q => data_out(18)
    );
  data_out_19 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(19),
      Q => data_out(19)
    );
  data_out_20 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(20),
      Q => data_out(20)
    );
  data_out_21 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(21),
      Q => data_out(21)
    );
  data_out_22 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(22),
      Q => data_out(22)
    );
  data_out_23 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(23),
      Q => data_out(23)
    );
  data_out_24 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(24),
      Q => data_out(24)
    );
  data_out_25 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(25),
      Q => data_out(25)
    );
  data_out_26 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(26),
      Q => data_out(26)
    );
  data_out_27 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(27),
      Q => data_out(27)
    );
  data_out_28 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(28),
      Q => data_out(28)
    );
  data_out_29 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(29),
      Q => data_out(29)
    );
  data_out_30 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(30),
      Q => data_out(30)
    );
  data_out_31 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(31),
      Q => data_out(31)
    );
  data_out_32 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(32),
      Q => data_out(32)
    );
  data_out_33 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(33),
      Q => data_out(33)
    );
  data_out_34 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(34),
      Q => data_out(34)
    );
  data_out_35 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(35),
      Q => data_out(35)
    );
  data_out_36 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(36),
      Q => data_out(36)
    );
  data_out_37 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(37),
      Q => data_out(37)
    );
  data_out_38 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(38),
      Q => data_out(38)
    );
  data_out_39 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(39),
      Q => data_out(39)
    );
  data_out_40 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(40),
      Q => data_out(40)
    );
  data_out_41 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(41),
      Q => data_out(41)
    );
  data_out_42 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(42),
      Q => data_out(42)
    );
  data_out_43 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(43),
      Q => data_out(43)
    );
  data_out_44 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(44),
      Q => data_out(44)
    );
  data_out_45 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(45),
      Q => data_out(45)
    );
  data_out_46 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(46),
      Q => data_out(46)
    );
  data_out_47 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(47),
      Q => data_out(47)
    );
  data_out_48 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(48),
      Q => data_out(48)
    );
  data_out_49 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(49),
      Q => data_out(49)
    );
  data_out_50 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(50),
      Q => data_out(50)
    );
  data_out_51 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(51),
      Q => data_out(51)
    );
  data_out_52 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(52),
      Q => data_out(52)
    );
  data_out_53 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(53),
      Q => data_out(53)
    );
  data_out_54 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(54),
      Q => data_out(54)
    );
  data_out_55 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(55),
      Q => data_out(55)
    );
  data_out_56 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(56),
      Q => data_out(56)
    );
  data_out_57 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(57),
      Q => data_out(57)
    );
  data_out_58 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(58),
      Q => data_out(58)
    );
  data_out_59 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(59),
      Q => data_out(59)
    );
  data_out_60 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(60),
      Q => data_out(60)
    );
  data_out_61 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(61),
      Q => data_out(61)
    );
  data_out_62 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(62),
      Q => data_out(62)
    );
  data_out_63 : FDE
    port map (
      C => clk_rd,
      CE => data_out_we,
      D => fifo_out(63),
      Q => data_out(63)
    );
  ctrl_fifo : ctrl_fifo1024x65_v5
    port map (
      rd_en => r_en,
      rst => reset_inv,
      empty => NlwRenamedSig_OI_flag_empty,
      wr_en => data_en,
      rd_clk => clk_rd,
      full => full,
      prog_empty => prog_empty,
      wr_clk => clk_wr,
      prog_full => prog_full,
      wr_data_count(0) => w_cnt,
      dout(64) => NLW_ctrl_fifo_dout_64_UNCONNECTED,
      dout(63) => fifo_out(63),
      dout(62) => fifo_out(62),
      dout(61) => fifo_out(61),
      dout(60) => fifo_out(60),
      dout(59) => fifo_out(59),
      dout(58) => fifo_out(58),
      dout(57) => fifo_out(57),
      dout(56) => fifo_out(56),
      dout(55) => fifo_out(55),
      dout(54) => fifo_out(54),
      dout(53) => fifo_out(53),
      dout(52) => fifo_out(52),
      dout(51) => fifo_out(51),
      dout(50) => fifo_out(50),
      dout(49) => fifo_out(49),
      dout(48) => fifo_out(48),
      dout(47) => fifo_out(47),
      dout(46) => fifo_out(46),
      dout(45) => fifo_out(45),
      dout(44) => fifo_out(44),
      dout(43) => fifo_out(43),
      dout(42) => fifo_out(42),
      dout(41) => fifo_out(41),
      dout(40) => fifo_out(40),
      dout(39) => fifo_out(39),
      dout(38) => fifo_out(38),
      dout(37) => fifo_out(37),
      dout(36) => fifo_out(36),
      dout(35) => fifo_out(35),
      dout(34) => fifo_out(34),
      dout(33) => fifo_out(33),
      dout(32) => fifo_out(32),
      dout(31) => fifo_out(31),
      dout(30) => fifo_out(30),
      dout(29) => fifo_out(29),
      dout(28) => fifo_out(28),
      dout(27) => fifo_out(27),
      dout(26) => fifo_out(26),
      dout(25) => fifo_out(25),
      dout(24) => fifo_out(24),
      dout(23) => fifo_out(23),
      dout(22) => fifo_out(22),
      dout(21) => fifo_out(21),
      dout(20) => fifo_out(20),
      dout(19) => fifo_out(19),
      dout(18) => fifo_out(18),
      dout(17) => fifo_out(17),
      dout(16) => fifo_out(16),
      dout(15) => fifo_out(15),
      dout(14) => fifo_out(14),
      dout(13) => fifo_out(13),
      dout(12) => fifo_out(12),
      dout(11) => fifo_out(11),
      dout(10) => fifo_out(10),
      dout(9) => fifo_out(9),
      dout(8) => fifo_out(8),
      dout(7) => fifo_out(7),
      dout(6) => fifo_out(6),
      dout(5) => fifo_out(5),
      dout(4) => fifo_out(4),
      dout(3) => fifo_out(3),
      dout(2) => fifo_out(2),
      dout(1) => fifo_out(1),
      dout(0) => fifo_out(0),
      rd_data_count(0) => r_cnt,
      din(64) => data_inx,
      din(63) => data_in(63),
      din(62) => data_in(62),
      din(61) => data_in(61),
      din(60) => data_in(60),
      din(59) => data_in(59),
      din(58) => data_in(58),
      din(57) => data_in(57),
      din(56) => data_in(56),
      din(55) => data_in(55),
      din(54) => data_in(54),
      din(53) => data_in(53),
      din(52) => data_in(52),
      din(51) => data_in(51),
      din(50) => data_in(50),
      din(49) => data_in(49),
      din(48) => data_in(48),
      din(47) => data_in(47),
      din(46) => data_in(46),
      din(45) => data_in(45),
      din(44) => data_in(44),
      din(43) => data_in(43),
      din(42) => data_in(42),
      din(41) => data_in(41),
      din(40) => data_in(40),
      din(39) => data_in(39),
      din(38) => data_in(38),
      din(37) => data_in(37),
      din(36) => data_in(36),
      din(35) => data_in(35),
      din(34) => data_in(34),
      din(33) => data_in(33),
      din(32) => data_in(32),
      din(31) => data_in(31),
      din(30) => data_in(30),
      din(29) => data_in(29),
      din(28) => data_in(28),
      din(27) => data_in(27),
      din(26) => data_in(26),
      din(25) => data_in(25),
      din(24) => data_in(24),
      din(23) => data_in(23),
      din(22) => data_in(22),
      din(21) => data_in(21),
      din(20) => data_in(20),
      din(19) => data_in(19),
      din(18) => data_in(18),
      din(17) => data_in(17),
      din(16) => data_in(16),
      din(15) => data_in(15),
      din(14) => data_in(14),
      din(13) => data_in(13),
      din(12) => data_in(12),
      din(11) => data_in(11),
      din(10) => data_in(10),
      din(9) => data_in(9),
      din(8) => data_in(8),
      din(7) => data_in(7),
      din(6) => data_in(6),
      din(5) => data_in(5),
      din(4) => data_in(4),
      din(3) => data_in(3),
      din(2) => data_in(2),
      din(1) => data_in(1),
      din(0) => data_in(0)
    );
  flag_wr_paf_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => prog_full,
      I1 => w_cnt,
      O => flag_wr_paf_or0000
    );
  flag_rd_paf_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => prog_full,
      I1 => r_cnt,
      O => flag_rd_paf_or0000
    );
  flag_rd_ff_or00001 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => full,
      I1 => r_cnt,
      O => flag_rd_ff_or0000
    );
  s_und_or0000_inv1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => data_cs,
      I1 => NlwRenamedSig_OI_flag_rd_ef,
      O => s_und_or0000_inv
    );
  s_ovr_not00011 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data_en,
      I1 => full,
      O => s_ovr_not0001
    );
  crl : cl_fifo_control_v2
    port map (
      clk => clk_rd,
      read => data_cs,
      ef => NlwRenamedSig_OI_flag_rd_ef,
      reset => reset,
      empty => NlwRenamedSig_OI_flag_empty,
      rd => r_en,
      we => data_out_we
    );
  flag_rd_pae_not00011_INV_0 : INV
    port map (
      I => prog_empty,
      O => flag_rd_pae_not0001
    );
  flag_rd_hf_not00011_INV_0 : INV
    port map (
      I => r_cnt,
      O => flag_rd_hf_not0001
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_chn_v3_INST_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    fifo_flag_und : in STD_LOGIC := 'X'; 
    fifo_flag_pae : in STD_LOGIC := 'X'; 
    fifo_flag_paf : in STD_LOGIC := 'X'; 
    fdiv_we : out STD_LOGIC; 
    st10 : in STD_LOGIC := 'X'; 
    bx_irq : out STD_LOGIC; 
    st11 : in STD_LOGIC := 'X'; 
    st12 : in STD_LOGIC := 'X'; 
    st13 : in STD_LOGIC := 'X'; 
    st14 : in STD_LOGIC := 'X'; 
    st15 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    rst : out STD_LOGIC; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    st9 : in STD_LOGIC := 'X'; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    fifo_rst : out STD_LOGIC; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    cmd_rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ovr : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    bx_drq_ack : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ef : in STD_LOGIC := 'X'; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    fifo_flag_ff : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    fifo_flag_hf : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    sflag : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end cl_chn_v3_INST_1;

architecture STRUCTURE of cl_chn_v3_INST_1 is
  signal N10 : STD_LOGIC; 
  signal bx_irq_or0000_inv : STD_LOGIC; 
  signal bx_irq_or0000_inv142_6162 : STD_LOGIC; 
  signal bx_irq_or0000_inv195_6163 : STD_LOGIC; 
  signal bx_irq_or0000_inv23_6164 : STD_LOGIC; 
  signal bx_irq_or0000_inv264_6165 : STD_LOGIC; 
  signal bx_irq_or0000_inv301_6166 : STD_LOGIC; 
  signal bx_irq_or0000_inv314_6167 : STD_LOGIC; 
  signal bx_irq_or0000_inv337_6168 : STD_LOGIC; 
  signal bx_irq_or0000_inv60_6169 : STD_LOGIC; 
  signal bx_irq_or0000_inv63_6170 : STD_LOGIC; 
  signal c_inv_not0001 : STD_LOGIC; 
  signal c_mask_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_12_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_13_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_3_Q : STD_LOGIC; 
  signal c_mode0_not0001 : STD_LOGIC; 
  signal c_rst_inv : STD_LOGIC; 
  signal fifo_rst_and0000 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal c_inv : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mask : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mode0 : STD_LOGIC_VECTOR ( 5 downto 5 ); 
  signal NlwRenamedSig_OI_c_status : STD_LOGIC_VECTOR ( 8 downto 1 ); 
begin
  bx_drq_en <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(13) <= NlwRenamedSig_OI_c_mode0_13_Q;
  mode0(12) <= NlwRenamedSig_OI_c_mode0_12_Q;
  mode0(5) <= c_mode0(5);
  mode0(3) <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(2) <= NlwRenamedSig_OI_c_mode0_2_Q;
  mode0(1) <= NlwRenamedSig_OI_c_mode0_1_Q;
  mode0(0) <= NlwRenamedSig_OI_c_mode0_0_Q;
  status(8) <= NlwRenamedSig_OI_c_status(8);
  status(7) <= NlwRenamedSig_OI_c_status(7);
  status(6) <= NlwRenamedSig_OI_c_status(6);
  status(5) <= NlwRenamedSig_OI_c_status(5);
  status(4) <= NlwRenamedSig_OI_c_status(4);
  status(3) <= NlwRenamedSig_OI_c_status(3);
  status(2) <= NlwRenamedSig_OI_c_status(2);
  status(1) <= NlwRenamedSig_OI_c_status(1);
  c_inv_0 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_inv(0)
    );
  c_inv_1 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_inv(1)
    );
  c_inv_2 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_inv(2)
    );
  c_inv_3 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_inv(3)
    );
  c_inv_4 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_inv(4)
    );
  c_inv_5 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_inv(5)
    );
  c_inv_6 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_inv(6)
    );
  c_inv_7 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_inv(7)
    );
  c_inv_8 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_inv(8)
    );
  c_inv_9 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_inv(9)
    );
  c_inv_10 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_inv(10)
    );
  c_inv_11 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_inv(11)
    );
  c_inv_12 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_inv(12)
    );
  c_inv_13 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_inv(13)
    );
  c_inv_14 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_inv(14)
    );
  c_inv_15 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_inv(15)
    );
  c_mask_0 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_mask(0)
    );
  c_mask_1 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_mask(1)
    );
  c_mask_2 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_mask(2)
    );
  c_mask_3 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_mask(3)
    );
  c_mask_4 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_mask(4)
    );
  c_mask_5 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_mask(5)
    );
  c_mask_6 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_mask(6)
    );
  c_mask_7 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_mask(7)
    );
  c_mask_8 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_mask(8)
    );
  c_mask_9 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_mask(9)
    );
  c_mask_10 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_mask(10)
    );
  c_mask_11 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_mask(11)
    );
  c_mask_12 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_mask(12)
    );
  c_mask_13 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_mask(13)
    );
  c_mask_14 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_mask(14)
    );
  c_mask_15 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_mask(15)
    );
  fifo_rst_5249 : FD
    port map (
      C => clk,
      D => fifo_rst_and0000,
      Q => fifo_rst
    );
  c_status_3 : FD
    port map (
      C => clk,
      D => fifo_flag_pae,
      Q => NlwRenamedSig_OI_c_status(3)
    );
  c_status_1 : FD
    port map (
      C => clk,
      D => rdy,
      Q => NlwRenamedSig_OI_c_status(1)
    );
  c_status_2 : FD
    port map (
      C => clk,
      D => fifo_flag_ef,
      Q => NlwRenamedSig_OI_c_status(2)
    );
  c_mode0_0 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(0),
      Q => NlwRenamedSig_OI_c_mode0_0_Q
    );
  c_mode0_1 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(1),
      Q => NlwRenamedSig_OI_c_mode0_1_Q
    );
  c_mode0_2 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(2),
      Q => NlwRenamedSig_OI_c_mode0_2_Q
    );
  c_mode0_3 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(3),
      Q => NlwRenamedSig_OI_c_mode0_3_Q
    );
  c_mode0_5 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(5),
      Q => c_mode0(5)
    );
  c_mode0_12 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(12),
      Q => NlwRenamedSig_OI_c_mode0_12_Q
    );
  c_mode0_13 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(13),
      Q => NlwRenamedSig_OI_c_mode0_13_Q
    );
  c_status_4 : FD
    port map (
      C => clk,
      D => fifo_flag_hf,
      Q => NlwRenamedSig_OI_c_status(4)
    );
  c_status_5 : FD
    port map (
      C => clk,
      D => fifo_flag_paf,
      Q => NlwRenamedSig_OI_c_status(5)
    );
  c_status_6 : FD
    port map (
      C => clk,
      D => fifo_flag_ff,
      Q => NlwRenamedSig_OI_c_status(6)
    );
  c_status_7 : FD
    port map (
      C => clk,
      D => fifo_flag_ovr,
      Q => NlwRenamedSig_OI_c_status(7)
    );
  c_status_8 : FD
    port map (
      C => clk,
      D => fifo_flag_und,
      Q => NlwRenamedSig_OI_c_status(8)
    );
  bx_irq_5265 : FDR
    port map (
      C => clk,
      D => NlwRenamedSig_OI_c_mode0_2_Q,
      R => bx_irq_or0000_inv,
      Q => bx_irq
    );
  c_rst_inv1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0_0_Q,
      O => c_rst_inv
    );
  fifo_rst_and00001 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0_0_Q,
      I2 => NlwRenamedSig_OI_c_mode0_1_Q,
      O => fifo_rst_and0000
    );
  c_mode0_not00011 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      I3 => N10,
      O => c_mode0_not0001
    );
  c_mask_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => cmd_adr(2),
      I2 => cmd_adr(1),
      I3 => N10,
      O => c_mask_not0001
    );
  c_inv_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => cmd_adr(2),
      I2 => cmd_adr(0),
      I3 => N10,
      O => c_inv_not0001
    );
  c_cnt0_not000121 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => cmd_adr(9),
      I2 => cmd_adr(8),
      I3 => cmd_cmd_data_we,
      O => N10
    );
  bx_irq_or0000_inv23 : LUT6
    generic map(
      INIT => X"115533FF0105030F"
    )
    port map (
      I0 => c_mask(13),
      I1 => c_mask(14),
      I2 => c_mask(0),
      I3 => c_inv(14),
      I4 => c_inv(13),
      I5 => c_inv(0),
      O => bx_irq_or0000_inv23_6164
    );
  bx_irq_or0000_inv60 : LUT5
    generic map(
      INIT => X"09990FFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(3),
      I1 => c_inv(3),
      I2 => c_mask(11),
      I3 => c_inv(11),
      I4 => c_mask(3),
      O => bx_irq_or0000_inv60_6169
    );
  bx_irq_or0000_inv63 : LUT3
    generic map(
      INIT => X"70"
    )
    port map (
      I0 => c_mask(12),
      I1 => c_inv(12),
      I2 => bx_irq_or0000_inv60_6169,
      O => bx_irq_or0000_inv63_6170
    );
  bx_irq_or0000_inv142 : LUT6
    generic map(
      INIT => X"90099999F00FFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(6),
      I1 => c_inv(6),
      I2 => NlwRenamedSig_OI_c_status(7),
      I3 => c_inv(7),
      I4 => c_mask(7),
      I5 => c_mask(6),
      O => bx_irq_or0000_inv142_6162
    );
  bx_irq_or0000_inv195 : LUT6
    generic map(
      INIT => X"90099999F00FFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(4),
      I1 => c_inv(4),
      I2 => NlwRenamedSig_OI_c_status(5),
      I3 => c_inv(5),
      I4 => c_mask(5),
      I5 => c_mask(4),
      O => bx_irq_or0000_inv195_6163
    );
  bx_irq_or0000_inv264 : LUT5
    generic map(
      INIT => X"09990FFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(8),
      I1 => c_inv(8),
      I2 => c_mask(15),
      I3 => c_inv(15),
      I4 => c_mask(8),
      O => bx_irq_or0000_inv264_6165
    );
  bx_irq_or0000_inv301 : LUT3
    generic map(
      INIT => X"9F"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_status(2),
      I1 => c_inv(2),
      I2 => c_mask(2),
      O => bx_irq_or0000_inv301_6166
    );
  bx_irq_or0000_inv314 : LUT4
    generic map(
      INIT => X"135F"
    )
    port map (
      I0 => c_mask(10),
      I1 => c_mask(9),
      I2 => c_inv(10),
      I3 => c_inv(9),
      O => bx_irq_or0000_inv314_6167
    );
  bx_irq_or0000_inv337 : LUT6
    generic map(
      INIT => X"D700000000000000"
    )
    port map (
      I0 => c_mask(1),
      I1 => c_inv(1),
      I2 => NlwRenamedSig_OI_c_status(1),
      I3 => bx_irq_or0000_inv301_6166,
      I4 => bx_irq_or0000_inv314_6167,
      I5 => bx_irq_or0000_inv264_6165,
      O => bx_irq_or0000_inv337_6168
    );
  bx_irq_or0000_inv361 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => bx_irq_or0000_inv23_6164,
      I1 => bx_irq_or0000_inv195_6163,
      I2 => bx_irq_or0000_inv142_6162,
      I3 => bx_irq_or0000_inv63_6170,
      I4 => bx_irq_or0000_inv337_6168,
      O => bx_irq_or0000_inv
    );
  bx_drq_req1 : LUT6
    generic map(
      INIT => X"5746000013020000"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_mode0_13_Q,
      I1 => NlwRenamedSig_OI_c_mode0_12_Q,
      I2 => fifo_flag_hf,
      I3 => fifo_flag_pae,
      I4 => NlwRenamedSig_OI_c_mode0_3_Q,
      I5 => rdy,
      O => bx_drq_req
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity trd_admdio64_in_v6 is
  port (
    clk : in STD_LOGIC := 'X'; 
    flag_rd_ef : out STD_LOGIC; 
    flag_rd_ff : out STD_LOGIC; 
    flag_rd_hf : out STD_LOGIC; 
    flag_wr_und : out STD_LOGIC; 
    bx_irq : out STD_LOGIC; 
    flag_wr_pae : out STD_LOGIC; 
    flag_wr_paf : out STD_LOGIC; 
    start : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    flag_wr_ef : out STD_LOGIC; 
    flag_wr_ff : out STD_LOGIC; 
    flag_rd_ovr : out STD_LOGIC; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    flag_wr_hf : out STD_LOGIC; 
    fifo_rst : out STD_LOGIC; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    clk_wr : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    flag_wr_ovr : out STD_LOGIC; 
    bx_drq_ack : out STD_LOGIC; 
    data_wr : in STD_LOGIC := 'X'; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    flag_rd_und : out STD_LOGIC; 
    flag_rd_pae : out STD_LOGIC; 
    flag_rd_paf : out STD_LOGIC; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    fifo_rst_in : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    fifo_cnt_rd : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    fifo_cnt_wr : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
    data_out2 : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end trd_admdio64_in_v6;

architecture STRUCTURE of trd_admdio64_in_v6 is
  component cl_chn_v3_INST_1
    port (
      clk : in STD_LOGIC := 'X'; 
      fifo_flag_und : in STD_LOGIC := 'X'; 
      fifo_flag_pae : in STD_LOGIC := 'X'; 
      fifo_flag_paf : in STD_LOGIC := 'X'; 
      fdiv_we : out STD_LOGIC; 
      st10 : in STD_LOGIC := 'X'; 
      bx_irq : out STD_LOGIC; 
      st11 : in STD_LOGIC := 'X'; 
      st12 : in STD_LOGIC := 'X'; 
      st13 : in STD_LOGIC := 'X'; 
      st14 : in STD_LOGIC := 'X'; 
      st15 : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      rst : out STD_LOGIC; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      st9 : in STD_LOGIC := 'X'; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      fifo_rst : out STD_LOGIC; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      cmd_rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ovr : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      bx_drq_ack : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ef : in STD_LOGIC := 'X'; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      fifo_flag_ff : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      fifo_flag_hf : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      sflag : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component cl_fifo1024x65_v5
    port (
      flag_rd_ef : out STD_LOGIC; 
      flag_rd_ff : out STD_LOGIC; 
      flag_rd_hf : out STD_LOGIC; 
      flag_wr_und : out STD_LOGIC; 
      flag_wr_pae : out STD_LOGIC; 
      flag_wr_paf : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : in STD_LOGIC := 'X'; 
      data_en : in STD_LOGIC := 'X'; 
      data_inx : in STD_LOGIC := 'X'; 
      flag_wr_ef : out STD_LOGIC; 
      clk_rd : in STD_LOGIC := 'X'; 
      flag_wr_ff : out STD_LOGIC; 
      flag_rd_ovr : out STD_LOGIC; 
      flag_wr_hf : out STD_LOGIC; 
      data_outx : out STD_LOGIC; 
      clk_wr : in STD_LOGIC := 'X'; 
      flag_wr_ovr : out STD_LOGIC; 
      flag_empty : out STD_LOGIC; 
      flag_rd_und : out STD_LOGIC; 
      flag_rd_pae : out STD_LOGIC; 
      flag_rd_paf : out STD_LOGIC; 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal NlwRenamedSig_OI_fifo_rst : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_ef : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_ff : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_hf : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_ovr : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_pae : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_paf : STD_LOGIC; 
  signal NlwRenamedSig_OI_flag_rd_und : STD_LOGIC; 
  signal NLW_x_fifo_data_outx_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_fifo_flag_empty_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_rst_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cmd_rdy_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_0_UNCONNECTED : STD_LOGIC; 
  signal NlwRenamedSig_OI_fifo_cnt_wr : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal NlwRenamedSignal_mode0 : STD_LOGIC_VECTOR ( 5 downto 5 ); 
begin
  flag_rd_ef <= NlwRenamedSig_OI_flag_rd_ef;
  flag_rd_ff <= NlwRenamedSig_OI_flag_rd_ff;
  flag_rd_hf <= NlwRenamedSig_OI_flag_rd_hf;
  start <= NlwRenamedSignal_mode0(5);
  flag_rd_ovr <= NlwRenamedSig_OI_flag_rd_ovr;
  fifo_rst <= NlwRenamedSig_OI_fifo_rst;
  flag_rd_und <= NlwRenamedSig_OI_flag_rd_und;
  flag_rd_pae <= NlwRenamedSig_OI_flag_rd_pae;
  flag_rd_paf <= NlwRenamedSig_OI_flag_rd_paf;
  fifo_cnt_rd(9) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(8) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(7) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(6) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(5) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(4) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(3) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(2) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(1) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_rd(0) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(9) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(8) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(7) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(6) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(5) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(4) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(3) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(2) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(1) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  fifo_cnt_wr(0) <= NlwRenamedSig_OI_fifo_cnt_wr(0);
  mode0(5) <= NlwRenamedSignal_mode0(5);
  XST_GND : GND
    port map (
      G => NlwRenamedSig_OI_fifo_cnt_wr(0)
    );
  chn : cl_chn_v3_INST_1
    port map (
      clk => clk,
      fifo_flag_und => NlwRenamedSig_OI_flag_rd_und,
      fifo_flag_pae => NlwRenamedSig_OI_flag_rd_pae,
      fifo_flag_paf => NlwRenamedSig_OI_flag_rd_paf,
      fdiv_we => NLW_chn_fdiv_we_UNCONNECTED,
      st10 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      bx_irq => bx_irq,
      st11 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      st12 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      st13 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      st14 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      st15 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      reset => reset,
      rst => NLW_chn_rst_UNCONNECTED,
      cmd_cmd_data_we => cmd_cmd_data_we,
      st9 => NlwRenamedSig_OI_fifo_cnt_wr(0),
      cmd_status_cs => cmd_status_cs,
      fifo_rst => NlwRenamedSig_OI_fifo_rst,
      cmd_data_cs => cmd_data_cs,
      cmd_rdy => NLW_chn_cmd_rdy_UNCONNECTED,
      fifo_flag_ovr => NlwRenamedSig_OI_flag_rd_ovr,
      bx_drq_en => bx_drq_en,
      bx_drq_ack => bx_drq_ack,
      cmd_data_oe => cmd_data_oe,
      cmd_cmd_data_cs => cmd_cmd_data_cs,
      rdy => NlwRenamedSig_OI_flag_rd_ef,
      fifo_flag_ef => NlwRenamedSig_OI_flag_rd_ef,
      cmd_cmd_adr_we => cmd_cmd_adr_we,
      fifo_flag_ff => NlwRenamedSig_OI_flag_rd_ff,
      cmd_data_we => cmd_data_we,
      fifo_flag_hf => NlwRenamedSig_OI_flag_rd_hf,
      bx_drq_req => bx_drq_req,
      sflag(15) => NLW_chn_sflag_15_UNCONNECTED,
      sflag(14) => NLW_chn_sflag_14_UNCONNECTED,
      sflag(13) => NLW_chn_sflag_13_UNCONNECTED,
      sflag(12) => NLW_chn_sflag_12_UNCONNECTED,
      sflag(11) => NLW_chn_sflag_11_UNCONNECTED,
      sflag(10) => NLW_chn_sflag_10_UNCONNECTED,
      sflag(9) => NLW_chn_sflag_9_UNCONNECTED,
      sflag(8) => NLW_chn_sflag_8_UNCONNECTED,
      sflag(7) => NLW_chn_sflag_7_UNCONNECTED,
      sflag(6) => NLW_chn_sflag_6_UNCONNECTED,
      sflag(5) => NLW_chn_sflag_5_UNCONNECTED,
      sflag(4) => NLW_chn_sflag_4_UNCONNECTED,
      sflag(3) => NLW_chn_sflag_3_UNCONNECTED,
      sflag(2) => NLW_chn_sflag_2_UNCONNECTED,
      sflag(1) => NLW_chn_sflag_1_UNCONNECTED,
      sflag(0) => NLW_chn_sflag_0_UNCONNECTED,
      stmode(15) => NLW_chn_stmode_15_UNCONNECTED,
      stmode(14) => NLW_chn_stmode_14_UNCONNECTED,
      stmode(13) => NLW_chn_stmode_13_UNCONNECTED,
      stmode(12) => NLW_chn_stmode_12_UNCONNECTED,
      stmode(11) => NLW_chn_stmode_11_UNCONNECTED,
      stmode(10) => NLW_chn_stmode_10_UNCONNECTED,
      stmode(9) => NLW_chn_stmode_9_UNCONNECTED,
      stmode(8) => NLW_chn_stmode_8_UNCONNECTED,
      stmode(7) => NLW_chn_stmode_7_UNCONNECTED,
      stmode(6) => NLW_chn_stmode_6_UNCONNECTED,
      stmode(5) => NLW_chn_stmode_5_UNCONNECTED,
      stmode(4) => NLW_chn_stmode_4_UNCONNECTED,
      stmode(3) => NLW_chn_stmode_3_UNCONNECTED,
      stmode(2) => NLW_chn_stmode_2_UNCONNECTED,
      stmode(1) => NLW_chn_stmode_1_UNCONNECTED,
      stmode(0) => NLW_chn_stmode_0_UNCONNECTED,
      mode0(15) => mode0(15),
      mode0(14) => mode0(14),
      mode0(13) => mode0(13),
      mode0(12) => mode0(12),
      mode0(11) => mode0(11),
      mode0(10) => mode0(10),
      mode0(9) => mode0(9),
      mode0(8) => mode0(8),
      mode0(7) => mode0(7),
      mode0(6) => mode0(6),
      mode0(5) => NlwRenamedSignal_mode0(5),
      mode0(4) => mode0(4),
      mode0(3) => mode0(3),
      mode0(2) => mode0(2),
      mode0(1) => mode0(1),
      mode0(0) => mode0(0),
      mode1(15) => mode1(15),
      mode1(14) => mode1(14),
      mode1(13) => mode1(13),
      mode1(12) => mode1(12),
      mode1(11) => mode1(11),
      mode1(10) => mode1(10),
      mode1(9) => mode1(9),
      mode1(8) => mode1(8),
      mode1(7) => mode1(7),
      mode1(6) => mode1(6),
      mode1(5) => mode1(5),
      mode1(4) => mode1(4),
      mode1(3) => mode1(3),
      mode1(2) => mode1(2),
      mode1(1) => mode1(1),
      mode1(0) => mode1(0),
      mode2(15) => mode2(15),
      mode2(14) => mode2(14),
      mode2(13) => mode2(13),
      mode2(12) => mode2(12),
      mode2(11) => mode2(11),
      mode2(10) => mode2(10),
      mode2(9) => mode2(9),
      mode2(8) => mode2(8),
      mode2(7) => mode2(7),
      mode2(6) => mode2(6),
      mode2(5) => mode2(5),
      mode2(4) => mode2(4),
      mode2(3) => mode2(3),
      mode2(2) => mode2(2),
      mode2(1) => mode2(1),
      mode2(0) => mode2(0),
      mode3(15) => mode3(15),
      mode3(14) => mode3(14),
      mode3(13) => mode3(13),
      mode3(12) => mode3(12),
      mode3(11) => mode3(11),
      mode3(10) => mode3(10),
      mode3(9) => mode3(9),
      mode3(8) => mode3(8),
      mode3(7) => mode3(7),
      mode3(6) => mode3(6),
      mode3(5) => mode3(5),
      mode3(4) => mode3(4),
      mode3(3) => mode3(3),
      mode3(2) => mode3(2),
      mode3(1) => mode3(1),
      mode3(0) => mode3(0),
      fdiv(15) => NLW_chn_fdiv_15_UNCONNECTED,
      fdiv(14) => NLW_chn_fdiv_14_UNCONNECTED,
      fdiv(13) => NLW_chn_fdiv_13_UNCONNECTED,
      fdiv(12) => NLW_chn_fdiv_12_UNCONNECTED,
      fdiv(11) => NLW_chn_fdiv_11_UNCONNECTED,
      fdiv(10) => NLW_chn_fdiv_10_UNCONNECTED,
      fdiv(9) => NLW_chn_fdiv_9_UNCONNECTED,
      fdiv(8) => NLW_chn_fdiv_8_UNCONNECTED,
      fdiv(7) => NLW_chn_fdiv_7_UNCONNECTED,
      fdiv(6) => NLW_chn_fdiv_6_UNCONNECTED,
      fdiv(5) => NLW_chn_fdiv_5_UNCONNECTED,
      fdiv(4) => NLW_chn_fdiv_4_UNCONNECTED,
      fdiv(3) => NLW_chn_fdiv_3_UNCONNECTED,
      fdiv(2) => NLW_chn_fdiv_2_UNCONNECTED,
      fdiv(1) => NLW_chn_fdiv_1_UNCONNECTED,
      fdiv(0) => NLW_chn_fdiv_0_UNCONNECTED,
      status(15) => cmd_data_out2(15),
      status(14) => cmd_data_out2(14),
      status(13) => cmd_data_out2(13),
      status(12) => cmd_data_out2(12),
      status(11) => cmd_data_out2(11),
      status(10) => cmd_data_out2(10),
      status(9) => cmd_data_out2(9),
      status(8) => cmd_data_out2(8),
      status(7) => cmd_data_out2(7),
      status(6) => cmd_data_out2(6),
      status(5) => cmd_data_out2(5),
      status(4) => cmd_data_out2(4),
      status(3) => cmd_data_out2(3),
      status(2) => cmd_data_out2(2),
      status(1) => cmd_data_out2(1),
      status(0) => cmd_data_out2(0),
      fmode(15) => NLW_chn_fmode_15_UNCONNECTED,
      fmode(14) => NLW_chn_fmode_14_UNCONNECTED,
      fmode(13) => NLW_chn_fmode_13_UNCONNECTED,
      fmode(12) => NLW_chn_fmode_12_UNCONNECTED,
      fmode(11) => NLW_chn_fmode_11_UNCONNECTED,
      fmode(10) => NLW_chn_fmode_10_UNCONNECTED,
      fmode(9) => NLW_chn_fmode_9_UNCONNECTED,
      fmode(8) => NLW_chn_fmode_8_UNCONNECTED,
      fmode(7) => NLW_chn_fmode_7_UNCONNECTED,
      fmode(6) => NLW_chn_fmode_6_UNCONNECTED,
      fmode(5) => NLW_chn_fmode_5_UNCONNECTED,
      fmode(4) => NLW_chn_fmode_4_UNCONNECTED,
      fmode(3) => NLW_chn_fmode_3_UNCONNECTED,
      fmode(2) => NLW_chn_fmode_2_UNCONNECTED,
      fmode(1) => NLW_chn_fmode_1_UNCONNECTED,
      fmode(0) => NLW_chn_fmode_0_UNCONNECTED,
      cnt0(15) => NLW_chn_cnt0_15_UNCONNECTED,
      cnt0(14) => NLW_chn_cnt0_14_UNCONNECTED,
      cnt0(13) => NLW_chn_cnt0_13_UNCONNECTED,
      cnt0(12) => NLW_chn_cnt0_12_UNCONNECTED,
      cnt0(11) => NLW_chn_cnt0_11_UNCONNECTED,
      cnt0(10) => NLW_chn_cnt0_10_UNCONNECTED,
      cnt0(9) => NLW_chn_cnt0_9_UNCONNECTED,
      cnt0(8) => NLW_chn_cnt0_8_UNCONNECTED,
      cnt0(7) => NLW_chn_cnt0_7_UNCONNECTED,
      cnt0(6) => NLW_chn_cnt0_6_UNCONNECTED,
      cnt0(5) => NLW_chn_cnt0_5_UNCONNECTED,
      cnt0(4) => NLW_chn_cnt0_4_UNCONNECTED,
      cnt0(3) => NLW_chn_cnt0_3_UNCONNECTED,
      cnt0(2) => NLW_chn_cnt0_2_UNCONNECTED,
      cnt0(1) => NLW_chn_cnt0_1_UNCONNECTED,
      cnt0(0) => NLW_chn_cnt0_0_UNCONNECTED,
      cnt1(15) => NLW_chn_cnt1_15_UNCONNECTED,
      cnt1(14) => NLW_chn_cnt1_14_UNCONNECTED,
      cnt1(13) => NLW_chn_cnt1_13_UNCONNECTED,
      cnt1(12) => NLW_chn_cnt1_12_UNCONNECTED,
      cnt1(11) => NLW_chn_cnt1_11_UNCONNECTED,
      cnt1(10) => NLW_chn_cnt1_10_UNCONNECTED,
      cnt1(9) => NLW_chn_cnt1_9_UNCONNECTED,
      cnt1(8) => NLW_chn_cnt1_8_UNCONNECTED,
      cnt1(7) => NLW_chn_cnt1_7_UNCONNECTED,
      cnt1(6) => NLW_chn_cnt1_6_UNCONNECTED,
      cnt1(5) => NLW_chn_cnt1_5_UNCONNECTED,
      cnt1(4) => NLW_chn_cnt1_4_UNCONNECTED,
      cnt1(3) => NLW_chn_cnt1_3_UNCONNECTED,
      cnt1(2) => NLW_chn_cnt1_2_UNCONNECTED,
      cnt1(1) => NLW_chn_cnt1_1_UNCONNECTED,
      cnt1(0) => NLW_chn_cnt1_0_UNCONNECTED,
      cnt2(15) => NLW_chn_cnt2_15_UNCONNECTED,
      cnt2(14) => NLW_chn_cnt2_14_UNCONNECTED,
      cnt2(13) => NLW_chn_cnt2_13_UNCONNECTED,
      cnt2(12) => NLW_chn_cnt2_12_UNCONNECTED,
      cnt2(11) => NLW_chn_cnt2_11_UNCONNECTED,
      cnt2(10) => NLW_chn_cnt2_10_UNCONNECTED,
      cnt2(9) => NLW_chn_cnt2_9_UNCONNECTED,
      cnt2(8) => NLW_chn_cnt2_8_UNCONNECTED,
      cnt2(7) => NLW_chn_cnt2_7_UNCONNECTED,
      cnt2(6) => NLW_chn_cnt2_6_UNCONNECTED,
      cnt2(5) => NLW_chn_cnt2_5_UNCONNECTED,
      cnt2(4) => NLW_chn_cnt2_4_UNCONNECTED,
      cnt2(3) => NLW_chn_cnt2_3_UNCONNECTED,
      cnt2(2) => NLW_chn_cnt2_2_UNCONNECTED,
      cnt2(1) => NLW_chn_cnt2_1_UNCONNECTED,
      cnt2(0) => NLW_chn_cnt2_0_UNCONNECTED,
      data_in(15) => cmd_data_in(15),
      data_in(14) => cmd_data_in(14),
      data_in(13) => cmd_data_in(13),
      data_in(12) => cmd_data_in(12),
      data_in(11) => cmd_data_in(11),
      data_in(10) => cmd_data_in(10),
      data_in(9) => cmd_data_in(9),
      data_in(8) => cmd_data_in(8),
      data_in(7) => cmd_data_in(7),
      data_in(6) => cmd_data_in(6),
      data_in(5) => cmd_data_in(5),
      data_in(4) => cmd_data_in(4),
      data_in(3) => cmd_data_in(3),
      data_in(2) => cmd_data_in(2),
      data_in(1) => cmd_data_in(1),
      data_in(0) => cmd_data_in(0),
      cmd_adr(9) => cmd_adr(9),
      cmd_adr(8) => cmd_adr(8),
      cmd_adr(7) => cmd_adr(7),
      cmd_adr(6) => cmd_adr(6),
      cmd_adr(5) => cmd_adr(5),
      cmd_adr(4) => cmd_adr(4),
      cmd_adr(3) => cmd_adr(3),
      cmd_adr(2) => cmd_adr(2),
      cmd_adr(1) => cmd_adr(1),
      cmd_adr(0) => cmd_adr(0)
    );
  x_fifo : cl_fifo1024x65_v5
    port map (
      flag_rd_ef => NlwRenamedSig_OI_flag_rd_ef,
      flag_rd_ff => NlwRenamedSig_OI_flag_rd_ff,
      flag_rd_hf => NlwRenamedSig_OI_flag_rd_hf,
      flag_wr_und => flag_wr_und,
      flag_wr_pae => flag_wr_pae,
      flag_wr_paf => flag_wr_paf,
      reset => NlwRenamedSig_OI_fifo_rst,
      data_cs => cmd_data_cs,
      data_en => data_wr,
      data_inx => NlwRenamedSig_OI_fifo_cnt_wr(0),
      flag_wr_ef => flag_wr_ef,
      clk_rd => clk,
      flag_wr_ff => flag_wr_ff,
      flag_rd_ovr => NlwRenamedSig_OI_flag_rd_ovr,
      flag_wr_hf => flag_wr_hf,
      data_outx => NLW_x_fifo_data_outx_UNCONNECTED,
      clk_wr => clk_wr,
      flag_wr_ovr => flag_wr_ovr,
      flag_empty => NLW_x_fifo_flag_empty_UNCONNECTED,
      flag_rd_und => NlwRenamedSig_OI_flag_rd_und,
      flag_rd_pae => NlwRenamedSig_OI_flag_rd_pae,
      flag_rd_paf => NlwRenamedSig_OI_flag_rd_paf,
      data_out(63) => data_out2(63),
      data_out(62) => data_out2(62),
      data_out(61) => data_out2(61),
      data_out(60) => data_out2(60),
      data_out(59) => data_out2(59),
      data_out(58) => data_out2(58),
      data_out(57) => data_out2(57),
      data_out(56) => data_out2(56),
      data_out(55) => data_out2(55),
      data_out(54) => data_out2(54),
      data_out(53) => data_out2(53),
      data_out(52) => data_out2(52),
      data_out(51) => data_out2(51),
      data_out(50) => data_out2(50),
      data_out(49) => data_out2(49),
      data_out(48) => data_out2(48),
      data_out(47) => data_out2(47),
      data_out(46) => data_out2(46),
      data_out(45) => data_out2(45),
      data_out(44) => data_out2(44),
      data_out(43) => data_out2(43),
      data_out(42) => data_out2(42),
      data_out(41) => data_out2(41),
      data_out(40) => data_out2(40),
      data_out(39) => data_out2(39),
      data_out(38) => data_out2(38),
      data_out(37) => data_out2(37),
      data_out(36) => data_out2(36),
      data_out(35) => data_out2(35),
      data_out(34) => data_out2(34),
      data_out(33) => data_out2(33),
      data_out(32) => data_out2(32),
      data_out(31) => data_out2(31),
      data_out(30) => data_out2(30),
      data_out(29) => data_out2(29),
      data_out(28) => data_out2(28),
      data_out(27) => data_out2(27),
      data_out(26) => data_out2(26),
      data_out(25) => data_out2(25),
      data_out(24) => data_out2(24),
      data_out(23) => data_out2(23),
      data_out(22) => data_out2(22),
      data_out(21) => data_out2(21),
      data_out(20) => data_out2(20),
      data_out(19) => data_out2(19),
      data_out(18) => data_out2(18),
      data_out(17) => data_out2(17),
      data_out(16) => data_out2(16),
      data_out(15) => data_out2(15),
      data_out(14) => data_out2(14),
      data_out(13) => data_out2(13),
      data_out(12) => data_out2(12),
      data_out(11) => data_out2(11),
      data_out(10) => data_out2(10),
      data_out(9) => data_out2(9),
      data_out(8) => data_out2(8),
      data_out(7) => data_out2(7),
      data_out(6) => data_out2(6),
      data_out(5) => data_out2(5),
      data_out(4) => data_out2(4),
      data_out(3) => data_out2(3),
      data_out(2) => data_out2(2),
      data_out(1) => data_out2(1),
      data_out(0) => data_out2(0),
      data_in(63) => data_in(63),
      data_in(62) => data_in(62),
      data_in(61) => data_in(61),
      data_in(60) => data_in(60),
      data_in(59) => data_in(59),
      data_in(58) => data_in(58),
      data_in(57) => data_in(57),
      data_in(56) => data_in(56),
      data_in(55) => data_in(55),
      data_in(54) => data_in(54),
      data_in(53) => data_in(53),
      data_in(52) => data_in(52),
      data_in(51) => data_in(51),
      data_in(50) => data_in(50),
      data_in(49) => data_in(49),
      data_in(48) => data_in(48),
      data_in(47) => data_in(47),
      data_in(46) => data_in(46),
      data_in(45) => data_in(45),
      data_in(44) => data_in(44),
      data_in(43) => data_in(43),
      data_in(42) => data_in(42),
      data_in(41) => data_in(41),
      data_in(40) => data_in(40),
      data_in(39) => data_in(39),
      data_in(38) => data_in(38),
      data_in(37) => data_in(37),
      data_in(36) => data_in(36),
      data_in(35) => data_in(35),
      data_in(34) => data_in(34),
      data_in(33) => data_in(33),
      data_in(32) => data_in(32),
      data_in(31) => data_in(31),
      data_in(30) => data_in(30),
      data_in(29) => data_in(29),
      data_in(28) => data_in(28),
      data_in(27) => data_in(27),
      data_in(26) => data_in(26),
      data_in(25) => data_in(25),
      data_in(24) => data_in(24),
      data_in(23) => data_in(23),
      data_in(22) => data_in(22),
      data_in(21) => data_in(21),
      data_in(20) => data_in(20),
      data_in(19) => data_in(19),
      data_in(18) => data_in(18),
      data_in(17) => data_in(17),
      data_in(16) => data_in(16),
      data_in(15) => data_in(15),
      data_in(14) => data_in(14),
      data_in(13) => data_in(13),
      data_in(12) => data_in(12),
      data_in(11) => data_in(11),
      data_in(10) => data_in(10),
      data_in(9) => data_in(9),
      data_in(8) => data_in(8),
      data_in(7) => data_in(7),
      data_in(6) => data_in(6),
      data_in(5) => data_in(5),
      data_in(4) => data_in(4),
      data_in(3) => data_in(3),
      data_in(2) => data_in(2),
      data_in(1) => data_in(1),
      data_in(0) => data_in(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_freq_INST_2 is
  port (
    clk_in : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    freq_en : out STD_LOGIC; 
    clk_sys : in STD_LOGIC := 'X'; 
    freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end ctrl_freq_INST_2;

architecture STRUCTURE of ctrl_freq_INST_2 is
  component ctrl_multiplier_v1_0
    port (
      clk : in STD_LOGIC := 'X'; 
      p : out STD_LOGIC_VECTOR ( 26 downto 0 ); 
      a : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 
    );
  end component;
  signal Madd_freq_adc_add0000_cy_10_rt_5135 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_11_rt_5137 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_12_rt_5139 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_13_rt_5141 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_14_rt_5143 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_1_rt_5145 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_2_rt_5147 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_3_rt_5149 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_4_rt_5151 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_5_rt_5153 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_6_rt_5155 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_7_rt_5157 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_8_rt_5159 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_9_rt_5161 : STD_LOGIC; 
  signal Mcount_cnt_value : STD_LOGIC; 
  signal Mcount_cnt_value1 : STD_LOGIC; 
  signal Mcount_cnt_value10 : STD_LOGIC; 
  signal Mcount_cnt_value11 : STD_LOGIC; 
  signal Mcount_cnt_value12 : STD_LOGIC; 
  signal Mcount_cnt_value2 : STD_LOGIC; 
  signal Mcount_cnt_value3 : STD_LOGIC; 
  signal Mcount_cnt_value4 : STD_LOGIC; 
  signal Mcount_cnt_value5 : STD_LOGIC; 
  signal Mcount_cnt_value6 : STD_LOGIC; 
  signal Mcount_cnt_value7 : STD_LOGIC; 
  signal Mcount_cnt_value8 : STD_LOGIC; 
  signal Mcount_cnt_value9 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_10_rt_5178 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_11_rt_5180 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_12_rt_5182 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_13_rt_5184 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_14_rt_5186 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_1_rt_5188 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_2_rt_5190 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_3_rt_5192 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_4_rt_5194 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_5_rt_5196 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_6_rt_5198 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_7_rt_5200 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_8_rt_5202 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_cy_9_rt_5204 : STD_LOGIC; 
  signal Mcount_cnt_value_adc_xor_15_rt_5206 : STD_LOGIC; 
  signal Mcount_new_cnt_c : STD_LOGIC; 
  signal Mcount_new_cnt_c1 : STD_LOGIC; 
  signal Mcount_new_cnt_c2 : STD_LOGIC; 
  signal Mcount_new_cnt_c3 : STD_LOGIC; 
  signal cnt_value_adc0_and0000 : STD_LOGIC; 
  signal cnt_value_adc_not0001 : STD_LOGIC; 
  signal freq_sys_0_Q : STD_LOGIC; 
  signal freq_sys_3_Q : STD_LOGIC; 
  signal new_cnt_5335 : STD_LOGIC; 
  signal new_cnt_c_not0001 : STD_LOGIC; 
  signal new_cnt_inv : STD_LOGIC; 
  signal new_cnt_mux0001 : STD_LOGIC; 
  signal new_cnt_z_5343 : STD_LOGIC; 
  signal new_cnt_z1_5344 : STD_LOGIC; 
  signal new_cnt_z2_5345 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NLW_x_mult_p_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_0_UNCONNECTED : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Madd_freq_adc_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_adc_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Mcount_cnt_value_adc_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_cy : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Mcount_cnt_value_lut : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal Result : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cnt_value : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal cnt_value_adc0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cnt_value_adc : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal freq_adc_add0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal new_cnt_c : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal result_freq : STD_LOGIC_VECTOR ( 26 downto 10 ); 
begin
  XST_GND : GND
    port map (
      G => freq_sys_0_Q
    );
  XST_VCC : VCC
    port map (
      P => freq_sys_3_Q
    );
  new_cnt : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => new_cnt_mux0001,
      Q => new_cnt_5335
    );
  new_cnt_z : FD
    port map (
      C => clk_in,
      D => new_cnt_5335,
      Q => new_cnt_z_5343
    );
  cnt_value_adc0_0 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(0),
      Q => cnt_value_adc0(0)
    );
  cnt_value_adc0_1 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(1),
      Q => cnt_value_adc0(1)
    );
  cnt_value_adc0_2 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(2),
      Q => cnt_value_adc0(2)
    );
  cnt_value_adc0_3 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(3),
      Q => cnt_value_adc0(3)
    );
  cnt_value_adc0_4 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(4),
      Q => cnt_value_adc0(4)
    );
  cnt_value_adc0_5 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(5),
      Q => cnt_value_adc0(5)
    );
  cnt_value_adc0_6 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(6),
      Q => cnt_value_adc0(6)
    );
  cnt_value_adc0_7 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(7),
      Q => cnt_value_adc0(7)
    );
  cnt_value_adc0_8 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(8),
      Q => cnt_value_adc0(8)
    );
  cnt_value_adc0_9 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(9),
      Q => cnt_value_adc0(9)
    );
  cnt_value_adc0_10 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(10),
      Q => cnt_value_adc0(10)
    );
  cnt_value_adc0_11 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(11),
      Q => cnt_value_adc0(11)
    );
  cnt_value_adc0_12 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(12),
      Q => cnt_value_adc0(12)
    );
  cnt_value_adc0_13 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(13),
      Q => cnt_value_adc0(13)
    );
  cnt_value_adc0_14 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(14),
      Q => cnt_value_adc0(14)
    );
  cnt_value_adc0_15 : FDE
    port map (
      C => clk_in,
      CE => cnt_value_adc0_and0000,
      D => cnt_value_adc(15),
      Q => cnt_value_adc0(15)
    );
  new_cnt_z1 : FD
    port map (
      C => clk_in,
      D => new_cnt_z_5343,
      Q => new_cnt_z1_5344
    );
  new_cnt_z2 : FD
    port map (
      C => clk_sys,
      D => new_cnt_z1_5344,
      Q => new_cnt_z2_5345
    );
  freq_adc_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(0),
      Q => freq_adc(0)
    );
  freq_adc_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(1),
      Q => freq_adc(1)
    );
  freq_adc_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(2),
      Q => freq_adc(2)
    );
  freq_adc_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(3),
      Q => freq_adc(3)
    );
  freq_adc_4 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(4),
      Q => freq_adc(4)
    );
  freq_adc_5 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(5),
      Q => freq_adc(5)
    );
  freq_adc_6 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(6),
      Q => freq_adc(6)
    );
  freq_adc_7 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(7),
      Q => freq_adc(7)
    );
  freq_adc_8 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(8),
      Q => freq_adc(8)
    );
  freq_adc_9 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(9),
      Q => freq_adc(9)
    );
  freq_adc_10 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(10),
      Q => freq_adc(10)
    );
  freq_adc_11 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(11),
      Q => freq_adc(11)
    );
  freq_adc_12 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(12),
      Q => freq_adc(12)
    );
  freq_adc_13 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(13),
      Q => freq_adc(13)
    );
  freq_adc_14 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(14),
      Q => freq_adc(14)
    );
  freq_adc_15 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(15),
      Q => freq_adc(15)
    );
  Mcount_cnt_value_lut_0_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(0),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(0)
    );
  Mcount_cnt_value_cy_0_Q : MUXCY
    port map (
      CI => new_cnt_inv,
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value_cy(0)
    );
  Mcount_cnt_value_xor_0_Q : XORCY
    port map (
      CI => new_cnt_inv,
      LI => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value
    );
  Mcount_cnt_value_lut_1_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(1),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(1)
    );
  Mcount_cnt_value_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value_cy(1)
    );
  Mcount_cnt_value_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      LI => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value1
    );
  Mcount_cnt_value_lut_2_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(2),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(2)
    );
  Mcount_cnt_value_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value_cy(2)
    );
  Mcount_cnt_value_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      LI => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value2
    );
  Mcount_cnt_value_lut_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(3),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(3)
    );
  Mcount_cnt_value_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value_cy(3)
    );
  Mcount_cnt_value_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      LI => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value3
    );
  Mcount_cnt_value_lut_4_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(4),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(4)
    );
  Mcount_cnt_value_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value_cy(4)
    );
  Mcount_cnt_value_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      LI => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value4
    );
  Mcount_cnt_value_lut_5_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(5),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(5)
    );
  Mcount_cnt_value_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value_cy(5)
    );
  Mcount_cnt_value_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      LI => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value5
    );
  Mcount_cnt_value_lut_6_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(6),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(6)
    );
  Mcount_cnt_value_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value_cy(6)
    );
  Mcount_cnt_value_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      LI => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value6
    );
  Mcount_cnt_value_lut_7_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(7),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(7)
    );
  Mcount_cnt_value_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value_cy(7)
    );
  Mcount_cnt_value_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      LI => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value7
    );
  Mcount_cnt_value_lut_8_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(8),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(8)
    );
  Mcount_cnt_value_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value_cy(8)
    );
  Mcount_cnt_value_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      LI => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value8
    );
  Mcount_cnt_value_lut_9_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(9),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(9)
    );
  Mcount_cnt_value_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value_cy(9)
    );
  Mcount_cnt_value_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      LI => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value9
    );
  Mcount_cnt_value_lut_10_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(10),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(10)
    );
  Mcount_cnt_value_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value_cy(10)
    );
  Mcount_cnt_value_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      LI => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value10
    );
  Mcount_cnt_value_lut_11_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(11),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(11)
    );
  Mcount_cnt_value_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value_cy(11)
    );
  Mcount_cnt_value_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      LI => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value11
    );
  Mcount_cnt_value_lut_12_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(12),
      I2 => freq_sys_0_Q,
      O => Mcount_cnt_value_lut(12)
    );
  Mcount_cnt_value_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(11),
      LI => Mcount_cnt_value_lut(12),
      O => Mcount_cnt_value12
    );
  cnt_value_0 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value,
      Q => cnt_value(0)
    );
  cnt_value_1 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value1,
      Q => cnt_value(1)
    );
  cnt_value_2 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value2,
      Q => cnt_value(2)
    );
  cnt_value_3 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value3,
      Q => cnt_value(3)
    );
  cnt_value_4 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value4,
      Q => cnt_value(4)
    );
  cnt_value_5 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value5,
      Q => cnt_value(5)
    );
  cnt_value_6 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value6,
      Q => cnt_value(6)
    );
  cnt_value_7 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value7,
      Q => cnt_value(7)
    );
  cnt_value_8 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value8,
      Q => cnt_value(8)
    );
  cnt_value_9 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value9,
      Q => cnt_value(9)
    );
  cnt_value_10 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value10,
      Q => cnt_value(10)
    );
  cnt_value_11 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value11,
      Q => cnt_value(11)
    );
  cnt_value_12 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value12,
      Q => cnt_value(12)
    );
  cnt_value_adc_0 : FDR
    port map (
      C => clk_in,
      D => Result(0),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(0)
    );
  cnt_value_adc_1 : FDR
    port map (
      C => clk_in,
      D => Result(1),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(1)
    );
  cnt_value_adc_2 : FDR
    port map (
      C => clk_in,
      D => Result(2),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(2)
    );
  cnt_value_adc_3 : FDR
    port map (
      C => clk_in,
      D => Result(3),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(3)
    );
  cnt_value_adc_4 : FDR
    port map (
      C => clk_in,
      D => Result(4),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(4)
    );
  cnt_value_adc_5 : FDR
    port map (
      C => clk_in,
      D => Result(5),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(5)
    );
  cnt_value_adc_6 : FDR
    port map (
      C => clk_in,
      D => Result(6),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(6)
    );
  cnt_value_adc_7 : FDR
    port map (
      C => clk_in,
      D => Result(7),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(7)
    );
  cnt_value_adc_8 : FDR
    port map (
      C => clk_in,
      D => Result(8),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(8)
    );
  cnt_value_adc_9 : FDR
    port map (
      C => clk_in,
      D => Result(9),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(9)
    );
  cnt_value_adc_10 : FDR
    port map (
      C => clk_in,
      D => Result(10),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(10)
    );
  cnt_value_adc_11 : FDR
    port map (
      C => clk_in,
      D => Result(11),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(11)
    );
  cnt_value_adc_12 : FDR
    port map (
      C => clk_in,
      D => Result(12),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(12)
    );
  cnt_value_adc_13 : FDR
    port map (
      C => clk_in,
      D => Result(13),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(13)
    );
  cnt_value_adc_14 : FDR
    port map (
      C => clk_in,
      D => Result(14),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(14)
    );
  cnt_value_adc_15 : FDR
    port map (
      C => clk_in,
      D => Result(15),
      R => cnt_value_adc_not0001,
      Q => cnt_value_adc(15)
    );
  new_cnt_c_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c,
      Q => new_cnt_c(0)
    );
  new_cnt_c_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c1,
      Q => new_cnt_c(1)
    );
  new_cnt_c_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c2,
      Q => new_cnt_c(2)
    );
  new_cnt_c_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c3,
      Q => new_cnt_c(3)
    );
  Mcount_cnt_value_adc_cy_0_Q : MUXCY
    port map (
      CI => freq_sys_0_Q,
      DI => freq_sys_3_Q,
      S => Mcount_cnt_value_adc_lut(0),
      O => Mcount_cnt_value_adc_cy(0)
    );
  Mcount_cnt_value_adc_xor_0_Q : XORCY
    port map (
      CI => freq_sys_0_Q,
      LI => Mcount_cnt_value_adc_lut(0),
      O => Result(0)
    );
  Mcount_cnt_value_adc_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_1_rt_5188,
      O => Mcount_cnt_value_adc_cy(1)
    );
  Mcount_cnt_value_adc_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      LI => Mcount_cnt_value_adc_cy_1_rt_5188,
      O => Result(1)
    );
  Mcount_cnt_value_adc_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(1),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_2_rt_5190,
      O => Mcount_cnt_value_adc_cy(2)
    );
  Mcount_cnt_value_adc_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(1),
      LI => Mcount_cnt_value_adc_cy_2_rt_5190,
      O => Result(2)
    );
  Mcount_cnt_value_adc_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(2),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_3_rt_5192,
      O => Mcount_cnt_value_adc_cy(3)
    );
  Mcount_cnt_value_adc_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(2),
      LI => Mcount_cnt_value_adc_cy_3_rt_5192,
      O => Result(3)
    );
  Mcount_cnt_value_adc_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(3),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_4_rt_5194,
      O => Mcount_cnt_value_adc_cy(4)
    );
  Mcount_cnt_value_adc_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(3),
      LI => Mcount_cnt_value_adc_cy_4_rt_5194,
      O => Result(4)
    );
  Mcount_cnt_value_adc_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(4),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_5_rt_5196,
      O => Mcount_cnt_value_adc_cy(5)
    );
  Mcount_cnt_value_adc_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(4),
      LI => Mcount_cnt_value_adc_cy_5_rt_5196,
      O => Result(5)
    );
  Mcount_cnt_value_adc_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(5),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_6_rt_5198,
      O => Mcount_cnt_value_adc_cy(6)
    );
  Mcount_cnt_value_adc_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(5),
      LI => Mcount_cnt_value_adc_cy_6_rt_5198,
      O => Result(6)
    );
  Mcount_cnt_value_adc_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(6),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_7_rt_5200,
      O => Mcount_cnt_value_adc_cy(7)
    );
  Mcount_cnt_value_adc_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(6),
      LI => Mcount_cnt_value_adc_cy_7_rt_5200,
      O => Result(7)
    );
  Mcount_cnt_value_adc_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(7),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_8_rt_5202,
      O => Mcount_cnt_value_adc_cy(8)
    );
  Mcount_cnt_value_adc_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(7),
      LI => Mcount_cnt_value_adc_cy_8_rt_5202,
      O => Result(8)
    );
  Mcount_cnt_value_adc_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(8),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_9_rt_5204,
      O => Mcount_cnt_value_adc_cy(9)
    );
  Mcount_cnt_value_adc_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(8),
      LI => Mcount_cnt_value_adc_cy_9_rt_5204,
      O => Result(9)
    );
  Mcount_cnt_value_adc_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(9),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_10_rt_5178,
      O => Mcount_cnt_value_adc_cy(10)
    );
  Mcount_cnt_value_adc_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(9),
      LI => Mcount_cnt_value_adc_cy_10_rt_5178,
      O => Result(10)
    );
  Mcount_cnt_value_adc_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(10),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_11_rt_5180,
      O => Mcount_cnt_value_adc_cy(11)
    );
  Mcount_cnt_value_adc_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(10),
      LI => Mcount_cnt_value_adc_cy_11_rt_5180,
      O => Result(11)
    );
  Mcount_cnt_value_adc_cy_12_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(11),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_12_rt_5182,
      O => Mcount_cnt_value_adc_cy(12)
    );
  Mcount_cnt_value_adc_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(11),
      LI => Mcount_cnt_value_adc_cy_12_rt_5182,
      O => Result(12)
    );
  Mcount_cnt_value_adc_cy_13_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(12),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_13_rt_5184,
      O => Mcount_cnt_value_adc_cy(13)
    );
  Mcount_cnt_value_adc_xor_13_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(12),
      LI => Mcount_cnt_value_adc_cy_13_rt_5184,
      O => Result(13)
    );
  Mcount_cnt_value_adc_cy_14_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(13),
      DI => freq_sys_0_Q,
      S => Mcount_cnt_value_adc_cy_14_rt_5186,
      O => Mcount_cnt_value_adc_cy(14)
    );
  Mcount_cnt_value_adc_xor_14_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(13),
      LI => Mcount_cnt_value_adc_cy_14_rt_5186,
      O => Result(14)
    );
  Mcount_cnt_value_adc_xor_15_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(14),
      LI => Mcount_cnt_value_adc_xor_15_rt_5206,
      O => Result(15)
    );
  Madd_freq_adc_add0000_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => result_freq(11),
      I1 => result_freq(10),
      O => Madd_freq_adc_add0000_lut(0)
    );
  Madd_freq_adc_add0000_cy_0_Q : MUXCY
    port map (
      CI => freq_sys_0_Q,
      DI => result_freq(11),
      S => Madd_freq_adc_add0000_lut(0),
      O => Madd_freq_adc_add0000_cy(0)
    );
  Madd_freq_adc_add0000_xor_0_Q : XORCY
    port map (
      CI => freq_sys_0_Q,
      LI => Madd_freq_adc_add0000_lut(0),
      O => freq_adc_add0000(0)
    );
  Madd_freq_adc_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_1_rt_5145,
      O => Madd_freq_adc_add0000_cy(1)
    );
  Madd_freq_adc_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      LI => Madd_freq_adc_add0000_cy_1_rt_5145,
      O => freq_adc_add0000(1)
    );
  Madd_freq_adc_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_2_rt_5147,
      O => Madd_freq_adc_add0000_cy(2)
    );
  Madd_freq_adc_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      LI => Madd_freq_adc_add0000_cy_2_rt_5147,
      O => freq_adc_add0000(2)
    );
  Madd_freq_adc_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_3_rt_5149,
      O => Madd_freq_adc_add0000_cy(3)
    );
  Madd_freq_adc_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      LI => Madd_freq_adc_add0000_cy_3_rt_5149,
      O => freq_adc_add0000(3)
    );
  Madd_freq_adc_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_4_rt_5151,
      O => Madd_freq_adc_add0000_cy(4)
    );
  Madd_freq_adc_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      LI => Madd_freq_adc_add0000_cy_4_rt_5151,
      O => freq_adc_add0000(4)
    );
  Madd_freq_adc_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_5_rt_5153,
      O => Madd_freq_adc_add0000_cy(5)
    );
  Madd_freq_adc_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      LI => Madd_freq_adc_add0000_cy_5_rt_5153,
      O => freq_adc_add0000(5)
    );
  Madd_freq_adc_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_6_rt_5155,
      O => Madd_freq_adc_add0000_cy(6)
    );
  Madd_freq_adc_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      LI => Madd_freq_adc_add0000_cy_6_rt_5155,
      O => freq_adc_add0000(6)
    );
  Madd_freq_adc_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_7_rt_5157,
      O => Madd_freq_adc_add0000_cy(7)
    );
  Madd_freq_adc_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      LI => Madd_freq_adc_add0000_cy_7_rt_5157,
      O => freq_adc_add0000(7)
    );
  Madd_freq_adc_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_8_rt_5159,
      O => Madd_freq_adc_add0000_cy(8)
    );
  Madd_freq_adc_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      LI => Madd_freq_adc_add0000_cy_8_rt_5159,
      O => freq_adc_add0000(8)
    );
  Madd_freq_adc_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_9_rt_5161,
      O => Madd_freq_adc_add0000_cy(9)
    );
  Madd_freq_adc_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      LI => Madd_freq_adc_add0000_cy_9_rt_5161,
      O => freq_adc_add0000(9)
    );
  Madd_freq_adc_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_10_rt_5135,
      O => Madd_freq_adc_add0000_cy(10)
    );
  Madd_freq_adc_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      LI => Madd_freq_adc_add0000_cy_10_rt_5135,
      O => freq_adc_add0000(10)
    );
  Madd_freq_adc_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_11_rt_5137,
      O => Madd_freq_adc_add0000_cy(11)
    );
  Madd_freq_adc_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      LI => Madd_freq_adc_add0000_cy_11_rt_5137,
      O => freq_adc_add0000(11)
    );
  Madd_freq_adc_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_12_rt_5139,
      O => Madd_freq_adc_add0000_cy(12)
    );
  Madd_freq_adc_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      LI => Madd_freq_adc_add0000_cy_12_rt_5139,
      O => freq_adc_add0000(12)
    );
  Madd_freq_adc_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_13_rt_5141,
      O => Madd_freq_adc_add0000_cy(13)
    );
  Madd_freq_adc_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      LI => Madd_freq_adc_add0000_cy_13_rt_5141,
      O => freq_adc_add0000(13)
    );
  Madd_freq_adc_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      DI => freq_sys_0_Q,
      S => Madd_freq_adc_add0000_cy_14_rt_5143,
      O => Madd_freq_adc_add0000_cy(14)
    );
  Madd_freq_adc_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      LI => Madd_freq_adc_add0000_cy_14_rt_5143,
      O => freq_adc_add0000(14)
    );
  Madd_freq_adc_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(14),
      LI => result_freq(26),
      O => freq_adc_add0000(15)
    );
  x_mult : ctrl_multiplier_v1_0
    port map (
      clk => clk_sys,
      p(26) => result_freq(26),
      p(25) => result_freq(25),
      p(24) => result_freq(24),
      p(23) => result_freq(23),
      p(22) => result_freq(22),
      p(21) => result_freq(21),
      p(20) => result_freq(20),
      p(19) => result_freq(19),
      p(18) => result_freq(18),
      p(17) => result_freq(17),
      p(16) => result_freq(16),
      p(15) => result_freq(15),
      p(14) => result_freq(14),
      p(13) => result_freq(13),
      p(12) => result_freq(12),
      p(11) => result_freq(11),
      p(10) => result_freq(10),
      p(9) => NLW_x_mult_p_9_UNCONNECTED,
      p(8) => NLW_x_mult_p_8_UNCONNECTED,
      p(7) => NLW_x_mult_p_7_UNCONNECTED,
      p(6) => NLW_x_mult_p_6_UNCONNECTED,
      p(5) => NLW_x_mult_p_5_UNCONNECTED,
      p(4) => NLW_x_mult_p_4_UNCONNECTED,
      p(3) => NLW_x_mult_p_3_UNCONNECTED,
      p(2) => NLW_x_mult_p_2_UNCONNECTED,
      p(1) => NLW_x_mult_p_1_UNCONNECTED,
      p(0) => NLW_x_mult_p_0_UNCONNECTED,
      a(15) => cnt_value_adc0(15),
      a(14) => cnt_value_adc0(14),
      a(13) => cnt_value_adc0(13),
      a(12) => cnt_value_adc0(12),
      a(11) => cnt_value_adc0(11),
      a(10) => cnt_value_adc0(10),
      a(9) => cnt_value_adc0(9),
      a(8) => cnt_value_adc0(8),
      a(7) => cnt_value_adc0(7),
      a(6) => cnt_value_adc0(6),
      a(5) => cnt_value_adc0(5),
      a(4) => cnt_value_adc0(4),
      a(3) => cnt_value_adc0(3),
      a(2) => cnt_value_adc0(2),
      a(1) => cnt_value_adc0(1),
      a(0) => cnt_value_adc0(0),
      b(10) => freq_sys_0_Q,
      b(9) => freq_sys_3_Q,
      b(8) => freq_sys_3_Q,
      b(7) => freq_sys_3_Q,
      b(6) => freq_sys_3_Q,
      b(5) => freq_sys_3_Q,
      b(4) => freq_sys_0_Q,
      b(3) => freq_sys_3_Q,
      b(2) => freq_sys_0_Q,
      b(1) => freq_sys_0_Q,
      b(0) => freq_sys_0_Q
    );
  Mcount_new_cnt_c_xor_0_11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => new_cnt_c(0),
      I1 => new_cnt_5335,
      O => Mcount_new_cnt_c
    );
  new_cnt_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => cnt_value(12),
      I2 => new_cnt_c(3),
      O => new_cnt_mux0001
    );
  Mcount_new_cnt_c_xor_1_11 : LUT3
    generic map(
      INIT => X"28"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => new_cnt_c(0),
      I2 => new_cnt_c(1),
      O => Mcount_new_cnt_c1
    );
  Mcount_new_cnt_c_xor_2_11 : LUT4
    generic map(
      INIT => X"2888"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => new_cnt_c(2),
      I2 => new_cnt_c(0),
      I3 => new_cnt_c(1),
      O => Mcount_new_cnt_c2
    );
  Mcount_new_cnt_c_xor_3_11 : LUT5
    generic map(
      INIT => X"28888888"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => new_cnt_c(3),
      I2 => new_cnt_c(2),
      I3 => new_cnt_c(0),
      I4 => new_cnt_c(1),
      O => Mcount_new_cnt_c3
    );
  new_cnt_c_not00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => new_cnt_5335,
      I1 => new_cnt_z2_5345,
      O => new_cnt_c_not0001
    );
  cnt_value_adc0_and00001 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => new_cnt_z_5343,
      I1 => reset,
      O => cnt_value_adc0_and0000
    );
  cnt_value_adc_not00011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => new_cnt_z_5343,
      O => cnt_value_adc_not0001
    );
  Mcount_cnt_value_adc_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(1),
      O => Mcount_cnt_value_adc_cy_1_rt_5188
    );
  Mcount_cnt_value_adc_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(2),
      O => Mcount_cnt_value_adc_cy_2_rt_5190
    );
  Mcount_cnt_value_adc_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(3),
      O => Mcount_cnt_value_adc_cy_3_rt_5192
    );
  Mcount_cnt_value_adc_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(4),
      O => Mcount_cnt_value_adc_cy_4_rt_5194
    );
  Mcount_cnt_value_adc_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(5),
      O => Mcount_cnt_value_adc_cy_5_rt_5196
    );
  Mcount_cnt_value_adc_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(6),
      O => Mcount_cnt_value_adc_cy_6_rt_5198
    );
  Mcount_cnt_value_adc_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(7),
      O => Mcount_cnt_value_adc_cy_7_rt_5200
    );
  Mcount_cnt_value_adc_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(8),
      O => Mcount_cnt_value_adc_cy_8_rt_5202
    );
  Mcount_cnt_value_adc_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(9),
      O => Mcount_cnt_value_adc_cy_9_rt_5204
    );
  Mcount_cnt_value_adc_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(10),
      O => Mcount_cnt_value_adc_cy_10_rt_5178
    );
  Mcount_cnt_value_adc_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(11),
      O => Mcount_cnt_value_adc_cy_11_rt_5180
    );
  Mcount_cnt_value_adc_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(12),
      O => Mcount_cnt_value_adc_cy_12_rt_5182
    );
  Mcount_cnt_value_adc_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(13),
      O => Mcount_cnt_value_adc_cy_13_rt_5184
    );
  Mcount_cnt_value_adc_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(14),
      O => Mcount_cnt_value_adc_cy_14_rt_5186
    );
  Madd_freq_adc_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(12),
      O => Madd_freq_adc_add0000_cy_1_rt_5145
    );
  Madd_freq_adc_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(13),
      O => Madd_freq_adc_add0000_cy_2_rt_5147
    );
  Madd_freq_adc_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(14),
      O => Madd_freq_adc_add0000_cy_3_rt_5149
    );
  Madd_freq_adc_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(15),
      O => Madd_freq_adc_add0000_cy_4_rt_5151
    );
  Madd_freq_adc_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(16),
      O => Madd_freq_adc_add0000_cy_5_rt_5153
    );
  Madd_freq_adc_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(17),
      O => Madd_freq_adc_add0000_cy_6_rt_5155
    );
  Madd_freq_adc_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(18),
      O => Madd_freq_adc_add0000_cy_7_rt_5157
    );
  Madd_freq_adc_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(19),
      O => Madd_freq_adc_add0000_cy_8_rt_5159
    );
  Madd_freq_adc_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(20),
      O => Madd_freq_adc_add0000_cy_9_rt_5161
    );
  Madd_freq_adc_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(21),
      O => Madd_freq_adc_add0000_cy_10_rt_5135
    );
  Madd_freq_adc_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(22),
      O => Madd_freq_adc_add0000_cy_11_rt_5137
    );
  Madd_freq_adc_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(23),
      O => Madd_freq_adc_add0000_cy_12_rt_5139
    );
  Madd_freq_adc_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(24),
      O => Madd_freq_adc_add0000_cy_13_rt_5141
    );
  Madd_freq_adc_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(25),
      O => Madd_freq_adc_add0000_cy_14_rt_5143
    );
  Mcount_cnt_value_adc_xor_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt_value_adc(15),
      O => Mcount_cnt_value_adc_xor_15_rt_5206
    );
  Mcount_cnt_value_adc_lut_0_INV_0 : INV
    port map (
      I => cnt_value_adc(0),
      O => Mcount_cnt_value_adc_lut(0)
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );
  new_cnt_inv1_INV_0 : INV
    port map (
      I => new_cnt_5335,
      O => new_cnt_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_freq_INST_1 is
  port (
    clk_in : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    freq_en : out STD_LOGIC; 
    clk_sys : in STD_LOGIC := 'X'; 
    freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end ctrl_freq_INST_1;

architecture STRUCTURE of ctrl_freq_INST_1 is
  component ctrl_multiplier_v1_0
    port (
      clk : in STD_LOGIC := 'X'; 
      p : out STD_LOGIC_VECTOR ( 26 downto 0 ); 
      a : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 
    );
  end component;
  signal Madd_freq_adc_add0000_cy_10_rt_4988 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_11_rt_4990 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_12_rt_4992 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_13_rt_4994 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_14_rt_4996 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_1_rt_4998 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_2_rt_5000 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_3_rt_5002 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_4_rt_5004 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_5_rt_5006 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_6_rt_5008 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_7_rt_5010 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_8_rt_5012 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_9_rt_5014 : STD_LOGIC; 
  signal Mcount_cnt_value : STD_LOGIC; 
  signal Mcount_cnt_value1 : STD_LOGIC; 
  signal Mcount_cnt_value10 : STD_LOGIC; 
  signal Mcount_cnt_value11 : STD_LOGIC; 
  signal Mcount_cnt_value12 : STD_LOGIC; 
  signal Mcount_cnt_value2 : STD_LOGIC; 
  signal Mcount_cnt_value3 : STD_LOGIC; 
  signal Mcount_cnt_value4 : STD_LOGIC; 
  signal Mcount_cnt_value5 : STD_LOGIC; 
  signal Mcount_cnt_value6 : STD_LOGIC; 
  signal Mcount_cnt_value7 : STD_LOGIC; 
  signal Mcount_cnt_value8 : STD_LOGIC; 
  signal Mcount_cnt_value9 : STD_LOGIC; 
  signal Mcount_new_cnt_c : STD_LOGIC; 
  signal Mcount_new_cnt_c1 : STD_LOGIC; 
  signal Mcount_new_cnt_c2 : STD_LOGIC; 
  signal Mcount_new_cnt_c3 : STD_LOGIC; 
  signal new_cnt_5106 : STD_LOGIC; 
  signal new_cnt_c_not0001 : STD_LOGIC; 
  signal new_cnt_inv : STD_LOGIC; 
  signal new_cnt_mux0001 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NLW_x_mult_p_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_0_UNCONNECTED : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Madd_freq_adc_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_adc_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_adc_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_cy : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Mcount_cnt_value_lut : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal cnt_value : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal freq_adc_add0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal new_cnt_c : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal result_freq : STD_LOGIC_VECTOR ( 26 downto 10 ); 
begin
  XST_GND : GND
    port map (
      G => Mcount_cnt_value_adc_cy(0)
    );
  XST_VCC : VCC
    port map (
      P => Mcount_cnt_value_adc_lut(0)
    );
  new_cnt : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => new_cnt_mux0001,
      Q => new_cnt_5106
    );
  freq_adc_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(0),
      Q => freq_adc(0)
    );
  freq_adc_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(1),
      Q => freq_adc(1)
    );
  freq_adc_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(2),
      Q => freq_adc(2)
    );
  freq_adc_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(3),
      Q => freq_adc(3)
    );
  freq_adc_4 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(4),
      Q => freq_adc(4)
    );
  freq_adc_5 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(5),
      Q => freq_adc(5)
    );
  freq_adc_6 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(6),
      Q => freq_adc(6)
    );
  freq_adc_7 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(7),
      Q => freq_adc(7)
    );
  freq_adc_8 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(8),
      Q => freq_adc(8)
    );
  freq_adc_9 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(9),
      Q => freq_adc(9)
    );
  freq_adc_10 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(10),
      Q => freq_adc(10)
    );
  freq_adc_11 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(11),
      Q => freq_adc(11)
    );
  freq_adc_12 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(12),
      Q => freq_adc(12)
    );
  freq_adc_13 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(13),
      Q => freq_adc(13)
    );
  freq_adc_14 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(14),
      Q => freq_adc(14)
    );
  freq_adc_15 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(15),
      Q => freq_adc(15)
    );
  Mcount_cnt_value_lut_0_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(0),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(0)
    );
  Mcount_cnt_value_cy_0_Q : MUXCY
    port map (
      CI => new_cnt_inv,
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value_cy(0)
    );
  Mcount_cnt_value_xor_0_Q : XORCY
    port map (
      CI => new_cnt_inv,
      LI => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value
    );
  Mcount_cnt_value_lut_1_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(1),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(1)
    );
  Mcount_cnt_value_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value_cy(1)
    );
  Mcount_cnt_value_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      LI => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value1
    );
  Mcount_cnt_value_lut_2_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(2),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(2)
    );
  Mcount_cnt_value_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value_cy(2)
    );
  Mcount_cnt_value_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      LI => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value2
    );
  Mcount_cnt_value_lut_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(3),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(3)
    );
  Mcount_cnt_value_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value_cy(3)
    );
  Mcount_cnt_value_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      LI => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value3
    );
  Mcount_cnt_value_lut_4_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(4),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(4)
    );
  Mcount_cnt_value_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value_cy(4)
    );
  Mcount_cnt_value_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      LI => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value4
    );
  Mcount_cnt_value_lut_5_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(5),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(5)
    );
  Mcount_cnt_value_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value_cy(5)
    );
  Mcount_cnt_value_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      LI => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value5
    );
  Mcount_cnt_value_lut_6_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(6),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(6)
    );
  Mcount_cnt_value_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value_cy(6)
    );
  Mcount_cnt_value_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      LI => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value6
    );
  Mcount_cnt_value_lut_7_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(7),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(7)
    );
  Mcount_cnt_value_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value_cy(7)
    );
  Mcount_cnt_value_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      LI => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value7
    );
  Mcount_cnt_value_lut_8_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(8),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(8)
    );
  Mcount_cnt_value_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value_cy(8)
    );
  Mcount_cnt_value_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      LI => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value8
    );
  Mcount_cnt_value_lut_9_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(9),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(9)
    );
  Mcount_cnt_value_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value_cy(9)
    );
  Mcount_cnt_value_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      LI => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value9
    );
  Mcount_cnt_value_lut_10_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(10),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(10)
    );
  Mcount_cnt_value_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value_cy(10)
    );
  Mcount_cnt_value_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      LI => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value10
    );
  Mcount_cnt_value_lut_11_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(11),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(11)
    );
  Mcount_cnt_value_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value_cy(11)
    );
  Mcount_cnt_value_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      LI => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value11
    );
  Mcount_cnt_value_lut_12_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(12),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(12)
    );
  Mcount_cnt_value_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(11),
      LI => Mcount_cnt_value_lut(12),
      O => Mcount_cnt_value12
    );
  cnt_value_0 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value,
      Q => cnt_value(0)
    );
  cnt_value_1 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value1,
      Q => cnt_value(1)
    );
  cnt_value_2 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value2,
      Q => cnt_value(2)
    );
  cnt_value_3 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value3,
      Q => cnt_value(3)
    );
  cnt_value_4 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value4,
      Q => cnt_value(4)
    );
  cnt_value_5 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value5,
      Q => cnt_value(5)
    );
  cnt_value_6 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value6,
      Q => cnt_value(6)
    );
  cnt_value_7 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value7,
      Q => cnt_value(7)
    );
  cnt_value_8 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value8,
      Q => cnt_value(8)
    );
  cnt_value_9 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value9,
      Q => cnt_value(9)
    );
  cnt_value_10 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value10,
      Q => cnt_value(10)
    );
  cnt_value_11 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value11,
      Q => cnt_value(11)
    );
  cnt_value_12 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value12,
      Q => cnt_value(12)
    );
  new_cnt_c_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c,
      Q => new_cnt_c(0)
    );
  new_cnt_c_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c1,
      Q => new_cnt_c(1)
    );
  new_cnt_c_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c2,
      Q => new_cnt_c(2)
    );
  new_cnt_c_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c3,
      Q => new_cnt_c(3)
    );
  Madd_freq_adc_add0000_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => result_freq(11),
      I1 => result_freq(10),
      O => Madd_freq_adc_add0000_lut(0)
    );
  Madd_freq_adc_add0000_cy_0_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      DI => result_freq(11),
      S => Madd_freq_adc_add0000_lut(0),
      O => Madd_freq_adc_add0000_cy(0)
    );
  Madd_freq_adc_add0000_xor_0_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      LI => Madd_freq_adc_add0000_lut(0),
      O => freq_adc_add0000(0)
    );
  Madd_freq_adc_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_1_rt_4998,
      O => Madd_freq_adc_add0000_cy(1)
    );
  Madd_freq_adc_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      LI => Madd_freq_adc_add0000_cy_1_rt_4998,
      O => freq_adc_add0000(1)
    );
  Madd_freq_adc_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_2_rt_5000,
      O => Madd_freq_adc_add0000_cy(2)
    );
  Madd_freq_adc_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      LI => Madd_freq_adc_add0000_cy_2_rt_5000,
      O => freq_adc_add0000(2)
    );
  Madd_freq_adc_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_3_rt_5002,
      O => Madd_freq_adc_add0000_cy(3)
    );
  Madd_freq_adc_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      LI => Madd_freq_adc_add0000_cy_3_rt_5002,
      O => freq_adc_add0000(3)
    );
  Madd_freq_adc_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_4_rt_5004,
      O => Madd_freq_adc_add0000_cy(4)
    );
  Madd_freq_adc_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      LI => Madd_freq_adc_add0000_cy_4_rt_5004,
      O => freq_adc_add0000(4)
    );
  Madd_freq_adc_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_5_rt_5006,
      O => Madd_freq_adc_add0000_cy(5)
    );
  Madd_freq_adc_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      LI => Madd_freq_adc_add0000_cy_5_rt_5006,
      O => freq_adc_add0000(5)
    );
  Madd_freq_adc_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_6_rt_5008,
      O => Madd_freq_adc_add0000_cy(6)
    );
  Madd_freq_adc_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      LI => Madd_freq_adc_add0000_cy_6_rt_5008,
      O => freq_adc_add0000(6)
    );
  Madd_freq_adc_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_7_rt_5010,
      O => Madd_freq_adc_add0000_cy(7)
    );
  Madd_freq_adc_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      LI => Madd_freq_adc_add0000_cy_7_rt_5010,
      O => freq_adc_add0000(7)
    );
  Madd_freq_adc_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_8_rt_5012,
      O => Madd_freq_adc_add0000_cy(8)
    );
  Madd_freq_adc_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      LI => Madd_freq_adc_add0000_cy_8_rt_5012,
      O => freq_adc_add0000(8)
    );
  Madd_freq_adc_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_9_rt_5014,
      O => Madd_freq_adc_add0000_cy(9)
    );
  Madd_freq_adc_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      LI => Madd_freq_adc_add0000_cy_9_rt_5014,
      O => freq_adc_add0000(9)
    );
  Madd_freq_adc_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_10_rt_4988,
      O => Madd_freq_adc_add0000_cy(10)
    );
  Madd_freq_adc_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      LI => Madd_freq_adc_add0000_cy_10_rt_4988,
      O => freq_adc_add0000(10)
    );
  Madd_freq_adc_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_11_rt_4990,
      O => Madd_freq_adc_add0000_cy(11)
    );
  Madd_freq_adc_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      LI => Madd_freq_adc_add0000_cy_11_rt_4990,
      O => freq_adc_add0000(11)
    );
  Madd_freq_adc_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_12_rt_4992,
      O => Madd_freq_adc_add0000_cy(12)
    );
  Madd_freq_adc_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      LI => Madd_freq_adc_add0000_cy_12_rt_4992,
      O => freq_adc_add0000(12)
    );
  Madd_freq_adc_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_13_rt_4994,
      O => Madd_freq_adc_add0000_cy(13)
    );
  Madd_freq_adc_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      LI => Madd_freq_adc_add0000_cy_13_rt_4994,
      O => freq_adc_add0000(13)
    );
  Madd_freq_adc_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_14_rt_4996,
      O => Madd_freq_adc_add0000_cy(14)
    );
  Madd_freq_adc_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      LI => Madd_freq_adc_add0000_cy_14_rt_4996,
      O => freq_adc_add0000(14)
    );
  Madd_freq_adc_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(14),
      LI => result_freq(26),
      O => freq_adc_add0000(15)
    );
  x_mult : ctrl_multiplier_v1_0
    port map (
      clk => clk_sys,
      p(26) => result_freq(26),
      p(25) => result_freq(25),
      p(24) => result_freq(24),
      p(23) => result_freq(23),
      p(22) => result_freq(22),
      p(21) => result_freq(21),
      p(20) => result_freq(20),
      p(19) => result_freq(19),
      p(18) => result_freq(18),
      p(17) => result_freq(17),
      p(16) => result_freq(16),
      p(15) => result_freq(15),
      p(14) => result_freq(14),
      p(13) => result_freq(13),
      p(12) => result_freq(12),
      p(11) => result_freq(11),
      p(10) => result_freq(10),
      p(9) => NLW_x_mult_p_9_UNCONNECTED,
      p(8) => NLW_x_mult_p_8_UNCONNECTED,
      p(7) => NLW_x_mult_p_7_UNCONNECTED,
      p(6) => NLW_x_mult_p_6_UNCONNECTED,
      p(5) => NLW_x_mult_p_5_UNCONNECTED,
      p(4) => NLW_x_mult_p_4_UNCONNECTED,
      p(3) => NLW_x_mult_p_3_UNCONNECTED,
      p(2) => NLW_x_mult_p_2_UNCONNECTED,
      p(1) => NLW_x_mult_p_1_UNCONNECTED,
      p(0) => NLW_x_mult_p_0_UNCONNECTED,
      a(15) => Mcount_cnt_value_adc_cy(0),
      a(14) => Mcount_cnt_value_adc_cy(0),
      a(13) => Mcount_cnt_value_adc_cy(0),
      a(12) => Mcount_cnt_value_adc_cy(0),
      a(11) => Mcount_cnt_value_adc_cy(0),
      a(10) => Mcount_cnt_value_adc_cy(0),
      a(9) => Mcount_cnt_value_adc_cy(0),
      a(8) => Mcount_cnt_value_adc_cy(0),
      a(7) => Mcount_cnt_value_adc_cy(0),
      a(6) => Mcount_cnt_value_adc_cy(0),
      a(5) => Mcount_cnt_value_adc_cy(0),
      a(4) => Mcount_cnt_value_adc_cy(0),
      a(3) => Mcount_cnt_value_adc_cy(0),
      a(2) => Mcount_cnt_value_adc_cy(0),
      a(1) => Mcount_cnt_value_adc_cy(0),
      a(0) => Mcount_cnt_value_adc_cy(0),
      b(10) => Mcount_cnt_value_adc_cy(0),
      b(9) => Mcount_cnt_value_adc_lut(0),
      b(8) => Mcount_cnt_value_adc_lut(0),
      b(7) => Mcount_cnt_value_adc_lut(0),
      b(6) => Mcount_cnt_value_adc_lut(0),
      b(5) => Mcount_cnt_value_adc_lut(0),
      b(4) => Mcount_cnt_value_adc_cy(0),
      b(3) => Mcount_cnt_value_adc_lut(0),
      b(2) => Mcount_cnt_value_adc_cy(0),
      b(1) => Mcount_cnt_value_adc_cy(0),
      b(0) => Mcount_cnt_value_adc_cy(0)
    );
  Mcount_new_cnt_c_xor_0_11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => new_cnt_c(0),
      I1 => new_cnt_5106,
      O => Mcount_new_cnt_c
    );
  new_cnt_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => cnt_value(12),
      I2 => new_cnt_c(3),
      O => new_cnt_mux0001
    );
  Mcount_new_cnt_c_xor_1_11 : LUT3
    generic map(
      INIT => X"28"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => new_cnt_c(0),
      I2 => new_cnt_c(1),
      O => Mcount_new_cnt_c1
    );
  Mcount_new_cnt_c_xor_2_11 : LUT4
    generic map(
      INIT => X"2888"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => new_cnt_c(2),
      I2 => new_cnt_c(0),
      I3 => new_cnt_c(1),
      O => Mcount_new_cnt_c2
    );
  Mcount_new_cnt_c_xor_3_11 : LUT5
    generic map(
      INIT => X"28888888"
    )
    port map (
      I0 => new_cnt_5106,
      I1 => new_cnt_c(3),
      I2 => new_cnt_c(2),
      I3 => new_cnt_c(0),
      I4 => new_cnt_c(1),
      O => Mcount_new_cnt_c3
    );
  Madd_freq_adc_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(12),
      O => Madd_freq_adc_add0000_cy_1_rt_4998
    );
  Madd_freq_adc_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(13),
      O => Madd_freq_adc_add0000_cy_2_rt_5000
    );
  Madd_freq_adc_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(14),
      O => Madd_freq_adc_add0000_cy_3_rt_5002
    );
  Madd_freq_adc_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(15),
      O => Madd_freq_adc_add0000_cy_4_rt_5004
    );
  Madd_freq_adc_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(16),
      O => Madd_freq_adc_add0000_cy_5_rt_5006
    );
  Madd_freq_adc_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(17),
      O => Madd_freq_adc_add0000_cy_6_rt_5008
    );
  Madd_freq_adc_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(18),
      O => Madd_freq_adc_add0000_cy_7_rt_5010
    );
  Madd_freq_adc_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(19),
      O => Madd_freq_adc_add0000_cy_8_rt_5012
    );
  Madd_freq_adc_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(20),
      O => Madd_freq_adc_add0000_cy_9_rt_5014
    );
  Madd_freq_adc_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(21),
      O => Madd_freq_adc_add0000_cy_10_rt_4988
    );
  Madd_freq_adc_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(22),
      O => Madd_freq_adc_add0000_cy_11_rt_4990
    );
  Madd_freq_adc_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(23),
      O => Madd_freq_adc_add0000_cy_12_rt_4992
    );
  Madd_freq_adc_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(24),
      O => Madd_freq_adc_add0000_cy_13_rt_4994
    );
  Madd_freq_adc_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(25),
      O => Madd_freq_adc_add0000_cy_14_rt_4996
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );
  new_cnt_inv1_INV_0 : INV
    port map (
      I => new_cnt_5106,
      O => new_cnt_inv
    );
  new_cnt_c_not000111_INV_0 : INV
    port map (
      I => new_cnt_5106,
      O => new_cnt_c_not0001
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_freq is
  port (
    clk_in : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    freq_en : out STD_LOGIC; 
    clk_sys : in STD_LOGIC := 'X'; 
    freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end ctrl_freq;

architecture STRUCTURE of ctrl_freq is
  component ctrl_multiplier_v1_0
    port (
      clk : in STD_LOGIC := 'X'; 
      p : out STD_LOGIC_VECTOR ( 26 downto 0 ); 
      a : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 
    );
  end component;
  signal Madd_freq_adc_add0000_cy_10_rt_4841 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_11_rt_4843 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_12_rt_4845 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_13_rt_4847 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_14_rt_4849 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_1_rt_4851 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_2_rt_4853 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_3_rt_4855 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_4_rt_4857 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_5_rt_4859 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_6_rt_4861 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_7_rt_4863 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_8_rt_4865 : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy_9_rt_4867 : STD_LOGIC; 
  signal Mcount_cnt_value : STD_LOGIC; 
  signal Mcount_cnt_value1 : STD_LOGIC; 
  signal Mcount_cnt_value10 : STD_LOGIC; 
  signal Mcount_cnt_value11 : STD_LOGIC; 
  signal Mcount_cnt_value12 : STD_LOGIC; 
  signal Mcount_cnt_value2 : STD_LOGIC; 
  signal Mcount_cnt_value3 : STD_LOGIC; 
  signal Mcount_cnt_value4 : STD_LOGIC; 
  signal Mcount_cnt_value5 : STD_LOGIC; 
  signal Mcount_cnt_value6 : STD_LOGIC; 
  signal Mcount_cnt_value7 : STD_LOGIC; 
  signal Mcount_cnt_value8 : STD_LOGIC; 
  signal Mcount_cnt_value9 : STD_LOGIC; 
  signal Mcount_new_cnt_c : STD_LOGIC; 
  signal Mcount_new_cnt_c1 : STD_LOGIC; 
  signal Mcount_new_cnt_c2 : STD_LOGIC; 
  signal Mcount_new_cnt_c3 : STD_LOGIC; 
  signal new_cnt_4959 : STD_LOGIC; 
  signal new_cnt_c_not0001 : STD_LOGIC; 
  signal new_cnt_inv : STD_LOGIC; 
  signal new_cnt_mux0001 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NLW_x_mult_p_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_x_mult_p_0_UNCONNECTED : STD_LOGIC; 
  signal Madd_freq_adc_add0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Madd_freq_adc_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_adc_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_adc_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt_value_cy : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal Mcount_cnt_value_lut : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal cnt_value : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal freq_adc_add0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal new_cnt_c : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal result_freq : STD_LOGIC_VECTOR ( 26 downto 10 ); 
begin
  XST_GND : GND
    port map (
      G => Mcount_cnt_value_adc_cy(0)
    );
  XST_VCC : VCC
    port map (
      P => Mcount_cnt_value_adc_lut(0)
    );
  new_cnt : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => new_cnt_mux0001,
      Q => new_cnt_4959
    );
  freq_adc_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(0),
      Q => freq_adc(0)
    );
  freq_adc_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(1),
      Q => freq_adc(1)
    );
  freq_adc_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(2),
      Q => freq_adc(2)
    );
  freq_adc_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(3),
      Q => freq_adc(3)
    );
  freq_adc_4 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(4),
      Q => freq_adc(4)
    );
  freq_adc_5 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(5),
      Q => freq_adc(5)
    );
  freq_adc_6 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(6),
      Q => freq_adc(6)
    );
  freq_adc_7 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(7),
      Q => freq_adc(7)
    );
  freq_adc_8 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(8),
      Q => freq_adc(8)
    );
  freq_adc_9 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(9),
      Q => freq_adc(9)
    );
  freq_adc_10 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(10),
      Q => freq_adc(10)
    );
  freq_adc_11 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(11),
      Q => freq_adc(11)
    );
  freq_adc_12 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(12),
      Q => freq_adc(12)
    );
  freq_adc_13 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(13),
      Q => freq_adc(13)
    );
  freq_adc_14 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(14),
      Q => freq_adc(14)
    );
  freq_adc_15 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c(2),
      CLR => reset_inv,
      D => freq_adc_add0000(15),
      Q => freq_adc(15)
    );
  Mcount_cnt_value_lut_0_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(0),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(0)
    );
  Mcount_cnt_value_cy_0_Q : MUXCY
    port map (
      CI => new_cnt_inv,
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value_cy(0)
    );
  Mcount_cnt_value_xor_0_Q : XORCY
    port map (
      CI => new_cnt_inv,
      LI => Mcount_cnt_value_lut(0),
      O => Mcount_cnt_value
    );
  Mcount_cnt_value_lut_1_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(1),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(1)
    );
  Mcount_cnt_value_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value_cy(1)
    );
  Mcount_cnt_value_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(0),
      LI => Mcount_cnt_value_lut(1),
      O => Mcount_cnt_value1
    );
  Mcount_cnt_value_lut_2_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(2),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(2)
    );
  Mcount_cnt_value_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value_cy(2)
    );
  Mcount_cnt_value_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(1),
      LI => Mcount_cnt_value_lut(2),
      O => Mcount_cnt_value2
    );
  Mcount_cnt_value_lut_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(3),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(3)
    );
  Mcount_cnt_value_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value_cy(3)
    );
  Mcount_cnt_value_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(2),
      LI => Mcount_cnt_value_lut(3),
      O => Mcount_cnt_value3
    );
  Mcount_cnt_value_lut_4_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(4),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(4)
    );
  Mcount_cnt_value_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value_cy(4)
    );
  Mcount_cnt_value_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(3),
      LI => Mcount_cnt_value_lut(4),
      O => Mcount_cnt_value4
    );
  Mcount_cnt_value_lut_5_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(5),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(5)
    );
  Mcount_cnt_value_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value_cy(5)
    );
  Mcount_cnt_value_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(4),
      LI => Mcount_cnt_value_lut(5),
      O => Mcount_cnt_value5
    );
  Mcount_cnt_value_lut_6_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(6),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(6)
    );
  Mcount_cnt_value_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value_cy(6)
    );
  Mcount_cnt_value_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(5),
      LI => Mcount_cnt_value_lut(6),
      O => Mcount_cnt_value6
    );
  Mcount_cnt_value_lut_7_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(7),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(7)
    );
  Mcount_cnt_value_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value_cy(7)
    );
  Mcount_cnt_value_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(6),
      LI => Mcount_cnt_value_lut(7),
      O => Mcount_cnt_value7
    );
  Mcount_cnt_value_lut_8_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(8),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(8)
    );
  Mcount_cnt_value_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value_cy(8)
    );
  Mcount_cnt_value_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(7),
      LI => Mcount_cnt_value_lut(8),
      O => Mcount_cnt_value8
    );
  Mcount_cnt_value_lut_9_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(9),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(9)
    );
  Mcount_cnt_value_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value_cy(9)
    );
  Mcount_cnt_value_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(8),
      LI => Mcount_cnt_value_lut(9),
      O => Mcount_cnt_value9
    );
  Mcount_cnt_value_lut_10_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(10),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(10)
    );
  Mcount_cnt_value_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value_cy(10)
    );
  Mcount_cnt_value_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(9),
      LI => Mcount_cnt_value_lut(10),
      O => Mcount_cnt_value10
    );
  Mcount_cnt_value_lut_11_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(11),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(11)
    );
  Mcount_cnt_value_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value_cy(11)
    );
  Mcount_cnt_value_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(10),
      LI => Mcount_cnt_value_lut(11),
      O => Mcount_cnt_value11
    );
  Mcount_cnt_value_lut_12_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(12),
      I2 => Mcount_cnt_value_adc_cy(0),
      O => Mcount_cnt_value_lut(12)
    );
  Mcount_cnt_value_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt_value_cy(11),
      LI => Mcount_cnt_value_lut(12),
      O => Mcount_cnt_value12
    );
  cnt_value_0 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value,
      Q => cnt_value(0)
    );
  cnt_value_1 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value1,
      Q => cnt_value(1)
    );
  cnt_value_2 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value2,
      Q => cnt_value(2)
    );
  cnt_value_3 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value3,
      Q => cnt_value(3)
    );
  cnt_value_4 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value4,
      Q => cnt_value(4)
    );
  cnt_value_5 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value5,
      Q => cnt_value(5)
    );
  cnt_value_6 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value6,
      Q => cnt_value(6)
    );
  cnt_value_7 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value7,
      Q => cnt_value(7)
    );
  cnt_value_8 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value8,
      Q => cnt_value(8)
    );
  cnt_value_9 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value9,
      Q => cnt_value(9)
    );
  cnt_value_10 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value10,
      Q => cnt_value(10)
    );
  cnt_value_11 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value11,
      Q => cnt_value(11)
    );
  cnt_value_12 : FDC
    port map (
      C => clk_sys,
      CLR => reset_inv,
      D => Mcount_cnt_value12,
      Q => cnt_value(12)
    );
  new_cnt_c_0 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c,
      Q => new_cnt_c(0)
    );
  new_cnt_c_1 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c1,
      Q => new_cnt_c(1)
    );
  new_cnt_c_2 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c2,
      Q => new_cnt_c(2)
    );
  new_cnt_c_3 : FDCE
    port map (
      C => clk_sys,
      CE => new_cnt_c_not0001,
      CLR => reset_inv,
      D => Mcount_new_cnt_c3,
      Q => new_cnt_c(3)
    );
  Madd_freq_adc_add0000_lut_0_Q : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => result_freq(11),
      I1 => result_freq(10),
      O => Madd_freq_adc_add0000_lut(0)
    );
  Madd_freq_adc_add0000_cy_0_Q : MUXCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      DI => result_freq(11),
      S => Madd_freq_adc_add0000_lut(0),
      O => Madd_freq_adc_add0000_cy(0)
    );
  Madd_freq_adc_add0000_xor_0_Q : XORCY
    port map (
      CI => Mcount_cnt_value_adc_cy(0),
      LI => Madd_freq_adc_add0000_lut(0),
      O => freq_adc_add0000(0)
    );
  Madd_freq_adc_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_1_rt_4851,
      O => Madd_freq_adc_add0000_cy(1)
    );
  Madd_freq_adc_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(0),
      LI => Madd_freq_adc_add0000_cy_1_rt_4851,
      O => freq_adc_add0000(1)
    );
  Madd_freq_adc_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_2_rt_4853,
      O => Madd_freq_adc_add0000_cy(2)
    );
  Madd_freq_adc_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(1),
      LI => Madd_freq_adc_add0000_cy_2_rt_4853,
      O => freq_adc_add0000(2)
    );
  Madd_freq_adc_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_3_rt_4855,
      O => Madd_freq_adc_add0000_cy(3)
    );
  Madd_freq_adc_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(2),
      LI => Madd_freq_adc_add0000_cy_3_rt_4855,
      O => freq_adc_add0000(3)
    );
  Madd_freq_adc_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_4_rt_4857,
      O => Madd_freq_adc_add0000_cy(4)
    );
  Madd_freq_adc_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(3),
      LI => Madd_freq_adc_add0000_cy_4_rt_4857,
      O => freq_adc_add0000(4)
    );
  Madd_freq_adc_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_5_rt_4859,
      O => Madd_freq_adc_add0000_cy(5)
    );
  Madd_freq_adc_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(4),
      LI => Madd_freq_adc_add0000_cy_5_rt_4859,
      O => freq_adc_add0000(5)
    );
  Madd_freq_adc_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_6_rt_4861,
      O => Madd_freq_adc_add0000_cy(6)
    );
  Madd_freq_adc_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(5),
      LI => Madd_freq_adc_add0000_cy_6_rt_4861,
      O => freq_adc_add0000(6)
    );
  Madd_freq_adc_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_7_rt_4863,
      O => Madd_freq_adc_add0000_cy(7)
    );
  Madd_freq_adc_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(6),
      LI => Madd_freq_adc_add0000_cy_7_rt_4863,
      O => freq_adc_add0000(7)
    );
  Madd_freq_adc_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_8_rt_4865,
      O => Madd_freq_adc_add0000_cy(8)
    );
  Madd_freq_adc_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(7),
      LI => Madd_freq_adc_add0000_cy_8_rt_4865,
      O => freq_adc_add0000(8)
    );
  Madd_freq_adc_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_9_rt_4867,
      O => Madd_freq_adc_add0000_cy(9)
    );
  Madd_freq_adc_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(8),
      LI => Madd_freq_adc_add0000_cy_9_rt_4867,
      O => freq_adc_add0000(9)
    );
  Madd_freq_adc_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_10_rt_4841,
      O => Madd_freq_adc_add0000_cy(10)
    );
  Madd_freq_adc_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(9),
      LI => Madd_freq_adc_add0000_cy_10_rt_4841,
      O => freq_adc_add0000(10)
    );
  Madd_freq_adc_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_11_rt_4843,
      O => Madd_freq_adc_add0000_cy(11)
    );
  Madd_freq_adc_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(10),
      LI => Madd_freq_adc_add0000_cy_11_rt_4843,
      O => freq_adc_add0000(11)
    );
  Madd_freq_adc_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_12_rt_4845,
      O => Madd_freq_adc_add0000_cy(12)
    );
  Madd_freq_adc_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(11),
      LI => Madd_freq_adc_add0000_cy_12_rt_4845,
      O => freq_adc_add0000(12)
    );
  Madd_freq_adc_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_13_rt_4847,
      O => Madd_freq_adc_add0000_cy(13)
    );
  Madd_freq_adc_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(12),
      LI => Madd_freq_adc_add0000_cy_13_rt_4847,
      O => freq_adc_add0000(13)
    );
  Madd_freq_adc_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      DI => Mcount_cnt_value_adc_cy(0),
      S => Madd_freq_adc_add0000_cy_14_rt_4849,
      O => Madd_freq_adc_add0000_cy(14)
    );
  Madd_freq_adc_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(13),
      LI => Madd_freq_adc_add0000_cy_14_rt_4849,
      O => freq_adc_add0000(14)
    );
  Madd_freq_adc_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_freq_adc_add0000_cy(14),
      LI => result_freq(26),
      O => freq_adc_add0000(15)
    );
  x_mult : ctrl_multiplier_v1_0
    port map (
      clk => clk_sys,
      p(26) => result_freq(26),
      p(25) => result_freq(25),
      p(24) => result_freq(24),
      p(23) => result_freq(23),
      p(22) => result_freq(22),
      p(21) => result_freq(21),
      p(20) => result_freq(20),
      p(19) => result_freq(19),
      p(18) => result_freq(18),
      p(17) => result_freq(17),
      p(16) => result_freq(16),
      p(15) => result_freq(15),
      p(14) => result_freq(14),
      p(13) => result_freq(13),
      p(12) => result_freq(12),
      p(11) => result_freq(11),
      p(10) => result_freq(10),
      p(9) => NLW_x_mult_p_9_UNCONNECTED,
      p(8) => NLW_x_mult_p_8_UNCONNECTED,
      p(7) => NLW_x_mult_p_7_UNCONNECTED,
      p(6) => NLW_x_mult_p_6_UNCONNECTED,
      p(5) => NLW_x_mult_p_5_UNCONNECTED,
      p(4) => NLW_x_mult_p_4_UNCONNECTED,
      p(3) => NLW_x_mult_p_3_UNCONNECTED,
      p(2) => NLW_x_mult_p_2_UNCONNECTED,
      p(1) => NLW_x_mult_p_1_UNCONNECTED,
      p(0) => NLW_x_mult_p_0_UNCONNECTED,
      a(15) => Mcount_cnt_value_adc_cy(0),
      a(14) => Mcount_cnt_value_adc_cy(0),
      a(13) => Mcount_cnt_value_adc_cy(0),
      a(12) => Mcount_cnt_value_adc_cy(0),
      a(11) => Mcount_cnt_value_adc_cy(0),
      a(10) => Mcount_cnt_value_adc_cy(0),
      a(9) => Mcount_cnt_value_adc_cy(0),
      a(8) => Mcount_cnt_value_adc_cy(0),
      a(7) => Mcount_cnt_value_adc_cy(0),
      a(6) => Mcount_cnt_value_adc_cy(0),
      a(5) => Mcount_cnt_value_adc_cy(0),
      a(4) => Mcount_cnt_value_adc_cy(0),
      a(3) => Mcount_cnt_value_adc_cy(0),
      a(2) => Mcount_cnt_value_adc_cy(0),
      a(1) => Mcount_cnt_value_adc_cy(0),
      a(0) => Mcount_cnt_value_adc_cy(0),
      b(10) => Mcount_cnt_value_adc_cy(0),
      b(9) => Mcount_cnt_value_adc_lut(0),
      b(8) => Mcount_cnt_value_adc_lut(0),
      b(7) => Mcount_cnt_value_adc_lut(0),
      b(6) => Mcount_cnt_value_adc_lut(0),
      b(5) => Mcount_cnt_value_adc_lut(0),
      b(4) => Mcount_cnt_value_adc_cy(0),
      b(3) => Mcount_cnt_value_adc_lut(0),
      b(2) => Mcount_cnt_value_adc_cy(0),
      b(1) => Mcount_cnt_value_adc_cy(0),
      b(0) => Mcount_cnt_value_adc_cy(0)
    );
  Mcount_new_cnt_c_xor_0_11 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => new_cnt_c(0),
      I1 => new_cnt_4959,
      O => Mcount_new_cnt_c
    );
  new_cnt_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => cnt_value(12),
      I2 => new_cnt_c(3),
      O => new_cnt_mux0001
    );
  Mcount_new_cnt_c_xor_1_11 : LUT3
    generic map(
      INIT => X"28"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => new_cnt_c(0),
      I2 => new_cnt_c(1),
      O => Mcount_new_cnt_c1
    );
  Mcount_new_cnt_c_xor_2_11 : LUT4
    generic map(
      INIT => X"2888"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => new_cnt_c(2),
      I2 => new_cnt_c(0),
      I3 => new_cnt_c(1),
      O => Mcount_new_cnt_c2
    );
  Mcount_new_cnt_c_xor_3_11 : LUT5
    generic map(
      INIT => X"28888888"
    )
    port map (
      I0 => new_cnt_4959,
      I1 => new_cnt_c(3),
      I2 => new_cnt_c(2),
      I3 => new_cnt_c(0),
      I4 => new_cnt_c(1),
      O => Mcount_new_cnt_c3
    );
  Madd_freq_adc_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(12),
      O => Madd_freq_adc_add0000_cy_1_rt_4851
    );
  Madd_freq_adc_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(13),
      O => Madd_freq_adc_add0000_cy_2_rt_4853
    );
  Madd_freq_adc_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(14),
      O => Madd_freq_adc_add0000_cy_3_rt_4855
    );
  Madd_freq_adc_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(15),
      O => Madd_freq_adc_add0000_cy_4_rt_4857
    );
  Madd_freq_adc_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(16),
      O => Madd_freq_adc_add0000_cy_5_rt_4859
    );
  Madd_freq_adc_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(17),
      O => Madd_freq_adc_add0000_cy_6_rt_4861
    );
  Madd_freq_adc_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(18),
      O => Madd_freq_adc_add0000_cy_7_rt_4863
    );
  Madd_freq_adc_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(19),
      O => Madd_freq_adc_add0000_cy_8_rt_4865
    );
  Madd_freq_adc_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(20),
      O => Madd_freq_adc_add0000_cy_9_rt_4867
    );
  Madd_freq_adc_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(21),
      O => Madd_freq_adc_add0000_cy_10_rt_4841
    );
  Madd_freq_adc_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(22),
      O => Madd_freq_adc_add0000_cy_11_rt_4843
    );
  Madd_freq_adc_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(23),
      O => Madd_freq_adc_add0000_cy_12_rt_4845
    );
  Madd_freq_adc_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(24),
      O => Madd_freq_adc_add0000_cy_13_rt_4847
    );
  Madd_freq_adc_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => result_freq(25),
      O => Madd_freq_adc_add0000_cy_14_rt_4849
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );
  new_cnt_inv1_INV_0 : INV
    port map (
      I => new_cnt_4959,
      O => new_cnt_inv
    );
  new_cnt_c_not000111_INV_0 : INV
    port map (
      I => new_cnt_4959,
      O => new_cnt_c_not0001
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_test_check is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    do_data_en : in STD_LOGIC := 'X'; 
    do_clk : in STD_LOGIC := 'X'; 
    test_check_error : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test_check_bl_ok : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test_check_bl_rd : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test_check_err_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_check_bl_err : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test_check_ctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_check_size : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_check_err_adr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    do_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end cl_test_check;

architecture STRUCTURE of cl_test_check is
  signal Madd_data_ex4_31_0_add0000_cy_10_rt_2383 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_11_rt_2385 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_12_rt_2387 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_13_rt_2389 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_14_rt_2391 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_15_rt_2393 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_16_rt_2395 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_17_rt_2397 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_18_rt_2399 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_19_rt_2401 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_1_rt_2403 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_20_rt_2405 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_21_rt_2407 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_22_rt_2409 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_23_rt_2411 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_24_rt_2413 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_25_rt_2415 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_26_rt_2417 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_27_rt_2419 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_28_rt_2421 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_29_rt_2423 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_2_rt_2425 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_30_rt_2427 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_3_rt_2429 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_4_rt_2431 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_5_rt_2433 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_6_rt_2435 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_7_rt_2437 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_8_rt_2439 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_9_rt_2441 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_xor_31_rt_2443 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_10_rt_2446 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_11_rt_2448 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_12_rt_2450 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_13_rt_2452 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_14_rt_2454 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_15_rt_2456 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_16_rt_2458 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_17_rt_2460 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_18_rt_2462 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_19_rt_2464 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_1_rt_2466 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_20_rt_2468 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_21_rt_2470 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_22_rt_2472 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_23_rt_2474 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_24_rt_2476 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_25_rt_2478 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_26_rt_2480 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_27_rt_2482 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_28_rt_2484 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_29_rt_2486 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_2_rt_2488 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_30_rt_2490 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_3_rt_2492 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_4_rt_2494 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_5_rt_2496 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_6_rt_2498 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_7_rt_2500 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_8_rt_2502 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_9_rt_2504 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_xor_31_rt_2506 : STD_LOGIC; 
  signal Mcount_block_err_cy_10_rt_2563 : STD_LOGIC; 
  signal Mcount_block_err_cy_11_rt_2565 : STD_LOGIC; 
  signal Mcount_block_err_cy_12_rt_2567 : STD_LOGIC; 
  signal Mcount_block_err_cy_13_rt_2569 : STD_LOGIC; 
  signal Mcount_block_err_cy_14_rt_2571 : STD_LOGIC; 
  signal Mcount_block_err_cy_15_rt_2573 : STD_LOGIC; 
  signal Mcount_block_err_cy_16_rt_2575 : STD_LOGIC; 
  signal Mcount_block_err_cy_17_rt_2577 : STD_LOGIC; 
  signal Mcount_block_err_cy_18_rt_2579 : STD_LOGIC; 
  signal Mcount_block_err_cy_19_rt_2581 : STD_LOGIC; 
  signal Mcount_block_err_cy_1_rt_2583 : STD_LOGIC; 
  signal Mcount_block_err_cy_20_rt_2585 : STD_LOGIC; 
  signal Mcount_block_err_cy_21_rt_2587 : STD_LOGIC; 
  signal Mcount_block_err_cy_22_rt_2589 : STD_LOGIC; 
  signal Mcount_block_err_cy_23_rt_2591 : STD_LOGIC; 
  signal Mcount_block_err_cy_24_rt_2593 : STD_LOGIC; 
  signal Mcount_block_err_cy_25_rt_2595 : STD_LOGIC; 
  signal Mcount_block_err_cy_26_rt_2597 : STD_LOGIC; 
  signal Mcount_block_err_cy_27_rt_2599 : STD_LOGIC; 
  signal Mcount_block_err_cy_28_rt_2601 : STD_LOGIC; 
  signal Mcount_block_err_cy_29_rt_2603 : STD_LOGIC; 
  signal Mcount_block_err_cy_2_rt_2605 : STD_LOGIC; 
  signal Mcount_block_err_cy_30_rt_2607 : STD_LOGIC; 
  signal Mcount_block_err_cy_3_rt_2609 : STD_LOGIC; 
  signal Mcount_block_err_cy_4_rt_2611 : STD_LOGIC; 
  signal Mcount_block_err_cy_5_rt_2613 : STD_LOGIC; 
  signal Mcount_block_err_cy_6_rt_2615 : STD_LOGIC; 
  signal Mcount_block_err_cy_7_rt_2617 : STD_LOGIC; 
  signal Mcount_block_err_cy_8_rt_2619 : STD_LOGIC; 
  signal Mcount_block_err_cy_9_rt_2621 : STD_LOGIC; 
  signal Mcount_block_mode : STD_LOGIC; 
  signal Mcount_block_mode1 : STD_LOGIC; 
  signal Mcount_block_mode2 : STD_LOGIC; 
  signal Mcount_block_mode3 : STD_LOGIC; 
  signal Mcount_block_ok_cy_10_rt_2629 : STD_LOGIC; 
  signal Mcount_block_ok_cy_11_rt_2631 : STD_LOGIC; 
  signal Mcount_block_ok_cy_12_rt_2633 : STD_LOGIC; 
  signal Mcount_block_ok_cy_13_rt_2635 : STD_LOGIC; 
  signal Mcount_block_ok_cy_14_rt_2637 : STD_LOGIC; 
  signal Mcount_block_ok_cy_15_rt_2639 : STD_LOGIC; 
  signal Mcount_block_ok_cy_16_rt_2641 : STD_LOGIC; 
  signal Mcount_block_ok_cy_17_rt_2643 : STD_LOGIC; 
  signal Mcount_block_ok_cy_18_rt_2645 : STD_LOGIC; 
  signal Mcount_block_ok_cy_19_rt_2647 : STD_LOGIC; 
  signal Mcount_block_ok_cy_1_rt_2649 : STD_LOGIC; 
  signal Mcount_block_ok_cy_20_rt_2651 : STD_LOGIC; 
  signal Mcount_block_ok_cy_21_rt_2653 : STD_LOGIC; 
  signal Mcount_block_ok_cy_22_rt_2655 : STD_LOGIC; 
  signal Mcount_block_ok_cy_23_rt_2657 : STD_LOGIC; 
  signal Mcount_block_ok_cy_24_rt_2659 : STD_LOGIC; 
  signal Mcount_block_ok_cy_25_rt_2661 : STD_LOGIC; 
  signal Mcount_block_ok_cy_26_rt_2663 : STD_LOGIC; 
  signal Mcount_block_ok_cy_27_rt_2665 : STD_LOGIC; 
  signal Mcount_block_ok_cy_28_rt_2667 : STD_LOGIC; 
  signal Mcount_block_ok_cy_29_rt_2669 : STD_LOGIC; 
  signal Mcount_block_ok_cy_2_rt_2671 : STD_LOGIC; 
  signal Mcount_block_ok_cy_30_rt_2673 : STD_LOGIC; 
  signal Mcount_block_ok_cy_3_rt_2675 : STD_LOGIC; 
  signal Mcount_block_ok_cy_4_rt_2677 : STD_LOGIC; 
  signal Mcount_block_ok_cy_5_rt_2679 : STD_LOGIC; 
  signal Mcount_block_ok_cy_6_rt_2681 : STD_LOGIC; 
  signal Mcount_block_ok_cy_7_rt_2683 : STD_LOGIC; 
  signal Mcount_block_ok_cy_8_rt_2685 : STD_LOGIC; 
  signal Mcount_block_ok_cy_9_rt_2687 : STD_LOGIC; 
  signal Mcount_block_rd_cy_10_rt_2691 : STD_LOGIC; 
  signal Mcount_block_rd_cy_11_rt_2693 : STD_LOGIC; 
  signal Mcount_block_rd_cy_12_rt_2695 : STD_LOGIC; 
  signal Mcount_block_rd_cy_13_rt_2697 : STD_LOGIC; 
  signal Mcount_block_rd_cy_14_rt_2699 : STD_LOGIC; 
  signal Mcount_block_rd_cy_15_rt_2701 : STD_LOGIC; 
  signal Mcount_block_rd_cy_16_rt_2703 : STD_LOGIC; 
  signal Mcount_block_rd_cy_17_rt_2705 : STD_LOGIC; 
  signal Mcount_block_rd_cy_18_rt_2707 : STD_LOGIC; 
  signal Mcount_block_rd_cy_19_rt_2709 : STD_LOGIC; 
  signal Mcount_block_rd_cy_1_rt_2711 : STD_LOGIC; 
  signal Mcount_block_rd_cy_20_rt_2713 : STD_LOGIC; 
  signal Mcount_block_rd_cy_21_rt_2715 : STD_LOGIC; 
  signal Mcount_block_rd_cy_22_rt_2717 : STD_LOGIC; 
  signal Mcount_block_rd_cy_23_rt_2719 : STD_LOGIC; 
  signal Mcount_block_rd_cy_24_rt_2721 : STD_LOGIC; 
  signal Mcount_block_rd_cy_25_rt_2723 : STD_LOGIC; 
  signal Mcount_block_rd_cy_26_rt_2725 : STD_LOGIC; 
  signal Mcount_block_rd_cy_27_rt_2727 : STD_LOGIC; 
  signal Mcount_block_rd_cy_28_rt_2729 : STD_LOGIC; 
  signal Mcount_block_rd_cy_29_rt_2731 : STD_LOGIC; 
  signal Mcount_block_rd_cy_2_rt_2733 : STD_LOGIC; 
  signal Mcount_block_rd_cy_30_rt_2735 : STD_LOGIC; 
  signal Mcount_block_rd_cy_3_rt_2737 : STD_LOGIC; 
  signal Mcount_block_rd_cy_4_rt_2739 : STD_LOGIC; 
  signal Mcount_block_rd_cy_5_rt_2741 : STD_LOGIC; 
  signal Mcount_block_rd_cy_6_rt_2743 : STD_LOGIC; 
  signal Mcount_block_rd_cy_7_rt_2745 : STD_LOGIC; 
  signal Mcount_block_rd_cy_8_rt_2747 : STD_LOGIC; 
  signal Mcount_block_rd_cy_9_rt_2749 : STD_LOGIC; 
  signal Mcount_block_rd_xor_31_rt_2751 : STD_LOGIC; 
  signal Mcount_cnt1_cy_10_rt_2754 : STD_LOGIC; 
  signal Mcount_cnt1_cy_11_rt_2756 : STD_LOGIC; 
  signal Mcount_cnt1_cy_12_rt_2758 : STD_LOGIC; 
  signal Mcount_cnt1_cy_13_rt_2760 : STD_LOGIC; 
  signal Mcount_cnt1_cy_14_rt_2762 : STD_LOGIC; 
  signal Mcount_cnt1_cy_15_rt_2764 : STD_LOGIC; 
  signal Mcount_cnt1_cy_16_rt_2766 : STD_LOGIC; 
  signal Mcount_cnt1_cy_17_rt_2768 : STD_LOGIC; 
  signal Mcount_cnt1_cy_18_rt_2770 : STD_LOGIC; 
  signal Mcount_cnt1_cy_19_rt_2772 : STD_LOGIC; 
  signal Mcount_cnt1_cy_1_rt_2774 : STD_LOGIC; 
  signal Mcount_cnt1_cy_20_rt_2776 : STD_LOGIC; 
  signal Mcount_cnt1_cy_21_rt_2778 : STD_LOGIC; 
  signal Mcount_cnt1_cy_22_rt_2780 : STD_LOGIC; 
  signal Mcount_cnt1_cy_23_rt_2782 : STD_LOGIC; 
  signal Mcount_cnt1_cy_2_rt_2784 : STD_LOGIC; 
  signal Mcount_cnt1_cy_3_rt_2786 : STD_LOGIC; 
  signal Mcount_cnt1_cy_4_rt_2788 : STD_LOGIC; 
  signal Mcount_cnt1_cy_5_rt_2790 : STD_LOGIC; 
  signal Mcount_cnt1_cy_6_rt_2792 : STD_LOGIC; 
  signal Mcount_cnt1_cy_7_rt_2794 : STD_LOGIC; 
  signal Mcount_cnt1_cy_8_rt_2796 : STD_LOGIC; 
  signal Mcount_cnt1_cy_9_rt_2798 : STD_LOGIC; 
  signal Mcount_cnt1_xor_24_rt_2800 : STD_LOGIC; 
  signal Mcount_total_err_cy_10_rt_2803 : STD_LOGIC; 
  signal Mcount_total_err_cy_11_rt_2805 : STD_LOGIC; 
  signal Mcount_total_err_cy_12_rt_2807 : STD_LOGIC; 
  signal Mcount_total_err_cy_13_rt_2809 : STD_LOGIC; 
  signal Mcount_total_err_cy_14_rt_2811 : STD_LOGIC; 
  signal Mcount_total_err_cy_15_rt_2813 : STD_LOGIC; 
  signal Mcount_total_err_cy_16_rt_2815 : STD_LOGIC; 
  signal Mcount_total_err_cy_17_rt_2817 : STD_LOGIC; 
  signal Mcount_total_err_cy_18_rt_2819 : STD_LOGIC; 
  signal Mcount_total_err_cy_19_rt_2821 : STD_LOGIC; 
  signal Mcount_total_err_cy_1_rt_2823 : STD_LOGIC; 
  signal Mcount_total_err_cy_20_rt_2825 : STD_LOGIC; 
  signal Mcount_total_err_cy_21_rt_2827 : STD_LOGIC; 
  signal Mcount_total_err_cy_22_rt_2829 : STD_LOGIC; 
  signal Mcount_total_err_cy_23_rt_2831 : STD_LOGIC; 
  signal Mcount_total_err_cy_24_rt_2833 : STD_LOGIC; 
  signal Mcount_total_err_cy_25_rt_2835 : STD_LOGIC; 
  signal Mcount_total_err_cy_26_rt_2837 : STD_LOGIC; 
  signal Mcount_total_err_cy_27_rt_2839 : STD_LOGIC; 
  signal Mcount_total_err_cy_28_rt_2841 : STD_LOGIC; 
  signal Mcount_total_err_cy_29_rt_2843 : STD_LOGIC; 
  signal Mcount_total_err_cy_2_rt_2845 : STD_LOGIC; 
  signal Mcount_total_err_cy_30_rt_2847 : STD_LOGIC; 
  signal Mcount_total_err_cy_3_rt_2849 : STD_LOGIC; 
  signal Mcount_total_err_cy_4_rt_2851 : STD_LOGIC; 
  signal Mcount_total_err_cy_5_rt_2853 : STD_LOGIC; 
  signal Mcount_total_err_cy_6_rt_2855 : STD_LOGIC; 
  signal Mcount_total_err_cy_7_rt_2857 : STD_LOGIC; 
  signal Mcount_total_err_cy_8_rt_2859 : STD_LOGIC; 
  signal Mcount_total_err_cy_9_rt_2861 : STD_LOGIC; 
  signal Mcount_total_err_xor_31_rt_2863 : STD_LOGIC; 
  signal Mmux_err_data_5_f7_2864 : STD_LOGIC; 
  signal Mmux_err_data_5_f71 : STD_LOGIC; 
  signal Mmux_err_data_5_f710 : STD_LOGIC; 
  signal Mmux_err_data_5_f711 : STD_LOGIC; 
  signal Mmux_err_data_5_f712 : STD_LOGIC; 
  signal Mmux_err_data_5_f713 : STD_LOGIC; 
  signal Mmux_err_data_5_f714 : STD_LOGIC; 
  signal Mmux_err_data_5_f715 : STD_LOGIC; 
  signal Mmux_err_data_5_f72 : STD_LOGIC; 
  signal Mmux_err_data_5_f73 : STD_LOGIC; 
  signal Mmux_err_data_5_f74 : STD_LOGIC; 
  signal Mmux_err_data_5_f75 : STD_LOGIC; 
  signal Mmux_err_data_5_f76 : STD_LOGIC; 
  signal Mmux_err_data_5_f77 : STD_LOGIC; 
  signal Mmux_err_data_5_f78 : STD_LOGIC; 
  signal Mmux_err_data_5_f79 : STD_LOGIC; 
  signal Mmux_err_data_6_2880 : STD_LOGIC; 
  signal Mmux_err_data_61_2881 : STD_LOGIC; 
  signal Mmux_err_data_610_2882 : STD_LOGIC; 
  signal Mmux_err_data_611_2883 : STD_LOGIC; 
  signal Mmux_err_data_612_2884 : STD_LOGIC; 
  signal Mmux_err_data_613_2885 : STD_LOGIC; 
  signal Mmux_err_data_614_2886 : STD_LOGIC; 
  signal Mmux_err_data_615_2887 : STD_LOGIC; 
  signal Mmux_err_data_62_2888 : STD_LOGIC; 
  signal Mmux_err_data_63_2889 : STD_LOGIC; 
  signal Mmux_err_data_64_2890 : STD_LOGIC; 
  signal Mmux_err_data_65_2891 : STD_LOGIC; 
  signal Mmux_err_data_66_2892 : STD_LOGIC; 
  signal Mmux_err_data_67_2893 : STD_LOGIC; 
  signal Mmux_err_data_68_2894 : STD_LOGIC; 
  signal Mmux_err_data_69_2895 : STD_LOGIC; 
  signal Mmux_err_data_7_2896 : STD_LOGIC; 
  signal Mmux_err_data_71_2897 : STD_LOGIC; 
  signal Mmux_err_data_710_2898 : STD_LOGIC; 
  signal Mmux_err_data_711_2899 : STD_LOGIC; 
  signal Mmux_err_data_712_2900 : STD_LOGIC; 
  signal Mmux_err_data_713_2901 : STD_LOGIC; 
  signal Mmux_err_data_714_2902 : STD_LOGIC; 
  signal Mmux_err_data_715_2903 : STD_LOGIC; 
  signal Mmux_err_data_72_2904 : STD_LOGIC; 
  signal Mmux_err_data_73_2905 : STD_LOGIC; 
  signal Mmux_err_data_74_2906 : STD_LOGIC; 
  signal Mmux_err_data_75_2907 : STD_LOGIC; 
  signal Mmux_err_data_76_2908 : STD_LOGIC; 
  signal Mmux_err_data_77_2909 : STD_LOGIC; 
  signal Mmux_err_data_78_2910 : STD_LOGIC; 
  signal Mmux_err_data_79_2911 : STD_LOGIC; 
  signal Msub_cnt1_eq_addsub0000_cy_0_rt_2913 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N248 : STD_LOGIC; 
  signal N249 : STD_LOGIC; 
  signal N250 : STD_LOGIC; 
  signal N251 : STD_LOGIC; 
  signal N252 : STD_LOGIC; 
  signal N253 : STD_LOGIC; 
  signal N254 : STD_LOGIC; 
  signal N255 : STD_LOGIC; 
  signal N256 : STD_LOGIC; 
  signal N257 : STD_LOGIC; 
  signal N258 : STD_LOGIC; 
  signal N259 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N260 : STD_LOGIC; 
  signal N261 : STD_LOGIC; 
  signal N262 : STD_LOGIC; 
  signal N263 : STD_LOGIC; 
  signal N264 : STD_LOGIC; 
  signal N265 : STD_LOGIC; 
  signal N266 : STD_LOGIC; 
  signal N267 : STD_LOGIC; 
  signal N268 : STD_LOGIC; 
  signal N269 : STD_LOGIC; 
  signal N270 : STD_LOGIC; 
  signal N271 : STD_LOGIC; 
  signal N272 : STD_LOGIC; 
  signal N273 : STD_LOGIC; 
  signal N274 : STD_LOGIC; 
  signal N275 : STD_LOGIC; 
  signal N276 : STD_LOGIC; 
  signal N277 : STD_LOGIC; 
  signal N278 : STD_LOGIC; 
  signal N279 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N280 : STD_LOGIC; 
  signal N281 : STD_LOGIC; 
  signal N282 : STD_LOGIC; 
  signal N283 : STD_LOGIC; 
  signal N284 : STD_LOGIC; 
  signal N285 : STD_LOGIC; 
  signal N286 : STD_LOGIC; 
  signal N287 : STD_LOGIC; 
  signal N288 : STD_LOGIC; 
  signal N289 : STD_LOGIC; 
  signal N290 : STD_LOGIC; 
  signal N291 : STD_LOGIC; 
  signal N292 : STD_LOGIC; 
  signal N293 : STD_LOGIC; 
  signal N294 : STD_LOGIC; 
  signal N295 : STD_LOGIC; 
  signal N296 : STD_LOGIC; 
  signal N297 : STD_LOGIC; 
  signal N298 : STD_LOGIC; 
  signal N299 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N300 : STD_LOGIC; 
  signal N301 : STD_LOGIC; 
  signal N302 : STD_LOGIC; 
  signal N303 : STD_LOGIC; 
  signal N304 : STD_LOGIC; 
  signal N305 : STD_LOGIC; 
  signal N306 : STD_LOGIC; 
  signal N307 : STD_LOGIC; 
  signal N308 : STD_LOGIC; 
  signal N309 : STD_LOGIC; 
  signal N310 : STD_LOGIC; 
  signal N311 : STD_LOGIC; 
  signal N312 : STD_LOGIC; 
  signal N313 : STD_LOGIC; 
  signal N314 : STD_LOGIC; 
  signal N315 : STD_LOGIC; 
  signal N316 : STD_LOGIC; 
  signal N317 : STD_LOGIC; 
  signal N318 : STD_LOGIC; 
  signal N319 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N320 : STD_LOGIC; 
  signal N321 : STD_LOGIC; 
  signal N322 : STD_LOGIC; 
  signal N323 : STD_LOGIC; 
  signal N324 : STD_LOGIC; 
  signal N325 : STD_LOGIC; 
  signal N326 : STD_LOGIC; 
  signal N327 : STD_LOGIC; 
  signal N328 : STD_LOGIC; 
  signal N329 : STD_LOGIC; 
  signal N330 : STD_LOGIC; 
  signal N331 : STD_LOGIC; 
  signal N332 : STD_LOGIC; 
  signal N333 : STD_LOGIC; 
  signal N334 : STD_LOGIC; 
  signal N335 : STD_LOGIC; 
  signal N336 : STD_LOGIC; 
  signal N337 : STD_LOGIC; 
  signal N338 : STD_LOGIC; 
  signal N339 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N340 : STD_LOGIC; 
  signal N341 : STD_LOGIC; 
  signal N342 : STD_LOGIC; 
  signal N343 : STD_LOGIC; 
  signal N344 : STD_LOGIC; 
  signal N345 : STD_LOGIC; 
  signal N346 : STD_LOGIC; 
  signal N347 : STD_LOGIC; 
  signal N348 : STD_LOGIC; 
  signal N349 : STD_LOGIC; 
  signal N350 : STD_LOGIC; 
  signal N351 : STD_LOGIC; 
  signal N352 : STD_LOGIC; 
  signal N353 : STD_LOGIC; 
  signal N354 : STD_LOGIC; 
  signal N355 : STD_LOGIC; 
  signal N356 : STD_LOGIC; 
  signal N357 : STD_LOGIC; 
  signal N358 : STD_LOGIC; 
  signal N359 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N360 : STD_LOGIC; 
  signal N361 : STD_LOGIC; 
  signal N362 : STD_LOGIC; 
  signal N363 : STD_LOGIC; 
  signal N364 : STD_LOGIC; 
  signal N365 : STD_LOGIC; 
  signal N366 : STD_LOGIC; 
  signal N367 : STD_LOGIC; 
  signal N368 : STD_LOGIC; 
  signal N369 : STD_LOGIC; 
  signal N370 : STD_LOGIC; 
  signal N371 : STD_LOGIC; 
  signal N372 : STD_LOGIC; 
  signal N373 : STD_LOGIC; 
  signal N374 : STD_LOGIC; 
  signal N375 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N63 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_0_2 : STD_LOGIC; 
  signal Result_0_3 : STD_LOGIC; 
  signal Result_0_4 : STD_LOGIC; 
  signal Result_10_1 : STD_LOGIC; 
  signal Result_10_2 : STD_LOGIC; 
  signal Result_10_3 : STD_LOGIC; 
  signal Result_10_4 : STD_LOGIC; 
  signal Result_11_1 : STD_LOGIC; 
  signal Result_11_2 : STD_LOGIC; 
  signal Result_11_3 : STD_LOGIC; 
  signal Result_11_4 : STD_LOGIC; 
  signal Result_12_1 : STD_LOGIC; 
  signal Result_12_2 : STD_LOGIC; 
  signal Result_12_3 : STD_LOGIC; 
  signal Result_12_4 : STD_LOGIC; 
  signal Result_13_1 : STD_LOGIC; 
  signal Result_13_2 : STD_LOGIC; 
  signal Result_13_3 : STD_LOGIC; 
  signal Result_13_4 : STD_LOGIC; 
  signal Result_14_1 : STD_LOGIC; 
  signal Result_14_2 : STD_LOGIC; 
  signal Result_14_3 : STD_LOGIC; 
  signal Result_14_4 : STD_LOGIC; 
  signal Result_15_1 : STD_LOGIC; 
  signal Result_15_2 : STD_LOGIC; 
  signal Result_15_3 : STD_LOGIC; 
  signal Result_15_4 : STD_LOGIC; 
  signal Result_16_1 : STD_LOGIC; 
  signal Result_16_2 : STD_LOGIC; 
  signal Result_16_3 : STD_LOGIC; 
  signal Result_16_4 : STD_LOGIC; 
  signal Result_17_1 : STD_LOGIC; 
  signal Result_17_2 : STD_LOGIC; 
  signal Result_17_3 : STD_LOGIC; 
  signal Result_17_4 : STD_LOGIC; 
  signal Result_18_1 : STD_LOGIC; 
  signal Result_18_2 : STD_LOGIC; 
  signal Result_18_3 : STD_LOGIC; 
  signal Result_18_4 : STD_LOGIC; 
  signal Result_19_1 : STD_LOGIC; 
  signal Result_19_2 : STD_LOGIC; 
  signal Result_19_3 : STD_LOGIC; 
  signal Result_19_4 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_1_2 : STD_LOGIC; 
  signal Result_1_3 : STD_LOGIC; 
  signal Result_1_4 : STD_LOGIC; 
  signal Result_20_1 : STD_LOGIC; 
  signal Result_20_2 : STD_LOGIC; 
  signal Result_20_3 : STD_LOGIC; 
  signal Result_20_4 : STD_LOGIC; 
  signal Result_21_1 : STD_LOGIC; 
  signal Result_21_2 : STD_LOGIC; 
  signal Result_21_3 : STD_LOGIC; 
  signal Result_21_4 : STD_LOGIC; 
  signal Result_22_1 : STD_LOGIC; 
  signal Result_22_2 : STD_LOGIC; 
  signal Result_22_3 : STD_LOGIC; 
  signal Result_22_4 : STD_LOGIC; 
  signal Result_23_1 : STD_LOGIC; 
  signal Result_23_2 : STD_LOGIC; 
  signal Result_23_3 : STD_LOGIC; 
  signal Result_23_4 : STD_LOGIC; 
  signal Result_24_1 : STD_LOGIC; 
  signal Result_24_2 : STD_LOGIC; 
  signal Result_24_3 : STD_LOGIC; 
  signal Result_24_4 : STD_LOGIC; 
  signal Result_25_1 : STD_LOGIC; 
  signal Result_25_2 : STD_LOGIC; 
  signal Result_25_3 : STD_LOGIC; 
  signal Result_26_1 : STD_LOGIC; 
  signal Result_26_2 : STD_LOGIC; 
  signal Result_26_3 : STD_LOGIC; 
  signal Result_27_1 : STD_LOGIC; 
  signal Result_27_2 : STD_LOGIC; 
  signal Result_27_3 : STD_LOGIC; 
  signal Result_28_1 : STD_LOGIC; 
  signal Result_28_2 : STD_LOGIC; 
  signal Result_28_3 : STD_LOGIC; 
  signal Result_29_1 : STD_LOGIC; 
  signal Result_29_2 : STD_LOGIC; 
  signal Result_29_3 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_2_2 : STD_LOGIC; 
  signal Result_2_3 : STD_LOGIC; 
  signal Result_2_4 : STD_LOGIC; 
  signal Result_30_1 : STD_LOGIC; 
  signal Result_30_2 : STD_LOGIC; 
  signal Result_30_3 : STD_LOGIC; 
  signal Result_31_1 : STD_LOGIC; 
  signal Result_31_2 : STD_LOGIC; 
  signal Result_31_3 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_3_2 : STD_LOGIC; 
  signal Result_3_3 : STD_LOGIC; 
  signal Result_3_4 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_4_2 : STD_LOGIC; 
  signal Result_4_3 : STD_LOGIC; 
  signal Result_4_4 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_5_2 : STD_LOGIC; 
  signal Result_5_3 : STD_LOGIC; 
  signal Result_5_4 : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_6_2 : STD_LOGIC; 
  signal Result_6_3 : STD_LOGIC; 
  signal Result_6_4 : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal Result_7_2 : STD_LOGIC; 
  signal Result_7_3 : STD_LOGIC; 
  signal Result_7_4 : STD_LOGIC; 
  signal Result_8_1 : STD_LOGIC; 
  signal Result_8_2 : STD_LOGIC; 
  signal Result_8_3 : STD_LOGIC; 
  signal Result_8_4 : STD_LOGIC; 
  signal Result_9_1 : STD_LOGIC; 
  signal Result_9_2 : STD_LOGIC; 
  signal Result_9_3 : STD_LOGIC; 
  signal Result_9_4 : STD_LOGIC; 
  signal block_err_not0001 : STD_LOGIC; 
  signal block_mode_not0001 : STD_LOGIC; 
  signal block_mode_or0000_3285 : STD_LOGIC; 
  signal block_ok_en_3318 : STD_LOGIC; 
  signal block_ok_not0001 : STD_LOGIC; 
  signal block_rd_and0000 : STD_LOGIC; 
  signal cnt1_eq_3379 : STD_LOGIC; 
  signal cnt1_eq_and0000_3396 : STD_LOGIC; 
  signal cnt1_eq_cmp_eq0000 : STD_LOGIC; 
  signal cnt1_or0000 : STD_LOGIC; 
  signal cnt1_z_3399 : STD_LOGIC; 
  signal data_en_z_3400 : STD_LOGIC; 
  signal data_error_153_Q : STD_LOGIC; 
  signal data_error_128_Q : STD_LOGIC; 
  signal data_error_129_Q : STD_LOGIC; 
  signal data_error_130_Q : STD_LOGIC; 
  signal data_error_131_Q : STD_LOGIC; 
  signal data_error_132_Q : STD_LOGIC; 
  signal data_error_133_Q : STD_LOGIC; 
  signal data_error_134_Q : STD_LOGIC; 
  signal data_error_135_Q : STD_LOGIC; 
  signal data_error_136_Q : STD_LOGIC; 
  signal data_error_137_Q : STD_LOGIC; 
  signal data_error_138_Q : STD_LOGIC; 
  signal data_error_139_Q : STD_LOGIC; 
  signal data_error_140_Q : STD_LOGIC; 
  signal data_error_141_Q : STD_LOGIC; 
  signal data_error_142_Q : STD_LOGIC; 
  signal data_error_143_Q : STD_LOGIC; 
  signal data_error_144_Q : STD_LOGIC; 
  signal data_error_145_Q : STD_LOGIC; 
  signal data_error_146_Q : STD_LOGIC; 
  signal data_error_147_Q : STD_LOGIC; 
  signal data_error_148_Q : STD_LOGIC; 
  signal data_error_149_Q : STD_LOGIC; 
  signal data_error_150_Q : STD_LOGIC; 
  signal data_error_151_Q : STD_LOGIC; 
  signal data_error_152_Q : STD_LOGIC; 
  signal data_error_160_Q : STD_LOGIC; 
  signal data_error_161_Q : STD_LOGIC; 
  signal data_error_162_Q : STD_LOGIC; 
  signal data_error_163_Q : STD_LOGIC; 
  signal data_error_164_Q : STD_LOGIC; 
  signal data_error_165_Q : STD_LOGIC; 
  signal data_error_166_Q : STD_LOGIC; 
  signal data_error_167_Q : STD_LOGIC; 
  signal data_error_168_Q : STD_LOGIC; 
  signal data_error_169_Q : STD_LOGIC; 
  signal data_error_170_Q : STD_LOGIC; 
  signal data_error_171_Q : STD_LOGIC; 
  signal data_error_172_Q : STD_LOGIC; 
  signal data_error_173_Q : STD_LOGIC; 
  signal data_error_174_Q : STD_LOGIC; 
  signal data_error_175_Q : STD_LOGIC; 
  signal data_error_176_Q : STD_LOGIC; 
  signal data_error_177_Q : STD_LOGIC; 
  signal data_error_178_Q : STD_LOGIC; 
  signal data_error_179_Q : STD_LOGIC; 
  signal data_error_180_Q : STD_LOGIC; 
  signal data_error_181_Q : STD_LOGIC; 
  signal data_error_182_Q : STD_LOGIC; 
  signal data_error_183_Q : STD_LOGIC; 
  signal data_error_184_Q : STD_LOGIC; 
  signal data_error_185_Q : STD_LOGIC; 
  signal data_error_186_Q : STD_LOGIC; 
  signal data_error_187_Q : STD_LOGIC; 
  signal data_error_188_Q : STD_LOGIC; 
  signal data_error_189_Q : STD_LOGIC; 
  signal data_error_190_Q : STD_LOGIC; 
  signal data_error_191_Q : STD_LOGIC; 
  signal data_error_ovr_3651 : STD_LOGIC; 
  signal data_error_ovr_and0000 : STD_LOGIC; 
  signal data_error_wr : STD_LOGIC; 
  signal data_error_wr1_3654 : STD_LOGIC; 
  signal data_ex0_0_mux0000 : STD_LOGIC; 
  signal data_ex0_0_not0001 : STD_LOGIC; 
  signal data_ex0_10_mux0000 : STD_LOGIC; 
  signal data_ex0_11_mux0000 : STD_LOGIC; 
  signal data_ex0_12_mux0000 : STD_LOGIC; 
  signal data_ex0_13_mux0000 : STD_LOGIC; 
  signal data_ex0_14_mux0000 : STD_LOGIC; 
  signal data_ex0_15_mux0000 : STD_LOGIC; 
  signal data_ex0_16_mux0000 : STD_LOGIC; 
  signal data_ex0_17_mux0000 : STD_LOGIC; 
  signal data_ex0_18_mux0000 : STD_LOGIC; 
  signal data_ex0_19_mux0000 : STD_LOGIC; 
  signal data_ex0_1_mux0000 : STD_LOGIC; 
  signal data_ex0_20_mux0000 : STD_LOGIC; 
  signal data_ex0_21_mux0000 : STD_LOGIC; 
  signal data_ex0_22_mux0000 : STD_LOGIC; 
  signal data_ex0_23_mux0000 : STD_LOGIC; 
  signal data_ex0_24_mux0000 : STD_LOGIC; 
  signal data_ex0_25_mux0000 : STD_LOGIC; 
  signal data_ex0_26_mux0000 : STD_LOGIC; 
  signal data_ex0_27_mux0000 : STD_LOGIC; 
  signal data_ex0_28_mux0000 : STD_LOGIC; 
  signal data_ex0_29_mux0000 : STD_LOGIC; 
  signal data_ex0_2_mux0000 : STD_LOGIC; 
  signal data_ex0_30_mux0000 : STD_LOGIC; 
  signal data_ex0_31_mux0000 : STD_LOGIC; 
  signal data_ex0_32_mux0000 : STD_LOGIC; 
  signal data_ex0_33_mux0000 : STD_LOGIC; 
  signal data_ex0_34_mux0000 : STD_LOGIC; 
  signal data_ex0_35_mux0000 : STD_LOGIC; 
  signal data_ex0_36_mux0000 : STD_LOGIC; 
  signal data_ex0_37_mux0000 : STD_LOGIC; 
  signal data_ex0_38_mux0000 : STD_LOGIC; 
  signal data_ex0_39_mux0000 : STD_LOGIC; 
  signal data_ex0_3_mux0000 : STD_LOGIC; 
  signal data_ex0_40_mux0000 : STD_LOGIC; 
  signal data_ex0_41_mux0000 : STD_LOGIC; 
  signal data_ex0_42_mux0000 : STD_LOGIC; 
  signal data_ex0_43_mux0000 : STD_LOGIC; 
  signal data_ex0_44_mux0000 : STD_LOGIC; 
  signal data_ex0_45_mux0000 : STD_LOGIC; 
  signal data_ex0_46_mux0000 : STD_LOGIC; 
  signal data_ex0_47_mux0000 : STD_LOGIC; 
  signal data_ex0_48_mux0000 : STD_LOGIC; 
  signal data_ex0_49_mux0000 : STD_LOGIC; 
  signal data_ex0_4_mux0000 : STD_LOGIC; 
  signal data_ex0_50_mux0000 : STD_LOGIC; 
  signal data_ex0_51_mux0000 : STD_LOGIC; 
  signal data_ex0_52_mux0000 : STD_LOGIC; 
  signal data_ex0_53_mux0000 : STD_LOGIC; 
  signal data_ex0_54_mux0000 : STD_LOGIC; 
  signal data_ex0_55_mux0000 : STD_LOGIC; 
  signal data_ex0_56_mux0000 : STD_LOGIC; 
  signal data_ex0_57_mux0000 : STD_LOGIC; 
  signal data_ex0_58_mux0000 : STD_LOGIC; 
  signal data_ex0_59_mux0000 : STD_LOGIC; 
  signal data_ex0_5_mux0000 : STD_LOGIC; 
  signal data_ex0_60_mux0000 : STD_LOGIC; 
  signal data_ex0_61_mux0000 : STD_LOGIC; 
  signal data_ex0_62_mux0000 : STD_LOGIC; 
  signal data_ex0_63_mux0000 : STD_LOGIC; 
  signal data_ex0_6_mux0000 : STD_LOGIC; 
  signal data_ex0_7_mux0000 : STD_LOGIC; 
  signal data_ex0_8_mux0000 : STD_LOGIC; 
  signal data_ex0_9_mux0000 : STD_LOGIC; 
  signal data_ex1_0_mux0000 : STD_LOGIC; 
  signal data_ex1_10_mux0000 : STD_LOGIC; 
  signal data_ex1_11_mux0000 : STD_LOGIC; 
  signal data_ex1_12_mux0000 : STD_LOGIC; 
  signal data_ex1_13_mux0000 : STD_LOGIC; 
  signal data_ex1_14_mux0000 : STD_LOGIC; 
  signal data_ex1_15_mux0000 : STD_LOGIC; 
  signal data_ex1_16_mux0000 : STD_LOGIC; 
  signal data_ex1_17_mux0000 : STD_LOGIC; 
  signal data_ex1_18_mux0000 : STD_LOGIC; 
  signal data_ex1_19_mux0000 : STD_LOGIC; 
  signal data_ex1_1_mux0000 : STD_LOGIC; 
  signal data_ex1_20_mux0000 : STD_LOGIC; 
  signal data_ex1_21_mux0000 : STD_LOGIC; 
  signal data_ex1_22_mux0000 : STD_LOGIC; 
  signal data_ex1_23_mux0000 : STD_LOGIC; 
  signal data_ex1_24_mux0000 : STD_LOGIC; 
  signal data_ex1_25_mux0000 : STD_LOGIC; 
  signal data_ex1_26_mux0000 : STD_LOGIC; 
  signal data_ex1_27_mux0000 : STD_LOGIC; 
  signal data_ex1_28_mux0000 : STD_LOGIC; 
  signal data_ex1_29_mux0000 : STD_LOGIC; 
  signal data_ex1_2_mux0000 : STD_LOGIC; 
  signal data_ex1_30_mux0000 : STD_LOGIC; 
  signal data_ex1_31_mux0000 : STD_LOGIC; 
  signal data_ex1_32_mux0000 : STD_LOGIC; 
  signal data_ex1_33_mux0000 : STD_LOGIC; 
  signal data_ex1_34_mux0000 : STD_LOGIC; 
  signal data_ex1_35_mux0000 : STD_LOGIC; 
  signal data_ex1_36_mux0000 : STD_LOGIC; 
  signal data_ex1_36_not0001_3845 : STD_LOGIC; 
  signal data_ex1_37_mux0000 : STD_LOGIC; 
  signal data_ex1_38_mux0000 : STD_LOGIC; 
  signal data_ex1_39_mux0000 : STD_LOGIC; 
  signal data_ex1_3_mux0000 : STD_LOGIC; 
  signal data_ex1_40_mux0000 : STD_LOGIC; 
  signal data_ex1_41_mux0000 : STD_LOGIC; 
  signal data_ex1_42_mux0000 : STD_LOGIC; 
  signal data_ex1_43_mux0000 : STD_LOGIC; 
  signal data_ex1_44_mux0000 : STD_LOGIC; 
  signal data_ex1_45_mux0000 : STD_LOGIC; 
  signal data_ex1_46_mux0000 : STD_LOGIC; 
  signal data_ex1_47_mux0000 : STD_LOGIC; 
  signal data_ex1_48_mux0000 : STD_LOGIC; 
  signal data_ex1_49_mux0000 : STD_LOGIC; 
  signal data_ex1_4_mux0000 : STD_LOGIC; 
  signal data_ex1_50_mux0000 : STD_LOGIC; 
  signal data_ex1_51_mux0000 : STD_LOGIC; 
  signal data_ex1_52_mux0000 : STD_LOGIC; 
  signal data_ex1_53_mux0000 : STD_LOGIC; 
  signal data_ex1_54_mux0000 : STD_LOGIC; 
  signal data_ex1_55_mux0000 : STD_LOGIC; 
  signal data_ex1_56_mux0000 : STD_LOGIC; 
  signal data_ex1_57_mux0000 : STD_LOGIC; 
  signal data_ex1_58_mux0000 : STD_LOGIC; 
  signal data_ex1_59_mux0000 : STD_LOGIC; 
  signal data_ex1_5_mux0000 : STD_LOGIC; 
  signal data_ex1_60_mux0000 : STD_LOGIC; 
  signal data_ex1_61_mux0000 : STD_LOGIC; 
  signal data_ex1_62_mux0000 : STD_LOGIC; 
  signal data_ex1_63_mux0000 : STD_LOGIC; 
  signal data_ex1_6_mux0000 : STD_LOGIC; 
  signal data_ex1_7_mux0000 : STD_LOGIC; 
  signal data_ex1_8_mux0000 : STD_LOGIC; 
  signal data_ex1_9_mux0000 : STD_LOGIC; 
  signal data_ex2_0_mux0000 : STD_LOGIC; 
  signal data_ex2_0_not0001 : STD_LOGIC; 
  signal data_ex2_10_mux0000 : STD_LOGIC; 
  signal data_ex2_11_mux0000 : STD_LOGIC; 
  signal data_ex2_12_mux0000 : STD_LOGIC; 
  signal data_ex2_13_mux0000 : STD_LOGIC; 
  signal data_ex2_14_mux0000 : STD_LOGIC; 
  signal data_ex2_15_mux0000 : STD_LOGIC; 
  signal data_ex2_16_mux0000 : STD_LOGIC; 
  signal data_ex2_17_mux0000 : STD_LOGIC; 
  signal data_ex2_18_mux0000 : STD_LOGIC; 
  signal data_ex2_19_mux0000 : STD_LOGIC; 
  signal data_ex2_1_mux0000 : STD_LOGIC; 
  signal data_ex2_20_mux0000 : STD_LOGIC; 
  signal data_ex2_21_mux0000 : STD_LOGIC; 
  signal data_ex2_22_mux0000 : STD_LOGIC; 
  signal data_ex2_23_mux0000 : STD_LOGIC; 
  signal data_ex2_24_mux0000 : STD_LOGIC; 
  signal data_ex2_25_mux0000 : STD_LOGIC; 
  signal data_ex2_26_mux0000 : STD_LOGIC; 
  signal data_ex2_27_mux0000 : STD_LOGIC; 
  signal data_ex2_28_mux0000 : STD_LOGIC; 
  signal data_ex2_29_mux0000 : STD_LOGIC; 
  signal data_ex2_2_mux0000 : STD_LOGIC; 
  signal data_ex2_30_mux0000 : STD_LOGIC; 
  signal data_ex2_31_mux0000 : STD_LOGIC; 
  signal data_ex2_32_mux0000 : STD_LOGIC; 
  signal data_ex2_33_mux0000 : STD_LOGIC; 
  signal data_ex2_34_mux0000 : STD_LOGIC; 
  signal data_ex2_35_mux0000 : STD_LOGIC; 
  signal data_ex2_36_mux0000 : STD_LOGIC; 
  signal data_ex2_37_mux0000 : STD_LOGIC; 
  signal data_ex2_38_mux0000 : STD_LOGIC; 
  signal data_ex2_39_mux0000 : STD_LOGIC; 
  signal data_ex2_3_mux0000 : STD_LOGIC; 
  signal data_ex2_40_mux0000 : STD_LOGIC; 
  signal data_ex2_41_mux0000 : STD_LOGIC; 
  signal data_ex2_42_mux0000 : STD_LOGIC; 
  signal data_ex2_43_mux0000 : STD_LOGIC; 
  signal data_ex2_44_mux0000 : STD_LOGIC; 
  signal data_ex2_45_mux0000 : STD_LOGIC; 
  signal data_ex2_46_mux0000 : STD_LOGIC; 
  signal data_ex2_47_mux0000 : STD_LOGIC; 
  signal data_ex2_48_mux0000 : STD_LOGIC; 
  signal data_ex2_49_mux0000 : STD_LOGIC; 
  signal data_ex2_4_mux0000 : STD_LOGIC; 
  signal data_ex2_50_mux0000 : STD_LOGIC; 
  signal data_ex2_51_mux0000 : STD_LOGIC; 
  signal data_ex2_52_mux0000 : STD_LOGIC; 
  signal data_ex2_53_mux0000 : STD_LOGIC; 
  signal data_ex2_54_mux0000 : STD_LOGIC; 
  signal data_ex2_55_mux0000 : STD_LOGIC; 
  signal data_ex2_56_mux0000 : STD_LOGIC; 
  signal data_ex2_57_mux0000 : STD_LOGIC; 
  signal data_ex2_58_mux0000 : STD_LOGIC; 
  signal data_ex2_59_mux0000 : STD_LOGIC; 
  signal data_ex2_5_mux0000 : STD_LOGIC; 
  signal data_ex2_60_mux0000 : STD_LOGIC; 
  signal data_ex2_61_mux0000 : STD_LOGIC; 
  signal data_ex2_62_mux0000 : STD_LOGIC; 
  signal data_ex2_63_mux0000 : STD_LOGIC; 
  signal data_ex2_6_mux0000 : STD_LOGIC; 
  signal data_ex2_7_mux0000 : STD_LOGIC; 
  signal data_ex2_8_mux0000 : STD_LOGIC; 
  signal data_ex2_9_mux0000 : STD_LOGIC; 
  signal data_ex3_and0000 : STD_LOGIC; 
  signal data_ex3_not0001 : STD_LOGIC; 
  signal data_ex3_not0001_inv : STD_LOGIC; 
  signal data_ex4_10_not0001 : STD_LOGIC; 
  signal data_ex4_32_not0001 : STD_LOGIC; 
  signal data_ex4_32_not000123_4234 : STD_LOGIC; 
  signal data_ex4_32_not000137_4235 : STD_LOGIC; 
  signal data_ex4_32_not000148_4236 : STD_LOGIC; 
  signal data_ex4_32_not00016_4237 : STD_LOGIC; 
  signal data_ex4_32_not000170_4238 : STD_LOGIC; 
  signal data_ex4_32_not000181_4239 : STD_LOGIC; 
  signal data_ex5_0_xor0000 : STD_LOGIC; 
  signal data_ex5_10_not0001 : STD_LOGIC; 
  signal data_expect_0_mux0000 : STD_LOGIC; 
  signal data_expect_0_mux000031_4377 : STD_LOGIC; 
  signal data_expect_10_mux0000 : STD_LOGIC; 
  signal data_expect_10_mux000099_4381 : STD_LOGIC; 
  signal data_expect_11_mux0000 : STD_LOGIC; 
  signal data_expect_11_mux000099_4384 : STD_LOGIC; 
  signal data_expect_12_mux0000 : STD_LOGIC; 
  signal data_expect_12_mux000099_4387 : STD_LOGIC; 
  signal data_expect_13_mux0000 : STD_LOGIC; 
  signal data_expect_13_mux000099_4390 : STD_LOGIC; 
  signal data_expect_14_mux0000 : STD_LOGIC; 
  signal data_expect_14_mux000099_4393 : STD_LOGIC; 
  signal data_expect_15_mux0000 : STD_LOGIC; 
  signal data_expect_15_mux000099_4396 : STD_LOGIC; 
  signal data_expect_16_mux0000 : STD_LOGIC; 
  signal data_expect_16_mux000031_4399 : STD_LOGIC; 
  signal data_expect_17_mux0000 : STD_LOGIC; 
  signal data_expect_17_mux000099_4402 : STD_LOGIC; 
  signal data_expect_18_mux0000 : STD_LOGIC; 
  signal data_expect_18_mux000031_4405 : STD_LOGIC; 
  signal data_expect_19_mux0000 : STD_LOGIC; 
  signal data_expect_19_mux000099_4408 : STD_LOGIC; 
  signal data_expect_1_mux0000 : STD_LOGIC; 
  signal data_expect_1_mux000031_4410 : STD_LOGIC; 
  signal data_expect_20_mux0000 : STD_LOGIC; 
  signal data_expect_20_mux000099_4414 : STD_LOGIC; 
  signal data_expect_21_mux0000 : STD_LOGIC; 
  signal data_expect_21_mux000031_4417 : STD_LOGIC; 
  signal data_expect_22_mux0000 : STD_LOGIC; 
  signal data_expect_22_mux000099_4420 : STD_LOGIC; 
  signal data_expect_23_mux0000 : STD_LOGIC; 
  signal data_expect_23_mux000031_4423 : STD_LOGIC; 
  signal data_expect_24_mux0000 : STD_LOGIC; 
  signal data_expect_24_mux000031_4426 : STD_LOGIC; 
  signal data_expect_25_mux0000 : STD_LOGIC; 
  signal data_expect_25_mux000099_4429 : STD_LOGIC; 
  signal data_expect_26_mux0000 : STD_LOGIC; 
  signal data_expect_26_mux000031_4432 : STD_LOGIC; 
  signal data_expect_27_mux0000 : STD_LOGIC; 
  signal data_expect_27_mux000099_4435 : STD_LOGIC; 
  signal data_expect_28_mux0000 : STD_LOGIC; 
  signal data_expect_28_mux000099_4438 : STD_LOGIC; 
  signal data_expect_29_mux0000 : STD_LOGIC; 
  signal data_expect_29_mux000031_4441 : STD_LOGIC; 
  signal data_expect_2_mux0000 : STD_LOGIC; 
  signal data_expect_2_mux000099_4443 : STD_LOGIC; 
  signal data_expect_30_mux0000 : STD_LOGIC; 
  signal data_expect_30_mux000099_4447 : STD_LOGIC; 
  signal data_expect_31_mux0000 : STD_LOGIC; 
  signal data_expect_31_mux000031_4450 : STD_LOGIC; 
  signal data_expect_32_mux0000 : STD_LOGIC; 
  signal data_expect_32_mux0000114_4453 : STD_LOGIC; 
  signal data_expect_32_mux000099_4454 : STD_LOGIC; 
  signal data_expect_33_mux0000 : STD_LOGIC; 
  signal data_expect_33_mux0000114_4457 : STD_LOGIC; 
  signal data_expect_33_mux000099_4458 : STD_LOGIC; 
  signal data_expect_34_mux0000 : STD_LOGIC; 
  signal data_expect_34_mux0000114_4461 : STD_LOGIC; 
  signal data_expect_34_mux000099_4462 : STD_LOGIC; 
  signal data_expect_35_mux0000 : STD_LOGIC; 
  signal data_expect_35_mux0000114_4465 : STD_LOGIC; 
  signal data_expect_35_mux000099_4466 : STD_LOGIC; 
  signal data_expect_36_mux0000 : STD_LOGIC; 
  signal data_expect_36_mux0000114_4469 : STD_LOGIC; 
  signal data_expect_36_mux000099_4470 : STD_LOGIC; 
  signal data_expect_37_mux0000 : STD_LOGIC; 
  signal data_expect_37_mux0000114_4473 : STD_LOGIC; 
  signal data_expect_37_mux000099_4474 : STD_LOGIC; 
  signal data_expect_38_mux0000 : STD_LOGIC; 
  signal data_expect_38_mux0000114_4477 : STD_LOGIC; 
  signal data_expect_38_mux000099_4478 : STD_LOGIC; 
  signal data_expect_39_mux0000 : STD_LOGIC; 
  signal data_expect_39_mux0000114_4481 : STD_LOGIC; 
  signal data_expect_39_mux000099_4482 : STD_LOGIC; 
  signal data_expect_3_cmp_eq0006 : STD_LOGIC; 
  signal data_expect_3_cmp_eq00068126_4484 : STD_LOGIC; 
  signal data_expect_3_mux0000 : STD_LOGIC; 
  signal data_expect_3_mux000099_4486 : STD_LOGIC; 
  signal data_expect_3_not0001 : STD_LOGIC; 
  signal data_expect_40_mux0000 : STD_LOGIC; 
  signal data_expect_40_mux0000114_4491 : STD_LOGIC; 
  signal data_expect_40_mux000099_4492 : STD_LOGIC; 
  signal data_expect_41_mux0000 : STD_LOGIC; 
  signal data_expect_41_mux0000114_4495 : STD_LOGIC; 
  signal data_expect_41_mux000099_4496 : STD_LOGIC; 
  signal data_expect_42_mux0000 : STD_LOGIC; 
  signal data_expect_42_mux0000114_4499 : STD_LOGIC; 
  signal data_expect_42_mux000099_4500 : STD_LOGIC; 
  signal data_expect_43_mux0000 : STD_LOGIC; 
  signal data_expect_43_mux0000114_4503 : STD_LOGIC; 
  signal data_expect_43_mux000099_4504 : STD_LOGIC; 
  signal data_expect_44_mux0000 : STD_LOGIC; 
  signal data_expect_44_mux0000114_4507 : STD_LOGIC; 
  signal data_expect_44_mux000099_4508 : STD_LOGIC; 
  signal data_expect_45_mux0000 : STD_LOGIC; 
  signal data_expect_45_mux0000114_4511 : STD_LOGIC; 
  signal data_expect_45_mux000099_4512 : STD_LOGIC; 
  signal data_expect_46_mux0000 : STD_LOGIC; 
  signal data_expect_46_mux0000114_4515 : STD_LOGIC; 
  signal data_expect_46_mux000099_4516 : STD_LOGIC; 
  signal data_expect_47_mux0000 : STD_LOGIC; 
  signal data_expect_47_mux0000114_4519 : STD_LOGIC; 
  signal data_expect_47_mux000099_4520 : STD_LOGIC; 
  signal data_expect_48_mux0000 : STD_LOGIC; 
  signal data_expect_48_mux0000114_4523 : STD_LOGIC; 
  signal data_expect_48_mux000099_4524 : STD_LOGIC; 
  signal data_expect_49_mux0000 : STD_LOGIC; 
  signal data_expect_49_mux0000114_4527 : STD_LOGIC; 
  signal data_expect_49_mux000099_4528 : STD_LOGIC; 
  signal data_expect_4_mux0000 : STD_LOGIC; 
  signal data_expect_4_mux000099_4530 : STD_LOGIC; 
  signal data_expect_50_mux0000 : STD_LOGIC; 
  signal data_expect_50_mux0000114_4534 : STD_LOGIC; 
  signal data_expect_50_mux000099_4535 : STD_LOGIC; 
  signal data_expect_51_mux0000 : STD_LOGIC; 
  signal data_expect_51_mux0000114_4538 : STD_LOGIC; 
  signal data_expect_51_mux000099_4539 : STD_LOGIC; 
  signal data_expect_52_mux0000 : STD_LOGIC; 
  signal data_expect_52_mux0000114_4542 : STD_LOGIC; 
  signal data_expect_52_mux000099_4543 : STD_LOGIC; 
  signal data_expect_53_mux0000 : STD_LOGIC; 
  signal data_expect_53_mux0000114_4546 : STD_LOGIC; 
  signal data_expect_53_mux000099_4547 : STD_LOGIC; 
  signal data_expect_54_mux0000 : STD_LOGIC; 
  signal data_expect_54_mux0000114_4550 : STD_LOGIC; 
  signal data_expect_54_mux000099_4551 : STD_LOGIC; 
  signal data_expect_55_mux0000 : STD_LOGIC; 
  signal data_expect_55_mux0000114_4554 : STD_LOGIC; 
  signal data_expect_55_mux000099_4555 : STD_LOGIC; 
  signal data_expect_56_mux0000 : STD_LOGIC; 
  signal data_expect_56_mux0000114_4558 : STD_LOGIC; 
  signal data_expect_56_mux000099_4559 : STD_LOGIC; 
  signal data_expect_57_mux0000 : STD_LOGIC; 
  signal data_expect_57_mux0000114_4562 : STD_LOGIC; 
  signal data_expect_57_mux000099_4563 : STD_LOGIC; 
  signal data_expect_58_mux0000 : STD_LOGIC; 
  signal data_expect_58_mux0000114_4566 : STD_LOGIC; 
  signal data_expect_58_mux000099_4567 : STD_LOGIC; 
  signal data_expect_59_mux0000 : STD_LOGIC; 
  signal data_expect_59_mux0000114_4570 : STD_LOGIC; 
  signal data_expect_59_mux000099_4571 : STD_LOGIC; 
  signal data_expect_5_mux0000 : STD_LOGIC; 
  signal data_expect_5_mux000031_4573 : STD_LOGIC; 
  signal data_expect_60_mux0000 : STD_LOGIC; 
  signal data_expect_60_mux0000114_4577 : STD_LOGIC; 
  signal data_expect_60_mux000099_4578 : STD_LOGIC; 
  signal data_expect_61_mux0000 : STD_LOGIC; 
  signal data_expect_61_mux0000114_4581 : STD_LOGIC; 
  signal data_expect_61_mux000099_4582 : STD_LOGIC; 
  signal data_expect_62_mux0000 : STD_LOGIC; 
  signal data_expect_62_mux0000114_4585 : STD_LOGIC; 
  signal data_expect_62_mux000099_4586 : STD_LOGIC; 
  signal data_expect_63_mux0000 : STD_LOGIC; 
  signal data_expect_63_mux0000114_4589 : STD_LOGIC; 
  signal data_expect_63_mux000099_4590 : STD_LOGIC; 
  signal data_expect_6_mux0000 : STD_LOGIC; 
  signal data_expect_6_mux000099_4592 : STD_LOGIC; 
  signal data_expect_7_mux0000 : STD_LOGIC; 
  signal data_expect_7_mux000099_4595 : STD_LOGIC; 
  signal data_expect_8_mux0000 : STD_LOGIC; 
  signal data_expect_8_mux000031_4598 : STD_LOGIC; 
  signal data_expect_9_mux0000 : STD_LOGIC; 
  signal data_expect_9_mux000099_4601 : STD_LOGIC; 
  signal flag_error_4748 : STD_LOGIC; 
  signal flag_error_clr_4749 : STD_LOGIC; 
  signal rst_inv : STD_LOGIC; 
  signal total_err_and0000 : STD_LOGIC; 
  signal total_err_and0000128_4831 : STD_LOGIC; 
  signal total_err_and0000164_4832 : STD_LOGIC; 
  signal total_err_and0000240_4833 : STD_LOGIC; 
  signal total_err_and0000244_4834 : STD_LOGIC; 
  signal total_err_and0000262_4835 : STD_LOGIC; 
  signal total_err_and000035_4836 : STD_LOGIC; 
  signal total_err_and000071_4837 : STD_LOGIC; 
  signal word_error : STD_LOGIC; 
  signal NLW_gen_data_error_0_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_1_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_2_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_3_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_4_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_5_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_6_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_7_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_8_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_9_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_10_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_11_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_12_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_13_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_14_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_15_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_16_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_17_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_18_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_19_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_20_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_21_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_22_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_23_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_24_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_25_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_26_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_27_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_28_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_29_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_30_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_31_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_32_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_33_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_34_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_35_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_36_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_37_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_38_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_39_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_40_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_41_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_42_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_43_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_44_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_45_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_46_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_47_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_48_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_49_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_50_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_51_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_52_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_53_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_54_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_55_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_56_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_57_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_58_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_59_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_60_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_61_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_62_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_63_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_64_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_65_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_66_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_67_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_68_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_69_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_70_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_71_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_72_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_73_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_74_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_75_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_76_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_77_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_78_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_79_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_80_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_81_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_82_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_83_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_84_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_85_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_86_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_87_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_88_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_89_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_90_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_91_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_92_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_93_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_94_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_95_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_96_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_97_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_98_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_99_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_100_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_101_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_102_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_103_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_104_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_105_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_106_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_107_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_108_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_109_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_110_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_111_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_112_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_113_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_114_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_115_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_116_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_117_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_118_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_119_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_120_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_121_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_122_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_123_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_124_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_125_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_126_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_127_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_128_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_129_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_130_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_131_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_132_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_133_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_134_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_135_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_136_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_137_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_138_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_139_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_140_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_141_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_142_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_143_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_144_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_145_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_146_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_147_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_148_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_149_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_150_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_151_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_152_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_153_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_154_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_155_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_156_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_157_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_158_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_159_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_160_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_161_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_162_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_163_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_164_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_165_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_166_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_167_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_168_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_169_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_170_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_171_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_172_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_173_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_174_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_175_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_176_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_177_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_178_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_179_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_180_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_181_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_182_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_183_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_184_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_185_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_186_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_187_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_188_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_189_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_190_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_gen_data_error_191_ram0_SPO_UNCONNECTED : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Madd_data_ex4_31_0_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Madd_data_ex4_63_32_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Madd_data_ex4_63_32_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_cnt1_eq_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Mcompar_cnt1_eq_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcompar_word_error_cmp_ne0000_cy : STD_LOGIC_VECTOR ( 20 downto 0 ); 
  signal Mcompar_word_error_cmp_ne0000_lut : STD_LOGIC_VECTOR ( 21 downto 0 ); 
  signal Mcount_block_err_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Mcount_block_err_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_block_ok_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Mcount_block_ok_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_block_rd_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Mcount_block_rd_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt1_cy : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal Mcount_cnt1_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_total_err_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Mcount_total_err_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Msub_cnt1_eq_addsub0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Msub_cnt1_eq_addsub0000_lut : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal Result : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSig_OI_block_err : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal block_mode : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_block_ok : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal NlwRenamedSig_OI_block_rd : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cnt1 : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal cnt1_eq_addsub0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal data_error_out : STD_LOGIC_VECTOR ( 191 downto 0 ); 
  signal data_ex0 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex1 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex2 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex3 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex3_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex4 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex4_31_0_add0000 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal data_ex4_63_32_add0000 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal data_ex5 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_expect : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal do_data_z : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal err_data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_total_err : STD_LOGIC_VECTOR ( 31 downto 0 ); 
begin
  test_check_error(31) <= NlwRenamedSig_OI_total_err(31);
  test_check_error(30) <= NlwRenamedSig_OI_total_err(30);
  test_check_error(29) <= NlwRenamedSig_OI_total_err(29);
  test_check_error(28) <= NlwRenamedSig_OI_total_err(28);
  test_check_error(27) <= NlwRenamedSig_OI_total_err(27);
  test_check_error(26) <= NlwRenamedSig_OI_total_err(26);
  test_check_error(25) <= NlwRenamedSig_OI_total_err(25);
  test_check_error(24) <= NlwRenamedSig_OI_total_err(24);
  test_check_error(23) <= NlwRenamedSig_OI_total_err(23);
  test_check_error(22) <= NlwRenamedSig_OI_total_err(22);
  test_check_error(21) <= NlwRenamedSig_OI_total_err(21);
  test_check_error(20) <= NlwRenamedSig_OI_total_err(20);
  test_check_error(19) <= NlwRenamedSig_OI_total_err(19);
  test_check_error(18) <= NlwRenamedSig_OI_total_err(18);
  test_check_error(17) <= NlwRenamedSig_OI_total_err(17);
  test_check_error(16) <= NlwRenamedSig_OI_total_err(16);
  test_check_error(15) <= NlwRenamedSig_OI_total_err(15);
  test_check_error(14) <= NlwRenamedSig_OI_total_err(14);
  test_check_error(13) <= NlwRenamedSig_OI_total_err(13);
  test_check_error(12) <= NlwRenamedSig_OI_total_err(12);
  test_check_error(11) <= NlwRenamedSig_OI_total_err(11);
  test_check_error(10) <= NlwRenamedSig_OI_total_err(10);
  test_check_error(9) <= NlwRenamedSig_OI_total_err(9);
  test_check_error(8) <= NlwRenamedSig_OI_total_err(8);
  test_check_error(7) <= NlwRenamedSig_OI_total_err(7);
  test_check_error(6) <= NlwRenamedSig_OI_total_err(6);
  test_check_error(5) <= NlwRenamedSig_OI_total_err(5);
  test_check_error(4) <= NlwRenamedSig_OI_total_err(4);
  test_check_error(3) <= NlwRenamedSig_OI_total_err(3);
  test_check_error(2) <= NlwRenamedSig_OI_total_err(2);
  test_check_error(1) <= NlwRenamedSig_OI_total_err(1);
  test_check_error(0) <= NlwRenamedSig_OI_total_err(0);
  test_check_bl_ok(31) <= NlwRenamedSig_OI_block_ok(31);
  test_check_bl_ok(30) <= NlwRenamedSig_OI_block_ok(30);
  test_check_bl_ok(29) <= NlwRenamedSig_OI_block_ok(29);
  test_check_bl_ok(28) <= NlwRenamedSig_OI_block_ok(28);
  test_check_bl_ok(27) <= NlwRenamedSig_OI_block_ok(27);
  test_check_bl_ok(26) <= NlwRenamedSig_OI_block_ok(26);
  test_check_bl_ok(25) <= NlwRenamedSig_OI_block_ok(25);
  test_check_bl_ok(24) <= NlwRenamedSig_OI_block_ok(24);
  test_check_bl_ok(23) <= NlwRenamedSig_OI_block_ok(23);
  test_check_bl_ok(22) <= NlwRenamedSig_OI_block_ok(22);
  test_check_bl_ok(21) <= NlwRenamedSig_OI_block_ok(21);
  test_check_bl_ok(20) <= NlwRenamedSig_OI_block_ok(20);
  test_check_bl_ok(19) <= NlwRenamedSig_OI_block_ok(19);
  test_check_bl_ok(18) <= NlwRenamedSig_OI_block_ok(18);
  test_check_bl_ok(17) <= NlwRenamedSig_OI_block_ok(17);
  test_check_bl_ok(16) <= NlwRenamedSig_OI_block_ok(16);
  test_check_bl_ok(15) <= NlwRenamedSig_OI_block_ok(15);
  test_check_bl_ok(14) <= NlwRenamedSig_OI_block_ok(14);
  test_check_bl_ok(13) <= NlwRenamedSig_OI_block_ok(13);
  test_check_bl_ok(12) <= NlwRenamedSig_OI_block_ok(12);
  test_check_bl_ok(11) <= NlwRenamedSig_OI_block_ok(11);
  test_check_bl_ok(10) <= NlwRenamedSig_OI_block_ok(10);
  test_check_bl_ok(9) <= NlwRenamedSig_OI_block_ok(9);
  test_check_bl_ok(8) <= NlwRenamedSig_OI_block_ok(8);
  test_check_bl_ok(7) <= NlwRenamedSig_OI_block_ok(7);
  test_check_bl_ok(6) <= NlwRenamedSig_OI_block_ok(6);
  test_check_bl_ok(5) <= NlwRenamedSig_OI_block_ok(5);
  test_check_bl_ok(4) <= NlwRenamedSig_OI_block_ok(4);
  test_check_bl_ok(3) <= NlwRenamedSig_OI_block_ok(3);
  test_check_bl_ok(2) <= NlwRenamedSig_OI_block_ok(2);
  test_check_bl_ok(1) <= NlwRenamedSig_OI_block_ok(1);
  test_check_bl_ok(0) <= NlwRenamedSig_OI_block_ok(0);
  test_check_bl_rd(31) <= NlwRenamedSig_OI_block_rd(31);
  test_check_bl_rd(30) <= NlwRenamedSig_OI_block_rd(30);
  test_check_bl_rd(29) <= NlwRenamedSig_OI_block_rd(29);
  test_check_bl_rd(28) <= NlwRenamedSig_OI_block_rd(28);
  test_check_bl_rd(27) <= NlwRenamedSig_OI_block_rd(27);
  test_check_bl_rd(26) <= NlwRenamedSig_OI_block_rd(26);
  test_check_bl_rd(25) <= NlwRenamedSig_OI_block_rd(25);
  test_check_bl_rd(24) <= NlwRenamedSig_OI_block_rd(24);
  test_check_bl_rd(23) <= NlwRenamedSig_OI_block_rd(23);
  test_check_bl_rd(22) <= NlwRenamedSig_OI_block_rd(22);
  test_check_bl_rd(21) <= NlwRenamedSig_OI_block_rd(21);
  test_check_bl_rd(20) <= NlwRenamedSig_OI_block_rd(20);
  test_check_bl_rd(19) <= NlwRenamedSig_OI_block_rd(19);
  test_check_bl_rd(18) <= NlwRenamedSig_OI_block_rd(18);
  test_check_bl_rd(17) <= NlwRenamedSig_OI_block_rd(17);
  test_check_bl_rd(16) <= NlwRenamedSig_OI_block_rd(16);
  test_check_bl_rd(15) <= NlwRenamedSig_OI_block_rd(15);
  test_check_bl_rd(14) <= NlwRenamedSig_OI_block_rd(14);
  test_check_bl_rd(13) <= NlwRenamedSig_OI_block_rd(13);
  test_check_bl_rd(12) <= NlwRenamedSig_OI_block_rd(12);
  test_check_bl_rd(11) <= NlwRenamedSig_OI_block_rd(11);
  test_check_bl_rd(10) <= NlwRenamedSig_OI_block_rd(10);
  test_check_bl_rd(9) <= NlwRenamedSig_OI_block_rd(9);
  test_check_bl_rd(8) <= NlwRenamedSig_OI_block_rd(8);
  test_check_bl_rd(7) <= NlwRenamedSig_OI_block_rd(7);
  test_check_bl_rd(6) <= NlwRenamedSig_OI_block_rd(6);
  test_check_bl_rd(5) <= NlwRenamedSig_OI_block_rd(5);
  test_check_bl_rd(4) <= NlwRenamedSig_OI_block_rd(4);
  test_check_bl_rd(3) <= NlwRenamedSig_OI_block_rd(3);
  test_check_bl_rd(2) <= NlwRenamedSig_OI_block_rd(2);
  test_check_bl_rd(1) <= NlwRenamedSig_OI_block_rd(1);
  test_check_bl_rd(0) <= NlwRenamedSig_OI_block_rd(0);
  test_check_bl_err(31) <= NlwRenamedSig_OI_block_err(31);
  test_check_bl_err(30) <= NlwRenamedSig_OI_block_err(30);
  test_check_bl_err(29) <= NlwRenamedSig_OI_block_err(29);
  test_check_bl_err(28) <= NlwRenamedSig_OI_block_err(28);
  test_check_bl_err(27) <= NlwRenamedSig_OI_block_err(27);
  test_check_bl_err(26) <= NlwRenamedSig_OI_block_err(26);
  test_check_bl_err(25) <= NlwRenamedSig_OI_block_err(25);
  test_check_bl_err(24) <= NlwRenamedSig_OI_block_err(24);
  test_check_bl_err(23) <= NlwRenamedSig_OI_block_err(23);
  test_check_bl_err(22) <= NlwRenamedSig_OI_block_err(22);
  test_check_bl_err(21) <= NlwRenamedSig_OI_block_err(21);
  test_check_bl_err(20) <= NlwRenamedSig_OI_block_err(20);
  test_check_bl_err(19) <= NlwRenamedSig_OI_block_err(19);
  test_check_bl_err(18) <= NlwRenamedSig_OI_block_err(18);
  test_check_bl_err(17) <= NlwRenamedSig_OI_block_err(17);
  test_check_bl_err(16) <= NlwRenamedSig_OI_block_err(16);
  test_check_bl_err(15) <= NlwRenamedSig_OI_block_err(15);
  test_check_bl_err(14) <= NlwRenamedSig_OI_block_err(14);
  test_check_bl_err(13) <= NlwRenamedSig_OI_block_err(13);
  test_check_bl_err(12) <= NlwRenamedSig_OI_block_err(12);
  test_check_bl_err(11) <= NlwRenamedSig_OI_block_err(11);
  test_check_bl_err(10) <= NlwRenamedSig_OI_block_err(10);
  test_check_bl_err(9) <= NlwRenamedSig_OI_block_err(9);
  test_check_bl_err(8) <= NlwRenamedSig_OI_block_err(8);
  test_check_bl_err(7) <= NlwRenamedSig_OI_block_err(7);
  test_check_bl_err(6) <= NlwRenamedSig_OI_block_err(6);
  test_check_bl_err(5) <= NlwRenamedSig_OI_block_err(5);
  test_check_bl_err(4) <= NlwRenamedSig_OI_block_err(4);
  test_check_bl_err(3) <= NlwRenamedSig_OI_block_err(3);
  test_check_bl_err(2) <= NlwRenamedSig_OI_block_err(2);
  test_check_bl_err(1) <= NlwRenamedSig_OI_block_err(1);
  test_check_bl_err(0) <= NlwRenamedSig_OI_block_err(0);
  XST_GND : GND
    port map (
      G => data_error_153_Q
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  data_expect_3 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_3_mux0000,
      Q => data_expect(3)
    );
  data_ex3_0 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(63),
      Q => data_ex3(0)
    );
  data_ex3_1 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(62),
      Q => data_ex3(1)
    );
  data_ex3_2 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(61),
      Q => data_ex3(2)
    );
  data_ex3_3 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(60),
      Q => data_ex3(3)
    );
  data_ex3_4 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(59),
      Q => data_ex3(4)
    );
  data_ex3_5 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(58),
      Q => data_ex3(5)
    );
  data_ex3_6 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(57),
      Q => data_ex3(6)
    );
  data_ex3_7 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(56),
      Q => data_ex3(7)
    );
  data_ex3_8 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(55),
      Q => data_ex3(8)
    );
  data_ex3_9 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(54),
      Q => data_ex3(9)
    );
  data_ex3_10 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(53),
      Q => data_ex3(10)
    );
  data_ex3_11 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(52),
      Q => data_ex3(11)
    );
  data_ex3_12 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(51),
      Q => data_ex3(12)
    );
  data_ex3_13 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(50),
      Q => data_ex3(13)
    );
  data_ex3_14 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(49),
      Q => data_ex3(14)
    );
  data_ex3_15 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(48),
      Q => data_ex3(15)
    );
  data_ex3_16 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(47),
      Q => data_ex3(16)
    );
  data_ex3_17 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(46),
      Q => data_ex3(17)
    );
  data_ex3_18 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(45),
      Q => data_ex3(18)
    );
  data_ex3_19 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(44),
      Q => data_ex3(19)
    );
  data_ex3_20 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(43),
      Q => data_ex3(20)
    );
  data_ex3_21 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(42),
      Q => data_ex3(21)
    );
  data_ex3_22 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(41),
      Q => data_ex3(22)
    );
  data_ex3_23 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(40),
      Q => data_ex3(23)
    );
  data_ex3_24 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(39),
      Q => data_ex3(24)
    );
  data_ex3_25 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(38),
      Q => data_ex3(25)
    );
  data_ex3_26 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(37),
      Q => data_ex3(26)
    );
  data_ex3_27 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(36),
      Q => data_ex3(27)
    );
  data_ex3_28 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(35),
      Q => data_ex3(28)
    );
  data_ex3_29 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(34),
      Q => data_ex3(29)
    );
  data_ex3_30 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(33),
      Q => data_ex3(30)
    );
  data_ex3_31 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(32),
      Q => data_ex3(31)
    );
  data_ex3_32 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(31),
      Q => data_ex3(32)
    );
  data_ex3_33 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(30),
      Q => data_ex3(33)
    );
  data_ex3_34 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(29),
      Q => data_ex3(34)
    );
  data_ex3_35 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(28),
      Q => data_ex3(35)
    );
  data_ex3_36 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(27),
      Q => data_ex3(36)
    );
  data_ex3_37 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(26),
      Q => data_ex3(37)
    );
  data_ex3_38 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(25),
      Q => data_ex3(38)
    );
  data_ex3_39 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(24),
      Q => data_ex3(39)
    );
  data_ex3_40 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(23),
      Q => data_ex3(40)
    );
  data_ex3_41 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(22),
      Q => data_ex3(41)
    );
  data_ex3_42 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(21),
      Q => data_ex3(42)
    );
  data_ex3_43 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(20),
      Q => data_ex3(43)
    );
  data_ex3_44 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(19),
      Q => data_ex3(44)
    );
  data_ex3_45 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(18),
      Q => data_ex3(45)
    );
  data_ex3_46 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(17),
      Q => data_ex3(46)
    );
  data_ex3_47 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(16),
      Q => data_ex3(47)
    );
  data_ex3_48 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(15),
      Q => data_ex3(48)
    );
  data_ex3_49 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(14),
      Q => data_ex3(49)
    );
  data_ex3_50 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(13),
      Q => data_ex3(50)
    );
  data_ex3_51 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(12),
      Q => data_ex3(51)
    );
  data_ex3_52 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(11),
      Q => data_ex3(52)
    );
  data_ex3_53 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(10),
      Q => data_ex3(53)
    );
  data_ex3_54 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(9),
      Q => data_ex3(54)
    );
  data_ex3_55 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(8),
      Q => data_ex3(55)
    );
  data_ex3_56 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(7),
      Q => data_ex3(56)
    );
  data_ex3_57 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(6),
      Q => data_ex3(57)
    );
  data_ex3_58 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(5),
      Q => data_ex3(58)
    );
  data_ex3_59 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(4),
      Q => data_ex3(59)
    );
  data_ex3_60 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(3),
      Q => data_ex3(60)
    );
  data_ex3_61 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(2),
      Q => data_ex3(61)
    );
  data_ex3_62 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(1),
      Q => data_ex3(62)
    );
  data_ex3_63 : FDE
    port map (
      C => do_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(0),
      Q => data_ex3(63)
    );
  data_ex1_36 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_36_mux0000,
      Q => data_ex1(36)
    );
  data_ex1_41 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_41_mux0000,
      Q => data_ex1(41)
    );
  data_expect_4 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_4_mux0000,
      Q => data_expect(4)
    );
  data_expect_37 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_37_mux0000,
      Q => data_expect(37)
    );
  data_expect_42 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_42_mux0000,
      Q => data_expect(42)
    );
  data_ex1_37 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_37_mux0000,
      Q => data_ex1(37)
    );
  data_ex1_42 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_42_mux0000,
      Q => data_ex1(42)
    );
  data_expect_5 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_5_mux0000,
      Q => data_expect(5)
    );
  data_expect_38 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_38_mux0000,
      Q => data_expect(38)
    );
  data_expect_43 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_43_mux0000,
      Q => data_expect(43)
    );
  data_ex1_38 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_38_mux0000,
      Q => data_ex1(38)
    );
  data_ex1_43 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_43_mux0000,
      Q => data_ex1(43)
    );
  data_expect_44 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_44_mux0000,
      Q => data_expect(44)
    );
  data_ex0_0 : FDSE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_0_mux0000,
      S => rst_inv,
      Q => data_ex0(0)
    );
  data_expect_39 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_39_mux0000,
      Q => data_expect(39)
    );
  data_ex1_44 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_44_mux0000,
      Q => data_ex1(44)
    );
  data_expect_6 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_6_mux0000,
      Q => data_expect(6)
    );
  data_ex1_39 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_39_mux0000,
      Q => data_ex1(39)
    );
  data_expect_50 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_50_mux0000,
      Q => data_expect(50)
    );
  data_ex0_1 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_1_mux0000,
      R => rst_inv,
      Q => data_ex0(1)
    );
  data_expect_45 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_45_mux0000,
      Q => data_expect(45)
    );
  data_expect_7 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_7_mux0000,
      Q => data_expect(7)
    );
  data_ex1_45 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_45_mux0000,
      Q => data_ex1(45)
    );
  data_expect_46 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_46_mux0000,
      Q => data_expect(46)
    );
  data_ex1_50 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_50_mux0000,
      Q => data_ex1(50)
    );
  data_ex0_2 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_2_mux0000,
      R => rst_inv,
      Q => data_ex0(2)
    );
  data_expect_51 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_51_mux0000,
      Q => data_expect(51)
    );
  data_expect_8 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_8_mux0000,
      Q => data_expect(8)
    );
  data_ex0_3 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_3_mux0000,
      R => rst_inv,
      Q => data_ex0(3)
    );
  data_ex1_46 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_46_mux0000,
      Q => data_ex1(46)
    );
  data_ex1_51 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_51_mux0000,
      Q => data_ex1(51)
    );
  data_expect_47 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_47_mux0000,
      Q => data_expect(47)
    );
  data_expect_52 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_52_mux0000,
      Q => data_expect(52)
    );
  data_ex1_52 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_52_mux0000,
      Q => data_ex1(52)
    );
  data_expect_9 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_9_mux0000,
      Q => data_expect(9)
    );
  data_ex1_47 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_47_mux0000,
      Q => data_ex1(47)
    );
  data_ex0_4 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_4_mux0000,
      R => rst_inv,
      Q => data_ex0(4)
    );
  data_expect_48 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_48_mux0000,
      Q => data_expect(48)
    );
  data_ex1_53 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_53_mux0000,
      Q => data_ex1(53)
    );
  data_expect_53 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_53_mux0000,
      Q => data_expect(53)
    );
  data_ex1_48 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_48_mux0000,
      Q => data_ex1(48)
    );
  data_ex0_5 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_5_mux0000,
      R => rst_inv,
      Q => data_ex0(5)
    );
  data_expect_49 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_49_mux0000,
      Q => data_expect(49)
    );
  data_ex1_54 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_54_mux0000,
      Q => data_ex1(54)
    );
  data_expect_54 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_54_mux0000,
      Q => data_expect(54)
    );
  data_ex1_49 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_49_mux0000,
      Q => data_ex1(49)
    );
  data_ex0_6 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_6_mux0000,
      R => rst_inv,
      Q => data_ex0(6)
    );
  data_expect_55 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_55_mux0000,
      Q => data_expect(55)
    );
  data_ex1_60 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_60_mux0000,
      Q => data_ex1(60)
    );
  data_expect_60 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_60_mux0000,
      Q => data_expect(60)
    );
  data_ex1_55 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_55_mux0000,
      Q => data_ex1(55)
    );
  data_ex0_7 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_7_mux0000,
      R => rst_inv,
      Q => data_ex0(7)
    );
  data_expect_56 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_56_mux0000,
      Q => data_expect(56)
    );
  data_ex1_61 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_61_mux0000,
      Q => data_ex1(61)
    );
  data_expect_61 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_61_mux0000,
      Q => data_expect(61)
    );
  data_ex1_56 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_56_mux0000,
      Q => data_ex1(56)
    );
  data_expect_62 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_62_mux0000,
      Q => data_expect(62)
    );
  data_ex0_8 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_8_mux0000,
      R => rst_inv,
      Q => data_ex0(8)
    );
  data_expect_57 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_57_mux0000,
      Q => data_expect(57)
    );
  data_ex0_9 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_9_mux0000,
      R => rst_inv,
      Q => data_ex0(9)
    );
  data_ex1_57 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_57_mux0000,
      Q => data_ex1(57)
    );
  data_ex1_62 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_62_mux0000,
      Q => data_ex1(62)
    );
  data_expect_58 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_58_mux0000,
      Q => data_expect(58)
    );
  data_expect_63 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_63_mux0000,
      Q => data_expect(63)
    );
  data_expect_59 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_59_mux0000,
      Q => data_expect(59)
    );
  data_ex1_58 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_58_mux0000,
      Q => data_ex1(58)
    );
  data_ex1_63 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_63_mux0000,
      Q => data_ex1(63)
    );
  data_ex0_10 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_10_mux0000,
      R => rst_inv,
      Q => data_ex0(10)
    );
  data_ex1_59 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_59_mux0000,
      Q => data_ex1(59)
    );
  data_ex0_13 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_13_mux0000,
      R => rst_inv,
      Q => data_ex0(13)
    );
  data_ex0_11 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_11_mux0000,
      R => rst_inv,
      Q => data_ex0(11)
    );
  data_ex0_12 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_12_mux0000,
      R => rst_inv,
      Q => data_ex0(12)
    );
  data_ex0_14 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_14_mux0000,
      R => rst_inv,
      Q => data_ex0(14)
    );
  data_ex0_20 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_20_mux0000,
      R => rst_inv,
      Q => data_ex0(20)
    );
  data_ex0_21 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_21_mux0000,
      R => rst_inv,
      Q => data_ex0(21)
    );
  data_ex0_15 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_15_mux0000,
      R => rst_inv,
      Q => data_ex0(15)
    );
  data_en_z : FD
    port map (
      C => do_clk,
      D => do_data_en,
      Q => data_en_z_3400
    );
  data_ex0_16 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_16_mux0000,
      R => rst_inv,
      Q => data_ex0(16)
    );
  data_ex0_22 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_22_mux0000,
      R => rst_inv,
      Q => data_ex0(22)
    );
  data_ex0_18 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_18_mux0000,
      R => rst_inv,
      Q => data_ex0(18)
    );
  data_ex0_17 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_17_mux0000,
      R => rst_inv,
      Q => data_ex0(17)
    );
  data_ex0_23 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_23_mux0000,
      R => rst_inv,
      Q => data_ex0(23)
    );
  data_ex0_24 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_24_mux0000,
      R => rst_inv,
      Q => data_ex0(24)
    );
  data_ex0_19 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_19_mux0000,
      R => rst_inv,
      Q => data_ex0(19)
    );
  data_ex0_30 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_30_mux0000,
      R => rst_inv,
      Q => data_ex0(30)
    );
  data_ex0_25 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_25_mux0000,
      R => rst_inv,
      Q => data_ex0(25)
    );
  data_ex5_11 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(10),
      R => rst_inv,
      Q => data_ex5(11)
    );
  data_ex0_31 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_31_mux0000,
      R => rst_inv,
      Q => data_ex0(31)
    );
  data_ex0_32 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_32_mux0000,
      R => rst_inv,
      Q => data_ex0(32)
    );
  data_ex0_26 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_26_mux0000,
      R => rst_inv,
      Q => data_ex0(26)
    );
  data_ex0_27 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_27_mux0000,
      R => rst_inv,
      Q => data_ex0(27)
    );
  data_ex0_33 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_33_mux0000,
      R => rst_inv,
      Q => data_ex0(33)
    );
  data_ex0_28 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_28_mux0000,
      R => rst_inv,
      Q => data_ex0(28)
    );
  data_ex1_0 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_0_mux0000,
      Q => data_ex1(0)
    );
  data_ex0_34 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_34_mux0000,
      R => rst_inv,
      Q => data_ex0(34)
    );
  data_ex0_29 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_29_mux0000,
      R => rst_inv,
      Q => data_ex0(29)
    );
  data_ex0_40 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_40_mux0000,
      R => rst_inv,
      Q => data_ex0(40)
    );
  data_ex0_35 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_35_mux0000,
      R => rst_inv,
      Q => data_ex0(35)
    );
  data_ex1_1 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_1_mux0000,
      Q => data_ex1(1)
    );
  data_ex0_41 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_41_mux0000,
      R => rst_inv,
      Q => data_ex0(41)
    );
  data_ex0_36 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_36_mux0000,
      R => rst_inv,
      Q => data_ex0(36)
    );
  data_ex1_2 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_2_mux0000,
      Q => data_ex1(2)
    );
  data_ex0_37 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_37_mux0000,
      R => rst_inv,
      Q => data_ex0(37)
    );
  data_ex0_42 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_42_mux0000,
      R => rst_inv,
      Q => data_ex0(42)
    );
  data_ex1_3 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_3_mux0000,
      Q => data_ex1(3)
    );
  data_ex0_43 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_43_mux0000,
      R => rst_inv,
      Q => data_ex0(43)
    );
  data_ex0_38 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_38_mux0000,
      R => rst_inv,
      Q => data_ex0(38)
    );
  data_ex1_4 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_4_mux0000,
      Q => data_ex1(4)
    );
  data_ex1_5 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_5_mux0000,
      Q => data_ex1(5)
    );
  data_ex0_44 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_44_mux0000,
      R => rst_inv,
      Q => data_ex0(44)
    );
  data_ex0_39 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_39_mux0000,
      R => rst_inv,
      Q => data_ex0(39)
    );
  data_ex0_50 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_50_mux0000,
      R => rst_inv,
      Q => data_ex0(50)
    );
  data_ex0_45 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_45_mux0000,
      R => rst_inv,
      Q => data_ex0(45)
    );
  data_ex1_6 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_6_mux0000,
      Q => data_ex1(6)
    );
  data_ex0_46 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_46_mux0000,
      R => rst_inv,
      Q => data_ex0(46)
    );
  data_ex0_51 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_51_mux0000,
      R => rst_inv,
      Q => data_ex0(51)
    );
  data_ex1_7 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_7_mux0000,
      Q => data_ex1(7)
    );
  data_ex1_8 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_8_mux0000,
      Q => data_ex1(8)
    );
  data_ex0_52 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_52_mux0000,
      R => rst_inv,
      Q => data_ex0(52)
    );
  data_ex0_47 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_47_mux0000,
      R => rst_inv,
      Q => data_ex0(47)
    );
  data_ex0_53 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_53_mux0000,
      R => rst_inv,
      Q => data_ex0(53)
    );
  data_ex0_48 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_48_mux0000,
      R => rst_inv,
      Q => data_ex0(48)
    );
  data_ex1_9 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_9_mux0000,
      Q => data_ex1(9)
    );
  data_ex0_49 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_49_mux0000,
      R => rst_inv,
      Q => data_ex0(49)
    );
  data_ex0_54 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_54_mux0000,
      R => rst_inv,
      Q => data_ex0(54)
    );
  data_ex0_60 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_60_mux0000,
      R => rst_inv,
      Q => data_ex0(60)
    );
  data_ex0_55 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_55_mux0000,
      R => rst_inv,
      Q => data_ex0(55)
    );
  data_ex0_61 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_61_mux0000,
      R => rst_inv,
      Q => data_ex0(61)
    );
  data_ex0_56 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_56_mux0000,
      R => rst_inv,
      Q => data_ex0(56)
    );
  data_ex0_57 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_57_mux0000,
      R => rst_inv,
      Q => data_ex0(57)
    );
  data_ex0_62 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_62_mux0000,
      R => rst_inv,
      Q => data_ex0(62)
    );
  data_ex0_58 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_58_mux0000,
      R => rst_inv,
      Q => data_ex0(58)
    );
  data_ex0_63 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_63_mux0000,
      R => rst_inv,
      Q => data_ex0(63)
    );
  data_ex0_59 : FDRE
    port map (
      C => do_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_59_mux0000,
      R => rst_inv,
      Q => data_ex0(59)
    );
  data_ex2_0 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_0_mux0000,
      Q => data_ex2(0)
    );
  data_ex4_11 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(11),
      R => rst_inv,
      Q => data_ex4(11)
    );
  data_ex4_12 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(12),
      R => rst_inv,
      Q => data_ex4(12)
    );
  data_ex2_1 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_1_mux0000,
      Q => data_ex2(1)
    );
  data_ex2_2 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_2_mux0000,
      Q => data_ex2(2)
    );
  data_ex4_13 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(13),
      R => rst_inv,
      Q => data_ex4(13)
    );
  data_ex2_3 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_3_mux0000,
      Q => data_ex2(3)
    );
  data_ex4_14 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(14),
      R => rst_inv,
      Q => data_ex4(14)
    );
  data_ex2_4 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_4_mux0000,
      Q => data_ex2(4)
    );
  data_ex4_20 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(20),
      R => rst_inv,
      Q => data_ex4(20)
    );
  data_ex4_15 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(15),
      R => rst_inv,
      Q => data_ex4(15)
    );
  data_ex2_5 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_5_mux0000,
      Q => data_ex2(5)
    );
  data_ex4_21 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(21),
      R => rst_inv,
      Q => data_ex4(21)
    );
  data_ex4_16 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(16),
      R => rst_inv,
      Q => data_ex4(16)
    );
  data_ex2_6 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_6_mux0000,
      Q => data_ex2(6)
    );
  data_ex4_22 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(22),
      R => rst_inv,
      Q => data_ex4(22)
    );
  data_ex4_17 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(17),
      R => rst_inv,
      Q => data_ex4(17)
    );
  data_ex2_7 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_7_mux0000,
      Q => data_ex2(7)
    );
  data_ex4_23 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(23),
      R => rst_inv,
      Q => data_ex4(23)
    );
  data_ex4_18 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(18),
      R => rst_inv,
      Q => data_ex4(18)
    );
  data_ex4_24 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(24),
      R => rst_inv,
      Q => data_ex4(24)
    );
  data_ex2_8 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_8_mux0000,
      Q => data_ex2(8)
    );
  data_ex4_19 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(19),
      R => rst_inv,
      Q => data_ex4(19)
    );
  data_ex2_9 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_9_mux0000,
      Q => data_ex2(9)
    );
  data_ex4_30 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(30),
      R => rst_inv,
      Q => data_ex4(30)
    );
  data_ex4_25 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(25),
      R => rst_inv,
      Q => data_ex4(25)
    );
  data_ex4_31 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(31),
      R => rst_inv,
      Q => data_ex4(31)
    );
  data_ex4_26 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(26),
      R => rst_inv,
      Q => data_ex4(26)
    );
  data_ex4_27 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(27),
      R => rst_inv,
      Q => data_ex4(27)
    );
  data_ex4_33 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(1),
      R => rst_inv,
      Q => data_ex4(33)
    );
  data_ex4_29 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(29),
      R => rst_inv,
      Q => data_ex4(29)
    );
  data_ex4_28 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(28),
      R => rst_inv,
      Q => data_ex4(28)
    );
  data_ex4_34 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(2),
      R => rst_inv,
      Q => data_ex4(34)
    );
  data_ex4_40 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(8),
      R => rst_inv,
      Q => data_ex4(40)
    );
  data_ex4_35 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(3),
      R => rst_inv,
      Q => data_ex4(35)
    );
  data_ex4_42 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(10),
      R => rst_inv,
      Q => data_ex4(42)
    );
  data_ex4_41 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(9),
      R => rst_inv,
      Q => data_ex4(41)
    );
  data_ex4_36 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(4),
      R => rst_inv,
      Q => data_ex4(36)
    );
  data_ex4_37 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(5),
      R => rst_inv,
      Q => data_ex4(37)
    );
  data_ex4_43 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(11),
      R => rst_inv,
      Q => data_ex4(43)
    );
  data_ex4_39 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(7),
      R => rst_inv,
      Q => data_ex4(39)
    );
  data_ex4_38 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(6),
      R => rst_inv,
      Q => data_ex4(38)
    );
  data_ex4_44 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(12),
      R => rst_inv,
      Q => data_ex4(44)
    );
  data_ex4_50 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(18),
      R => rst_inv,
      Q => data_ex4(50)
    );
  data_ex4_51 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(19),
      R => rst_inv,
      Q => data_ex4(51)
    );
  data_ex4_45 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(13),
      R => rst_inv,
      Q => data_ex4(45)
    );
  flag_error_clr : FDR
    port map (
      C => do_clk,
      D => N1,
      R => data_ex3_not0001_inv,
      Q => flag_error_clr_4749
    );
  data_ex4_46 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(14),
      R => rst_inv,
      Q => data_ex4(46)
    );
  data_ex4_52 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(20),
      R => rst_inv,
      Q => data_ex4(52)
    );
  data_ex4_53 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(21),
      R => rst_inv,
      Q => data_ex4(53)
    );
  data_ex4_47 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(15),
      R => rst_inv,
      Q => data_ex4(47)
    );
  data_ex4_49 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(17),
      R => rst_inv,
      Q => data_ex4(49)
    );
  data_ex4_48 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(16),
      R => rst_inv,
      Q => data_ex4(48)
    );
  data_ex4_54 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(22),
      R => rst_inv,
      Q => data_ex4(54)
    );
  data_ex4_60 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(28),
      R => rst_inv,
      Q => data_ex4(60)
    );
  data_ex4_55 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(23),
      R => rst_inv,
      Q => data_ex4(55)
    );
  data_ex4_61 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(29),
      R => rst_inv,
      Q => data_ex4(61)
    );
  data_ex4_56 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(24),
      R => rst_inv,
      Q => data_ex4(56)
    );
  data_ex4_63 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(31),
      R => rst_inv,
      Q => data_ex4(63)
    );
  data_ex4_62 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(30),
      R => rst_inv,
      Q => data_ex4(62)
    );
  data_ex4_57 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(25),
      R => rst_inv,
      Q => data_ex4(57)
    );
  data_ex4_58 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(26),
      R => rst_inv,
      Q => data_ex4(58)
    );
  data_ex4_59 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(27),
      R => rst_inv,
      Q => data_ex4(59)
    );
  data_ex4_0 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(0),
      R => rst_inv,
      Q => data_ex4(0)
    );
  do_data_z_0 : FD
    port map (
      C => do_clk,
      D => do_data(0),
      Q => do_data_z(0)
    );
  do_data_z_1 : FD
    port map (
      C => do_clk,
      D => do_data(1),
      Q => do_data_z(1)
    );
  do_data_z_2 : FD
    port map (
      C => do_clk,
      D => do_data(2),
      Q => do_data_z(2)
    );
  do_data_z_3 : FD
    port map (
      C => do_clk,
      D => do_data(3),
      Q => do_data_z(3)
    );
  do_data_z_4 : FD
    port map (
      C => do_clk,
      D => do_data(4),
      Q => do_data_z(4)
    );
  do_data_z_5 : FD
    port map (
      C => do_clk,
      D => do_data(5),
      Q => do_data_z(5)
    );
  do_data_z_6 : FD
    port map (
      C => do_clk,
      D => do_data(6),
      Q => do_data_z(6)
    );
  do_data_z_7 : FD
    port map (
      C => do_clk,
      D => do_data(7),
      Q => do_data_z(7)
    );
  do_data_z_8 : FD
    port map (
      C => do_clk,
      D => do_data(8),
      Q => do_data_z(8)
    );
  do_data_z_9 : FD
    port map (
      C => do_clk,
      D => do_data(9),
      Q => do_data_z(9)
    );
  do_data_z_10 : FD
    port map (
      C => do_clk,
      D => do_data(10),
      Q => do_data_z(10)
    );
  do_data_z_11 : FD
    port map (
      C => do_clk,
      D => do_data(11),
      Q => do_data_z(11)
    );
  do_data_z_12 : FD
    port map (
      C => do_clk,
      D => do_data(12),
      Q => do_data_z(12)
    );
  do_data_z_13 : FD
    port map (
      C => do_clk,
      D => do_data(13),
      Q => do_data_z(13)
    );
  do_data_z_14 : FD
    port map (
      C => do_clk,
      D => do_data(14),
      Q => do_data_z(14)
    );
  do_data_z_15 : FD
    port map (
      C => do_clk,
      D => do_data(15),
      Q => do_data_z(15)
    );
  do_data_z_16 : FD
    port map (
      C => do_clk,
      D => do_data(16),
      Q => do_data_z(16)
    );
  do_data_z_17 : FD
    port map (
      C => do_clk,
      D => do_data(17),
      Q => do_data_z(17)
    );
  do_data_z_18 : FD
    port map (
      C => do_clk,
      D => do_data(18),
      Q => do_data_z(18)
    );
  do_data_z_19 : FD
    port map (
      C => do_clk,
      D => do_data(19),
      Q => do_data_z(19)
    );
  do_data_z_20 : FD
    port map (
      C => do_clk,
      D => do_data(20),
      Q => do_data_z(20)
    );
  do_data_z_21 : FD
    port map (
      C => do_clk,
      D => do_data(21),
      Q => do_data_z(21)
    );
  do_data_z_22 : FD
    port map (
      C => do_clk,
      D => do_data(22),
      Q => do_data_z(22)
    );
  do_data_z_23 : FD
    port map (
      C => do_clk,
      D => do_data(23),
      Q => do_data_z(23)
    );
  do_data_z_24 : FD
    port map (
      C => do_clk,
      D => do_data(24),
      Q => do_data_z(24)
    );
  do_data_z_25 : FD
    port map (
      C => do_clk,
      D => do_data(25),
      Q => do_data_z(25)
    );
  do_data_z_26 : FD
    port map (
      C => do_clk,
      D => do_data(26),
      Q => do_data_z(26)
    );
  do_data_z_27 : FD
    port map (
      C => do_clk,
      D => do_data(27),
      Q => do_data_z(27)
    );
  do_data_z_28 : FD
    port map (
      C => do_clk,
      D => do_data(28),
      Q => do_data_z(28)
    );
  do_data_z_29 : FD
    port map (
      C => do_clk,
      D => do_data(29),
      Q => do_data_z(29)
    );
  do_data_z_30 : FD
    port map (
      C => do_clk,
      D => do_data(30),
      Q => do_data_z(30)
    );
  do_data_z_31 : FD
    port map (
      C => do_clk,
      D => do_data(31),
      Q => do_data_z(31)
    );
  do_data_z_32 : FD
    port map (
      C => do_clk,
      D => do_data(32),
      Q => do_data_z(32)
    );
  do_data_z_33 : FD
    port map (
      C => do_clk,
      D => do_data(33),
      Q => do_data_z(33)
    );
  do_data_z_34 : FD
    port map (
      C => do_clk,
      D => do_data(34),
      Q => do_data_z(34)
    );
  do_data_z_35 : FD
    port map (
      C => do_clk,
      D => do_data(35),
      Q => do_data_z(35)
    );
  do_data_z_36 : FD
    port map (
      C => do_clk,
      D => do_data(36),
      Q => do_data_z(36)
    );
  do_data_z_37 : FD
    port map (
      C => do_clk,
      D => do_data(37),
      Q => do_data_z(37)
    );
  do_data_z_38 : FD
    port map (
      C => do_clk,
      D => do_data(38),
      Q => do_data_z(38)
    );
  do_data_z_39 : FD
    port map (
      C => do_clk,
      D => do_data(39),
      Q => do_data_z(39)
    );
  do_data_z_40 : FD
    port map (
      C => do_clk,
      D => do_data(40),
      Q => do_data_z(40)
    );
  do_data_z_41 : FD
    port map (
      C => do_clk,
      D => do_data(41),
      Q => do_data_z(41)
    );
  do_data_z_42 : FD
    port map (
      C => do_clk,
      D => do_data(42),
      Q => do_data_z(42)
    );
  do_data_z_43 : FD
    port map (
      C => do_clk,
      D => do_data(43),
      Q => do_data_z(43)
    );
  do_data_z_44 : FD
    port map (
      C => do_clk,
      D => do_data(44),
      Q => do_data_z(44)
    );
  do_data_z_45 : FD
    port map (
      C => do_clk,
      D => do_data(45),
      Q => do_data_z(45)
    );
  do_data_z_46 : FD
    port map (
      C => do_clk,
      D => do_data(46),
      Q => do_data_z(46)
    );
  do_data_z_47 : FD
    port map (
      C => do_clk,
      D => do_data(47),
      Q => do_data_z(47)
    );
  do_data_z_48 : FD
    port map (
      C => do_clk,
      D => do_data(48),
      Q => do_data_z(48)
    );
  do_data_z_49 : FD
    port map (
      C => do_clk,
      D => do_data(49),
      Q => do_data_z(49)
    );
  do_data_z_50 : FD
    port map (
      C => do_clk,
      D => do_data(50),
      Q => do_data_z(50)
    );
  do_data_z_51 : FD
    port map (
      C => do_clk,
      D => do_data(51),
      Q => do_data_z(51)
    );
  do_data_z_52 : FD
    port map (
      C => do_clk,
      D => do_data(52),
      Q => do_data_z(52)
    );
  do_data_z_53 : FD
    port map (
      C => do_clk,
      D => do_data(53),
      Q => do_data_z(53)
    );
  do_data_z_54 : FD
    port map (
      C => do_clk,
      D => do_data(54),
      Q => do_data_z(54)
    );
  do_data_z_55 : FD
    port map (
      C => do_clk,
      D => do_data(55),
      Q => do_data_z(55)
    );
  do_data_z_56 : FD
    port map (
      C => do_clk,
      D => do_data(56),
      Q => do_data_z(56)
    );
  do_data_z_57 : FD
    port map (
      C => do_clk,
      D => do_data(57),
      Q => do_data_z(57)
    );
  do_data_z_58 : FD
    port map (
      C => do_clk,
      D => do_data(58),
      Q => do_data_z(58)
    );
  do_data_z_59 : FD
    port map (
      C => do_clk,
      D => do_data(59),
      Q => do_data_z(59)
    );
  do_data_z_60 : FD
    port map (
      C => do_clk,
      D => do_data(60),
      Q => do_data_z(60)
    );
  do_data_z_61 : FD
    port map (
      C => do_clk,
      D => do_data(61),
      Q => do_data_z(61)
    );
  do_data_z_62 : FD
    port map (
      C => do_clk,
      D => do_data(62),
      Q => do_data_z(62)
    );
  do_data_z_63 : FD
    port map (
      C => do_clk,
      D => do_data(63),
      Q => do_data_z(63)
    );
  data_error_ovr : FDRE
    port map (
      C => do_clk,
      CE => data_error_ovr_and0000,
      D => N1,
      R => rst_inv,
      Q => data_error_ovr_3651
    );
  data_ex4_1 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(1),
      R => rst_inv,
      Q => data_ex4(1)
    );
  data_ex4_2 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(2),
      R => rst_inv,
      Q => data_ex4(2)
    );
  data_ex4_4 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(4),
      R => rst_inv,
      Q => data_ex4(4)
    );
  cnt1_eq : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => cnt1_eq_and0000_3396,
      R => rst_inv,
      Q => cnt1_eq_3379
    );
  data_ex4_3 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(3),
      R => rst_inv,
      Q => data_ex4(3)
    );
  data_ex4_5 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(5),
      R => rst_inv,
      Q => data_ex4(5)
    );
  data_ex4_6 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(6),
      R => rst_inv,
      Q => data_ex4(6)
    );
  data_ex4_8 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(8),
      R => rst_inv,
      Q => data_ex4(8)
    );
  data_ex4_7 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(7),
      R => rst_inv,
      Q => data_ex4(7)
    );
  data_ex2_10 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_10_mux0000,
      Q => data_ex2(10)
    );
  data_ex2_11 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_11_mux0000,
      Q => data_ex2(11)
    );
  data_ex4_9 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(9),
      R => rst_inv,
      Q => data_ex4(9)
    );
  data_ex2_14 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_14_mux0000,
      Q => data_ex2(14)
    );
  data_ex2_12 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_12_mux0000,
      Q => data_ex2(12)
    );
  data_ex2_13 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_13_mux0000,
      Q => data_ex2(13)
    );
  data_ex2_20 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_20_mux0000,
      Q => data_ex2(20)
    );
  data_ex2_15 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_15_mux0000,
      Q => data_ex2(15)
    );
  data_ex2_22 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_22_mux0000,
      Q => data_ex2(22)
    );
  data_ex2_21 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_21_mux0000,
      Q => data_ex2(21)
    );
  data_ex2_16 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_16_mux0000,
      Q => data_ex2(16)
    );
  data_ex2_17 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_17_mux0000,
      Q => data_ex2(17)
    );
  data_ex2_23 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_23_mux0000,
      Q => data_ex2(23)
    );
  data_ex2_19 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_19_mux0000,
      Q => data_ex2(19)
    );
  data_ex2_18 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_18_mux0000,
      Q => data_ex2(18)
    );
  data_ex2_24 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_24_mux0000,
      Q => data_ex2(24)
    );
  data_ex2_31 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_31_mux0000,
      Q => data_ex2(31)
    );
  data_ex2_30 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_30_mux0000,
      Q => data_ex2(30)
    );
  data_ex2_25 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_25_mux0000,
      Q => data_ex2(25)
    );
  data_ex2_27 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_27_mux0000,
      Q => data_ex2(27)
    );
  data_ex2_26 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_26_mux0000,
      Q => data_ex2(26)
    );
  data_ex2_32 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_32_mux0000,
      Q => data_ex2(32)
    );
  data_ex2_33 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_33_mux0000,
      Q => data_ex2(33)
    );
  data_ex2_28 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_28_mux0000,
      Q => data_ex2(28)
    );
  data_ex2_40 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_40_mux0000,
      Q => data_ex2(40)
    );
  data_ex2_34 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_34_mux0000,
      Q => data_ex2(34)
    );
  data_ex2_29 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_29_mux0000,
      Q => data_ex2(29)
    );
  data_ex2_35 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_35_mux0000,
      Q => data_ex2(35)
    );
  data_ex2_36 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_36_mux0000,
      Q => data_ex2(36)
    );
  data_ex2_42 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_42_mux0000,
      Q => data_ex2(42)
    );
  data_ex2_41 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_41_mux0000,
      Q => data_ex2(41)
    );
  data_ex2_37 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_37_mux0000,
      Q => data_ex2(37)
    );
  data_ex2_38 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_38_mux0000,
      Q => data_ex2(38)
    );
  data_ex2_39 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_39_mux0000,
      Q => data_ex2(39)
    );
  data_ex2_43 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_43_mux0000,
      Q => data_ex2(43)
    );
  data_ex2_44 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_44_mux0000,
      Q => data_ex2(44)
    );
  data_ex2_45 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_45_mux0000,
      Q => data_ex2(45)
    );
  data_ex2_50 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_50_mux0000,
      Q => data_ex2(50)
    );
  data_ex2_51 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_51_mux0000,
      Q => data_ex2(51)
    );
  data_ex2_46 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_46_mux0000,
      Q => data_ex2(46)
    );
  data_ex2_52 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_52_mux0000,
      Q => data_ex2(52)
    );
  data_ex2_47 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_47_mux0000,
      Q => data_ex2(47)
    );
  data_ex2_53 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_53_mux0000,
      Q => data_ex2(53)
    );
  data_ex2_48 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_48_mux0000,
      Q => data_ex2(48)
    );
  data_ex2_54 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_54_mux0000,
      Q => data_ex2(54)
    );
  data_ex2_49 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_49_mux0000,
      Q => data_ex2(49)
    );
  data_ex2_55 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_55_mux0000,
      Q => data_ex2(55)
    );
  data_ex2_60 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_60_mux0000,
      Q => data_ex2(60)
    );
  data_ex2_61 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_61_mux0000,
      Q => data_ex2(61)
    );
  data_ex2_62 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_62_mux0000,
      Q => data_ex2(62)
    );
  data_ex2_56 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_56_mux0000,
      Q => data_ex2(56)
    );
  data_ex2_57 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_57_mux0000,
      Q => data_ex2(57)
    );
  data_expect_10 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_10_mux0000,
      Q => data_expect(10)
    );
  data_expect_11 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_11_mux0000,
      Q => data_expect(11)
    );
  data_ex2_63 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_63_mux0000,
      Q => data_ex2(63)
    );
  data_ex2_58 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_58_mux0000,
      Q => data_ex2(58)
    );
  data_ex1_10 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_10_mux0000,
      Q => data_ex1(10)
    );
  data_ex2_59 : FDE
    port map (
      C => do_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_59_mux0000,
      Q => data_ex2(59)
    );
  data_expect_13 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_13_mux0000,
      Q => data_expect(13)
    );
  data_expect_12 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_12_mux0000,
      Q => data_expect(12)
    );
  data_ex1_11 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_11_mux0000,
      Q => data_ex1(11)
    );
  data_ex1_12 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_12_mux0000,
      Q => data_ex1(12)
    );
  data_expect_14 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_14_mux0000,
      Q => data_expect(14)
    );
  data_expect_15 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_15_mux0000,
      Q => data_expect(15)
    );
  data_ex1_13 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_13_mux0000,
      Q => data_ex1(13)
    );
  data_expect_20 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_20_mux0000,
      Q => data_expect(20)
    );
  data_ex1_14 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_14_mux0000,
      Q => data_ex1(14)
    );
  data_expect_21 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_21_mux0000,
      Q => data_expect(21)
    );
  data_ex1_15 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_15_mux0000,
      Q => data_ex1(15)
    );
  data_expect_16 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_16_mux0000,
      Q => data_expect(16)
    );
  data_ex1_20 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_20_mux0000,
      Q => data_ex1(20)
    );
  data_expect_22 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_22_mux0000,
      Q => data_expect(22)
    );
  data_ex1_16 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_16_mux0000,
      Q => data_ex1(16)
    );
  data_expect_17 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_17_mux0000,
      Q => data_expect(17)
    );
  data_ex1_21 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_21_mux0000,
      Q => data_ex1(21)
    );
  data_expect_23 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_23_mux0000,
      Q => data_expect(23)
    );
  data_expect_18 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_18_mux0000,
      Q => data_expect(18)
    );
  data_expect_24 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_24_mux0000,
      Q => data_expect(24)
    );
  data_ex1_22 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_22_mux0000,
      Q => data_ex1(22)
    );
  data_ex1_17 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_17_mux0000,
      Q => data_ex1(17)
    );
  data_expect_19 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_19_mux0000,
      Q => data_expect(19)
    );
  data_ex1_23 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_23_mux0000,
      Q => data_ex1(23)
    );
  data_expect_25 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_25_mux0000,
      Q => data_expect(25)
    );
  data_ex1_18 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_18_mux0000,
      Q => data_ex1(18)
    );
  data_expect_30 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_30_mux0000,
      Q => data_expect(30)
    );
  data_expect_26 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_26_mux0000,
      Q => data_expect(26)
    );
  data_ex1_24 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_24_mux0000,
      Q => data_ex1(24)
    );
  data_ex1_19 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_19_mux0000,
      Q => data_ex1(19)
    );
  data_ex1_25 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_25_mux0000,
      Q => data_ex1(25)
    );
  data_expect_31 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_31_mux0000,
      Q => data_expect(31)
    );
  data_ex1_30 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_30_mux0000,
      Q => data_ex1(30)
    );
  data_expect_32 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_32_mux0000,
      Q => data_expect(32)
    );
  data_expect_27 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_27_mux0000,
      Q => data_expect(27)
    );
  data_expect_33 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_33_mux0000,
      Q => data_expect(33)
    );
  data_ex1_31 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_31_mux0000,
      Q => data_ex1(31)
    );
  data_ex1_26 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_26_mux0000,
      Q => data_ex1(26)
    );
  data_expect_28 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_28_mux0000,
      Q => data_expect(28)
    );
  data_ex1_32 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_32_mux0000,
      Q => data_ex1(32)
    );
  data_expect_34 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_34_mux0000,
      Q => data_expect(34)
    );
  data_ex1_27 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_27_mux0000,
      Q => data_ex1(27)
    );
  data_expect_0 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_0_mux0000,
      Q => data_expect(0)
    );
  data_expect_29 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_29_mux0000,
      Q => data_expect(29)
    );
  data_ex1_33 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_33_mux0000,
      Q => data_ex1(33)
    );
  data_expect_35 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_35_mux0000,
      Q => data_expect(35)
    );
  data_ex1_28 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_28_mux0000,
      Q => data_ex1(28)
    );
  data_expect_1 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_1_mux0000,
      Q => data_expect(1)
    );
  data_expect_40 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_40_mux0000,
      Q => data_expect(40)
    );
  data_ex1_34 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_34_mux0000,
      Q => data_ex1(34)
    );
  data_expect_36 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_36_mux0000,
      Q => data_expect(36)
    );
  data_ex1_29 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_29_mux0000,
      Q => data_ex1(29)
    );
  data_expect_2 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_2_mux0000,
      Q => data_expect(2)
    );
  data_expect_41 : FDE
    port map (
      C => do_clk,
      CE => data_expect_3_not0001,
      D => data_expect_41_mux0000,
      Q => data_expect(41)
    );
  data_ex1_40 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_40_mux0000,
      Q => data_ex1(40)
    );
  data_ex1_35 : FDE
    port map (
      C => do_clk,
      CE => data_ex1_36_not0001_3845,
      D => data_ex1_35_mux0000,
      Q => data_ex1(35)
    );
  data_ex5_12 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(11),
      R => rst_inv,
      Q => data_ex5(12)
    );
  data_error_130 : FD
    port map (
      C => do_clk,
      D => cnt1(2),
      Q => data_error_130_Q
    );
  data_error_131 : FD
    port map (
      C => do_clk,
      D => cnt1(3),
      Q => data_error_131_Q
    );
  data_error_132 : FD
    port map (
      C => do_clk,
      D => cnt1(4),
      Q => data_error_132_Q
    );
  data_error_133 : FD
    port map (
      C => do_clk,
      D => cnt1(5),
      Q => data_error_133_Q
    );
  data_error_128 : FD
    port map (
      C => do_clk,
      D => cnt1(0),
      Q => data_error_128_Q
    );
  data_error_134 : FD
    port map (
      C => do_clk,
      D => cnt1(6),
      Q => data_error_134_Q
    );
  data_error_129 : FD
    port map (
      C => do_clk,
      D => cnt1(1),
      Q => data_error_129_Q
    );
  data_error_135 : FD
    port map (
      C => do_clk,
      D => cnt1(7),
      Q => data_error_135_Q
    );
  data_error_140 : FD
    port map (
      C => do_clk,
      D => cnt1(12),
      Q => data_error_140_Q
    );
  data_error_141 : FD
    port map (
      C => do_clk,
      D => cnt1(13),
      Q => data_error_141_Q
    );
  data_error_136 : FD
    port map (
      C => do_clk,
      D => cnt1(8),
      Q => data_error_136_Q
    );
  data_error_142 : FD
    port map (
      C => do_clk,
      D => cnt1(14),
      Q => data_error_142_Q
    );
  data_error_137 : FD
    port map (
      C => do_clk,
      D => cnt1(9),
      Q => data_error_137_Q
    );
  data_error_143 : FD
    port map (
      C => do_clk,
      D => cnt1(15),
      Q => data_error_143_Q
    );
  data_error_138 : FD
    port map (
      C => do_clk,
      D => cnt1(10),
      Q => data_error_138_Q
    );
  data_error_139 : FD
    port map (
      C => do_clk,
      D => cnt1(11),
      Q => data_error_139_Q
    );
  data_error_144 : FD
    port map (
      C => do_clk,
      D => cnt1(16),
      Q => data_error_144_Q
    );
  data_error_150 : FD
    port map (
      C => do_clk,
      D => cnt1(22),
      Q => data_error_150_Q
    );
  data_error_145 : FD
    port map (
      C => do_clk,
      D => cnt1(17),
      Q => data_error_145_Q
    );
  data_error_151 : FD
    port map (
      C => do_clk,
      D => cnt1(23),
      Q => data_error_151_Q
    );
  data_error_146 : FD
    port map (
      C => do_clk,
      D => cnt1(18),
      Q => data_error_146_Q
    );
  data_error_152 : FD
    port map (
      C => do_clk,
      D => cnt1(24),
      Q => data_error_152_Q
    );
  data_error_147 : FD
    port map (
      C => do_clk,
      D => cnt1(19),
      Q => data_error_147_Q
    );
  data_error_148 : FD
    port map (
      C => do_clk,
      D => cnt1(20),
      Q => data_error_148_Q
    );
  data_error_149 : FD
    port map (
      C => do_clk,
      D => cnt1(21),
      Q => data_error_149_Q
    );
  data_error_160 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(0),
      Q => data_error_160_Q
    );
  data_error_161 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(1),
      Q => data_error_161_Q
    );
  data_error_162 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(2),
      Q => data_error_162_Q
    );
  data_error_163 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(3),
      Q => data_error_163_Q
    );
  data_error_164 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(4),
      Q => data_error_164_Q
    );
  data_error_165 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(5),
      Q => data_error_165_Q
    );
  data_error_170 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(10),
      Q => data_error_170_Q
    );
  data_error_171 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(11),
      Q => data_error_171_Q
    );
  data_error_166 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(6),
      Q => data_error_166_Q
    );
  data_error_167 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(7),
      Q => data_error_167_Q
    );
  data_error_172 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(12),
      Q => data_error_172_Q
    );
  data_error_168 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(8),
      Q => data_error_168_Q
    );
  data_error_173 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(13),
      Q => data_error_173_Q
    );
  data_error_169 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(9),
      Q => data_error_169_Q
    );
  data_error_174 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(14),
      Q => data_error_174_Q
    );
  data_error_175 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(15),
      Q => data_error_175_Q
    );
  data_error_180 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(20),
      Q => data_error_180_Q
    );
  data_error_181 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(21),
      Q => data_error_181_Q
    );
  data_error_176 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(16),
      Q => data_error_176_Q
    );
  data_error_177 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(17),
      Q => data_error_177_Q
    );
  data_error_182 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(22),
      Q => data_error_182_Q
    );
  data_error_178 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(18),
      Q => data_error_178_Q
    );
  data_error_183 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(23),
      Q => data_error_183_Q
    );
  data_error_179 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(19),
      Q => data_error_179_Q
    );
  data_error_184 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(24),
      Q => data_error_184_Q
    );
  data_error_185 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(25),
      Q => data_error_185_Q
    );
  data_error_190 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(30),
      Q => data_error_190_Q
    );
  data_error_186 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(26),
      Q => data_error_186_Q
    );
  data_error_191 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(31),
      Q => data_error_191_Q
    );
  data_error_187 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(27),
      Q => data_error_187_Q
    );
  data_error_188 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(28),
      Q => data_error_188_Q
    );
  data_error_189 : FD
    port map (
      C => do_clk,
      D => NlwRenamedSig_OI_block_rd(29),
      Q => data_error_189_Q
    );
  block_ok_en : FDRE
    port map (
      C => clk,
      CE => cnt1_eq_3379,
      D => N1,
      R => rst_inv,
      Q => block_ok_en_3318
    );
  flag_error : FDRSE
    port map (
      C => do_clk,
      CE => flag_error_clr_4749,
      D => data_error_153_Q,
      R => rst_inv,
      S => data_error_wr,
      Q => flag_error_4748
    );
  cnt1_z : FDSE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => cnt1_eq_3379,
      S => rst_inv,
      Q => cnt1_z_3399
    );
  data_ex5_13 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(12),
      R => rst_inv,
      Q => data_ex5(13)
    );
  data_ex4_10 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(10),
      R => rst_inv,
      Q => data_ex4(10)
    );
  data_ex4_32 : FDRE
    port map (
      C => do_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(0),
      R => rst_inv,
      Q => data_ex4(32)
    );
  data_ex5_14 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(13),
      R => rst_inv,
      Q => data_ex5(14)
    );
  data_ex5_15 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(14),
      R => rst_inv,
      Q => data_ex5(15)
    );
  test_check_err_data_0 : FD
    port map (
      C => clk,
      D => err_data(0),
      Q => test_check_err_data(0)
    );
  test_check_err_data_1 : FD
    port map (
      C => clk,
      D => err_data(1),
      Q => test_check_err_data(1)
    );
  test_check_err_data_2 : FD
    port map (
      C => clk,
      D => err_data(2),
      Q => test_check_err_data(2)
    );
  test_check_err_data_3 : FD
    port map (
      C => clk,
      D => err_data(3),
      Q => test_check_err_data(3)
    );
  test_check_err_data_4 : FD
    port map (
      C => clk,
      D => err_data(4),
      Q => test_check_err_data(4)
    );
  test_check_err_data_5 : FD
    port map (
      C => clk,
      D => err_data(5),
      Q => test_check_err_data(5)
    );
  test_check_err_data_6 : FD
    port map (
      C => clk,
      D => err_data(6),
      Q => test_check_err_data(6)
    );
  test_check_err_data_7 : FD
    port map (
      C => clk,
      D => err_data(7),
      Q => test_check_err_data(7)
    );
  test_check_err_data_8 : FD
    port map (
      C => clk,
      D => err_data(8),
      Q => test_check_err_data(8)
    );
  test_check_err_data_9 : FD
    port map (
      C => clk,
      D => err_data(9),
      Q => test_check_err_data(9)
    );
  test_check_err_data_10 : FD
    port map (
      C => clk,
      D => err_data(10),
      Q => test_check_err_data(10)
    );
  test_check_err_data_11 : FD
    port map (
      C => clk,
      D => err_data(11),
      Q => test_check_err_data(11)
    );
  test_check_err_data_12 : FD
    port map (
      C => clk,
      D => err_data(12),
      Q => test_check_err_data(12)
    );
  test_check_err_data_13 : FD
    port map (
      C => clk,
      D => err_data(13),
      Q => test_check_err_data(13)
    );
  test_check_err_data_14 : FD
    port map (
      C => clk,
      D => err_data(14),
      Q => test_check_err_data(14)
    );
  test_check_err_data_15 : FD
    port map (
      C => clk,
      D => err_data(15),
      Q => test_check_err_data(15)
    );
  data_ex5_16 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(15),
      R => rst_inv,
      Q => data_ex5(16)
    );
  data_ex5_17 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(16),
      R => rst_inv,
      Q => data_ex5(17)
    );
  data_ex5_18 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(17),
      R => rst_inv,
      Q => data_ex5(18)
    );
  data_ex5_19 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(18),
      R => rst_inv,
      Q => data_ex5(19)
    );
  data_ex5_20 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(19),
      R => rst_inv,
      Q => data_ex5(20)
    );
  data_ex5_21 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(20),
      R => rst_inv,
      Q => data_ex5(21)
    );
  data_ex5_22 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(21),
      R => rst_inv,
      Q => data_ex5(22)
    );
  data_ex5_23 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(22),
      R => rst_inv,
      Q => data_ex5(23)
    );
  data_ex5_24 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(23),
      R => rst_inv,
      Q => data_ex5(24)
    );
  data_ex5_25 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(24),
      R => rst_inv,
      Q => data_ex5(25)
    );
  data_ex5_26 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(25),
      R => rst_inv,
      Q => data_ex5(26)
    );
  data_ex5_27 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(26),
      R => rst_inv,
      Q => data_ex5(27)
    );
  data_ex5_28 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(27),
      R => rst_inv,
      Q => data_ex5(28)
    );
  data_ex5_29 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(28),
      R => rst_inv,
      Q => data_ex5(29)
    );
  data_ex5_30 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(29),
      R => rst_inv,
      Q => data_ex5(30)
    );
  data_ex5_31 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(30),
      R => rst_inv,
      Q => data_ex5(31)
    );
  data_ex5_32 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(31),
      R => rst_inv,
      Q => data_ex5(32)
    );
  data_ex5_33 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(32),
      R => rst_inv,
      Q => data_ex5(33)
    );
  data_ex5_34 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(33),
      R => rst_inv,
      Q => data_ex5(34)
    );
  data_ex5_35 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(34),
      R => rst_inv,
      Q => data_ex5(35)
    );
  data_ex5_36 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(35),
      R => rst_inv,
      Q => data_ex5(36)
    );
  data_ex5_37 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(36),
      R => rst_inv,
      Q => data_ex5(37)
    );
  data_ex5_38 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(37),
      R => rst_inv,
      Q => data_ex5(38)
    );
  data_ex5_39 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(38),
      R => rst_inv,
      Q => data_ex5(39)
    );
  data_ex5_40 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(39),
      R => rst_inv,
      Q => data_ex5(40)
    );
  data_ex5_41 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(40),
      R => rst_inv,
      Q => data_ex5(41)
    );
  data_ex5_42 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(41),
      R => rst_inv,
      Q => data_ex5(42)
    );
  data_ex5_43 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(42),
      R => rst_inv,
      Q => data_ex5(43)
    );
  data_ex5_44 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(43),
      R => rst_inv,
      Q => data_ex5(44)
    );
  data_ex5_45 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(44),
      R => rst_inv,
      Q => data_ex5(45)
    );
  data_ex5_46 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(45),
      R => rst_inv,
      Q => data_ex5(46)
    );
  data_ex5_47 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(46),
      R => rst_inv,
      Q => data_ex5(47)
    );
  data_ex5_48 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(47),
      R => rst_inv,
      Q => data_ex5(48)
    );
  data_ex5_49 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(48),
      R => rst_inv,
      Q => data_ex5(49)
    );
  data_ex5_50 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(49),
      R => rst_inv,
      Q => data_ex5(50)
    );
  data_ex5_51 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(50),
      R => rst_inv,
      Q => data_ex5(51)
    );
  data_ex5_52 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(51),
      R => rst_inv,
      Q => data_ex5(52)
    );
  data_ex5_53 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(52),
      R => rst_inv,
      Q => data_ex5(53)
    );
  data_ex5_54 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(53),
      R => rst_inv,
      Q => data_ex5(54)
    );
  data_ex5_55 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(54),
      R => rst_inv,
      Q => data_ex5(55)
    );
  data_ex5_56 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(55),
      R => rst_inv,
      Q => data_ex5(56)
    );
  data_ex5_57 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(56),
      R => rst_inv,
      Q => data_ex5(57)
    );
  data_ex5_58 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(57),
      R => rst_inv,
      Q => data_ex5(58)
    );
  data_ex5_59 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(58),
      R => rst_inv,
      Q => data_ex5(59)
    );
  data_ex5_60 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(59),
      R => rst_inv,
      Q => data_ex5(60)
    );
  data_ex5_61 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(60),
      R => rst_inv,
      Q => data_ex5(61)
    );
  data_ex5_62 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(61),
      R => rst_inv,
      Q => data_ex5(62)
    );
  data_ex5_63 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(62),
      R => rst_inv,
      Q => data_ex5(63)
    );
  data_ex5_0 : FDSE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5_0_xor0000,
      S => rst_inv,
      Q => data_ex5(0)
    );
  data_ex5_1 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(0),
      R => rst_inv,
      Q => data_ex5(1)
    );
  data_ex5_2 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(1),
      R => rst_inv,
      Q => data_ex5(2)
    );
  data_ex5_3 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(2),
      R => rst_inv,
      Q => data_ex5(3)
    );
  data_ex5_4 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(3),
      R => rst_inv,
      Q => data_ex5(4)
    );
  data_ex5_5 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(4),
      R => rst_inv,
      Q => data_ex5(5)
    );
  data_ex5_6 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(5),
      R => rst_inv,
      Q => data_ex5(6)
    );
  data_ex5_7 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(6),
      R => rst_inv,
      Q => data_ex5(7)
    );
  data_ex5_8 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(7),
      R => rst_inv,
      Q => data_ex5(8)
    );
  data_ex5_9 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(8),
      R => rst_inv,
      Q => data_ex5(9)
    );
  data_ex5_10 : FDRE
    port map (
      C => do_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(9),
      R => rst_inv,
      Q => data_ex5(10)
    );
  block_ok_0 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(0),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(0)
    );
  block_ok_1 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(1),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(1)
    );
  block_ok_2 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(2),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(2)
    );
  block_ok_3 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(3),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(3)
    );
  block_ok_4 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(4),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(4)
    );
  block_ok_5 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(5),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(5)
    );
  block_ok_6 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(6),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(6)
    );
  block_ok_7 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(7),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(7)
    );
  block_ok_8 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(8),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(8)
    );
  block_ok_9 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(9),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(9)
    );
  block_ok_10 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(10),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(10)
    );
  block_ok_11 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(11),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(11)
    );
  block_ok_12 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(12),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(12)
    );
  block_ok_13 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(13),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(13)
    );
  block_ok_14 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(14),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(14)
    );
  block_ok_15 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(15),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(15)
    );
  block_ok_16 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(16),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(16)
    );
  block_ok_17 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(17),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(17)
    );
  block_ok_18 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(18),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(18)
    );
  block_ok_19 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(19),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(19)
    );
  block_ok_20 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(20),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(20)
    );
  block_ok_21 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(21),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(21)
    );
  block_ok_22 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(22),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(22)
    );
  block_ok_23 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(23),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(23)
    );
  block_ok_24 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(24),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(24)
    );
  block_ok_25 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(25),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(25)
    );
  block_ok_26 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(26),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(26)
    );
  block_ok_27 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(27),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(27)
    );
  block_ok_28 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(28),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(28)
    );
  block_ok_29 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(29),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(29)
    );
  block_ok_30 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(30),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(30)
    );
  block_ok_31 : FDRE
    port map (
      C => do_clk,
      CE => block_ok_not0001,
      D => Result(31),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_ok(31)
    );
  block_mode_0 : FDRE
    port map (
      C => do_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode,
      R => block_mode_or0000_3285,
      Q => block_mode(0)
    );
  block_mode_1 : FDRE
    port map (
      C => do_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode1,
      R => block_mode_or0000_3285,
      Q => block_mode(1)
    );
  block_mode_2 : FDRE
    port map (
      C => do_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode2,
      R => block_mode_or0000_3285,
      Q => block_mode(2)
    );
  block_mode_3 : FDRE
    port map (
      C => do_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode3,
      R => block_mode_or0000_3285,
      Q => block_mode(3)
    );
  block_err_0 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_0_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(0)
    );
  block_err_1 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_1_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(1)
    );
  block_err_2 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_2_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(2)
    );
  block_err_3 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_3_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(3)
    );
  block_err_4 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_4_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(4)
    );
  block_err_5 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_5_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(5)
    );
  block_err_6 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_6_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(6)
    );
  block_err_7 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_7_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(7)
    );
  block_err_8 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_8_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(8)
    );
  block_err_9 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_9_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(9)
    );
  block_err_10 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_10_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(10)
    );
  block_err_11 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_11_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(11)
    );
  block_err_12 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_12_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(12)
    );
  block_err_13 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_13_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(13)
    );
  block_err_14 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_14_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(14)
    );
  block_err_15 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_15_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(15)
    );
  block_err_16 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_16_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(16)
    );
  block_err_17 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_17_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(17)
    );
  block_err_18 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_18_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(18)
    );
  block_err_19 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_19_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(19)
    );
  block_err_20 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_20_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(20)
    );
  block_err_21 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_21_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(21)
    );
  block_err_22 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_22_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(22)
    );
  block_err_23 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_23_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(23)
    );
  block_err_24 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_24_4,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(24)
    );
  block_err_25 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_25_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(25)
    );
  block_err_26 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_26_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(26)
    );
  block_err_27 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_27_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(27)
    );
  block_err_28 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_28_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(28)
    );
  block_err_29 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_29_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(29)
    );
  block_err_30 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_30_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(30)
    );
  block_err_31 : FDRE
    port map (
      C => do_clk,
      CE => block_err_not0001,
      D => Result_31_3,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_err(31)
    );
  total_err_0 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_0_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(0)
    );
  total_err_1 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_1_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(1)
    );
  total_err_2 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_2_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(2)
    );
  total_err_3 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_3_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(3)
    );
  total_err_4 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_4_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(4)
    );
  total_err_5 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_5_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(5)
    );
  total_err_6 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_6_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(6)
    );
  total_err_7 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_7_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(7)
    );
  total_err_8 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_8_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(8)
    );
  total_err_9 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_9_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(9)
    );
  total_err_10 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_10_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(10)
    );
  total_err_11 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_11_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(11)
    );
  total_err_12 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_12_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(12)
    );
  total_err_13 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_13_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(13)
    );
  total_err_14 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_14_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(14)
    );
  total_err_15 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_15_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(15)
    );
  total_err_16 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_16_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(16)
    );
  total_err_17 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_17_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(17)
    );
  total_err_18 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_18_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(18)
    );
  total_err_19 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_19_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(19)
    );
  total_err_20 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_20_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(20)
    );
  total_err_21 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_21_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(21)
    );
  total_err_22 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_22_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(22)
    );
  total_err_23 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_23_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(23)
    );
  total_err_24 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_24_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(24)
    );
  total_err_25 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_25_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(25)
    );
  total_err_26 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_26_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(26)
    );
  total_err_27 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_27_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(27)
    );
  total_err_28 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_28_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(28)
    );
  total_err_29 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_29_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(29)
    );
  total_err_30 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_30_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(30)
    );
  total_err_31 : FDRE
    port map (
      C => do_clk,
      CE => total_err_and0000,
      D => Result_31_1,
      R => rst_inv,
      Q => NlwRenamedSig_OI_total_err(31)
    );
  block_rd_0 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_0_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(0)
    );
  block_rd_1 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_1_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(1)
    );
  block_rd_2 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_2_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(2)
    );
  block_rd_3 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_3_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(3)
    );
  block_rd_4 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_4_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(4)
    );
  block_rd_5 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_5_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(5)
    );
  block_rd_6 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_6_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(6)
    );
  block_rd_7 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_7_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(7)
    );
  block_rd_8 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_8_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(8)
    );
  block_rd_9 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_9_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(9)
    );
  block_rd_10 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_10_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(10)
    );
  block_rd_11 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_11_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(11)
    );
  block_rd_12 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_12_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(12)
    );
  block_rd_13 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_13_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(13)
    );
  block_rd_14 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_14_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(14)
    );
  block_rd_15 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_15_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(15)
    );
  block_rd_16 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_16_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(16)
    );
  block_rd_17 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_17_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(17)
    );
  block_rd_18 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_18_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(18)
    );
  block_rd_19 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_19_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(19)
    );
  block_rd_20 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_20_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(20)
    );
  block_rd_21 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_21_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(21)
    );
  block_rd_22 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_22_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(22)
    );
  block_rd_23 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_23_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(23)
    );
  block_rd_24 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_24_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(24)
    );
  block_rd_25 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_25_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(25)
    );
  block_rd_26 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_26_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(26)
    );
  block_rd_27 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_27_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(27)
    );
  block_rd_28 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_28_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(28)
    );
  block_rd_29 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_29_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(29)
    );
  block_rd_30 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_30_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(30)
    );
  block_rd_31 : FDRE
    port map (
      C => do_clk,
      CE => block_rd_and0000,
      D => Result_31_2,
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(31)
    );
  cnt1_0 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_0_3,
      R => cnt1_or0000,
      Q => cnt1(0)
    );
  cnt1_1 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_1_3,
      R => cnt1_or0000,
      Q => cnt1(1)
    );
  cnt1_2 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_2_3,
      R => cnt1_or0000,
      Q => cnt1(2)
    );
  cnt1_3 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_3_3,
      R => cnt1_or0000,
      Q => cnt1(3)
    );
  cnt1_4 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_4_3,
      R => cnt1_or0000,
      Q => cnt1(4)
    );
  cnt1_5 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_5_3,
      R => cnt1_or0000,
      Q => cnt1(5)
    );
  cnt1_6 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_6_3,
      R => cnt1_or0000,
      Q => cnt1(6)
    );
  cnt1_7 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_7_3,
      R => cnt1_or0000,
      Q => cnt1(7)
    );
  cnt1_8 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_8_3,
      R => cnt1_or0000,
      Q => cnt1(8)
    );
  cnt1_9 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_9_3,
      R => cnt1_or0000,
      Q => cnt1(9)
    );
  cnt1_10 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_10_3,
      R => cnt1_or0000,
      Q => cnt1(10)
    );
  cnt1_11 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_11_3,
      R => cnt1_or0000,
      Q => cnt1(11)
    );
  cnt1_12 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_12_3,
      R => cnt1_or0000,
      Q => cnt1(12)
    );
  cnt1_13 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_13_3,
      R => cnt1_or0000,
      Q => cnt1(13)
    );
  cnt1_14 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_14_3,
      R => cnt1_or0000,
      Q => cnt1(14)
    );
  cnt1_15 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_15_3,
      R => cnt1_or0000,
      Q => cnt1(15)
    );
  cnt1_16 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_16_3,
      R => cnt1_or0000,
      Q => cnt1(16)
    );
  cnt1_17 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_17_3,
      R => cnt1_or0000,
      Q => cnt1(17)
    );
  cnt1_18 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_18_3,
      R => cnt1_or0000,
      Q => cnt1(18)
    );
  cnt1_19 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_19_3,
      R => cnt1_or0000,
      Q => cnt1(19)
    );
  cnt1_20 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_20_3,
      R => cnt1_or0000,
      Q => cnt1(20)
    );
  cnt1_21 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_21_3,
      R => cnt1_or0000,
      Q => cnt1(21)
    );
  cnt1_22 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_22_3,
      R => cnt1_or0000,
      Q => cnt1(22)
    );
  cnt1_23 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_23_3,
      R => cnt1_or0000,
      Q => cnt1(23)
    );
  cnt1_24 : FDRE
    port map (
      C => do_clk,
      CE => do_data_en,
      D => Result_24_3,
      R => cnt1_or0000,
      Q => cnt1(24)
    );
  Madd_data_ex4_63_32_add0000_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Madd_data_ex4_63_32_add0000_lut(0),
      O => Madd_data_ex4_63_32_add0000_cy(0)
    );
  Madd_data_ex4_63_32_add0000_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Madd_data_ex4_63_32_add0000_lut(0),
      O => data_ex4_63_32_add0000(0)
    );
  Madd_data_ex4_63_32_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(0),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_1_rt_2466,
      O => Madd_data_ex4_63_32_add0000_cy(1)
    );
  Madd_data_ex4_63_32_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(0),
      LI => Madd_data_ex4_63_32_add0000_cy_1_rt_2466,
      O => data_ex4_63_32_add0000(1)
    );
  Madd_data_ex4_63_32_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(1),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_2_rt_2488,
      O => Madd_data_ex4_63_32_add0000_cy(2)
    );
  Madd_data_ex4_63_32_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(1),
      LI => Madd_data_ex4_63_32_add0000_cy_2_rt_2488,
      O => data_ex4_63_32_add0000(2)
    );
  Madd_data_ex4_63_32_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(2),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_3_rt_2492,
      O => Madd_data_ex4_63_32_add0000_cy(3)
    );
  Madd_data_ex4_63_32_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(2),
      LI => Madd_data_ex4_63_32_add0000_cy_3_rt_2492,
      O => data_ex4_63_32_add0000(3)
    );
  Madd_data_ex4_63_32_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(3),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_4_rt_2494,
      O => Madd_data_ex4_63_32_add0000_cy(4)
    );
  Madd_data_ex4_63_32_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(3),
      LI => Madd_data_ex4_63_32_add0000_cy_4_rt_2494,
      O => data_ex4_63_32_add0000(4)
    );
  Madd_data_ex4_63_32_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(4),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_5_rt_2496,
      O => Madd_data_ex4_63_32_add0000_cy(5)
    );
  Madd_data_ex4_63_32_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(4),
      LI => Madd_data_ex4_63_32_add0000_cy_5_rt_2496,
      O => data_ex4_63_32_add0000(5)
    );
  Madd_data_ex4_63_32_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(5),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_6_rt_2498,
      O => Madd_data_ex4_63_32_add0000_cy(6)
    );
  Madd_data_ex4_63_32_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(5),
      LI => Madd_data_ex4_63_32_add0000_cy_6_rt_2498,
      O => data_ex4_63_32_add0000(6)
    );
  Madd_data_ex4_63_32_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(6),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_7_rt_2500,
      O => Madd_data_ex4_63_32_add0000_cy(7)
    );
  Madd_data_ex4_63_32_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(6),
      LI => Madd_data_ex4_63_32_add0000_cy_7_rt_2500,
      O => data_ex4_63_32_add0000(7)
    );
  Madd_data_ex4_63_32_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(7),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_8_rt_2502,
      O => Madd_data_ex4_63_32_add0000_cy(8)
    );
  Madd_data_ex4_63_32_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(7),
      LI => Madd_data_ex4_63_32_add0000_cy_8_rt_2502,
      O => data_ex4_63_32_add0000(8)
    );
  Madd_data_ex4_63_32_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(8),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_9_rt_2504,
      O => Madd_data_ex4_63_32_add0000_cy(9)
    );
  Madd_data_ex4_63_32_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(8),
      LI => Madd_data_ex4_63_32_add0000_cy_9_rt_2504,
      O => data_ex4_63_32_add0000(9)
    );
  Madd_data_ex4_63_32_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(9),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_10_rt_2446,
      O => Madd_data_ex4_63_32_add0000_cy(10)
    );
  Madd_data_ex4_63_32_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(9),
      LI => Madd_data_ex4_63_32_add0000_cy_10_rt_2446,
      O => data_ex4_63_32_add0000(10)
    );
  Madd_data_ex4_63_32_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(10),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_11_rt_2448,
      O => Madd_data_ex4_63_32_add0000_cy(11)
    );
  Madd_data_ex4_63_32_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(10),
      LI => Madd_data_ex4_63_32_add0000_cy_11_rt_2448,
      O => data_ex4_63_32_add0000(11)
    );
  Madd_data_ex4_63_32_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(11),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_12_rt_2450,
      O => Madd_data_ex4_63_32_add0000_cy(12)
    );
  Madd_data_ex4_63_32_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(11),
      LI => Madd_data_ex4_63_32_add0000_cy_12_rt_2450,
      O => data_ex4_63_32_add0000(12)
    );
  Madd_data_ex4_63_32_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(12),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_13_rt_2452,
      O => Madd_data_ex4_63_32_add0000_cy(13)
    );
  Madd_data_ex4_63_32_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(12),
      LI => Madd_data_ex4_63_32_add0000_cy_13_rt_2452,
      O => data_ex4_63_32_add0000(13)
    );
  Madd_data_ex4_63_32_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(13),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_14_rt_2454,
      O => Madd_data_ex4_63_32_add0000_cy(14)
    );
  Madd_data_ex4_63_32_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(13),
      LI => Madd_data_ex4_63_32_add0000_cy_14_rt_2454,
      O => data_ex4_63_32_add0000(14)
    );
  Madd_data_ex4_63_32_add0000_cy_15_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(14),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_15_rt_2456,
      O => Madd_data_ex4_63_32_add0000_cy(15)
    );
  Madd_data_ex4_63_32_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(14),
      LI => Madd_data_ex4_63_32_add0000_cy_15_rt_2456,
      O => data_ex4_63_32_add0000(15)
    );
  Madd_data_ex4_63_32_add0000_cy_16_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(15),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_16_rt_2458,
      O => Madd_data_ex4_63_32_add0000_cy(16)
    );
  Madd_data_ex4_63_32_add0000_xor_16_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(15),
      LI => Madd_data_ex4_63_32_add0000_cy_16_rt_2458,
      O => data_ex4_63_32_add0000(16)
    );
  Madd_data_ex4_63_32_add0000_cy_17_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(16),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_17_rt_2460,
      O => Madd_data_ex4_63_32_add0000_cy(17)
    );
  Madd_data_ex4_63_32_add0000_xor_17_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(16),
      LI => Madd_data_ex4_63_32_add0000_cy_17_rt_2460,
      O => data_ex4_63_32_add0000(17)
    );
  Madd_data_ex4_63_32_add0000_cy_18_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(17),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_18_rt_2462,
      O => Madd_data_ex4_63_32_add0000_cy(18)
    );
  Madd_data_ex4_63_32_add0000_xor_18_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(17),
      LI => Madd_data_ex4_63_32_add0000_cy_18_rt_2462,
      O => data_ex4_63_32_add0000(18)
    );
  Madd_data_ex4_63_32_add0000_cy_19_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(18),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_19_rt_2464,
      O => Madd_data_ex4_63_32_add0000_cy(19)
    );
  Madd_data_ex4_63_32_add0000_xor_19_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(18),
      LI => Madd_data_ex4_63_32_add0000_cy_19_rt_2464,
      O => data_ex4_63_32_add0000(19)
    );
  Madd_data_ex4_63_32_add0000_cy_20_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(19),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_20_rt_2468,
      O => Madd_data_ex4_63_32_add0000_cy(20)
    );
  Madd_data_ex4_63_32_add0000_xor_20_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(19),
      LI => Madd_data_ex4_63_32_add0000_cy_20_rt_2468,
      O => data_ex4_63_32_add0000(20)
    );
  Madd_data_ex4_63_32_add0000_cy_21_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(20),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_21_rt_2470,
      O => Madd_data_ex4_63_32_add0000_cy(21)
    );
  Madd_data_ex4_63_32_add0000_xor_21_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(20),
      LI => Madd_data_ex4_63_32_add0000_cy_21_rt_2470,
      O => data_ex4_63_32_add0000(21)
    );
  Madd_data_ex4_63_32_add0000_cy_22_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(21),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_22_rt_2472,
      O => Madd_data_ex4_63_32_add0000_cy(22)
    );
  Madd_data_ex4_63_32_add0000_xor_22_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(21),
      LI => Madd_data_ex4_63_32_add0000_cy_22_rt_2472,
      O => data_ex4_63_32_add0000(22)
    );
  Madd_data_ex4_63_32_add0000_cy_23_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(22),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_23_rt_2474,
      O => Madd_data_ex4_63_32_add0000_cy(23)
    );
  Madd_data_ex4_63_32_add0000_xor_23_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(22),
      LI => Madd_data_ex4_63_32_add0000_cy_23_rt_2474,
      O => data_ex4_63_32_add0000(23)
    );
  Madd_data_ex4_63_32_add0000_cy_24_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(23),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_24_rt_2476,
      O => Madd_data_ex4_63_32_add0000_cy(24)
    );
  Madd_data_ex4_63_32_add0000_xor_24_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(23),
      LI => Madd_data_ex4_63_32_add0000_cy_24_rt_2476,
      O => data_ex4_63_32_add0000(24)
    );
  Madd_data_ex4_63_32_add0000_cy_25_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(24),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_25_rt_2478,
      O => Madd_data_ex4_63_32_add0000_cy(25)
    );
  Madd_data_ex4_63_32_add0000_xor_25_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(24),
      LI => Madd_data_ex4_63_32_add0000_cy_25_rt_2478,
      O => data_ex4_63_32_add0000(25)
    );
  Madd_data_ex4_63_32_add0000_cy_26_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(25),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_26_rt_2480,
      O => Madd_data_ex4_63_32_add0000_cy(26)
    );
  Madd_data_ex4_63_32_add0000_xor_26_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(25),
      LI => Madd_data_ex4_63_32_add0000_cy_26_rt_2480,
      O => data_ex4_63_32_add0000(26)
    );
  Madd_data_ex4_63_32_add0000_cy_27_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(26),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_27_rt_2482,
      O => Madd_data_ex4_63_32_add0000_cy(27)
    );
  Madd_data_ex4_63_32_add0000_xor_27_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(26),
      LI => Madd_data_ex4_63_32_add0000_cy_27_rt_2482,
      O => data_ex4_63_32_add0000(27)
    );
  Madd_data_ex4_63_32_add0000_cy_28_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(27),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_28_rt_2484,
      O => Madd_data_ex4_63_32_add0000_cy(28)
    );
  Madd_data_ex4_63_32_add0000_xor_28_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(27),
      LI => Madd_data_ex4_63_32_add0000_cy_28_rt_2484,
      O => data_ex4_63_32_add0000(28)
    );
  Madd_data_ex4_63_32_add0000_cy_29_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(28),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_29_rt_2486,
      O => Madd_data_ex4_63_32_add0000_cy(29)
    );
  Madd_data_ex4_63_32_add0000_xor_29_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(28),
      LI => Madd_data_ex4_63_32_add0000_cy_29_rt_2486,
      O => data_ex4_63_32_add0000(29)
    );
  Madd_data_ex4_63_32_add0000_cy_30_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(29),
      DI => data_error_153_Q,
      S => Madd_data_ex4_63_32_add0000_cy_30_rt_2490,
      O => Madd_data_ex4_63_32_add0000_cy(30)
    );
  Madd_data_ex4_63_32_add0000_xor_30_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(29),
      LI => Madd_data_ex4_63_32_add0000_cy_30_rt_2490,
      O => data_ex4_63_32_add0000(30)
    );
  Madd_data_ex4_63_32_add0000_xor_31_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(30),
      LI => Madd_data_ex4_63_32_add0000_xor_31_rt_2506,
      O => data_ex4_63_32_add0000(31)
    );
  Madd_data_ex4_31_0_add0000_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Madd_data_ex4_31_0_add0000_lut(0),
      O => Madd_data_ex4_31_0_add0000_cy(0)
    );
  Madd_data_ex4_31_0_add0000_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Madd_data_ex4_31_0_add0000_lut(0),
      O => data_ex4_31_0_add0000(0)
    );
  Madd_data_ex4_31_0_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(0),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_1_rt_2403,
      O => Madd_data_ex4_31_0_add0000_cy(1)
    );
  Madd_data_ex4_31_0_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(0),
      LI => Madd_data_ex4_31_0_add0000_cy_1_rt_2403,
      O => data_ex4_31_0_add0000(1)
    );
  Madd_data_ex4_31_0_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(1),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_2_rt_2425,
      O => Madd_data_ex4_31_0_add0000_cy(2)
    );
  Madd_data_ex4_31_0_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(1),
      LI => Madd_data_ex4_31_0_add0000_cy_2_rt_2425,
      O => data_ex4_31_0_add0000(2)
    );
  Madd_data_ex4_31_0_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(2),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_3_rt_2429,
      O => Madd_data_ex4_31_0_add0000_cy(3)
    );
  Madd_data_ex4_31_0_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(2),
      LI => Madd_data_ex4_31_0_add0000_cy_3_rt_2429,
      O => data_ex4_31_0_add0000(3)
    );
  Madd_data_ex4_31_0_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(3),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_4_rt_2431,
      O => Madd_data_ex4_31_0_add0000_cy(4)
    );
  Madd_data_ex4_31_0_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(3),
      LI => Madd_data_ex4_31_0_add0000_cy_4_rt_2431,
      O => data_ex4_31_0_add0000(4)
    );
  Madd_data_ex4_31_0_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(4),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_5_rt_2433,
      O => Madd_data_ex4_31_0_add0000_cy(5)
    );
  Madd_data_ex4_31_0_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(4),
      LI => Madd_data_ex4_31_0_add0000_cy_5_rt_2433,
      O => data_ex4_31_0_add0000(5)
    );
  Madd_data_ex4_31_0_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(5),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_6_rt_2435,
      O => Madd_data_ex4_31_0_add0000_cy(6)
    );
  Madd_data_ex4_31_0_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(5),
      LI => Madd_data_ex4_31_0_add0000_cy_6_rt_2435,
      O => data_ex4_31_0_add0000(6)
    );
  Madd_data_ex4_31_0_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(6),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_7_rt_2437,
      O => Madd_data_ex4_31_0_add0000_cy(7)
    );
  Madd_data_ex4_31_0_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(6),
      LI => Madd_data_ex4_31_0_add0000_cy_7_rt_2437,
      O => data_ex4_31_0_add0000(7)
    );
  Madd_data_ex4_31_0_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(7),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_8_rt_2439,
      O => Madd_data_ex4_31_0_add0000_cy(8)
    );
  Madd_data_ex4_31_0_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(7),
      LI => Madd_data_ex4_31_0_add0000_cy_8_rt_2439,
      O => data_ex4_31_0_add0000(8)
    );
  Madd_data_ex4_31_0_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(8),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_9_rt_2441,
      O => Madd_data_ex4_31_0_add0000_cy(9)
    );
  Madd_data_ex4_31_0_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(8),
      LI => Madd_data_ex4_31_0_add0000_cy_9_rt_2441,
      O => data_ex4_31_0_add0000(9)
    );
  Madd_data_ex4_31_0_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(9),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_10_rt_2383,
      O => Madd_data_ex4_31_0_add0000_cy(10)
    );
  Madd_data_ex4_31_0_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(9),
      LI => Madd_data_ex4_31_0_add0000_cy_10_rt_2383,
      O => data_ex4_31_0_add0000(10)
    );
  Madd_data_ex4_31_0_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(10),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_11_rt_2385,
      O => Madd_data_ex4_31_0_add0000_cy(11)
    );
  Madd_data_ex4_31_0_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(10),
      LI => Madd_data_ex4_31_0_add0000_cy_11_rt_2385,
      O => data_ex4_31_0_add0000(11)
    );
  Madd_data_ex4_31_0_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(11),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_12_rt_2387,
      O => Madd_data_ex4_31_0_add0000_cy(12)
    );
  Madd_data_ex4_31_0_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(11),
      LI => Madd_data_ex4_31_0_add0000_cy_12_rt_2387,
      O => data_ex4_31_0_add0000(12)
    );
  Madd_data_ex4_31_0_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(12),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_13_rt_2389,
      O => Madd_data_ex4_31_0_add0000_cy(13)
    );
  Madd_data_ex4_31_0_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(12),
      LI => Madd_data_ex4_31_0_add0000_cy_13_rt_2389,
      O => data_ex4_31_0_add0000(13)
    );
  Madd_data_ex4_31_0_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(13),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_14_rt_2391,
      O => Madd_data_ex4_31_0_add0000_cy(14)
    );
  Madd_data_ex4_31_0_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(13),
      LI => Madd_data_ex4_31_0_add0000_cy_14_rt_2391,
      O => data_ex4_31_0_add0000(14)
    );
  Madd_data_ex4_31_0_add0000_cy_15_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(14),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_15_rt_2393,
      O => Madd_data_ex4_31_0_add0000_cy(15)
    );
  Madd_data_ex4_31_0_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(14),
      LI => Madd_data_ex4_31_0_add0000_cy_15_rt_2393,
      O => data_ex4_31_0_add0000(15)
    );
  Madd_data_ex4_31_0_add0000_cy_16_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(15),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_16_rt_2395,
      O => Madd_data_ex4_31_0_add0000_cy(16)
    );
  Madd_data_ex4_31_0_add0000_xor_16_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(15),
      LI => Madd_data_ex4_31_0_add0000_cy_16_rt_2395,
      O => data_ex4_31_0_add0000(16)
    );
  Madd_data_ex4_31_0_add0000_cy_17_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(16),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_17_rt_2397,
      O => Madd_data_ex4_31_0_add0000_cy(17)
    );
  Madd_data_ex4_31_0_add0000_xor_17_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(16),
      LI => Madd_data_ex4_31_0_add0000_cy_17_rt_2397,
      O => data_ex4_31_0_add0000(17)
    );
  Madd_data_ex4_31_0_add0000_cy_18_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(17),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_18_rt_2399,
      O => Madd_data_ex4_31_0_add0000_cy(18)
    );
  Madd_data_ex4_31_0_add0000_xor_18_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(17),
      LI => Madd_data_ex4_31_0_add0000_cy_18_rt_2399,
      O => data_ex4_31_0_add0000(18)
    );
  Madd_data_ex4_31_0_add0000_cy_19_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(18),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_19_rt_2401,
      O => Madd_data_ex4_31_0_add0000_cy(19)
    );
  Madd_data_ex4_31_0_add0000_xor_19_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(18),
      LI => Madd_data_ex4_31_0_add0000_cy_19_rt_2401,
      O => data_ex4_31_0_add0000(19)
    );
  Madd_data_ex4_31_0_add0000_cy_20_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(19),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_20_rt_2405,
      O => Madd_data_ex4_31_0_add0000_cy(20)
    );
  Madd_data_ex4_31_0_add0000_xor_20_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(19),
      LI => Madd_data_ex4_31_0_add0000_cy_20_rt_2405,
      O => data_ex4_31_0_add0000(20)
    );
  Madd_data_ex4_31_0_add0000_cy_21_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(20),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_21_rt_2407,
      O => Madd_data_ex4_31_0_add0000_cy(21)
    );
  Madd_data_ex4_31_0_add0000_xor_21_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(20),
      LI => Madd_data_ex4_31_0_add0000_cy_21_rt_2407,
      O => data_ex4_31_0_add0000(21)
    );
  Madd_data_ex4_31_0_add0000_cy_22_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(21),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_22_rt_2409,
      O => Madd_data_ex4_31_0_add0000_cy(22)
    );
  Madd_data_ex4_31_0_add0000_xor_22_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(21),
      LI => Madd_data_ex4_31_0_add0000_cy_22_rt_2409,
      O => data_ex4_31_0_add0000(22)
    );
  Madd_data_ex4_31_0_add0000_cy_23_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(22),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_23_rt_2411,
      O => Madd_data_ex4_31_0_add0000_cy(23)
    );
  Madd_data_ex4_31_0_add0000_xor_23_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(22),
      LI => Madd_data_ex4_31_0_add0000_cy_23_rt_2411,
      O => data_ex4_31_0_add0000(23)
    );
  Madd_data_ex4_31_0_add0000_cy_24_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(23),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_24_rt_2413,
      O => Madd_data_ex4_31_0_add0000_cy(24)
    );
  Madd_data_ex4_31_0_add0000_xor_24_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(23),
      LI => Madd_data_ex4_31_0_add0000_cy_24_rt_2413,
      O => data_ex4_31_0_add0000(24)
    );
  Madd_data_ex4_31_0_add0000_cy_25_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(24),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_25_rt_2415,
      O => Madd_data_ex4_31_0_add0000_cy(25)
    );
  Madd_data_ex4_31_0_add0000_xor_25_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(24),
      LI => Madd_data_ex4_31_0_add0000_cy_25_rt_2415,
      O => data_ex4_31_0_add0000(25)
    );
  Madd_data_ex4_31_0_add0000_cy_26_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(25),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_26_rt_2417,
      O => Madd_data_ex4_31_0_add0000_cy(26)
    );
  Madd_data_ex4_31_0_add0000_xor_26_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(25),
      LI => Madd_data_ex4_31_0_add0000_cy_26_rt_2417,
      O => data_ex4_31_0_add0000(26)
    );
  Madd_data_ex4_31_0_add0000_cy_27_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(26),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_27_rt_2419,
      O => Madd_data_ex4_31_0_add0000_cy(27)
    );
  Madd_data_ex4_31_0_add0000_xor_27_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(26),
      LI => Madd_data_ex4_31_0_add0000_cy_27_rt_2419,
      O => data_ex4_31_0_add0000(27)
    );
  Madd_data_ex4_31_0_add0000_cy_28_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(27),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_28_rt_2421,
      O => Madd_data_ex4_31_0_add0000_cy(28)
    );
  Madd_data_ex4_31_0_add0000_xor_28_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(27),
      LI => Madd_data_ex4_31_0_add0000_cy_28_rt_2421,
      O => data_ex4_31_0_add0000(28)
    );
  Madd_data_ex4_31_0_add0000_cy_29_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(28),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_29_rt_2423,
      O => Madd_data_ex4_31_0_add0000_cy(29)
    );
  Madd_data_ex4_31_0_add0000_xor_29_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(28),
      LI => Madd_data_ex4_31_0_add0000_cy_29_rt_2423,
      O => data_ex4_31_0_add0000(29)
    );
  Madd_data_ex4_31_0_add0000_cy_30_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(29),
      DI => data_error_153_Q,
      S => Madd_data_ex4_31_0_add0000_cy_30_rt_2427,
      O => Madd_data_ex4_31_0_add0000_cy(30)
    );
  Madd_data_ex4_31_0_add0000_xor_30_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(29),
      LI => Madd_data_ex4_31_0_add0000_cy_30_rt_2427,
      O => data_ex4_31_0_add0000(30)
    );
  Madd_data_ex4_31_0_add0000_xor_31_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(30),
      LI => Madd_data_ex4_31_0_add0000_xor_31_rt_2443,
      O => data_ex4_31_0_add0000(31)
    );
  Msub_cnt1_eq_addsub0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => data_error_153_Q,
      S => Msub_cnt1_eq_addsub0000_cy_0_rt_2913,
      O => Msub_cnt1_eq_addsub0000_cy(0)
    );
  Msub_cnt1_eq_addsub0000_xor_0_Q : XORCY
    port map (
      CI => N1,
      LI => Msub_cnt1_eq_addsub0000_cy_0_rt_2913,
      O => cnt1_eq_addsub0000(0)
    );
  Msub_cnt1_eq_addsub0000_cy_1_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(0),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(1),
      O => Msub_cnt1_eq_addsub0000_cy(1)
    );
  Msub_cnt1_eq_addsub0000_xor_1_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(0),
      LI => Msub_cnt1_eq_addsub0000_lut(1),
      O => cnt1_eq_addsub0000(1)
    );
  Msub_cnt1_eq_addsub0000_cy_2_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(1),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(2),
      O => Msub_cnt1_eq_addsub0000_cy(2)
    );
  Msub_cnt1_eq_addsub0000_xor_2_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(1),
      LI => Msub_cnt1_eq_addsub0000_lut(2),
      O => cnt1_eq_addsub0000(2)
    );
  Msub_cnt1_eq_addsub0000_cy_3_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(2),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(3),
      O => Msub_cnt1_eq_addsub0000_cy(3)
    );
  Msub_cnt1_eq_addsub0000_xor_3_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(2),
      LI => Msub_cnt1_eq_addsub0000_lut(3),
      O => cnt1_eq_addsub0000(3)
    );
  Msub_cnt1_eq_addsub0000_cy_4_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(3),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(4),
      O => Msub_cnt1_eq_addsub0000_cy(4)
    );
  Msub_cnt1_eq_addsub0000_xor_4_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(3),
      LI => Msub_cnt1_eq_addsub0000_lut(4),
      O => cnt1_eq_addsub0000(4)
    );
  Msub_cnt1_eq_addsub0000_cy_5_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(4),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(5),
      O => Msub_cnt1_eq_addsub0000_cy(5)
    );
  Msub_cnt1_eq_addsub0000_xor_5_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(4),
      LI => Msub_cnt1_eq_addsub0000_lut(5),
      O => cnt1_eq_addsub0000(5)
    );
  Msub_cnt1_eq_addsub0000_cy_6_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(5),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(6),
      O => Msub_cnt1_eq_addsub0000_cy(6)
    );
  Msub_cnt1_eq_addsub0000_xor_6_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(5),
      LI => Msub_cnt1_eq_addsub0000_lut(6),
      O => cnt1_eq_addsub0000(6)
    );
  Msub_cnt1_eq_addsub0000_cy_7_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(6),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(7),
      O => Msub_cnt1_eq_addsub0000_cy(7)
    );
  Msub_cnt1_eq_addsub0000_xor_7_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(6),
      LI => Msub_cnt1_eq_addsub0000_lut(7),
      O => cnt1_eq_addsub0000(7)
    );
  Msub_cnt1_eq_addsub0000_cy_8_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(7),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(8),
      O => Msub_cnt1_eq_addsub0000_cy(8)
    );
  Msub_cnt1_eq_addsub0000_xor_8_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(7),
      LI => Msub_cnt1_eq_addsub0000_lut(8),
      O => cnt1_eq_addsub0000(8)
    );
  Msub_cnt1_eq_addsub0000_cy_9_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(8),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(9),
      O => Msub_cnt1_eq_addsub0000_cy(9)
    );
  Msub_cnt1_eq_addsub0000_xor_9_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(8),
      LI => Msub_cnt1_eq_addsub0000_lut(9),
      O => cnt1_eq_addsub0000(9)
    );
  Msub_cnt1_eq_addsub0000_cy_10_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(9),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(10),
      O => Msub_cnt1_eq_addsub0000_cy(10)
    );
  Msub_cnt1_eq_addsub0000_xor_10_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(9),
      LI => Msub_cnt1_eq_addsub0000_lut(10),
      O => cnt1_eq_addsub0000(10)
    );
  Msub_cnt1_eq_addsub0000_cy_11_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(10),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(11),
      O => Msub_cnt1_eq_addsub0000_cy(11)
    );
  Msub_cnt1_eq_addsub0000_xor_11_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(10),
      LI => Msub_cnt1_eq_addsub0000_lut(11),
      O => cnt1_eq_addsub0000(11)
    );
  Msub_cnt1_eq_addsub0000_cy_12_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(11),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(12),
      O => Msub_cnt1_eq_addsub0000_cy(12)
    );
  Msub_cnt1_eq_addsub0000_xor_12_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(11),
      LI => Msub_cnt1_eq_addsub0000_lut(12),
      O => cnt1_eq_addsub0000(12)
    );
  Msub_cnt1_eq_addsub0000_cy_13_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(12),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(13),
      O => Msub_cnt1_eq_addsub0000_cy(13)
    );
  Msub_cnt1_eq_addsub0000_xor_13_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(12),
      LI => Msub_cnt1_eq_addsub0000_lut(13),
      O => cnt1_eq_addsub0000(13)
    );
  Msub_cnt1_eq_addsub0000_cy_14_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(13),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(14),
      O => Msub_cnt1_eq_addsub0000_cy(14)
    );
  Msub_cnt1_eq_addsub0000_xor_14_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(13),
      LI => Msub_cnt1_eq_addsub0000_lut(14),
      O => cnt1_eq_addsub0000(14)
    );
  Msub_cnt1_eq_addsub0000_xor_15_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(14),
      LI => Msub_cnt1_eq_addsub0000_lut(15),
      O => cnt1_eq_addsub0000(15)
    );
  Mcompar_word_error_cmp_ne0000_lut_0_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(0),
      I1 => data_expect(0),
      I2 => do_data_z(1),
      I3 => data_expect(1),
      I4 => do_data_z(2),
      I5 => data_expect(2),
      O => Mcompar_word_error_cmp_ne0000_lut(0)
    );
  Mcompar_word_error_cmp_ne0000_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(0),
      O => Mcompar_word_error_cmp_ne0000_cy(0)
    );
  Mcompar_word_error_cmp_ne0000_lut_1_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(3),
      I1 => data_expect(3),
      I2 => do_data_z(4),
      I3 => data_expect(4),
      I4 => do_data_z(5),
      I5 => data_expect(5),
      O => Mcompar_word_error_cmp_ne0000_lut(1)
    );
  Mcompar_word_error_cmp_ne0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(0),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(1),
      O => Mcompar_word_error_cmp_ne0000_cy(1)
    );
  Mcompar_word_error_cmp_ne0000_lut_2_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(6),
      I1 => data_expect(6),
      I2 => do_data_z(7),
      I3 => data_expect(7),
      I4 => do_data_z(8),
      I5 => data_expect(8),
      O => Mcompar_word_error_cmp_ne0000_lut(2)
    );
  Mcompar_word_error_cmp_ne0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(1),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(2),
      O => Mcompar_word_error_cmp_ne0000_cy(2)
    );
  Mcompar_word_error_cmp_ne0000_lut_3_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(9),
      I1 => data_expect(9),
      I2 => do_data_z(10),
      I3 => data_expect(10),
      I4 => do_data_z(11),
      I5 => data_expect(11),
      O => Mcompar_word_error_cmp_ne0000_lut(3)
    );
  Mcompar_word_error_cmp_ne0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(2),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(3),
      O => Mcompar_word_error_cmp_ne0000_cy(3)
    );
  Mcompar_word_error_cmp_ne0000_lut_4_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(12),
      I1 => data_expect(12),
      I2 => do_data_z(13),
      I3 => data_expect(13),
      I4 => do_data_z(14),
      I5 => data_expect(14),
      O => Mcompar_word_error_cmp_ne0000_lut(4)
    );
  Mcompar_word_error_cmp_ne0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(3),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(4),
      O => Mcompar_word_error_cmp_ne0000_cy(4)
    );
  Mcompar_word_error_cmp_ne0000_lut_5_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(15),
      I1 => data_expect(15),
      I2 => do_data_z(16),
      I3 => data_expect(16),
      I4 => do_data_z(17),
      I5 => data_expect(17),
      O => Mcompar_word_error_cmp_ne0000_lut(5)
    );
  Mcompar_word_error_cmp_ne0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(4),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(5),
      O => Mcompar_word_error_cmp_ne0000_cy(5)
    );
  Mcompar_word_error_cmp_ne0000_lut_6_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(18),
      I1 => data_expect(18),
      I2 => do_data_z(19),
      I3 => data_expect(19),
      I4 => do_data_z(20),
      I5 => data_expect(20),
      O => Mcompar_word_error_cmp_ne0000_lut(6)
    );
  Mcompar_word_error_cmp_ne0000_cy_6_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(5),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(6),
      O => Mcompar_word_error_cmp_ne0000_cy(6)
    );
  Mcompar_word_error_cmp_ne0000_lut_7_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(21),
      I1 => data_expect(21),
      I2 => do_data_z(22),
      I3 => data_expect(22),
      I4 => do_data_z(23),
      I5 => data_expect(23),
      O => Mcompar_word_error_cmp_ne0000_lut(7)
    );
  Mcompar_word_error_cmp_ne0000_cy_7_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(6),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(7),
      O => Mcompar_word_error_cmp_ne0000_cy(7)
    );
  Mcompar_word_error_cmp_ne0000_lut_8_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(24),
      I1 => data_expect(24),
      I2 => do_data_z(25),
      I3 => data_expect(25),
      I4 => do_data_z(26),
      I5 => data_expect(26),
      O => Mcompar_word_error_cmp_ne0000_lut(8)
    );
  Mcompar_word_error_cmp_ne0000_cy_8_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(7),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(8),
      O => Mcompar_word_error_cmp_ne0000_cy(8)
    );
  Mcompar_word_error_cmp_ne0000_lut_9_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(27),
      I1 => data_expect(27),
      I2 => do_data_z(28),
      I3 => data_expect(28),
      I4 => do_data_z(29),
      I5 => data_expect(29),
      O => Mcompar_word_error_cmp_ne0000_lut(9)
    );
  Mcompar_word_error_cmp_ne0000_cy_9_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(8),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(9),
      O => Mcompar_word_error_cmp_ne0000_cy(9)
    );
  Mcompar_word_error_cmp_ne0000_lut_10_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(30),
      I1 => data_expect(30),
      I2 => do_data_z(31),
      I3 => data_expect(31),
      I4 => do_data_z(32),
      I5 => data_expect(32),
      O => Mcompar_word_error_cmp_ne0000_lut(10)
    );
  Mcompar_word_error_cmp_ne0000_cy_10_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(9),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(10),
      O => Mcompar_word_error_cmp_ne0000_cy(10)
    );
  Mcompar_word_error_cmp_ne0000_lut_11_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(33),
      I1 => data_expect(33),
      I2 => do_data_z(34),
      I3 => data_expect(34),
      I4 => do_data_z(35),
      I5 => data_expect(35),
      O => Mcompar_word_error_cmp_ne0000_lut(11)
    );
  Mcompar_word_error_cmp_ne0000_cy_11_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(10),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(11),
      O => Mcompar_word_error_cmp_ne0000_cy(11)
    );
  Mcompar_word_error_cmp_ne0000_lut_12_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(36),
      I1 => data_expect(36),
      I2 => do_data_z(37),
      I3 => data_expect(37),
      I4 => do_data_z(38),
      I5 => data_expect(38),
      O => Mcompar_word_error_cmp_ne0000_lut(12)
    );
  Mcompar_word_error_cmp_ne0000_cy_12_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(11),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(12),
      O => Mcompar_word_error_cmp_ne0000_cy(12)
    );
  Mcompar_word_error_cmp_ne0000_lut_13_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(39),
      I1 => data_expect(39),
      I2 => do_data_z(40),
      I3 => data_expect(40),
      I4 => do_data_z(41),
      I5 => data_expect(41),
      O => Mcompar_word_error_cmp_ne0000_lut(13)
    );
  Mcompar_word_error_cmp_ne0000_cy_13_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(12),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(13),
      O => Mcompar_word_error_cmp_ne0000_cy(13)
    );
  Mcompar_word_error_cmp_ne0000_lut_14_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(42),
      I1 => data_expect(42),
      I2 => do_data_z(43),
      I3 => data_expect(43),
      I4 => do_data_z(44),
      I5 => data_expect(44),
      O => Mcompar_word_error_cmp_ne0000_lut(14)
    );
  Mcompar_word_error_cmp_ne0000_cy_14_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(13),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(14),
      O => Mcompar_word_error_cmp_ne0000_cy(14)
    );
  Mcompar_word_error_cmp_ne0000_lut_15_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(45),
      I1 => data_expect(45),
      I2 => do_data_z(46),
      I3 => data_expect(46),
      I4 => do_data_z(47),
      I5 => data_expect(47),
      O => Mcompar_word_error_cmp_ne0000_lut(15)
    );
  Mcompar_word_error_cmp_ne0000_cy_15_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(14),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(15),
      O => Mcompar_word_error_cmp_ne0000_cy(15)
    );
  Mcompar_word_error_cmp_ne0000_lut_16_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(48),
      I1 => data_expect(48),
      I2 => do_data_z(49),
      I3 => data_expect(49),
      I4 => do_data_z(50),
      I5 => data_expect(50),
      O => Mcompar_word_error_cmp_ne0000_lut(16)
    );
  Mcompar_word_error_cmp_ne0000_cy_16_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(15),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(16),
      O => Mcompar_word_error_cmp_ne0000_cy(16)
    );
  Mcompar_word_error_cmp_ne0000_lut_17_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(51),
      I1 => data_expect(51),
      I2 => do_data_z(52),
      I3 => data_expect(52),
      I4 => do_data_z(53),
      I5 => data_expect(53),
      O => Mcompar_word_error_cmp_ne0000_lut(17)
    );
  Mcompar_word_error_cmp_ne0000_cy_17_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(16),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(17),
      O => Mcompar_word_error_cmp_ne0000_cy(17)
    );
  Mcompar_word_error_cmp_ne0000_lut_18_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(54),
      I1 => data_expect(54),
      I2 => do_data_z(55),
      I3 => data_expect(55),
      I4 => do_data_z(56),
      I5 => data_expect(56),
      O => Mcompar_word_error_cmp_ne0000_lut(18)
    );
  Mcompar_word_error_cmp_ne0000_cy_18_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(17),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(18),
      O => Mcompar_word_error_cmp_ne0000_cy(18)
    );
  Mcompar_word_error_cmp_ne0000_lut_19_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(57),
      I1 => data_expect(57),
      I2 => do_data_z(58),
      I3 => data_expect(58),
      I4 => do_data_z(59),
      I5 => data_expect(59),
      O => Mcompar_word_error_cmp_ne0000_lut(19)
    );
  Mcompar_word_error_cmp_ne0000_cy_19_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(18),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(19),
      O => Mcompar_word_error_cmp_ne0000_cy(19)
    );
  Mcompar_word_error_cmp_ne0000_lut_20_Q : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => do_data_z(60),
      I1 => data_expect(60),
      I2 => do_data_z(61),
      I3 => data_expect(61),
      I4 => do_data_z(62),
      I5 => data_expect(62),
      O => Mcompar_word_error_cmp_ne0000_lut(20)
    );
  Mcompar_word_error_cmp_ne0000_cy_20_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(19),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(20),
      O => Mcompar_word_error_cmp_ne0000_cy(20)
    );
  Mcompar_word_error_cmp_ne0000_lut_21_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => do_data_z(63),
      I1 => data_expect(63),
      O => Mcompar_word_error_cmp_ne0000_lut(21)
    );
  Mcompar_word_error_cmp_ne0000_cy_21_Q : MUXCY
    port map (
      CI => Mcompar_word_error_cmp_ne0000_cy(20),
      DI => N1,
      S => Mcompar_word_error_cmp_ne0000_lut(21),
      O => word_error
    );
  Mcount_total_err_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcount_total_err_lut(0),
      O => Mcount_total_err_cy(0)
    );
  Mcount_total_err_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Mcount_total_err_lut(0),
      O => Result_0_1
    );
  Mcount_total_err_cy_1_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(0),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_1_rt_2823,
      O => Mcount_total_err_cy(1)
    );
  Mcount_total_err_xor_1_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(0),
      LI => Mcount_total_err_cy_1_rt_2823,
      O => Result_1_1
    );
  Mcount_total_err_cy_2_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(1),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_2_rt_2845,
      O => Mcount_total_err_cy(2)
    );
  Mcount_total_err_xor_2_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(1),
      LI => Mcount_total_err_cy_2_rt_2845,
      O => Result_2_1
    );
  Mcount_total_err_cy_3_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(2),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_3_rt_2849,
      O => Mcount_total_err_cy(3)
    );
  Mcount_total_err_xor_3_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(2),
      LI => Mcount_total_err_cy_3_rt_2849,
      O => Result_3_1
    );
  Mcount_total_err_cy_4_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(3),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_4_rt_2851,
      O => Mcount_total_err_cy(4)
    );
  Mcount_total_err_xor_4_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(3),
      LI => Mcount_total_err_cy_4_rt_2851,
      O => Result_4_1
    );
  Mcount_total_err_cy_5_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(4),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_5_rt_2853,
      O => Mcount_total_err_cy(5)
    );
  Mcount_total_err_xor_5_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(4),
      LI => Mcount_total_err_cy_5_rt_2853,
      O => Result_5_1
    );
  Mcount_total_err_cy_6_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(5),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_6_rt_2855,
      O => Mcount_total_err_cy(6)
    );
  Mcount_total_err_xor_6_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(5),
      LI => Mcount_total_err_cy_6_rt_2855,
      O => Result_6_1
    );
  Mcount_total_err_cy_7_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(6),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_7_rt_2857,
      O => Mcount_total_err_cy(7)
    );
  Mcount_total_err_xor_7_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(6),
      LI => Mcount_total_err_cy_7_rt_2857,
      O => Result_7_1
    );
  Mcount_total_err_cy_8_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(7),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_8_rt_2859,
      O => Mcount_total_err_cy(8)
    );
  Mcount_total_err_xor_8_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(7),
      LI => Mcount_total_err_cy_8_rt_2859,
      O => Result_8_1
    );
  Mcount_total_err_cy_9_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(8),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_9_rt_2861,
      O => Mcount_total_err_cy(9)
    );
  Mcount_total_err_xor_9_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(8),
      LI => Mcount_total_err_cy_9_rt_2861,
      O => Result_9_1
    );
  Mcount_total_err_cy_10_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(9),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_10_rt_2803,
      O => Mcount_total_err_cy(10)
    );
  Mcount_total_err_xor_10_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(9),
      LI => Mcount_total_err_cy_10_rt_2803,
      O => Result_10_1
    );
  Mcount_total_err_cy_11_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(10),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_11_rt_2805,
      O => Mcount_total_err_cy(11)
    );
  Mcount_total_err_xor_11_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(10),
      LI => Mcount_total_err_cy_11_rt_2805,
      O => Result_11_1
    );
  Mcount_total_err_cy_12_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(11),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_12_rt_2807,
      O => Mcount_total_err_cy(12)
    );
  Mcount_total_err_xor_12_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(11),
      LI => Mcount_total_err_cy_12_rt_2807,
      O => Result_12_1
    );
  Mcount_total_err_cy_13_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(12),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_13_rt_2809,
      O => Mcount_total_err_cy(13)
    );
  Mcount_total_err_xor_13_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(12),
      LI => Mcount_total_err_cy_13_rt_2809,
      O => Result_13_1
    );
  Mcount_total_err_cy_14_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(13),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_14_rt_2811,
      O => Mcount_total_err_cy(14)
    );
  Mcount_total_err_xor_14_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(13),
      LI => Mcount_total_err_cy_14_rt_2811,
      O => Result_14_1
    );
  Mcount_total_err_cy_15_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(14),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_15_rt_2813,
      O => Mcount_total_err_cy(15)
    );
  Mcount_total_err_xor_15_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(14),
      LI => Mcount_total_err_cy_15_rt_2813,
      O => Result_15_1
    );
  Mcount_total_err_cy_16_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(15),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_16_rt_2815,
      O => Mcount_total_err_cy(16)
    );
  Mcount_total_err_xor_16_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(15),
      LI => Mcount_total_err_cy_16_rt_2815,
      O => Result_16_1
    );
  Mcount_total_err_cy_17_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(16),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_17_rt_2817,
      O => Mcount_total_err_cy(17)
    );
  Mcount_total_err_xor_17_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(16),
      LI => Mcount_total_err_cy_17_rt_2817,
      O => Result_17_1
    );
  Mcount_total_err_cy_18_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(17),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_18_rt_2819,
      O => Mcount_total_err_cy(18)
    );
  Mcount_total_err_xor_18_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(17),
      LI => Mcount_total_err_cy_18_rt_2819,
      O => Result_18_1
    );
  Mcount_total_err_cy_19_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(18),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_19_rt_2821,
      O => Mcount_total_err_cy(19)
    );
  Mcount_total_err_xor_19_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(18),
      LI => Mcount_total_err_cy_19_rt_2821,
      O => Result_19_1
    );
  Mcount_total_err_cy_20_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(19),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_20_rt_2825,
      O => Mcount_total_err_cy(20)
    );
  Mcount_total_err_xor_20_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(19),
      LI => Mcount_total_err_cy_20_rt_2825,
      O => Result_20_1
    );
  Mcount_total_err_cy_21_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(20),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_21_rt_2827,
      O => Mcount_total_err_cy(21)
    );
  Mcount_total_err_xor_21_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(20),
      LI => Mcount_total_err_cy_21_rt_2827,
      O => Result_21_1
    );
  Mcount_total_err_cy_22_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(21),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_22_rt_2829,
      O => Mcount_total_err_cy(22)
    );
  Mcount_total_err_xor_22_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(21),
      LI => Mcount_total_err_cy_22_rt_2829,
      O => Result_22_1
    );
  Mcount_total_err_cy_23_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(22),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_23_rt_2831,
      O => Mcount_total_err_cy(23)
    );
  Mcount_total_err_xor_23_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(22),
      LI => Mcount_total_err_cy_23_rt_2831,
      O => Result_23_1
    );
  Mcount_total_err_cy_24_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(23),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_24_rt_2833,
      O => Mcount_total_err_cy(24)
    );
  Mcount_total_err_xor_24_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(23),
      LI => Mcount_total_err_cy_24_rt_2833,
      O => Result_24_1
    );
  Mcount_total_err_cy_25_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(24),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_25_rt_2835,
      O => Mcount_total_err_cy(25)
    );
  Mcount_total_err_xor_25_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(24),
      LI => Mcount_total_err_cy_25_rt_2835,
      O => Result_25_1
    );
  Mcount_total_err_cy_26_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(25),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_26_rt_2837,
      O => Mcount_total_err_cy(26)
    );
  Mcount_total_err_xor_26_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(25),
      LI => Mcount_total_err_cy_26_rt_2837,
      O => Result_26_1
    );
  Mcount_total_err_cy_27_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(26),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_27_rt_2839,
      O => Mcount_total_err_cy(27)
    );
  Mcount_total_err_xor_27_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(26),
      LI => Mcount_total_err_cy_27_rt_2839,
      O => Result_27_1
    );
  Mcount_total_err_cy_28_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(27),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_28_rt_2841,
      O => Mcount_total_err_cy(28)
    );
  Mcount_total_err_xor_28_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(27),
      LI => Mcount_total_err_cy_28_rt_2841,
      O => Result_28_1
    );
  Mcount_total_err_cy_29_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(28),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_29_rt_2843,
      O => Mcount_total_err_cy(29)
    );
  Mcount_total_err_xor_29_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(28),
      LI => Mcount_total_err_cy_29_rt_2843,
      O => Result_29_1
    );
  Mcount_total_err_cy_30_Q : MUXCY
    port map (
      CI => Mcount_total_err_cy(29),
      DI => data_error_153_Q,
      S => Mcount_total_err_cy_30_rt_2847,
      O => Mcount_total_err_cy(30)
    );
  Mcount_total_err_xor_30_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(29),
      LI => Mcount_total_err_cy_30_rt_2847,
      O => Result_30_1
    );
  Mcount_total_err_xor_31_Q : XORCY
    port map (
      CI => Mcount_total_err_cy(30),
      LI => Mcount_total_err_xor_31_rt_2863,
      O => Result_31_1
    );
  Mcount_block_ok_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcount_block_ok_lut(0),
      O => Mcount_block_ok_cy(0)
    );
  Mcount_block_ok_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Mcount_block_ok_lut(0),
      O => Result(0)
    );
  Mcount_block_ok_cy_1_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(0),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_1_rt_2649,
      O => Mcount_block_ok_cy(1)
    );
  Mcount_block_ok_xor_1_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(0),
      LI => Mcount_block_ok_cy_1_rt_2649,
      O => Result(1)
    );
  Mcount_block_ok_cy_2_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(1),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_2_rt_2671,
      O => Mcount_block_ok_cy(2)
    );
  Mcount_block_ok_xor_2_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(1),
      LI => Mcount_block_ok_cy_2_rt_2671,
      O => Result(2)
    );
  Mcount_block_ok_cy_3_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(2),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_3_rt_2675,
      O => Mcount_block_ok_cy(3)
    );
  Mcount_block_ok_xor_3_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(2),
      LI => Mcount_block_ok_cy_3_rt_2675,
      O => Result(3)
    );
  Mcount_block_ok_cy_4_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(3),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_4_rt_2677,
      O => Mcount_block_ok_cy(4)
    );
  Mcount_block_ok_xor_4_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(3),
      LI => Mcount_block_ok_cy_4_rt_2677,
      O => Result(4)
    );
  Mcount_block_ok_cy_5_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(4),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_5_rt_2679,
      O => Mcount_block_ok_cy(5)
    );
  Mcount_block_ok_xor_5_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(4),
      LI => Mcount_block_ok_cy_5_rt_2679,
      O => Result(5)
    );
  Mcount_block_ok_cy_6_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(5),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_6_rt_2681,
      O => Mcount_block_ok_cy(6)
    );
  Mcount_block_ok_xor_6_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(5),
      LI => Mcount_block_ok_cy_6_rt_2681,
      O => Result(6)
    );
  Mcount_block_ok_cy_7_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(6),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_7_rt_2683,
      O => Mcount_block_ok_cy(7)
    );
  Mcount_block_ok_xor_7_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(6),
      LI => Mcount_block_ok_cy_7_rt_2683,
      O => Result(7)
    );
  Mcount_block_ok_cy_8_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(7),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_8_rt_2685,
      O => Mcount_block_ok_cy(8)
    );
  Mcount_block_ok_xor_8_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(7),
      LI => Mcount_block_ok_cy_8_rt_2685,
      O => Result(8)
    );
  Mcount_block_ok_cy_9_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(8),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_9_rt_2687,
      O => Mcount_block_ok_cy(9)
    );
  Mcount_block_ok_xor_9_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(8),
      LI => Mcount_block_ok_cy_9_rt_2687,
      O => Result(9)
    );
  Mcount_block_ok_cy_10_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(9),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_10_rt_2629,
      O => Mcount_block_ok_cy(10)
    );
  Mcount_block_ok_xor_10_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(9),
      LI => Mcount_block_ok_cy_10_rt_2629,
      O => Result(10)
    );
  Mcount_block_ok_cy_11_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(10),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_11_rt_2631,
      O => Mcount_block_ok_cy(11)
    );
  Mcount_block_ok_xor_11_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(10),
      LI => Mcount_block_ok_cy_11_rt_2631,
      O => Result(11)
    );
  Mcount_block_ok_cy_12_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(11),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_12_rt_2633,
      O => Mcount_block_ok_cy(12)
    );
  Mcount_block_ok_xor_12_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(11),
      LI => Mcount_block_ok_cy_12_rt_2633,
      O => Result(12)
    );
  Mcount_block_ok_cy_13_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(12),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_13_rt_2635,
      O => Mcount_block_ok_cy(13)
    );
  Mcount_block_ok_xor_13_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(12),
      LI => Mcount_block_ok_cy_13_rt_2635,
      O => Result(13)
    );
  Mcount_block_ok_cy_14_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(13),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_14_rt_2637,
      O => Mcount_block_ok_cy(14)
    );
  Mcount_block_ok_xor_14_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(13),
      LI => Mcount_block_ok_cy_14_rt_2637,
      O => Result(14)
    );
  Mcount_block_ok_cy_15_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(14),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_15_rt_2639,
      O => Mcount_block_ok_cy(15)
    );
  Mcount_block_ok_xor_15_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(14),
      LI => Mcount_block_ok_cy_15_rt_2639,
      O => Result(15)
    );
  Mcount_block_ok_cy_16_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(15),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_16_rt_2641,
      O => Mcount_block_ok_cy(16)
    );
  Mcount_block_ok_xor_16_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(15),
      LI => Mcount_block_ok_cy_16_rt_2641,
      O => Result(16)
    );
  Mcount_block_ok_cy_17_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(16),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_17_rt_2643,
      O => Mcount_block_ok_cy(17)
    );
  Mcount_block_ok_xor_17_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(16),
      LI => Mcount_block_ok_cy_17_rt_2643,
      O => Result(17)
    );
  Mcount_block_ok_cy_18_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(17),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_18_rt_2645,
      O => Mcount_block_ok_cy(18)
    );
  Mcount_block_ok_xor_18_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(17),
      LI => Mcount_block_ok_cy_18_rt_2645,
      O => Result(18)
    );
  Mcount_block_ok_cy_19_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(18),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_19_rt_2647,
      O => Mcount_block_ok_cy(19)
    );
  Mcount_block_ok_xor_19_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(18),
      LI => Mcount_block_ok_cy_19_rt_2647,
      O => Result(19)
    );
  Mcount_block_ok_cy_20_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(19),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_20_rt_2651,
      O => Mcount_block_ok_cy(20)
    );
  Mcount_block_ok_xor_20_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(19),
      LI => Mcount_block_ok_cy_20_rt_2651,
      O => Result(20)
    );
  Mcount_block_ok_cy_21_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(20),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_21_rt_2653,
      O => Mcount_block_ok_cy(21)
    );
  Mcount_block_ok_xor_21_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(20),
      LI => Mcount_block_ok_cy_21_rt_2653,
      O => Result(21)
    );
  Mcount_block_ok_cy_22_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(21),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_22_rt_2655,
      O => Mcount_block_ok_cy(22)
    );
  Mcount_block_ok_xor_22_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(21),
      LI => Mcount_block_ok_cy_22_rt_2655,
      O => Result(22)
    );
  Mcount_block_ok_cy_23_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(22),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_23_rt_2657,
      O => Mcount_block_ok_cy(23)
    );
  Mcount_block_ok_xor_23_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(22),
      LI => Mcount_block_ok_cy_23_rt_2657,
      O => Result(23)
    );
  Mcount_block_ok_cy_24_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(23),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_24_rt_2659,
      O => Mcount_block_ok_cy(24)
    );
  Mcount_block_ok_xor_24_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(23),
      LI => Mcount_block_ok_cy_24_rt_2659,
      O => Result(24)
    );
  Mcount_block_ok_cy_25_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(24),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_25_rt_2661,
      O => Mcount_block_ok_cy(25)
    );
  Mcount_block_ok_xor_25_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(24),
      LI => Mcount_block_ok_cy_25_rt_2661,
      O => Result(25)
    );
  Mcount_block_ok_cy_26_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(25),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_26_rt_2663,
      O => Mcount_block_ok_cy(26)
    );
  Mcount_block_ok_xor_26_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(25),
      LI => Mcount_block_ok_cy_26_rt_2663,
      O => Result(26)
    );
  Mcount_block_ok_cy_27_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(26),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_27_rt_2665,
      O => Mcount_block_ok_cy(27)
    );
  Mcount_block_ok_xor_27_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(26),
      LI => Mcount_block_ok_cy_27_rt_2665,
      O => Result(27)
    );
  Mcount_block_ok_cy_28_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(27),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_28_rt_2667,
      O => Mcount_block_ok_cy(28)
    );
  Mcount_block_ok_xor_28_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(27),
      LI => Mcount_block_ok_cy_28_rt_2667,
      O => Result(28)
    );
  Mcount_block_ok_cy_29_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(28),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_29_rt_2669,
      O => Mcount_block_ok_cy(29)
    );
  Mcount_block_ok_xor_29_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(28),
      LI => Mcount_block_ok_cy_29_rt_2669,
      O => Result(29)
    );
  Mcount_block_ok_cy_30_Q : MUXCY
    port map (
      CI => Mcount_block_ok_cy(29),
      DI => data_error_153_Q,
      S => Mcount_block_ok_cy_30_rt_2673,
      O => Mcount_block_ok_cy(30)
    );
  Mcount_block_ok_xor_30_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(29),
      LI => Mcount_block_ok_cy_30_rt_2673,
      O => Result(30)
    );
  Mcount_block_ok_xor_31_Q : XORCY
    port map (
      CI => Mcount_block_ok_cy(30),
      LI => NlwRenamedSig_OI_block_ok(31),
      O => Result(31)
    );
  Mcount_block_err_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcount_block_err_lut(0),
      O => Mcount_block_err_cy(0)
    );
  Mcount_block_err_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Mcount_block_err_lut(0),
      O => Result_0_4
    );
  Mcount_block_err_cy_1_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(0),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_1_rt_2583,
      O => Mcount_block_err_cy(1)
    );
  Mcount_block_err_xor_1_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(0),
      LI => Mcount_block_err_cy_1_rt_2583,
      O => Result_1_4
    );
  Mcount_block_err_cy_2_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(1),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_2_rt_2605,
      O => Mcount_block_err_cy(2)
    );
  Mcount_block_err_xor_2_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(1),
      LI => Mcount_block_err_cy_2_rt_2605,
      O => Result_2_4
    );
  Mcount_block_err_cy_3_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(2),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_3_rt_2609,
      O => Mcount_block_err_cy(3)
    );
  Mcount_block_err_xor_3_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(2),
      LI => Mcount_block_err_cy_3_rt_2609,
      O => Result_3_4
    );
  Mcount_block_err_cy_4_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(3),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_4_rt_2611,
      O => Mcount_block_err_cy(4)
    );
  Mcount_block_err_xor_4_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(3),
      LI => Mcount_block_err_cy_4_rt_2611,
      O => Result_4_4
    );
  Mcount_block_err_cy_5_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(4),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_5_rt_2613,
      O => Mcount_block_err_cy(5)
    );
  Mcount_block_err_xor_5_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(4),
      LI => Mcount_block_err_cy_5_rt_2613,
      O => Result_5_4
    );
  Mcount_block_err_cy_6_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(5),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_6_rt_2615,
      O => Mcount_block_err_cy(6)
    );
  Mcount_block_err_xor_6_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(5),
      LI => Mcount_block_err_cy_6_rt_2615,
      O => Result_6_4
    );
  Mcount_block_err_cy_7_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(6),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_7_rt_2617,
      O => Mcount_block_err_cy(7)
    );
  Mcount_block_err_xor_7_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(6),
      LI => Mcount_block_err_cy_7_rt_2617,
      O => Result_7_4
    );
  Mcount_block_err_cy_8_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(7),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_8_rt_2619,
      O => Mcount_block_err_cy(8)
    );
  Mcount_block_err_xor_8_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(7),
      LI => Mcount_block_err_cy_8_rt_2619,
      O => Result_8_4
    );
  Mcount_block_err_cy_9_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(8),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_9_rt_2621,
      O => Mcount_block_err_cy(9)
    );
  Mcount_block_err_xor_9_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(8),
      LI => Mcount_block_err_cy_9_rt_2621,
      O => Result_9_4
    );
  Mcount_block_err_cy_10_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(9),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_10_rt_2563,
      O => Mcount_block_err_cy(10)
    );
  Mcount_block_err_xor_10_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(9),
      LI => Mcount_block_err_cy_10_rt_2563,
      O => Result_10_4
    );
  Mcount_block_err_cy_11_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(10),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_11_rt_2565,
      O => Mcount_block_err_cy(11)
    );
  Mcount_block_err_xor_11_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(10),
      LI => Mcount_block_err_cy_11_rt_2565,
      O => Result_11_4
    );
  Mcount_block_err_cy_12_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(11),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_12_rt_2567,
      O => Mcount_block_err_cy(12)
    );
  Mcount_block_err_xor_12_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(11),
      LI => Mcount_block_err_cy_12_rt_2567,
      O => Result_12_4
    );
  Mcount_block_err_cy_13_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(12),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_13_rt_2569,
      O => Mcount_block_err_cy(13)
    );
  Mcount_block_err_xor_13_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(12),
      LI => Mcount_block_err_cy_13_rt_2569,
      O => Result_13_4
    );
  Mcount_block_err_cy_14_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(13),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_14_rt_2571,
      O => Mcount_block_err_cy(14)
    );
  Mcount_block_err_xor_14_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(13),
      LI => Mcount_block_err_cy_14_rt_2571,
      O => Result_14_4
    );
  Mcount_block_err_cy_15_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(14),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_15_rt_2573,
      O => Mcount_block_err_cy(15)
    );
  Mcount_block_err_xor_15_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(14),
      LI => Mcount_block_err_cy_15_rt_2573,
      O => Result_15_4
    );
  Mcount_block_err_cy_16_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(15),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_16_rt_2575,
      O => Mcount_block_err_cy(16)
    );
  Mcount_block_err_xor_16_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(15),
      LI => Mcount_block_err_cy_16_rt_2575,
      O => Result_16_4
    );
  Mcount_block_err_cy_17_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(16),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_17_rt_2577,
      O => Mcount_block_err_cy(17)
    );
  Mcount_block_err_xor_17_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(16),
      LI => Mcount_block_err_cy_17_rt_2577,
      O => Result_17_4
    );
  Mcount_block_err_cy_18_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(17),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_18_rt_2579,
      O => Mcount_block_err_cy(18)
    );
  Mcount_block_err_xor_18_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(17),
      LI => Mcount_block_err_cy_18_rt_2579,
      O => Result_18_4
    );
  Mcount_block_err_cy_19_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(18),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_19_rt_2581,
      O => Mcount_block_err_cy(19)
    );
  Mcount_block_err_xor_19_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(18),
      LI => Mcount_block_err_cy_19_rt_2581,
      O => Result_19_4
    );
  Mcount_block_err_cy_20_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(19),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_20_rt_2585,
      O => Mcount_block_err_cy(20)
    );
  Mcount_block_err_xor_20_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(19),
      LI => Mcount_block_err_cy_20_rt_2585,
      O => Result_20_4
    );
  Mcount_block_err_cy_21_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(20),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_21_rt_2587,
      O => Mcount_block_err_cy(21)
    );
  Mcount_block_err_xor_21_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(20),
      LI => Mcount_block_err_cy_21_rt_2587,
      O => Result_21_4
    );
  Mcount_block_err_cy_22_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(21),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_22_rt_2589,
      O => Mcount_block_err_cy(22)
    );
  Mcount_block_err_xor_22_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(21),
      LI => Mcount_block_err_cy_22_rt_2589,
      O => Result_22_4
    );
  Mcount_block_err_cy_23_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(22),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_23_rt_2591,
      O => Mcount_block_err_cy(23)
    );
  Mcount_block_err_xor_23_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(22),
      LI => Mcount_block_err_cy_23_rt_2591,
      O => Result_23_4
    );
  Mcount_block_err_cy_24_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(23),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_24_rt_2593,
      O => Mcount_block_err_cy(24)
    );
  Mcount_block_err_xor_24_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(23),
      LI => Mcount_block_err_cy_24_rt_2593,
      O => Result_24_4
    );
  Mcount_block_err_cy_25_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(24),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_25_rt_2595,
      O => Mcount_block_err_cy(25)
    );
  Mcount_block_err_xor_25_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(24),
      LI => Mcount_block_err_cy_25_rt_2595,
      O => Result_25_3
    );
  Mcount_block_err_cy_26_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(25),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_26_rt_2597,
      O => Mcount_block_err_cy(26)
    );
  Mcount_block_err_xor_26_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(25),
      LI => Mcount_block_err_cy_26_rt_2597,
      O => Result_26_3
    );
  Mcount_block_err_cy_27_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(26),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_27_rt_2599,
      O => Mcount_block_err_cy(27)
    );
  Mcount_block_err_xor_27_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(26),
      LI => Mcount_block_err_cy_27_rt_2599,
      O => Result_27_3
    );
  Mcount_block_err_cy_28_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(27),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_28_rt_2601,
      O => Mcount_block_err_cy(28)
    );
  Mcount_block_err_xor_28_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(27),
      LI => Mcount_block_err_cy_28_rt_2601,
      O => Result_28_3
    );
  Mcount_block_err_cy_29_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(28),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_29_rt_2603,
      O => Mcount_block_err_cy(29)
    );
  Mcount_block_err_xor_29_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(28),
      LI => Mcount_block_err_cy_29_rt_2603,
      O => Result_29_3
    );
  Mcount_block_err_cy_30_Q : MUXCY
    port map (
      CI => Mcount_block_err_cy(29),
      DI => data_error_153_Q,
      S => Mcount_block_err_cy_30_rt_2607,
      O => Mcount_block_err_cy(30)
    );
  Mcount_block_err_xor_30_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(29),
      LI => Mcount_block_err_cy_30_rt_2607,
      O => Result_30_3
    );
  Mcount_block_err_xor_31_Q : XORCY
    port map (
      CI => Mcount_block_err_cy(30),
      LI => NlwRenamedSig_OI_block_err(31),
      O => Result_31_3
    );
  Mcount_block_rd_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcount_block_rd_lut(0),
      O => Mcount_block_rd_cy(0)
    );
  Mcount_block_rd_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Mcount_block_rd_lut(0),
      O => Result_0_2
    );
  Mcount_block_rd_cy_1_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(0),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_1_rt_2711,
      O => Mcount_block_rd_cy(1)
    );
  Mcount_block_rd_xor_1_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(0),
      LI => Mcount_block_rd_cy_1_rt_2711,
      O => Result_1_2
    );
  Mcount_block_rd_cy_2_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(1),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_2_rt_2733,
      O => Mcount_block_rd_cy(2)
    );
  Mcount_block_rd_xor_2_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(1),
      LI => Mcount_block_rd_cy_2_rt_2733,
      O => Result_2_2
    );
  Mcount_block_rd_cy_3_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(2),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_3_rt_2737,
      O => Mcount_block_rd_cy(3)
    );
  Mcount_block_rd_xor_3_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(2),
      LI => Mcount_block_rd_cy_3_rt_2737,
      O => Result_3_2
    );
  Mcount_block_rd_cy_4_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(3),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_4_rt_2739,
      O => Mcount_block_rd_cy(4)
    );
  Mcount_block_rd_xor_4_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(3),
      LI => Mcount_block_rd_cy_4_rt_2739,
      O => Result_4_2
    );
  Mcount_block_rd_cy_5_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(4),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_5_rt_2741,
      O => Mcount_block_rd_cy(5)
    );
  Mcount_block_rd_xor_5_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(4),
      LI => Mcount_block_rd_cy_5_rt_2741,
      O => Result_5_2
    );
  Mcount_block_rd_cy_6_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(5),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_6_rt_2743,
      O => Mcount_block_rd_cy(6)
    );
  Mcount_block_rd_xor_6_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(5),
      LI => Mcount_block_rd_cy_6_rt_2743,
      O => Result_6_2
    );
  Mcount_block_rd_cy_7_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(6),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_7_rt_2745,
      O => Mcount_block_rd_cy(7)
    );
  Mcount_block_rd_xor_7_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(6),
      LI => Mcount_block_rd_cy_7_rt_2745,
      O => Result_7_2
    );
  Mcount_block_rd_cy_8_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(7),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_8_rt_2747,
      O => Mcount_block_rd_cy(8)
    );
  Mcount_block_rd_xor_8_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(7),
      LI => Mcount_block_rd_cy_8_rt_2747,
      O => Result_8_2
    );
  Mcount_block_rd_cy_9_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(8),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_9_rt_2749,
      O => Mcount_block_rd_cy(9)
    );
  Mcount_block_rd_xor_9_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(8),
      LI => Mcount_block_rd_cy_9_rt_2749,
      O => Result_9_2
    );
  Mcount_block_rd_cy_10_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(9),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_10_rt_2691,
      O => Mcount_block_rd_cy(10)
    );
  Mcount_block_rd_xor_10_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(9),
      LI => Mcount_block_rd_cy_10_rt_2691,
      O => Result_10_2
    );
  Mcount_block_rd_cy_11_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(10),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_11_rt_2693,
      O => Mcount_block_rd_cy(11)
    );
  Mcount_block_rd_xor_11_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(10),
      LI => Mcount_block_rd_cy_11_rt_2693,
      O => Result_11_2
    );
  Mcount_block_rd_cy_12_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(11),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_12_rt_2695,
      O => Mcount_block_rd_cy(12)
    );
  Mcount_block_rd_xor_12_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(11),
      LI => Mcount_block_rd_cy_12_rt_2695,
      O => Result_12_2
    );
  Mcount_block_rd_cy_13_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(12),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_13_rt_2697,
      O => Mcount_block_rd_cy(13)
    );
  Mcount_block_rd_xor_13_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(12),
      LI => Mcount_block_rd_cy_13_rt_2697,
      O => Result_13_2
    );
  Mcount_block_rd_cy_14_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(13),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_14_rt_2699,
      O => Mcount_block_rd_cy(14)
    );
  Mcount_block_rd_xor_14_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(13),
      LI => Mcount_block_rd_cy_14_rt_2699,
      O => Result_14_2
    );
  Mcount_block_rd_cy_15_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(14),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_15_rt_2701,
      O => Mcount_block_rd_cy(15)
    );
  Mcount_block_rd_xor_15_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(14),
      LI => Mcount_block_rd_cy_15_rt_2701,
      O => Result_15_2
    );
  Mcount_block_rd_cy_16_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(15),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_16_rt_2703,
      O => Mcount_block_rd_cy(16)
    );
  Mcount_block_rd_xor_16_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(15),
      LI => Mcount_block_rd_cy_16_rt_2703,
      O => Result_16_2
    );
  Mcount_block_rd_cy_17_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(16),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_17_rt_2705,
      O => Mcount_block_rd_cy(17)
    );
  Mcount_block_rd_xor_17_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(16),
      LI => Mcount_block_rd_cy_17_rt_2705,
      O => Result_17_2
    );
  Mcount_block_rd_cy_18_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(17),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_18_rt_2707,
      O => Mcount_block_rd_cy(18)
    );
  Mcount_block_rd_xor_18_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(17),
      LI => Mcount_block_rd_cy_18_rt_2707,
      O => Result_18_2
    );
  Mcount_block_rd_cy_19_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(18),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_19_rt_2709,
      O => Mcount_block_rd_cy(19)
    );
  Mcount_block_rd_xor_19_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(18),
      LI => Mcount_block_rd_cy_19_rt_2709,
      O => Result_19_2
    );
  Mcount_block_rd_cy_20_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(19),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_20_rt_2713,
      O => Mcount_block_rd_cy(20)
    );
  Mcount_block_rd_xor_20_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(19),
      LI => Mcount_block_rd_cy_20_rt_2713,
      O => Result_20_2
    );
  Mcount_block_rd_cy_21_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(20),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_21_rt_2715,
      O => Mcount_block_rd_cy(21)
    );
  Mcount_block_rd_xor_21_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(20),
      LI => Mcount_block_rd_cy_21_rt_2715,
      O => Result_21_2
    );
  Mcount_block_rd_cy_22_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(21),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_22_rt_2717,
      O => Mcount_block_rd_cy(22)
    );
  Mcount_block_rd_xor_22_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(21),
      LI => Mcount_block_rd_cy_22_rt_2717,
      O => Result_22_2
    );
  Mcount_block_rd_cy_23_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(22),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_23_rt_2719,
      O => Mcount_block_rd_cy(23)
    );
  Mcount_block_rd_xor_23_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(22),
      LI => Mcount_block_rd_cy_23_rt_2719,
      O => Result_23_2
    );
  Mcount_block_rd_cy_24_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(23),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_24_rt_2721,
      O => Mcount_block_rd_cy(24)
    );
  Mcount_block_rd_xor_24_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(23),
      LI => Mcount_block_rd_cy_24_rt_2721,
      O => Result_24_2
    );
  Mcount_block_rd_cy_25_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(24),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_25_rt_2723,
      O => Mcount_block_rd_cy(25)
    );
  Mcount_block_rd_xor_25_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(24),
      LI => Mcount_block_rd_cy_25_rt_2723,
      O => Result_25_2
    );
  Mcount_block_rd_cy_26_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(25),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_26_rt_2725,
      O => Mcount_block_rd_cy(26)
    );
  Mcount_block_rd_xor_26_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(25),
      LI => Mcount_block_rd_cy_26_rt_2725,
      O => Result_26_2
    );
  Mcount_block_rd_cy_27_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(26),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_27_rt_2727,
      O => Mcount_block_rd_cy(27)
    );
  Mcount_block_rd_xor_27_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(26),
      LI => Mcount_block_rd_cy_27_rt_2727,
      O => Result_27_2
    );
  Mcount_block_rd_cy_28_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(27),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_28_rt_2729,
      O => Mcount_block_rd_cy(28)
    );
  Mcount_block_rd_xor_28_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(27),
      LI => Mcount_block_rd_cy_28_rt_2729,
      O => Result_28_2
    );
  Mcount_block_rd_cy_29_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(28),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_29_rt_2731,
      O => Mcount_block_rd_cy(29)
    );
  Mcount_block_rd_xor_29_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(28),
      LI => Mcount_block_rd_cy_29_rt_2731,
      O => Result_29_2
    );
  Mcount_block_rd_cy_30_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(29),
      DI => data_error_153_Q,
      S => Mcount_block_rd_cy_30_rt_2735,
      O => Mcount_block_rd_cy(30)
    );
  Mcount_block_rd_xor_30_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(29),
      LI => Mcount_block_rd_cy_30_rt_2735,
      O => Result_30_2
    );
  Mcount_block_rd_xor_31_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(30),
      LI => Mcount_block_rd_xor_31_rt_2751,
      O => Result_31_2
    );
  Mcount_cnt1_cy_0_Q : MUXCY
    port map (
      CI => data_error_153_Q,
      DI => N1,
      S => Mcount_cnt1_lut(0),
      O => Mcount_cnt1_cy(0)
    );
  Mcount_cnt1_xor_0_Q : XORCY
    port map (
      CI => data_error_153_Q,
      LI => Mcount_cnt1_lut(0),
      O => Result_0_3
    );
  Mcount_cnt1_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(0),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_1_rt_2774,
      O => Mcount_cnt1_cy(1)
    );
  Mcount_cnt1_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(0),
      LI => Mcount_cnt1_cy_1_rt_2774,
      O => Result_1_3
    );
  Mcount_cnt1_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(1),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_2_rt_2784,
      O => Mcount_cnt1_cy(2)
    );
  Mcount_cnt1_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(1),
      LI => Mcount_cnt1_cy_2_rt_2784,
      O => Result_2_3
    );
  Mcount_cnt1_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(2),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_3_rt_2786,
      O => Mcount_cnt1_cy(3)
    );
  Mcount_cnt1_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(2),
      LI => Mcount_cnt1_cy_3_rt_2786,
      O => Result_3_3
    );
  Mcount_cnt1_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(3),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_4_rt_2788,
      O => Mcount_cnt1_cy(4)
    );
  Mcount_cnt1_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(3),
      LI => Mcount_cnt1_cy_4_rt_2788,
      O => Result_4_3
    );
  Mcount_cnt1_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(4),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_5_rt_2790,
      O => Mcount_cnt1_cy(5)
    );
  Mcount_cnt1_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(4),
      LI => Mcount_cnt1_cy_5_rt_2790,
      O => Result_5_3
    );
  Mcount_cnt1_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(5),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_6_rt_2792,
      O => Mcount_cnt1_cy(6)
    );
  Mcount_cnt1_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(5),
      LI => Mcount_cnt1_cy_6_rt_2792,
      O => Result_6_3
    );
  Mcount_cnt1_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(6),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_7_rt_2794,
      O => Mcount_cnt1_cy(7)
    );
  Mcount_cnt1_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(6),
      LI => Mcount_cnt1_cy_7_rt_2794,
      O => Result_7_3
    );
  Mcount_cnt1_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(7),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_8_rt_2796,
      O => Mcount_cnt1_cy(8)
    );
  Mcount_cnt1_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(7),
      LI => Mcount_cnt1_cy_8_rt_2796,
      O => Result_8_3
    );
  Mcount_cnt1_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(8),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_9_rt_2798,
      O => Mcount_cnt1_cy(9)
    );
  Mcount_cnt1_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(8),
      LI => Mcount_cnt1_cy_9_rt_2798,
      O => Result_9_3
    );
  Mcount_cnt1_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(9),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_10_rt_2754,
      O => Mcount_cnt1_cy(10)
    );
  Mcount_cnt1_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(9),
      LI => Mcount_cnt1_cy_10_rt_2754,
      O => Result_10_3
    );
  Mcount_cnt1_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(10),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_11_rt_2756,
      O => Mcount_cnt1_cy(11)
    );
  Mcount_cnt1_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(10),
      LI => Mcount_cnt1_cy_11_rt_2756,
      O => Result_11_3
    );
  Mcount_cnt1_cy_12_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(11),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_12_rt_2758,
      O => Mcount_cnt1_cy(12)
    );
  Mcount_cnt1_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(11),
      LI => Mcount_cnt1_cy_12_rt_2758,
      O => Result_12_3
    );
  Mcount_cnt1_cy_13_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(12),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_13_rt_2760,
      O => Mcount_cnt1_cy(13)
    );
  Mcount_cnt1_xor_13_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(12),
      LI => Mcount_cnt1_cy_13_rt_2760,
      O => Result_13_3
    );
  Mcount_cnt1_cy_14_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(13),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_14_rt_2762,
      O => Mcount_cnt1_cy(14)
    );
  Mcount_cnt1_xor_14_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(13),
      LI => Mcount_cnt1_cy_14_rt_2762,
      O => Result_14_3
    );
  Mcount_cnt1_cy_15_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(14),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_15_rt_2764,
      O => Mcount_cnt1_cy(15)
    );
  Mcount_cnt1_xor_15_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(14),
      LI => Mcount_cnt1_cy_15_rt_2764,
      O => Result_15_3
    );
  Mcount_cnt1_cy_16_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(15),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_16_rt_2766,
      O => Mcount_cnt1_cy(16)
    );
  Mcount_cnt1_xor_16_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(15),
      LI => Mcount_cnt1_cy_16_rt_2766,
      O => Result_16_3
    );
  Mcount_cnt1_cy_17_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(16),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_17_rt_2768,
      O => Mcount_cnt1_cy(17)
    );
  Mcount_cnt1_xor_17_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(16),
      LI => Mcount_cnt1_cy_17_rt_2768,
      O => Result_17_3
    );
  Mcount_cnt1_cy_18_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(17),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_18_rt_2770,
      O => Mcount_cnt1_cy(18)
    );
  Mcount_cnt1_xor_18_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(17),
      LI => Mcount_cnt1_cy_18_rt_2770,
      O => Result_18_3
    );
  Mcount_cnt1_cy_19_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(18),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_19_rt_2772,
      O => Mcount_cnt1_cy(19)
    );
  Mcount_cnt1_xor_19_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(18),
      LI => Mcount_cnt1_cy_19_rt_2772,
      O => Result_19_3
    );
  Mcount_cnt1_cy_20_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(19),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_20_rt_2776,
      O => Mcount_cnt1_cy(20)
    );
  Mcount_cnt1_xor_20_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(19),
      LI => Mcount_cnt1_cy_20_rt_2776,
      O => Result_20_3
    );
  Mcount_cnt1_cy_21_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(20),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_21_rt_2778,
      O => Mcount_cnt1_cy(21)
    );
  Mcount_cnt1_xor_21_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(20),
      LI => Mcount_cnt1_cy_21_rt_2778,
      O => Result_21_3
    );
  Mcount_cnt1_cy_22_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(21),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_22_rt_2780,
      O => Mcount_cnt1_cy(22)
    );
  Mcount_cnt1_xor_22_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(21),
      LI => Mcount_cnt1_cy_22_rt_2780,
      O => Result_22_3
    );
  Mcount_cnt1_cy_23_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(22),
      DI => data_error_153_Q,
      S => Mcount_cnt1_cy_23_rt_2782,
      O => Mcount_cnt1_cy(23)
    );
  Mcount_cnt1_xor_23_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(22),
      LI => Mcount_cnt1_cy_23_rt_2782,
      O => Result_23_3
    );
  Mcount_cnt1_xor_24_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(23),
      LI => Mcount_cnt1_xor_24_rt_2800,
      O => Result_24_3
    );
  Mmux_err_data_715 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(89),
      I3 => data_error_out(9),
      I4 => data_error_out(73),
      I5 => data_error_out(25),
      O => Mmux_err_data_715_2903
    );
  Mmux_err_data_615 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(121),
      I3 => data_error_out(41),
      I4 => data_error_out(105),
      I5 => data_error_out(57),
      O => Mmux_err_data_615_2887
    );
  Mmux_err_data_714 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(88),
      I3 => data_error_out(8),
      I4 => data_error_out(72),
      I5 => data_error_out(24),
      O => Mmux_err_data_714_2902
    );
  Mmux_err_data_614 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(120),
      I3 => data_error_out(40),
      I4 => data_error_out(104),
      I5 => data_error_out(56),
      O => Mmux_err_data_614_2886
    );
  Mmux_err_data_713 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(87),
      I3 => data_error_out(7),
      I4 => data_error_out(71),
      I5 => data_error_out(23),
      O => Mmux_err_data_713_2901
    );
  Mmux_err_data_613 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(119),
      I3 => data_error_out(39),
      I4 => data_error_out(103),
      I5 => data_error_out(55),
      O => Mmux_err_data_613_2885
    );
  Mmux_err_data_712 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(86),
      I3 => data_error_out(6),
      I4 => data_error_out(70),
      I5 => data_error_out(22),
      O => Mmux_err_data_712_2900
    );
  Mmux_err_data_612 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(118),
      I3 => data_error_out(38),
      I4 => data_error_out(102),
      I5 => data_error_out(54),
      O => Mmux_err_data_612_2884
    );
  Mmux_err_data_711 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(85),
      I3 => data_error_out(5),
      I4 => data_error_out(69),
      I5 => data_error_out(21),
      O => Mmux_err_data_711_2899
    );
  Mmux_err_data_611 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(117),
      I3 => data_error_out(37),
      I4 => data_error_out(101),
      I5 => data_error_out(53),
      O => Mmux_err_data_611_2883
    );
  Mmux_err_data_710 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(84),
      I3 => data_error_out(4),
      I4 => data_error_out(68),
      I5 => data_error_out(20),
      O => Mmux_err_data_710_2898
    );
  Mmux_err_data_610 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(116),
      I3 => data_error_out(36),
      I4 => data_error_out(100),
      I5 => data_error_out(52),
      O => Mmux_err_data_610_2882
    );
  Mmux_err_data_79 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(83),
      I3 => data_error_out(3),
      I4 => data_error_out(67),
      I5 => data_error_out(19),
      O => Mmux_err_data_79_2911
    );
  Mmux_err_data_69 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(115),
      I3 => data_error_out(35),
      I4 => data_error_out(99),
      I5 => data_error_out(51),
      O => Mmux_err_data_69_2895
    );
  Mmux_err_data_78 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(82),
      I3 => data_error_out(2),
      I4 => data_error_out(66),
      I5 => data_error_out(18),
      O => Mmux_err_data_78_2910
    );
  Mmux_err_data_68 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(114),
      I3 => data_error_out(34),
      I4 => data_error_out(98),
      I5 => data_error_out(50),
      O => Mmux_err_data_68_2894
    );
  Mmux_err_data_77 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(81),
      I3 => data_error_out(1),
      I4 => data_error_out(65),
      I5 => data_error_out(17),
      O => Mmux_err_data_77_2909
    );
  Mmux_err_data_67 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(113),
      I3 => data_error_out(33),
      I4 => data_error_out(97),
      I5 => data_error_out(49),
      O => Mmux_err_data_67_2893
    );
  Mmux_err_data_76 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(95),
      I3 => data_error_out(15),
      I4 => data_error_out(79),
      I5 => data_error_out(31),
      O => Mmux_err_data_76_2908
    );
  Mmux_err_data_66 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(127),
      I3 => data_error_out(47),
      I4 => data_error_out(111),
      I5 => data_error_out(63),
      O => Mmux_err_data_66_2892
    );
  Mmux_err_data_75 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(94),
      I3 => data_error_out(14),
      I4 => data_error_out(78),
      I5 => data_error_out(30),
      O => Mmux_err_data_75_2907
    );
  Mmux_err_data_65 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(126),
      I3 => data_error_out(46),
      I4 => data_error_out(110),
      I5 => data_error_out(62),
      O => Mmux_err_data_65_2891
    );
  Mmux_err_data_74 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(93),
      I3 => data_error_out(13),
      I4 => data_error_out(77),
      I5 => data_error_out(29),
      O => Mmux_err_data_74_2906
    );
  Mmux_err_data_64 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(125),
      I3 => data_error_out(45),
      I4 => data_error_out(109),
      I5 => data_error_out(61),
      O => Mmux_err_data_64_2890
    );
  Mmux_err_data_73 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(92),
      I3 => data_error_out(12),
      I4 => data_error_out(76),
      I5 => data_error_out(28),
      O => Mmux_err_data_73_2905
    );
  Mmux_err_data_63 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(124),
      I3 => data_error_out(44),
      I4 => data_error_out(108),
      I5 => data_error_out(60),
      O => Mmux_err_data_63_2889
    );
  Mmux_err_data_72 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(91),
      I3 => data_error_out(11),
      I4 => data_error_out(75),
      I5 => data_error_out(27),
      O => Mmux_err_data_72_2904
    );
  Mmux_err_data_62 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(123),
      I3 => data_error_out(43),
      I4 => data_error_out(107),
      I5 => data_error_out(59),
      O => Mmux_err_data_62_2888
    );
  Mmux_err_data_71 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(90),
      I3 => data_error_out(10),
      I4 => data_error_out(74),
      I5 => data_error_out(26),
      O => Mmux_err_data_71_2897
    );
  Mmux_err_data_61 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(122),
      I3 => data_error_out(42),
      I4 => data_error_out(106),
      I5 => data_error_out(58),
      O => Mmux_err_data_61_2881
    );
  Mmux_err_data_7 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(80),
      I3 => data_error_out(0),
      I4 => data_error_out(64),
      I5 => data_error_out(16),
      O => Mmux_err_data_7_2896
    );
  Mmux_err_data_6 : LUT6
    generic map(
      INIT => X"F7E6D5C4B3A29180"
    )
    port map (
      I0 => test_check_err_adr(2),
      I1 => test_check_err_adr(0),
      I2 => data_error_out(112),
      I3 => data_error_out(32),
      I4 => data_error_out(96),
      I5 => data_error_out(48),
      O => Mmux_err_data_6_2880
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(11),
      I1 => cnt1(10),
      I2 => cnt1(9),
      I3 => cnt1_eq_addsub0000(0),
      I4 => cnt1_eq_addsub0000(1),
      I5 => cnt1_eq_addsub0000(2),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(0)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(0),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(0)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(14),
      I1 => cnt1(13),
      I2 => cnt1(12),
      I3 => cnt1_eq_addsub0000(3),
      I4 => cnt1_eq_addsub0000(4),
      I5 => cnt1_eq_addsub0000(5),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(1)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(0),
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(1),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(1)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_2_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(17),
      I1 => cnt1(16),
      I2 => cnt1(15),
      I3 => cnt1_eq_addsub0000(6),
      I4 => cnt1_eq_addsub0000(7),
      I5 => cnt1_eq_addsub0000(8),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(2)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(1),
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(2),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(2)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(20),
      I1 => cnt1(19),
      I2 => cnt1(18),
      I3 => cnt1_eq_addsub0000(9),
      I4 => cnt1_eq_addsub0000(10),
      I5 => cnt1_eq_addsub0000(11),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(3)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(2),
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(3),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(3)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(23),
      I1 => cnt1(22),
      I2 => cnt1(21),
      I3 => cnt1_eq_addsub0000(12),
      I4 => cnt1_eq_addsub0000(13),
      I5 => cnt1_eq_addsub0000(14),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(4)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(3),
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(4),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(4)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_5_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cnt1(24),
      I1 => cnt1_eq_addsub0000(15),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(5)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(4),
      DI => data_error_153_Q,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(5),
      O => cnt1_eq_cmp_eq0000
    );
  gen_data_error_0_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(0),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_0_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(0)
    );
  gen_data_error_1_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(1),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_1_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(1)
    );
  gen_data_error_2_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(2),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_2_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(2)
    );
  gen_data_error_3_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(3),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_3_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(3)
    );
  gen_data_error_4_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(4),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_4_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(4)
    );
  gen_data_error_5_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(5),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_5_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(5)
    );
  gen_data_error_6_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(6),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_6_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(6)
    );
  gen_data_error_7_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(7),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_7_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(7)
    );
  gen_data_error_8_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(8),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_8_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(8)
    );
  gen_data_error_9_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(9),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_9_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(9)
    );
  gen_data_error_10_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(10),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_10_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(10)
    );
  gen_data_error_11_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(11),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_11_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(11)
    );
  gen_data_error_12_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(12),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_12_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(12)
    );
  gen_data_error_13_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(13),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_13_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(13)
    );
  gen_data_error_14_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(14),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_14_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(14)
    );
  gen_data_error_15_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(15),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_15_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(15)
    );
  gen_data_error_16_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(16),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_16_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(16)
    );
  gen_data_error_17_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(17),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_17_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(17)
    );
  gen_data_error_18_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(18),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_18_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(18)
    );
  gen_data_error_19_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(19),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_19_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(19)
    );
  gen_data_error_20_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(20),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_20_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(20)
    );
  gen_data_error_21_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(21),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_21_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(21)
    );
  gen_data_error_22_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(22),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_22_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(22)
    );
  gen_data_error_23_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(23),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_23_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(23)
    );
  gen_data_error_24_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(24),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_24_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(24)
    );
  gen_data_error_25_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(25),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_25_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(25)
    );
  gen_data_error_26_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(26),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_26_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(26)
    );
  gen_data_error_27_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(27),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_27_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(27)
    );
  gen_data_error_28_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(28),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_28_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(28)
    );
  gen_data_error_29_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(29),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_29_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(29)
    );
  gen_data_error_30_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(30),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_30_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(30)
    );
  gen_data_error_31_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(31),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_31_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(31)
    );
  gen_data_error_32_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(32),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_32_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(32)
    );
  gen_data_error_33_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(33),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_33_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(33)
    );
  gen_data_error_34_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(34),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_34_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(34)
    );
  gen_data_error_35_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(35),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_35_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(35)
    );
  gen_data_error_36_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(36),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_36_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(36)
    );
  gen_data_error_37_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(37),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_37_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(37)
    );
  gen_data_error_38_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(38),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_38_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(38)
    );
  gen_data_error_39_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(39),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_39_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(39)
    );
  gen_data_error_40_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(40),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_40_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(40)
    );
  gen_data_error_41_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(41),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_41_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(41)
    );
  gen_data_error_42_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(42),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_42_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(42)
    );
  gen_data_error_43_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(43),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_43_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(43)
    );
  gen_data_error_44_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(44),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_44_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(44)
    );
  gen_data_error_45_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(45),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_45_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(45)
    );
  gen_data_error_46_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(46),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_46_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(46)
    );
  gen_data_error_47_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(47),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_47_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(47)
    );
  gen_data_error_48_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(48),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_48_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(48)
    );
  gen_data_error_49_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(49),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_49_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(49)
    );
  gen_data_error_50_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(50),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_50_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(50)
    );
  gen_data_error_51_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(51),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_51_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(51)
    );
  gen_data_error_52_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(52),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_52_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(52)
    );
  gen_data_error_53_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(53),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_53_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(53)
    );
  gen_data_error_54_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(54),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_54_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(54)
    );
  gen_data_error_55_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(55),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_55_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(55)
    );
  gen_data_error_56_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(56),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_56_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(56)
    );
  gen_data_error_57_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(57),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_57_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(57)
    );
  gen_data_error_58_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(58),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_58_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(58)
    );
  gen_data_error_59_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(59),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_59_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(59)
    );
  gen_data_error_60_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(60),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_60_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(60)
    );
  gen_data_error_61_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(61),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_61_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(61)
    );
  gen_data_error_62_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(62),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_62_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(62)
    );
  gen_data_error_63_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => do_data_z(63),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_63_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(63)
    );
  gen_data_error_64_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(0),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_64_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(64)
    );
  gen_data_error_65_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(1),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_65_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(65)
    );
  gen_data_error_66_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(2),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_66_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(66)
    );
  gen_data_error_67_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(3),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_67_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(67)
    );
  gen_data_error_68_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(4),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_68_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(68)
    );
  gen_data_error_69_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(5),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_69_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(69)
    );
  gen_data_error_70_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(6),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_70_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(70)
    );
  gen_data_error_71_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(7),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_71_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(71)
    );
  gen_data_error_72_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(8),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_72_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(72)
    );
  gen_data_error_73_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(9),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_73_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(73)
    );
  gen_data_error_74_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(10),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_74_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(74)
    );
  gen_data_error_75_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(11),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_75_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(75)
    );
  gen_data_error_76_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(12),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_76_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(76)
    );
  gen_data_error_77_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(13),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_77_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(77)
    );
  gen_data_error_78_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(14),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_78_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(78)
    );
  gen_data_error_79_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(15),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_79_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(79)
    );
  gen_data_error_80_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(16),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_80_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(80)
    );
  gen_data_error_81_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(17),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_81_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(81)
    );
  gen_data_error_82_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(18),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_82_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(82)
    );
  gen_data_error_83_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(19),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_83_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(83)
    );
  gen_data_error_84_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(20),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_84_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(84)
    );
  gen_data_error_85_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(21),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_85_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(85)
    );
  gen_data_error_86_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(22),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_86_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(86)
    );
  gen_data_error_87_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(23),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_87_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(87)
    );
  gen_data_error_88_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(24),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_88_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(88)
    );
  gen_data_error_89_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(25),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_89_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(89)
    );
  gen_data_error_90_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(26),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_90_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(90)
    );
  gen_data_error_91_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(27),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_91_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(91)
    );
  gen_data_error_92_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(28),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_92_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(92)
    );
  gen_data_error_93_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(29),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_93_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(93)
    );
  gen_data_error_94_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(30),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_94_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(94)
    );
  gen_data_error_95_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(31),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_95_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(95)
    );
  gen_data_error_96_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(32),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_96_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(96)
    );
  gen_data_error_97_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(33),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_97_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(97)
    );
  gen_data_error_98_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(34),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_98_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(98)
    );
  gen_data_error_99_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(35),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_99_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(99)
    );
  gen_data_error_100_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(36),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_100_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(100)
    );
  gen_data_error_101_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(37),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_101_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(101)
    );
  gen_data_error_102_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(38),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_102_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(102)
    );
  gen_data_error_103_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(39),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_103_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(103)
    );
  gen_data_error_104_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(40),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_104_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(104)
    );
  gen_data_error_105_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(41),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_105_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(105)
    );
  gen_data_error_106_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(42),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_106_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(106)
    );
  gen_data_error_107_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(43),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_107_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(107)
    );
  gen_data_error_108_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(44),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_108_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(108)
    );
  gen_data_error_109_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(45),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_109_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(109)
    );
  gen_data_error_110_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(46),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_110_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(110)
    );
  gen_data_error_111_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(47),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_111_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(111)
    );
  gen_data_error_112_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(48),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_112_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(112)
    );
  gen_data_error_113_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(49),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_113_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(113)
    );
  gen_data_error_114_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(50),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_114_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(114)
    );
  gen_data_error_115_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(51),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_115_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(115)
    );
  gen_data_error_116_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(52),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_116_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(116)
    );
  gen_data_error_117_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(53),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_117_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(117)
    );
  gen_data_error_118_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(54),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_118_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(118)
    );
  gen_data_error_119_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(55),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_119_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(119)
    );
  gen_data_error_120_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(56),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_120_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(120)
    );
  gen_data_error_121_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(57),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_121_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(121)
    );
  gen_data_error_122_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(58),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_122_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(122)
    );
  gen_data_error_123_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(59),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_123_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(123)
    );
  gen_data_error_124_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(60),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_124_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(124)
    );
  gen_data_error_125_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(61),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_125_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(125)
    );
  gen_data_error_126_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(62),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_126_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(126)
    );
  gen_data_error_127_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_expect(63),
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_127_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(127)
    );
  gen_data_error_128_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_128_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_128_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(128)
    );
  gen_data_error_129_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_129_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_129_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(129)
    );
  gen_data_error_130_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_130_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_130_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(130)
    );
  gen_data_error_131_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_131_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_131_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(131)
    );
  gen_data_error_132_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_132_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_132_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(132)
    );
  gen_data_error_133_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_133_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_133_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(133)
    );
  gen_data_error_134_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_134_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_134_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(134)
    );
  gen_data_error_135_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_135_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_135_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(135)
    );
  gen_data_error_136_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_136_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_136_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(136)
    );
  gen_data_error_137_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_137_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_137_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(137)
    );
  gen_data_error_138_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_138_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_138_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(138)
    );
  gen_data_error_139_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_139_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_139_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(139)
    );
  gen_data_error_140_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_140_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_140_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(140)
    );
  gen_data_error_141_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_141_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_141_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(141)
    );
  gen_data_error_142_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_142_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_142_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(142)
    );
  gen_data_error_143_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_143_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_143_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(143)
    );
  gen_data_error_144_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_144_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_144_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(144)
    );
  gen_data_error_145_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_145_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_145_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(145)
    );
  gen_data_error_146_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_146_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_146_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(146)
    );
  gen_data_error_147_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_147_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_147_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(147)
    );
  gen_data_error_148_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_148_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_148_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(148)
    );
  gen_data_error_149_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_149_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_149_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(149)
    );
  gen_data_error_150_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_150_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_150_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(150)
    );
  gen_data_error_151_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_151_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_151_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(151)
    );
  gen_data_error_152_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_152_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_152_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(152)
    );
  gen_data_error_153_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_153_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(153)
    );
  gen_data_error_154_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_154_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(154)
    );
  gen_data_error_155_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_155_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(155)
    );
  gen_data_error_156_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_156_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(156)
    );
  gen_data_error_157_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_157_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(157)
    );
  gen_data_error_158_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_158_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(158)
    );
  gen_data_error_159_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_153_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_159_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(159)
    );
  gen_data_error_160_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_160_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_160_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(160)
    );
  gen_data_error_161_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_161_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_161_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(161)
    );
  gen_data_error_162_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_162_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_162_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(162)
    );
  gen_data_error_163_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_163_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_163_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(163)
    );
  gen_data_error_164_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_164_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_164_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(164)
    );
  gen_data_error_165_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_165_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_165_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(165)
    );
  gen_data_error_166_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_166_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_166_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(166)
    );
  gen_data_error_167_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_167_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_167_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(167)
    );
  gen_data_error_168_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_168_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_168_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(168)
    );
  gen_data_error_169_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_169_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_169_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(169)
    );
  gen_data_error_170_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_170_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_170_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(170)
    );
  gen_data_error_171_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_171_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_171_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(171)
    );
  gen_data_error_172_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_172_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_172_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(172)
    );
  gen_data_error_173_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_173_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_173_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(173)
    );
  gen_data_error_174_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_174_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_174_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(174)
    );
  gen_data_error_175_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_175_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_175_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(175)
    );
  gen_data_error_176_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_176_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_176_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(176)
    );
  gen_data_error_177_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_177_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_177_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(177)
    );
  gen_data_error_178_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_178_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_178_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(178)
    );
  gen_data_error_179_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_179_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_179_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(179)
    );
  gen_data_error_180_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_180_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_180_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(180)
    );
  gen_data_error_181_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_181_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_181_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(181)
    );
  gen_data_error_182_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_182_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_182_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(182)
    );
  gen_data_error_183_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_183_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_183_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(183)
    );
  gen_data_error_184_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_184_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_184_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(184)
    );
  gen_data_error_185_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_185_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_185_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(185)
    );
  gen_data_error_186_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_186_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_186_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(186)
    );
  gen_data_error_187_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_187_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_187_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(187)
    );
  gen_data_error_188_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_188_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_188_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(188)
    );
  gen_data_error_189_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_189_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_189_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(189)
    );
  gen_data_error_190_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_190_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_190_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(190)
    );
  gen_data_error_191_ram0 : RAM16X1D
    generic map(
      INIT => X"0000"
    )
    port map (
      A0 => NlwRenamedSig_OI_total_err(0),
      A1 => NlwRenamedSig_OI_total_err(1),
      A2 => NlwRenamedSig_OI_total_err(2),
      A3 => NlwRenamedSig_OI_total_err(3),
      D => data_error_191_Q,
      DPRA0 => test_check_err_adr(4),
      DPRA1 => test_check_err_adr(5),
      DPRA2 => test_check_err_adr(6),
      DPRA3 => test_check_err_adr(7),
      WCLK => do_clk,
      WE => data_error_wr1_3654,
      SPO => NLW_gen_data_error_191_ram0_SPO_UNCONNECTED,
      DPO => data_error_out(191)
    );
  Mcount_block_mode_xor_0_11 : LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      I0 => test_check_ctrl(7),
      I1 => block_mode(0),
      I2 => test_check_ctrl(8),
      O => Mcount_block_mode
    );
  Mxor_data_ex5_0_xor0000_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => data_ex5(59),
      I1 => data_ex5(60),
      I2 => data_ex5(62),
      I3 => data_ex5(63),
      O => data_ex5_0_xor0000
    );
  Mcount_block_mode_xor_1_11 : LUT4
    generic map(
      INIT => X"BE14"
    )
    port map (
      I0 => test_check_ctrl(7),
      I1 => block_mode(0),
      I2 => block_mode(1),
      I3 => test_check_ctrl(9),
      O => Mcount_block_mode1
    );
  Mcount_block_mode_xor_2_11 : LUT5
    generic map(
      INIT => X"BEEE1444"
    )
    port map (
      I0 => test_check_ctrl(7),
      I1 => block_mode(2),
      I2 => block_mode(0),
      I3 => block_mode(1),
      I4 => test_check_ctrl(10),
      O => Mcount_block_mode2
    );
  Mcount_block_mode_xor_3_11 : LUT6
    generic map(
      INIT => X"BEEEEEEE14444444"
    )
    port map (
      I0 => test_check_ctrl(7),
      I1 => block_mode(3),
      I2 => block_mode(0),
      I3 => block_mode(1),
      I4 => block_mode(2),
      I5 => test_check_ctrl(11),
      O => Mcount_block_mode3
    );
  data_expect_3_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => do_data_en,
      I1 => reset,
      I2 => test_check_ctrl(0),
      O => data_expect_3_not0001
    );
  block_ok_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => block_ok_en_3318,
      I1 => flag_error_clr_4749,
      I2 => flag_error_4748,
      O => block_ok_not0001
    );
  block_err_not00011 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => flag_error_clr_4749,
      I1 => flag_error_4748,
      I2 => block_ok_en_3318,
      O => block_err_not0001
    );
  rst_inv2011 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => test_check_ctrl(0),
      O => rst_inv
    );
  data_ex3_or00001 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => reset,
      I2 => do_data_en,
      I3 => test_check_ctrl(0),
      O => data_ex3_not0001_inv
    );
  data_ex1_36_not0001_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => reset,
      I1 => do_data_en,
      O => N0
    );
  data_ex1_36_not0001 : LUT6
    generic map(
      INIT => X"080808080A080808"
    )
    port map (
      I0 => N0,
      I1 => cnt1_z_3399,
      I2 => test_check_ctrl(0),
      I3 => cnt1(0),
      I4 => N80,
      I5 => block_mode(2),
      O => data_ex1_36_not0001_3845
    );
  block_rd_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => do_data_en,
      I1 => cnt1_eq_3379,
      O => block_rd_and0000
    );
  data_ex4_32_not00016 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => data_ex4(19),
      I1 => data_ex4(1),
      I2 => data_ex4(0),
      I3 => data_ex4(10),
      O => data_ex4_32_not00016_4237
    );
  data_ex4_32_not000123 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(18),
      I1 => data_ex4(17),
      I2 => data_ex4(16),
      I3 => data_ex4(15),
      I4 => data_ex4_32_not00016_4237,
      I5 => data_ex4_10_not0001,
      O => data_ex4_32_not000123_4234
    );
  data_ex4_32_not000137 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(28),
      I1 => data_ex4(29),
      I2 => data_ex4(2),
      I3 => data_ex4(30),
      I4 => data_ex4(20),
      I5 => data_ex4(21),
      O => data_ex4_32_not000137_4235
    );
  data_ex4_32_not000148 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(11),
      I1 => data_ex4(12),
      I2 => data_ex4(13),
      I3 => data_ex4(14),
      I4 => data_ex4(26),
      I5 => data_ex4(27),
      O => data_ex4_32_not000148_4236
    );
  data_ex4_32_not000170 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(4),
      I1 => data_ex4(5),
      I2 => data_ex4(6),
      I3 => data_ex4(7),
      I4 => data_ex4(8),
      I5 => data_ex4(9),
      O => data_ex4_32_not000170_4238
    );
  data_ex4_32_not000181 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(22),
      I1 => data_ex4(23),
      I2 => data_ex4(24),
      I3 => data_ex4(25),
      I4 => data_ex4(31),
      I5 => data_ex4(3),
      O => data_ex4_32_not000181_4239
    );
  block_mode_or0000_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => block_mode(0),
      I1 => do_data_en,
      I2 => test_check_ctrl(7),
      O => N2
    );
  block_mode_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFF5555D555"
    )
    port map (
      I0 => reset,
      I1 => block_mode(3),
      I2 => cnt1_eq_3379,
      I3 => N63,
      I4 => N2,
      I5 => test_check_ctrl(0),
      O => block_mode_or0000_3285
    );
  data_ex2_0_not00011 : LUT6
    generic map(
      INIT => X"4040400040004000"
    )
    port map (
      I0 => test_check_ctrl(0),
      I1 => reset,
      I2 => do_data_en,
      I3 => cnt1_z_3399,
      I4 => data_ex3_and0000,
      I5 => data_expect_3_cmp_eq0006,
      O => data_ex2_0_not0001
    );
  data_ex4_32_not0001112 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(1),
      O => N80
    );
  data_ex2_0_not0001111 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => block_mode(1),
      O => data_ex3_and0000
    );
  data_expect_8_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(8),
      I1 => data_expect(8),
      I2 => data_ex0(8),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_8_mux000031_4598
    );
  data_expect_5_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(5),
      I1 => data_expect(5),
      I2 => data_ex0(5),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_5_mux000031_4573
    );
  data_expect_31_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(31),
      I1 => data_expect(31),
      I2 => data_ex0(31),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_31_mux000031_4450
    );
  data_expect_29_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(29),
      I1 => data_expect(29),
      I2 => data_ex0(29),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_29_mux000031_4441
    );
  data_expect_26_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(26),
      I1 => data_expect(26),
      I2 => data_ex0(26),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_26_mux000031_4432
    );
  data_expect_24_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(24),
      I1 => data_expect(24),
      I2 => data_ex0(24),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_24_mux000031_4426
    );
  data_expect_23_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(23),
      I1 => data_expect(23),
      I2 => data_ex0(23),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_23_mux000031_4423
    );
  data_expect_21_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(21),
      I1 => data_expect(21),
      I2 => data_ex0(21),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_21_mux000031_4417
    );
  data_expect_1_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(1),
      I1 => data_expect(1),
      I2 => data_ex0(1),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_1_mux000031_4410
    );
  data_expect_18_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(18),
      I1 => data_expect(18),
      I2 => data_ex0(18),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_18_mux000031_4405
    );
  data_expect_16_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(16),
      I1 => data_expect(16),
      I2 => data_ex0(16),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_16_mux000031_4399
    );
  data_expect_0_mux000031 : LUT6
    generic map(
      INIT => X"FFAAFFF0FFCCFF00"
    )
    port map (
      I0 => data_ex5(0),
      I1 => data_expect(0),
      I2 => data_ex0(0),
      I3 => cnt1_z_3399,
      I4 => block_mode(3),
      I5 => N63,
      O => data_expect_0_mux000031_4377
    );
  block_mode_or000011 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => block_mode(1),
      I1 => block_mode(2),
      O => N63
    );
  data_expect_9_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(9),
      I1 => data_ex2(9),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_9_mux000099_4601,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_9_mux0000
    );
  data_expect_7_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(7),
      I1 => data_ex2(7),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_7_mux000099_4595,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_7_mux0000
    );
  data_expect_6_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(6),
      I1 => data_ex2(6),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_6_mux000099_4592,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_6_mux0000
    );
  data_expect_4_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(4),
      I1 => data_ex2(4),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_4_mux000099_4530,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_4_mux0000
    );
  data_expect_3_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(3),
      I1 => data_ex2(3),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_3_mux000099_4486,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_3_mux0000
    );
  data_expect_30_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(30),
      I1 => data_ex2(30),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_30_mux000099_4447,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_30_mux0000
    );
  data_expect_2_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(2),
      I1 => data_ex2(2),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_2_mux000099_4443,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_2_mux0000
    );
  data_expect_28_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(28),
      I1 => data_ex2(28),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_28_mux000099_4438,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_28_mux0000
    );
  data_expect_27_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(27),
      I1 => data_ex2(27),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_27_mux000099_4435,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_27_mux0000
    );
  data_expect_25_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(25),
      I1 => data_ex2(25),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_25_mux000099_4429,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_25_mux0000
    );
  data_expect_22_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(22),
      I1 => data_ex2(22),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_22_mux000099_4420,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_22_mux0000
    );
  data_expect_20_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(20),
      I1 => data_ex2(20),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_20_mux000099_4414,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_20_mux0000
    );
  data_expect_19_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(19),
      I1 => data_ex2(19),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_19_mux000099_4408,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_19_mux0000
    );
  data_expect_17_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(17),
      I1 => data_ex2(17),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_17_mux000099_4402,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_17_mux0000
    );
  data_expect_15_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(15),
      I1 => data_ex2(15),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_15_mux000099_4396,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_15_mux0000
    );
  data_expect_14_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(14),
      I1 => data_ex2(14),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_14_mux000099_4393,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_14_mux0000
    );
  data_expect_13_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(13),
      I1 => data_ex2(13),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_13_mux000099_4390,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_13_mux0000
    );
  data_expect_12_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(12),
      I1 => data_ex2(12),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_12_mux000099_4387,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_12_mux0000
    );
  data_expect_11_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(11),
      I1 => data_ex2(11),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_11_mux000099_4384,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_11_mux0000
    );
  data_expect_10_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(10),
      I1 => data_ex2(10),
      I2 => cnt1_z_3399,
      I3 => data_ex3_and0000,
      I4 => data_expect_10_mux000099_4381,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_10_mux0000
    );
  total_err_and000035 : LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(28),
      I1 => NlwRenamedSig_OI_total_err(29),
      I2 => NlwRenamedSig_OI_total_err(9),
      I3 => NlwRenamedSig_OI_total_err(8),
      I4 => NlwRenamedSig_OI_total_err(7),
      I5 => NlwRenamedSig_OI_total_err(6),
      O => total_err_and000035_4836
    );
  total_err_and000071 : LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(4),
      I1 => NlwRenamedSig_OI_total_err(5),
      I2 => NlwRenamedSig_OI_total_err(21),
      I3 => NlwRenamedSig_OI_total_err(20),
      I4 => NlwRenamedSig_OI_total_err(1),
      I5 => NlwRenamedSig_OI_total_err(19),
      O => total_err_and000071_4837
    );
  total_err_and0000128 : LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(13),
      I1 => NlwRenamedSig_OI_total_err(14),
      I2 => NlwRenamedSig_OI_total_err(15),
      I3 => NlwRenamedSig_OI_total_err(16),
      I4 => NlwRenamedSig_OI_total_err(10),
      I5 => NlwRenamedSig_OI_total_err(0),
      O => total_err_and0000128_4831
    );
  total_err_and0000164 : LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(11),
      I1 => NlwRenamedSig_OI_total_err(12),
      I2 => NlwRenamedSig_OI_total_err(3),
      I3 => NlwRenamedSig_OI_total_err(31),
      I4 => NlwRenamedSig_OI_total_err(30),
      I5 => NlwRenamedSig_OI_total_err(2),
      O => total_err_and0000164_4832
    );
  total_err_and0000240 : LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(17),
      I1 => NlwRenamedSig_OI_total_err(18),
      I2 => NlwRenamedSig_OI_total_err(27),
      I3 => NlwRenamedSig_OI_total_err(26),
      I4 => NlwRenamedSig_OI_total_err(25),
      I5 => NlwRenamedSig_OI_total_err(24),
      O => total_err_and0000240_4833
    );
  total_err_and0000244 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(22),
      I1 => NlwRenamedSig_OI_total_err(23),
      O => total_err_and0000244_4834
    );
  total_err_and0000262 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => total_err_and0000244_4834,
      I1 => total_err_and0000240_4833,
      I2 => total_err_and0000164_4832,
      I3 => total_err_and000071_4837,
      I4 => total_err_and000035_4836,
      I5 => total_err_and0000128_4831,
      O => total_err_and0000262_4835
    );
  total_err_and0000277 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => data_en_z_3400,
      I1 => word_error,
      I2 => total_err_and0000262_4835,
      O => total_err_and0000
    );
  cnt1_eq_and0000_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => cnt1(5),
      I1 => cnt1(4),
      I2 => cnt1(3),
      I3 => cnt1(2),
      I4 => cnt1(8),
      O => N4
    );
  cnt1_eq_and0000 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => cnt1(6),
      I1 => cnt1(1),
      I2 => cnt1(7),
      I3 => cnt1(0),
      I4 => N4,
      I5 => cnt1_eq_cmp_eq0000,
      O => cnt1_eq_and0000_3396
    );
  data_expect_63_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(63),
      I1 => data_ex2(63),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_63_mux0000114_4589
    );
  data_expect_62_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(62),
      I1 => data_ex2(62),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_62_mux0000114_4585
    );
  data_expect_61_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(61),
      I1 => data_ex2(61),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_61_mux0000114_4581
    );
  data_expect_60_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(60),
      I1 => data_ex2(60),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_60_mux0000114_4577
    );
  data_expect_59_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(59),
      I1 => data_ex2(59),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_59_mux0000114_4570
    );
  data_expect_58_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(58),
      I1 => data_ex2(58),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_58_mux0000114_4566
    );
  data_expect_57_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(57),
      I1 => data_ex2(57),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_57_mux0000114_4562
    );
  data_expect_56_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(56),
      I1 => data_ex2(56),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_56_mux0000114_4558
    );
  data_expect_55_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(55),
      I1 => data_ex2(55),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_55_mux0000114_4554
    );
  data_expect_54_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(54),
      I1 => data_ex2(54),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_54_mux0000114_4550
    );
  data_expect_53_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(53),
      I1 => data_ex2(53),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_53_mux0000114_4546
    );
  data_expect_52_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(52),
      I1 => data_ex2(52),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_52_mux0000114_4542
    );
  data_expect_51_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(51),
      I1 => data_ex2(51),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_51_mux0000114_4538
    );
  data_expect_50_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(50),
      I1 => data_ex2(50),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_50_mux0000114_4534
    );
  data_expect_49_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(49),
      I1 => data_ex2(49),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_49_mux0000114_4527
    );
  data_expect_48_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(48),
      I1 => data_ex2(48),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_48_mux0000114_4523
    );
  data_expect_47_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(47),
      I1 => data_ex2(47),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_47_mux0000114_4519
    );
  data_expect_46_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(46),
      I1 => data_ex2(46),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_46_mux0000114_4515
    );
  data_expect_45_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(45),
      I1 => data_ex2(45),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_45_mux0000114_4511
    );
  data_expect_44_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(44),
      I1 => data_ex2(44),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_44_mux0000114_4507
    );
  data_expect_43_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(43),
      I1 => data_ex2(43),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_43_mux0000114_4503
    );
  data_expect_42_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(42),
      I1 => data_ex2(42),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_42_mux0000114_4499
    );
  data_expect_41_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(41),
      I1 => data_ex2(41),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_41_mux0000114_4495
    );
  data_expect_40_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(40),
      I1 => data_ex2(40),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_40_mux0000114_4491
    );
  data_expect_39_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(39),
      I1 => data_ex2(39),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_39_mux0000114_4481
    );
  data_expect_38_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(38),
      I1 => data_ex2(38),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_38_mux0000114_4477
    );
  data_expect_37_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(37),
      I1 => data_ex2(37),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_37_mux0000114_4473
    );
  data_expect_36_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(36),
      I1 => data_ex2(36),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_36_mux0000114_4469
    );
  data_expect_35_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(35),
      I1 => data_ex2(35),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_35_mux0000114_4465
    );
  data_expect_34_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(34),
      I1 => data_ex2(34),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_34_mux0000114_4461
    );
  data_expect_33_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(33),
      I1 => data_ex2(33),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_33_mux0000114_4457
    );
  data_expect_32_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(32),
      I1 => data_ex2(32),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_32_mux0000114_4453
    );
  test_check_err_adr_3_9_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(147),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(163),
      I4 => data_error_out(131),
      I5 => data_error_out(179),
      O => N6
    );
  test_check_err_adr_3_9 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N6,
      I2 => Mmux_err_data_5_f79,
      O => err_data(3)
    );
  test_check_err_adr_3_8_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(146),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(162),
      I4 => data_error_out(130),
      I5 => data_error_out(178),
      O => N8
    );
  test_check_err_adr_3_8 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N8,
      I2 => Mmux_err_data_5_f78,
      O => err_data(2)
    );
  test_check_err_adr_3_7_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(145),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(161),
      I4 => data_error_out(129),
      I5 => data_error_out(177),
      O => N10
    );
  test_check_err_adr_3_7 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N10,
      I2 => Mmux_err_data_5_f77,
      O => err_data(1)
    );
  test_check_err_adr_3_6_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(159),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(175),
      I4 => data_error_out(143),
      I5 => data_error_out(191),
      O => N12
    );
  test_check_err_adr_3_6 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N12,
      I2 => Mmux_err_data_5_f76,
      O => err_data(15)
    );
  test_check_err_adr_3_5_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(158),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(174),
      I4 => data_error_out(142),
      I5 => data_error_out(190),
      O => N14
    );
  test_check_err_adr_3_5 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N14,
      I2 => Mmux_err_data_5_f75,
      O => err_data(14)
    );
  test_check_err_adr_3_4_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(157),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(173),
      I4 => data_error_out(141),
      I5 => data_error_out(189),
      O => N16
    );
  test_check_err_adr_3_4 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N16,
      I2 => Mmux_err_data_5_f74,
      O => err_data(13)
    );
  test_check_err_adr_3_3_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(156),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(172),
      I4 => data_error_out(140),
      I5 => data_error_out(188),
      O => N18
    );
  test_check_err_adr_3_3 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N18,
      I2 => Mmux_err_data_5_f73,
      O => err_data(12)
    );
  test_check_err_adr_3_2_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(155),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(171),
      I4 => data_error_out(139),
      I5 => data_error_out(187),
      O => N20
    );
  test_check_err_adr_3_2 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N20,
      I2 => Mmux_err_data_5_f72,
      O => err_data(11)
    );
  test_check_err_adr_3_15_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(153),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(169),
      I4 => data_error_out(137),
      I5 => data_error_out(185),
      O => N22
    );
  test_check_err_adr_3_15 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N22,
      I2 => Mmux_err_data_5_f715,
      O => err_data(9)
    );
  test_check_err_adr_3_14_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(152),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(168),
      I4 => data_error_out(136),
      I5 => data_error_out(184),
      O => N24
    );
  test_check_err_adr_3_14 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N24,
      I2 => Mmux_err_data_5_f714,
      O => err_data(8)
    );
  test_check_err_adr_3_13_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(151),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(167),
      I4 => data_error_out(135),
      I5 => data_error_out(183),
      O => N26
    );
  test_check_err_adr_3_13 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N26,
      I2 => Mmux_err_data_5_f713,
      O => err_data(7)
    );
  test_check_err_adr_3_12_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(150),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(166),
      I4 => data_error_out(134),
      I5 => data_error_out(182),
      O => N28
    );
  test_check_err_adr_3_12 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N28,
      I2 => Mmux_err_data_5_f712,
      O => err_data(6)
    );
  test_check_err_adr_3_11_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(149),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(165),
      I4 => data_error_out(133),
      I5 => data_error_out(181),
      O => N30
    );
  test_check_err_adr_3_11 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N30,
      I2 => Mmux_err_data_5_f711,
      O => err_data(5)
    );
  test_check_err_adr_3_10_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(148),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(164),
      I4 => data_error_out(132),
      I5 => data_error_out(180),
      O => N32
    );
  test_check_err_adr_3_10 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N32,
      I2 => Mmux_err_data_5_f710,
      O => err_data(4)
    );
  test_check_err_adr_3_1_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(154),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(170),
      I4 => data_error_out(138),
      I5 => data_error_out(186),
      O => N34
    );
  test_check_err_adr_3_1 : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N34,
      I2 => Mmux_err_data_5_f71,
      O => err_data(10)
    );
  test_check_err_adr_3_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => test_check_err_adr(1),
      I1 => data_error_out(144),
      I2 => test_check_err_adr(0),
      I3 => data_error_out(160),
      I4 => data_error_out(128),
      I5 => data_error_out(176),
      O => N36
    );
  test_check_err_adr_3_Q : LUT3
    generic map(
      INIT => X"D8"
    )
    port map (
      I0 => test_check_err_adr(3),
      I1 => N36,
      I2 => Mmux_err_data_5_f7_2864,
      O => err_data(0)
    );
  data_expect_3_cmp_eq00068126 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => cnt1(7),
      I1 => NlwRenamedSig_OI_block_rd(7),
      I2 => cnt1(0),
      I3 => NlwRenamedSig_OI_block_rd(0),
      I4 => cnt1(1),
      I5 => NlwRenamedSig_OI_block_rd(1),
      O => data_expect_3_cmp_eq00068126_4484
    );
  data_error_wr1 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data_en_z_3400,
      I1 => word_error,
      O => data_error_wr
    );
  Madd_data_ex4_63_32_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(33),
      O => Madd_data_ex4_63_32_add0000_cy_1_rt_2466
    );
  Madd_data_ex4_63_32_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(34),
      O => Madd_data_ex4_63_32_add0000_cy_2_rt_2488
    );
  Madd_data_ex4_63_32_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(35),
      O => Madd_data_ex4_63_32_add0000_cy_3_rt_2492
    );
  Madd_data_ex4_63_32_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(36),
      O => Madd_data_ex4_63_32_add0000_cy_4_rt_2494
    );
  Madd_data_ex4_63_32_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(37),
      O => Madd_data_ex4_63_32_add0000_cy_5_rt_2496
    );
  Madd_data_ex4_63_32_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(38),
      O => Madd_data_ex4_63_32_add0000_cy_6_rt_2498
    );
  Madd_data_ex4_63_32_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(39),
      O => Madd_data_ex4_63_32_add0000_cy_7_rt_2500
    );
  Madd_data_ex4_63_32_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(40),
      O => Madd_data_ex4_63_32_add0000_cy_8_rt_2502
    );
  Madd_data_ex4_63_32_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(41),
      O => Madd_data_ex4_63_32_add0000_cy_9_rt_2504
    );
  Madd_data_ex4_63_32_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(42),
      O => Madd_data_ex4_63_32_add0000_cy_10_rt_2446
    );
  Madd_data_ex4_63_32_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(43),
      O => Madd_data_ex4_63_32_add0000_cy_11_rt_2448
    );
  Madd_data_ex4_63_32_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(44),
      O => Madd_data_ex4_63_32_add0000_cy_12_rt_2450
    );
  Madd_data_ex4_63_32_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(45),
      O => Madd_data_ex4_63_32_add0000_cy_13_rt_2452
    );
  Madd_data_ex4_63_32_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(46),
      O => Madd_data_ex4_63_32_add0000_cy_14_rt_2454
    );
  Madd_data_ex4_63_32_add0000_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(47),
      O => Madd_data_ex4_63_32_add0000_cy_15_rt_2456
    );
  Madd_data_ex4_63_32_add0000_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(48),
      O => Madd_data_ex4_63_32_add0000_cy_16_rt_2458
    );
  Madd_data_ex4_63_32_add0000_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(49),
      O => Madd_data_ex4_63_32_add0000_cy_17_rt_2460
    );
  Madd_data_ex4_63_32_add0000_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(50),
      O => Madd_data_ex4_63_32_add0000_cy_18_rt_2462
    );
  Madd_data_ex4_63_32_add0000_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(51),
      O => Madd_data_ex4_63_32_add0000_cy_19_rt_2464
    );
  Madd_data_ex4_63_32_add0000_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(52),
      O => Madd_data_ex4_63_32_add0000_cy_20_rt_2468
    );
  Madd_data_ex4_63_32_add0000_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(53),
      O => Madd_data_ex4_63_32_add0000_cy_21_rt_2470
    );
  Madd_data_ex4_63_32_add0000_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(54),
      O => Madd_data_ex4_63_32_add0000_cy_22_rt_2472
    );
  Madd_data_ex4_63_32_add0000_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(55),
      O => Madd_data_ex4_63_32_add0000_cy_23_rt_2474
    );
  Madd_data_ex4_63_32_add0000_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(56),
      O => Madd_data_ex4_63_32_add0000_cy_24_rt_2476
    );
  Madd_data_ex4_63_32_add0000_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(57),
      O => Madd_data_ex4_63_32_add0000_cy_25_rt_2478
    );
  Madd_data_ex4_63_32_add0000_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(58),
      O => Madd_data_ex4_63_32_add0000_cy_26_rt_2480
    );
  Madd_data_ex4_63_32_add0000_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(59),
      O => Madd_data_ex4_63_32_add0000_cy_27_rt_2482
    );
  Madd_data_ex4_63_32_add0000_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(60),
      O => Madd_data_ex4_63_32_add0000_cy_28_rt_2484
    );
  Madd_data_ex4_63_32_add0000_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(61),
      O => Madd_data_ex4_63_32_add0000_cy_29_rt_2486
    );
  Madd_data_ex4_63_32_add0000_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(62),
      O => Madd_data_ex4_63_32_add0000_cy_30_rt_2490
    );
  Madd_data_ex4_31_0_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(1),
      O => Madd_data_ex4_31_0_add0000_cy_1_rt_2403
    );
  Madd_data_ex4_31_0_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(2),
      O => Madd_data_ex4_31_0_add0000_cy_2_rt_2425
    );
  Madd_data_ex4_31_0_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(3),
      O => Madd_data_ex4_31_0_add0000_cy_3_rt_2429
    );
  Madd_data_ex4_31_0_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(4),
      O => Madd_data_ex4_31_0_add0000_cy_4_rt_2431
    );
  Madd_data_ex4_31_0_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(5),
      O => Madd_data_ex4_31_0_add0000_cy_5_rt_2433
    );
  Madd_data_ex4_31_0_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(6),
      O => Madd_data_ex4_31_0_add0000_cy_6_rt_2435
    );
  Madd_data_ex4_31_0_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(7),
      O => Madd_data_ex4_31_0_add0000_cy_7_rt_2437
    );
  Madd_data_ex4_31_0_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(8),
      O => Madd_data_ex4_31_0_add0000_cy_8_rt_2439
    );
  Madd_data_ex4_31_0_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(9),
      O => Madd_data_ex4_31_0_add0000_cy_9_rt_2441
    );
  Madd_data_ex4_31_0_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(10),
      O => Madd_data_ex4_31_0_add0000_cy_10_rt_2383
    );
  Madd_data_ex4_31_0_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(11),
      O => Madd_data_ex4_31_0_add0000_cy_11_rt_2385
    );
  Madd_data_ex4_31_0_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(12),
      O => Madd_data_ex4_31_0_add0000_cy_12_rt_2387
    );
  Madd_data_ex4_31_0_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(13),
      O => Madd_data_ex4_31_0_add0000_cy_13_rt_2389
    );
  Madd_data_ex4_31_0_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(14),
      O => Madd_data_ex4_31_0_add0000_cy_14_rt_2391
    );
  Madd_data_ex4_31_0_add0000_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(15),
      O => Madd_data_ex4_31_0_add0000_cy_15_rt_2393
    );
  Madd_data_ex4_31_0_add0000_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(16),
      O => Madd_data_ex4_31_0_add0000_cy_16_rt_2395
    );
  Madd_data_ex4_31_0_add0000_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(17),
      O => Madd_data_ex4_31_0_add0000_cy_17_rt_2397
    );
  Madd_data_ex4_31_0_add0000_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(18),
      O => Madd_data_ex4_31_0_add0000_cy_18_rt_2399
    );
  Madd_data_ex4_31_0_add0000_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(19),
      O => Madd_data_ex4_31_0_add0000_cy_19_rt_2401
    );
  Madd_data_ex4_31_0_add0000_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(20),
      O => Madd_data_ex4_31_0_add0000_cy_20_rt_2405
    );
  Madd_data_ex4_31_0_add0000_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(21),
      O => Madd_data_ex4_31_0_add0000_cy_21_rt_2407
    );
  Madd_data_ex4_31_0_add0000_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(22),
      O => Madd_data_ex4_31_0_add0000_cy_22_rt_2409
    );
  Madd_data_ex4_31_0_add0000_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(23),
      O => Madd_data_ex4_31_0_add0000_cy_23_rt_2411
    );
  Madd_data_ex4_31_0_add0000_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(24),
      O => Madd_data_ex4_31_0_add0000_cy_24_rt_2413
    );
  Madd_data_ex4_31_0_add0000_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(25),
      O => Madd_data_ex4_31_0_add0000_cy_25_rt_2415
    );
  Madd_data_ex4_31_0_add0000_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(26),
      O => Madd_data_ex4_31_0_add0000_cy_26_rt_2417
    );
  Madd_data_ex4_31_0_add0000_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(27),
      O => Madd_data_ex4_31_0_add0000_cy_27_rt_2419
    );
  Madd_data_ex4_31_0_add0000_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(28),
      O => Madd_data_ex4_31_0_add0000_cy_28_rt_2421
    );
  Madd_data_ex4_31_0_add0000_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(29),
      O => Madd_data_ex4_31_0_add0000_cy_29_rt_2423
    );
  Madd_data_ex4_31_0_add0000_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(30),
      O => Madd_data_ex4_31_0_add0000_cy_30_rt_2427
    );
  Msub_cnt1_eq_addsub0000_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => test_check_size(0),
      O => Msub_cnt1_eq_addsub0000_cy_0_rt_2913
    );
  Mcount_total_err_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(1),
      O => Mcount_total_err_cy_1_rt_2823
    );
  Mcount_total_err_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(2),
      O => Mcount_total_err_cy_2_rt_2845
    );
  Mcount_total_err_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(3),
      O => Mcount_total_err_cy_3_rt_2849
    );
  Mcount_total_err_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(4),
      O => Mcount_total_err_cy_4_rt_2851
    );
  Mcount_total_err_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(5),
      O => Mcount_total_err_cy_5_rt_2853
    );
  Mcount_total_err_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(6),
      O => Mcount_total_err_cy_6_rt_2855
    );
  Mcount_total_err_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(7),
      O => Mcount_total_err_cy_7_rt_2857
    );
  Mcount_total_err_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(8),
      O => Mcount_total_err_cy_8_rt_2859
    );
  Mcount_total_err_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(9),
      O => Mcount_total_err_cy_9_rt_2861
    );
  Mcount_total_err_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(10),
      O => Mcount_total_err_cy_10_rt_2803
    );
  Mcount_total_err_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(11),
      O => Mcount_total_err_cy_11_rt_2805
    );
  Mcount_total_err_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(12),
      O => Mcount_total_err_cy_12_rt_2807
    );
  Mcount_total_err_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(13),
      O => Mcount_total_err_cy_13_rt_2809
    );
  Mcount_total_err_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(14),
      O => Mcount_total_err_cy_14_rt_2811
    );
  Mcount_total_err_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(15),
      O => Mcount_total_err_cy_15_rt_2813
    );
  Mcount_total_err_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(16),
      O => Mcount_total_err_cy_16_rt_2815
    );
  Mcount_total_err_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(17),
      O => Mcount_total_err_cy_17_rt_2817
    );
  Mcount_total_err_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(18),
      O => Mcount_total_err_cy_18_rt_2819
    );
  Mcount_total_err_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(19),
      O => Mcount_total_err_cy_19_rt_2821
    );
  Mcount_total_err_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(20),
      O => Mcount_total_err_cy_20_rt_2825
    );
  Mcount_total_err_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(21),
      O => Mcount_total_err_cy_21_rt_2827
    );
  Mcount_total_err_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(22),
      O => Mcount_total_err_cy_22_rt_2829
    );
  Mcount_total_err_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(23),
      O => Mcount_total_err_cy_23_rt_2831
    );
  Mcount_total_err_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(24),
      O => Mcount_total_err_cy_24_rt_2833
    );
  Mcount_total_err_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(25),
      O => Mcount_total_err_cy_25_rt_2835
    );
  Mcount_total_err_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(26),
      O => Mcount_total_err_cy_26_rt_2837
    );
  Mcount_total_err_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(27),
      O => Mcount_total_err_cy_27_rt_2839
    );
  Mcount_total_err_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(28),
      O => Mcount_total_err_cy_28_rt_2841
    );
  Mcount_total_err_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(29),
      O => Mcount_total_err_cy_29_rt_2843
    );
  Mcount_total_err_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(30),
      O => Mcount_total_err_cy_30_rt_2847
    );
  Mcount_block_ok_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(1),
      O => Mcount_block_ok_cy_1_rt_2649
    );
  Mcount_block_ok_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(2),
      O => Mcount_block_ok_cy_2_rt_2671
    );
  Mcount_block_ok_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(3),
      O => Mcount_block_ok_cy_3_rt_2675
    );
  Mcount_block_ok_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(4),
      O => Mcount_block_ok_cy_4_rt_2677
    );
  Mcount_block_ok_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(5),
      O => Mcount_block_ok_cy_5_rt_2679
    );
  Mcount_block_ok_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(6),
      O => Mcount_block_ok_cy_6_rt_2681
    );
  Mcount_block_ok_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(7),
      O => Mcount_block_ok_cy_7_rt_2683
    );
  Mcount_block_ok_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(8),
      O => Mcount_block_ok_cy_8_rt_2685
    );
  Mcount_block_ok_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(9),
      O => Mcount_block_ok_cy_9_rt_2687
    );
  Mcount_block_ok_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(10),
      O => Mcount_block_ok_cy_10_rt_2629
    );
  Mcount_block_ok_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(11),
      O => Mcount_block_ok_cy_11_rt_2631
    );
  Mcount_block_ok_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(12),
      O => Mcount_block_ok_cy_12_rt_2633
    );
  Mcount_block_ok_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(13),
      O => Mcount_block_ok_cy_13_rt_2635
    );
  Mcount_block_ok_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(14),
      O => Mcount_block_ok_cy_14_rt_2637
    );
  Mcount_block_ok_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(15),
      O => Mcount_block_ok_cy_15_rt_2639
    );
  Mcount_block_ok_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(16),
      O => Mcount_block_ok_cy_16_rt_2641
    );
  Mcount_block_ok_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(17),
      O => Mcount_block_ok_cy_17_rt_2643
    );
  Mcount_block_ok_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(18),
      O => Mcount_block_ok_cy_18_rt_2645
    );
  Mcount_block_ok_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(19),
      O => Mcount_block_ok_cy_19_rt_2647
    );
  Mcount_block_ok_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(20),
      O => Mcount_block_ok_cy_20_rt_2651
    );
  Mcount_block_ok_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(21),
      O => Mcount_block_ok_cy_21_rt_2653
    );
  Mcount_block_ok_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(22),
      O => Mcount_block_ok_cy_22_rt_2655
    );
  Mcount_block_ok_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(23),
      O => Mcount_block_ok_cy_23_rt_2657
    );
  Mcount_block_ok_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(24),
      O => Mcount_block_ok_cy_24_rt_2659
    );
  Mcount_block_ok_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(25),
      O => Mcount_block_ok_cy_25_rt_2661
    );
  Mcount_block_ok_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(26),
      O => Mcount_block_ok_cy_26_rt_2663
    );
  Mcount_block_ok_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(27),
      O => Mcount_block_ok_cy_27_rt_2665
    );
  Mcount_block_ok_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(28),
      O => Mcount_block_ok_cy_28_rt_2667
    );
  Mcount_block_ok_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(29),
      O => Mcount_block_ok_cy_29_rt_2669
    );
  Mcount_block_ok_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_ok(30),
      O => Mcount_block_ok_cy_30_rt_2673
    );
  Mcount_block_err_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(1),
      O => Mcount_block_err_cy_1_rt_2583
    );
  Mcount_block_err_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(2),
      O => Mcount_block_err_cy_2_rt_2605
    );
  Mcount_block_err_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(3),
      O => Mcount_block_err_cy_3_rt_2609
    );
  Mcount_block_err_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(4),
      O => Mcount_block_err_cy_4_rt_2611
    );
  Mcount_block_err_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(5),
      O => Mcount_block_err_cy_5_rt_2613
    );
  Mcount_block_err_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(6),
      O => Mcount_block_err_cy_6_rt_2615
    );
  Mcount_block_err_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(7),
      O => Mcount_block_err_cy_7_rt_2617
    );
  Mcount_block_err_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(8),
      O => Mcount_block_err_cy_8_rt_2619
    );
  Mcount_block_err_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(9),
      O => Mcount_block_err_cy_9_rt_2621
    );
  Mcount_block_err_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(10),
      O => Mcount_block_err_cy_10_rt_2563
    );
  Mcount_block_err_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(11),
      O => Mcount_block_err_cy_11_rt_2565
    );
  Mcount_block_err_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(12),
      O => Mcount_block_err_cy_12_rt_2567
    );
  Mcount_block_err_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(13),
      O => Mcount_block_err_cy_13_rt_2569
    );
  Mcount_block_err_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(14),
      O => Mcount_block_err_cy_14_rt_2571
    );
  Mcount_block_err_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(15),
      O => Mcount_block_err_cy_15_rt_2573
    );
  Mcount_block_err_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(16),
      O => Mcount_block_err_cy_16_rt_2575
    );
  Mcount_block_err_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(17),
      O => Mcount_block_err_cy_17_rt_2577
    );
  Mcount_block_err_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(18),
      O => Mcount_block_err_cy_18_rt_2579
    );
  Mcount_block_err_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(19),
      O => Mcount_block_err_cy_19_rt_2581
    );
  Mcount_block_err_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(20),
      O => Mcount_block_err_cy_20_rt_2585
    );
  Mcount_block_err_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(21),
      O => Mcount_block_err_cy_21_rt_2587
    );
  Mcount_block_err_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(22),
      O => Mcount_block_err_cy_22_rt_2589
    );
  Mcount_block_err_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(23),
      O => Mcount_block_err_cy_23_rt_2591
    );
  Mcount_block_err_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(24),
      O => Mcount_block_err_cy_24_rt_2593
    );
  Mcount_block_err_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(25),
      O => Mcount_block_err_cy_25_rt_2595
    );
  Mcount_block_err_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(26),
      O => Mcount_block_err_cy_26_rt_2597
    );
  Mcount_block_err_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(27),
      O => Mcount_block_err_cy_27_rt_2599
    );
  Mcount_block_err_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(28),
      O => Mcount_block_err_cy_28_rt_2601
    );
  Mcount_block_err_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(29),
      O => Mcount_block_err_cy_29_rt_2603
    );
  Mcount_block_err_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_err(30),
      O => Mcount_block_err_cy_30_rt_2607
    );
  Mcount_block_rd_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(1),
      O => Mcount_block_rd_cy_1_rt_2711
    );
  Mcount_block_rd_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(2),
      O => Mcount_block_rd_cy_2_rt_2733
    );
  Mcount_block_rd_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      O => Mcount_block_rd_cy_3_rt_2737
    );
  Mcount_block_rd_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(4),
      O => Mcount_block_rd_cy_4_rt_2739
    );
  Mcount_block_rd_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      O => Mcount_block_rd_cy_5_rt_2741
    );
  Mcount_block_rd_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(6),
      O => Mcount_block_rd_cy_6_rt_2743
    );
  Mcount_block_rd_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(7),
      O => Mcount_block_rd_cy_7_rt_2745
    );
  Mcount_block_rd_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(8),
      O => Mcount_block_rd_cy_8_rt_2747
    );
  Mcount_block_rd_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(9),
      O => Mcount_block_rd_cy_9_rt_2749
    );
  Mcount_block_rd_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(10),
      O => Mcount_block_rd_cy_10_rt_2691
    );
  Mcount_block_rd_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(11),
      O => Mcount_block_rd_cy_11_rt_2693
    );
  Mcount_block_rd_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(12),
      O => Mcount_block_rd_cy_12_rt_2695
    );
  Mcount_block_rd_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(13),
      O => Mcount_block_rd_cy_13_rt_2697
    );
  Mcount_block_rd_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(14),
      O => Mcount_block_rd_cy_14_rt_2699
    );
  Mcount_block_rd_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(15),
      O => Mcount_block_rd_cy_15_rt_2701
    );
  Mcount_block_rd_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(16),
      O => Mcount_block_rd_cy_16_rt_2703
    );
  Mcount_block_rd_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(17),
      O => Mcount_block_rd_cy_17_rt_2705
    );
  Mcount_block_rd_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(18),
      O => Mcount_block_rd_cy_18_rt_2707
    );
  Mcount_block_rd_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(19),
      O => Mcount_block_rd_cy_19_rt_2709
    );
  Mcount_block_rd_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(20),
      O => Mcount_block_rd_cy_20_rt_2713
    );
  Mcount_block_rd_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(21),
      O => Mcount_block_rd_cy_21_rt_2715
    );
  Mcount_block_rd_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(22),
      O => Mcount_block_rd_cy_22_rt_2717
    );
  Mcount_block_rd_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(23),
      O => Mcount_block_rd_cy_23_rt_2719
    );
  Mcount_block_rd_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(24),
      O => Mcount_block_rd_cy_24_rt_2721
    );
  Mcount_block_rd_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(25),
      O => Mcount_block_rd_cy_25_rt_2723
    );
  Mcount_block_rd_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(26),
      O => Mcount_block_rd_cy_26_rt_2725
    );
  Mcount_block_rd_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(27),
      O => Mcount_block_rd_cy_27_rt_2727
    );
  Mcount_block_rd_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(28),
      O => Mcount_block_rd_cy_28_rt_2729
    );
  Mcount_block_rd_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(29),
      O => Mcount_block_rd_cy_29_rt_2731
    );
  Mcount_block_rd_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(30),
      O => Mcount_block_rd_cy_30_rt_2735
    );
  Mcount_cnt1_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(1),
      O => Mcount_cnt1_cy_1_rt_2774
    );
  Mcount_cnt1_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(2),
      O => Mcount_cnt1_cy_2_rt_2784
    );
  Mcount_cnt1_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(3),
      O => Mcount_cnt1_cy_3_rt_2786
    );
  Mcount_cnt1_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(4),
      O => Mcount_cnt1_cy_4_rt_2788
    );
  Mcount_cnt1_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(5),
      O => Mcount_cnt1_cy_5_rt_2790
    );
  Mcount_cnt1_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(6),
      O => Mcount_cnt1_cy_6_rt_2792
    );
  Mcount_cnt1_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(7),
      O => Mcount_cnt1_cy_7_rt_2794
    );
  Mcount_cnt1_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(8),
      O => Mcount_cnt1_cy_8_rt_2796
    );
  Mcount_cnt1_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(9),
      O => Mcount_cnt1_cy_9_rt_2798
    );
  Mcount_cnt1_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(10),
      O => Mcount_cnt1_cy_10_rt_2754
    );
  Mcount_cnt1_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(11),
      O => Mcount_cnt1_cy_11_rt_2756
    );
  Mcount_cnt1_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(12),
      O => Mcount_cnt1_cy_12_rt_2758
    );
  Mcount_cnt1_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(13),
      O => Mcount_cnt1_cy_13_rt_2760
    );
  Mcount_cnt1_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(14),
      O => Mcount_cnt1_cy_14_rt_2762
    );
  Mcount_cnt1_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(15),
      O => Mcount_cnt1_cy_15_rt_2764
    );
  Mcount_cnt1_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(16),
      O => Mcount_cnt1_cy_16_rt_2766
    );
  Mcount_cnt1_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(17),
      O => Mcount_cnt1_cy_17_rt_2768
    );
  Mcount_cnt1_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(18),
      O => Mcount_cnt1_cy_18_rt_2770
    );
  Mcount_cnt1_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(19),
      O => Mcount_cnt1_cy_19_rt_2772
    );
  Mcount_cnt1_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(20),
      O => Mcount_cnt1_cy_20_rt_2776
    );
  Mcount_cnt1_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(21),
      O => Mcount_cnt1_cy_21_rt_2778
    );
  Mcount_cnt1_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(22),
      O => Mcount_cnt1_cy_22_rt_2780
    );
  Mcount_cnt1_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(23),
      O => Mcount_cnt1_cy_23_rt_2782
    );
  Madd_data_ex4_63_32_add0000_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(63),
      O => Madd_data_ex4_63_32_add0000_xor_31_rt_2506
    );
  Madd_data_ex4_31_0_add0000_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(31),
      O => Madd_data_ex4_31_0_add0000_xor_31_rt_2443
    );
  Mcount_total_err_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_total_err(31),
      O => Mcount_total_err_xor_31_rt_2863
    );
  Mcount_block_rd_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(31),
      O => Mcount_block_rd_xor_31_rt_2751
    );
  Mcount_cnt1_xor_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(24),
      O => Mcount_cnt1_xor_24_rt_2800
    );
  data_error_wr11 : LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      I0 => data_error_ovr_3651,
      I1 => data_en_z_3400,
      I2 => word_error,
      O => data_error_wr1_3654
    );
  data_error_ovr_and00001 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_en_z_3400,
      I1 => NlwRenamedSig_OI_total_err(3),
      I2 => NlwRenamedSig_OI_total_err(2),
      I3 => NlwRenamedSig_OI_total_err(1),
      I4 => NlwRenamedSig_OI_total_err(0),
      I5 => word_error,
      O => data_error_ovr_and0000
    );
  data_ex4_32_not0001104 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => data_ex4_32_not000181_4239,
      I1 => data_ex4_32_not000170_4238,
      I2 => data_ex4_32_not000148_4236,
      I3 => data_ex4_32_not000137_4235,
      I4 => data_ex4_32_not000123_4234,
      O => data_ex4_32_not0001
    );
  data_ex4_32_not000121 : LUT6
    generic map(
      INIT => X"0000000000800000"
    )
    port map (
      I0 => do_data_en,
      I1 => cnt1(0),
      I2 => block_mode(1),
      I3 => cnt1_z_3399,
      I4 => block_mode(2),
      I5 => block_mode(3),
      O => data_ex4_10_not0001
    );
  Mmux_err_data_5_f7_13 : MUXF7
    port map (
      I0 => Mmux_err_data_714_2902,
      I1 => Mmux_err_data_614_2886,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f714
    );
  Mmux_err_data_5_f7_12 : MUXF7
    port map (
      I0 => Mmux_err_data_713_2901,
      I1 => Mmux_err_data_613_2885,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f713
    );
  Mmux_err_data_5_f7_14 : MUXF7
    port map (
      I0 => Mmux_err_data_715_2903,
      I1 => Mmux_err_data_615_2887,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f715
    );
  Mmux_err_data_5_f7_11 : MUXF7
    port map (
      I0 => Mmux_err_data_712_2900,
      I1 => Mmux_err_data_612_2884,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f712
    );
  Mmux_err_data_5_f7_10 : MUXF7
    port map (
      I0 => Mmux_err_data_711_2899,
      I1 => Mmux_err_data_611_2883,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f711
    );
  Mmux_err_data_5_f7_8 : MUXF7
    port map (
      I0 => Mmux_err_data_79_2911,
      I1 => Mmux_err_data_69_2895,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f79
    );
  Mmux_err_data_5_f7_7 : MUXF7
    port map (
      I0 => Mmux_err_data_78_2910,
      I1 => Mmux_err_data_68_2894,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f78
    );
  Mmux_err_data_5_f7_9 : MUXF7
    port map (
      I0 => Mmux_err_data_710_2898,
      I1 => Mmux_err_data_610_2882,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f710
    );
  Mmux_err_data_5_f7_5 : MUXF7
    port map (
      I0 => Mmux_err_data_76_2908,
      I1 => Mmux_err_data_66_2892,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f76
    );
  Mmux_err_data_5_f7_4 : MUXF7
    port map (
      I0 => Mmux_err_data_75_2907,
      I1 => Mmux_err_data_65_2891,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f75
    );
  Mmux_err_data_5_f7_6 : MUXF7
    port map (
      I0 => Mmux_err_data_77_2909,
      I1 => Mmux_err_data_67_2893,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f77
    );
  Mmux_err_data_5_f7_2 : MUXF7
    port map (
      I0 => Mmux_err_data_73_2905,
      I1 => Mmux_err_data_63_2889,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f73
    );
  Mmux_err_data_5_f7_1 : MUXF7
    port map (
      I0 => Mmux_err_data_72_2904,
      I1 => Mmux_err_data_62_2888,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f72
    );
  Mmux_err_data_5_f7_3 : MUXF7
    port map (
      I0 => Mmux_err_data_74_2906,
      I1 => Mmux_err_data_64_2890,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f74
    );
  Mmux_err_data_5_f7_0 : MUXF7
    port map (
      I0 => Mmux_err_data_71_2897,
      I1 => Mmux_err_data_61_2881,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f71
    );
  Mmux_err_data_5_f7 : MUXF7
    port map (
      I0 => Mmux_err_data_7_2896,
      I1 => Mmux_err_data_6_2880,
      S => test_check_err_adr(1),
      O => Mmux_err_data_5_f7_2864
    );
  data_expect_3_cmp_eq00068142_SW0 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      I1 => cnt1(5),
      I2 => NlwRenamedSig_OI_block_rd(6),
      I3 => cnt1(6),
      I4 => NlwRenamedSig_OI_block_rd(2),
      I5 => cnt1(2),
      O => N38
    );
  data_expect_3_cmp_eq00068142 : LUT6
    generic map(
      INIT => X"9009000000000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      I1 => cnt1(3),
      I2 => NlwRenamedSig_OI_block_rd(4),
      I3 => cnt1(4),
      I4 => data_expect_3_cmp_eq00068126_4484,
      I5 => N38,
      O => data_expect_3_cmp_eq0006
    );
  data_expect_63_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(31),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_63_mux000099_4590,
      I4 => data_expect_63_mux0000114_4589,
      O => data_expect_63_mux0000
    );
  data_expect_62_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(30),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_62_mux000099_4586,
      I4 => data_expect_62_mux0000114_4585,
      O => data_expect_62_mux0000
    );
  data_expect_61_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(29),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_61_mux000099_4582,
      I4 => data_expect_61_mux0000114_4581,
      O => data_expect_61_mux0000
    );
  data_expect_60_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(28),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_60_mux000099_4578,
      I4 => data_expect_60_mux0000114_4577,
      O => data_expect_60_mux0000
    );
  data_expect_59_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(27),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_59_mux000099_4571,
      I4 => data_expect_59_mux0000114_4570,
      O => data_expect_59_mux0000
    );
  data_expect_58_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(26),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_58_mux000099_4567,
      I4 => data_expect_58_mux0000114_4566,
      O => data_expect_58_mux0000
    );
  data_expect_57_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(25),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_57_mux000099_4563,
      I4 => data_expect_57_mux0000114_4562,
      O => data_expect_57_mux0000
    );
  data_expect_56_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(24),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_56_mux000099_4559,
      I4 => data_expect_56_mux0000114_4558,
      O => data_expect_56_mux0000
    );
  data_expect_55_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(23),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_55_mux000099_4555,
      I4 => data_expect_55_mux0000114_4554,
      O => data_expect_55_mux0000
    );
  data_expect_54_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(22),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_54_mux000099_4551,
      I4 => data_expect_54_mux0000114_4550,
      O => data_expect_54_mux0000
    );
  data_expect_53_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(21),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_53_mux000099_4547,
      I4 => data_expect_53_mux0000114_4546,
      O => data_expect_53_mux0000
    );
  data_expect_52_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(20),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_52_mux000099_4543,
      I4 => data_expect_52_mux0000114_4542,
      O => data_expect_52_mux0000
    );
  data_expect_51_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(19),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_51_mux000099_4539,
      I4 => data_expect_51_mux0000114_4538,
      O => data_expect_51_mux0000
    );
  data_expect_50_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(18),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_50_mux000099_4535,
      I4 => data_expect_50_mux0000114_4534,
      O => data_expect_50_mux0000
    );
  data_expect_49_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(17),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_49_mux000099_4528,
      I4 => data_expect_49_mux0000114_4527,
      O => data_expect_49_mux0000
    );
  data_expect_48_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(16),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_48_mux000099_4524,
      I4 => data_expect_48_mux0000114_4523,
      O => data_expect_48_mux0000
    );
  data_expect_47_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(15),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_47_mux000099_4520,
      I4 => data_expect_47_mux0000114_4519,
      O => data_expect_47_mux0000
    );
  data_expect_46_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(14),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_46_mux000099_4516,
      I4 => data_expect_46_mux0000114_4515,
      O => data_expect_46_mux0000
    );
  data_expect_45_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(13),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_45_mux000099_4512,
      I4 => data_expect_45_mux0000114_4511,
      O => data_expect_45_mux0000
    );
  data_expect_44_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(12),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_44_mux000099_4508,
      I4 => data_expect_44_mux0000114_4507,
      O => data_expect_44_mux0000
    );
  data_expect_43_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(11),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_43_mux000099_4504,
      I4 => data_expect_43_mux0000114_4503,
      O => data_expect_43_mux0000
    );
  data_expect_42_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(10),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_42_mux000099_4500,
      I4 => data_expect_42_mux0000114_4499,
      O => data_expect_42_mux0000
    );
  data_expect_41_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(9),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_41_mux000099_4496,
      I4 => data_expect_41_mux0000114_4495,
      O => data_expect_41_mux0000
    );
  data_expect_40_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(8),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_40_mux000099_4492,
      I4 => data_expect_40_mux0000114_4491,
      O => data_expect_40_mux0000
    );
  data_expect_39_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(7),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_39_mux000099_4482,
      I4 => data_expect_39_mux0000114_4481,
      O => data_expect_39_mux0000
    );
  data_expect_38_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(6),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_38_mux000099_4478,
      I4 => data_expect_38_mux0000114_4477,
      O => data_expect_38_mux0000
    );
  data_expect_37_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_37_mux000099_4474,
      I4 => data_expect_37_mux0000114_4473,
      O => data_expect_37_mux0000
    );
  data_expect_36_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(4),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_36_mux000099_4470,
      I4 => data_expect_36_mux0000114_4469,
      O => data_expect_36_mux0000
    );
  data_expect_35_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_35_mux000099_4466,
      I4 => data_expect_35_mux0000114_4465,
      O => data_expect_35_mux0000
    );
  data_expect_34_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(2),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_34_mux000099_4462,
      I4 => data_expect_34_mux0000114_4461,
      O => data_expect_34_mux0000
    );
  data_expect_33_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(1),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_33_mux000099_4458,
      I4 => data_expect_33_mux0000114_4457,
      O => data_expect_33_mux0000
    );
  data_expect_32_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(0),
      I1 => cnt1_z_3399,
      I2 => data_ex3_and0000,
      I3 => data_expect_32_mux000099_4454,
      I4 => data_expect_32_mux0000114_4453,
      O => data_expect_32_mux0000
    );
  data_ex3_mux0000_9_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(54),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(9)
    );
  data_ex3_mux0000_8_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(55),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(8)
    );
  data_ex3_mux0000_7_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(56),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(7)
    );
  data_ex3_mux0000_6_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(57),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(6)
    );
  data_ex3_mux0000_63_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(0),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(63)
    );
  data_ex3_mux0000_62_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(1),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(62)
    );
  data_ex3_mux0000_61_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(2),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(61)
    );
  data_ex3_mux0000_60_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(3),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(60)
    );
  data_ex3_mux0000_5_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(58),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(5)
    );
  data_ex3_mux0000_59_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(4),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(59)
    );
  data_ex3_mux0000_58_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(5),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(58)
    );
  data_ex3_mux0000_57_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(6),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(57)
    );
  data_ex3_mux0000_56_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(7),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(56)
    );
  data_ex3_mux0000_55_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(8),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(55)
    );
  data_ex3_mux0000_54_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(9),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(54)
    );
  data_ex3_mux0000_53_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(10),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(53)
    );
  data_ex3_mux0000_52_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(11),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(52)
    );
  data_ex3_mux0000_51_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(12),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(51)
    );
  data_ex3_mux0000_50_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(13),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(50)
    );
  data_ex3_mux0000_4_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(59),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(4)
    );
  data_ex3_mux0000_49_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(14),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(49)
    );
  data_ex3_mux0000_48_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(15),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(48)
    );
  data_ex3_mux0000_47_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(16),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(47)
    );
  data_ex3_mux0000_46_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(17),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(46)
    );
  data_ex3_mux0000_45_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(18),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(45)
    );
  data_ex3_mux0000_44_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(19),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(44)
    );
  data_ex3_mux0000_43_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(20),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(43)
    );
  data_ex3_mux0000_42_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(21),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(42)
    );
  data_ex3_mux0000_41_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(22),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(41)
    );
  data_ex3_mux0000_40_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(23),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(40)
    );
  data_ex3_mux0000_3_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(60),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(3)
    );
  data_ex3_mux0000_39_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(24),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(39)
    );
  data_ex3_mux0000_38_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(25),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(38)
    );
  data_ex3_mux0000_37_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(26),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(37)
    );
  data_ex3_mux0000_36_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(27),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(36)
    );
  data_ex3_mux0000_35_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(28),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(35)
    );
  data_ex3_mux0000_34_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(29),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(34)
    );
  data_ex3_mux0000_33_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(30),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(33)
    );
  data_ex3_mux0000_32_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(31),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(32)
    );
  data_ex3_mux0000_31_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(32),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(31)
    );
  data_ex3_mux0000_30_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(33),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(30)
    );
  data_ex3_mux0000_2_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(61),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(2)
    );
  data_ex3_mux0000_29_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(34),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(29)
    );
  data_ex3_mux0000_28_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(35),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(28)
    );
  data_ex3_mux0000_27_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(36),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(27)
    );
  data_ex3_mux0000_26_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(37),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(26)
    );
  data_ex3_mux0000_25_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(38),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(25)
    );
  data_ex3_mux0000_24_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(39),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(24)
    );
  data_ex3_mux0000_23_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(40),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(23)
    );
  data_ex3_mux0000_22_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(41),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(22)
    );
  data_ex3_mux0000_21_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(42),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(21)
    );
  data_ex3_mux0000_20_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(43),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(20)
    );
  data_ex3_mux0000_1_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(62),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(1)
    );
  data_ex3_mux0000_19_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(44),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(19)
    );
  data_ex3_mux0000_18_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(45),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(18)
    );
  data_ex3_mux0000_17_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(46),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(17)
    );
  data_ex3_mux0000_16_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(47),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(16)
    );
  data_ex3_mux0000_15_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(48),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(15)
    );
  data_ex3_mux0000_14_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(49),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(14)
    );
  data_ex3_mux0000_13_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(50),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(13)
    );
  data_ex3_mux0000_12_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(51),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(12)
    );
  data_ex3_mux0000_11_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(52),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(11)
    );
  data_ex3_mux0000_10_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(53),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(10)
    );
  data_ex3_mux0000_0_2 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(63),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(0)
    );
  data_ex2_0_mux00001 : LUT5
    generic map(
      INIT => X"5DFD08A8"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(0),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(63),
      O => data_ex2_0_mux0000
    );
  block_mode_not00011 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => do_data_en,
      I1 => cnt1_eq_3379,
      I2 => test_check_ctrl(7),
      O => block_mode_not0001
    );
  data_ex1_0_mux00001 : LUT6
    generic map(
      INIT => X"DD5DDDFD880888A8"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex1(0),
      I2 => N80,
      I3 => block_mode(2),
      I4 => block_mode(0),
      I5 => data_ex1(63),
      O => data_ex1_0_mux0000
    );
  data_ex0_0_mux00001 : LUT6
    generic map(
      INIT => X"DD5DDDFD880888A8"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex0(0),
      I2 => N63,
      I3 => block_mode(3),
      I4 => block_mode(0),
      I5 => data_ex0(63),
      O => data_ex0_0_mux0000
    );
  cnt1_or00001 : LUT4
    generic map(
      INIT => X"FFD5"
    )
    port map (
      I0 => reset,
      I1 => do_data_en,
      I2 => cnt1_eq_3379,
      I3 => test_check_ctrl(0),
      O => cnt1_or0000
    );
  data_ex3_not00011 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => reset,
      I1 => test_check_ctrl(0),
      I2 => do_data_en,
      I3 => cnt1_z_3399,
      O => data_ex3_not0001
    );
  data_ex5_10_not00011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => block_mode(3),
      I1 => do_data_en,
      I2 => cnt1_z_3399,
      I3 => block_mode(2),
      I4 => block_mode(1),
      O => data_ex5_10_not0001
    );
  data_ex2_9_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(9),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(8),
      O => data_ex2_9_mux0000
    );
  data_ex2_8_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(8),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(7),
      O => data_ex2_8_mux0000
    );
  data_ex2_7_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(7),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(6),
      O => data_ex2_7_mux0000
    );
  data_ex2_6_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(6),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(5),
      O => data_ex2_6_mux0000
    );
  data_ex2_63_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(63),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(62),
      O => data_ex2_63_mux0000
    );
  data_ex2_62_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(62),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(61),
      O => data_ex2_62_mux0000
    );
  data_ex2_61_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(61),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(60),
      O => data_ex2_61_mux0000
    );
  data_ex2_60_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(60),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(59),
      O => data_ex2_60_mux0000
    );
  data_ex2_5_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(5),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(4),
      O => data_ex2_5_mux0000
    );
  data_ex2_59_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(59),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(58),
      O => data_ex2_59_mux0000
    );
  data_ex2_58_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(58),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(57),
      O => data_ex2_58_mux0000
    );
  data_ex2_57_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(57),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(56),
      O => data_ex2_57_mux0000
    );
  data_ex2_56_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(56),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(55),
      O => data_ex2_56_mux0000
    );
  data_ex2_55_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(55),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(54),
      O => data_ex2_55_mux0000
    );
  data_ex2_54_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(54),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(53),
      O => data_ex2_54_mux0000
    );
  data_ex2_53_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(53),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(52),
      O => data_ex2_53_mux0000
    );
  data_ex2_52_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(52),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(51),
      O => data_ex2_52_mux0000
    );
  data_ex2_51_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(51),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(50),
      O => data_ex2_51_mux0000
    );
  data_ex2_50_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(50),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(49),
      O => data_ex2_50_mux0000
    );
  data_ex2_4_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(4),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(3),
      O => data_ex2_4_mux0000
    );
  data_ex2_49_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(49),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(48),
      O => data_ex2_49_mux0000
    );
  data_ex2_48_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(48),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(47),
      O => data_ex2_48_mux0000
    );
  data_ex2_47_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(47),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(46),
      O => data_ex2_47_mux0000
    );
  data_ex2_46_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(46),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(45),
      O => data_ex2_46_mux0000
    );
  data_ex2_45_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(45),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(44),
      O => data_ex2_45_mux0000
    );
  data_ex2_44_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(44),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(43),
      O => data_ex2_44_mux0000
    );
  data_ex2_43_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(43),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(42),
      O => data_ex2_43_mux0000
    );
  data_ex2_42_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(42),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(41),
      O => data_ex2_42_mux0000
    );
  data_ex2_41_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(41),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(40),
      O => data_ex2_41_mux0000
    );
  data_ex2_40_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(40),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(39),
      O => data_ex2_40_mux0000
    );
  data_ex2_3_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(3),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(2),
      O => data_ex2_3_mux0000
    );
  data_ex2_39_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(39),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(38),
      O => data_ex2_39_mux0000
    );
  data_ex2_38_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(38),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(37),
      O => data_ex2_38_mux0000
    );
  data_ex2_37_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(37),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(36),
      O => data_ex2_37_mux0000
    );
  data_ex2_36_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(36),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(35),
      O => data_ex2_36_mux0000
    );
  data_ex2_35_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(35),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(34),
      O => data_ex2_35_mux0000
    );
  data_ex2_34_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(34),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(33),
      O => data_ex2_34_mux0000
    );
  data_ex2_33_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(33),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(32),
      O => data_ex2_33_mux0000
    );
  data_ex2_32_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(32),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(31),
      O => data_ex2_32_mux0000
    );
  data_ex2_31_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(31),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(30),
      O => data_ex2_31_mux0000
    );
  data_ex2_30_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(30),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(29),
      O => data_ex2_30_mux0000
    );
  data_ex2_2_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(2),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(1),
      O => data_ex2_2_mux0000
    );
  data_ex2_29_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(29),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(28),
      O => data_ex2_29_mux0000
    );
  data_ex2_28_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(28),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(27),
      O => data_ex2_28_mux0000
    );
  data_ex2_27_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(27),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(26),
      O => data_ex2_27_mux0000
    );
  data_ex2_26_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(26),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(25),
      O => data_ex2_26_mux0000
    );
  data_ex2_25_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(25),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(24),
      O => data_ex2_25_mux0000
    );
  data_ex2_24_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(24),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(23),
      O => data_ex2_24_mux0000
    );
  data_ex2_23_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(23),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(22),
      O => data_ex2_23_mux0000
    );
  data_ex2_22_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(22),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(21),
      O => data_ex2_22_mux0000
    );
  data_ex2_21_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(21),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(20),
      O => data_ex2_21_mux0000
    );
  data_ex2_20_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(20),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(19),
      O => data_ex2_20_mux0000
    );
  data_ex2_1_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(1),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(0),
      O => data_ex2_1_mux0000
    );
  data_ex2_19_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(19),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(18),
      O => data_ex2_19_mux0000
    );
  data_ex2_18_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(18),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(17),
      O => data_ex2_18_mux0000
    );
  data_ex2_17_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(17),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(16),
      O => data_ex2_17_mux0000
    );
  data_ex2_16_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(16),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(15),
      O => data_ex2_16_mux0000
    );
  data_ex2_15_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(15),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(14),
      O => data_ex2_15_mux0000
    );
  data_ex2_14_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(14),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(13),
      O => data_ex2_14_mux0000
    );
  data_ex2_13_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(13),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(12),
      O => data_ex2_13_mux0000
    );
  data_ex2_12_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(12),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(11),
      O => data_ex2_12_mux0000
    );
  data_ex2_11_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(11),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(10),
      O => data_ex2_11_mux0000
    );
  data_ex2_10_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => data_ex2(10),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(9),
      O => data_ex2_10_mux0000
    );
  data_ex1_9_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(8),
      I5 => data_ex1(9),
      O => data_ex1_9_mux0000
    );
  data_ex1_8_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(7),
      I5 => data_ex1(8),
      O => data_ex1_8_mux0000
    );
  data_ex1_7_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(6),
      I5 => data_ex1(7),
      O => data_ex1_7_mux0000
    );
  data_ex1_6_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(5),
      I5 => data_ex1(6),
      O => data_ex1_6_mux0000
    );
  data_ex1_63_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(62),
      I5 => data_ex1(63),
      O => data_ex1_63_mux0000
    );
  data_ex1_62_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(61),
      I5 => data_ex1(62),
      O => data_ex1_62_mux0000
    );
  data_ex1_61_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(60),
      I5 => data_ex1(61),
      O => data_ex1_61_mux0000
    );
  data_ex1_60_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(59),
      I5 => data_ex1(60),
      O => data_ex1_60_mux0000
    );
  data_ex1_5_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(4),
      I5 => data_ex1(5),
      O => data_ex1_5_mux0000
    );
  data_ex1_59_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(58),
      I5 => data_ex1(59),
      O => data_ex1_59_mux0000
    );
  data_ex1_58_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(57),
      I5 => data_ex1(58),
      O => data_ex1_58_mux0000
    );
  data_ex1_57_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(56),
      I5 => data_ex1(57),
      O => data_ex1_57_mux0000
    );
  data_ex1_56_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(55),
      I5 => data_ex1(56),
      O => data_ex1_56_mux0000
    );
  data_ex1_55_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(54),
      I5 => data_ex1(55),
      O => data_ex1_55_mux0000
    );
  data_ex1_54_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(53),
      I5 => data_ex1(54),
      O => data_ex1_54_mux0000
    );
  data_ex1_53_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(52),
      I5 => data_ex1(53),
      O => data_ex1_53_mux0000
    );
  data_ex1_52_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(51),
      I5 => data_ex1(52),
      O => data_ex1_52_mux0000
    );
  data_ex1_51_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(50),
      I5 => data_ex1(51),
      O => data_ex1_51_mux0000
    );
  data_ex1_50_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(49),
      I5 => data_ex1(50),
      O => data_ex1_50_mux0000
    );
  data_ex1_4_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(3),
      I5 => data_ex1(4),
      O => data_ex1_4_mux0000
    );
  data_ex1_49_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(48),
      I5 => data_ex1(49),
      O => data_ex1_49_mux0000
    );
  data_ex1_48_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(47),
      I5 => data_ex1(48),
      O => data_ex1_48_mux0000
    );
  data_ex1_47_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(46),
      I5 => data_ex1(47),
      O => data_ex1_47_mux0000
    );
  data_ex1_46_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(45),
      I5 => data_ex1(46),
      O => data_ex1_46_mux0000
    );
  data_ex1_45_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(44),
      I5 => data_ex1(45),
      O => data_ex1_45_mux0000
    );
  data_ex1_44_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(43),
      I5 => data_ex1(44),
      O => data_ex1_44_mux0000
    );
  data_ex1_43_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(42),
      I5 => data_ex1(43),
      O => data_ex1_43_mux0000
    );
  data_ex1_42_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(41),
      I5 => data_ex1(42),
      O => data_ex1_42_mux0000
    );
  data_ex1_41_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(40),
      I5 => data_ex1(41),
      O => data_ex1_41_mux0000
    );
  data_ex1_40_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(39),
      I5 => data_ex1(40),
      O => data_ex1_40_mux0000
    );
  data_ex1_3_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(2),
      I5 => data_ex1(3),
      O => data_ex1_3_mux0000
    );
  data_ex1_39_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(38),
      I5 => data_ex1(39),
      O => data_ex1_39_mux0000
    );
  data_ex1_38_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(37),
      I5 => data_ex1(38),
      O => data_ex1_38_mux0000
    );
  data_ex1_37_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(36),
      I5 => data_ex1(37),
      O => data_ex1_37_mux0000
    );
  data_ex1_36_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(35),
      I5 => data_ex1(36),
      O => data_ex1_36_mux0000
    );
  data_ex1_35_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(34),
      I5 => data_ex1(35),
      O => data_ex1_35_mux0000
    );
  data_ex1_34_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(33),
      I5 => data_ex1(34),
      O => data_ex1_34_mux0000
    );
  data_ex1_33_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(32),
      I5 => data_ex1(33),
      O => data_ex1_33_mux0000
    );
  data_ex1_32_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(31),
      I5 => data_ex1(32),
      O => data_ex1_32_mux0000
    );
  data_ex1_31_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(30),
      I5 => data_ex1(31),
      O => data_ex1_31_mux0000
    );
  data_ex1_30_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(29),
      I5 => data_ex1(30),
      O => data_ex1_30_mux0000
    );
  data_ex1_2_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(1),
      I5 => data_ex1(2),
      O => data_ex1_2_mux0000
    );
  data_ex1_29_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(28),
      I5 => data_ex1(29),
      O => data_ex1_29_mux0000
    );
  data_ex1_28_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(27),
      I5 => data_ex1(28),
      O => data_ex1_28_mux0000
    );
  data_ex1_27_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(26),
      I5 => data_ex1(27),
      O => data_ex1_27_mux0000
    );
  data_ex1_26_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(25),
      I5 => data_ex1(26),
      O => data_ex1_26_mux0000
    );
  data_ex1_25_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(24),
      I5 => data_ex1(25),
      O => data_ex1_25_mux0000
    );
  data_ex1_24_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(23),
      I5 => data_ex1(24),
      O => data_ex1_24_mux0000
    );
  data_ex1_23_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(22),
      I5 => data_ex1(23),
      O => data_ex1_23_mux0000
    );
  data_ex1_22_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(21),
      I5 => data_ex1(22),
      O => data_ex1_22_mux0000
    );
  data_ex1_21_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(20),
      I5 => data_ex1(21),
      O => data_ex1_21_mux0000
    );
  data_ex1_20_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(19),
      I5 => data_ex1(20),
      O => data_ex1_20_mux0000
    );
  data_ex1_1_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(0),
      I5 => data_ex1(1),
      O => data_ex1_1_mux0000
    );
  data_ex1_19_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(18),
      I5 => data_ex1(19),
      O => data_ex1_19_mux0000
    );
  data_ex1_18_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(17),
      I5 => data_ex1(18),
      O => data_ex1_18_mux0000
    );
  data_ex1_17_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(16),
      I5 => data_ex1(17),
      O => data_ex1_17_mux0000
    );
  data_ex1_16_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(15),
      I5 => data_ex1(16),
      O => data_ex1_16_mux0000
    );
  data_ex1_15_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(14),
      I5 => data_ex1(15),
      O => data_ex1_15_mux0000
    );
  data_ex1_14_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(13),
      I5 => data_ex1(14),
      O => data_ex1_14_mux0000
    );
  data_ex1_13_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(12),
      I5 => data_ex1(13),
      O => data_ex1_13_mux0000
    );
  data_ex1_12_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(11),
      I5 => data_ex1(12),
      O => data_ex1_12_mux0000
    );
  data_ex1_11_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(10),
      I5 => data_ex1(11),
      O => data_ex1_11_mux0000
    );
  data_ex1_10_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(9),
      I5 => data_ex1(10),
      O => data_ex1_10_mux0000
    );
  data_ex0_9_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(8),
      I5 => data_ex0(9),
      O => data_ex0_9_mux0000
    );
  data_ex0_8_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(7),
      I5 => data_ex0(8),
      O => data_ex0_8_mux0000
    );
  data_ex0_7_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(6),
      I5 => data_ex0(7),
      O => data_ex0_7_mux0000
    );
  data_ex0_6_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(5),
      I5 => data_ex0(6),
      O => data_ex0_6_mux0000
    );
  data_ex0_63_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(62),
      I5 => data_ex0(63),
      O => data_ex0_63_mux0000
    );
  data_ex0_62_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(61),
      I5 => data_ex0(62),
      O => data_ex0_62_mux0000
    );
  data_ex0_61_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(60),
      I5 => data_ex0(61),
      O => data_ex0_61_mux0000
    );
  data_ex0_60_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(59),
      I5 => data_ex0(60),
      O => data_ex0_60_mux0000
    );
  data_ex0_5_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(4),
      I5 => data_ex0(5),
      O => data_ex0_5_mux0000
    );
  data_ex0_59_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(58),
      I5 => data_ex0(59),
      O => data_ex0_59_mux0000
    );
  data_ex0_58_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(57),
      I5 => data_ex0(58),
      O => data_ex0_58_mux0000
    );
  data_ex0_57_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(56),
      I5 => data_ex0(57),
      O => data_ex0_57_mux0000
    );
  data_ex0_56_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(55),
      I5 => data_ex0(56),
      O => data_ex0_56_mux0000
    );
  data_ex0_55_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(54),
      I5 => data_ex0(55),
      O => data_ex0_55_mux0000
    );
  data_ex0_54_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(53),
      I5 => data_ex0(54),
      O => data_ex0_54_mux0000
    );
  data_ex0_53_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(52),
      I5 => data_ex0(53),
      O => data_ex0_53_mux0000
    );
  data_ex0_52_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(51),
      I5 => data_ex0(52),
      O => data_ex0_52_mux0000
    );
  data_ex0_51_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(50),
      I5 => data_ex0(51),
      O => data_ex0_51_mux0000
    );
  data_ex0_50_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(49),
      I5 => data_ex0(50),
      O => data_ex0_50_mux0000
    );
  data_ex0_4_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(3),
      I5 => data_ex0(4),
      O => data_ex0_4_mux0000
    );
  data_ex0_49_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(48),
      I5 => data_ex0(49),
      O => data_ex0_49_mux0000
    );
  data_ex0_48_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(47),
      I5 => data_ex0(48),
      O => data_ex0_48_mux0000
    );
  data_ex0_47_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(46),
      I5 => data_ex0(47),
      O => data_ex0_47_mux0000
    );
  data_ex0_46_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(45),
      I5 => data_ex0(46),
      O => data_ex0_46_mux0000
    );
  data_ex0_45_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(44),
      I5 => data_ex0(45),
      O => data_ex0_45_mux0000
    );
  data_ex0_44_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(43),
      I5 => data_ex0(44),
      O => data_ex0_44_mux0000
    );
  data_ex0_43_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(42),
      I5 => data_ex0(43),
      O => data_ex0_43_mux0000
    );
  data_ex0_42_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(41),
      I5 => data_ex0(42),
      O => data_ex0_42_mux0000
    );
  data_ex0_41_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(40),
      I5 => data_ex0(41),
      O => data_ex0_41_mux0000
    );
  data_ex0_40_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(39),
      I5 => data_ex0(40),
      O => data_ex0_40_mux0000
    );
  data_ex0_3_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(2),
      I5 => data_ex0(3),
      O => data_ex0_3_mux0000
    );
  data_ex0_39_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(38),
      I5 => data_ex0(39),
      O => data_ex0_39_mux0000
    );
  data_ex0_38_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(37),
      I5 => data_ex0(38),
      O => data_ex0_38_mux0000
    );
  data_ex0_37_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(36),
      I5 => data_ex0(37),
      O => data_ex0_37_mux0000
    );
  data_ex0_36_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(35),
      I5 => data_ex0(36),
      O => data_ex0_36_mux0000
    );
  data_ex0_35_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(34),
      I5 => data_ex0(35),
      O => data_ex0_35_mux0000
    );
  data_ex0_34_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(33),
      I5 => data_ex0(34),
      O => data_ex0_34_mux0000
    );
  data_ex0_33_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(32),
      I5 => data_ex0(33),
      O => data_ex0_33_mux0000
    );
  data_ex0_32_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(31),
      I5 => data_ex0(32),
      O => data_ex0_32_mux0000
    );
  data_ex0_31_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(30),
      I5 => data_ex0(31),
      O => data_ex0_31_mux0000
    );
  data_ex0_30_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(29),
      I5 => data_ex0(30),
      O => data_ex0_30_mux0000
    );
  data_ex0_2_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(1),
      I5 => data_ex0(2),
      O => data_ex0_2_mux0000
    );
  data_ex0_29_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(28),
      I5 => data_ex0(29),
      O => data_ex0_29_mux0000
    );
  data_ex0_28_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(27),
      I5 => data_ex0(28),
      O => data_ex0_28_mux0000
    );
  data_ex0_27_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(26),
      I5 => data_ex0(27),
      O => data_ex0_27_mux0000
    );
  data_ex0_26_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(25),
      I5 => data_ex0(26),
      O => data_ex0_26_mux0000
    );
  data_ex0_25_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(24),
      I5 => data_ex0(25),
      O => data_ex0_25_mux0000
    );
  data_ex0_24_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(23),
      I5 => data_ex0(24),
      O => data_ex0_24_mux0000
    );
  data_ex0_23_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(22),
      I5 => data_ex0(23),
      O => data_ex0_23_mux0000
    );
  data_ex0_22_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(21),
      I5 => data_ex0(22),
      O => data_ex0_22_mux0000
    );
  data_ex0_21_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(20),
      I5 => data_ex0(21),
      O => data_ex0_21_mux0000
    );
  data_ex0_20_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(19),
      I5 => data_ex0(20),
      O => data_ex0_20_mux0000
    );
  data_ex0_1_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(0),
      I5 => data_ex0(1),
      O => data_ex0_1_mux0000
    );
  data_ex0_19_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(18),
      I5 => data_ex0(19),
      O => data_ex0_19_mux0000
    );
  data_ex0_18_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(17),
      I5 => data_ex0(18),
      O => data_ex0_18_mux0000
    );
  data_ex0_17_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(16),
      I5 => data_ex0(17),
      O => data_ex0_17_mux0000
    );
  data_ex0_16_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(15),
      I5 => data_ex0(16),
      O => data_ex0_16_mux0000
    );
  data_ex0_15_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(14),
      I5 => data_ex0(15),
      O => data_ex0_15_mux0000
    );
  data_ex0_14_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(13),
      I5 => data_ex0(14),
      O => data_ex0_14_mux0000
    );
  data_ex0_13_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(12),
      I5 => data_ex0(13),
      O => data_ex0_13_mux0000
    );
  data_ex0_12_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(11),
      I5 => data_ex0(12),
      O => data_ex0_12_mux0000
    );
  data_ex0_11_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(10),
      I5 => data_ex0(11),
      O => data_ex0_11_mux0000
    );
  data_ex0_10_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_3399,
      I1 => N63,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(9),
      I5 => data_ex0(10),
      O => data_ex0_10_mux0000
    );
  data_ex0_0_not00011 : LUT5
    generic map(
      INIT => X"8888888A"
    )
    port map (
      I0 => do_data_en,
      I1 => cnt1_z_3399,
      I2 => block_mode(2),
      I3 => block_mode(1),
      I4 => block_mode(3),
      O => data_ex0_0_not0001
    );
  data_expect_8_mux0000124 : MUXF7
    port map (
      I0 => N248,
      I1 => N249,
      S => block_mode(1),
      O => data_expect_8_mux0000
    );
  data_expect_8_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(8),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(8),
      I5 => data_expect_8_mux000031_4598,
      O => N248
    );
  data_expect_8_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(8),
      I4 => data_ex1(8),
      I5 => data_expect_8_mux000031_4598,
      O => N249
    );
  data_expect_5_mux0000124 : MUXF7
    port map (
      I0 => N250,
      I1 => N251,
      S => block_mode(1),
      O => data_expect_5_mux0000
    );
  data_expect_5_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(5),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(5),
      I5 => data_expect_5_mux000031_4573,
      O => N250
    );
  data_expect_5_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(5),
      I4 => data_ex1(5),
      I5 => data_expect_5_mux000031_4573,
      O => N251
    );
  data_expect_31_mux0000124 : MUXF7
    port map (
      I0 => N252,
      I1 => N253,
      S => block_mode(1),
      O => data_expect_31_mux0000
    );
  data_expect_31_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(31),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(31),
      I5 => data_expect_31_mux000031_4450,
      O => N252
    );
  data_expect_31_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(31),
      I4 => data_ex1(31),
      I5 => data_expect_31_mux000031_4450,
      O => N253
    );
  data_expect_29_mux0000124 : MUXF7
    port map (
      I0 => N254,
      I1 => N255,
      S => block_mode(1),
      O => data_expect_29_mux0000
    );
  data_expect_29_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(29),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(29),
      I5 => data_expect_29_mux000031_4441,
      O => N254
    );
  data_expect_29_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(29),
      I4 => data_ex1(29),
      I5 => data_expect_29_mux000031_4441,
      O => N255
    );
  data_expect_26_mux0000124 : MUXF7
    port map (
      I0 => N256,
      I1 => N257,
      S => block_mode(1),
      O => data_expect_26_mux0000
    );
  data_expect_26_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(26),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(26),
      I5 => data_expect_26_mux000031_4432,
      O => N256
    );
  data_expect_26_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(26),
      I4 => data_ex1(26),
      I5 => data_expect_26_mux000031_4432,
      O => N257
    );
  data_expect_24_mux0000124 : MUXF7
    port map (
      I0 => N258,
      I1 => N259,
      S => block_mode(1),
      O => data_expect_24_mux0000
    );
  data_expect_24_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(24),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(24),
      I5 => data_expect_24_mux000031_4426,
      O => N258
    );
  data_expect_24_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(24),
      I4 => data_ex1(24),
      I5 => data_expect_24_mux000031_4426,
      O => N259
    );
  data_expect_23_mux0000124 : MUXF7
    port map (
      I0 => N260,
      I1 => N261,
      S => block_mode(1),
      O => data_expect_23_mux0000
    );
  data_expect_23_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(23),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(23),
      I5 => data_expect_23_mux000031_4423,
      O => N260
    );
  data_expect_23_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(23),
      I4 => data_ex1(23),
      I5 => data_expect_23_mux000031_4423,
      O => N261
    );
  data_expect_21_mux0000124 : MUXF7
    port map (
      I0 => N262,
      I1 => N263,
      S => block_mode(1),
      O => data_expect_21_mux0000
    );
  data_expect_21_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(21),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(21),
      I5 => data_expect_21_mux000031_4417,
      O => N262
    );
  data_expect_21_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(21),
      I4 => data_ex1(21),
      I5 => data_expect_21_mux000031_4417,
      O => N263
    );
  data_expect_1_mux0000124 : MUXF7
    port map (
      I0 => N264,
      I1 => N265,
      S => block_mode(1),
      O => data_expect_1_mux0000
    );
  data_expect_1_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(1),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(1),
      I5 => data_expect_1_mux000031_4410,
      O => N264
    );
  data_expect_1_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(1),
      I4 => data_ex1(1),
      I5 => data_expect_1_mux000031_4410,
      O => N265
    );
  data_expect_18_mux0000124 : MUXF7
    port map (
      I0 => N266,
      I1 => N267,
      S => block_mode(1),
      O => data_expect_18_mux0000
    );
  data_expect_18_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(18),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(18),
      I5 => data_expect_18_mux000031_4405,
      O => N266
    );
  data_expect_18_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(18),
      I4 => data_ex1(18),
      I5 => data_expect_18_mux000031_4405,
      O => N267
    );
  data_expect_16_mux0000124 : MUXF7
    port map (
      I0 => N268,
      I1 => N269,
      S => block_mode(1),
      O => data_expect_16_mux0000
    );
  data_expect_16_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(16),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(16),
      I5 => data_expect_16_mux000031_4399,
      O => N268
    );
  data_expect_16_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(16),
      I4 => data_ex1(16),
      I5 => data_expect_16_mux000031_4399,
      O => N269
    );
  data_expect_0_mux0000124 : MUXF7
    port map (
      I0 => N270,
      I1 => N271,
      S => block_mode(1),
      O => data_expect_0_mux0000
    );
  data_expect_0_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(0),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(0),
      I5 => data_expect_0_mux000031_4377,
      O => N270
    );
  data_expect_0_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(0),
      I4 => data_ex1(0),
      I5 => data_expect_0_mux000031_4377,
      O => N271
    );
  data_expect_63_mux000099 : MUXF7
    port map (
      I0 => N272,
      I1 => N273,
      S => block_mode(1),
      O => data_expect_63_mux000099_4590
    );
  data_expect_63_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(63),
      I3 => data_ex0(63),
      I4 => data_expect(63),
      O => N272
    );
  data_expect_63_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(63),
      I4 => data_ex1(63),
      I5 => data_expect(63),
      O => N273
    );
  data_expect_62_mux000099 : MUXF7
    port map (
      I0 => N274,
      I1 => N275,
      S => block_mode(1),
      O => data_expect_62_mux000099_4586
    );
  data_expect_62_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(62),
      I3 => data_ex0(62),
      I4 => data_expect(62),
      O => N274
    );
  data_expect_62_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(62),
      I4 => data_ex1(62),
      I5 => data_expect(62),
      O => N275
    );
  data_expect_61_mux000099 : MUXF7
    port map (
      I0 => N276,
      I1 => N277,
      S => block_mode(1),
      O => data_expect_61_mux000099_4582
    );
  data_expect_61_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(61),
      I3 => data_ex0(61),
      I4 => data_expect(61),
      O => N276
    );
  data_expect_61_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(61),
      I4 => data_ex1(61),
      I5 => data_expect(61),
      O => N277
    );
  data_expect_60_mux000099 : MUXF7
    port map (
      I0 => N278,
      I1 => N279,
      S => block_mode(1),
      O => data_expect_60_mux000099_4578
    );
  data_expect_60_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(60),
      I3 => data_ex0(60),
      I4 => data_expect(60),
      O => N278
    );
  data_expect_60_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(60),
      I4 => data_ex1(60),
      I5 => data_expect(60),
      O => N279
    );
  data_expect_59_mux000099 : MUXF7
    port map (
      I0 => N280,
      I1 => N281,
      S => block_mode(1),
      O => data_expect_59_mux000099_4571
    );
  data_expect_59_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(59),
      I3 => data_ex0(59),
      I4 => data_expect(59),
      O => N280
    );
  data_expect_59_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(59),
      I4 => data_ex1(59),
      I5 => data_expect(59),
      O => N281
    );
  data_expect_58_mux000099 : MUXF7
    port map (
      I0 => N282,
      I1 => N283,
      S => block_mode(1),
      O => data_expect_58_mux000099_4567
    );
  data_expect_58_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(58),
      I3 => data_ex0(58),
      I4 => data_expect(58),
      O => N282
    );
  data_expect_58_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(58),
      I4 => data_ex1(58),
      I5 => data_expect(58),
      O => N283
    );
  data_expect_57_mux000099 : MUXF7
    port map (
      I0 => N284,
      I1 => N285,
      S => block_mode(1),
      O => data_expect_57_mux000099_4563
    );
  data_expect_57_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(57),
      I3 => data_ex0(57),
      I4 => data_expect(57),
      O => N284
    );
  data_expect_57_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(57),
      I4 => data_ex1(57),
      I5 => data_expect(57),
      O => N285
    );
  data_expect_56_mux000099 : MUXF7
    port map (
      I0 => N286,
      I1 => N287,
      S => block_mode(1),
      O => data_expect_56_mux000099_4559
    );
  data_expect_56_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(56),
      I3 => data_ex0(56),
      I4 => data_expect(56),
      O => N286
    );
  data_expect_56_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(56),
      I4 => data_ex1(56),
      I5 => data_expect(56),
      O => N287
    );
  data_expect_55_mux000099 : MUXF7
    port map (
      I0 => N288,
      I1 => N289,
      S => block_mode(1),
      O => data_expect_55_mux000099_4555
    );
  data_expect_55_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(55),
      I3 => data_ex0(55),
      I4 => data_expect(55),
      O => N288
    );
  data_expect_55_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(55),
      I4 => data_ex1(55),
      I5 => data_expect(55),
      O => N289
    );
  data_expect_54_mux000099 : MUXF7
    port map (
      I0 => N290,
      I1 => N291,
      S => block_mode(1),
      O => data_expect_54_mux000099_4551
    );
  data_expect_54_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(54),
      I3 => data_ex0(54),
      I4 => data_expect(54),
      O => N290
    );
  data_expect_54_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(54),
      I4 => data_ex1(54),
      I5 => data_expect(54),
      O => N291
    );
  data_expect_53_mux000099 : MUXF7
    port map (
      I0 => N292,
      I1 => N293,
      S => block_mode(1),
      O => data_expect_53_mux000099_4547
    );
  data_expect_53_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(53),
      I3 => data_ex0(53),
      I4 => data_expect(53),
      O => N292
    );
  data_expect_53_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(53),
      I4 => data_ex1(53),
      I5 => data_expect(53),
      O => N293
    );
  data_expect_52_mux000099 : MUXF7
    port map (
      I0 => N294,
      I1 => N295,
      S => block_mode(1),
      O => data_expect_52_mux000099_4543
    );
  data_expect_52_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(52),
      I3 => data_ex0(52),
      I4 => data_expect(52),
      O => N294
    );
  data_expect_52_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(52),
      I4 => data_ex1(52),
      I5 => data_expect(52),
      O => N295
    );
  data_expect_51_mux000099 : MUXF7
    port map (
      I0 => N296,
      I1 => N297,
      S => block_mode(1),
      O => data_expect_51_mux000099_4539
    );
  data_expect_51_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(51),
      I3 => data_ex0(51),
      I4 => data_expect(51),
      O => N296
    );
  data_expect_51_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(51),
      I4 => data_ex1(51),
      I5 => data_expect(51),
      O => N297
    );
  data_expect_50_mux000099 : MUXF7
    port map (
      I0 => N298,
      I1 => N299,
      S => block_mode(1),
      O => data_expect_50_mux000099_4535
    );
  data_expect_50_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(50),
      I3 => data_ex0(50),
      I4 => data_expect(50),
      O => N298
    );
  data_expect_50_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(50),
      I4 => data_ex1(50),
      I5 => data_expect(50),
      O => N299
    );
  data_expect_49_mux000099 : MUXF7
    port map (
      I0 => N300,
      I1 => N301,
      S => block_mode(1),
      O => data_expect_49_mux000099_4528
    );
  data_expect_49_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(49),
      I3 => data_ex0(49),
      I4 => data_expect(49),
      O => N300
    );
  data_expect_49_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(49),
      I4 => data_ex1(49),
      I5 => data_expect(49),
      O => N301
    );
  data_expect_48_mux000099 : MUXF7
    port map (
      I0 => N302,
      I1 => N303,
      S => block_mode(1),
      O => data_expect_48_mux000099_4524
    );
  data_expect_48_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(48),
      I3 => data_ex0(48),
      I4 => data_expect(48),
      O => N302
    );
  data_expect_48_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(48),
      I4 => data_ex1(48),
      I5 => data_expect(48),
      O => N303
    );
  data_expect_47_mux000099 : MUXF7
    port map (
      I0 => N304,
      I1 => N305,
      S => block_mode(1),
      O => data_expect_47_mux000099_4520
    );
  data_expect_47_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(47),
      I3 => data_ex0(47),
      I4 => data_expect(47),
      O => N304
    );
  data_expect_47_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(47),
      I4 => data_ex1(47),
      I5 => data_expect(47),
      O => N305
    );
  data_expect_46_mux000099 : MUXF7
    port map (
      I0 => N306,
      I1 => N307,
      S => block_mode(1),
      O => data_expect_46_mux000099_4516
    );
  data_expect_46_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(46),
      I3 => data_ex0(46),
      I4 => data_expect(46),
      O => N306
    );
  data_expect_46_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(46),
      I4 => data_ex1(46),
      I5 => data_expect(46),
      O => N307
    );
  data_expect_45_mux000099 : MUXF7
    port map (
      I0 => N308,
      I1 => N309,
      S => block_mode(1),
      O => data_expect_45_mux000099_4512
    );
  data_expect_45_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(45),
      I3 => data_ex0(45),
      I4 => data_expect(45),
      O => N308
    );
  data_expect_45_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(45),
      I4 => data_ex1(45),
      I5 => data_expect(45),
      O => N309
    );
  data_expect_44_mux000099 : MUXF7
    port map (
      I0 => N310,
      I1 => N311,
      S => block_mode(1),
      O => data_expect_44_mux000099_4508
    );
  data_expect_44_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(44),
      I3 => data_ex0(44),
      I4 => data_expect(44),
      O => N310
    );
  data_expect_44_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(44),
      I4 => data_ex1(44),
      I5 => data_expect(44),
      O => N311
    );
  data_expect_43_mux000099 : MUXF7
    port map (
      I0 => N312,
      I1 => N313,
      S => block_mode(1),
      O => data_expect_43_mux000099_4504
    );
  data_expect_43_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(43),
      I3 => data_ex0(43),
      I4 => data_expect(43),
      O => N312
    );
  data_expect_43_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(43),
      I4 => data_ex1(43),
      I5 => data_expect(43),
      O => N313
    );
  data_expect_42_mux000099 : MUXF7
    port map (
      I0 => N314,
      I1 => N315,
      S => block_mode(1),
      O => data_expect_42_mux000099_4500
    );
  data_expect_42_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(42),
      I3 => data_ex0(42),
      I4 => data_expect(42),
      O => N314
    );
  data_expect_42_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(42),
      I4 => data_ex1(42),
      I5 => data_expect(42),
      O => N315
    );
  data_expect_41_mux000099 : MUXF7
    port map (
      I0 => N316,
      I1 => N317,
      S => block_mode(1),
      O => data_expect_41_mux000099_4496
    );
  data_expect_41_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(41),
      I3 => data_ex0(41),
      I4 => data_expect(41),
      O => N316
    );
  data_expect_41_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(41),
      I4 => data_ex1(41),
      I5 => data_expect(41),
      O => N317
    );
  data_expect_40_mux000099 : MUXF7
    port map (
      I0 => N318,
      I1 => N319,
      S => block_mode(1),
      O => data_expect_40_mux000099_4492
    );
  data_expect_40_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(40),
      I3 => data_ex0(40),
      I4 => data_expect(40),
      O => N318
    );
  data_expect_40_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(40),
      I4 => data_ex1(40),
      I5 => data_expect(40),
      O => N319
    );
  data_expect_39_mux000099 : MUXF7
    port map (
      I0 => N320,
      I1 => N321,
      S => block_mode(1),
      O => data_expect_39_mux000099_4482
    );
  data_expect_39_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(39),
      I3 => data_ex0(39),
      I4 => data_expect(39),
      O => N320
    );
  data_expect_39_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(39),
      I4 => data_ex1(39),
      I5 => data_expect(39),
      O => N321
    );
  data_expect_38_mux000099 : MUXF7
    port map (
      I0 => N322,
      I1 => N323,
      S => block_mode(1),
      O => data_expect_38_mux000099_4478
    );
  data_expect_38_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(38),
      I3 => data_ex0(38),
      I4 => data_expect(38),
      O => N322
    );
  data_expect_38_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(38),
      I4 => data_ex1(38),
      I5 => data_expect(38),
      O => N323
    );
  data_expect_37_mux000099 : MUXF7
    port map (
      I0 => N324,
      I1 => N325,
      S => block_mode(1),
      O => data_expect_37_mux000099_4474
    );
  data_expect_37_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(37),
      I3 => data_ex0(37),
      I4 => data_expect(37),
      O => N324
    );
  data_expect_37_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(37),
      I4 => data_ex1(37),
      I5 => data_expect(37),
      O => N325
    );
  data_expect_36_mux000099 : MUXF7
    port map (
      I0 => N326,
      I1 => N327,
      S => block_mode(1),
      O => data_expect_36_mux000099_4470
    );
  data_expect_36_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(36),
      I3 => data_ex0(36),
      I4 => data_expect(36),
      O => N326
    );
  data_expect_36_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(36),
      I4 => data_ex1(36),
      I5 => data_expect(36),
      O => N327
    );
  data_expect_35_mux000099 : MUXF7
    port map (
      I0 => N328,
      I1 => N329,
      S => block_mode(1),
      O => data_expect_35_mux000099_4466
    );
  data_expect_35_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(35),
      I3 => data_ex0(35),
      I4 => data_expect(35),
      O => N328
    );
  data_expect_35_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(35),
      I4 => data_ex1(35),
      I5 => data_expect(35),
      O => N329
    );
  data_expect_34_mux000099 : MUXF7
    port map (
      I0 => N330,
      I1 => N331,
      S => block_mode(1),
      O => data_expect_34_mux000099_4462
    );
  data_expect_34_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(34),
      I3 => data_ex0(34),
      I4 => data_expect(34),
      O => N330
    );
  data_expect_34_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(34),
      I4 => data_ex1(34),
      I5 => data_expect(34),
      O => N331
    );
  data_expect_33_mux000099 : MUXF7
    port map (
      I0 => N332,
      I1 => N333,
      S => block_mode(1),
      O => data_expect_33_mux000099_4458
    );
  data_expect_33_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(33),
      I3 => data_ex0(33),
      I4 => data_expect(33),
      O => N332
    );
  data_expect_33_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(33),
      I4 => data_ex1(33),
      I5 => data_expect(33),
      O => N333
    );
  data_expect_32_mux000099 : MUXF7
    port map (
      I0 => N334,
      I1 => N335,
      S => block_mode(1),
      O => data_expect_32_mux000099_4454
    );
  data_expect_32_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(32),
      I3 => data_ex0(32),
      I4 => data_expect(32),
      O => N334
    );
  data_expect_32_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(32),
      I4 => data_ex1(32),
      I5 => data_expect(32),
      O => N335
    );
  data_expect_9_mux000099 : MUXF7
    port map (
      I0 => N336,
      I1 => N337,
      S => block_mode(1),
      O => data_expect_9_mux000099_4601
    );
  data_expect_9_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(9),
      I3 => data_ex0(9),
      I4 => data_expect(9),
      O => N336
    );
  data_expect_9_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(9),
      I4 => data_ex1(9),
      I5 => data_expect(9),
      O => N337
    );
  data_expect_7_mux000099 : MUXF7
    port map (
      I0 => N338,
      I1 => N339,
      S => block_mode(1),
      O => data_expect_7_mux000099_4595
    );
  data_expect_7_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(7),
      I3 => data_ex0(7),
      I4 => data_expect(7),
      O => N338
    );
  data_expect_7_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(7),
      I4 => data_ex1(7),
      I5 => data_expect(7),
      O => N339
    );
  data_expect_6_mux000099 : MUXF7
    port map (
      I0 => N340,
      I1 => N341,
      S => block_mode(1),
      O => data_expect_6_mux000099_4592
    );
  data_expect_6_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(6),
      I3 => data_ex0(6),
      I4 => data_expect(6),
      O => N340
    );
  data_expect_6_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(6),
      I4 => data_ex1(6),
      I5 => data_expect(6),
      O => N341
    );
  data_expect_4_mux000099 : MUXF7
    port map (
      I0 => N342,
      I1 => N343,
      S => block_mode(1),
      O => data_expect_4_mux000099_4530
    );
  data_expect_4_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(4),
      I3 => data_ex0(4),
      I4 => data_expect(4),
      O => N342
    );
  data_expect_4_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(4),
      I4 => data_ex1(4),
      I5 => data_expect(4),
      O => N343
    );
  data_expect_3_mux000099 : MUXF7
    port map (
      I0 => N344,
      I1 => N345,
      S => block_mode(1),
      O => data_expect_3_mux000099_4486
    );
  data_expect_3_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(3),
      I3 => data_ex0(3),
      I4 => data_expect(3),
      O => N344
    );
  data_expect_3_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(3),
      I4 => data_ex1(3),
      I5 => data_expect(3),
      O => N345
    );
  data_expect_30_mux000099 : MUXF7
    port map (
      I0 => N346,
      I1 => N347,
      S => block_mode(1),
      O => data_expect_30_mux000099_4447
    );
  data_expect_30_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(30),
      I3 => data_ex0(30),
      I4 => data_expect(30),
      O => N346
    );
  data_expect_30_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(30),
      I4 => data_ex1(30),
      I5 => data_expect(30),
      O => N347
    );
  data_expect_2_mux000099 : MUXF7
    port map (
      I0 => N348,
      I1 => N349,
      S => block_mode(1),
      O => data_expect_2_mux000099_4443
    );
  data_expect_2_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(2),
      I3 => data_ex0(2),
      I4 => data_expect(2),
      O => N348
    );
  data_expect_2_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(2),
      I4 => data_ex1(2),
      I5 => data_expect(2),
      O => N349
    );
  data_expect_28_mux000099 : MUXF7
    port map (
      I0 => N350,
      I1 => N351,
      S => block_mode(1),
      O => data_expect_28_mux000099_4438
    );
  data_expect_28_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(28),
      I3 => data_ex0(28),
      I4 => data_expect(28),
      O => N350
    );
  data_expect_28_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(28),
      I4 => data_ex1(28),
      I5 => data_expect(28),
      O => N351
    );
  data_expect_27_mux000099 : MUXF7
    port map (
      I0 => N352,
      I1 => N353,
      S => block_mode(1),
      O => data_expect_27_mux000099_4435
    );
  data_expect_27_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(27),
      I3 => data_ex0(27),
      I4 => data_expect(27),
      O => N352
    );
  data_expect_27_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(27),
      I4 => data_ex1(27),
      I5 => data_expect(27),
      O => N353
    );
  data_expect_25_mux000099 : MUXF7
    port map (
      I0 => N354,
      I1 => N355,
      S => block_mode(1),
      O => data_expect_25_mux000099_4429
    );
  data_expect_25_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(25),
      I3 => data_ex0(25),
      I4 => data_expect(25),
      O => N354
    );
  data_expect_25_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(25),
      I4 => data_ex1(25),
      I5 => data_expect(25),
      O => N355
    );
  data_expect_22_mux000099 : MUXF7
    port map (
      I0 => N356,
      I1 => N357,
      S => block_mode(1),
      O => data_expect_22_mux000099_4420
    );
  data_expect_22_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(22),
      I3 => data_ex0(22),
      I4 => data_expect(22),
      O => N356
    );
  data_expect_22_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(22),
      I4 => data_ex1(22),
      I5 => data_expect(22),
      O => N357
    );
  data_expect_20_mux000099 : MUXF7
    port map (
      I0 => N358,
      I1 => N359,
      S => block_mode(1),
      O => data_expect_20_mux000099_4414
    );
  data_expect_20_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(20),
      I3 => data_ex0(20),
      I4 => data_expect(20),
      O => N358
    );
  data_expect_20_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(20),
      I4 => data_ex1(20),
      I5 => data_expect(20),
      O => N359
    );
  data_expect_19_mux000099 : MUXF7
    port map (
      I0 => N360,
      I1 => N361,
      S => block_mode(1),
      O => data_expect_19_mux000099_4408
    );
  data_expect_19_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(19),
      I3 => data_ex0(19),
      I4 => data_expect(19),
      O => N360
    );
  data_expect_19_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(19),
      I4 => data_ex1(19),
      I5 => data_expect(19),
      O => N361
    );
  data_expect_17_mux000099 : MUXF7
    port map (
      I0 => N362,
      I1 => N363,
      S => block_mode(1),
      O => data_expect_17_mux000099_4402
    );
  data_expect_17_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(17),
      I3 => data_ex0(17),
      I4 => data_expect(17),
      O => N362
    );
  data_expect_17_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(17),
      I4 => data_ex1(17),
      I5 => data_expect(17),
      O => N363
    );
  data_expect_15_mux000099 : MUXF7
    port map (
      I0 => N364,
      I1 => N365,
      S => block_mode(1),
      O => data_expect_15_mux000099_4396
    );
  data_expect_15_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(15),
      I3 => data_ex0(15),
      I4 => data_expect(15),
      O => N364
    );
  data_expect_15_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(15),
      I4 => data_ex1(15),
      I5 => data_expect(15),
      O => N365
    );
  data_expect_14_mux000099 : MUXF7
    port map (
      I0 => N366,
      I1 => N367,
      S => block_mode(1),
      O => data_expect_14_mux000099_4393
    );
  data_expect_14_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(14),
      I3 => data_ex0(14),
      I4 => data_expect(14),
      O => N366
    );
  data_expect_14_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(14),
      I4 => data_ex1(14),
      I5 => data_expect(14),
      O => N367
    );
  data_expect_13_mux000099 : MUXF7
    port map (
      I0 => N368,
      I1 => N369,
      S => block_mode(1),
      O => data_expect_13_mux000099_4390
    );
  data_expect_13_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(13),
      I3 => data_ex0(13),
      I4 => data_expect(13),
      O => N368
    );
  data_expect_13_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(13),
      I4 => data_ex1(13),
      I5 => data_expect(13),
      O => N369
    );
  data_expect_12_mux000099 : MUXF7
    port map (
      I0 => N370,
      I1 => N371,
      S => block_mode(1),
      O => data_expect_12_mux000099_4387
    );
  data_expect_12_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(12),
      I3 => data_ex0(12),
      I4 => data_expect(12),
      O => N370
    );
  data_expect_12_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(12),
      I4 => data_ex1(12),
      I5 => data_expect(12),
      O => N371
    );
  data_expect_11_mux000099 : MUXF7
    port map (
      I0 => N372,
      I1 => N373,
      S => block_mode(1),
      O => data_expect_11_mux000099_4384
    );
  data_expect_11_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(11),
      I3 => data_ex0(11),
      I4 => data_expect(11),
      O => N372
    );
  data_expect_11_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(11),
      I4 => data_ex1(11),
      I5 => data_expect(11),
      O => N373
    );
  data_expect_10_mux000099 : MUXF7
    port map (
      I0 => N374,
      I1 => N375,
      S => block_mode(1),
      O => data_expect_10_mux000099_4381
    );
  data_expect_10_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(10),
      I3 => data_ex0(10),
      I4 => data_expect(10),
      O => N374
    );
  data_expect_10_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(10),
      I4 => data_ex1(10),
      I5 => data_expect(10),
      O => N375
    );
  Madd_data_ex4_63_32_add0000_lut_0_INV_0 : INV
    port map (
      I => data_ex4(32),
      O => Madd_data_ex4_63_32_add0000_lut(0)
    );
  Madd_data_ex4_31_0_add0000_lut_0_INV_0 : INV
    port map (
      I => data_ex4(0),
      O => Madd_data_ex4_31_0_add0000_lut(0)
    );
  Msub_cnt1_eq_addsub0000_lut_1_INV_0 : INV
    port map (
      I => test_check_size(1),
      O => Msub_cnt1_eq_addsub0000_lut(1)
    );
  Msub_cnt1_eq_addsub0000_lut_2_INV_0 : INV
    port map (
      I => test_check_size(2),
      O => Msub_cnt1_eq_addsub0000_lut(2)
    );
  Msub_cnt1_eq_addsub0000_lut_3_INV_0 : INV
    port map (
      I => test_check_size(3),
      O => Msub_cnt1_eq_addsub0000_lut(3)
    );
  Msub_cnt1_eq_addsub0000_lut_4_INV_0 : INV
    port map (
      I => test_check_size(4),
      O => Msub_cnt1_eq_addsub0000_lut(4)
    );
  Msub_cnt1_eq_addsub0000_lut_5_INV_0 : INV
    port map (
      I => test_check_size(5),
      O => Msub_cnt1_eq_addsub0000_lut(5)
    );
  Msub_cnt1_eq_addsub0000_lut_6_INV_0 : INV
    port map (
      I => test_check_size(6),
      O => Msub_cnt1_eq_addsub0000_lut(6)
    );
  Msub_cnt1_eq_addsub0000_lut_7_INV_0 : INV
    port map (
      I => test_check_size(7),
      O => Msub_cnt1_eq_addsub0000_lut(7)
    );
  Msub_cnt1_eq_addsub0000_lut_8_INV_0 : INV
    port map (
      I => test_check_size(8),
      O => Msub_cnt1_eq_addsub0000_lut(8)
    );
  Msub_cnt1_eq_addsub0000_lut_9_INV_0 : INV
    port map (
      I => test_check_size(9),
      O => Msub_cnt1_eq_addsub0000_lut(9)
    );
  Msub_cnt1_eq_addsub0000_lut_10_INV_0 : INV
    port map (
      I => test_check_size(10),
      O => Msub_cnt1_eq_addsub0000_lut(10)
    );
  Msub_cnt1_eq_addsub0000_lut_11_INV_0 : INV
    port map (
      I => test_check_size(11),
      O => Msub_cnt1_eq_addsub0000_lut(11)
    );
  Msub_cnt1_eq_addsub0000_lut_12_INV_0 : INV
    port map (
      I => test_check_size(12),
      O => Msub_cnt1_eq_addsub0000_lut(12)
    );
  Msub_cnt1_eq_addsub0000_lut_13_INV_0 : INV
    port map (
      I => test_check_size(13),
      O => Msub_cnt1_eq_addsub0000_lut(13)
    );
  Msub_cnt1_eq_addsub0000_lut_14_INV_0 : INV
    port map (
      I => test_check_size(14),
      O => Msub_cnt1_eq_addsub0000_lut(14)
    );
  Msub_cnt1_eq_addsub0000_lut_15_INV_0 : INV
    port map (
      I => test_check_size(15),
      O => Msub_cnt1_eq_addsub0000_lut(15)
    );
  Mcount_total_err_lut_0_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_total_err(0),
      O => Mcount_total_err_lut(0)
    );
  Mcount_block_ok_lut_0_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_block_ok(0),
      O => Mcount_block_ok_lut(0)
    );
  Mcount_block_err_lut_0_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_block_err(0),
      O => Mcount_block_err_lut(0)
    );
  Mcount_block_rd_lut_0_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_block_rd(0),
      O => Mcount_block_rd_lut(0)
    );
  Mcount_cnt1_lut_0_INV_0 : INV
    port map (
      I => cnt1(0),
      O => Mcount_cnt1_lut(0)
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_test_generate is
  port (
    di_clk : in STD_LOGIC := 'X'; 
    di_data_we : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    di_fifo_rst : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    di_start : in STD_LOGIC := 'X'; 
    di_flag_paf : in STD_LOGIC := 'X'; 
    di_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    test_gen_bl_wr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
    test_gen_ctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_gen_size : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_gen_cnt1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    test_gen_cnt2 : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end cl_test_generate;

architecture STRUCTURE of cl_test_generate is
  signal Madd_data_ex4_31_0_add0000_cy_10_rt_665 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_11_rt_667 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_12_rt_669 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_13_rt_671 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_14_rt_673 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_15_rt_675 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_16_rt_677 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_17_rt_679 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_18_rt_681 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_19_rt_683 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_1_rt_685 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_20_rt_687 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_21_rt_689 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_22_rt_691 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_23_rt_693 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_24_rt_695 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_25_rt_697 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_26_rt_699 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_27_rt_701 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_28_rt_703 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_29_rt_705 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_2_rt_707 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_30_rt_709 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_3_rt_711 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_4_rt_713 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_5_rt_715 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_6_rt_717 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_7_rt_719 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_8_rt_721 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy_9_rt_723 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_xor_31_rt_725 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_10_rt_728 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_11_rt_730 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_12_rt_732 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_13_rt_734 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_14_rt_736 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_15_rt_738 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_16_rt_740 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_17_rt_742 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_18_rt_744 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_19_rt_746 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_1_rt_748 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_20_rt_750 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_21_rt_752 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_22_rt_754 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_23_rt_756 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_24_rt_758 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_25_rt_760 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_26_rt_762 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_27_rt_764 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_28_rt_766 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_29_rt_768 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_2_rt_770 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_30_rt_772 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_3_rt_774 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_4_rt_776 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_5_rt_778 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_6_rt_780 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_7_rt_782 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_8_rt_784 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_cy_9_rt_786 : STD_LOGIC; 
  signal Madd_data_ex4_63_32_add0000_xor_31_rt_788 : STD_LOGIC; 
  signal Mcount_block_mode : STD_LOGIC; 
  signal Mcount_block_mode1 : STD_LOGIC; 
  signal Mcount_block_mode2 : STD_LOGIC; 
  signal Mcount_block_mode3 : STD_LOGIC; 
  signal Mcount_block_rd_cy_10_rt_806 : STD_LOGIC; 
  signal Mcount_block_rd_cy_11_rt_808 : STD_LOGIC; 
  signal Mcount_block_rd_cy_12_rt_810 : STD_LOGIC; 
  signal Mcount_block_rd_cy_13_rt_812 : STD_LOGIC; 
  signal Mcount_block_rd_cy_14_rt_814 : STD_LOGIC; 
  signal Mcount_block_rd_cy_15_rt_816 : STD_LOGIC; 
  signal Mcount_block_rd_cy_16_rt_818 : STD_LOGIC; 
  signal Mcount_block_rd_cy_17_rt_820 : STD_LOGIC; 
  signal Mcount_block_rd_cy_18_rt_822 : STD_LOGIC; 
  signal Mcount_block_rd_cy_19_rt_824 : STD_LOGIC; 
  signal Mcount_block_rd_cy_1_rt_826 : STD_LOGIC; 
  signal Mcount_block_rd_cy_20_rt_828 : STD_LOGIC; 
  signal Mcount_block_rd_cy_21_rt_830 : STD_LOGIC; 
  signal Mcount_block_rd_cy_22_rt_832 : STD_LOGIC; 
  signal Mcount_block_rd_cy_23_rt_834 : STD_LOGIC; 
  signal Mcount_block_rd_cy_24_rt_836 : STD_LOGIC; 
  signal Mcount_block_rd_cy_25_rt_838 : STD_LOGIC; 
  signal Mcount_block_rd_cy_26_rt_840 : STD_LOGIC; 
  signal Mcount_block_rd_cy_27_rt_842 : STD_LOGIC; 
  signal Mcount_block_rd_cy_28_rt_844 : STD_LOGIC; 
  signal Mcount_block_rd_cy_29_rt_846 : STD_LOGIC; 
  signal Mcount_block_rd_cy_2_rt_848 : STD_LOGIC; 
  signal Mcount_block_rd_cy_30_rt_850 : STD_LOGIC; 
  signal Mcount_block_rd_cy_3_rt_852 : STD_LOGIC; 
  signal Mcount_block_rd_cy_4_rt_854 : STD_LOGIC; 
  signal Mcount_block_rd_cy_5_rt_856 : STD_LOGIC; 
  signal Mcount_block_rd_cy_6_rt_858 : STD_LOGIC; 
  signal Mcount_block_rd_cy_7_rt_860 : STD_LOGIC; 
  signal Mcount_block_rd_cy_8_rt_862 : STD_LOGIC; 
  signal Mcount_block_rd_cy_9_rt_864 : STD_LOGIC; 
  signal Mcount_block_rd_xor_31_rt_866 : STD_LOGIC; 
  signal Mcount_cnt1_cy_10_rt_869 : STD_LOGIC; 
  signal Mcount_cnt1_cy_11_rt_871 : STD_LOGIC; 
  signal Mcount_cnt1_cy_12_rt_873 : STD_LOGIC; 
  signal Mcount_cnt1_cy_13_rt_875 : STD_LOGIC; 
  signal Mcount_cnt1_cy_14_rt_877 : STD_LOGIC; 
  signal Mcount_cnt1_cy_15_rt_879 : STD_LOGIC; 
  signal Mcount_cnt1_cy_16_rt_881 : STD_LOGIC; 
  signal Mcount_cnt1_cy_17_rt_883 : STD_LOGIC; 
  signal Mcount_cnt1_cy_18_rt_885 : STD_LOGIC; 
  signal Mcount_cnt1_cy_19_rt_887 : STD_LOGIC; 
  signal Mcount_cnt1_cy_1_rt_889 : STD_LOGIC; 
  signal Mcount_cnt1_cy_20_rt_891 : STD_LOGIC; 
  signal Mcount_cnt1_cy_21_rt_893 : STD_LOGIC; 
  signal Mcount_cnt1_cy_22_rt_895 : STD_LOGIC; 
  signal Mcount_cnt1_cy_23_rt_897 : STD_LOGIC; 
  signal Mcount_cnt1_cy_2_rt_899 : STD_LOGIC; 
  signal Mcount_cnt1_cy_3_rt_901 : STD_LOGIC; 
  signal Mcount_cnt1_cy_4_rt_903 : STD_LOGIC; 
  signal Mcount_cnt1_cy_5_rt_905 : STD_LOGIC; 
  signal Mcount_cnt1_cy_6_rt_907 : STD_LOGIC; 
  signal Mcount_cnt1_cy_7_rt_909 : STD_LOGIC; 
  signal Mcount_cnt1_cy_8_rt_911 : STD_LOGIC; 
  signal Mcount_cnt1_cy_9_rt_913 : STD_LOGIC; 
  signal Mcount_cnt1_xor_24_rt_915 : STD_LOGIC; 
  signal Mcount_xcnt1 : STD_LOGIC; 
  signal Mcount_xcnt11 : STD_LOGIC; 
  signal Mcount_xcnt110 : STD_LOGIC; 
  signal Mcount_xcnt111 : STD_LOGIC; 
  signal Mcount_xcnt112 : STD_LOGIC; 
  signal Mcount_xcnt113 : STD_LOGIC; 
  signal Mcount_xcnt114 : STD_LOGIC; 
  signal Mcount_xcnt115 : STD_LOGIC; 
  signal Mcount_xcnt12 : STD_LOGIC; 
  signal Mcount_xcnt13 : STD_LOGIC; 
  signal Mcount_xcnt14 : STD_LOGIC; 
  signal Mcount_xcnt15 : STD_LOGIC; 
  signal Mcount_xcnt16 : STD_LOGIC; 
  signal Mcount_xcnt17 : STD_LOGIC; 
  signal Mcount_xcnt18 : STD_LOGIC; 
  signal Mcount_xcnt19 : STD_LOGIC; 
  signal Mcount_xcnt2 : STD_LOGIC; 
  signal Mcount_xcnt21 : STD_LOGIC; 
  signal Mcount_xcnt210 : STD_LOGIC; 
  signal Mcount_xcnt211 : STD_LOGIC; 
  signal Mcount_xcnt212 : STD_LOGIC; 
  signal Mcount_xcnt213 : STD_LOGIC; 
  signal Mcount_xcnt214 : STD_LOGIC; 
  signal Mcount_xcnt215 : STD_LOGIC; 
  signal Mcount_xcnt22 : STD_LOGIC; 
  signal Mcount_xcnt23 : STD_LOGIC; 
  signal Mcount_xcnt24 : STD_LOGIC; 
  signal Mcount_xcnt25 : STD_LOGIC; 
  signal Mcount_xcnt26 : STD_LOGIC; 
  signal Mcount_xcnt27 : STD_LOGIC; 
  signal Mcount_xcnt28 : STD_LOGIC; 
  signal Mcount_xcnt29 : STD_LOGIC; 
  signal Msub_cnt1_eq_addsub0000_cy_0_rt_1011 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N220 : STD_LOGIC; 
  signal N221 : STD_LOGIC; 
  signal N222 : STD_LOGIC; 
  signal N223 : STD_LOGIC; 
  signal N224 : STD_LOGIC; 
  signal N225 : STD_LOGIC; 
  signal N226 : STD_LOGIC; 
  signal N227 : STD_LOGIC; 
  signal N228 : STD_LOGIC; 
  signal N229 : STD_LOGIC; 
  signal N230 : STD_LOGIC; 
  signal N231 : STD_LOGIC; 
  signal N232 : STD_LOGIC; 
  signal N233 : STD_LOGIC; 
  signal N234 : STD_LOGIC; 
  signal N235 : STD_LOGIC; 
  signal N236 : STD_LOGIC; 
  signal N237 : STD_LOGIC; 
  signal N238 : STD_LOGIC; 
  signal N239 : STD_LOGIC; 
  signal N240 : STD_LOGIC; 
  signal N241 : STD_LOGIC; 
  signal N242 : STD_LOGIC; 
  signal N243 : STD_LOGIC; 
  signal N244 : STD_LOGIC; 
  signal N245 : STD_LOGIC; 
  signal N246 : STD_LOGIC; 
  signal N247 : STD_LOGIC; 
  signal N248 : STD_LOGIC; 
  signal N249 : STD_LOGIC; 
  signal N250 : STD_LOGIC; 
  signal N251 : STD_LOGIC; 
  signal N252 : STD_LOGIC; 
  signal N253 : STD_LOGIC; 
  signal N254 : STD_LOGIC; 
  signal N255 : STD_LOGIC; 
  signal N256 : STD_LOGIC; 
  signal N257 : STD_LOGIC; 
  signal N258 : STD_LOGIC; 
  signal N259 : STD_LOGIC; 
  signal N260 : STD_LOGIC; 
  signal N261 : STD_LOGIC; 
  signal N262 : STD_LOGIC; 
  signal N263 : STD_LOGIC; 
  signal N264 : STD_LOGIC; 
  signal N265 : STD_LOGIC; 
  signal N266 : STD_LOGIC; 
  signal N267 : STD_LOGIC; 
  signal N268 : STD_LOGIC; 
  signal N269 : STD_LOGIC; 
  signal N270 : STD_LOGIC; 
  signal N271 : STD_LOGIC; 
  signal N272 : STD_LOGIC; 
  signal N273 : STD_LOGIC; 
  signal N274 : STD_LOGIC; 
  signal N275 : STD_LOGIC; 
  signal N276 : STD_LOGIC; 
  signal N277 : STD_LOGIC; 
  signal N278 : STD_LOGIC; 
  signal N279 : STD_LOGIC; 
  signal N280 : STD_LOGIC; 
  signal N281 : STD_LOGIC; 
  signal N282 : STD_LOGIC; 
  signal N283 : STD_LOGIC; 
  signal N284 : STD_LOGIC; 
  signal N285 : STD_LOGIC; 
  signal N286 : STD_LOGIC; 
  signal N287 : STD_LOGIC; 
  signal N288 : STD_LOGIC; 
  signal N289 : STD_LOGIC; 
  signal N290 : STD_LOGIC; 
  signal N291 : STD_LOGIC; 
  signal N292 : STD_LOGIC; 
  signal N293 : STD_LOGIC; 
  signal N294 : STD_LOGIC; 
  signal N295 : STD_LOGIC; 
  signal N296 : STD_LOGIC; 
  signal N297 : STD_LOGIC; 
  signal N298 : STD_LOGIC; 
  signal N299 : STD_LOGIC; 
  signal N300 : STD_LOGIC; 
  signal N301 : STD_LOGIC; 
  signal N302 : STD_LOGIC; 
  signal N303 : STD_LOGIC; 
  signal N304 : STD_LOGIC; 
  signal N305 : STD_LOGIC; 
  signal N306 : STD_LOGIC; 
  signal N307 : STD_LOGIC; 
  signal N308 : STD_LOGIC; 
  signal N309 : STD_LOGIC; 
  signal N310 : STD_LOGIC; 
  signal N311 : STD_LOGIC; 
  signal N312 : STD_LOGIC; 
  signal N313 : STD_LOGIC; 
  signal N314 : STD_LOGIC; 
  signal N315 : STD_LOGIC; 
  signal N316 : STD_LOGIC; 
  signal N317 : STD_LOGIC; 
  signal N318 : STD_LOGIC; 
  signal N319 : STD_LOGIC; 
  signal N320 : STD_LOGIC; 
  signal N321 : STD_LOGIC; 
  signal N322 : STD_LOGIC; 
  signal N323 : STD_LOGIC; 
  signal N324 : STD_LOGIC; 
  signal N325 : STD_LOGIC; 
  signal N326 : STD_LOGIC; 
  signal N327 : STD_LOGIC; 
  signal N328 : STD_LOGIC; 
  signal N329 : STD_LOGIC; 
  signal N330 : STD_LOGIC; 
  signal N331 : STD_LOGIC; 
  signal N332 : STD_LOGIC; 
  signal N333 : STD_LOGIC; 
  signal N334 : STD_LOGIC; 
  signal N335 : STD_LOGIC; 
  signal N336 : STD_LOGIC; 
  signal N337 : STD_LOGIC; 
  signal N338 : STD_LOGIC; 
  signal N339 : STD_LOGIC; 
  signal N340 : STD_LOGIC; 
  signal N341 : STD_LOGIC; 
  signal N342 : STD_LOGIC; 
  signal N343 : STD_LOGIC; 
  signal N344 : STD_LOGIC; 
  signal N345 : STD_LOGIC; 
  signal N346 : STD_LOGIC; 
  signal N347 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal Result_0_1 : STD_LOGIC; 
  signal Result_10_1 : STD_LOGIC; 
  signal Result_11_1 : STD_LOGIC; 
  signal Result_12_1 : STD_LOGIC; 
  signal Result_13_1 : STD_LOGIC; 
  signal Result_14_1 : STD_LOGIC; 
  signal Result_15_1 : STD_LOGIC; 
  signal Result_16_1 : STD_LOGIC; 
  signal Result_17_1 : STD_LOGIC; 
  signal Result_18_1 : STD_LOGIC; 
  signal Result_19_1 : STD_LOGIC; 
  signal Result_1_1 : STD_LOGIC; 
  signal Result_20_1 : STD_LOGIC; 
  signal Result_21_1 : STD_LOGIC; 
  signal Result_22_1 : STD_LOGIC; 
  signal Result_23_1 : STD_LOGIC; 
  signal Result_24_1 : STD_LOGIC; 
  signal Result_2_1 : STD_LOGIC; 
  signal Result_3_1 : STD_LOGIC; 
  signal Result_4_1 : STD_LOGIC; 
  signal Result_5_1 : STD_LOGIC; 
  signal Result_6_1 : STD_LOGIC; 
  signal Result_7_1 : STD_LOGIC; 
  signal Result_8_1 : STD_LOGIC; 
  signal Result_9_1 : STD_LOGIC; 
  signal block_mode_not0001 : STD_LOGIC; 
  signal block_mode_or0000_1241 : STD_LOGIC; 
  signal block_rd_and0000 : STD_LOGIC; 
  signal cnt1_eq_1300 : STD_LOGIC; 
  signal cnt1_eq_and0000_1317 : STD_LOGIC; 
  signal cnt1_eq_cmp_eq0000 : STD_LOGIC; 
  signal cnt1_or0000 : STD_LOGIC; 
  signal cnt1_z_1320 : STD_LOGIC; 
  signal data_en_1321 : STD_LOGIC; 
  signal data_en_mux0001 : STD_LOGIC; 
  signal data_ex0_0_mux0000 : STD_LOGIC; 
  signal data_ex0_0_not0001 : STD_LOGIC; 
  signal data_ex0_10_mux0000 : STD_LOGIC; 
  signal data_ex0_11_mux0000 : STD_LOGIC; 
  signal data_ex0_12_mux0000 : STD_LOGIC; 
  signal data_ex0_13_mux0000 : STD_LOGIC; 
  signal data_ex0_14_mux0000 : STD_LOGIC; 
  signal data_ex0_15_mux0000 : STD_LOGIC; 
  signal data_ex0_16_mux0000 : STD_LOGIC; 
  signal data_ex0_17_mux0000 : STD_LOGIC; 
  signal data_ex0_18_mux0000 : STD_LOGIC; 
  signal data_ex0_19_mux0000 : STD_LOGIC; 
  signal data_ex0_1_mux0000 : STD_LOGIC; 
  signal data_ex0_20_mux0000 : STD_LOGIC; 
  signal data_ex0_21_mux0000 : STD_LOGIC; 
  signal data_ex0_22_mux0000 : STD_LOGIC; 
  signal data_ex0_23_mux0000 : STD_LOGIC; 
  signal data_ex0_24_mux0000 : STD_LOGIC; 
  signal data_ex0_25_mux0000 : STD_LOGIC; 
  signal data_ex0_26_mux0000 : STD_LOGIC; 
  signal data_ex0_27_mux0000 : STD_LOGIC; 
  signal data_ex0_28_mux0000 : STD_LOGIC; 
  signal data_ex0_29_mux0000 : STD_LOGIC; 
  signal data_ex0_2_mux0000 : STD_LOGIC; 
  signal data_ex0_30_mux0000 : STD_LOGIC; 
  signal data_ex0_31_mux0000 : STD_LOGIC; 
  signal data_ex0_32_mux0000 : STD_LOGIC; 
  signal data_ex0_33_mux0000 : STD_LOGIC; 
  signal data_ex0_34_mux0000 : STD_LOGIC; 
  signal data_ex0_35_mux0000 : STD_LOGIC; 
  signal data_ex0_36_mux0000 : STD_LOGIC; 
  signal data_ex0_37_mux0000 : STD_LOGIC; 
  signal data_ex0_38_mux0000 : STD_LOGIC; 
  signal data_ex0_39_mux0000 : STD_LOGIC; 
  signal data_ex0_3_mux0000 : STD_LOGIC; 
  signal data_ex0_40_mux0000 : STD_LOGIC; 
  signal data_ex0_41_mux0000 : STD_LOGIC; 
  signal data_ex0_42_mux0000 : STD_LOGIC; 
  signal data_ex0_43_mux0000 : STD_LOGIC; 
  signal data_ex0_44_mux0000 : STD_LOGIC; 
  signal data_ex0_45_mux0000 : STD_LOGIC; 
  signal data_ex0_46_mux0000 : STD_LOGIC; 
  signal data_ex0_47_mux0000 : STD_LOGIC; 
  signal data_ex0_48_mux0000 : STD_LOGIC; 
  signal data_ex0_49_mux0000 : STD_LOGIC; 
  signal data_ex0_4_mux0000 : STD_LOGIC; 
  signal data_ex0_50_mux0000 : STD_LOGIC; 
  signal data_ex0_51_mux0000 : STD_LOGIC; 
  signal data_ex0_52_mux0000 : STD_LOGIC; 
  signal data_ex0_53_mux0000 : STD_LOGIC; 
  signal data_ex0_54_mux0000 : STD_LOGIC; 
  signal data_ex0_55_mux0000 : STD_LOGIC; 
  signal data_ex0_56_mux0000 : STD_LOGIC; 
  signal data_ex0_57_mux0000 : STD_LOGIC; 
  signal data_ex0_58_mux0000 : STD_LOGIC; 
  signal data_ex0_59_mux0000 : STD_LOGIC; 
  signal data_ex0_5_mux0000 : STD_LOGIC; 
  signal data_ex0_60_mux0000 : STD_LOGIC; 
  signal data_ex0_61_mux0000 : STD_LOGIC; 
  signal data_ex0_62_mux0000 : STD_LOGIC; 
  signal data_ex0_63_mux0000 : STD_LOGIC; 
  signal data_ex0_6_mux0000 : STD_LOGIC; 
  signal data_ex0_7_mux0000 : STD_LOGIC; 
  signal data_ex0_8_mux0000 : STD_LOGIC; 
  signal data_ex0_9_mux0000 : STD_LOGIC; 
  signal data_ex1_0_mux0000 : STD_LOGIC; 
  signal data_ex1_10_mux0000 : STD_LOGIC; 
  signal data_ex1_11_mux0000 : STD_LOGIC; 
  signal data_ex1_12_mux0000 : STD_LOGIC; 
  signal data_ex1_13_mux0000 : STD_LOGIC; 
  signal data_ex1_14_mux0000 : STD_LOGIC; 
  signal data_ex1_15_mux0000 : STD_LOGIC; 
  signal data_ex1_16_mux0000 : STD_LOGIC; 
  signal data_ex1_17_mux0000 : STD_LOGIC; 
  signal data_ex1_18_mux0000 : STD_LOGIC; 
  signal data_ex1_19_mux0000 : STD_LOGIC; 
  signal data_ex1_1_mux0000 : STD_LOGIC; 
  signal data_ex1_20_mux0000 : STD_LOGIC; 
  signal data_ex1_21_mux0000 : STD_LOGIC; 
  signal data_ex1_22_mux0000 : STD_LOGIC; 
  signal data_ex1_23_mux0000 : STD_LOGIC; 
  signal data_ex1_24_mux0000 : STD_LOGIC; 
  signal data_ex1_25_mux0000 : STD_LOGIC; 
  signal data_ex1_26_mux0000 : STD_LOGIC; 
  signal data_ex1_27_mux0000 : STD_LOGIC; 
  signal data_ex1_28_mux0000 : STD_LOGIC; 
  signal data_ex1_29_mux0000 : STD_LOGIC; 
  signal data_ex1_2_mux0000 : STD_LOGIC; 
  signal data_ex1_30_mux0000 : STD_LOGIC; 
  signal data_ex1_31_mux0000 : STD_LOGIC; 
  signal data_ex1_32_mux0000 : STD_LOGIC; 
  signal data_ex1_33_mux0000 : STD_LOGIC; 
  signal data_ex1_34_mux0000 : STD_LOGIC; 
  signal data_ex1_35_mux0000 : STD_LOGIC; 
  signal data_ex1_36_mux0000 : STD_LOGIC; 
  signal data_ex1_36_not0001_1513 : STD_LOGIC; 
  signal data_ex1_37_mux0000 : STD_LOGIC; 
  signal data_ex1_38_mux0000 : STD_LOGIC; 
  signal data_ex1_39_mux0000 : STD_LOGIC; 
  signal data_ex1_3_mux0000 : STD_LOGIC; 
  signal data_ex1_40_mux0000 : STD_LOGIC; 
  signal data_ex1_41_mux0000 : STD_LOGIC; 
  signal data_ex1_42_mux0000 : STD_LOGIC; 
  signal data_ex1_43_mux0000 : STD_LOGIC; 
  signal data_ex1_44_mux0000 : STD_LOGIC; 
  signal data_ex1_45_mux0000 : STD_LOGIC; 
  signal data_ex1_46_mux0000 : STD_LOGIC; 
  signal data_ex1_47_mux0000 : STD_LOGIC; 
  signal data_ex1_48_mux0000 : STD_LOGIC; 
  signal data_ex1_49_mux0000 : STD_LOGIC; 
  signal data_ex1_4_mux0000 : STD_LOGIC; 
  signal data_ex1_50_mux0000 : STD_LOGIC; 
  signal data_ex1_51_mux0000 : STD_LOGIC; 
  signal data_ex1_52_mux0000 : STD_LOGIC; 
  signal data_ex1_53_mux0000 : STD_LOGIC; 
  signal data_ex1_54_mux0000 : STD_LOGIC; 
  signal data_ex1_55_mux0000 : STD_LOGIC; 
  signal data_ex1_56_mux0000 : STD_LOGIC; 
  signal data_ex1_57_mux0000 : STD_LOGIC; 
  signal data_ex1_58_mux0000 : STD_LOGIC; 
  signal data_ex1_59_mux0000 : STD_LOGIC; 
  signal data_ex1_5_mux0000 : STD_LOGIC; 
  signal data_ex1_60_mux0000 : STD_LOGIC; 
  signal data_ex1_61_mux0000 : STD_LOGIC; 
  signal data_ex1_62_mux0000 : STD_LOGIC; 
  signal data_ex1_63_mux0000 : STD_LOGIC; 
  signal data_ex1_6_mux0000 : STD_LOGIC; 
  signal data_ex1_7_mux0000 : STD_LOGIC; 
  signal data_ex1_8_mux0000 : STD_LOGIC; 
  signal data_ex1_9_mux0000 : STD_LOGIC; 
  signal data_ex2_0_mux0000 : STD_LOGIC; 
  signal data_ex2_0_not0001 : STD_LOGIC; 
  signal data_ex2_10_mux0000 : STD_LOGIC; 
  signal data_ex2_11_mux0000 : STD_LOGIC; 
  signal data_ex2_12_mux0000 : STD_LOGIC; 
  signal data_ex2_13_mux0000 : STD_LOGIC; 
  signal data_ex2_14_mux0000 : STD_LOGIC; 
  signal data_ex2_15_mux0000 : STD_LOGIC; 
  signal data_ex2_16_mux0000 : STD_LOGIC; 
  signal data_ex2_17_mux0000 : STD_LOGIC; 
  signal data_ex2_18_mux0000 : STD_LOGIC; 
  signal data_ex2_19_mux0000 : STD_LOGIC; 
  signal data_ex2_1_mux0000 : STD_LOGIC; 
  signal data_ex2_20_mux0000 : STD_LOGIC; 
  signal data_ex2_21_mux0000 : STD_LOGIC; 
  signal data_ex2_22_mux0000 : STD_LOGIC; 
  signal data_ex2_23_mux0000 : STD_LOGIC; 
  signal data_ex2_24_mux0000 : STD_LOGIC; 
  signal data_ex2_25_mux0000 : STD_LOGIC; 
  signal data_ex2_26_mux0000 : STD_LOGIC; 
  signal data_ex2_27_mux0000 : STD_LOGIC; 
  signal data_ex2_28_mux0000 : STD_LOGIC; 
  signal data_ex2_29_mux0000 : STD_LOGIC; 
  signal data_ex2_2_mux0000 : STD_LOGIC; 
  signal data_ex2_30_mux0000 : STD_LOGIC; 
  signal data_ex2_31_mux0000 : STD_LOGIC; 
  signal data_ex2_32_mux0000 : STD_LOGIC; 
  signal data_ex2_33_mux0000 : STD_LOGIC; 
  signal data_ex2_34_mux0000 : STD_LOGIC; 
  signal data_ex2_35_mux0000 : STD_LOGIC; 
  signal data_ex2_36_mux0000 : STD_LOGIC; 
  signal data_ex2_37_mux0000 : STD_LOGIC; 
  signal data_ex2_38_mux0000 : STD_LOGIC; 
  signal data_ex2_39_mux0000 : STD_LOGIC; 
  signal data_ex2_3_mux0000 : STD_LOGIC; 
  signal data_ex2_40_mux0000 : STD_LOGIC; 
  signal data_ex2_41_mux0000 : STD_LOGIC; 
  signal data_ex2_42_mux0000 : STD_LOGIC; 
  signal data_ex2_43_mux0000 : STD_LOGIC; 
  signal data_ex2_44_mux0000 : STD_LOGIC; 
  signal data_ex2_45_mux0000 : STD_LOGIC; 
  signal data_ex2_46_mux0000 : STD_LOGIC; 
  signal data_ex2_47_mux0000 : STD_LOGIC; 
  signal data_ex2_48_mux0000 : STD_LOGIC; 
  signal data_ex2_49_mux0000 : STD_LOGIC; 
  signal data_ex2_4_mux0000 : STD_LOGIC; 
  signal data_ex2_50_mux0000 : STD_LOGIC; 
  signal data_ex2_51_mux0000 : STD_LOGIC; 
  signal data_ex2_52_mux0000 : STD_LOGIC; 
  signal data_ex2_53_mux0000 : STD_LOGIC; 
  signal data_ex2_54_mux0000 : STD_LOGIC; 
  signal data_ex2_55_mux0000 : STD_LOGIC; 
  signal data_ex2_56_mux0000 : STD_LOGIC; 
  signal data_ex2_57_mux0000 : STD_LOGIC; 
  signal data_ex2_58_mux0000 : STD_LOGIC; 
  signal data_ex2_59_mux0000 : STD_LOGIC; 
  signal data_ex2_5_mux0000 : STD_LOGIC; 
  signal data_ex2_60_mux0000 : STD_LOGIC; 
  signal data_ex2_61_mux0000 : STD_LOGIC; 
  signal data_ex2_62_mux0000 : STD_LOGIC; 
  signal data_ex2_63_mux0000 : STD_LOGIC; 
  signal data_ex2_6_mux0000 : STD_LOGIC; 
  signal data_ex2_7_mux0000 : STD_LOGIC; 
  signal data_ex2_8_mux0000 : STD_LOGIC; 
  signal data_ex2_9_mux0000 : STD_LOGIC; 
  signal data_ex3_and0000 : STD_LOGIC; 
  signal data_ex3_not0001 : STD_LOGIC; 
  signal data_ex4_10_not0001 : STD_LOGIC; 
  signal data_ex4_32_not0001 : STD_LOGIC; 
  signal data_ex4_32_not000123_1901 : STD_LOGIC; 
  signal data_ex4_32_not000137_1902 : STD_LOGIC; 
  signal data_ex4_32_not000148_1903 : STD_LOGIC; 
  signal data_ex4_32_not00016_1904 : STD_LOGIC; 
  signal data_ex4_32_not000170_1905 : STD_LOGIC; 
  signal data_ex4_32_not000181_1906 : STD_LOGIC; 
  signal data_ex5_0_xor0000 : STD_LOGIC; 
  signal data_ex5_10_not0001 : STD_LOGIC; 
  signal data_expect_0_mux0000 : STD_LOGIC; 
  signal data_expect_0_mux000031_2044 : STD_LOGIC; 
  signal data_expect_10_mux0000 : STD_LOGIC; 
  signal data_expect_10_mux000099_2048 : STD_LOGIC; 
  signal data_expect_11_mux0000 : STD_LOGIC; 
  signal data_expect_11_mux000099_2051 : STD_LOGIC; 
  signal data_expect_12_mux0000 : STD_LOGIC; 
  signal data_expect_12_mux000099_2054 : STD_LOGIC; 
  signal data_expect_13_mux0000 : STD_LOGIC; 
  signal data_expect_13_mux000099_2057 : STD_LOGIC; 
  signal data_expect_14_mux0000 : STD_LOGIC; 
  signal data_expect_14_mux000099_2060 : STD_LOGIC; 
  signal data_expect_15_mux0000 : STD_LOGIC; 
  signal data_expect_15_mux000099_2063 : STD_LOGIC; 
  signal data_expect_16_mux0000 : STD_LOGIC; 
  signal data_expect_16_mux000031_2066 : STD_LOGIC; 
  signal data_expect_17_mux0000 : STD_LOGIC; 
  signal data_expect_17_mux000099_2069 : STD_LOGIC; 
  signal data_expect_18_mux0000 : STD_LOGIC; 
  signal data_expect_18_mux000031_2072 : STD_LOGIC; 
  signal data_expect_19_mux0000 : STD_LOGIC; 
  signal data_expect_19_mux000099_2075 : STD_LOGIC; 
  signal data_expect_1_mux0000 : STD_LOGIC; 
  signal data_expect_1_mux000031_2077 : STD_LOGIC; 
  signal data_expect_20_mux0000 : STD_LOGIC; 
  signal data_expect_20_mux000099_2081 : STD_LOGIC; 
  signal data_expect_21_mux0000 : STD_LOGIC; 
  signal data_expect_21_mux000031_2084 : STD_LOGIC; 
  signal data_expect_22_mux0000 : STD_LOGIC; 
  signal data_expect_22_mux000099_2087 : STD_LOGIC; 
  signal data_expect_23_mux0000 : STD_LOGIC; 
  signal data_expect_23_mux000031_2090 : STD_LOGIC; 
  signal data_expect_24_mux0000 : STD_LOGIC; 
  signal data_expect_24_mux000031_2093 : STD_LOGIC; 
  signal data_expect_25_mux0000 : STD_LOGIC; 
  signal data_expect_25_mux000099_2096 : STD_LOGIC; 
  signal data_expect_26_mux0000 : STD_LOGIC; 
  signal data_expect_26_mux000031_2099 : STD_LOGIC; 
  signal data_expect_27_mux0000 : STD_LOGIC; 
  signal data_expect_27_mux000099_2102 : STD_LOGIC; 
  signal data_expect_28_mux0000 : STD_LOGIC; 
  signal data_expect_28_mux000099_2105 : STD_LOGIC; 
  signal data_expect_29_mux0000 : STD_LOGIC; 
  signal data_expect_29_mux000031_2108 : STD_LOGIC; 
  signal data_expect_2_mux0000 : STD_LOGIC; 
  signal data_expect_2_mux000099_2110 : STD_LOGIC; 
  signal data_expect_30_mux0000 : STD_LOGIC; 
  signal data_expect_30_mux000099_2114 : STD_LOGIC; 
  signal data_expect_31_mux0000 : STD_LOGIC; 
  signal data_expect_31_mux000031_2117 : STD_LOGIC; 
  signal data_expect_32_mux0000 : STD_LOGIC; 
  signal data_expect_32_mux0000114_2120 : STD_LOGIC; 
  signal data_expect_32_mux000099_2121 : STD_LOGIC; 
  signal data_expect_33_mux0000 : STD_LOGIC; 
  signal data_expect_33_mux0000114_2124 : STD_LOGIC; 
  signal data_expect_33_mux000099_2125 : STD_LOGIC; 
  signal data_expect_34_mux0000 : STD_LOGIC; 
  signal data_expect_34_mux0000114_2128 : STD_LOGIC; 
  signal data_expect_34_mux000099_2129 : STD_LOGIC; 
  signal data_expect_35_mux0000 : STD_LOGIC; 
  signal data_expect_35_mux0000114_2132 : STD_LOGIC; 
  signal data_expect_35_mux000099_2133 : STD_LOGIC; 
  signal data_expect_36_mux0000 : STD_LOGIC; 
  signal data_expect_36_mux0000114_2136 : STD_LOGIC; 
  signal data_expect_36_mux000099_2137 : STD_LOGIC; 
  signal data_expect_37_mux0000 : STD_LOGIC; 
  signal data_expect_37_mux0000114_2140 : STD_LOGIC; 
  signal data_expect_37_mux000099_2141 : STD_LOGIC; 
  signal data_expect_38_mux0000 : STD_LOGIC; 
  signal data_expect_38_mux0000114_2144 : STD_LOGIC; 
  signal data_expect_38_mux000099_2145 : STD_LOGIC; 
  signal data_expect_39_mux0000 : STD_LOGIC; 
  signal data_expect_39_mux0000114_2148 : STD_LOGIC; 
  signal data_expect_39_mux000099_2149 : STD_LOGIC; 
  signal data_expect_3_cmp_eq0006 : STD_LOGIC; 
  signal data_expect_3_cmp_eq00068126_2151 : STD_LOGIC; 
  signal data_expect_3_mux0000 : STD_LOGIC; 
  signal data_expect_3_mux000099_2153 : STD_LOGIC; 
  signal data_expect_3_not0001 : STD_LOGIC; 
  signal data_expect_40_mux0000 : STD_LOGIC; 
  signal data_expect_40_mux0000114_2158 : STD_LOGIC; 
  signal data_expect_40_mux000099_2159 : STD_LOGIC; 
  signal data_expect_41_mux0000 : STD_LOGIC; 
  signal data_expect_41_mux0000114_2162 : STD_LOGIC; 
  signal data_expect_41_mux000099_2163 : STD_LOGIC; 
  signal data_expect_42_mux0000 : STD_LOGIC; 
  signal data_expect_42_mux0000114_2166 : STD_LOGIC; 
  signal data_expect_42_mux000099_2167 : STD_LOGIC; 
  signal data_expect_43_mux0000 : STD_LOGIC; 
  signal data_expect_43_mux0000114_2170 : STD_LOGIC; 
  signal data_expect_43_mux000099_2171 : STD_LOGIC; 
  signal data_expect_44_mux0000 : STD_LOGIC; 
  signal data_expect_44_mux0000114_2174 : STD_LOGIC; 
  signal data_expect_44_mux000099_2175 : STD_LOGIC; 
  signal data_expect_45_mux0000 : STD_LOGIC; 
  signal data_expect_45_mux0000114_2178 : STD_LOGIC; 
  signal data_expect_45_mux000099_2179 : STD_LOGIC; 
  signal data_expect_46_mux0000 : STD_LOGIC; 
  signal data_expect_46_mux0000114_2182 : STD_LOGIC; 
  signal data_expect_46_mux000099_2183 : STD_LOGIC; 
  signal data_expect_47_mux0000 : STD_LOGIC; 
  signal data_expect_47_mux0000114_2186 : STD_LOGIC; 
  signal data_expect_47_mux000099_2187 : STD_LOGIC; 
  signal data_expect_48_mux0000 : STD_LOGIC; 
  signal data_expect_48_mux0000114_2190 : STD_LOGIC; 
  signal data_expect_48_mux000099_2191 : STD_LOGIC; 
  signal data_expect_49_mux0000 : STD_LOGIC; 
  signal data_expect_49_mux0000114_2194 : STD_LOGIC; 
  signal data_expect_49_mux000099_2195 : STD_LOGIC; 
  signal data_expect_4_mux0000 : STD_LOGIC; 
  signal data_expect_4_mux000099_2197 : STD_LOGIC; 
  signal data_expect_50_mux0000 : STD_LOGIC; 
  signal data_expect_50_mux0000114_2201 : STD_LOGIC; 
  signal data_expect_50_mux000099_2202 : STD_LOGIC; 
  signal data_expect_51_mux0000 : STD_LOGIC; 
  signal data_expect_51_mux0000114_2205 : STD_LOGIC; 
  signal data_expect_51_mux000099_2206 : STD_LOGIC; 
  signal data_expect_52_mux0000 : STD_LOGIC; 
  signal data_expect_52_mux0000114_2209 : STD_LOGIC; 
  signal data_expect_52_mux000099_2210 : STD_LOGIC; 
  signal data_expect_53_mux0000 : STD_LOGIC; 
  signal data_expect_53_mux0000114_2213 : STD_LOGIC; 
  signal data_expect_53_mux000099_2214 : STD_LOGIC; 
  signal data_expect_54_mux0000 : STD_LOGIC; 
  signal data_expect_54_mux0000114_2217 : STD_LOGIC; 
  signal data_expect_54_mux000099_2218 : STD_LOGIC; 
  signal data_expect_55_mux0000 : STD_LOGIC; 
  signal data_expect_55_mux0000114_2221 : STD_LOGIC; 
  signal data_expect_55_mux000099_2222 : STD_LOGIC; 
  signal data_expect_56_mux0000 : STD_LOGIC; 
  signal data_expect_56_mux0000114_2225 : STD_LOGIC; 
  signal data_expect_56_mux000099_2226 : STD_LOGIC; 
  signal data_expect_57_mux0000 : STD_LOGIC; 
  signal data_expect_57_mux0000114_2229 : STD_LOGIC; 
  signal data_expect_57_mux000099_2230 : STD_LOGIC; 
  signal data_expect_58_mux0000 : STD_LOGIC; 
  signal data_expect_58_mux0000114_2233 : STD_LOGIC; 
  signal data_expect_58_mux000099_2234 : STD_LOGIC; 
  signal data_expect_59_mux0000 : STD_LOGIC; 
  signal data_expect_59_mux0000114_2237 : STD_LOGIC; 
  signal data_expect_59_mux000099_2238 : STD_LOGIC; 
  signal data_expect_5_mux0000 : STD_LOGIC; 
  signal data_expect_5_mux000031_2240 : STD_LOGIC; 
  signal data_expect_60_mux0000 : STD_LOGIC; 
  signal data_expect_60_mux0000114_2244 : STD_LOGIC; 
  signal data_expect_60_mux000099_2245 : STD_LOGIC; 
  signal data_expect_61_mux0000 : STD_LOGIC; 
  signal data_expect_61_mux0000114_2248 : STD_LOGIC; 
  signal data_expect_61_mux000099_2249 : STD_LOGIC; 
  signal data_expect_62_mux0000 : STD_LOGIC; 
  signal data_expect_62_mux0000114_2252 : STD_LOGIC; 
  signal data_expect_62_mux000099_2253 : STD_LOGIC; 
  signal data_expect_63_mux0000 : STD_LOGIC; 
  signal data_expect_63_mux0000114_2256 : STD_LOGIC; 
  signal data_expect_63_mux000099_2257 : STD_LOGIC; 
  signal data_expect_6_mux0000 : STD_LOGIC; 
  signal data_expect_6_mux000099_2259 : STD_LOGIC; 
  signal data_expect_7_mux0000 : STD_LOGIC; 
  signal data_expect_7_mux000099_2262 : STD_LOGIC; 
  signal data_expect_8_mux0000 : STD_LOGIC; 
  signal data_expect_8_mux000031_2265 : STD_LOGIC; 
  signal data_expect_9_mux0000 : STD_LOGIC; 
  signal data_expect_9_mux000099_2268 : STD_LOGIC; 
  signal di_rdy_2272 : STD_LOGIC; 
  signal di_rdy_or0000_inv : STD_LOGIC; 
  signal rst_inv : STD_LOGIC; 
  signal stp_FSM_FFd1_2277 : STD_LOGIC; 
  signal stp_FSM_FFd1_In : STD_LOGIC; 
  signal stp_FSM_FFd2_2279 : STD_LOGIC; 
  signal stp_FSM_FFd2_In : STD_LOGIC; 
  signal stp_FSM_FFd3_2281 : STD_LOGIC; 
  signal stp_FSM_FFd3_In_2282 : STD_LOGIC; 
  signal stp_FSM_FFd4_2283 : STD_LOGIC; 
  signal stp_FSM_FFd4_In : STD_LOGIC; 
  signal xcnt1_or0000 : STD_LOGIC; 
  signal xcnt1_z : STD_LOGIC; 
  signal xcnt1_z_cmp_eq000070_2360 : STD_LOGIC; 
  signal xcnt2_or0000 : STD_LOGIC; 
  signal xcnt2_z : STD_LOGIC; 
  signal xcnt2_z_cmp_eq000034_2379 : STD_LOGIC; 
  signal xcnt2_z_cmp_eq000070_2380 : STD_LOGIC; 
  signal Madd_data_ex4_31_0_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Madd_data_ex4_31_0_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Madd_data_ex4_63_32_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Madd_data_ex4_63_32_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_cnt1_eq_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal Mcompar_cnt1_eq_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Mcount_block_rd_cy : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal Mcount_block_rd_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_cnt1_cy : STD_LOGIC_VECTOR ( 23 downto 0 ); 
  signal Mcount_cnt1_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcount_xcnt1_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Mcount_xcnt1_lut : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Mcount_xcnt2_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Mcount_xcnt2_lut : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Msub_cnt1_eq_addsub0000_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Msub_cnt1_eq_addsub0000_lut : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal Result : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal block_mode : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal NlwRenamedSig_OI_block_rd : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal cnt1 : STD_LOGIC_VECTOR ( 24 downto 0 ); 
  signal cnt1_eq_addsub0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal data_ex0 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex1 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex2 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex3 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex3_mux0000 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex4 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal data_ex4_31_0_add0000 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal data_ex4_63_32_add0000 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal data_ex5 : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal NlwRenamedSig_OI_data_expect : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal xcnt1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal xcnt2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  di_data(63) <= NlwRenamedSig_OI_data_expect(63);
  di_data(62) <= NlwRenamedSig_OI_data_expect(62);
  di_data(61) <= NlwRenamedSig_OI_data_expect(61);
  di_data(60) <= NlwRenamedSig_OI_data_expect(60);
  di_data(59) <= NlwRenamedSig_OI_data_expect(59);
  di_data(58) <= NlwRenamedSig_OI_data_expect(58);
  di_data(57) <= NlwRenamedSig_OI_data_expect(57);
  di_data(56) <= NlwRenamedSig_OI_data_expect(56);
  di_data(55) <= NlwRenamedSig_OI_data_expect(55);
  di_data(54) <= NlwRenamedSig_OI_data_expect(54);
  di_data(53) <= NlwRenamedSig_OI_data_expect(53);
  di_data(52) <= NlwRenamedSig_OI_data_expect(52);
  di_data(51) <= NlwRenamedSig_OI_data_expect(51);
  di_data(50) <= NlwRenamedSig_OI_data_expect(50);
  di_data(49) <= NlwRenamedSig_OI_data_expect(49);
  di_data(48) <= NlwRenamedSig_OI_data_expect(48);
  di_data(47) <= NlwRenamedSig_OI_data_expect(47);
  di_data(46) <= NlwRenamedSig_OI_data_expect(46);
  di_data(45) <= NlwRenamedSig_OI_data_expect(45);
  di_data(44) <= NlwRenamedSig_OI_data_expect(44);
  di_data(43) <= NlwRenamedSig_OI_data_expect(43);
  di_data(42) <= NlwRenamedSig_OI_data_expect(42);
  di_data(41) <= NlwRenamedSig_OI_data_expect(41);
  di_data(40) <= NlwRenamedSig_OI_data_expect(40);
  di_data(39) <= NlwRenamedSig_OI_data_expect(39);
  di_data(38) <= NlwRenamedSig_OI_data_expect(38);
  di_data(37) <= NlwRenamedSig_OI_data_expect(37);
  di_data(36) <= NlwRenamedSig_OI_data_expect(36);
  di_data(35) <= NlwRenamedSig_OI_data_expect(35);
  di_data(34) <= NlwRenamedSig_OI_data_expect(34);
  di_data(33) <= NlwRenamedSig_OI_data_expect(33);
  di_data(32) <= NlwRenamedSig_OI_data_expect(32);
  di_data(31) <= NlwRenamedSig_OI_data_expect(31);
  di_data(30) <= NlwRenamedSig_OI_data_expect(30);
  di_data(29) <= NlwRenamedSig_OI_data_expect(29);
  di_data(28) <= NlwRenamedSig_OI_data_expect(28);
  di_data(27) <= NlwRenamedSig_OI_data_expect(27);
  di_data(26) <= NlwRenamedSig_OI_data_expect(26);
  di_data(25) <= NlwRenamedSig_OI_data_expect(25);
  di_data(24) <= NlwRenamedSig_OI_data_expect(24);
  di_data(23) <= NlwRenamedSig_OI_data_expect(23);
  di_data(22) <= NlwRenamedSig_OI_data_expect(22);
  di_data(21) <= NlwRenamedSig_OI_data_expect(21);
  di_data(20) <= NlwRenamedSig_OI_data_expect(20);
  di_data(19) <= NlwRenamedSig_OI_data_expect(19);
  di_data(18) <= NlwRenamedSig_OI_data_expect(18);
  di_data(17) <= NlwRenamedSig_OI_data_expect(17);
  di_data(16) <= NlwRenamedSig_OI_data_expect(16);
  di_data(15) <= NlwRenamedSig_OI_data_expect(15);
  di_data(14) <= NlwRenamedSig_OI_data_expect(14);
  di_data(13) <= NlwRenamedSig_OI_data_expect(13);
  di_data(12) <= NlwRenamedSig_OI_data_expect(12);
  di_data(11) <= NlwRenamedSig_OI_data_expect(11);
  di_data(10) <= NlwRenamedSig_OI_data_expect(10);
  di_data(9) <= NlwRenamedSig_OI_data_expect(9);
  di_data(8) <= NlwRenamedSig_OI_data_expect(8);
  di_data(7) <= NlwRenamedSig_OI_data_expect(7);
  di_data(6) <= NlwRenamedSig_OI_data_expect(6);
  di_data(5) <= NlwRenamedSig_OI_data_expect(5);
  di_data(4) <= NlwRenamedSig_OI_data_expect(4);
  di_data(3) <= NlwRenamedSig_OI_data_expect(3);
  di_data(2) <= NlwRenamedSig_OI_data_expect(2);
  di_data(1) <= NlwRenamedSig_OI_data_expect(1);
  di_data(0) <= NlwRenamedSig_OI_data_expect(0);
  test_gen_bl_wr(31) <= NlwRenamedSig_OI_block_rd(31);
  test_gen_bl_wr(30) <= NlwRenamedSig_OI_block_rd(30);
  test_gen_bl_wr(29) <= NlwRenamedSig_OI_block_rd(29);
  test_gen_bl_wr(28) <= NlwRenamedSig_OI_block_rd(28);
  test_gen_bl_wr(27) <= NlwRenamedSig_OI_block_rd(27);
  test_gen_bl_wr(26) <= NlwRenamedSig_OI_block_rd(26);
  test_gen_bl_wr(25) <= NlwRenamedSig_OI_block_rd(25);
  test_gen_bl_wr(24) <= NlwRenamedSig_OI_block_rd(24);
  test_gen_bl_wr(23) <= NlwRenamedSig_OI_block_rd(23);
  test_gen_bl_wr(22) <= NlwRenamedSig_OI_block_rd(22);
  test_gen_bl_wr(21) <= NlwRenamedSig_OI_block_rd(21);
  test_gen_bl_wr(20) <= NlwRenamedSig_OI_block_rd(20);
  test_gen_bl_wr(19) <= NlwRenamedSig_OI_block_rd(19);
  test_gen_bl_wr(18) <= NlwRenamedSig_OI_block_rd(18);
  test_gen_bl_wr(17) <= NlwRenamedSig_OI_block_rd(17);
  test_gen_bl_wr(16) <= NlwRenamedSig_OI_block_rd(16);
  test_gen_bl_wr(15) <= NlwRenamedSig_OI_block_rd(15);
  test_gen_bl_wr(14) <= NlwRenamedSig_OI_block_rd(14);
  test_gen_bl_wr(13) <= NlwRenamedSig_OI_block_rd(13);
  test_gen_bl_wr(12) <= NlwRenamedSig_OI_block_rd(12);
  test_gen_bl_wr(11) <= NlwRenamedSig_OI_block_rd(11);
  test_gen_bl_wr(10) <= NlwRenamedSig_OI_block_rd(10);
  test_gen_bl_wr(9) <= NlwRenamedSig_OI_block_rd(9);
  test_gen_bl_wr(8) <= NlwRenamedSig_OI_block_rd(8);
  test_gen_bl_wr(7) <= NlwRenamedSig_OI_block_rd(7);
  test_gen_bl_wr(6) <= NlwRenamedSig_OI_block_rd(6);
  test_gen_bl_wr(5) <= NlwRenamedSig_OI_block_rd(5);
  test_gen_bl_wr(4) <= NlwRenamedSig_OI_block_rd(4);
  test_gen_bl_wr(3) <= NlwRenamedSig_OI_block_rd(3);
  test_gen_bl_wr(2) <= NlwRenamedSig_OI_block_rd(2);
  test_gen_bl_wr(1) <= NlwRenamedSig_OI_block_rd(1);
  test_gen_bl_wr(0) <= NlwRenamedSig_OI_block_rd(0);
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  data_ex3_0 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(63),
      Q => data_ex3(0)
    );
  data_ex3_1 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(62),
      Q => data_ex3(1)
    );
  data_ex3_2 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(61),
      Q => data_ex3(2)
    );
  data_ex3_3 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(60),
      Q => data_ex3(3)
    );
  data_ex3_4 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(59),
      Q => data_ex3(4)
    );
  data_ex3_5 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(58),
      Q => data_ex3(5)
    );
  data_ex3_6 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(57),
      Q => data_ex3(6)
    );
  data_ex3_7 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(56),
      Q => data_ex3(7)
    );
  data_ex3_8 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(55),
      Q => data_ex3(8)
    );
  data_ex3_9 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(54),
      Q => data_ex3(9)
    );
  data_ex3_10 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(53),
      Q => data_ex3(10)
    );
  data_ex3_11 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(52),
      Q => data_ex3(11)
    );
  data_ex3_12 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(51),
      Q => data_ex3(12)
    );
  data_ex3_13 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(50),
      Q => data_ex3(13)
    );
  data_ex3_14 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(49),
      Q => data_ex3(14)
    );
  data_ex3_15 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(48),
      Q => data_ex3(15)
    );
  data_ex3_16 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(47),
      Q => data_ex3(16)
    );
  data_ex3_17 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(46),
      Q => data_ex3(17)
    );
  data_ex3_18 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(45),
      Q => data_ex3(18)
    );
  data_ex3_19 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(44),
      Q => data_ex3(19)
    );
  data_ex3_20 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(43),
      Q => data_ex3(20)
    );
  data_ex3_21 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(42),
      Q => data_ex3(21)
    );
  data_ex3_22 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(41),
      Q => data_ex3(22)
    );
  data_ex3_23 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(40),
      Q => data_ex3(23)
    );
  data_ex3_24 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(39),
      Q => data_ex3(24)
    );
  data_ex3_25 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(38),
      Q => data_ex3(25)
    );
  data_ex3_26 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(37),
      Q => data_ex3(26)
    );
  data_ex3_27 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(36),
      Q => data_ex3(27)
    );
  data_ex3_28 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(35),
      Q => data_ex3(28)
    );
  data_ex3_29 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(34),
      Q => data_ex3(29)
    );
  data_ex3_30 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(33),
      Q => data_ex3(30)
    );
  data_ex3_31 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(32),
      Q => data_ex3(31)
    );
  data_ex3_32 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(31),
      Q => data_ex3(32)
    );
  data_ex3_33 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(30),
      Q => data_ex3(33)
    );
  data_ex3_34 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(29),
      Q => data_ex3(34)
    );
  data_ex3_35 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(28),
      Q => data_ex3(35)
    );
  data_ex3_36 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(27),
      Q => data_ex3(36)
    );
  data_ex3_37 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(26),
      Q => data_ex3(37)
    );
  data_ex3_38 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(25),
      Q => data_ex3(38)
    );
  data_ex3_39 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(24),
      Q => data_ex3(39)
    );
  data_ex3_40 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(23),
      Q => data_ex3(40)
    );
  data_ex3_41 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(22),
      Q => data_ex3(41)
    );
  data_ex3_42 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(21),
      Q => data_ex3(42)
    );
  data_ex3_43 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(20),
      Q => data_ex3(43)
    );
  data_ex3_44 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(19),
      Q => data_ex3(44)
    );
  data_ex3_45 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(18),
      Q => data_ex3(45)
    );
  data_ex3_46 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(17),
      Q => data_ex3(46)
    );
  data_ex3_47 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(16),
      Q => data_ex3(47)
    );
  data_ex3_48 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(15),
      Q => data_ex3(48)
    );
  data_ex3_49 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(14),
      Q => data_ex3(49)
    );
  data_ex3_50 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(13),
      Q => data_ex3(50)
    );
  data_ex3_51 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(12),
      Q => data_ex3(51)
    );
  data_ex3_52 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(11),
      Q => data_ex3(52)
    );
  data_ex3_53 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(10),
      Q => data_ex3(53)
    );
  data_ex3_54 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(9),
      Q => data_ex3(54)
    );
  data_ex3_55 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(8),
      Q => data_ex3(55)
    );
  data_ex3_56 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(7),
      Q => data_ex3(56)
    );
  data_ex3_57 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(6),
      Q => data_ex3(57)
    );
  data_ex3_58 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(5),
      Q => data_ex3(58)
    );
  data_ex3_59 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(4),
      Q => data_ex3(59)
    );
  data_ex3_60 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(3),
      Q => data_ex3(60)
    );
  data_ex3_61 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(2),
      Q => data_ex3(61)
    );
  data_ex3_62 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(1),
      Q => data_ex3(62)
    );
  data_ex3_63 : FDE
    port map (
      C => di_clk,
      CE => data_ex3_not0001,
      D => data_ex3_mux0000(0),
      Q => data_ex3(63)
    );
  data_expect_3 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_3_mux0000,
      Q => NlwRenamedSig_OI_data_expect(3)
    );
  data_ex1_36 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_36_mux0000,
      Q => data_ex1(36)
    );
  data_expect_42 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_42_mux0000,
      Q => NlwRenamedSig_OI_data_expect(42)
    );
  data_ex1_41 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_41_mux0000,
      Q => data_ex1(41)
    );
  data_expect_37 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_37_mux0000,
      Q => NlwRenamedSig_OI_data_expect(37)
    );
  data_ex1_42 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_42_mux0000,
      Q => data_ex1(42)
    );
  data_expect_4 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_4_mux0000,
      Q => NlwRenamedSig_OI_data_expect(4)
    );
  data_ex1_37 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_37_mux0000,
      Q => data_ex1(37)
    );
  data_expect_38 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_38_mux0000,
      Q => NlwRenamedSig_OI_data_expect(38)
    );
  data_expect_43 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_43_mux0000,
      Q => NlwRenamedSig_OI_data_expect(43)
    );
  data_expect_5 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_5_mux0000,
      Q => NlwRenamedSig_OI_data_expect(5)
    );
  data_ex1_38 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_38_mux0000,
      Q => data_ex1(38)
    );
  data_ex1_43 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_43_mux0000,
      Q => data_ex1(43)
    );
  data_expect_44 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_44_mux0000,
      Q => NlwRenamedSig_OI_data_expect(44)
    );
  data_ex0_0 : FDSE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_0_mux0000,
      S => rst_inv,
      Q => data_ex0(0)
    );
  data_expect_39 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_39_mux0000,
      Q => NlwRenamedSig_OI_data_expect(39)
    );
  data_ex1_44 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_44_mux0000,
      Q => data_ex1(44)
    );
  data_expect_6 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_6_mux0000,
      Q => NlwRenamedSig_OI_data_expect(6)
    );
  data_ex1_39 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_39_mux0000,
      Q => data_ex1(39)
    );
  data_expect_50 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_50_mux0000,
      Q => NlwRenamedSig_OI_data_expect(50)
    );
  data_ex0_1 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_1_mux0000,
      R => rst_inv,
      Q => data_ex0(1)
    );
  data_expect_45 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_45_mux0000,
      Q => NlwRenamedSig_OI_data_expect(45)
    );
  data_expect_7 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_7_mux0000,
      Q => NlwRenamedSig_OI_data_expect(7)
    );
  data_ex1_45 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_45_mux0000,
      Q => data_ex1(45)
    );
  data_ex1_50 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_50_mux0000,
      Q => data_ex1(50)
    );
  data_ex0_2 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_2_mux0000,
      R => rst_inv,
      Q => data_ex0(2)
    );
  data_expect_8 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_8_mux0000,
      Q => NlwRenamedSig_OI_data_expect(8)
    );
  data_expect_46 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_46_mux0000,
      Q => NlwRenamedSig_OI_data_expect(46)
    );
  data_expect_51 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_51_mux0000,
      Q => NlwRenamedSig_OI_data_expect(51)
    );
  data_ex0_3 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_3_mux0000,
      R => rst_inv,
      Q => data_ex0(3)
    );
  data_ex1_46 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_46_mux0000,
      Q => data_ex1(46)
    );
  data_ex1_51 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_51_mux0000,
      Q => data_ex1(51)
    );
  data_expect_9 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_9_mux0000,
      Q => NlwRenamedSig_OI_data_expect(9)
    );
  data_expect_47 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_47_mux0000,
      Q => NlwRenamedSig_OI_data_expect(47)
    );
  data_expect_52 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_52_mux0000,
      Q => NlwRenamedSig_OI_data_expect(52)
    );
  data_ex0_4 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_4_mux0000,
      R => rst_inv,
      Q => data_ex0(4)
    );
  data_ex1_47 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_47_mux0000,
      Q => data_ex1(47)
    );
  data_ex1_52 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_52_mux0000,
      Q => data_ex1(52)
    );
  data_ex1_48 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_48_mux0000,
      Q => data_ex1(48)
    );
  data_expect_48 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_48_mux0000,
      Q => NlwRenamedSig_OI_data_expect(48)
    );
  data_expect_53 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_53_mux0000,
      Q => NlwRenamedSig_OI_data_expect(53)
    );
  data_expect_49 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_49_mux0000,
      Q => NlwRenamedSig_OI_data_expect(49)
    );
  data_ex1_53 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_53_mux0000,
      Q => data_ex1(53)
    );
  data_ex0_5 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_5_mux0000,
      R => rst_inv,
      Q => data_ex0(5)
    );
  data_ex1_54 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_54_mux0000,
      Q => data_ex1(54)
    );
  data_expect_54 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_54_mux0000,
      Q => NlwRenamedSig_OI_data_expect(54)
    );
  data_ex1_49 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_49_mux0000,
      Q => data_ex1(49)
    );
  data_ex0_6 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_6_mux0000,
      R => rst_inv,
      Q => data_ex0(6)
    );
  data_expect_55 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_55_mux0000,
      Q => NlwRenamedSig_OI_data_expect(55)
    );
  data_expect_60 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_60_mux0000,
      Q => NlwRenamedSig_OI_data_expect(60)
    );
  data_ex1_55 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_55_mux0000,
      Q => data_ex1(55)
    );
  data_expect_56 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_56_mux0000,
      Q => NlwRenamedSig_OI_data_expect(56)
    );
  data_ex1_60 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_60_mux0000,
      Q => data_ex1(60)
    );
  data_ex0_7 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_7_mux0000,
      R => rst_inv,
      Q => data_ex0(7)
    );
  data_ex1_61 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_61_mux0000,
      Q => data_ex1(61)
    );
  data_expect_61 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_61_mux0000,
      Q => NlwRenamedSig_OI_data_expect(61)
    );
  data_ex1_56 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_56_mux0000,
      Q => data_ex1(56)
    );
  data_expect_62 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_62_mux0000,
      Q => NlwRenamedSig_OI_data_expect(62)
    );
  data_ex0_8 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_8_mux0000,
      R => rst_inv,
      Q => data_ex0(8)
    );
  data_expect_57 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_57_mux0000,
      Q => NlwRenamedSig_OI_data_expect(57)
    );
  data_ex0_9 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_9_mux0000,
      R => rst_inv,
      Q => data_ex0(9)
    );
  data_ex1_57 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_57_mux0000,
      Q => data_ex1(57)
    );
  data_ex1_62 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_62_mux0000,
      Q => data_ex1(62)
    );
  data_ex1_58 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_58_mux0000,
      Q => data_ex1(58)
    );
  data_expect_58 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_58_mux0000,
      Q => NlwRenamedSig_OI_data_expect(58)
    );
  data_expect_63 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_63_mux0000,
      Q => NlwRenamedSig_OI_data_expect(63)
    );
  data_ex0_10 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_10_mux0000,
      R => rst_inv,
      Q => data_ex0(10)
    );
  data_ex1_63 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_63_mux0000,
      Q => data_ex1(63)
    );
  data_expect_59 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_59_mux0000,
      Q => NlwRenamedSig_OI_data_expect(59)
    );
  data_ex0_12 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_12_mux0000,
      R => rst_inv,
      Q => data_ex0(12)
    );
  data_ex1_59 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_59_mux0000,
      Q => data_ex1(59)
    );
  data_ex0_11 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_11_mux0000,
      R => rst_inv,
      Q => data_ex0(11)
    );
  data_ex0_13 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_13_mux0000,
      R => rst_inv,
      Q => data_ex0(13)
    );
  data_ex0_14 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_14_mux0000,
      R => rst_inv,
      Q => data_ex0(14)
    );
  data_ex0_20 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_20_mux0000,
      R => rst_inv,
      Q => data_ex0(20)
    );
  data_ex0_15 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_15_mux0000,
      R => rst_inv,
      Q => data_ex0(15)
    );
  data_ex0_22 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_22_mux0000,
      R => rst_inv,
      Q => data_ex0(22)
    );
  data_ex0_21 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_21_mux0000,
      R => rst_inv,
      Q => data_ex0(21)
    );
  data_ex0_16 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_16_mux0000,
      R => rst_inv,
      Q => data_ex0(16)
    );
  data_ex0_18 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_18_mux0000,
      R => rst_inv,
      Q => data_ex0(18)
    );
  data_ex0_17 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_17_mux0000,
      R => rst_inv,
      Q => data_ex0(17)
    );
  data_ex0_23 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_23_mux0000,
      R => rst_inv,
      Q => data_ex0(23)
    );
  data_ex0_24 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_24_mux0000,
      R => rst_inv,
      Q => data_ex0(24)
    );
  data_ex0_19 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_19_mux0000,
      R => rst_inv,
      Q => data_ex0(19)
    );
  data_ex5_11 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(10),
      R => rst_inv,
      Q => data_ex5(11)
    );
  data_ex0_25 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_25_mux0000,
      R => rst_inv,
      Q => data_ex0(25)
    );
  data_ex0_30 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_30_mux0000,
      R => rst_inv,
      Q => data_ex0(30)
    );
  data_ex0_31 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_31_mux0000,
      R => rst_inv,
      Q => data_ex0(31)
    );
  data_ex0_26 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_26_mux0000,
      R => rst_inv,
      Q => data_ex0(26)
    );
  data_ex0_32 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_32_mux0000,
      R => rst_inv,
      Q => data_ex0(32)
    );
  data_ex0_27 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_27_mux0000,
      R => rst_inv,
      Q => data_ex0(27)
    );
  data_ex0_28 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_28_mux0000,
      R => rst_inv,
      Q => data_ex0(28)
    );
  data_ex0_33 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_33_mux0000,
      R => rst_inv,
      Q => data_ex0(33)
    );
  data_ex0_34 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_34_mux0000,
      R => rst_inv,
      Q => data_ex0(34)
    );
  data_ex0_29 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_29_mux0000,
      R => rst_inv,
      Q => data_ex0(29)
    );
  data_ex1_0 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_0_mux0000,
      Q => data_ex1(0)
    );
  data_ex0_40 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_40_mux0000,
      R => rst_inv,
      Q => data_ex0(40)
    );
  data_ex0_35 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_35_mux0000,
      R => rst_inv,
      Q => data_ex0(35)
    );
  data_ex1_1 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_1_mux0000,
      Q => data_ex1(1)
    );
  data_ex0_36 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_36_mux0000,
      R => rst_inv,
      Q => data_ex0(36)
    );
  data_ex0_41 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_41_mux0000,
      R => rst_inv,
      Q => data_ex0(41)
    );
  data_ex1_2 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_2_mux0000,
      Q => data_ex1(2)
    );
  data_ex0_37 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_37_mux0000,
      R => rst_inv,
      Q => data_ex0(37)
    );
  data_ex0_42 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_42_mux0000,
      R => rst_inv,
      Q => data_ex0(42)
    );
  data_ex1_3 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_3_mux0000,
      Q => data_ex1(3)
    );
  data_ex0_38 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_38_mux0000,
      R => rst_inv,
      Q => data_ex0(38)
    );
  data_ex0_43 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_43_mux0000,
      R => rst_inv,
      Q => data_ex0(43)
    );
  data_ex1_4 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_4_mux0000,
      Q => data_ex1(4)
    );
  data_ex0_44 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_44_mux0000,
      R => rst_inv,
      Q => data_ex0(44)
    );
  data_ex0_39 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_39_mux0000,
      R => rst_inv,
      Q => data_ex0(39)
    );
  data_ex1_5 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_5_mux0000,
      Q => data_ex1(5)
    );
  data_ex0_45 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_45_mux0000,
      R => rst_inv,
      Q => data_ex0(45)
    );
  data_ex0_50 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_50_mux0000,
      R => rst_inv,
      Q => data_ex0(50)
    );
  data_ex1_6 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_6_mux0000,
      Q => data_ex1(6)
    );
  data_ex1_7 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_7_mux0000,
      Q => data_ex1(7)
    );
  data_ex0_51 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_51_mux0000,
      R => rst_inv,
      Q => data_ex0(51)
    );
  data_ex0_46 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_46_mux0000,
      R => rst_inv,
      Q => data_ex0(46)
    );
  data_ex0_52 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_52_mux0000,
      R => rst_inv,
      Q => data_ex0(52)
    );
  data_ex0_47 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_47_mux0000,
      R => rst_inv,
      Q => data_ex0(47)
    );
  data_ex1_8 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_8_mux0000,
      Q => data_ex1(8)
    );
  data_ex0_48 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_48_mux0000,
      R => rst_inv,
      Q => data_ex0(48)
    );
  data_ex0_53 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_53_mux0000,
      R => rst_inv,
      Q => data_ex0(53)
    );
  data_ex1_9 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_9_mux0000,
      Q => data_ex1(9)
    );
  data_ex0_54 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_54_mux0000,
      R => rst_inv,
      Q => data_ex0(54)
    );
  data_ex0_49 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_49_mux0000,
      R => rst_inv,
      Q => data_ex0(49)
    );
  data_ex0_60 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_60_mux0000,
      R => rst_inv,
      Q => data_ex0(60)
    );
  data_ex0_55 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_55_mux0000,
      R => rst_inv,
      Q => data_ex0(55)
    );
  data_ex0_56 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_56_mux0000,
      R => rst_inv,
      Q => data_ex0(56)
    );
  data_ex0_61 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_61_mux0000,
      R => rst_inv,
      Q => data_ex0(61)
    );
  data_ex0_62 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_62_mux0000,
      R => rst_inv,
      Q => data_ex0(62)
    );
  data_ex0_57 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_57_mux0000,
      R => rst_inv,
      Q => data_ex0(57)
    );
  data_ex0_63 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_63_mux0000,
      R => rst_inv,
      Q => data_ex0(63)
    );
  data_ex0_58 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_58_mux0000,
      R => rst_inv,
      Q => data_ex0(58)
    );
  data_ex0_59 : FDRE
    port map (
      C => di_clk,
      CE => data_ex0_0_not0001,
      D => data_ex0_59_mux0000,
      R => rst_inv,
      Q => data_ex0(59)
    );
  data_ex2_1 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_1_mux0000,
      Q => data_ex2(1)
    );
  data_ex2_0 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_0_mux0000,
      Q => data_ex2(0)
    );
  data_ex4_11 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(11),
      R => rst_inv,
      Q => data_ex4(11)
    );
  data_ex4_13 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(13),
      R => rst_inv,
      Q => data_ex4(13)
    );
  data_ex4_12 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(12),
      R => rst_inv,
      Q => data_ex4(12)
    );
  data_ex2_2 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_2_mux0000,
      Q => data_ex2(2)
    );
  data_ex2_4 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_4_mux0000,
      Q => data_ex2(4)
    );
  data_ex2_3 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_3_mux0000,
      Q => data_ex2(3)
    );
  data_ex4_14 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(14),
      R => rst_inv,
      Q => data_ex4(14)
    );
  data_ex4_20 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(20),
      R => rst_inv,
      Q => data_ex4(20)
    );
  data_ex4_15 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(15),
      R => rst_inv,
      Q => data_ex4(15)
    );
  data_ex2_5 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_5_mux0000,
      Q => data_ex2(5)
    );
  data_ex4_21 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(21),
      R => rst_inv,
      Q => data_ex4(21)
    );
  data_ex4_22 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(22),
      R => rst_inv,
      Q => data_ex4(22)
    );
  data_ex4_16 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(16),
      R => rst_inv,
      Q => data_ex4(16)
    );
  data_ex2_6 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_6_mux0000,
      Q => data_ex2(6)
    );
  data_ex4_23 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(23),
      R => rst_inv,
      Q => data_ex4(23)
    );
  data_ex4_17 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(17),
      R => rst_inv,
      Q => data_ex4(17)
    );
  data_ex2_7 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_7_mux0000,
      Q => data_ex2(7)
    );
  data_ex4_24 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(24),
      R => rst_inv,
      Q => data_ex4(24)
    );
  data_ex4_18 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(18),
      R => rst_inv,
      Q => data_ex4(18)
    );
  data_ex2_8 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_8_mux0000,
      Q => data_ex2(8)
    );
  data_ex4_19 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(19),
      R => rst_inv,
      Q => data_ex4(19)
    );
  data_ex2_9 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_9_mux0000,
      Q => data_ex2(9)
    );
  data_ex4_30 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(30),
      R => rst_inv,
      Q => data_ex4(30)
    );
  data_ex4_25 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(25),
      R => rst_inv,
      Q => data_ex4(25)
    );
  data_ex4_26 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(26),
      R => rst_inv,
      Q => data_ex4(26)
    );
  data_ex4_31 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(31),
      R => rst_inv,
      Q => data_ex4(31)
    );
  data_ex4_33 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(1),
      R => rst_inv,
      Q => data_ex4(33)
    );
  data_ex4_27 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(27),
      R => rst_inv,
      Q => data_ex4(27)
    );
  data_ex4_29 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(29),
      R => rst_inv,
      Q => data_ex4(29)
    );
  data_ex4_28 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(28),
      R => rst_inv,
      Q => data_ex4(28)
    );
  data_ex4_34 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(2),
      R => rst_inv,
      Q => data_ex4(34)
    );
  data_ex4_40 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(8),
      R => rst_inv,
      Q => data_ex4(40)
    );
  data_ex4_35 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(3),
      R => rst_inv,
      Q => data_ex4(35)
    );
  data_ex4_41 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(9),
      R => rst_inv,
      Q => data_ex4(41)
    );
  data_ex4_36 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(4),
      R => rst_inv,
      Q => data_ex4(36)
    );
  data_ex4_43 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(11),
      R => rst_inv,
      Q => data_ex4(43)
    );
  data_ex4_42 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(10),
      R => rst_inv,
      Q => data_ex4(42)
    );
  data_ex4_37 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(5),
      R => rst_inv,
      Q => data_ex4(37)
    );
  data_ex4_39 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(7),
      R => rst_inv,
      Q => data_ex4(39)
    );
  data_ex4_38 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(6),
      R => rst_inv,
      Q => data_ex4(38)
    );
  data_ex4_44 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(12),
      R => rst_inv,
      Q => data_ex4(44)
    );
  data_ex4_51 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(19),
      R => rst_inv,
      Q => data_ex4(51)
    );
  data_ex4_50 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(18),
      R => rst_inv,
      Q => data_ex4(50)
    );
  data_ex4_45 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(13),
      R => rst_inv,
      Q => data_ex4(45)
    );
  data_ex4_47 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(15),
      R => rst_inv,
      Q => data_ex4(47)
    );
  data_ex4_46 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(14),
      R => rst_inv,
      Q => data_ex4(46)
    );
  data_ex4_52 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(20),
      R => rst_inv,
      Q => data_ex4(52)
    );
  data_ex4_48 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(16),
      R => rst_inv,
      Q => data_ex4(48)
    );
  data_ex4_53 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(21),
      R => rst_inv,
      Q => data_ex4(53)
    );
  data_ex4_60 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(28),
      R => rst_inv,
      Q => data_ex4(60)
    );
  data_ex4_49 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(17),
      R => rst_inv,
      Q => data_ex4(49)
    );
  data_ex4_54 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(22),
      R => rst_inv,
      Q => data_ex4(54)
    );
  data_ex4_61 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(29),
      R => rst_inv,
      Q => data_ex4(61)
    );
  data_ex4_55 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(23),
      R => rst_inv,
      Q => data_ex4(55)
    );
  data_ex4_56 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(24),
      R => rst_inv,
      Q => data_ex4(56)
    );
  data_ex4_62 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(30),
      R => rst_inv,
      Q => data_ex4(62)
    );
  data_ex4_57 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(25),
      R => rst_inv,
      Q => data_ex4(57)
    );
  data_ex4_63 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(31),
      R => rst_inv,
      Q => data_ex4(63)
    );
  data_ex4_0 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(0),
      R => rst_inv,
      Q => data_ex4(0)
    );
  data_ex4_58 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(26),
      R => rst_inv,
      Q => data_ex4(58)
    );
  data_ex4_59 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(27),
      R => rst_inv,
      Q => data_ex4(59)
    );
  data_ex4_1 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(1),
      R => rst_inv,
      Q => data_ex4(1)
    );
  data_ex4_2 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(2),
      R => rst_inv,
      Q => data_ex4(2)
    );
  data_ex4_5 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(5),
      R => rst_inv,
      Q => data_ex4(5)
    );
  data_ex4_3 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(3),
      R => rst_inv,
      Q => data_ex4(3)
    );
  data_ex4_4 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(4),
      R => rst_inv,
      Q => data_ex4(4)
    );
  data_ex2_10 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_10_mux0000,
      Q => data_ex2(10)
    );
  data_ex4_6 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(6),
      R => rst_inv,
      Q => data_ex4(6)
    );
  data_ex4_7 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(7),
      R => rst_inv,
      Q => data_ex4(7)
    );
  data_ex4_9 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(9),
      R => rst_inv,
      Q => data_ex4(9)
    );
  data_ex4_8 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(8),
      R => rst_inv,
      Q => data_ex4(8)
    );
  data_ex2_11 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_11_mux0000,
      Q => data_ex2(11)
    );
  data_ex2_14 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_14_mux0000,
      Q => data_ex2(14)
    );
  data_ex2_12 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_12_mux0000,
      Q => data_ex2(12)
    );
  data_ex2_13 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_13_mux0000,
      Q => data_ex2(13)
    );
  data_ex2_21 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_21_mux0000,
      Q => data_ex2(21)
    );
  data_ex2_20 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_20_mux0000,
      Q => data_ex2(20)
    );
  data_ex2_15 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_15_mux0000,
      Q => data_ex2(15)
    );
  data_ex2_16 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_16_mux0000,
      Q => data_ex2(16)
    );
  data_ex2_22 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_22_mux0000,
      Q => data_ex2(22)
    );
  data_ex2_17 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_17_mux0000,
      Q => data_ex2(17)
    );
  data_ex2_23 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_23_mux0000,
      Q => data_ex2(23)
    );
  data_ex2_19 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_19_mux0000,
      Q => data_ex2(19)
    );
  data_ex2_18 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_18_mux0000,
      Q => data_ex2(18)
    );
  data_ex2_24 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_24_mux0000,
      Q => data_ex2(24)
    );
  data_ex2_31 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_31_mux0000,
      Q => data_ex2(31)
    );
  data_ex2_30 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_30_mux0000,
      Q => data_ex2(30)
    );
  data_ex2_25 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_25_mux0000,
      Q => data_ex2(25)
    );
  data_ex2_27 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_27_mux0000,
      Q => data_ex2(27)
    );
  data_ex2_26 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_26_mux0000,
      Q => data_ex2(26)
    );
  data_ex2_32 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_32_mux0000,
      Q => data_ex2(32)
    );
  data_ex2_34 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_34_mux0000,
      Q => data_ex2(34)
    );
  data_ex2_33 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_33_mux0000,
      Q => data_ex2(33)
    );
  data_ex2_28 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_28_mux0000,
      Q => data_ex2(28)
    );
  data_ex2_35 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_35_mux0000,
      Q => data_ex2(35)
    );
  data_ex2_29 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_29_mux0000,
      Q => data_ex2(29)
    );
  data_ex2_40 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_40_mux0000,
      Q => data_ex2(40)
    );
  data_ex2_37 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_37_mux0000,
      Q => data_ex2(37)
    );
  data_ex2_36 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_36_mux0000,
      Q => data_ex2(36)
    );
  data_ex2_41 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_41_mux0000,
      Q => data_ex2(41)
    );
  data_ex2_38 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_38_mux0000,
      Q => data_ex2(38)
    );
  data_ex2_42 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_42_mux0000,
      Q => data_ex2(42)
    );
  data_ex2_43 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_43_mux0000,
      Q => data_ex2(43)
    );
  data_ex2_39 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_39_mux0000,
      Q => data_ex2(39)
    );
  data_ex2_44 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_44_mux0000,
      Q => data_ex2(44)
    );
  data_ex2_50 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_50_mux0000,
      Q => data_ex2(50)
    );
  data_ex2_45 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_45_mux0000,
      Q => data_ex2(45)
    );
  data_ex2_46 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_46_mux0000,
      Q => data_ex2(46)
    );
  data_ex2_51 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_51_mux0000,
      Q => data_ex2(51)
    );
  data_ex2_47 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_47_mux0000,
      Q => data_ex2(47)
    );
  data_ex2_52 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_52_mux0000,
      Q => data_ex2(52)
    );
  data_ex2_48 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_48_mux0000,
      Q => data_ex2(48)
    );
  data_ex2_53 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_53_mux0000,
      Q => data_ex2(53)
    );
  data_ex2_49 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_49_mux0000,
      Q => data_ex2(49)
    );
  data_ex2_54 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_54_mux0000,
      Q => data_ex2(54)
    );
  data_ex2_55 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_55_mux0000,
      Q => data_ex2(55)
    );
  data_ex2_60 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_60_mux0000,
      Q => data_ex2(60)
    );
  data_ex2_56 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_56_mux0000,
      Q => data_ex2(56)
    );
  data_ex2_61 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_61_mux0000,
      Q => data_ex2(61)
    );
  data_ex2_62 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_62_mux0000,
      Q => data_ex2(62)
    );
  data_ex2_57 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_57_mux0000,
      Q => data_ex2(57)
    );
  data_expect_10 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_10_mux0000,
      Q => NlwRenamedSig_OI_data_expect(10)
    );
  data_expect_11 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_11_mux0000,
      Q => NlwRenamedSig_OI_data_expect(11)
    );
  data_ex2_63 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_63_mux0000,
      Q => data_ex2(63)
    );
  data_ex2_58 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_58_mux0000,
      Q => data_ex2(58)
    );
  data_expect_12 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_12_mux0000,
      Q => NlwRenamedSig_OI_data_expect(12)
    );
  data_ex1_10 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_10_mux0000,
      Q => data_ex1(10)
    );
  data_ex2_59 : FDE
    port map (
      C => di_clk,
      CE => data_ex2_0_not0001,
      D => data_ex2_59_mux0000,
      Q => data_ex2(59)
    );
  data_ex1_12 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_12_mux0000,
      Q => data_ex1(12)
    );
  data_ex1_11 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_11_mux0000,
      Q => data_ex1(11)
    );
  data_expect_13 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_13_mux0000,
      Q => NlwRenamedSig_OI_data_expect(13)
    );
  data_expect_20 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_20_mux0000,
      Q => NlwRenamedSig_OI_data_expect(20)
    );
  data_expect_14 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_14_mux0000,
      Q => NlwRenamedSig_OI_data_expect(14)
    );
  data_ex1_13 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_13_mux0000,
      Q => data_ex1(13)
    );
  data_expect_21 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_21_mux0000,
      Q => NlwRenamedSig_OI_data_expect(21)
    );
  data_expect_15 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_15_mux0000,
      Q => NlwRenamedSig_OI_data_expect(15)
    );
  data_ex1_14 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_14_mux0000,
      Q => data_ex1(14)
    );
  data_ex1_15 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_15_mux0000,
      Q => data_ex1(15)
    );
  data_expect_16 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_16_mux0000,
      Q => NlwRenamedSig_OI_data_expect(16)
    );
  data_ex1_20 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_20_mux0000,
      Q => data_ex1(20)
    );
  data_expect_17 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_17_mux0000,
      Q => NlwRenamedSig_OI_data_expect(17)
    );
  data_expect_22 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_22_mux0000,
      Q => NlwRenamedSig_OI_data_expect(22)
    );
  data_ex1_21 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_21_mux0000,
      Q => data_ex1(21)
    );
  data_ex1_16 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_16_mux0000,
      Q => data_ex1(16)
    );
  data_expect_23 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_23_mux0000,
      Q => NlwRenamedSig_OI_data_expect(23)
    );
  data_expect_18 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_18_mux0000,
      Q => NlwRenamedSig_OI_data_expect(18)
    );
  data_expect_24 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_24_mux0000,
      Q => NlwRenamedSig_OI_data_expect(24)
    );
  data_ex1_22 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_22_mux0000,
      Q => data_ex1(22)
    );
  data_ex1_17 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_17_mux0000,
      Q => data_ex1(17)
    );
  data_ex1_18 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_18_mux0000,
      Q => data_ex1(18)
    );
  data_expect_19 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_19_mux0000,
      Q => NlwRenamedSig_OI_data_expect(19)
    );
  data_ex1_23 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_23_mux0000,
      Q => data_ex1(23)
    );
  data_ex1_24 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_24_mux0000,
      Q => data_ex1(24)
    );
  data_expect_30 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_30_mux0000,
      Q => NlwRenamedSig_OI_data_expect(30)
    );
  data_expect_25 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_25_mux0000,
      Q => NlwRenamedSig_OI_data_expect(25)
    );
  data_expect_31 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_31_mux0000,
      Q => NlwRenamedSig_OI_data_expect(31)
    );
  data_ex1_19 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_19_mux0000,
      Q => data_ex1(19)
    );
  data_expect_26 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_26_mux0000,
      Q => NlwRenamedSig_OI_data_expect(26)
    );
  data_expect_32 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_32_mux0000,
      Q => NlwRenamedSig_OI_data_expect(32)
    );
  data_ex1_30 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_30_mux0000,
      Q => data_ex1(30)
    );
  data_ex1_25 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_25_mux0000,
      Q => data_ex1(25)
    );
  data_ex1_26 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_26_mux0000,
      Q => data_ex1(26)
    );
  data_expect_27 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_27_mux0000,
      Q => NlwRenamedSig_OI_data_expect(27)
    );
  data_ex1_31 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_31_mux0000,
      Q => data_ex1(31)
    );
  data_expect_28 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_28_mux0000,
      Q => NlwRenamedSig_OI_data_expect(28)
    );
  data_en : FD
    port map (
      C => di_clk,
      D => data_en_mux0001,
      Q => data_en_1321
    );
  data_expect_33 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_33_mux0000,
      Q => NlwRenamedSig_OI_data_expect(33)
    );
  data_ex1_32 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_32_mux0000,
      Q => data_ex1(32)
    );
  data_ex1_27 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_27_mux0000,
      Q => data_ex1(27)
    );
  data_expect_0 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_0_mux0000,
      Q => NlwRenamedSig_OI_data_expect(0)
    );
  data_expect_34 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_34_mux0000,
      Q => NlwRenamedSig_OI_data_expect(34)
    );
  data_ex1_28 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_28_mux0000,
      Q => data_ex1(28)
    );
  data_expect_29 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_29_mux0000,
      Q => NlwRenamedSig_OI_data_expect(29)
    );
  data_ex1_33 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_33_mux0000,
      Q => data_ex1(33)
    );
  data_expect_40 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_40_mux0000,
      Q => NlwRenamedSig_OI_data_expect(40)
    );
  data_expect_1 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_1_mux0000,
      Q => NlwRenamedSig_OI_data_expect(1)
    );
  data_expect_35 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_35_mux0000,
      Q => NlwRenamedSig_OI_data_expect(35)
    );
  data_expect_2 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_2_mux0000,
      Q => NlwRenamedSig_OI_data_expect(2)
    );
  data_ex1_34 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_34_mux0000,
      Q => data_ex1(34)
    );
  data_ex1_29 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_29_mux0000,
      Q => data_ex1(29)
    );
  data_ex1_40 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_40_mux0000,
      Q => data_ex1(40)
    );
  data_expect_36 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_36_mux0000,
      Q => NlwRenamedSig_OI_data_expect(36)
    );
  data_expect_41 : FDE
    port map (
      C => di_clk,
      CE => data_expect_3_not0001,
      D => data_expect_41_mux0000,
      Q => NlwRenamedSig_OI_data_expect(41)
    );
  data_ex1_35 : FDE
    port map (
      C => di_clk,
      CE => data_ex1_36_not0001_1513,
      D => data_ex1_35_mux0000,
      Q => data_ex1(35)
    );
  di_rdy : FDR
    port map (
      C => di_clk,
      D => di_start,
      R => di_rdy_or0000_inv,
      Q => di_rdy_2272
    );
  data_ex5_12 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(11),
      R => rst_inv,
      Q => data_ex5(12)
    );
  di_data_we_947 : FD
    port map (
      C => di_clk,
      D => data_en_1321,
      Q => di_data_we
    );
  cnt1_eq : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => cnt1_eq_and0000_1317,
      R => rst_inv,
      Q => cnt1_eq_1300
    );
  data_ex5_13 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(12),
      R => rst_inv,
      Q => data_ex5(13)
    );
  data_ex4_10 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_10_not0001,
      D => data_ex4_31_0_add0000(10),
      R => rst_inv,
      Q => data_ex4(10)
    );
  data_ex4_32 : FDRE
    port map (
      C => di_clk,
      CE => data_ex4_32_not0001,
      D => data_ex4_63_32_add0000(0),
      R => rst_inv,
      Q => data_ex4(32)
    );
  cnt1_z : FDSE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => cnt1_eq_1300,
      S => rst_inv,
      Q => cnt1_z_1320
    );
  data_ex5_14 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(13),
      R => rst_inv,
      Q => data_ex5(14)
    );
  data_ex5_15 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(14),
      R => rst_inv,
      Q => data_ex5(15)
    );
  data_ex5_16 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(15),
      R => rst_inv,
      Q => data_ex5(16)
    );
  data_ex5_17 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(16),
      R => rst_inv,
      Q => data_ex5(17)
    );
  data_ex5_18 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(17),
      R => rst_inv,
      Q => data_ex5(18)
    );
  data_ex5_19 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(18),
      R => rst_inv,
      Q => data_ex5(19)
    );
  data_ex5_20 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(19),
      R => rst_inv,
      Q => data_ex5(20)
    );
  data_ex5_21 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(20),
      R => rst_inv,
      Q => data_ex5(21)
    );
  data_ex5_22 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(21),
      R => rst_inv,
      Q => data_ex5(22)
    );
  data_ex5_23 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(22),
      R => rst_inv,
      Q => data_ex5(23)
    );
  data_ex5_24 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(23),
      R => rst_inv,
      Q => data_ex5(24)
    );
  data_ex5_25 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(24),
      R => rst_inv,
      Q => data_ex5(25)
    );
  data_ex5_26 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(25),
      R => rst_inv,
      Q => data_ex5(26)
    );
  data_ex5_27 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(26),
      R => rst_inv,
      Q => data_ex5(27)
    );
  data_ex5_28 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(27),
      R => rst_inv,
      Q => data_ex5(28)
    );
  data_ex5_29 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(28),
      R => rst_inv,
      Q => data_ex5(29)
    );
  data_ex5_30 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(29),
      R => rst_inv,
      Q => data_ex5(30)
    );
  data_ex5_31 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(30),
      R => rst_inv,
      Q => data_ex5(31)
    );
  data_ex5_32 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(31),
      R => rst_inv,
      Q => data_ex5(32)
    );
  data_ex5_33 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(32),
      R => rst_inv,
      Q => data_ex5(33)
    );
  data_ex5_34 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(33),
      R => rst_inv,
      Q => data_ex5(34)
    );
  data_ex5_35 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(34),
      R => rst_inv,
      Q => data_ex5(35)
    );
  data_ex5_36 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(35),
      R => rst_inv,
      Q => data_ex5(36)
    );
  data_ex5_37 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(36),
      R => rst_inv,
      Q => data_ex5(37)
    );
  data_ex5_38 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(37),
      R => rst_inv,
      Q => data_ex5(38)
    );
  data_ex5_39 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(38),
      R => rst_inv,
      Q => data_ex5(39)
    );
  data_ex5_40 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(39),
      R => rst_inv,
      Q => data_ex5(40)
    );
  data_ex5_41 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(40),
      R => rst_inv,
      Q => data_ex5(41)
    );
  data_ex5_42 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(41),
      R => rst_inv,
      Q => data_ex5(42)
    );
  data_ex5_43 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(42),
      R => rst_inv,
      Q => data_ex5(43)
    );
  data_ex5_44 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(43),
      R => rst_inv,
      Q => data_ex5(44)
    );
  data_ex5_45 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(44),
      R => rst_inv,
      Q => data_ex5(45)
    );
  data_ex5_46 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(45),
      R => rst_inv,
      Q => data_ex5(46)
    );
  data_ex5_47 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(46),
      R => rst_inv,
      Q => data_ex5(47)
    );
  data_ex5_48 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(47),
      R => rst_inv,
      Q => data_ex5(48)
    );
  data_ex5_49 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(48),
      R => rst_inv,
      Q => data_ex5(49)
    );
  data_ex5_50 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(49),
      R => rst_inv,
      Q => data_ex5(50)
    );
  data_ex5_51 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(50),
      R => rst_inv,
      Q => data_ex5(51)
    );
  data_ex5_52 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(51),
      R => rst_inv,
      Q => data_ex5(52)
    );
  data_ex5_53 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(52),
      R => rst_inv,
      Q => data_ex5(53)
    );
  data_ex5_54 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(53),
      R => rst_inv,
      Q => data_ex5(54)
    );
  data_ex5_55 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(54),
      R => rst_inv,
      Q => data_ex5(55)
    );
  data_ex5_56 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(55),
      R => rst_inv,
      Q => data_ex5(56)
    );
  data_ex5_57 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(56),
      R => rst_inv,
      Q => data_ex5(57)
    );
  data_ex5_58 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(57),
      R => rst_inv,
      Q => data_ex5(58)
    );
  data_ex5_59 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(58),
      R => rst_inv,
      Q => data_ex5(59)
    );
  data_ex5_60 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(59),
      R => rst_inv,
      Q => data_ex5(60)
    );
  data_ex5_61 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(60),
      R => rst_inv,
      Q => data_ex5(61)
    );
  data_ex5_62 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(61),
      R => rst_inv,
      Q => data_ex5(62)
    );
  data_ex5_63 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(62),
      R => rst_inv,
      Q => data_ex5(63)
    );
  data_ex5_0 : FDSE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5_0_xor0000,
      S => rst_inv,
      Q => data_ex5(0)
    );
  data_ex5_1 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(0),
      R => rst_inv,
      Q => data_ex5(1)
    );
  data_ex5_2 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(1),
      R => rst_inv,
      Q => data_ex5(2)
    );
  data_ex5_3 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(2),
      R => rst_inv,
      Q => data_ex5(3)
    );
  data_ex5_4 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(3),
      R => rst_inv,
      Q => data_ex5(4)
    );
  data_ex5_5 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(4),
      R => rst_inv,
      Q => data_ex5(5)
    );
  data_ex5_6 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(5),
      R => rst_inv,
      Q => data_ex5(6)
    );
  data_ex5_7 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(6),
      R => rst_inv,
      Q => data_ex5(7)
    );
  data_ex5_8 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(7),
      R => rst_inv,
      Q => data_ex5(8)
    );
  data_ex5_9 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(8),
      R => rst_inv,
      Q => data_ex5(9)
    );
  data_ex5_10 : FDRE
    port map (
      C => di_clk,
      CE => data_ex5_10_not0001,
      D => data_ex5(9),
      R => rst_inv,
      Q => data_ex5(10)
    );
  Mcount_xcnt2_cy_0_Q : MUXCY
    port map (
      CI => xcnt2_or0000,
      DI => N1,
      S => Mcount_xcnt2_lut(0),
      O => Mcount_xcnt2_cy(0)
    );
  Mcount_xcnt2_xor_0_Q : XORCY
    port map (
      CI => xcnt2_or0000,
      LI => Mcount_xcnt2_lut(0),
      O => Mcount_xcnt2
    );
  Mcount_xcnt2_cy_1_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(0),
      DI => N1,
      S => Mcount_xcnt2_lut(1),
      O => Mcount_xcnt2_cy(1)
    );
  Mcount_xcnt2_xor_1_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(0),
      LI => Mcount_xcnt2_lut(1),
      O => Mcount_xcnt21
    );
  Mcount_xcnt2_cy_2_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(1),
      DI => N1,
      S => Mcount_xcnt2_lut(2),
      O => Mcount_xcnt2_cy(2)
    );
  Mcount_xcnt2_xor_2_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(1),
      LI => Mcount_xcnt2_lut(2),
      O => Mcount_xcnt22
    );
  Mcount_xcnt2_cy_3_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(2),
      DI => N1,
      S => Mcount_xcnt2_lut(3),
      O => Mcount_xcnt2_cy(3)
    );
  Mcount_xcnt2_xor_3_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(2),
      LI => Mcount_xcnt2_lut(3),
      O => Mcount_xcnt23
    );
  Mcount_xcnt2_cy_4_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(3),
      DI => N1,
      S => Mcount_xcnt2_lut(4),
      O => Mcount_xcnt2_cy(4)
    );
  Mcount_xcnt2_xor_4_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(3),
      LI => Mcount_xcnt2_lut(4),
      O => Mcount_xcnt24
    );
  Mcount_xcnt2_cy_5_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(4),
      DI => N1,
      S => Mcount_xcnt2_lut(5),
      O => Mcount_xcnt2_cy(5)
    );
  Mcount_xcnt2_xor_5_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(4),
      LI => Mcount_xcnt2_lut(5),
      O => Mcount_xcnt25
    );
  Mcount_xcnt2_cy_6_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(5),
      DI => N1,
      S => Mcount_xcnt2_lut(6),
      O => Mcount_xcnt2_cy(6)
    );
  Mcount_xcnt2_xor_6_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(5),
      LI => Mcount_xcnt2_lut(6),
      O => Mcount_xcnt26
    );
  Mcount_xcnt2_cy_7_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(6),
      DI => N1,
      S => Mcount_xcnt2_lut(7),
      O => Mcount_xcnt2_cy(7)
    );
  Mcount_xcnt2_xor_7_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(6),
      LI => Mcount_xcnt2_lut(7),
      O => Mcount_xcnt27
    );
  Mcount_xcnt2_cy_8_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(7),
      DI => N1,
      S => Mcount_xcnt2_lut(8),
      O => Mcount_xcnt2_cy(8)
    );
  Mcount_xcnt2_xor_8_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(7),
      LI => Mcount_xcnt2_lut(8),
      O => Mcount_xcnt28
    );
  Mcount_xcnt2_cy_9_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(8),
      DI => N1,
      S => Mcount_xcnt2_lut(9),
      O => Mcount_xcnt2_cy(9)
    );
  Mcount_xcnt2_xor_9_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(8),
      LI => Mcount_xcnt2_lut(9),
      O => Mcount_xcnt29
    );
  Mcount_xcnt2_cy_10_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(9),
      DI => N1,
      S => Mcount_xcnt2_lut(10),
      O => Mcount_xcnt2_cy(10)
    );
  Mcount_xcnt2_xor_10_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(9),
      LI => Mcount_xcnt2_lut(10),
      O => Mcount_xcnt210
    );
  Mcount_xcnt2_cy_11_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(10),
      DI => N1,
      S => Mcount_xcnt2_lut(11),
      O => Mcount_xcnt2_cy(11)
    );
  Mcount_xcnt2_xor_11_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(10),
      LI => Mcount_xcnt2_lut(11),
      O => Mcount_xcnt211
    );
  Mcount_xcnt2_cy_12_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(11),
      DI => N1,
      S => Mcount_xcnt2_lut(12),
      O => Mcount_xcnt2_cy(12)
    );
  Mcount_xcnt2_xor_12_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(11),
      LI => Mcount_xcnt2_lut(12),
      O => Mcount_xcnt212
    );
  Mcount_xcnt2_cy_13_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(12),
      DI => N1,
      S => Mcount_xcnt2_lut(13),
      O => Mcount_xcnt2_cy(13)
    );
  Mcount_xcnt2_xor_13_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(12),
      LI => Mcount_xcnt2_lut(13),
      O => Mcount_xcnt213
    );
  Mcount_xcnt2_cy_14_Q : MUXCY
    port map (
      CI => Mcount_xcnt2_cy(13),
      DI => N1,
      S => Mcount_xcnt2_lut(14),
      O => Mcount_xcnt2_cy(14)
    );
  Mcount_xcnt2_xor_14_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(13),
      LI => Mcount_xcnt2_lut(14),
      O => Mcount_xcnt214
    );
  Mcount_xcnt2_xor_15_Q : XORCY
    port map (
      CI => Mcount_xcnt2_cy(14),
      LI => Mcount_xcnt2_lut(15),
      O => Mcount_xcnt215
    );
  Mcount_xcnt1_cy_0_Q : MUXCY
    port map (
      CI => xcnt1_or0000,
      DI => N1,
      S => Mcount_xcnt1_lut(0),
      O => Mcount_xcnt1_cy(0)
    );
  Mcount_xcnt1_xor_0_Q : XORCY
    port map (
      CI => xcnt1_or0000,
      LI => Mcount_xcnt1_lut(0),
      O => Mcount_xcnt1
    );
  Mcount_xcnt1_cy_1_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(0),
      DI => N1,
      S => Mcount_xcnt1_lut(1),
      O => Mcount_xcnt1_cy(1)
    );
  Mcount_xcnt1_xor_1_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(0),
      LI => Mcount_xcnt1_lut(1),
      O => Mcount_xcnt11
    );
  Mcount_xcnt1_cy_2_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(1),
      DI => N1,
      S => Mcount_xcnt1_lut(2),
      O => Mcount_xcnt1_cy(2)
    );
  Mcount_xcnt1_xor_2_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(1),
      LI => Mcount_xcnt1_lut(2),
      O => Mcount_xcnt12
    );
  Mcount_xcnt1_cy_3_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(2),
      DI => N1,
      S => Mcount_xcnt1_lut(3),
      O => Mcount_xcnt1_cy(3)
    );
  Mcount_xcnt1_xor_3_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(2),
      LI => Mcount_xcnt1_lut(3),
      O => Mcount_xcnt13
    );
  Mcount_xcnt1_cy_4_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(3),
      DI => N1,
      S => Mcount_xcnt1_lut(4),
      O => Mcount_xcnt1_cy(4)
    );
  Mcount_xcnt1_xor_4_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(3),
      LI => Mcount_xcnt1_lut(4),
      O => Mcount_xcnt14
    );
  Mcount_xcnt1_cy_5_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(4),
      DI => N1,
      S => Mcount_xcnt1_lut(5),
      O => Mcount_xcnt1_cy(5)
    );
  Mcount_xcnt1_xor_5_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(4),
      LI => Mcount_xcnt1_lut(5),
      O => Mcount_xcnt15
    );
  Mcount_xcnt1_cy_6_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(5),
      DI => N1,
      S => Mcount_xcnt1_lut(6),
      O => Mcount_xcnt1_cy(6)
    );
  Mcount_xcnt1_xor_6_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(5),
      LI => Mcount_xcnt1_lut(6),
      O => Mcount_xcnt16
    );
  Mcount_xcnt1_cy_7_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(6),
      DI => N1,
      S => Mcount_xcnt1_lut(7),
      O => Mcount_xcnt1_cy(7)
    );
  Mcount_xcnt1_xor_7_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(6),
      LI => Mcount_xcnt1_lut(7),
      O => Mcount_xcnt17
    );
  Mcount_xcnt1_cy_8_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(7),
      DI => N1,
      S => Mcount_xcnt1_lut(8),
      O => Mcount_xcnt1_cy(8)
    );
  Mcount_xcnt1_xor_8_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(7),
      LI => Mcount_xcnt1_lut(8),
      O => Mcount_xcnt18
    );
  Mcount_xcnt1_cy_9_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(8),
      DI => N1,
      S => Mcount_xcnt1_lut(9),
      O => Mcount_xcnt1_cy(9)
    );
  Mcount_xcnt1_xor_9_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(8),
      LI => Mcount_xcnt1_lut(9),
      O => Mcount_xcnt19
    );
  Mcount_xcnt1_cy_10_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(9),
      DI => N1,
      S => Mcount_xcnt1_lut(10),
      O => Mcount_xcnt1_cy(10)
    );
  Mcount_xcnt1_xor_10_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(9),
      LI => Mcount_xcnt1_lut(10),
      O => Mcount_xcnt110
    );
  Mcount_xcnt1_cy_11_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(10),
      DI => N1,
      S => Mcount_xcnt1_lut(11),
      O => Mcount_xcnt1_cy(11)
    );
  Mcount_xcnt1_xor_11_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(10),
      LI => Mcount_xcnt1_lut(11),
      O => Mcount_xcnt111
    );
  Mcount_xcnt1_cy_12_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(11),
      DI => N1,
      S => Mcount_xcnt1_lut(12),
      O => Mcount_xcnt1_cy(12)
    );
  Mcount_xcnt1_xor_12_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(11),
      LI => Mcount_xcnt1_lut(12),
      O => Mcount_xcnt112
    );
  Mcount_xcnt1_cy_13_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(12),
      DI => N1,
      S => Mcount_xcnt1_lut(13),
      O => Mcount_xcnt1_cy(13)
    );
  Mcount_xcnt1_xor_13_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(12),
      LI => Mcount_xcnt1_lut(13),
      O => Mcount_xcnt113
    );
  Mcount_xcnt1_cy_14_Q : MUXCY
    port map (
      CI => Mcount_xcnt1_cy(13),
      DI => N1,
      S => Mcount_xcnt1_lut(14),
      O => Mcount_xcnt1_cy(14)
    );
  Mcount_xcnt1_xor_14_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(13),
      LI => Mcount_xcnt1_lut(14),
      O => Mcount_xcnt114
    );
  Mcount_xcnt1_xor_15_Q : XORCY
    port map (
      CI => Mcount_xcnt1_cy(14),
      LI => Mcount_xcnt1_lut(15),
      O => Mcount_xcnt115
    );
  xcnt2_0 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt2,
      Q => xcnt2(0)
    );
  xcnt2_1 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt21,
      Q => xcnt2(1)
    );
  xcnt2_2 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt22,
      Q => xcnt2(2)
    );
  xcnt2_3 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt23,
      Q => xcnt2(3)
    );
  xcnt2_4 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt24,
      Q => xcnt2(4)
    );
  xcnt2_5 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt25,
      Q => xcnt2(5)
    );
  xcnt2_6 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt26,
      Q => xcnt2(6)
    );
  xcnt2_7 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt27,
      Q => xcnt2(7)
    );
  xcnt2_8 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt28,
      Q => xcnt2(8)
    );
  xcnt2_9 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt29,
      Q => xcnt2(9)
    );
  xcnt2_10 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt210,
      Q => xcnt2(10)
    );
  xcnt2_11 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt211,
      Q => xcnt2(11)
    );
  xcnt2_12 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt212,
      Q => xcnt2(12)
    );
  xcnt2_13 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt213,
      Q => xcnt2(13)
    );
  xcnt2_14 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt214,
      Q => xcnt2(14)
    );
  xcnt2_15 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt215,
      Q => xcnt2(15)
    );
  xcnt1_0 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt1,
      Q => xcnt1(0)
    );
  xcnt1_1 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt11,
      Q => xcnt1(1)
    );
  xcnt1_2 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt12,
      Q => xcnt1(2)
    );
  xcnt1_3 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt13,
      Q => xcnt1(3)
    );
  xcnt1_4 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt14,
      Q => xcnt1(4)
    );
  xcnt1_5 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt15,
      Q => xcnt1(5)
    );
  xcnt1_6 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt16,
      Q => xcnt1(6)
    );
  xcnt1_7 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt17,
      Q => xcnt1(7)
    );
  xcnt1_8 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt18,
      Q => xcnt1(8)
    );
  xcnt1_9 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt19,
      Q => xcnt1(9)
    );
  xcnt1_10 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt110,
      Q => xcnt1(10)
    );
  xcnt1_11 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt111,
      Q => xcnt1(11)
    );
  xcnt1_12 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt112,
      Q => xcnt1(12)
    );
  xcnt1_13 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt113,
      Q => xcnt1(13)
    );
  xcnt1_14 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt114,
      Q => xcnt1(14)
    );
  xcnt1_15 : FD
    port map (
      C => di_clk,
      D => Mcount_xcnt115,
      Q => xcnt1(15)
    );
  block_mode_0 : FDRE
    port map (
      C => di_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode,
      R => block_mode_or0000_1241,
      Q => block_mode(0)
    );
  block_mode_1 : FDRE
    port map (
      C => di_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode1,
      R => block_mode_or0000_1241,
      Q => block_mode(1)
    );
  block_mode_2 : FDRE
    port map (
      C => di_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode2,
      R => block_mode_or0000_1241,
      Q => block_mode(2)
    );
  block_mode_3 : FDRE
    port map (
      C => di_clk,
      CE => block_mode_not0001,
      D => Mcount_block_mode3,
      R => block_mode_or0000_1241,
      Q => block_mode(3)
    );
  block_rd_0 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(0),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(0)
    );
  block_rd_1 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(1),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(1)
    );
  block_rd_2 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(2),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(2)
    );
  block_rd_3 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(3),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(3)
    );
  block_rd_4 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(4),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(4)
    );
  block_rd_5 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(5),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(5)
    );
  block_rd_6 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(6),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(6)
    );
  block_rd_7 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(7),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(7)
    );
  block_rd_8 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(8),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(8)
    );
  block_rd_9 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(9),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(9)
    );
  block_rd_10 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(10),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(10)
    );
  block_rd_11 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(11),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(11)
    );
  block_rd_12 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(12),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(12)
    );
  block_rd_13 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(13),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(13)
    );
  block_rd_14 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(14),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(14)
    );
  block_rd_15 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(15),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(15)
    );
  block_rd_16 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(16),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(16)
    );
  block_rd_17 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(17),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(17)
    );
  block_rd_18 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(18),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(18)
    );
  block_rd_19 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(19),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(19)
    );
  block_rd_20 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(20),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(20)
    );
  block_rd_21 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(21),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(21)
    );
  block_rd_22 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(22),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(22)
    );
  block_rd_23 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(23),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(23)
    );
  block_rd_24 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(24),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(24)
    );
  block_rd_25 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(25),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(25)
    );
  block_rd_26 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(26),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(26)
    );
  block_rd_27 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(27),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(27)
    );
  block_rd_28 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(28),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(28)
    );
  block_rd_29 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(29),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(29)
    );
  block_rd_30 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(30),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(30)
    );
  block_rd_31 : FDRE
    port map (
      C => di_clk,
      CE => block_rd_and0000,
      D => Result(31),
      R => rst_inv,
      Q => NlwRenamedSig_OI_block_rd(31)
    );
  cnt1_0 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_0_1,
      R => cnt1_or0000,
      Q => cnt1(0)
    );
  cnt1_1 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_1_1,
      R => cnt1_or0000,
      Q => cnt1(1)
    );
  cnt1_2 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_2_1,
      R => cnt1_or0000,
      Q => cnt1(2)
    );
  cnt1_3 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_3_1,
      R => cnt1_or0000,
      Q => cnt1(3)
    );
  cnt1_4 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_4_1,
      R => cnt1_or0000,
      Q => cnt1(4)
    );
  cnt1_5 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_5_1,
      R => cnt1_or0000,
      Q => cnt1(5)
    );
  cnt1_6 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_6_1,
      R => cnt1_or0000,
      Q => cnt1(6)
    );
  cnt1_7 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_7_1,
      R => cnt1_or0000,
      Q => cnt1(7)
    );
  cnt1_8 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_8_1,
      R => cnt1_or0000,
      Q => cnt1(8)
    );
  cnt1_9 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_9_1,
      R => cnt1_or0000,
      Q => cnt1(9)
    );
  cnt1_10 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_10_1,
      R => cnt1_or0000,
      Q => cnt1(10)
    );
  cnt1_11 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_11_1,
      R => cnt1_or0000,
      Q => cnt1(11)
    );
  cnt1_12 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_12_1,
      R => cnt1_or0000,
      Q => cnt1(12)
    );
  cnt1_13 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_13_1,
      R => cnt1_or0000,
      Q => cnt1(13)
    );
  cnt1_14 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_14_1,
      R => cnt1_or0000,
      Q => cnt1(14)
    );
  cnt1_15 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_15_1,
      R => cnt1_or0000,
      Q => cnt1(15)
    );
  cnt1_16 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_16_1,
      R => cnt1_or0000,
      Q => cnt1(16)
    );
  cnt1_17 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_17_1,
      R => cnt1_or0000,
      Q => cnt1(17)
    );
  cnt1_18 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_18_1,
      R => cnt1_or0000,
      Q => cnt1(18)
    );
  cnt1_19 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_19_1,
      R => cnt1_or0000,
      Q => cnt1(19)
    );
  cnt1_20 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_20_1,
      R => cnt1_or0000,
      Q => cnt1(20)
    );
  cnt1_21 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_21_1,
      R => cnt1_or0000,
      Q => cnt1(21)
    );
  cnt1_22 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_22_1,
      R => cnt1_or0000,
      Q => cnt1(22)
    );
  cnt1_23 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_23_1,
      R => cnt1_or0000,
      Q => cnt1(23)
    );
  cnt1_24 : FDRE
    port map (
      C => di_clk,
      CE => data_en_1321,
      D => Result_24_1,
      R => cnt1_or0000,
      Q => cnt1(24)
    );
  Madd_data_ex4_63_32_add0000_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Madd_data_ex4_63_32_add0000_lut(0),
      O => Madd_data_ex4_63_32_add0000_cy(0)
    );
  Madd_data_ex4_63_32_add0000_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Madd_data_ex4_63_32_add0000_lut(0),
      O => data_ex4_63_32_add0000(0)
    );
  Madd_data_ex4_63_32_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(0),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_1_rt_748,
      O => Madd_data_ex4_63_32_add0000_cy(1)
    );
  Madd_data_ex4_63_32_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(0),
      LI => Madd_data_ex4_63_32_add0000_cy_1_rt_748,
      O => data_ex4_63_32_add0000(1)
    );
  Madd_data_ex4_63_32_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(1),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_2_rt_770,
      O => Madd_data_ex4_63_32_add0000_cy(2)
    );
  Madd_data_ex4_63_32_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(1),
      LI => Madd_data_ex4_63_32_add0000_cy_2_rt_770,
      O => data_ex4_63_32_add0000(2)
    );
  Madd_data_ex4_63_32_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(2),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_3_rt_774,
      O => Madd_data_ex4_63_32_add0000_cy(3)
    );
  Madd_data_ex4_63_32_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(2),
      LI => Madd_data_ex4_63_32_add0000_cy_3_rt_774,
      O => data_ex4_63_32_add0000(3)
    );
  Madd_data_ex4_63_32_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(3),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_4_rt_776,
      O => Madd_data_ex4_63_32_add0000_cy(4)
    );
  Madd_data_ex4_63_32_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(3),
      LI => Madd_data_ex4_63_32_add0000_cy_4_rt_776,
      O => data_ex4_63_32_add0000(4)
    );
  Madd_data_ex4_63_32_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(4),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_5_rt_778,
      O => Madd_data_ex4_63_32_add0000_cy(5)
    );
  Madd_data_ex4_63_32_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(4),
      LI => Madd_data_ex4_63_32_add0000_cy_5_rt_778,
      O => data_ex4_63_32_add0000(5)
    );
  Madd_data_ex4_63_32_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(5),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_6_rt_780,
      O => Madd_data_ex4_63_32_add0000_cy(6)
    );
  Madd_data_ex4_63_32_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(5),
      LI => Madd_data_ex4_63_32_add0000_cy_6_rt_780,
      O => data_ex4_63_32_add0000(6)
    );
  Madd_data_ex4_63_32_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(6),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_7_rt_782,
      O => Madd_data_ex4_63_32_add0000_cy(7)
    );
  Madd_data_ex4_63_32_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(6),
      LI => Madd_data_ex4_63_32_add0000_cy_7_rt_782,
      O => data_ex4_63_32_add0000(7)
    );
  Madd_data_ex4_63_32_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(7),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_8_rt_784,
      O => Madd_data_ex4_63_32_add0000_cy(8)
    );
  Madd_data_ex4_63_32_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(7),
      LI => Madd_data_ex4_63_32_add0000_cy_8_rt_784,
      O => data_ex4_63_32_add0000(8)
    );
  Madd_data_ex4_63_32_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(8),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_9_rt_786,
      O => Madd_data_ex4_63_32_add0000_cy(9)
    );
  Madd_data_ex4_63_32_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(8),
      LI => Madd_data_ex4_63_32_add0000_cy_9_rt_786,
      O => data_ex4_63_32_add0000(9)
    );
  Madd_data_ex4_63_32_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(9),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_10_rt_728,
      O => Madd_data_ex4_63_32_add0000_cy(10)
    );
  Madd_data_ex4_63_32_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(9),
      LI => Madd_data_ex4_63_32_add0000_cy_10_rt_728,
      O => data_ex4_63_32_add0000(10)
    );
  Madd_data_ex4_63_32_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(10),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_11_rt_730,
      O => Madd_data_ex4_63_32_add0000_cy(11)
    );
  Madd_data_ex4_63_32_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(10),
      LI => Madd_data_ex4_63_32_add0000_cy_11_rt_730,
      O => data_ex4_63_32_add0000(11)
    );
  Madd_data_ex4_63_32_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(11),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_12_rt_732,
      O => Madd_data_ex4_63_32_add0000_cy(12)
    );
  Madd_data_ex4_63_32_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(11),
      LI => Madd_data_ex4_63_32_add0000_cy_12_rt_732,
      O => data_ex4_63_32_add0000(12)
    );
  Madd_data_ex4_63_32_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(12),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_13_rt_734,
      O => Madd_data_ex4_63_32_add0000_cy(13)
    );
  Madd_data_ex4_63_32_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(12),
      LI => Madd_data_ex4_63_32_add0000_cy_13_rt_734,
      O => data_ex4_63_32_add0000(13)
    );
  Madd_data_ex4_63_32_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(13),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_14_rt_736,
      O => Madd_data_ex4_63_32_add0000_cy(14)
    );
  Madd_data_ex4_63_32_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(13),
      LI => Madd_data_ex4_63_32_add0000_cy_14_rt_736,
      O => data_ex4_63_32_add0000(14)
    );
  Madd_data_ex4_63_32_add0000_cy_15_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(14),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_15_rt_738,
      O => Madd_data_ex4_63_32_add0000_cy(15)
    );
  Madd_data_ex4_63_32_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(14),
      LI => Madd_data_ex4_63_32_add0000_cy_15_rt_738,
      O => data_ex4_63_32_add0000(15)
    );
  Madd_data_ex4_63_32_add0000_cy_16_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(15),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_16_rt_740,
      O => Madd_data_ex4_63_32_add0000_cy(16)
    );
  Madd_data_ex4_63_32_add0000_xor_16_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(15),
      LI => Madd_data_ex4_63_32_add0000_cy_16_rt_740,
      O => data_ex4_63_32_add0000(16)
    );
  Madd_data_ex4_63_32_add0000_cy_17_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(16),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_17_rt_742,
      O => Madd_data_ex4_63_32_add0000_cy(17)
    );
  Madd_data_ex4_63_32_add0000_xor_17_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(16),
      LI => Madd_data_ex4_63_32_add0000_cy_17_rt_742,
      O => data_ex4_63_32_add0000(17)
    );
  Madd_data_ex4_63_32_add0000_cy_18_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(17),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_18_rt_744,
      O => Madd_data_ex4_63_32_add0000_cy(18)
    );
  Madd_data_ex4_63_32_add0000_xor_18_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(17),
      LI => Madd_data_ex4_63_32_add0000_cy_18_rt_744,
      O => data_ex4_63_32_add0000(18)
    );
  Madd_data_ex4_63_32_add0000_cy_19_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(18),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_19_rt_746,
      O => Madd_data_ex4_63_32_add0000_cy(19)
    );
  Madd_data_ex4_63_32_add0000_xor_19_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(18),
      LI => Madd_data_ex4_63_32_add0000_cy_19_rt_746,
      O => data_ex4_63_32_add0000(19)
    );
  Madd_data_ex4_63_32_add0000_cy_20_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(19),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_20_rt_750,
      O => Madd_data_ex4_63_32_add0000_cy(20)
    );
  Madd_data_ex4_63_32_add0000_xor_20_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(19),
      LI => Madd_data_ex4_63_32_add0000_cy_20_rt_750,
      O => data_ex4_63_32_add0000(20)
    );
  Madd_data_ex4_63_32_add0000_cy_21_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(20),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_21_rt_752,
      O => Madd_data_ex4_63_32_add0000_cy(21)
    );
  Madd_data_ex4_63_32_add0000_xor_21_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(20),
      LI => Madd_data_ex4_63_32_add0000_cy_21_rt_752,
      O => data_ex4_63_32_add0000(21)
    );
  Madd_data_ex4_63_32_add0000_cy_22_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(21),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_22_rt_754,
      O => Madd_data_ex4_63_32_add0000_cy(22)
    );
  Madd_data_ex4_63_32_add0000_xor_22_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(21),
      LI => Madd_data_ex4_63_32_add0000_cy_22_rt_754,
      O => data_ex4_63_32_add0000(22)
    );
  Madd_data_ex4_63_32_add0000_cy_23_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(22),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_23_rt_756,
      O => Madd_data_ex4_63_32_add0000_cy(23)
    );
  Madd_data_ex4_63_32_add0000_xor_23_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(22),
      LI => Madd_data_ex4_63_32_add0000_cy_23_rt_756,
      O => data_ex4_63_32_add0000(23)
    );
  Madd_data_ex4_63_32_add0000_cy_24_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(23),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_24_rt_758,
      O => Madd_data_ex4_63_32_add0000_cy(24)
    );
  Madd_data_ex4_63_32_add0000_xor_24_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(23),
      LI => Madd_data_ex4_63_32_add0000_cy_24_rt_758,
      O => data_ex4_63_32_add0000(24)
    );
  Madd_data_ex4_63_32_add0000_cy_25_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(24),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_25_rt_760,
      O => Madd_data_ex4_63_32_add0000_cy(25)
    );
  Madd_data_ex4_63_32_add0000_xor_25_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(24),
      LI => Madd_data_ex4_63_32_add0000_cy_25_rt_760,
      O => data_ex4_63_32_add0000(25)
    );
  Madd_data_ex4_63_32_add0000_cy_26_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(25),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_26_rt_762,
      O => Madd_data_ex4_63_32_add0000_cy(26)
    );
  Madd_data_ex4_63_32_add0000_xor_26_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(25),
      LI => Madd_data_ex4_63_32_add0000_cy_26_rt_762,
      O => data_ex4_63_32_add0000(26)
    );
  Madd_data_ex4_63_32_add0000_cy_27_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(26),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_27_rt_764,
      O => Madd_data_ex4_63_32_add0000_cy(27)
    );
  Madd_data_ex4_63_32_add0000_xor_27_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(26),
      LI => Madd_data_ex4_63_32_add0000_cy_27_rt_764,
      O => data_ex4_63_32_add0000(27)
    );
  Madd_data_ex4_63_32_add0000_cy_28_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(27),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_28_rt_766,
      O => Madd_data_ex4_63_32_add0000_cy(28)
    );
  Madd_data_ex4_63_32_add0000_xor_28_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(27),
      LI => Madd_data_ex4_63_32_add0000_cy_28_rt_766,
      O => data_ex4_63_32_add0000(28)
    );
  Madd_data_ex4_63_32_add0000_cy_29_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(28),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_29_rt_768,
      O => Madd_data_ex4_63_32_add0000_cy(29)
    );
  Madd_data_ex4_63_32_add0000_xor_29_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(28),
      LI => Madd_data_ex4_63_32_add0000_cy_29_rt_768,
      O => data_ex4_63_32_add0000(29)
    );
  Madd_data_ex4_63_32_add0000_cy_30_Q : MUXCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(29),
      DI => N0,
      S => Madd_data_ex4_63_32_add0000_cy_30_rt_772,
      O => Madd_data_ex4_63_32_add0000_cy(30)
    );
  Madd_data_ex4_63_32_add0000_xor_30_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(29),
      LI => Madd_data_ex4_63_32_add0000_cy_30_rt_772,
      O => data_ex4_63_32_add0000(30)
    );
  Madd_data_ex4_63_32_add0000_xor_31_Q : XORCY
    port map (
      CI => Madd_data_ex4_63_32_add0000_cy(30),
      LI => Madd_data_ex4_63_32_add0000_xor_31_rt_788,
      O => data_ex4_63_32_add0000(31)
    );
  Madd_data_ex4_31_0_add0000_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Madd_data_ex4_31_0_add0000_lut(0),
      O => Madd_data_ex4_31_0_add0000_cy(0)
    );
  Madd_data_ex4_31_0_add0000_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Madd_data_ex4_31_0_add0000_lut(0),
      O => data_ex4_31_0_add0000(0)
    );
  Madd_data_ex4_31_0_add0000_cy_1_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(0),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_1_rt_685,
      O => Madd_data_ex4_31_0_add0000_cy(1)
    );
  Madd_data_ex4_31_0_add0000_xor_1_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(0),
      LI => Madd_data_ex4_31_0_add0000_cy_1_rt_685,
      O => data_ex4_31_0_add0000(1)
    );
  Madd_data_ex4_31_0_add0000_cy_2_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(1),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_2_rt_707,
      O => Madd_data_ex4_31_0_add0000_cy(2)
    );
  Madd_data_ex4_31_0_add0000_xor_2_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(1),
      LI => Madd_data_ex4_31_0_add0000_cy_2_rt_707,
      O => data_ex4_31_0_add0000(2)
    );
  Madd_data_ex4_31_0_add0000_cy_3_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(2),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_3_rt_711,
      O => Madd_data_ex4_31_0_add0000_cy(3)
    );
  Madd_data_ex4_31_0_add0000_xor_3_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(2),
      LI => Madd_data_ex4_31_0_add0000_cy_3_rt_711,
      O => data_ex4_31_0_add0000(3)
    );
  Madd_data_ex4_31_0_add0000_cy_4_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(3),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_4_rt_713,
      O => Madd_data_ex4_31_0_add0000_cy(4)
    );
  Madd_data_ex4_31_0_add0000_xor_4_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(3),
      LI => Madd_data_ex4_31_0_add0000_cy_4_rt_713,
      O => data_ex4_31_0_add0000(4)
    );
  Madd_data_ex4_31_0_add0000_cy_5_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(4),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_5_rt_715,
      O => Madd_data_ex4_31_0_add0000_cy(5)
    );
  Madd_data_ex4_31_0_add0000_xor_5_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(4),
      LI => Madd_data_ex4_31_0_add0000_cy_5_rt_715,
      O => data_ex4_31_0_add0000(5)
    );
  Madd_data_ex4_31_0_add0000_cy_6_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(5),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_6_rt_717,
      O => Madd_data_ex4_31_0_add0000_cy(6)
    );
  Madd_data_ex4_31_0_add0000_xor_6_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(5),
      LI => Madd_data_ex4_31_0_add0000_cy_6_rt_717,
      O => data_ex4_31_0_add0000(6)
    );
  Madd_data_ex4_31_0_add0000_cy_7_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(6),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_7_rt_719,
      O => Madd_data_ex4_31_0_add0000_cy(7)
    );
  Madd_data_ex4_31_0_add0000_xor_7_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(6),
      LI => Madd_data_ex4_31_0_add0000_cy_7_rt_719,
      O => data_ex4_31_0_add0000(7)
    );
  Madd_data_ex4_31_0_add0000_cy_8_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(7),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_8_rt_721,
      O => Madd_data_ex4_31_0_add0000_cy(8)
    );
  Madd_data_ex4_31_0_add0000_xor_8_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(7),
      LI => Madd_data_ex4_31_0_add0000_cy_8_rt_721,
      O => data_ex4_31_0_add0000(8)
    );
  Madd_data_ex4_31_0_add0000_cy_9_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(8),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_9_rt_723,
      O => Madd_data_ex4_31_0_add0000_cy(9)
    );
  Madd_data_ex4_31_0_add0000_xor_9_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(8),
      LI => Madd_data_ex4_31_0_add0000_cy_9_rt_723,
      O => data_ex4_31_0_add0000(9)
    );
  Madd_data_ex4_31_0_add0000_cy_10_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(9),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_10_rt_665,
      O => Madd_data_ex4_31_0_add0000_cy(10)
    );
  Madd_data_ex4_31_0_add0000_xor_10_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(9),
      LI => Madd_data_ex4_31_0_add0000_cy_10_rt_665,
      O => data_ex4_31_0_add0000(10)
    );
  Madd_data_ex4_31_0_add0000_cy_11_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(10),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_11_rt_667,
      O => Madd_data_ex4_31_0_add0000_cy(11)
    );
  Madd_data_ex4_31_0_add0000_xor_11_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(10),
      LI => Madd_data_ex4_31_0_add0000_cy_11_rt_667,
      O => data_ex4_31_0_add0000(11)
    );
  Madd_data_ex4_31_0_add0000_cy_12_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(11),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_12_rt_669,
      O => Madd_data_ex4_31_0_add0000_cy(12)
    );
  Madd_data_ex4_31_0_add0000_xor_12_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(11),
      LI => Madd_data_ex4_31_0_add0000_cy_12_rt_669,
      O => data_ex4_31_0_add0000(12)
    );
  Madd_data_ex4_31_0_add0000_cy_13_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(12),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_13_rt_671,
      O => Madd_data_ex4_31_0_add0000_cy(13)
    );
  Madd_data_ex4_31_0_add0000_xor_13_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(12),
      LI => Madd_data_ex4_31_0_add0000_cy_13_rt_671,
      O => data_ex4_31_0_add0000(13)
    );
  Madd_data_ex4_31_0_add0000_cy_14_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(13),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_14_rt_673,
      O => Madd_data_ex4_31_0_add0000_cy(14)
    );
  Madd_data_ex4_31_0_add0000_xor_14_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(13),
      LI => Madd_data_ex4_31_0_add0000_cy_14_rt_673,
      O => data_ex4_31_0_add0000(14)
    );
  Madd_data_ex4_31_0_add0000_cy_15_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(14),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_15_rt_675,
      O => Madd_data_ex4_31_0_add0000_cy(15)
    );
  Madd_data_ex4_31_0_add0000_xor_15_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(14),
      LI => Madd_data_ex4_31_0_add0000_cy_15_rt_675,
      O => data_ex4_31_0_add0000(15)
    );
  Madd_data_ex4_31_0_add0000_cy_16_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(15),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_16_rt_677,
      O => Madd_data_ex4_31_0_add0000_cy(16)
    );
  Madd_data_ex4_31_0_add0000_xor_16_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(15),
      LI => Madd_data_ex4_31_0_add0000_cy_16_rt_677,
      O => data_ex4_31_0_add0000(16)
    );
  Madd_data_ex4_31_0_add0000_cy_17_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(16),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_17_rt_679,
      O => Madd_data_ex4_31_0_add0000_cy(17)
    );
  Madd_data_ex4_31_0_add0000_xor_17_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(16),
      LI => Madd_data_ex4_31_0_add0000_cy_17_rt_679,
      O => data_ex4_31_0_add0000(17)
    );
  Madd_data_ex4_31_0_add0000_cy_18_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(17),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_18_rt_681,
      O => Madd_data_ex4_31_0_add0000_cy(18)
    );
  Madd_data_ex4_31_0_add0000_xor_18_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(17),
      LI => Madd_data_ex4_31_0_add0000_cy_18_rt_681,
      O => data_ex4_31_0_add0000(18)
    );
  Madd_data_ex4_31_0_add0000_cy_19_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(18),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_19_rt_683,
      O => Madd_data_ex4_31_0_add0000_cy(19)
    );
  Madd_data_ex4_31_0_add0000_xor_19_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(18),
      LI => Madd_data_ex4_31_0_add0000_cy_19_rt_683,
      O => data_ex4_31_0_add0000(19)
    );
  Madd_data_ex4_31_0_add0000_cy_20_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(19),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_20_rt_687,
      O => Madd_data_ex4_31_0_add0000_cy(20)
    );
  Madd_data_ex4_31_0_add0000_xor_20_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(19),
      LI => Madd_data_ex4_31_0_add0000_cy_20_rt_687,
      O => data_ex4_31_0_add0000(20)
    );
  Madd_data_ex4_31_0_add0000_cy_21_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(20),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_21_rt_689,
      O => Madd_data_ex4_31_0_add0000_cy(21)
    );
  Madd_data_ex4_31_0_add0000_xor_21_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(20),
      LI => Madd_data_ex4_31_0_add0000_cy_21_rt_689,
      O => data_ex4_31_0_add0000(21)
    );
  Madd_data_ex4_31_0_add0000_cy_22_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(21),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_22_rt_691,
      O => Madd_data_ex4_31_0_add0000_cy(22)
    );
  Madd_data_ex4_31_0_add0000_xor_22_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(21),
      LI => Madd_data_ex4_31_0_add0000_cy_22_rt_691,
      O => data_ex4_31_0_add0000(22)
    );
  Madd_data_ex4_31_0_add0000_cy_23_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(22),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_23_rt_693,
      O => Madd_data_ex4_31_0_add0000_cy(23)
    );
  Madd_data_ex4_31_0_add0000_xor_23_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(22),
      LI => Madd_data_ex4_31_0_add0000_cy_23_rt_693,
      O => data_ex4_31_0_add0000(23)
    );
  Madd_data_ex4_31_0_add0000_cy_24_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(23),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_24_rt_695,
      O => Madd_data_ex4_31_0_add0000_cy(24)
    );
  Madd_data_ex4_31_0_add0000_xor_24_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(23),
      LI => Madd_data_ex4_31_0_add0000_cy_24_rt_695,
      O => data_ex4_31_0_add0000(24)
    );
  Madd_data_ex4_31_0_add0000_cy_25_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(24),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_25_rt_697,
      O => Madd_data_ex4_31_0_add0000_cy(25)
    );
  Madd_data_ex4_31_0_add0000_xor_25_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(24),
      LI => Madd_data_ex4_31_0_add0000_cy_25_rt_697,
      O => data_ex4_31_0_add0000(25)
    );
  Madd_data_ex4_31_0_add0000_cy_26_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(25),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_26_rt_699,
      O => Madd_data_ex4_31_0_add0000_cy(26)
    );
  Madd_data_ex4_31_0_add0000_xor_26_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(25),
      LI => Madd_data_ex4_31_0_add0000_cy_26_rt_699,
      O => data_ex4_31_0_add0000(26)
    );
  Madd_data_ex4_31_0_add0000_cy_27_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(26),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_27_rt_701,
      O => Madd_data_ex4_31_0_add0000_cy(27)
    );
  Madd_data_ex4_31_0_add0000_xor_27_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(26),
      LI => Madd_data_ex4_31_0_add0000_cy_27_rt_701,
      O => data_ex4_31_0_add0000(27)
    );
  Madd_data_ex4_31_0_add0000_cy_28_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(27),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_28_rt_703,
      O => Madd_data_ex4_31_0_add0000_cy(28)
    );
  Madd_data_ex4_31_0_add0000_xor_28_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(27),
      LI => Madd_data_ex4_31_0_add0000_cy_28_rt_703,
      O => data_ex4_31_0_add0000(28)
    );
  Madd_data_ex4_31_0_add0000_cy_29_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(28),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_29_rt_705,
      O => Madd_data_ex4_31_0_add0000_cy(29)
    );
  Madd_data_ex4_31_0_add0000_xor_29_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(28),
      LI => Madd_data_ex4_31_0_add0000_cy_29_rt_705,
      O => data_ex4_31_0_add0000(29)
    );
  Madd_data_ex4_31_0_add0000_cy_30_Q : MUXCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(29),
      DI => N0,
      S => Madd_data_ex4_31_0_add0000_cy_30_rt_709,
      O => Madd_data_ex4_31_0_add0000_cy(30)
    );
  Madd_data_ex4_31_0_add0000_xor_30_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(29),
      LI => Madd_data_ex4_31_0_add0000_cy_30_rt_709,
      O => data_ex4_31_0_add0000(30)
    );
  Madd_data_ex4_31_0_add0000_xor_31_Q : XORCY
    port map (
      CI => Madd_data_ex4_31_0_add0000_cy(30),
      LI => Madd_data_ex4_31_0_add0000_xor_31_rt_725,
      O => data_ex4_31_0_add0000(31)
    );
  Msub_cnt1_eq_addsub0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => Msub_cnt1_eq_addsub0000_cy_0_rt_1011,
      O => Msub_cnt1_eq_addsub0000_cy(0)
    );
  Msub_cnt1_eq_addsub0000_xor_0_Q : XORCY
    port map (
      CI => N1,
      LI => Msub_cnt1_eq_addsub0000_cy_0_rt_1011,
      O => cnt1_eq_addsub0000(0)
    );
  Msub_cnt1_eq_addsub0000_cy_1_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(0),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(1),
      O => Msub_cnt1_eq_addsub0000_cy(1)
    );
  Msub_cnt1_eq_addsub0000_xor_1_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(0),
      LI => Msub_cnt1_eq_addsub0000_lut(1),
      O => cnt1_eq_addsub0000(1)
    );
  Msub_cnt1_eq_addsub0000_cy_2_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(1),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(2),
      O => Msub_cnt1_eq_addsub0000_cy(2)
    );
  Msub_cnt1_eq_addsub0000_xor_2_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(1),
      LI => Msub_cnt1_eq_addsub0000_lut(2),
      O => cnt1_eq_addsub0000(2)
    );
  Msub_cnt1_eq_addsub0000_cy_3_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(2),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(3),
      O => Msub_cnt1_eq_addsub0000_cy(3)
    );
  Msub_cnt1_eq_addsub0000_xor_3_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(2),
      LI => Msub_cnt1_eq_addsub0000_lut(3),
      O => cnt1_eq_addsub0000(3)
    );
  Msub_cnt1_eq_addsub0000_cy_4_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(3),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(4),
      O => Msub_cnt1_eq_addsub0000_cy(4)
    );
  Msub_cnt1_eq_addsub0000_xor_4_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(3),
      LI => Msub_cnt1_eq_addsub0000_lut(4),
      O => cnt1_eq_addsub0000(4)
    );
  Msub_cnt1_eq_addsub0000_cy_5_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(4),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(5),
      O => Msub_cnt1_eq_addsub0000_cy(5)
    );
  Msub_cnt1_eq_addsub0000_xor_5_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(4),
      LI => Msub_cnt1_eq_addsub0000_lut(5),
      O => cnt1_eq_addsub0000(5)
    );
  Msub_cnt1_eq_addsub0000_cy_6_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(5),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(6),
      O => Msub_cnt1_eq_addsub0000_cy(6)
    );
  Msub_cnt1_eq_addsub0000_xor_6_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(5),
      LI => Msub_cnt1_eq_addsub0000_lut(6),
      O => cnt1_eq_addsub0000(6)
    );
  Msub_cnt1_eq_addsub0000_cy_7_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(6),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(7),
      O => Msub_cnt1_eq_addsub0000_cy(7)
    );
  Msub_cnt1_eq_addsub0000_xor_7_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(6),
      LI => Msub_cnt1_eq_addsub0000_lut(7),
      O => cnt1_eq_addsub0000(7)
    );
  Msub_cnt1_eq_addsub0000_cy_8_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(7),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(8),
      O => Msub_cnt1_eq_addsub0000_cy(8)
    );
  Msub_cnt1_eq_addsub0000_xor_8_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(7),
      LI => Msub_cnt1_eq_addsub0000_lut(8),
      O => cnt1_eq_addsub0000(8)
    );
  Msub_cnt1_eq_addsub0000_cy_9_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(8),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(9),
      O => Msub_cnt1_eq_addsub0000_cy(9)
    );
  Msub_cnt1_eq_addsub0000_xor_9_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(8),
      LI => Msub_cnt1_eq_addsub0000_lut(9),
      O => cnt1_eq_addsub0000(9)
    );
  Msub_cnt1_eq_addsub0000_cy_10_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(9),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(10),
      O => Msub_cnt1_eq_addsub0000_cy(10)
    );
  Msub_cnt1_eq_addsub0000_xor_10_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(9),
      LI => Msub_cnt1_eq_addsub0000_lut(10),
      O => cnt1_eq_addsub0000(10)
    );
  Msub_cnt1_eq_addsub0000_cy_11_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(10),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(11),
      O => Msub_cnt1_eq_addsub0000_cy(11)
    );
  Msub_cnt1_eq_addsub0000_xor_11_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(10),
      LI => Msub_cnt1_eq_addsub0000_lut(11),
      O => cnt1_eq_addsub0000(11)
    );
  Msub_cnt1_eq_addsub0000_cy_12_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(11),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(12),
      O => Msub_cnt1_eq_addsub0000_cy(12)
    );
  Msub_cnt1_eq_addsub0000_xor_12_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(11),
      LI => Msub_cnt1_eq_addsub0000_lut(12),
      O => cnt1_eq_addsub0000(12)
    );
  Msub_cnt1_eq_addsub0000_cy_13_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(12),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(13),
      O => Msub_cnt1_eq_addsub0000_cy(13)
    );
  Msub_cnt1_eq_addsub0000_xor_13_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(12),
      LI => Msub_cnt1_eq_addsub0000_lut(13),
      O => cnt1_eq_addsub0000(13)
    );
  Msub_cnt1_eq_addsub0000_cy_14_Q : MUXCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(13),
      DI => N1,
      S => Msub_cnt1_eq_addsub0000_lut(14),
      O => Msub_cnt1_eq_addsub0000_cy(14)
    );
  Msub_cnt1_eq_addsub0000_xor_14_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(13),
      LI => Msub_cnt1_eq_addsub0000_lut(14),
      O => cnt1_eq_addsub0000(14)
    );
  Msub_cnt1_eq_addsub0000_xor_15_Q : XORCY
    port map (
      CI => Msub_cnt1_eq_addsub0000_cy(14),
      LI => Msub_cnt1_eq_addsub0000_lut(15),
      O => cnt1_eq_addsub0000(15)
    );
  Mcount_block_rd_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_block_rd_lut(0),
      O => Mcount_block_rd_cy(0)
    );
  Mcount_block_rd_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_block_rd_lut(0),
      O => Result(0)
    );
  Mcount_block_rd_cy_1_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(0),
      DI => N0,
      S => Mcount_block_rd_cy_1_rt_826,
      O => Mcount_block_rd_cy(1)
    );
  Mcount_block_rd_xor_1_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(0),
      LI => Mcount_block_rd_cy_1_rt_826,
      O => Result(1)
    );
  Mcount_block_rd_cy_2_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(1),
      DI => N0,
      S => Mcount_block_rd_cy_2_rt_848,
      O => Mcount_block_rd_cy(2)
    );
  Mcount_block_rd_xor_2_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(1),
      LI => Mcount_block_rd_cy_2_rt_848,
      O => Result(2)
    );
  Mcount_block_rd_cy_3_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(2),
      DI => N0,
      S => Mcount_block_rd_cy_3_rt_852,
      O => Mcount_block_rd_cy(3)
    );
  Mcount_block_rd_xor_3_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(2),
      LI => Mcount_block_rd_cy_3_rt_852,
      O => Result(3)
    );
  Mcount_block_rd_cy_4_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(3),
      DI => N0,
      S => Mcount_block_rd_cy_4_rt_854,
      O => Mcount_block_rd_cy(4)
    );
  Mcount_block_rd_xor_4_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(3),
      LI => Mcount_block_rd_cy_4_rt_854,
      O => Result(4)
    );
  Mcount_block_rd_cy_5_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(4),
      DI => N0,
      S => Mcount_block_rd_cy_5_rt_856,
      O => Mcount_block_rd_cy(5)
    );
  Mcount_block_rd_xor_5_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(4),
      LI => Mcount_block_rd_cy_5_rt_856,
      O => Result(5)
    );
  Mcount_block_rd_cy_6_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(5),
      DI => N0,
      S => Mcount_block_rd_cy_6_rt_858,
      O => Mcount_block_rd_cy(6)
    );
  Mcount_block_rd_xor_6_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(5),
      LI => Mcount_block_rd_cy_6_rt_858,
      O => Result(6)
    );
  Mcount_block_rd_cy_7_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(6),
      DI => N0,
      S => Mcount_block_rd_cy_7_rt_860,
      O => Mcount_block_rd_cy(7)
    );
  Mcount_block_rd_xor_7_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(6),
      LI => Mcount_block_rd_cy_7_rt_860,
      O => Result(7)
    );
  Mcount_block_rd_cy_8_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(7),
      DI => N0,
      S => Mcount_block_rd_cy_8_rt_862,
      O => Mcount_block_rd_cy(8)
    );
  Mcount_block_rd_xor_8_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(7),
      LI => Mcount_block_rd_cy_8_rt_862,
      O => Result(8)
    );
  Mcount_block_rd_cy_9_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(8),
      DI => N0,
      S => Mcount_block_rd_cy_9_rt_864,
      O => Mcount_block_rd_cy(9)
    );
  Mcount_block_rd_xor_9_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(8),
      LI => Mcount_block_rd_cy_9_rt_864,
      O => Result(9)
    );
  Mcount_block_rd_cy_10_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(9),
      DI => N0,
      S => Mcount_block_rd_cy_10_rt_806,
      O => Mcount_block_rd_cy(10)
    );
  Mcount_block_rd_xor_10_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(9),
      LI => Mcount_block_rd_cy_10_rt_806,
      O => Result(10)
    );
  Mcount_block_rd_cy_11_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(10),
      DI => N0,
      S => Mcount_block_rd_cy_11_rt_808,
      O => Mcount_block_rd_cy(11)
    );
  Mcount_block_rd_xor_11_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(10),
      LI => Mcount_block_rd_cy_11_rt_808,
      O => Result(11)
    );
  Mcount_block_rd_cy_12_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(11),
      DI => N0,
      S => Mcount_block_rd_cy_12_rt_810,
      O => Mcount_block_rd_cy(12)
    );
  Mcount_block_rd_xor_12_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(11),
      LI => Mcount_block_rd_cy_12_rt_810,
      O => Result(12)
    );
  Mcount_block_rd_cy_13_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(12),
      DI => N0,
      S => Mcount_block_rd_cy_13_rt_812,
      O => Mcount_block_rd_cy(13)
    );
  Mcount_block_rd_xor_13_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(12),
      LI => Mcount_block_rd_cy_13_rt_812,
      O => Result(13)
    );
  Mcount_block_rd_cy_14_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(13),
      DI => N0,
      S => Mcount_block_rd_cy_14_rt_814,
      O => Mcount_block_rd_cy(14)
    );
  Mcount_block_rd_xor_14_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(13),
      LI => Mcount_block_rd_cy_14_rt_814,
      O => Result(14)
    );
  Mcount_block_rd_cy_15_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(14),
      DI => N0,
      S => Mcount_block_rd_cy_15_rt_816,
      O => Mcount_block_rd_cy(15)
    );
  Mcount_block_rd_xor_15_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(14),
      LI => Mcount_block_rd_cy_15_rt_816,
      O => Result(15)
    );
  Mcount_block_rd_cy_16_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(15),
      DI => N0,
      S => Mcount_block_rd_cy_16_rt_818,
      O => Mcount_block_rd_cy(16)
    );
  Mcount_block_rd_xor_16_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(15),
      LI => Mcount_block_rd_cy_16_rt_818,
      O => Result(16)
    );
  Mcount_block_rd_cy_17_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(16),
      DI => N0,
      S => Mcount_block_rd_cy_17_rt_820,
      O => Mcount_block_rd_cy(17)
    );
  Mcount_block_rd_xor_17_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(16),
      LI => Mcount_block_rd_cy_17_rt_820,
      O => Result(17)
    );
  Mcount_block_rd_cy_18_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(17),
      DI => N0,
      S => Mcount_block_rd_cy_18_rt_822,
      O => Mcount_block_rd_cy(18)
    );
  Mcount_block_rd_xor_18_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(17),
      LI => Mcount_block_rd_cy_18_rt_822,
      O => Result(18)
    );
  Mcount_block_rd_cy_19_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(18),
      DI => N0,
      S => Mcount_block_rd_cy_19_rt_824,
      O => Mcount_block_rd_cy(19)
    );
  Mcount_block_rd_xor_19_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(18),
      LI => Mcount_block_rd_cy_19_rt_824,
      O => Result(19)
    );
  Mcount_block_rd_cy_20_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(19),
      DI => N0,
      S => Mcount_block_rd_cy_20_rt_828,
      O => Mcount_block_rd_cy(20)
    );
  Mcount_block_rd_xor_20_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(19),
      LI => Mcount_block_rd_cy_20_rt_828,
      O => Result(20)
    );
  Mcount_block_rd_cy_21_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(20),
      DI => N0,
      S => Mcount_block_rd_cy_21_rt_830,
      O => Mcount_block_rd_cy(21)
    );
  Mcount_block_rd_xor_21_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(20),
      LI => Mcount_block_rd_cy_21_rt_830,
      O => Result(21)
    );
  Mcount_block_rd_cy_22_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(21),
      DI => N0,
      S => Mcount_block_rd_cy_22_rt_832,
      O => Mcount_block_rd_cy(22)
    );
  Mcount_block_rd_xor_22_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(21),
      LI => Mcount_block_rd_cy_22_rt_832,
      O => Result(22)
    );
  Mcount_block_rd_cy_23_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(22),
      DI => N0,
      S => Mcount_block_rd_cy_23_rt_834,
      O => Mcount_block_rd_cy(23)
    );
  Mcount_block_rd_xor_23_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(22),
      LI => Mcount_block_rd_cy_23_rt_834,
      O => Result(23)
    );
  Mcount_block_rd_cy_24_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(23),
      DI => N0,
      S => Mcount_block_rd_cy_24_rt_836,
      O => Mcount_block_rd_cy(24)
    );
  Mcount_block_rd_xor_24_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(23),
      LI => Mcount_block_rd_cy_24_rt_836,
      O => Result(24)
    );
  Mcount_block_rd_cy_25_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(24),
      DI => N0,
      S => Mcount_block_rd_cy_25_rt_838,
      O => Mcount_block_rd_cy(25)
    );
  Mcount_block_rd_xor_25_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(24),
      LI => Mcount_block_rd_cy_25_rt_838,
      O => Result(25)
    );
  Mcount_block_rd_cy_26_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(25),
      DI => N0,
      S => Mcount_block_rd_cy_26_rt_840,
      O => Mcount_block_rd_cy(26)
    );
  Mcount_block_rd_xor_26_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(25),
      LI => Mcount_block_rd_cy_26_rt_840,
      O => Result(26)
    );
  Mcount_block_rd_cy_27_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(26),
      DI => N0,
      S => Mcount_block_rd_cy_27_rt_842,
      O => Mcount_block_rd_cy(27)
    );
  Mcount_block_rd_xor_27_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(26),
      LI => Mcount_block_rd_cy_27_rt_842,
      O => Result(27)
    );
  Mcount_block_rd_cy_28_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(27),
      DI => N0,
      S => Mcount_block_rd_cy_28_rt_844,
      O => Mcount_block_rd_cy(28)
    );
  Mcount_block_rd_xor_28_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(27),
      LI => Mcount_block_rd_cy_28_rt_844,
      O => Result(28)
    );
  Mcount_block_rd_cy_29_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(28),
      DI => N0,
      S => Mcount_block_rd_cy_29_rt_846,
      O => Mcount_block_rd_cy(29)
    );
  Mcount_block_rd_xor_29_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(28),
      LI => Mcount_block_rd_cy_29_rt_846,
      O => Result(29)
    );
  Mcount_block_rd_cy_30_Q : MUXCY
    port map (
      CI => Mcount_block_rd_cy(29),
      DI => N0,
      S => Mcount_block_rd_cy_30_rt_850,
      O => Mcount_block_rd_cy(30)
    );
  Mcount_block_rd_xor_30_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(29),
      LI => Mcount_block_rd_cy_30_rt_850,
      O => Result(30)
    );
  Mcount_block_rd_xor_31_Q : XORCY
    port map (
      CI => Mcount_block_rd_cy(30),
      LI => Mcount_block_rd_xor_31_rt_866,
      O => Result(31)
    );
  Mcount_cnt1_cy_0_Q : MUXCY
    port map (
      CI => N0,
      DI => N1,
      S => Mcount_cnt1_lut(0),
      O => Mcount_cnt1_cy(0)
    );
  Mcount_cnt1_xor_0_Q : XORCY
    port map (
      CI => N0,
      LI => Mcount_cnt1_lut(0),
      O => Result_0_1
    );
  Mcount_cnt1_cy_1_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(0),
      DI => N0,
      S => Mcount_cnt1_cy_1_rt_889,
      O => Mcount_cnt1_cy(1)
    );
  Mcount_cnt1_xor_1_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(0),
      LI => Mcount_cnt1_cy_1_rt_889,
      O => Result_1_1
    );
  Mcount_cnt1_cy_2_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(1),
      DI => N0,
      S => Mcount_cnt1_cy_2_rt_899,
      O => Mcount_cnt1_cy(2)
    );
  Mcount_cnt1_xor_2_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(1),
      LI => Mcount_cnt1_cy_2_rt_899,
      O => Result_2_1
    );
  Mcount_cnt1_cy_3_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(2),
      DI => N0,
      S => Mcount_cnt1_cy_3_rt_901,
      O => Mcount_cnt1_cy(3)
    );
  Mcount_cnt1_xor_3_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(2),
      LI => Mcount_cnt1_cy_3_rt_901,
      O => Result_3_1
    );
  Mcount_cnt1_cy_4_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(3),
      DI => N0,
      S => Mcount_cnt1_cy_4_rt_903,
      O => Mcount_cnt1_cy(4)
    );
  Mcount_cnt1_xor_4_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(3),
      LI => Mcount_cnt1_cy_4_rt_903,
      O => Result_4_1
    );
  Mcount_cnt1_cy_5_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(4),
      DI => N0,
      S => Mcount_cnt1_cy_5_rt_905,
      O => Mcount_cnt1_cy(5)
    );
  Mcount_cnt1_xor_5_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(4),
      LI => Mcount_cnt1_cy_5_rt_905,
      O => Result_5_1
    );
  Mcount_cnt1_cy_6_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(5),
      DI => N0,
      S => Mcount_cnt1_cy_6_rt_907,
      O => Mcount_cnt1_cy(6)
    );
  Mcount_cnt1_xor_6_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(5),
      LI => Mcount_cnt1_cy_6_rt_907,
      O => Result_6_1
    );
  Mcount_cnt1_cy_7_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(6),
      DI => N0,
      S => Mcount_cnt1_cy_7_rt_909,
      O => Mcount_cnt1_cy(7)
    );
  Mcount_cnt1_xor_7_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(6),
      LI => Mcount_cnt1_cy_7_rt_909,
      O => Result_7_1
    );
  Mcount_cnt1_cy_8_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(7),
      DI => N0,
      S => Mcount_cnt1_cy_8_rt_911,
      O => Mcount_cnt1_cy(8)
    );
  Mcount_cnt1_xor_8_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(7),
      LI => Mcount_cnt1_cy_8_rt_911,
      O => Result_8_1
    );
  Mcount_cnt1_cy_9_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(8),
      DI => N0,
      S => Mcount_cnt1_cy_9_rt_913,
      O => Mcount_cnt1_cy(9)
    );
  Mcount_cnt1_xor_9_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(8),
      LI => Mcount_cnt1_cy_9_rt_913,
      O => Result_9_1
    );
  Mcount_cnt1_cy_10_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(9),
      DI => N0,
      S => Mcount_cnt1_cy_10_rt_869,
      O => Mcount_cnt1_cy(10)
    );
  Mcount_cnt1_xor_10_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(9),
      LI => Mcount_cnt1_cy_10_rt_869,
      O => Result_10_1
    );
  Mcount_cnt1_cy_11_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(10),
      DI => N0,
      S => Mcount_cnt1_cy_11_rt_871,
      O => Mcount_cnt1_cy(11)
    );
  Mcount_cnt1_xor_11_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(10),
      LI => Mcount_cnt1_cy_11_rt_871,
      O => Result_11_1
    );
  Mcount_cnt1_cy_12_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(11),
      DI => N0,
      S => Mcount_cnt1_cy_12_rt_873,
      O => Mcount_cnt1_cy(12)
    );
  Mcount_cnt1_xor_12_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(11),
      LI => Mcount_cnt1_cy_12_rt_873,
      O => Result_12_1
    );
  Mcount_cnt1_cy_13_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(12),
      DI => N0,
      S => Mcount_cnt1_cy_13_rt_875,
      O => Mcount_cnt1_cy(13)
    );
  Mcount_cnt1_xor_13_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(12),
      LI => Mcount_cnt1_cy_13_rt_875,
      O => Result_13_1
    );
  Mcount_cnt1_cy_14_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(13),
      DI => N0,
      S => Mcount_cnt1_cy_14_rt_877,
      O => Mcount_cnt1_cy(14)
    );
  Mcount_cnt1_xor_14_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(13),
      LI => Mcount_cnt1_cy_14_rt_877,
      O => Result_14_1
    );
  Mcount_cnt1_cy_15_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(14),
      DI => N0,
      S => Mcount_cnt1_cy_15_rt_879,
      O => Mcount_cnt1_cy(15)
    );
  Mcount_cnt1_xor_15_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(14),
      LI => Mcount_cnt1_cy_15_rt_879,
      O => Result_15_1
    );
  Mcount_cnt1_cy_16_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(15),
      DI => N0,
      S => Mcount_cnt1_cy_16_rt_881,
      O => Mcount_cnt1_cy(16)
    );
  Mcount_cnt1_xor_16_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(15),
      LI => Mcount_cnt1_cy_16_rt_881,
      O => Result_16_1
    );
  Mcount_cnt1_cy_17_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(16),
      DI => N0,
      S => Mcount_cnt1_cy_17_rt_883,
      O => Mcount_cnt1_cy(17)
    );
  Mcount_cnt1_xor_17_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(16),
      LI => Mcount_cnt1_cy_17_rt_883,
      O => Result_17_1
    );
  Mcount_cnt1_cy_18_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(17),
      DI => N0,
      S => Mcount_cnt1_cy_18_rt_885,
      O => Mcount_cnt1_cy(18)
    );
  Mcount_cnt1_xor_18_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(17),
      LI => Mcount_cnt1_cy_18_rt_885,
      O => Result_18_1
    );
  Mcount_cnt1_cy_19_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(18),
      DI => N0,
      S => Mcount_cnt1_cy_19_rt_887,
      O => Mcount_cnt1_cy(19)
    );
  Mcount_cnt1_xor_19_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(18),
      LI => Mcount_cnt1_cy_19_rt_887,
      O => Result_19_1
    );
  Mcount_cnt1_cy_20_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(19),
      DI => N0,
      S => Mcount_cnt1_cy_20_rt_891,
      O => Mcount_cnt1_cy(20)
    );
  Mcount_cnt1_xor_20_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(19),
      LI => Mcount_cnt1_cy_20_rt_891,
      O => Result_20_1
    );
  Mcount_cnt1_cy_21_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(20),
      DI => N0,
      S => Mcount_cnt1_cy_21_rt_893,
      O => Mcount_cnt1_cy(21)
    );
  Mcount_cnt1_xor_21_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(20),
      LI => Mcount_cnt1_cy_21_rt_893,
      O => Result_21_1
    );
  Mcount_cnt1_cy_22_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(21),
      DI => N0,
      S => Mcount_cnt1_cy_22_rt_895,
      O => Mcount_cnt1_cy(22)
    );
  Mcount_cnt1_xor_22_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(21),
      LI => Mcount_cnt1_cy_22_rt_895,
      O => Result_22_1
    );
  Mcount_cnt1_cy_23_Q : MUXCY
    port map (
      CI => Mcount_cnt1_cy(22),
      DI => N0,
      S => Mcount_cnt1_cy_23_rt_897,
      O => Mcount_cnt1_cy(23)
    );
  Mcount_cnt1_xor_23_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(22),
      LI => Mcount_cnt1_cy_23_rt_897,
      O => Result_23_1
    );
  Mcount_cnt1_xor_24_Q : XORCY
    port map (
      CI => Mcount_cnt1_cy(23),
      LI => Mcount_cnt1_xor_24_rt_915,
      O => Result_24_1
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_0_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(11),
      I1 => cnt1(10),
      I2 => cnt1(9),
      I3 => cnt1_eq_addsub0000(0),
      I4 => cnt1_eq_addsub0000(1),
      I5 => cnt1_eq_addsub0000(2),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(0)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_0_Q : MUXCY
    port map (
      CI => N1,
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(0),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(0)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_1_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(14),
      I1 => cnt1(13),
      I2 => cnt1(12),
      I3 => cnt1_eq_addsub0000(3),
      I4 => cnt1_eq_addsub0000(4),
      I5 => cnt1_eq_addsub0000(5),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(1)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_1_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(0),
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(1),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(1)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_2_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(17),
      I1 => cnt1(16),
      I2 => cnt1(15),
      I3 => cnt1_eq_addsub0000(6),
      I4 => cnt1_eq_addsub0000(7),
      I5 => cnt1_eq_addsub0000(8),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(2)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_2_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(1),
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(2),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(2)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_3_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(20),
      I1 => cnt1(19),
      I2 => cnt1(18),
      I3 => cnt1_eq_addsub0000(9),
      I4 => cnt1_eq_addsub0000(10),
      I5 => cnt1_eq_addsub0000(11),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(3)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_3_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(2),
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(3),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(3)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_4_Q : LUT6
    generic map(
      INIT => X"8008200240041001"
    )
    port map (
      I0 => cnt1(23),
      I1 => cnt1(22),
      I2 => cnt1(21),
      I3 => cnt1_eq_addsub0000(12),
      I4 => cnt1_eq_addsub0000(13),
      I5 => cnt1_eq_addsub0000(14),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(4)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_4_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(3),
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(4),
      O => Mcompar_cnt1_eq_cmp_eq0000_cy(4)
    );
  Mcompar_cnt1_eq_cmp_eq0000_lut_5_Q : LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      I0 => cnt1(24),
      I1 => cnt1_eq_addsub0000(15),
      O => Mcompar_cnt1_eq_cmp_eq0000_lut(5)
    );
  Mcompar_cnt1_eq_cmp_eq0000_cy_5_Q : MUXCY
    port map (
      CI => Mcompar_cnt1_eq_cmp_eq0000_cy(4),
      DI => N0,
      S => Mcompar_cnt1_eq_cmp_eq0000_lut(5),
      O => cnt1_eq_cmp_eq0000
    );
  stp_FSM_FFd1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => di_clk,
      D => stp_FSM_FFd1_In,
      R => rst_inv,
      Q => stp_FSM_FFd1_2277
    );
  stp_FSM_FFd2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => di_clk,
      D => stp_FSM_FFd2_In,
      R => rst_inv,
      Q => stp_FSM_FFd2_2279
    );
  stp_FSM_FFd3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => di_clk,
      D => stp_FSM_FFd3_In_2282,
      R => rst_inv,
      Q => stp_FSM_FFd3_2281
    );
  stp_FSM_FFd4 : FDS
    generic map(
      INIT => '1'
    )
    port map (
      C => di_clk,
      D => stp_FSM_FFd4_In,
      S => rst_inv,
      Q => stp_FSM_FFd4_2283
    );
  data_en_mux00011 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => di_rdy_2272,
      I1 => stp_FSM_FFd2_2279,
      I2 => stp_FSM_FFd3_2281,
      O => data_en_mux0001
    );
  Mcount_block_mode_xor_0_11 : LUT3
    generic map(
      INIT => X"B1"
    )
    port map (
      I0 => test_gen_ctrl(7),
      I1 => block_mode(0),
      I2 => test_gen_ctrl(8),
      O => Mcount_block_mode
    );
  stp_FSM_FFd2_In1 : LUT4
    generic map(
      INIT => X"F020"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_ctrl(6),
      I2 => test_gen_ctrl(5),
      I3 => stp_FSM_FFd2_2279,
      O => stp_FSM_FFd2_In
    );
  Mxor_data_ex5_0_xor0000_xo_0_1 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => data_ex5(59),
      I1 => data_ex5(60),
      I2 => data_ex5(62),
      I3 => data_ex5(63),
      O => data_ex5_0_xor0000
    );
  Mcount_block_mode_xor_1_11 : LUT4
    generic map(
      INIT => X"BE14"
    )
    port map (
      I0 => test_gen_ctrl(7),
      I1 => block_mode(0),
      I2 => block_mode(1),
      I3 => test_gen_ctrl(9),
      O => Mcount_block_mode1
    );
  Mcount_block_mode_xor_2_11 : LUT5
    generic map(
      INIT => X"BEEE1444"
    )
    port map (
      I0 => test_gen_ctrl(7),
      I1 => block_mode(2),
      I2 => block_mode(0),
      I3 => block_mode(1),
      I4 => test_gen_ctrl(10),
      O => Mcount_block_mode2
    );
  Mcount_block_mode_xor_3_11 : LUT6
    generic map(
      INIT => X"BEEEEEEE14444444"
    )
    port map (
      I0 => test_gen_ctrl(7),
      I1 => block_mode(3),
      I2 => block_mode(0),
      I3 => block_mode(1),
      I4 => block_mode(2),
      I5 => test_gen_ctrl(11),
      O => Mcount_block_mode3
    );
  rst_inv1951 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => test_gen_ctrl(0),
      O => rst_inv
    );
  di_rdy_or0000_inv1 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => di_flag_paf,
      I1 => test_gen_ctrl(12),
      O => di_rdy_or0000_inv
    );
  data_ex2_0_not000121 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => data_en_1321,
      I1 => reset,
      I2 => test_gen_ctrl(0),
      O => data_expect_3_not0001
    );
  data_ex1_36_not0001_SW0 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => test_gen_ctrl(0),
      O => N01
    );
  data_ex1_36_not0001 : LUT6
    generic map(
      INIT => X"080808080A080808"
    )
    port map (
      I0 => data_en_1321,
      I1 => cnt1_z_1320,
      I2 => N01,
      I3 => cnt1(0),
      I4 => N80,
      I5 => block_mode(2),
      O => data_ex1_36_not0001_1513
    );
  block_rd_and00001 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => data_en_1321,
      I1 => cnt1_eq_1300,
      O => block_rd_and0000
    );
  data_ex4_32_not00016 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => data_ex4(19),
      I1 => data_ex4(1),
      I2 => data_ex4(0),
      I3 => data_ex4(10),
      O => data_ex4_32_not00016_1904
    );
  data_ex4_32_not000123 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(18),
      I1 => data_ex4(17),
      I2 => data_ex4(16),
      I3 => data_ex4(15),
      I4 => data_ex4_32_not00016_1904,
      I5 => data_ex4_10_not0001,
      O => data_ex4_32_not000123_1901
    );
  data_ex4_32_not000137 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(28),
      I1 => data_ex4(29),
      I2 => data_ex4(2),
      I3 => data_ex4(30),
      I4 => data_ex4(20),
      I5 => data_ex4(21),
      O => data_ex4_32_not000137_1902
    );
  data_ex4_32_not000148 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(11),
      I1 => data_ex4(12),
      I2 => data_ex4(13),
      I3 => data_ex4(14),
      I4 => data_ex4(26),
      I5 => data_ex4(27),
      O => data_ex4_32_not000148_1903
    );
  data_ex4_32_not000170 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(4),
      I1 => data_ex4(5),
      I2 => data_ex4(6),
      I3 => data_ex4(7),
      I4 => data_ex4(8),
      I5 => data_ex4(9),
      O => data_ex4_32_not000170_1905
    );
  data_ex4_32_not000181 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => data_ex4(22),
      I1 => data_ex4(23),
      I2 => data_ex4(24),
      I3 => data_ex4(25),
      I4 => data_ex4(31),
      I5 => data_ex4(3),
      O => data_ex4_32_not000181_1906
    );
  block_mode_or0000_SW0 : LUT3
    generic map(
      INIT => X"F7"
    )
    port map (
      I0 => cnt1_eq_1300,
      I1 => block_mode(0),
      I2 => test_gen_ctrl(7),
      O => N2
    );
  block_mode_or0000 : LUT6
    generic map(
      INIT => X"FFFFFFFF5555D555"
    )
    port map (
      I0 => reset,
      I1 => block_mode(3),
      I2 => data_en_1321,
      I3 => N61,
      I4 => N2,
      I5 => test_gen_ctrl(0),
      O => block_mode_or0000_1241
    );
  xcnt2_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd2_2279,
      I1 => stp_FSM_FFd4_2283,
      I2 => stp_FSM_FFd3_2281,
      O => xcnt2_or0000
    );
  xcnt1_or00001 : LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      I0 => stp_FSM_FFd1_2277,
      I1 => stp_FSM_FFd4_2283,
      I2 => stp_FSM_FFd2_2279,
      O => xcnt1_or0000
    );
  data_ex4_32_not0001112 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(1),
      O => N80
    );
  data_ex2_0_not0001111 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => block_mode(1),
      O => data_ex3_and0000
    );
  stp_FSM_FFd1_In1 : LUT5
    generic map(
      INIT => X"A0A80088"
    )
    port map (
      I0 => test_gen_ctrl(5),
      I1 => stp_FSM_FFd1_2277,
      I2 => stp_FSM_FFd3_2281,
      I3 => xcnt2_z,
      I4 => xcnt1_z,
      O => stp_FSM_FFd1_In
    );
  data_expect_8_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(8),
      I1 => data_ex5(8),
      I2 => data_ex0(8),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_8_mux000031_2265
    );
  data_expect_5_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(5),
      I1 => data_ex5(5),
      I2 => data_ex0(5),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_5_mux000031_2240
    );
  data_expect_31_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(31),
      I1 => data_ex5(31),
      I2 => data_ex0(31),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_31_mux000031_2117
    );
  data_expect_29_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(29),
      I1 => data_ex5(29),
      I2 => data_ex0(29),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_29_mux000031_2108
    );
  data_expect_26_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(26),
      I1 => data_ex5(26),
      I2 => data_ex0(26),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_26_mux000031_2099
    );
  data_expect_24_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(24),
      I1 => data_ex5(24),
      I2 => data_ex0(24),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_24_mux000031_2093
    );
  data_expect_23_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(23),
      I1 => data_ex5(23),
      I2 => data_ex0(23),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_23_mux000031_2090
    );
  data_expect_21_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(21),
      I1 => data_ex5(21),
      I2 => data_ex0(21),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_21_mux000031_2084
    );
  data_expect_1_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(1),
      I1 => data_ex5(1),
      I2 => data_ex0(1),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_1_mux000031_2077
    );
  data_expect_18_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(18),
      I1 => data_ex5(18),
      I2 => data_ex0(18),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_18_mux000031_2072
    );
  data_expect_16_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(16),
      I1 => data_ex5(16),
      I2 => data_ex0(16),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_16_mux000031_2066
    );
  data_expect_0_mux000031 : LUT6
    generic map(
      INIT => X"FFCCFFF0FFAAFF00"
    )
    port map (
      I0 => NlwRenamedSig_OI_data_expect(0),
      I1 => data_ex5(0),
      I2 => data_ex0(0),
      I3 => cnt1_z_1320,
      I4 => block_mode(3),
      I5 => N61,
      O => data_expect_0_mux000031_2044
    );
  block_mode_or000011 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => block_mode(1),
      I1 => block_mode(2),
      O => N61
    );
  data_expect_9_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(9),
      I1 => data_ex2(9),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_9_mux000099_2268,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_9_mux0000
    );
  data_expect_7_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(7),
      I1 => data_ex2(7),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_7_mux000099_2262,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_7_mux0000
    );
  data_expect_6_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(6),
      I1 => data_ex2(6),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_6_mux000099_2259,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_6_mux0000
    );
  data_expect_4_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(4),
      I1 => data_ex2(4),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_4_mux000099_2197,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_4_mux0000
    );
  data_expect_3_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(3),
      I1 => data_ex2(3),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_3_mux000099_2153,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_3_mux0000
    );
  data_expect_30_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(30),
      I1 => data_ex2(30),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_30_mux000099_2114,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_30_mux0000
    );
  data_expect_2_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(2),
      I1 => data_ex2(2),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_2_mux000099_2110,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_2_mux0000
    );
  data_expect_28_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(28),
      I1 => data_ex2(28),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_28_mux000099_2105,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_28_mux0000
    );
  data_expect_27_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(27),
      I1 => data_ex2(27),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_27_mux000099_2102,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_27_mux0000
    );
  data_expect_25_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(25),
      I1 => data_ex2(25),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_25_mux000099_2096,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_25_mux0000
    );
  data_expect_22_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(22),
      I1 => data_ex2(22),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_22_mux000099_2087,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_22_mux0000
    );
  data_expect_20_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(20),
      I1 => data_ex2(20),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_20_mux000099_2081,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_20_mux0000
    );
  data_expect_19_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(19),
      I1 => data_ex2(19),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_19_mux000099_2075,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_19_mux0000
    );
  data_expect_17_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(17),
      I1 => data_ex2(17),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_17_mux000099_2069,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_17_mux0000
    );
  data_expect_15_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(15),
      I1 => data_ex2(15),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_15_mux000099_2063,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_15_mux0000
    );
  data_expect_14_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(14),
      I1 => data_ex2(14),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_14_mux000099_2060,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_14_mux0000
    );
  data_expect_13_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(13),
      I1 => data_ex2(13),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_13_mux000099_2057,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_13_mux0000
    );
  data_expect_12_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(12),
      I1 => data_ex2(12),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_12_mux000099_2054,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_12_mux0000
    );
  data_expect_11_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(11),
      I1 => data_ex2(11),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_11_mux000099_2051,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_11_mux0000
    );
  data_expect_10_mux0000140 : LUT6
    generic map(
      INIT => X"0F0F0C000F0F0A00"
    )
    port map (
      I0 => data_ex3(10),
      I1 => data_ex2(10),
      I2 => cnt1_z_1320,
      I3 => data_ex3_and0000,
      I4 => data_expect_10_mux000099_2048,
      I5 => data_expect_3_cmp_eq0006,
      O => data_expect_10_mux0000
    );
  xcnt2_z_cmp_eq000034 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => xcnt2(1),
      I1 => xcnt2(4),
      I2 => xcnt2(3),
      I3 => xcnt2(2),
      I4 => xcnt2(0),
      I5 => xcnt2(10),
      O => xcnt2_z_cmp_eq000034_2379
    );
  xcnt2_z_cmp_eq000070 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => xcnt2(8),
      I1 => xcnt2(9),
      I2 => xcnt2(7),
      I3 => xcnt2(6),
      I4 => xcnt2(5),
      I5 => xcnt2(15),
      O => xcnt2_z_cmp_eq000070_2380
    );
  cnt1_eq_and0000_SW0 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => cnt1(5),
      I1 => cnt1(4),
      I2 => cnt1(3),
      I3 => cnt1(2),
      I4 => cnt1(8),
      O => N4
    );
  cnt1_eq_and0000 : LUT6
    generic map(
      INIT => X"0080000000000000"
    )
    port map (
      I0 => cnt1(6),
      I1 => cnt1(1),
      I2 => cnt1(7),
      I3 => cnt1(0),
      I4 => N4,
      I5 => cnt1_eq_cmp_eq0000,
      O => cnt1_eq_and0000_1317
    );
  xcnt1_z_cmp_eq000070 : LUT6
    generic map(
      INIT => X"0000000000000001"
    )
    port map (
      I0 => xcnt1(8),
      I1 => xcnt1(9),
      I2 => xcnt1(7),
      I3 => xcnt1(6),
      I4 => xcnt1(5),
      I5 => xcnt1(15),
      O => xcnt1_z_cmp_eq000070_2360
    );
  data_expect_63_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(63),
      I1 => data_ex2(63),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_63_mux0000114_2256
    );
  data_expect_62_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(62),
      I1 => data_ex2(62),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_62_mux0000114_2252
    );
  data_expect_61_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(61),
      I1 => data_ex2(61),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_61_mux0000114_2248
    );
  data_expect_60_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(60),
      I1 => data_ex2(60),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_60_mux0000114_2244
    );
  data_expect_59_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(59),
      I1 => data_ex2(59),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_59_mux0000114_2237
    );
  data_expect_58_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(58),
      I1 => data_ex2(58),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_58_mux0000114_2233
    );
  data_expect_57_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(57),
      I1 => data_ex2(57),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_57_mux0000114_2229
    );
  data_expect_56_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(56),
      I1 => data_ex2(56),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_56_mux0000114_2225
    );
  data_expect_55_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(55),
      I1 => data_ex2(55),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_55_mux0000114_2221
    );
  data_expect_54_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(54),
      I1 => data_ex2(54),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_54_mux0000114_2217
    );
  data_expect_53_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(53),
      I1 => data_ex2(53),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_53_mux0000114_2213
    );
  data_expect_52_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(52),
      I1 => data_ex2(52),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_52_mux0000114_2209
    );
  data_expect_51_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(51),
      I1 => data_ex2(51),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_51_mux0000114_2205
    );
  data_expect_50_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(50),
      I1 => data_ex2(50),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_50_mux0000114_2201
    );
  data_expect_49_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(49),
      I1 => data_ex2(49),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_49_mux0000114_2194
    );
  data_expect_48_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(48),
      I1 => data_ex2(48),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_48_mux0000114_2190
    );
  data_expect_47_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(47),
      I1 => data_ex2(47),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_47_mux0000114_2186
    );
  data_expect_46_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(46),
      I1 => data_ex2(46),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_46_mux0000114_2182
    );
  data_expect_45_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(45),
      I1 => data_ex2(45),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_45_mux0000114_2178
    );
  data_expect_44_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(44),
      I1 => data_ex2(44),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_44_mux0000114_2174
    );
  data_expect_43_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(43),
      I1 => data_ex2(43),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_43_mux0000114_2170
    );
  data_expect_42_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(42),
      I1 => data_ex2(42),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_42_mux0000114_2166
    );
  data_expect_41_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(41),
      I1 => data_ex2(41),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_41_mux0000114_2162
    );
  data_expect_40_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(40),
      I1 => data_ex2(40),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_40_mux0000114_2158
    );
  data_expect_39_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(39),
      I1 => data_ex2(39),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_39_mux0000114_2148
    );
  data_expect_38_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(38),
      I1 => data_ex2(38),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_38_mux0000114_2144
    );
  data_expect_37_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(37),
      I1 => data_ex2(37),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_37_mux0000114_2140
    );
  data_expect_36_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(36),
      I1 => data_ex2(36),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_36_mux0000114_2136
    );
  data_expect_35_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(35),
      I1 => data_ex2(35),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_35_mux0000114_2132
    );
  data_expect_34_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(34),
      I1 => data_ex2(34),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_34_mux0000114_2128
    );
  data_expect_33_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(33),
      I1 => data_ex2(33),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_33_mux0000114_2124
    );
  data_expect_32_mux0000114 : LUT3
    generic map(
      INIT => X"CA"
    )
    port map (
      I0 => data_ex3(32),
      I1 => data_ex2(32),
      I2 => data_expect_3_cmp_eq0006,
      O => data_expect_32_mux0000114_2120
    );
  stp_FSM_FFd3_In_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_ctrl(6),
      O => N6
    );
  stp_FSM_FFd3_In : LUT6
    generic map(
      INIT => X"AA88AA00AAA8AAA0"
    )
    port map (
      I0 => test_gen_ctrl(5),
      I1 => stp_FSM_FFd1_2277,
      I2 => stp_FSM_FFd3_2281,
      I3 => N6,
      I4 => xcnt2_z,
      I5 => xcnt1_z,
      O => stp_FSM_FFd3_In_2282
    );
  data_expect_3_cmp_eq00068126 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => cnt1(7),
      I1 => NlwRenamedSig_OI_block_rd(7),
      I2 => cnt1(0),
      I3 => NlwRenamedSig_OI_block_rd(0),
      I4 => cnt1(1),
      I5 => NlwRenamedSig_OI_block_rd(1),
      O => data_expect_3_cmp_eq00068126_2151
    );
  Madd_data_ex4_63_32_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(33),
      O => Madd_data_ex4_63_32_add0000_cy_1_rt_748
    );
  Madd_data_ex4_63_32_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(34),
      O => Madd_data_ex4_63_32_add0000_cy_2_rt_770
    );
  Madd_data_ex4_63_32_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(35),
      O => Madd_data_ex4_63_32_add0000_cy_3_rt_774
    );
  Madd_data_ex4_63_32_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(36),
      O => Madd_data_ex4_63_32_add0000_cy_4_rt_776
    );
  Madd_data_ex4_63_32_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(37),
      O => Madd_data_ex4_63_32_add0000_cy_5_rt_778
    );
  Madd_data_ex4_63_32_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(38),
      O => Madd_data_ex4_63_32_add0000_cy_6_rt_780
    );
  Madd_data_ex4_63_32_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(39),
      O => Madd_data_ex4_63_32_add0000_cy_7_rt_782
    );
  Madd_data_ex4_63_32_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(40),
      O => Madd_data_ex4_63_32_add0000_cy_8_rt_784
    );
  Madd_data_ex4_63_32_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(41),
      O => Madd_data_ex4_63_32_add0000_cy_9_rt_786
    );
  Madd_data_ex4_63_32_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(42),
      O => Madd_data_ex4_63_32_add0000_cy_10_rt_728
    );
  Madd_data_ex4_63_32_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(43),
      O => Madd_data_ex4_63_32_add0000_cy_11_rt_730
    );
  Madd_data_ex4_63_32_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(44),
      O => Madd_data_ex4_63_32_add0000_cy_12_rt_732
    );
  Madd_data_ex4_63_32_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(45),
      O => Madd_data_ex4_63_32_add0000_cy_13_rt_734
    );
  Madd_data_ex4_63_32_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(46),
      O => Madd_data_ex4_63_32_add0000_cy_14_rt_736
    );
  Madd_data_ex4_63_32_add0000_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(47),
      O => Madd_data_ex4_63_32_add0000_cy_15_rt_738
    );
  Madd_data_ex4_63_32_add0000_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(48),
      O => Madd_data_ex4_63_32_add0000_cy_16_rt_740
    );
  Madd_data_ex4_63_32_add0000_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(49),
      O => Madd_data_ex4_63_32_add0000_cy_17_rt_742
    );
  Madd_data_ex4_63_32_add0000_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(50),
      O => Madd_data_ex4_63_32_add0000_cy_18_rt_744
    );
  Madd_data_ex4_63_32_add0000_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(51),
      O => Madd_data_ex4_63_32_add0000_cy_19_rt_746
    );
  Madd_data_ex4_63_32_add0000_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(52),
      O => Madd_data_ex4_63_32_add0000_cy_20_rt_750
    );
  Madd_data_ex4_63_32_add0000_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(53),
      O => Madd_data_ex4_63_32_add0000_cy_21_rt_752
    );
  Madd_data_ex4_63_32_add0000_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(54),
      O => Madd_data_ex4_63_32_add0000_cy_22_rt_754
    );
  Madd_data_ex4_63_32_add0000_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(55),
      O => Madd_data_ex4_63_32_add0000_cy_23_rt_756
    );
  Madd_data_ex4_63_32_add0000_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(56),
      O => Madd_data_ex4_63_32_add0000_cy_24_rt_758
    );
  Madd_data_ex4_63_32_add0000_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(57),
      O => Madd_data_ex4_63_32_add0000_cy_25_rt_760
    );
  Madd_data_ex4_63_32_add0000_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(58),
      O => Madd_data_ex4_63_32_add0000_cy_26_rt_762
    );
  Madd_data_ex4_63_32_add0000_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(59),
      O => Madd_data_ex4_63_32_add0000_cy_27_rt_764
    );
  Madd_data_ex4_63_32_add0000_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(60),
      O => Madd_data_ex4_63_32_add0000_cy_28_rt_766
    );
  Madd_data_ex4_63_32_add0000_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(61),
      O => Madd_data_ex4_63_32_add0000_cy_29_rt_768
    );
  Madd_data_ex4_63_32_add0000_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(62),
      O => Madd_data_ex4_63_32_add0000_cy_30_rt_772
    );
  Madd_data_ex4_31_0_add0000_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(1),
      O => Madd_data_ex4_31_0_add0000_cy_1_rt_685
    );
  Madd_data_ex4_31_0_add0000_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(2),
      O => Madd_data_ex4_31_0_add0000_cy_2_rt_707
    );
  Madd_data_ex4_31_0_add0000_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(3),
      O => Madd_data_ex4_31_0_add0000_cy_3_rt_711
    );
  Madd_data_ex4_31_0_add0000_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(4),
      O => Madd_data_ex4_31_0_add0000_cy_4_rt_713
    );
  Madd_data_ex4_31_0_add0000_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(5),
      O => Madd_data_ex4_31_0_add0000_cy_5_rt_715
    );
  Madd_data_ex4_31_0_add0000_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(6),
      O => Madd_data_ex4_31_0_add0000_cy_6_rt_717
    );
  Madd_data_ex4_31_0_add0000_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(7),
      O => Madd_data_ex4_31_0_add0000_cy_7_rt_719
    );
  Madd_data_ex4_31_0_add0000_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(8),
      O => Madd_data_ex4_31_0_add0000_cy_8_rt_721
    );
  Madd_data_ex4_31_0_add0000_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(9),
      O => Madd_data_ex4_31_0_add0000_cy_9_rt_723
    );
  Madd_data_ex4_31_0_add0000_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(10),
      O => Madd_data_ex4_31_0_add0000_cy_10_rt_665
    );
  Madd_data_ex4_31_0_add0000_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(11),
      O => Madd_data_ex4_31_0_add0000_cy_11_rt_667
    );
  Madd_data_ex4_31_0_add0000_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(12),
      O => Madd_data_ex4_31_0_add0000_cy_12_rt_669
    );
  Madd_data_ex4_31_0_add0000_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(13),
      O => Madd_data_ex4_31_0_add0000_cy_13_rt_671
    );
  Madd_data_ex4_31_0_add0000_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(14),
      O => Madd_data_ex4_31_0_add0000_cy_14_rt_673
    );
  Madd_data_ex4_31_0_add0000_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(15),
      O => Madd_data_ex4_31_0_add0000_cy_15_rt_675
    );
  Madd_data_ex4_31_0_add0000_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(16),
      O => Madd_data_ex4_31_0_add0000_cy_16_rt_677
    );
  Madd_data_ex4_31_0_add0000_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(17),
      O => Madd_data_ex4_31_0_add0000_cy_17_rt_679
    );
  Madd_data_ex4_31_0_add0000_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(18),
      O => Madd_data_ex4_31_0_add0000_cy_18_rt_681
    );
  Madd_data_ex4_31_0_add0000_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(19),
      O => Madd_data_ex4_31_0_add0000_cy_19_rt_683
    );
  Madd_data_ex4_31_0_add0000_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(20),
      O => Madd_data_ex4_31_0_add0000_cy_20_rt_687
    );
  Madd_data_ex4_31_0_add0000_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(21),
      O => Madd_data_ex4_31_0_add0000_cy_21_rt_689
    );
  Madd_data_ex4_31_0_add0000_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(22),
      O => Madd_data_ex4_31_0_add0000_cy_22_rt_691
    );
  Madd_data_ex4_31_0_add0000_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(23),
      O => Madd_data_ex4_31_0_add0000_cy_23_rt_693
    );
  Madd_data_ex4_31_0_add0000_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(24),
      O => Madd_data_ex4_31_0_add0000_cy_24_rt_695
    );
  Madd_data_ex4_31_0_add0000_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(25),
      O => Madd_data_ex4_31_0_add0000_cy_25_rt_697
    );
  Madd_data_ex4_31_0_add0000_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(26),
      O => Madd_data_ex4_31_0_add0000_cy_26_rt_699
    );
  Madd_data_ex4_31_0_add0000_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(27),
      O => Madd_data_ex4_31_0_add0000_cy_27_rt_701
    );
  Madd_data_ex4_31_0_add0000_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(28),
      O => Madd_data_ex4_31_0_add0000_cy_28_rt_703
    );
  Madd_data_ex4_31_0_add0000_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(29),
      O => Madd_data_ex4_31_0_add0000_cy_29_rt_705
    );
  Madd_data_ex4_31_0_add0000_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(30),
      O => Madd_data_ex4_31_0_add0000_cy_30_rt_709
    );
  Msub_cnt1_eq_addsub0000_cy_0_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => test_gen_size(0),
      O => Msub_cnt1_eq_addsub0000_cy_0_rt_1011
    );
  Mcount_block_rd_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(1),
      O => Mcount_block_rd_cy_1_rt_826
    );
  Mcount_block_rd_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(2),
      O => Mcount_block_rd_cy_2_rt_848
    );
  Mcount_block_rd_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      O => Mcount_block_rd_cy_3_rt_852
    );
  Mcount_block_rd_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(4),
      O => Mcount_block_rd_cy_4_rt_854
    );
  Mcount_block_rd_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      O => Mcount_block_rd_cy_5_rt_856
    );
  Mcount_block_rd_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(6),
      O => Mcount_block_rd_cy_6_rt_858
    );
  Mcount_block_rd_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(7),
      O => Mcount_block_rd_cy_7_rt_860
    );
  Mcount_block_rd_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(8),
      O => Mcount_block_rd_cy_8_rt_862
    );
  Mcount_block_rd_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(9),
      O => Mcount_block_rd_cy_9_rt_864
    );
  Mcount_block_rd_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(10),
      O => Mcount_block_rd_cy_10_rt_806
    );
  Mcount_block_rd_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(11),
      O => Mcount_block_rd_cy_11_rt_808
    );
  Mcount_block_rd_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(12),
      O => Mcount_block_rd_cy_12_rt_810
    );
  Mcount_block_rd_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(13),
      O => Mcount_block_rd_cy_13_rt_812
    );
  Mcount_block_rd_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(14),
      O => Mcount_block_rd_cy_14_rt_814
    );
  Mcount_block_rd_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(15),
      O => Mcount_block_rd_cy_15_rt_816
    );
  Mcount_block_rd_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(16),
      O => Mcount_block_rd_cy_16_rt_818
    );
  Mcount_block_rd_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(17),
      O => Mcount_block_rd_cy_17_rt_820
    );
  Mcount_block_rd_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(18),
      O => Mcount_block_rd_cy_18_rt_822
    );
  Mcount_block_rd_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(19),
      O => Mcount_block_rd_cy_19_rt_824
    );
  Mcount_block_rd_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(20),
      O => Mcount_block_rd_cy_20_rt_828
    );
  Mcount_block_rd_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(21),
      O => Mcount_block_rd_cy_21_rt_830
    );
  Mcount_block_rd_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(22),
      O => Mcount_block_rd_cy_22_rt_832
    );
  Mcount_block_rd_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(23),
      O => Mcount_block_rd_cy_23_rt_834
    );
  Mcount_block_rd_cy_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(24),
      O => Mcount_block_rd_cy_24_rt_836
    );
  Mcount_block_rd_cy_25_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(25),
      O => Mcount_block_rd_cy_25_rt_838
    );
  Mcount_block_rd_cy_26_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(26),
      O => Mcount_block_rd_cy_26_rt_840
    );
  Mcount_block_rd_cy_27_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(27),
      O => Mcount_block_rd_cy_27_rt_842
    );
  Mcount_block_rd_cy_28_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(28),
      O => Mcount_block_rd_cy_28_rt_844
    );
  Mcount_block_rd_cy_29_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(29),
      O => Mcount_block_rd_cy_29_rt_846
    );
  Mcount_block_rd_cy_30_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(30),
      O => Mcount_block_rd_cy_30_rt_850
    );
  Mcount_cnt1_cy_1_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(1),
      O => Mcount_cnt1_cy_1_rt_889
    );
  Mcount_cnt1_cy_2_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(2),
      O => Mcount_cnt1_cy_2_rt_899
    );
  Mcount_cnt1_cy_3_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(3),
      O => Mcount_cnt1_cy_3_rt_901
    );
  Mcount_cnt1_cy_4_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(4),
      O => Mcount_cnt1_cy_4_rt_903
    );
  Mcount_cnt1_cy_5_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(5),
      O => Mcount_cnt1_cy_5_rt_905
    );
  Mcount_cnt1_cy_6_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(6),
      O => Mcount_cnt1_cy_6_rt_907
    );
  Mcount_cnt1_cy_7_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(7),
      O => Mcount_cnt1_cy_7_rt_909
    );
  Mcount_cnt1_cy_8_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(8),
      O => Mcount_cnt1_cy_8_rt_911
    );
  Mcount_cnt1_cy_9_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(9),
      O => Mcount_cnt1_cy_9_rt_913
    );
  Mcount_cnt1_cy_10_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(10),
      O => Mcount_cnt1_cy_10_rt_869
    );
  Mcount_cnt1_cy_11_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(11),
      O => Mcount_cnt1_cy_11_rt_871
    );
  Mcount_cnt1_cy_12_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(12),
      O => Mcount_cnt1_cy_12_rt_873
    );
  Mcount_cnt1_cy_13_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(13),
      O => Mcount_cnt1_cy_13_rt_875
    );
  Mcount_cnt1_cy_14_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(14),
      O => Mcount_cnt1_cy_14_rt_877
    );
  Mcount_cnt1_cy_15_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(15),
      O => Mcount_cnt1_cy_15_rt_879
    );
  Mcount_cnt1_cy_16_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(16),
      O => Mcount_cnt1_cy_16_rt_881
    );
  Mcount_cnt1_cy_17_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(17),
      O => Mcount_cnt1_cy_17_rt_883
    );
  Mcount_cnt1_cy_18_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(18),
      O => Mcount_cnt1_cy_18_rt_885
    );
  Mcount_cnt1_cy_19_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(19),
      O => Mcount_cnt1_cy_19_rt_887
    );
  Mcount_cnt1_cy_20_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(20),
      O => Mcount_cnt1_cy_20_rt_891
    );
  Mcount_cnt1_cy_21_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(21),
      O => Mcount_cnt1_cy_21_rt_893
    );
  Mcount_cnt1_cy_22_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(22),
      O => Mcount_cnt1_cy_22_rt_895
    );
  Mcount_cnt1_cy_23_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(23),
      O => Mcount_cnt1_cy_23_rt_897
    );
  Madd_data_ex4_63_32_add0000_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(63),
      O => Madd_data_ex4_63_32_add0000_xor_31_rt_788
    );
  Madd_data_ex4_31_0_add0000_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => data_ex4(31),
      O => Madd_data_ex4_31_0_add0000_xor_31_rt_725
    );
  Mcount_block_rd_xor_31_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(31),
      O => Mcount_block_rd_xor_31_rt_866
    );
  Mcount_cnt1_xor_24_rt : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => cnt1(24),
      O => Mcount_cnt1_xor_24_rt_915
    );
  data_ex4_32_not0001104 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => data_ex4_32_not000181_1906,
      I1 => data_ex4_32_not000170_1905,
      I2 => data_ex4_32_not000148_1903,
      I3 => data_ex4_32_not000137_1902,
      I4 => data_ex4_32_not000123_1901,
      O => data_ex4_32_not0001
    );
  data_ex4_32_not000121 : LUT6
    generic map(
      INIT => X"0000000000800000"
    )
    port map (
      I0 => data_en_1321,
      I1 => cnt1(0),
      I2 => block_mode(1),
      I3 => cnt1_z_1320,
      I4 => block_mode(2),
      I5 => block_mode(3),
      O => data_ex4_10_not0001
    );
  data_expect_3_cmp_eq00068142_SW0 : LUT6
    generic map(
      INIT => X"9009000000009009"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      I1 => cnt1(5),
      I2 => NlwRenamedSig_OI_block_rd(6),
      I3 => cnt1(6),
      I4 => NlwRenamedSig_OI_block_rd(2),
      I5 => cnt1(2),
      O => N8
    );
  data_expect_3_cmp_eq00068142 : LUT6
    generic map(
      INIT => X"9009000000000000"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      I1 => cnt1(3),
      I2 => NlwRenamedSig_OI_block_rd(4),
      I3 => cnt1(4),
      I4 => data_expect_3_cmp_eq00068126_2151,
      I5 => N8,
      O => data_expect_3_cmp_eq0006
    );
  data_expect_63_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(31),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_63_mux000099_2257,
      I4 => data_expect_63_mux0000114_2256,
      O => data_expect_63_mux0000
    );
  data_expect_62_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(30),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_62_mux000099_2253,
      I4 => data_expect_62_mux0000114_2252,
      O => data_expect_62_mux0000
    );
  data_expect_61_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(29),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_61_mux000099_2249,
      I4 => data_expect_61_mux0000114_2248,
      O => data_expect_61_mux0000
    );
  data_expect_60_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(28),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_60_mux000099_2245,
      I4 => data_expect_60_mux0000114_2244,
      O => data_expect_60_mux0000
    );
  data_expect_59_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(27),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_59_mux000099_2238,
      I4 => data_expect_59_mux0000114_2237,
      O => data_expect_59_mux0000
    );
  data_expect_58_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(26),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_58_mux000099_2234,
      I4 => data_expect_58_mux0000114_2233,
      O => data_expect_58_mux0000
    );
  data_expect_57_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(25),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_57_mux000099_2230,
      I4 => data_expect_57_mux0000114_2229,
      O => data_expect_57_mux0000
    );
  data_expect_56_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(24),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_56_mux000099_2226,
      I4 => data_expect_56_mux0000114_2225,
      O => data_expect_56_mux0000
    );
  data_expect_55_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(23),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_55_mux000099_2222,
      I4 => data_expect_55_mux0000114_2221,
      O => data_expect_55_mux0000
    );
  data_expect_54_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(22),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_54_mux000099_2218,
      I4 => data_expect_54_mux0000114_2217,
      O => data_expect_54_mux0000
    );
  data_expect_53_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(21),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_53_mux000099_2214,
      I4 => data_expect_53_mux0000114_2213,
      O => data_expect_53_mux0000
    );
  data_expect_52_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(20),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_52_mux000099_2210,
      I4 => data_expect_52_mux0000114_2209,
      O => data_expect_52_mux0000
    );
  data_expect_51_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(19),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_51_mux000099_2206,
      I4 => data_expect_51_mux0000114_2205,
      O => data_expect_51_mux0000
    );
  data_expect_50_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(18),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_50_mux000099_2202,
      I4 => data_expect_50_mux0000114_2201,
      O => data_expect_50_mux0000
    );
  data_expect_49_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(17),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_49_mux000099_2195,
      I4 => data_expect_49_mux0000114_2194,
      O => data_expect_49_mux0000
    );
  data_expect_48_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(16),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_48_mux000099_2191,
      I4 => data_expect_48_mux0000114_2190,
      O => data_expect_48_mux0000
    );
  data_expect_47_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(15),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_47_mux000099_2187,
      I4 => data_expect_47_mux0000114_2186,
      O => data_expect_47_mux0000
    );
  data_expect_46_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(14),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_46_mux000099_2183,
      I4 => data_expect_46_mux0000114_2182,
      O => data_expect_46_mux0000
    );
  data_expect_45_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(13),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_45_mux000099_2179,
      I4 => data_expect_45_mux0000114_2178,
      O => data_expect_45_mux0000
    );
  data_expect_44_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(12),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_44_mux000099_2175,
      I4 => data_expect_44_mux0000114_2174,
      O => data_expect_44_mux0000
    );
  data_expect_43_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(11),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_43_mux000099_2171,
      I4 => data_expect_43_mux0000114_2170,
      O => data_expect_43_mux0000
    );
  data_expect_42_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(10),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_42_mux000099_2167,
      I4 => data_expect_42_mux0000114_2166,
      O => data_expect_42_mux0000
    );
  data_expect_41_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(9),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_41_mux000099_2163,
      I4 => data_expect_41_mux0000114_2162,
      O => data_expect_41_mux0000
    );
  data_expect_40_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(8),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_40_mux000099_2159,
      I4 => data_expect_40_mux0000114_2158,
      O => data_expect_40_mux0000
    );
  data_expect_39_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(7),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_39_mux000099_2149,
      I4 => data_expect_39_mux0000114_2148,
      O => data_expect_39_mux0000
    );
  data_expect_38_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(6),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_38_mux000099_2145,
      I4 => data_expect_38_mux0000114_2144,
      O => data_expect_38_mux0000
    );
  data_expect_37_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(5),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_37_mux000099_2141,
      I4 => data_expect_37_mux0000114_2140,
      O => data_expect_37_mux0000
    );
  data_expect_36_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(4),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_36_mux000099_2137,
      I4 => data_expect_36_mux0000114_2136,
      O => data_expect_36_mux0000
    );
  data_expect_35_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(3),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_35_mux000099_2133,
      I4 => data_expect_35_mux0000114_2132,
      O => data_expect_35_mux0000
    );
  data_expect_34_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(2),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_34_mux000099_2129,
      I4 => data_expect_34_mux0000114_2128,
      O => data_expect_34_mux0000
    );
  data_expect_33_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(1),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_33_mux000099_2125,
      I4 => data_expect_33_mux0000114_2124,
      O => data_expect_33_mux0000
    );
  data_expect_32_mux0000152 : LUT5
    generic map(
      INIT => X"BBB8BB88"
    )
    port map (
      I0 => NlwRenamedSig_OI_block_rd(0),
      I1 => cnt1_z_1320,
      I2 => data_ex3_and0000,
      I3 => data_expect_32_mux000099_2121,
      I4 => data_expect_32_mux0000114_2120,
      O => data_expect_32_mux0000
    );
  xcnt2_z_cmp_eq0000105 : LUT6
    generic map(
      INIT => X"0001000000000000"
    )
    port map (
      I0 => xcnt2(11),
      I1 => xcnt2(12),
      I2 => xcnt2(14),
      I3 => xcnt2(13),
      I4 => xcnt2_z_cmp_eq000070_2380,
      I5 => xcnt2_z_cmp_eq000034_2379,
      O => xcnt2_z
    );
  xcnt1_z_cmp_eq0000107_SW0 : LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
    port map (
      I0 => xcnt1(13),
      I1 => xcnt1(3),
      I2 => xcnt1(2),
      I3 => xcnt1(14),
      I4 => xcnt1(4),
      I5 => xcnt1_z_cmp_eq000070_2360,
      O => N114
    );
  xcnt1_z_cmp_eq0000107 : LUT6
    generic map(
      INIT => X"0000000000000002"
    )
    port map (
      I0 => xcnt1(1),
      I1 => xcnt1(0),
      I2 => xcnt1(10),
      I3 => xcnt1(11),
      I4 => xcnt1(12),
      I5 => N114,
      O => xcnt1_z
    );
  data_ex3_mux0000_9_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(54),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(9)
    );
  data_ex3_mux0000_8_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(55),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(8)
    );
  data_ex3_mux0000_7_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(56),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(7)
    );
  data_ex3_mux0000_6_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(57),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(6)
    );
  data_ex3_mux0000_63_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(0),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(63)
    );
  data_ex3_mux0000_62_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(1),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(62)
    );
  data_ex3_mux0000_61_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(2),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(61)
    );
  data_ex3_mux0000_60_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(3),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(60)
    );
  data_ex3_mux0000_5_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(58),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(5)
    );
  data_ex3_mux0000_59_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(4),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(59)
    );
  data_ex3_mux0000_58_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(5),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(58)
    );
  data_ex3_mux0000_57_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(6),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(57)
    );
  data_ex3_mux0000_56_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(7),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(56)
    );
  data_ex3_mux0000_55_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(8),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(55)
    );
  data_ex3_mux0000_54_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(9),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(54)
    );
  data_ex3_mux0000_53_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(10),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(53)
    );
  data_ex3_mux0000_52_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(11),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(52)
    );
  data_ex3_mux0000_51_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(12),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(51)
    );
  data_ex3_mux0000_50_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(13),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(50)
    );
  data_ex3_mux0000_4_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(59),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(4)
    );
  data_ex3_mux0000_49_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(14),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(49)
    );
  data_ex3_mux0000_48_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(15),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(48)
    );
  data_ex3_mux0000_47_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(16),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(47)
    );
  data_ex3_mux0000_46_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(17),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(46)
    );
  data_ex3_mux0000_45_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(18),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(45)
    );
  data_ex3_mux0000_44_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(19),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(44)
    );
  data_ex3_mux0000_43_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(20),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(43)
    );
  data_ex3_mux0000_42_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(21),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(42)
    );
  data_ex3_mux0000_41_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(22),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(41)
    );
  data_ex3_mux0000_40_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(23),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(40)
    );
  data_ex3_mux0000_3_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(60),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(3)
    );
  data_ex3_mux0000_39_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(24),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(39)
    );
  data_ex3_mux0000_38_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(25),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(38)
    );
  data_ex3_mux0000_37_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(26),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(37)
    );
  data_ex3_mux0000_36_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(27),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(36)
    );
  data_ex3_mux0000_35_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(28),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(35)
    );
  data_ex3_mux0000_34_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(29),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(34)
    );
  data_ex3_mux0000_33_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(30),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(33)
    );
  data_ex3_mux0000_32_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(31),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(32)
    );
  data_ex3_mux0000_31_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(32),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(31)
    );
  data_ex3_mux0000_30_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(33),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(30)
    );
  data_ex3_mux0000_2_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(61),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(2)
    );
  data_ex3_mux0000_29_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(34),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(29)
    );
  data_ex3_mux0000_28_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(35),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(28)
    );
  data_ex3_mux0000_27_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(36),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(27)
    );
  data_ex3_mux0000_26_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(37),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(26)
    );
  data_ex3_mux0000_25_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(38),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(25)
    );
  data_ex3_mux0000_24_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(39),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(24)
    );
  data_ex3_mux0000_23_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(40),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(23)
    );
  data_ex3_mux0000_22_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(41),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(22)
    );
  data_ex3_mux0000_21_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(42),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(21)
    );
  data_ex3_mux0000_20_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(43),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(20)
    );
  data_ex3_mux0000_1_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(62),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(1)
    );
  data_ex3_mux0000_19_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(44),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(19)
    );
  data_ex3_mux0000_18_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(45),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(18)
    );
  data_ex3_mux0000_17_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(46),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(17)
    );
  data_ex3_mux0000_16_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(47),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(16)
    );
  data_ex3_mux0000_15_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(48),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(15)
    );
  data_ex3_mux0000_14_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(49),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(14)
    );
  data_ex3_mux0000_13_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(50),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(13)
    );
  data_ex3_mux0000_12_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(51),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(12)
    );
  data_ex3_mux0000_11_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(52),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(11)
    );
  data_ex3_mux0000_10_1 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(53),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(10)
    );
  data_ex3_mux0000_0_2 : LUT5
    generic map(
      INIT => X"CCDCCC8C"
    )
    port map (
      I0 => block_mode(1),
      I1 => data_ex3(63),
      I2 => block_mode(2),
      I3 => block_mode(3),
      I4 => block_mode(0),
      O => data_ex3_mux0000(0)
    );
  data_ex2_0_mux00001 : LUT5
    generic map(
      INIT => X"5DFD08A8"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(0),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(63),
      O => data_ex2_0_mux0000
    );
  block_mode_not00011 : LUT3
    generic map(
      INIT => X"F8"
    )
    port map (
      I0 => data_en_1321,
      I1 => cnt1_eq_1300,
      I2 => test_gen_ctrl(7),
      O => block_mode_not0001
    );
  data_ex1_0_mux00001 : LUT6
    generic map(
      INIT => X"DD5DDDFD880888A8"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex1(0),
      I2 => N80,
      I3 => block_mode(2),
      I4 => block_mode(0),
      I5 => data_ex1(63),
      O => data_ex1_0_mux0000
    );
  data_ex0_0_mux00001 : LUT6
    generic map(
      INIT => X"DD5DDDFD880888A8"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex0(0),
      I2 => N61,
      I3 => block_mode(3),
      I4 => block_mode(0),
      I5 => data_ex0(63),
      O => data_ex0_0_mux0000
    );
  cnt1_or00001 : LUT4
    generic map(
      INIT => X"FFD5"
    )
    port map (
      I0 => reset,
      I1 => data_en_1321,
      I2 => cnt1_eq_1300,
      I3 => test_gen_ctrl(0),
      O => cnt1_or0000
    );
  data_ex3_not00011 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => data_en_1321,
      I1 => test_gen_ctrl(0),
      I2 => reset,
      I3 => cnt1_z_1320,
      O => data_ex3_not0001
    );
  Mcount_xcnt2_lut_0_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(0),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(0),
      O => Mcount_xcnt2_lut(0)
    );
  Mcount_xcnt1_lut_0_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(0),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(0),
      O => Mcount_xcnt1_lut(0)
    );
  Mcount_xcnt2_lut_1_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(1),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(1),
      O => Mcount_xcnt2_lut(1)
    );
  Mcount_xcnt1_lut_1_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(1),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(1),
      O => Mcount_xcnt1_lut(1)
    );
  Mcount_xcnt2_lut_2_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(2),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(2),
      O => Mcount_xcnt2_lut(2)
    );
  Mcount_xcnt1_lut_2_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(2),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(2),
      O => Mcount_xcnt1_lut(2)
    );
  Mcount_xcnt2_lut_3_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(3),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(3),
      O => Mcount_xcnt2_lut(3)
    );
  Mcount_xcnt1_lut_3_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(3),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(3),
      O => Mcount_xcnt1_lut(3)
    );
  Mcount_xcnt2_lut_4_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(4),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(4),
      O => Mcount_xcnt2_lut(4)
    );
  Mcount_xcnt1_lut_4_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(4),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(4),
      O => Mcount_xcnt1_lut(4)
    );
  Mcount_xcnt2_lut_5_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(5),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(5),
      O => Mcount_xcnt2_lut(5)
    );
  Mcount_xcnt1_lut_5_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(5),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(5),
      O => Mcount_xcnt1_lut(5)
    );
  Mcount_xcnt2_lut_6_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(6),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(6),
      O => Mcount_xcnt2_lut(6)
    );
  Mcount_xcnt1_lut_6_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(6),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(6),
      O => Mcount_xcnt1_lut(6)
    );
  Mcount_xcnt2_lut_7_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(7),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(7),
      O => Mcount_xcnt2_lut(7)
    );
  Mcount_xcnt1_lut_7_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(7),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(7),
      O => Mcount_xcnt1_lut(7)
    );
  Mcount_xcnt2_lut_8_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(8),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(8),
      O => Mcount_xcnt2_lut(8)
    );
  Mcount_xcnt1_lut_8_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(8),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(8),
      O => Mcount_xcnt1_lut(8)
    );
  Mcount_xcnt2_lut_9_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(9),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(9),
      O => Mcount_xcnt2_lut(9)
    );
  Mcount_xcnt1_lut_9_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(9),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(9),
      O => Mcount_xcnt1_lut(9)
    );
  Mcount_xcnt2_lut_10_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(10),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(10),
      O => Mcount_xcnt2_lut(10)
    );
  Mcount_xcnt1_lut_10_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(10),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(10),
      O => Mcount_xcnt1_lut(10)
    );
  Mcount_xcnt2_lut_11_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(11),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(11),
      O => Mcount_xcnt2_lut(11)
    );
  Mcount_xcnt1_lut_11_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(11),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(11),
      O => Mcount_xcnt1_lut(11)
    );
  Mcount_xcnt2_lut_12_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(12),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(12),
      O => Mcount_xcnt2_lut(12)
    );
  Mcount_xcnt1_lut_12_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(12),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(12),
      O => Mcount_xcnt1_lut(12)
    );
  Mcount_xcnt2_lut_13_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(13),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(13),
      O => Mcount_xcnt2_lut(13)
    );
  Mcount_xcnt1_lut_13_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(13),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(13),
      O => Mcount_xcnt1_lut(13)
    );
  Mcount_xcnt2_lut_14_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(14),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(14),
      O => Mcount_xcnt2_lut(14)
    );
  Mcount_xcnt1_lut_14_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(14),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(14),
      O => Mcount_xcnt1_lut(14)
    );
  data_ex5_10_not00011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => block_mode(3),
      I1 => data_en_1321,
      I2 => cnt1_z_1320,
      I3 => block_mode(2),
      I4 => block_mode(1),
      O => data_ex5_10_not0001
    );
  Mcount_xcnt2_lut_15_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt2(15),
      I2 => stp_FSM_FFd3_2281,
      I3 => stp_FSM_FFd2_2279,
      I4 => xcnt2(15),
      O => Mcount_xcnt2_lut(15)
    );
  Mcount_xcnt1_lut_15_Q : LUT5
    generic map(
      INIT => X"33323337"
    )
    port map (
      I0 => stp_FSM_FFd4_2283,
      I1 => test_gen_cnt1(15),
      I2 => stp_FSM_FFd2_2279,
      I3 => stp_FSM_FFd1_2277,
      I4 => xcnt1(15),
      O => Mcount_xcnt1_lut(15)
    );
  data_ex2_0_not00011 : LUT6
    generic map(
      INIT => X"4040400040004000"
    )
    port map (
      I0 => test_gen_ctrl(0),
      I1 => reset,
      I2 => data_en_1321,
      I3 => cnt1_z_1320,
      I4 => data_ex3_and0000,
      I5 => data_expect_3_cmp_eq0006,
      O => data_ex2_0_not0001
    );
  data_ex2_9_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(9),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(8),
      O => data_ex2_9_mux0000
    );
  data_ex2_8_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(8),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(7),
      O => data_ex2_8_mux0000
    );
  data_ex2_7_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(7),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(6),
      O => data_ex2_7_mux0000
    );
  data_ex2_6_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(6),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(5),
      O => data_ex2_6_mux0000
    );
  data_ex2_63_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(63),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(62),
      O => data_ex2_63_mux0000
    );
  data_ex2_62_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(62),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(61),
      O => data_ex2_62_mux0000
    );
  data_ex2_61_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(61),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(60),
      O => data_ex2_61_mux0000
    );
  data_ex2_60_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(60),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(59),
      O => data_ex2_60_mux0000
    );
  data_ex2_5_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(5),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(4),
      O => data_ex2_5_mux0000
    );
  data_ex2_59_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(59),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(58),
      O => data_ex2_59_mux0000
    );
  data_ex2_58_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(58),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(57),
      O => data_ex2_58_mux0000
    );
  data_ex2_57_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(57),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(56),
      O => data_ex2_57_mux0000
    );
  data_ex2_56_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(56),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(55),
      O => data_ex2_56_mux0000
    );
  data_ex2_55_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(55),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(54),
      O => data_ex2_55_mux0000
    );
  data_ex2_54_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(54),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(53),
      O => data_ex2_54_mux0000
    );
  data_ex2_53_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(53),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(52),
      O => data_ex2_53_mux0000
    );
  data_ex2_52_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(52),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(51),
      O => data_ex2_52_mux0000
    );
  data_ex2_51_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(51),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(50),
      O => data_ex2_51_mux0000
    );
  data_ex2_50_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(50),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(49),
      O => data_ex2_50_mux0000
    );
  data_ex2_4_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(4),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(3),
      O => data_ex2_4_mux0000
    );
  data_ex2_49_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(49),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(48),
      O => data_ex2_49_mux0000
    );
  data_ex2_48_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(48),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(47),
      O => data_ex2_48_mux0000
    );
  data_ex2_47_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(47),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(46),
      O => data_ex2_47_mux0000
    );
  data_ex2_46_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(46),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(45),
      O => data_ex2_46_mux0000
    );
  data_ex2_45_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(45),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(44),
      O => data_ex2_45_mux0000
    );
  data_ex2_44_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(44),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(43),
      O => data_ex2_44_mux0000
    );
  data_ex2_43_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(43),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(42),
      O => data_ex2_43_mux0000
    );
  data_ex2_42_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(42),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(41),
      O => data_ex2_42_mux0000
    );
  data_ex2_41_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(41),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(40),
      O => data_ex2_41_mux0000
    );
  data_ex2_40_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(40),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(39),
      O => data_ex2_40_mux0000
    );
  data_ex2_3_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(3),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(2),
      O => data_ex2_3_mux0000
    );
  data_ex2_39_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(39),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(38),
      O => data_ex2_39_mux0000
    );
  data_ex2_38_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(38),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(37),
      O => data_ex2_38_mux0000
    );
  data_ex2_37_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(37),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(36),
      O => data_ex2_37_mux0000
    );
  data_ex2_36_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(36),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(35),
      O => data_ex2_36_mux0000
    );
  data_ex2_35_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(35),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(34),
      O => data_ex2_35_mux0000
    );
  data_ex2_34_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(34),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(33),
      O => data_ex2_34_mux0000
    );
  data_ex2_33_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(33),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(32),
      O => data_ex2_33_mux0000
    );
  data_ex2_32_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(32),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(31),
      O => data_ex2_32_mux0000
    );
  data_ex2_31_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(31),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(30),
      O => data_ex2_31_mux0000
    );
  data_ex2_30_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(30),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(29),
      O => data_ex2_30_mux0000
    );
  data_ex2_2_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(2),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(1),
      O => data_ex2_2_mux0000
    );
  data_ex2_29_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(29),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(28),
      O => data_ex2_29_mux0000
    );
  data_ex2_28_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(28),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(27),
      O => data_ex2_28_mux0000
    );
  data_ex2_27_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(27),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(26),
      O => data_ex2_27_mux0000
    );
  data_ex2_26_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(26),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(25),
      O => data_ex2_26_mux0000
    );
  data_ex2_25_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(25),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(24),
      O => data_ex2_25_mux0000
    );
  data_ex2_24_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(24),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(23),
      O => data_ex2_24_mux0000
    );
  data_ex2_23_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(23),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(22),
      O => data_ex2_23_mux0000
    );
  data_ex2_22_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(22),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(21),
      O => data_ex2_22_mux0000
    );
  data_ex2_21_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(21),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(20),
      O => data_ex2_21_mux0000
    );
  data_ex2_20_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(20),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(19),
      O => data_ex2_20_mux0000
    );
  data_ex2_1_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(1),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(0),
      O => data_ex2_1_mux0000
    );
  data_ex2_19_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(19),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(18),
      O => data_ex2_19_mux0000
    );
  data_ex2_18_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(18),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(17),
      O => data_ex2_18_mux0000
    );
  data_ex2_17_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(17),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(16),
      O => data_ex2_17_mux0000
    );
  data_ex2_16_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(16),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(15),
      O => data_ex2_16_mux0000
    );
  data_ex2_15_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(15),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(14),
      O => data_ex2_15_mux0000
    );
  data_ex2_14_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(14),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(13),
      O => data_ex2_14_mux0000
    );
  data_ex2_13_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(13),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(12),
      O => data_ex2_13_mux0000
    );
  data_ex2_12_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(12),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(11),
      O => data_ex2_12_mux0000
    );
  data_ex2_11_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(11),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(10),
      O => data_ex2_11_mux0000
    );
  data_ex2_10_mux00001 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => data_ex2(10),
      I2 => data_ex3_and0000,
      I3 => block_mode(0),
      I4 => data_ex2(9),
      O => data_ex2_10_mux0000
    );
  data_ex1_9_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(8),
      I5 => data_ex1(9),
      O => data_ex1_9_mux0000
    );
  data_ex1_8_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(7),
      I5 => data_ex1(8),
      O => data_ex1_8_mux0000
    );
  data_ex1_7_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(6),
      I5 => data_ex1(7),
      O => data_ex1_7_mux0000
    );
  data_ex1_6_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(5),
      I5 => data_ex1(6),
      O => data_ex1_6_mux0000
    );
  data_ex1_63_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(62),
      I5 => data_ex1(63),
      O => data_ex1_63_mux0000
    );
  data_ex1_62_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(61),
      I5 => data_ex1(62),
      O => data_ex1_62_mux0000
    );
  data_ex1_61_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(60),
      I5 => data_ex1(61),
      O => data_ex1_61_mux0000
    );
  data_ex1_60_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(59),
      I5 => data_ex1(60),
      O => data_ex1_60_mux0000
    );
  data_ex1_5_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(4),
      I5 => data_ex1(5),
      O => data_ex1_5_mux0000
    );
  data_ex1_59_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(58),
      I5 => data_ex1(59),
      O => data_ex1_59_mux0000
    );
  data_ex1_58_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(57),
      I5 => data_ex1(58),
      O => data_ex1_58_mux0000
    );
  data_ex1_57_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(56),
      I5 => data_ex1(57),
      O => data_ex1_57_mux0000
    );
  data_ex1_56_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(55),
      I5 => data_ex1(56),
      O => data_ex1_56_mux0000
    );
  data_ex1_55_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(54),
      I5 => data_ex1(55),
      O => data_ex1_55_mux0000
    );
  data_ex1_54_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(53),
      I5 => data_ex1(54),
      O => data_ex1_54_mux0000
    );
  data_ex1_53_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(52),
      I5 => data_ex1(53),
      O => data_ex1_53_mux0000
    );
  data_ex1_52_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(51),
      I5 => data_ex1(52),
      O => data_ex1_52_mux0000
    );
  data_ex1_51_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(50),
      I5 => data_ex1(51),
      O => data_ex1_51_mux0000
    );
  data_ex1_50_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(49),
      I5 => data_ex1(50),
      O => data_ex1_50_mux0000
    );
  data_ex1_4_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(3),
      I5 => data_ex1(4),
      O => data_ex1_4_mux0000
    );
  data_ex1_49_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(48),
      I5 => data_ex1(49),
      O => data_ex1_49_mux0000
    );
  data_ex1_48_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(47),
      I5 => data_ex1(48),
      O => data_ex1_48_mux0000
    );
  data_ex1_47_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(46),
      I5 => data_ex1(47),
      O => data_ex1_47_mux0000
    );
  data_ex1_46_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(45),
      I5 => data_ex1(46),
      O => data_ex1_46_mux0000
    );
  data_ex1_45_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(44),
      I5 => data_ex1(45),
      O => data_ex1_45_mux0000
    );
  data_ex1_44_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(43),
      I5 => data_ex1(44),
      O => data_ex1_44_mux0000
    );
  data_ex1_43_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(42),
      I5 => data_ex1(43),
      O => data_ex1_43_mux0000
    );
  data_ex1_42_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(41),
      I5 => data_ex1(42),
      O => data_ex1_42_mux0000
    );
  data_ex1_41_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(40),
      I5 => data_ex1(41),
      O => data_ex1_41_mux0000
    );
  data_ex1_40_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(39),
      I5 => data_ex1(40),
      O => data_ex1_40_mux0000
    );
  data_ex1_3_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(2),
      I5 => data_ex1(3),
      O => data_ex1_3_mux0000
    );
  data_ex1_39_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(38),
      I5 => data_ex1(39),
      O => data_ex1_39_mux0000
    );
  data_ex1_38_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(37),
      I5 => data_ex1(38),
      O => data_ex1_38_mux0000
    );
  data_ex1_37_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(36),
      I5 => data_ex1(37),
      O => data_ex1_37_mux0000
    );
  data_ex1_36_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(35),
      I5 => data_ex1(36),
      O => data_ex1_36_mux0000
    );
  data_ex1_35_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(34),
      I5 => data_ex1(35),
      O => data_ex1_35_mux0000
    );
  data_ex1_34_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(33),
      I5 => data_ex1(34),
      O => data_ex1_34_mux0000
    );
  data_ex1_33_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(32),
      I5 => data_ex1(33),
      O => data_ex1_33_mux0000
    );
  data_ex1_32_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(31),
      I5 => data_ex1(32),
      O => data_ex1_32_mux0000
    );
  data_ex1_31_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(30),
      I5 => data_ex1(31),
      O => data_ex1_31_mux0000
    );
  data_ex1_30_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(29),
      I5 => data_ex1(30),
      O => data_ex1_30_mux0000
    );
  data_ex1_2_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(1),
      I5 => data_ex1(2),
      O => data_ex1_2_mux0000
    );
  data_ex1_29_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(28),
      I5 => data_ex1(29),
      O => data_ex1_29_mux0000
    );
  data_ex1_28_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(27),
      I5 => data_ex1(28),
      O => data_ex1_28_mux0000
    );
  data_ex1_27_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(26),
      I5 => data_ex1(27),
      O => data_ex1_27_mux0000
    );
  data_ex1_26_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(25),
      I5 => data_ex1(26),
      O => data_ex1_26_mux0000
    );
  data_ex1_25_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(24),
      I5 => data_ex1(25),
      O => data_ex1_25_mux0000
    );
  data_ex1_24_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(23),
      I5 => data_ex1(24),
      O => data_ex1_24_mux0000
    );
  data_ex1_23_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(22),
      I5 => data_ex1(23),
      O => data_ex1_23_mux0000
    );
  data_ex1_22_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(21),
      I5 => data_ex1(22),
      O => data_ex1_22_mux0000
    );
  data_ex1_21_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(20),
      I5 => data_ex1(21),
      O => data_ex1_21_mux0000
    );
  data_ex1_20_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(19),
      I5 => data_ex1(20),
      O => data_ex1_20_mux0000
    );
  data_ex1_1_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(0),
      I5 => data_ex1(1),
      O => data_ex1_1_mux0000
    );
  data_ex1_19_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(18),
      I5 => data_ex1(19),
      O => data_ex1_19_mux0000
    );
  data_ex1_18_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(17),
      I5 => data_ex1(18),
      O => data_ex1_18_mux0000
    );
  data_ex1_17_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(16),
      I5 => data_ex1(17),
      O => data_ex1_17_mux0000
    );
  data_ex1_16_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(15),
      I5 => data_ex1(16),
      O => data_ex1_16_mux0000
    );
  data_ex1_15_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(14),
      I5 => data_ex1(15),
      O => data_ex1_15_mux0000
    );
  data_ex1_14_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(13),
      I5 => data_ex1(14),
      O => data_ex1_14_mux0000
    );
  data_ex1_13_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(12),
      I5 => data_ex1(13),
      O => data_ex1_13_mux0000
    );
  data_ex1_12_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(11),
      I5 => data_ex1(12),
      O => data_ex1_12_mux0000
    );
  data_ex1_11_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(10),
      I5 => data_ex1(11),
      O => data_ex1_11_mux0000
    );
  data_ex1_10_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N80,
      I2 => block_mode(0),
      I3 => block_mode(2),
      I4 => data_ex1(9),
      I5 => data_ex1(10),
      O => data_ex1_10_mux0000
    );
  data_ex0_9_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(8),
      I5 => data_ex0(9),
      O => data_ex0_9_mux0000
    );
  data_ex0_8_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(7),
      I5 => data_ex0(8),
      O => data_ex0_8_mux0000
    );
  data_ex0_7_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(6),
      I5 => data_ex0(7),
      O => data_ex0_7_mux0000
    );
  data_ex0_6_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(5),
      I5 => data_ex0(6),
      O => data_ex0_6_mux0000
    );
  data_ex0_63_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(62),
      I5 => data_ex0(63),
      O => data_ex0_63_mux0000
    );
  data_ex0_62_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(61),
      I5 => data_ex0(62),
      O => data_ex0_62_mux0000
    );
  data_ex0_61_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(60),
      I5 => data_ex0(61),
      O => data_ex0_61_mux0000
    );
  data_ex0_60_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(59),
      I5 => data_ex0(60),
      O => data_ex0_60_mux0000
    );
  data_ex0_5_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(4),
      I5 => data_ex0(5),
      O => data_ex0_5_mux0000
    );
  data_ex0_59_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(58),
      I5 => data_ex0(59),
      O => data_ex0_59_mux0000
    );
  data_ex0_58_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(57),
      I5 => data_ex0(58),
      O => data_ex0_58_mux0000
    );
  data_ex0_57_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(56),
      I5 => data_ex0(57),
      O => data_ex0_57_mux0000
    );
  data_ex0_56_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(55),
      I5 => data_ex0(56),
      O => data_ex0_56_mux0000
    );
  data_ex0_55_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(54),
      I5 => data_ex0(55),
      O => data_ex0_55_mux0000
    );
  data_ex0_54_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(53),
      I5 => data_ex0(54),
      O => data_ex0_54_mux0000
    );
  data_ex0_53_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(52),
      I5 => data_ex0(53),
      O => data_ex0_53_mux0000
    );
  data_ex0_52_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(51),
      I5 => data_ex0(52),
      O => data_ex0_52_mux0000
    );
  data_ex0_51_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(50),
      I5 => data_ex0(51),
      O => data_ex0_51_mux0000
    );
  data_ex0_50_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(49),
      I5 => data_ex0(50),
      O => data_ex0_50_mux0000
    );
  data_ex0_4_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(3),
      I5 => data_ex0(4),
      O => data_ex0_4_mux0000
    );
  data_ex0_49_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(48),
      I5 => data_ex0(49),
      O => data_ex0_49_mux0000
    );
  data_ex0_48_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(47),
      I5 => data_ex0(48),
      O => data_ex0_48_mux0000
    );
  data_ex0_47_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(46),
      I5 => data_ex0(47),
      O => data_ex0_47_mux0000
    );
  data_ex0_46_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(45),
      I5 => data_ex0(46),
      O => data_ex0_46_mux0000
    );
  data_ex0_45_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(44),
      I5 => data_ex0(45),
      O => data_ex0_45_mux0000
    );
  data_ex0_44_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(43),
      I5 => data_ex0(44),
      O => data_ex0_44_mux0000
    );
  data_ex0_43_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(42),
      I5 => data_ex0(43),
      O => data_ex0_43_mux0000
    );
  data_ex0_42_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(41),
      I5 => data_ex0(42),
      O => data_ex0_42_mux0000
    );
  data_ex0_41_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(40),
      I5 => data_ex0(41),
      O => data_ex0_41_mux0000
    );
  data_ex0_40_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(39),
      I5 => data_ex0(40),
      O => data_ex0_40_mux0000
    );
  data_ex0_3_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(2),
      I5 => data_ex0(3),
      O => data_ex0_3_mux0000
    );
  data_ex0_39_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(38),
      I5 => data_ex0(39),
      O => data_ex0_39_mux0000
    );
  data_ex0_38_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(37),
      I5 => data_ex0(38),
      O => data_ex0_38_mux0000
    );
  data_ex0_37_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(36),
      I5 => data_ex0(37),
      O => data_ex0_37_mux0000
    );
  data_ex0_36_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(35),
      I5 => data_ex0(36),
      O => data_ex0_36_mux0000
    );
  data_ex0_35_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(34),
      I5 => data_ex0(35),
      O => data_ex0_35_mux0000
    );
  data_ex0_34_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(33),
      I5 => data_ex0(34),
      O => data_ex0_34_mux0000
    );
  data_ex0_33_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(32),
      I5 => data_ex0(33),
      O => data_ex0_33_mux0000
    );
  data_ex0_32_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(31),
      I5 => data_ex0(32),
      O => data_ex0_32_mux0000
    );
  data_ex0_31_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(30),
      I5 => data_ex0(31),
      O => data_ex0_31_mux0000
    );
  data_ex0_30_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(29),
      I5 => data_ex0(30),
      O => data_ex0_30_mux0000
    );
  data_ex0_2_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(1),
      I5 => data_ex0(2),
      O => data_ex0_2_mux0000
    );
  data_ex0_29_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(28),
      I5 => data_ex0(29),
      O => data_ex0_29_mux0000
    );
  data_ex0_28_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(27),
      I5 => data_ex0(28),
      O => data_ex0_28_mux0000
    );
  data_ex0_27_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(26),
      I5 => data_ex0(27),
      O => data_ex0_27_mux0000
    );
  data_ex0_26_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(25),
      I5 => data_ex0(26),
      O => data_ex0_26_mux0000
    );
  data_ex0_25_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(24),
      I5 => data_ex0(25),
      O => data_ex0_25_mux0000
    );
  data_ex0_24_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(23),
      I5 => data_ex0(24),
      O => data_ex0_24_mux0000
    );
  data_ex0_23_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(22),
      I5 => data_ex0(23),
      O => data_ex0_23_mux0000
    );
  data_ex0_22_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(21),
      I5 => data_ex0(22),
      O => data_ex0_22_mux0000
    );
  data_ex0_21_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(20),
      I5 => data_ex0(21),
      O => data_ex0_21_mux0000
    );
  data_ex0_20_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(19),
      I5 => data_ex0(20),
      O => data_ex0_20_mux0000
    );
  data_ex0_1_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(0),
      I5 => data_ex0(1),
      O => data_ex0_1_mux0000
    );
  data_ex0_19_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(18),
      I5 => data_ex0(19),
      O => data_ex0_19_mux0000
    );
  data_ex0_18_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(17),
      I5 => data_ex0(18),
      O => data_ex0_18_mux0000
    );
  data_ex0_17_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(16),
      I5 => data_ex0(17),
      O => data_ex0_17_mux0000
    );
  data_ex0_16_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(15),
      I5 => data_ex0(16),
      O => data_ex0_16_mux0000
    );
  data_ex0_15_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(14),
      I5 => data_ex0(15),
      O => data_ex0_15_mux0000
    );
  data_ex0_14_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(13),
      I5 => data_ex0(14),
      O => data_ex0_14_mux0000
    );
  data_ex0_13_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(12),
      I5 => data_ex0(13),
      O => data_ex0_13_mux0000
    );
  data_ex0_12_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(11),
      I5 => data_ex0(12),
      O => data_ex0_12_mux0000
    );
  data_ex0_11_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(10),
      I5 => data_ex0(11),
      O => data_ex0_11_mux0000
    );
  data_ex0_10_mux00001 : LUT6
    generic map(
      INIT => X"FFF7AAA255D50080"
    )
    port map (
      I0 => cnt1_z_1320,
      I1 => N61,
      I2 => block_mode(0),
      I3 => block_mode(3),
      I4 => data_ex0(9),
      I5 => data_ex0(10),
      O => data_ex0_10_mux0000
    );
  data_ex0_0_not00011 : LUT5
    generic map(
      INIT => X"8888888A"
    )
    port map (
      I0 => data_en_1321,
      I1 => cnt1_z_1320,
      I2 => block_mode(2),
      I3 => block_mode(1),
      I4 => block_mode(3),
      O => data_ex0_0_not0001
    );
  data_expect_8_mux0000124 : MUXF7
    port map (
      I0 => N220,
      I1 => N221,
      S => block_mode(1),
      O => data_expect_8_mux0000
    );
  data_expect_8_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(8),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(8),
      I5 => data_expect_8_mux000031_2265,
      O => N220
    );
  data_expect_8_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(8),
      I4 => data_ex1(8),
      I5 => data_expect_8_mux000031_2265,
      O => N221
    );
  data_expect_5_mux0000124 : MUXF7
    port map (
      I0 => N222,
      I1 => N223,
      S => block_mode(1),
      O => data_expect_5_mux0000
    );
  data_expect_5_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(5),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(5),
      I5 => data_expect_5_mux000031_2240,
      O => N222
    );
  data_expect_5_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(5),
      I4 => data_ex1(5),
      I5 => data_expect_5_mux000031_2240,
      O => N223
    );
  data_expect_31_mux0000124 : MUXF7
    port map (
      I0 => N224,
      I1 => N225,
      S => block_mode(1),
      O => data_expect_31_mux0000
    );
  data_expect_31_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(31),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(31),
      I5 => data_expect_31_mux000031_2117,
      O => N224
    );
  data_expect_31_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(31),
      I4 => data_ex1(31),
      I5 => data_expect_31_mux000031_2117,
      O => N225
    );
  data_expect_29_mux0000124 : MUXF7
    port map (
      I0 => N226,
      I1 => N227,
      S => block_mode(1),
      O => data_expect_29_mux0000
    );
  data_expect_29_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(29),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(29),
      I5 => data_expect_29_mux000031_2108,
      O => N226
    );
  data_expect_29_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(29),
      I4 => data_ex1(29),
      I5 => data_expect_29_mux000031_2108,
      O => N227
    );
  data_expect_26_mux0000124 : MUXF7
    port map (
      I0 => N228,
      I1 => N229,
      S => block_mode(1),
      O => data_expect_26_mux0000
    );
  data_expect_26_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(26),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(26),
      I5 => data_expect_26_mux000031_2099,
      O => N228
    );
  data_expect_26_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(26),
      I4 => data_ex1(26),
      I5 => data_expect_26_mux000031_2099,
      O => N229
    );
  data_expect_24_mux0000124 : MUXF7
    port map (
      I0 => N230,
      I1 => N231,
      S => block_mode(1),
      O => data_expect_24_mux0000
    );
  data_expect_24_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(24),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(24),
      I5 => data_expect_24_mux000031_2093,
      O => N230
    );
  data_expect_24_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(24),
      I4 => data_ex1(24),
      I5 => data_expect_24_mux000031_2093,
      O => N231
    );
  data_expect_23_mux0000124 : MUXF7
    port map (
      I0 => N232,
      I1 => N233,
      S => block_mode(1),
      O => data_expect_23_mux0000
    );
  data_expect_23_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(23),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(23),
      I5 => data_expect_23_mux000031_2090,
      O => N232
    );
  data_expect_23_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(23),
      I4 => data_ex1(23),
      I5 => data_expect_23_mux000031_2090,
      O => N233
    );
  data_expect_21_mux0000124 : MUXF7
    port map (
      I0 => N234,
      I1 => N235,
      S => block_mode(1),
      O => data_expect_21_mux0000
    );
  data_expect_21_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(21),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(21),
      I5 => data_expect_21_mux000031_2084,
      O => N234
    );
  data_expect_21_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(21),
      I4 => data_ex1(21),
      I5 => data_expect_21_mux000031_2084,
      O => N235
    );
  data_expect_1_mux0000124 : MUXF7
    port map (
      I0 => N236,
      I1 => N237,
      S => block_mode(1),
      O => data_expect_1_mux0000
    );
  data_expect_1_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(1),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(1),
      I5 => data_expect_1_mux000031_2077,
      O => N236
    );
  data_expect_1_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(1),
      I4 => data_ex1(1),
      I5 => data_expect_1_mux000031_2077,
      O => N237
    );
  data_expect_18_mux0000124 : MUXF7
    port map (
      I0 => N238,
      I1 => N239,
      S => block_mode(1),
      O => data_expect_18_mux0000
    );
  data_expect_18_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(18),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(18),
      I5 => data_expect_18_mux000031_2072,
      O => N238
    );
  data_expect_18_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(18),
      I4 => data_ex1(18),
      I5 => data_expect_18_mux000031_2072,
      O => N239
    );
  data_expect_16_mux0000124 : MUXF7
    port map (
      I0 => N240,
      I1 => N241,
      S => block_mode(1),
      O => data_expect_16_mux0000
    );
  data_expect_16_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(16),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(16),
      I5 => data_expect_16_mux000031_2066,
      O => N240
    );
  data_expect_16_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(16),
      I4 => data_ex1(16),
      I5 => data_expect_16_mux000031_2066,
      O => N241
    );
  data_expect_0_mux0000124 : MUXF7
    port map (
      I0 => N242,
      I1 => N243,
      S => block_mode(1),
      O => data_expect_0_mux0000
    );
  data_expect_0_mux0000124_F : LUT6
    generic map(
      INIT => X"FFFFFFFF20222000"
    )
    port map (
      I0 => block_mode(2),
      I1 => block_mode(3),
      I2 => data_ex2(0),
      I3 => data_expect_3_cmp_eq0006,
      I4 => data_ex3(0),
      I5 => data_expect_0_mux000031_2044,
      O => N242
    );
  data_expect_0_mux0000124_G : LUT6
    generic map(
      INIT => X"FFFFFFFF11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(0),
      I4 => data_ex1(0),
      I5 => data_expect_0_mux000031_2044,
      O => N243
    );
  data_expect_63_mux000099 : MUXF7
    port map (
      I0 => N244,
      I1 => N245,
      S => block_mode(1),
      O => data_expect_63_mux000099_2257
    );
  data_expect_63_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(63),
      I3 => data_ex0(63),
      I4 => NlwRenamedSig_OI_data_expect(63),
      O => N244
    );
  data_expect_63_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(63),
      I4 => data_ex1(63),
      I5 => NlwRenamedSig_OI_data_expect(63),
      O => N245
    );
  data_expect_62_mux000099 : MUXF7
    port map (
      I0 => N246,
      I1 => N247,
      S => block_mode(1),
      O => data_expect_62_mux000099_2253
    );
  data_expect_62_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(62),
      I3 => data_ex0(62),
      I4 => NlwRenamedSig_OI_data_expect(62),
      O => N246
    );
  data_expect_62_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(62),
      I4 => data_ex1(62),
      I5 => NlwRenamedSig_OI_data_expect(62),
      O => N247
    );
  data_expect_61_mux000099 : MUXF7
    port map (
      I0 => N248,
      I1 => N249,
      S => block_mode(1),
      O => data_expect_61_mux000099_2249
    );
  data_expect_61_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(61),
      I3 => data_ex0(61),
      I4 => NlwRenamedSig_OI_data_expect(61),
      O => N248
    );
  data_expect_61_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(61),
      I4 => data_ex1(61),
      I5 => NlwRenamedSig_OI_data_expect(61),
      O => N249
    );
  data_expect_60_mux000099 : MUXF7
    port map (
      I0 => N250,
      I1 => N251,
      S => block_mode(1),
      O => data_expect_60_mux000099_2245
    );
  data_expect_60_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(60),
      I3 => data_ex0(60),
      I4 => NlwRenamedSig_OI_data_expect(60),
      O => N250
    );
  data_expect_60_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(60),
      I4 => data_ex1(60),
      I5 => NlwRenamedSig_OI_data_expect(60),
      O => N251
    );
  data_expect_59_mux000099 : MUXF7
    port map (
      I0 => N252,
      I1 => N253,
      S => block_mode(1),
      O => data_expect_59_mux000099_2238
    );
  data_expect_59_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(59),
      I3 => data_ex0(59),
      I4 => NlwRenamedSig_OI_data_expect(59),
      O => N252
    );
  data_expect_59_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(59),
      I4 => data_ex1(59),
      I5 => NlwRenamedSig_OI_data_expect(59),
      O => N253
    );
  data_expect_58_mux000099 : MUXF7
    port map (
      I0 => N254,
      I1 => N255,
      S => block_mode(1),
      O => data_expect_58_mux000099_2234
    );
  data_expect_58_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(58),
      I3 => data_ex0(58),
      I4 => NlwRenamedSig_OI_data_expect(58),
      O => N254
    );
  data_expect_58_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(58),
      I4 => data_ex1(58),
      I5 => NlwRenamedSig_OI_data_expect(58),
      O => N255
    );
  data_expect_57_mux000099 : MUXF7
    port map (
      I0 => N256,
      I1 => N257,
      S => block_mode(1),
      O => data_expect_57_mux000099_2230
    );
  data_expect_57_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(57),
      I3 => data_ex0(57),
      I4 => NlwRenamedSig_OI_data_expect(57),
      O => N256
    );
  data_expect_57_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(57),
      I4 => data_ex1(57),
      I5 => NlwRenamedSig_OI_data_expect(57),
      O => N257
    );
  data_expect_56_mux000099 : MUXF7
    port map (
      I0 => N258,
      I1 => N259,
      S => block_mode(1),
      O => data_expect_56_mux000099_2226
    );
  data_expect_56_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(56),
      I3 => data_ex0(56),
      I4 => NlwRenamedSig_OI_data_expect(56),
      O => N258
    );
  data_expect_56_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(56),
      I4 => data_ex1(56),
      I5 => NlwRenamedSig_OI_data_expect(56),
      O => N259
    );
  data_expect_55_mux000099 : MUXF7
    port map (
      I0 => N260,
      I1 => N261,
      S => block_mode(1),
      O => data_expect_55_mux000099_2222
    );
  data_expect_55_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(55),
      I3 => data_ex0(55),
      I4 => NlwRenamedSig_OI_data_expect(55),
      O => N260
    );
  data_expect_55_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(55),
      I4 => data_ex1(55),
      I5 => NlwRenamedSig_OI_data_expect(55),
      O => N261
    );
  data_expect_54_mux000099 : MUXF7
    port map (
      I0 => N262,
      I1 => N263,
      S => block_mode(1),
      O => data_expect_54_mux000099_2218
    );
  data_expect_54_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(54),
      I3 => data_ex0(54),
      I4 => NlwRenamedSig_OI_data_expect(54),
      O => N262
    );
  data_expect_54_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(54),
      I4 => data_ex1(54),
      I5 => NlwRenamedSig_OI_data_expect(54),
      O => N263
    );
  data_expect_53_mux000099 : MUXF7
    port map (
      I0 => N264,
      I1 => N265,
      S => block_mode(1),
      O => data_expect_53_mux000099_2214
    );
  data_expect_53_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(53),
      I3 => data_ex0(53),
      I4 => NlwRenamedSig_OI_data_expect(53),
      O => N264
    );
  data_expect_53_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(53),
      I4 => data_ex1(53),
      I5 => NlwRenamedSig_OI_data_expect(53),
      O => N265
    );
  data_expect_52_mux000099 : MUXF7
    port map (
      I0 => N266,
      I1 => N267,
      S => block_mode(1),
      O => data_expect_52_mux000099_2210
    );
  data_expect_52_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(52),
      I3 => data_ex0(52),
      I4 => NlwRenamedSig_OI_data_expect(52),
      O => N266
    );
  data_expect_52_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(52),
      I4 => data_ex1(52),
      I5 => NlwRenamedSig_OI_data_expect(52),
      O => N267
    );
  data_expect_51_mux000099 : MUXF7
    port map (
      I0 => N268,
      I1 => N269,
      S => block_mode(1),
      O => data_expect_51_mux000099_2206
    );
  data_expect_51_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(51),
      I3 => data_ex0(51),
      I4 => NlwRenamedSig_OI_data_expect(51),
      O => N268
    );
  data_expect_51_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(51),
      I4 => data_ex1(51),
      I5 => NlwRenamedSig_OI_data_expect(51),
      O => N269
    );
  data_expect_50_mux000099 : MUXF7
    port map (
      I0 => N270,
      I1 => N271,
      S => block_mode(1),
      O => data_expect_50_mux000099_2202
    );
  data_expect_50_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(50),
      I3 => data_ex0(50),
      I4 => NlwRenamedSig_OI_data_expect(50),
      O => N270
    );
  data_expect_50_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(50),
      I4 => data_ex1(50),
      I5 => NlwRenamedSig_OI_data_expect(50),
      O => N271
    );
  data_expect_49_mux000099 : MUXF7
    port map (
      I0 => N272,
      I1 => N273,
      S => block_mode(1),
      O => data_expect_49_mux000099_2195
    );
  data_expect_49_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(49),
      I3 => data_ex0(49),
      I4 => NlwRenamedSig_OI_data_expect(49),
      O => N272
    );
  data_expect_49_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(49),
      I4 => data_ex1(49),
      I5 => NlwRenamedSig_OI_data_expect(49),
      O => N273
    );
  data_expect_48_mux000099 : MUXF7
    port map (
      I0 => N274,
      I1 => N275,
      S => block_mode(1),
      O => data_expect_48_mux000099_2191
    );
  data_expect_48_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(48),
      I3 => data_ex0(48),
      I4 => NlwRenamedSig_OI_data_expect(48),
      O => N274
    );
  data_expect_48_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(48),
      I4 => data_ex1(48),
      I5 => NlwRenamedSig_OI_data_expect(48),
      O => N275
    );
  data_expect_47_mux000099 : MUXF7
    port map (
      I0 => N276,
      I1 => N277,
      S => block_mode(1),
      O => data_expect_47_mux000099_2187
    );
  data_expect_47_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(47),
      I3 => data_ex0(47),
      I4 => NlwRenamedSig_OI_data_expect(47),
      O => N276
    );
  data_expect_47_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(47),
      I4 => data_ex1(47),
      I5 => NlwRenamedSig_OI_data_expect(47),
      O => N277
    );
  data_expect_46_mux000099 : MUXF7
    port map (
      I0 => N278,
      I1 => N279,
      S => block_mode(1),
      O => data_expect_46_mux000099_2183
    );
  data_expect_46_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(46),
      I3 => data_ex0(46),
      I4 => NlwRenamedSig_OI_data_expect(46),
      O => N278
    );
  data_expect_46_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(46),
      I4 => data_ex1(46),
      I5 => NlwRenamedSig_OI_data_expect(46),
      O => N279
    );
  data_expect_45_mux000099 : MUXF7
    port map (
      I0 => N280,
      I1 => N281,
      S => block_mode(1),
      O => data_expect_45_mux000099_2179
    );
  data_expect_45_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(45),
      I3 => data_ex0(45),
      I4 => NlwRenamedSig_OI_data_expect(45),
      O => N280
    );
  data_expect_45_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(45),
      I4 => data_ex1(45),
      I5 => NlwRenamedSig_OI_data_expect(45),
      O => N281
    );
  data_expect_44_mux000099 : MUXF7
    port map (
      I0 => N282,
      I1 => N283,
      S => block_mode(1),
      O => data_expect_44_mux000099_2175
    );
  data_expect_44_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(44),
      I3 => data_ex0(44),
      I4 => NlwRenamedSig_OI_data_expect(44),
      O => N282
    );
  data_expect_44_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(44),
      I4 => data_ex1(44),
      I5 => NlwRenamedSig_OI_data_expect(44),
      O => N283
    );
  data_expect_43_mux000099 : MUXF7
    port map (
      I0 => N284,
      I1 => N285,
      S => block_mode(1),
      O => data_expect_43_mux000099_2171
    );
  data_expect_43_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(43),
      I3 => data_ex0(43),
      I4 => NlwRenamedSig_OI_data_expect(43),
      O => N284
    );
  data_expect_43_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(43),
      I4 => data_ex1(43),
      I5 => NlwRenamedSig_OI_data_expect(43),
      O => N285
    );
  data_expect_42_mux000099 : MUXF7
    port map (
      I0 => N286,
      I1 => N287,
      S => block_mode(1),
      O => data_expect_42_mux000099_2167
    );
  data_expect_42_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(42),
      I3 => data_ex0(42),
      I4 => NlwRenamedSig_OI_data_expect(42),
      O => N286
    );
  data_expect_42_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(42),
      I4 => data_ex1(42),
      I5 => NlwRenamedSig_OI_data_expect(42),
      O => N287
    );
  data_expect_41_mux000099 : MUXF7
    port map (
      I0 => N288,
      I1 => N289,
      S => block_mode(1),
      O => data_expect_41_mux000099_2163
    );
  data_expect_41_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(41),
      I3 => data_ex0(41),
      I4 => NlwRenamedSig_OI_data_expect(41),
      O => N288
    );
  data_expect_41_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(41),
      I4 => data_ex1(41),
      I5 => NlwRenamedSig_OI_data_expect(41),
      O => N289
    );
  data_expect_40_mux000099 : MUXF7
    port map (
      I0 => N290,
      I1 => N291,
      S => block_mode(1),
      O => data_expect_40_mux000099_2159
    );
  data_expect_40_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(40),
      I3 => data_ex0(40),
      I4 => NlwRenamedSig_OI_data_expect(40),
      O => N290
    );
  data_expect_40_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(40),
      I4 => data_ex1(40),
      I5 => NlwRenamedSig_OI_data_expect(40),
      O => N291
    );
  data_expect_39_mux000099 : MUXF7
    port map (
      I0 => N292,
      I1 => N293,
      S => block_mode(1),
      O => data_expect_39_mux000099_2149
    );
  data_expect_39_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(39),
      I3 => data_ex0(39),
      I4 => NlwRenamedSig_OI_data_expect(39),
      O => N292
    );
  data_expect_39_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(39),
      I4 => data_ex1(39),
      I5 => NlwRenamedSig_OI_data_expect(39),
      O => N293
    );
  data_expect_38_mux000099 : MUXF7
    port map (
      I0 => N294,
      I1 => N295,
      S => block_mode(1),
      O => data_expect_38_mux000099_2145
    );
  data_expect_38_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(38),
      I3 => data_ex0(38),
      I4 => NlwRenamedSig_OI_data_expect(38),
      O => N294
    );
  data_expect_38_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(38),
      I4 => data_ex1(38),
      I5 => NlwRenamedSig_OI_data_expect(38),
      O => N295
    );
  data_expect_37_mux000099 : MUXF7
    port map (
      I0 => N296,
      I1 => N297,
      S => block_mode(1),
      O => data_expect_37_mux000099_2141
    );
  data_expect_37_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(37),
      I3 => data_ex0(37),
      I4 => NlwRenamedSig_OI_data_expect(37),
      O => N296
    );
  data_expect_37_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(37),
      I4 => data_ex1(37),
      I5 => NlwRenamedSig_OI_data_expect(37),
      O => N297
    );
  data_expect_36_mux000099 : MUXF7
    port map (
      I0 => N298,
      I1 => N299,
      S => block_mode(1),
      O => data_expect_36_mux000099_2137
    );
  data_expect_36_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(36),
      I3 => data_ex0(36),
      I4 => NlwRenamedSig_OI_data_expect(36),
      O => N298
    );
  data_expect_36_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(36),
      I4 => data_ex1(36),
      I5 => NlwRenamedSig_OI_data_expect(36),
      O => N299
    );
  data_expect_35_mux000099 : MUXF7
    port map (
      I0 => N300,
      I1 => N301,
      S => block_mode(1),
      O => data_expect_35_mux000099_2133
    );
  data_expect_35_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(35),
      I3 => data_ex0(35),
      I4 => NlwRenamedSig_OI_data_expect(35),
      O => N300
    );
  data_expect_35_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(35),
      I4 => data_ex1(35),
      I5 => NlwRenamedSig_OI_data_expect(35),
      O => N301
    );
  data_expect_34_mux000099 : MUXF7
    port map (
      I0 => N302,
      I1 => N303,
      S => block_mode(1),
      O => data_expect_34_mux000099_2129
    );
  data_expect_34_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(34),
      I3 => data_ex0(34),
      I4 => NlwRenamedSig_OI_data_expect(34),
      O => N302
    );
  data_expect_34_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(34),
      I4 => data_ex1(34),
      I5 => NlwRenamedSig_OI_data_expect(34),
      O => N303
    );
  data_expect_33_mux000099 : MUXF7
    port map (
      I0 => N304,
      I1 => N305,
      S => block_mode(1),
      O => data_expect_33_mux000099_2125
    );
  data_expect_33_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(33),
      I3 => data_ex0(33),
      I4 => NlwRenamedSig_OI_data_expect(33),
      O => N304
    );
  data_expect_33_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(33),
      I4 => data_ex1(33),
      I5 => NlwRenamedSig_OI_data_expect(33),
      O => N305
    );
  data_expect_32_mux000099 : MUXF7
    port map (
      I0 => N306,
      I1 => N307,
      S => block_mode(1),
      O => data_expect_32_mux000099_2121
    );
  data_expect_32_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(32),
      I3 => data_ex0(32),
      I4 => NlwRenamedSig_OI_data_expect(32),
      O => N306
    );
  data_expect_32_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(32),
      I4 => data_ex1(32),
      I5 => NlwRenamedSig_OI_data_expect(32),
      O => N307
    );
  data_expect_9_mux000099 : MUXF7
    port map (
      I0 => N308,
      I1 => N309,
      S => block_mode(1),
      O => data_expect_9_mux000099_2268
    );
  data_expect_9_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(9),
      I3 => data_ex0(9),
      I4 => NlwRenamedSig_OI_data_expect(9),
      O => N308
    );
  data_expect_9_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(9),
      I4 => data_ex1(9),
      I5 => NlwRenamedSig_OI_data_expect(9),
      O => N309
    );
  data_expect_7_mux000099 : MUXF7
    port map (
      I0 => N310,
      I1 => N311,
      S => block_mode(1),
      O => data_expect_7_mux000099_2262
    );
  data_expect_7_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(7),
      I3 => data_ex0(7),
      I4 => NlwRenamedSig_OI_data_expect(7),
      O => N310
    );
  data_expect_7_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(7),
      I4 => data_ex1(7),
      I5 => NlwRenamedSig_OI_data_expect(7),
      O => N311
    );
  data_expect_6_mux000099 : MUXF7
    port map (
      I0 => N312,
      I1 => N313,
      S => block_mode(1),
      O => data_expect_6_mux000099_2259
    );
  data_expect_6_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(6),
      I3 => data_ex0(6),
      I4 => NlwRenamedSig_OI_data_expect(6),
      O => N312
    );
  data_expect_6_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(6),
      I4 => data_ex1(6),
      I5 => NlwRenamedSig_OI_data_expect(6),
      O => N313
    );
  data_expect_4_mux000099 : MUXF7
    port map (
      I0 => N314,
      I1 => N315,
      S => block_mode(1),
      O => data_expect_4_mux000099_2197
    );
  data_expect_4_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(4),
      I3 => data_ex0(4),
      I4 => NlwRenamedSig_OI_data_expect(4),
      O => N314
    );
  data_expect_4_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(4),
      I4 => data_ex1(4),
      I5 => NlwRenamedSig_OI_data_expect(4),
      O => N315
    );
  data_expect_3_mux000099 : MUXF7
    port map (
      I0 => N316,
      I1 => N317,
      S => block_mode(1),
      O => data_expect_3_mux000099_2153
    );
  data_expect_3_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(3),
      I3 => data_ex0(3),
      I4 => NlwRenamedSig_OI_data_expect(3),
      O => N316
    );
  data_expect_3_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(3),
      I4 => data_ex1(3),
      I5 => NlwRenamedSig_OI_data_expect(3),
      O => N317
    );
  data_expect_30_mux000099 : MUXF7
    port map (
      I0 => N318,
      I1 => N319,
      S => block_mode(1),
      O => data_expect_30_mux000099_2114
    );
  data_expect_30_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(30),
      I3 => data_ex0(30),
      I4 => NlwRenamedSig_OI_data_expect(30),
      O => N318
    );
  data_expect_30_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(30),
      I4 => data_ex1(30),
      I5 => NlwRenamedSig_OI_data_expect(30),
      O => N319
    );
  data_expect_2_mux000099 : MUXF7
    port map (
      I0 => N320,
      I1 => N321,
      S => block_mode(1),
      O => data_expect_2_mux000099_2110
    );
  data_expect_2_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(2),
      I3 => data_ex0(2),
      I4 => NlwRenamedSig_OI_data_expect(2),
      O => N320
    );
  data_expect_2_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(2),
      I4 => data_ex1(2),
      I5 => NlwRenamedSig_OI_data_expect(2),
      O => N321
    );
  data_expect_28_mux000099 : MUXF7
    port map (
      I0 => N322,
      I1 => N323,
      S => block_mode(1),
      O => data_expect_28_mux000099_2105
    );
  data_expect_28_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(28),
      I3 => data_ex0(28),
      I4 => NlwRenamedSig_OI_data_expect(28),
      O => N322
    );
  data_expect_28_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(28),
      I4 => data_ex1(28),
      I5 => NlwRenamedSig_OI_data_expect(28),
      O => N323
    );
  data_expect_27_mux000099 : MUXF7
    port map (
      I0 => N324,
      I1 => N325,
      S => block_mode(1),
      O => data_expect_27_mux000099_2102
    );
  data_expect_27_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(27),
      I3 => data_ex0(27),
      I4 => NlwRenamedSig_OI_data_expect(27),
      O => N324
    );
  data_expect_27_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(27),
      I4 => data_ex1(27),
      I5 => NlwRenamedSig_OI_data_expect(27),
      O => N325
    );
  data_expect_25_mux000099 : MUXF7
    port map (
      I0 => N326,
      I1 => N327,
      S => block_mode(1),
      O => data_expect_25_mux000099_2096
    );
  data_expect_25_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(25),
      I3 => data_ex0(25),
      I4 => NlwRenamedSig_OI_data_expect(25),
      O => N326
    );
  data_expect_25_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(25),
      I4 => data_ex1(25),
      I5 => NlwRenamedSig_OI_data_expect(25),
      O => N327
    );
  data_expect_22_mux000099 : MUXF7
    port map (
      I0 => N328,
      I1 => N329,
      S => block_mode(1),
      O => data_expect_22_mux000099_2087
    );
  data_expect_22_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(22),
      I3 => data_ex0(22),
      I4 => NlwRenamedSig_OI_data_expect(22),
      O => N328
    );
  data_expect_22_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(22),
      I4 => data_ex1(22),
      I5 => NlwRenamedSig_OI_data_expect(22),
      O => N329
    );
  data_expect_20_mux000099 : MUXF7
    port map (
      I0 => N330,
      I1 => N331,
      S => block_mode(1),
      O => data_expect_20_mux000099_2081
    );
  data_expect_20_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(20),
      I3 => data_ex0(20),
      I4 => NlwRenamedSig_OI_data_expect(20),
      O => N330
    );
  data_expect_20_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(20),
      I4 => data_ex1(20),
      I5 => NlwRenamedSig_OI_data_expect(20),
      O => N331
    );
  data_expect_19_mux000099 : MUXF7
    port map (
      I0 => N332,
      I1 => N333,
      S => block_mode(1),
      O => data_expect_19_mux000099_2075
    );
  data_expect_19_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(19),
      I3 => data_ex0(19),
      I4 => NlwRenamedSig_OI_data_expect(19),
      O => N332
    );
  data_expect_19_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(19),
      I4 => data_ex1(19),
      I5 => NlwRenamedSig_OI_data_expect(19),
      O => N333
    );
  data_expect_17_mux000099 : MUXF7
    port map (
      I0 => N334,
      I1 => N335,
      S => block_mode(1),
      O => data_expect_17_mux000099_2069
    );
  data_expect_17_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(17),
      I3 => data_ex0(17),
      I4 => NlwRenamedSig_OI_data_expect(17),
      O => N334
    );
  data_expect_17_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(17),
      I4 => data_ex1(17),
      I5 => NlwRenamedSig_OI_data_expect(17),
      O => N335
    );
  data_expect_15_mux000099 : MUXF7
    port map (
      I0 => N336,
      I1 => N337,
      S => block_mode(1),
      O => data_expect_15_mux000099_2063
    );
  data_expect_15_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(15),
      I3 => data_ex0(15),
      I4 => NlwRenamedSig_OI_data_expect(15),
      O => N336
    );
  data_expect_15_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(15),
      I4 => data_ex1(15),
      I5 => NlwRenamedSig_OI_data_expect(15),
      O => N337
    );
  data_expect_14_mux000099 : MUXF7
    port map (
      I0 => N338,
      I1 => N339,
      S => block_mode(1),
      O => data_expect_14_mux000099_2060
    );
  data_expect_14_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(14),
      I3 => data_ex0(14),
      I4 => NlwRenamedSig_OI_data_expect(14),
      O => N338
    );
  data_expect_14_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(14),
      I4 => data_ex1(14),
      I5 => NlwRenamedSig_OI_data_expect(14),
      O => N339
    );
  data_expect_13_mux000099 : MUXF7
    port map (
      I0 => N340,
      I1 => N341,
      S => block_mode(1),
      O => data_expect_13_mux000099_2057
    );
  data_expect_13_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(13),
      I3 => data_ex0(13),
      I4 => NlwRenamedSig_OI_data_expect(13),
      O => N340
    );
  data_expect_13_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(13),
      I4 => data_ex1(13),
      I5 => NlwRenamedSig_OI_data_expect(13),
      O => N341
    );
  data_expect_12_mux000099 : MUXF7
    port map (
      I0 => N342,
      I1 => N343,
      S => block_mode(1),
      O => data_expect_12_mux000099_2054
    );
  data_expect_12_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(12),
      I3 => data_ex0(12),
      I4 => NlwRenamedSig_OI_data_expect(12),
      O => N342
    );
  data_expect_12_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(12),
      I4 => data_ex1(12),
      I5 => NlwRenamedSig_OI_data_expect(12),
      O => N343
    );
  data_expect_11_mux000099 : MUXF7
    port map (
      I0 => N344,
      I1 => N345,
      S => block_mode(1),
      O => data_expect_11_mux000099_2051
    );
  data_expect_11_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(11),
      I3 => data_ex0(11),
      I4 => NlwRenamedSig_OI_data_expect(11),
      O => N344
    );
  data_expect_11_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(11),
      I4 => data_ex1(11),
      I5 => NlwRenamedSig_OI_data_expect(11),
      O => N345
    );
  data_expect_10_mux000099 : MUXF7
    port map (
      I0 => N346,
      I1 => N347,
      S => block_mode(1),
      O => data_expect_10_mux000099_2048
    );
  data_expect_10_mux000099_F : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => block_mode(3),
      I1 => block_mode(2),
      I2 => data_ex5(10),
      I3 => data_ex0(10),
      I4 => NlwRenamedSig_OI_data_expect(10),
      O => N346
    );
  data_expect_10_mux000099_G : LUT6
    generic map(
      INIT => X"BBEBBEEE11411444"
    )
    port map (
      I0 => block_mode(3),
      I1 => cnt1(0),
      I2 => block_mode(2),
      I3 => data_ex4(10),
      I4 => data_ex1(10),
      I5 => NlwRenamedSig_OI_data_expect(10),
      O => N347
    );
  Madd_data_ex4_63_32_add0000_lut_0_INV_0 : INV
    port map (
      I => data_ex4(32),
      O => Madd_data_ex4_63_32_add0000_lut(0)
    );
  Madd_data_ex4_31_0_add0000_lut_0_INV_0 : INV
    port map (
      I => data_ex4(0),
      O => Madd_data_ex4_31_0_add0000_lut(0)
    );
  Msub_cnt1_eq_addsub0000_lut_1_INV_0 : INV
    port map (
      I => test_gen_size(1),
      O => Msub_cnt1_eq_addsub0000_lut(1)
    );
  Msub_cnt1_eq_addsub0000_lut_2_INV_0 : INV
    port map (
      I => test_gen_size(2),
      O => Msub_cnt1_eq_addsub0000_lut(2)
    );
  Msub_cnt1_eq_addsub0000_lut_3_INV_0 : INV
    port map (
      I => test_gen_size(3),
      O => Msub_cnt1_eq_addsub0000_lut(3)
    );
  Msub_cnt1_eq_addsub0000_lut_4_INV_0 : INV
    port map (
      I => test_gen_size(4),
      O => Msub_cnt1_eq_addsub0000_lut(4)
    );
  Msub_cnt1_eq_addsub0000_lut_5_INV_0 : INV
    port map (
      I => test_gen_size(5),
      O => Msub_cnt1_eq_addsub0000_lut(5)
    );
  Msub_cnt1_eq_addsub0000_lut_6_INV_0 : INV
    port map (
      I => test_gen_size(6),
      O => Msub_cnt1_eq_addsub0000_lut(6)
    );
  Msub_cnt1_eq_addsub0000_lut_7_INV_0 : INV
    port map (
      I => test_gen_size(7),
      O => Msub_cnt1_eq_addsub0000_lut(7)
    );
  Msub_cnt1_eq_addsub0000_lut_8_INV_0 : INV
    port map (
      I => test_gen_size(8),
      O => Msub_cnt1_eq_addsub0000_lut(8)
    );
  Msub_cnt1_eq_addsub0000_lut_9_INV_0 : INV
    port map (
      I => test_gen_size(9),
      O => Msub_cnt1_eq_addsub0000_lut(9)
    );
  Msub_cnt1_eq_addsub0000_lut_10_INV_0 : INV
    port map (
      I => test_gen_size(10),
      O => Msub_cnt1_eq_addsub0000_lut(10)
    );
  Msub_cnt1_eq_addsub0000_lut_11_INV_0 : INV
    port map (
      I => test_gen_size(11),
      O => Msub_cnt1_eq_addsub0000_lut(11)
    );
  Msub_cnt1_eq_addsub0000_lut_12_INV_0 : INV
    port map (
      I => test_gen_size(12),
      O => Msub_cnt1_eq_addsub0000_lut(12)
    );
  Msub_cnt1_eq_addsub0000_lut_13_INV_0 : INV
    port map (
      I => test_gen_size(13),
      O => Msub_cnt1_eq_addsub0000_lut(13)
    );
  Msub_cnt1_eq_addsub0000_lut_14_INV_0 : INV
    port map (
      I => test_gen_size(14),
      O => Msub_cnt1_eq_addsub0000_lut(14)
    );
  Msub_cnt1_eq_addsub0000_lut_15_INV_0 : INV
    port map (
      I => test_gen_size(15),
      O => Msub_cnt1_eq_addsub0000_lut(15)
    );
  Mcount_block_rd_lut_0_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_block_rd(0),
      O => Mcount_block_rd_lut(0)
    );
  Mcount_cnt1_lut_0_INV_0 : INV
    port map (
      I => cnt1(0),
      O => Mcount_cnt1_lut(0)
    );
  stp_FSM_FFd4_In1_INV_0 : INV
    port map (
      I => test_gen_ctrl(5),
      O => stp_FSM_FFd4_In
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_chn_v3 is
  port (
    clk : in STD_LOGIC := 'X'; 
    fifo_flag_und : in STD_LOGIC := 'X'; 
    fifo_flag_pae : in STD_LOGIC := 'X'; 
    fifo_flag_paf : in STD_LOGIC := 'X'; 
    fdiv_we : out STD_LOGIC; 
    st10 : in STD_LOGIC := 'X'; 
    bx_irq : out STD_LOGIC; 
    st11 : in STD_LOGIC := 'X'; 
    st12 : in STD_LOGIC := 'X'; 
    st13 : in STD_LOGIC := 'X'; 
    st14 : in STD_LOGIC := 'X'; 
    st15 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    rst : out STD_LOGIC; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    st9 : in STD_LOGIC := 'X'; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    fifo_rst : out STD_LOGIC; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    cmd_rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ovr : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    bx_drq_ack : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    rdy : in STD_LOGIC := 'X'; 
    fifo_flag_ef : in STD_LOGIC := 'X'; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    fifo_flag_ff : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    fifo_flag_hf : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    sflag : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end cl_chn_v3;

architecture STRUCTURE of cl_chn_v3 is
  signal N10 : STD_LOGIC; 
  signal bx_irq_or0000_inv : STD_LOGIC; 
  signal bx_irq_or0000_inv130_588 : STD_LOGIC; 
  signal bx_irq_or0000_inv155_589 : STD_LOGIC; 
  signal bx_irq_or0000_inv2_590 : STD_LOGIC; 
  signal bx_irq_or0000_inv27_591 : STD_LOGIC; 
  signal bx_irq_or0000_inv63_592 : STD_LOGIC; 
  signal bx_irq_or0000_inv88_593 : STD_LOGIC; 
  signal c_inv_not0001 : STD_LOGIC; 
  signal c_mask_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_12_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_13_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_mode0_3_Q : STD_LOGIC; 
  signal c_mode0_not0001 : STD_LOGIC; 
  signal c_rst_inv : STD_LOGIC; 
  signal c_rst_norst : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal c_inv : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mask : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  bx_drq_en <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(13) <= NlwRenamedSig_OI_c_mode0_13_Q;
  mode0(12) <= NlwRenamedSig_OI_c_mode0_12_Q;
  mode0(3) <= NlwRenamedSig_OI_c_mode0_3_Q;
  mode0(2) <= NlwRenamedSig_OI_c_mode0_2_Q;
  mode0(0) <= NlwRenamedSig_OI_c_mode0_0_Q;
  c_inv_0 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_inv(0)
    );
  c_inv_1 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_inv(1)
    );
  c_inv_2 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_inv(2)
    );
  c_inv_3 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_inv(3)
    );
  c_inv_4 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_inv(4)
    );
  c_inv_5 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_inv(5)
    );
  c_inv_6 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_inv(6)
    );
  c_inv_7 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_inv(7)
    );
  c_inv_8 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_inv(8)
    );
  c_inv_9 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_inv(9)
    );
  c_inv_10 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_inv(10)
    );
  c_inv_11 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_inv(11)
    );
  c_inv_12 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_inv(12)
    );
  c_inv_13 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_inv(13)
    );
  c_inv_14 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_inv(14)
    );
  c_inv_15 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_inv(15)
    );
  c_mask_0 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(0),
      Q => c_mask(0)
    );
  c_mask_1 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(1),
      Q => c_mask(1)
    );
  c_mask_2 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(2),
      Q => c_mask(2)
    );
  c_mask_3 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(3),
      Q => c_mask(3)
    );
  c_mask_4 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(4),
      Q => c_mask(4)
    );
  c_mask_5 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(5),
      Q => c_mask(5)
    );
  c_mask_6 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(6),
      Q => c_mask(6)
    );
  c_mask_7 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(7),
      Q => c_mask(7)
    );
  c_mask_8 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(8),
      Q => c_mask(8)
    );
  c_mask_9 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(9),
      Q => c_mask(9)
    );
  c_mask_10 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(10),
      Q => c_mask(10)
    );
  c_mask_11 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(11),
      Q => c_mask(11)
    );
  c_mask_12 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(12),
      Q => c_mask(12)
    );
  c_mask_13 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(13),
      Q => c_mask(13)
    );
  c_mask_14 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(14),
      Q => c_mask(14)
    );
  c_mask_15 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => c_rst_inv,
      D => data_in(15),
      Q => c_mask(15)
    );
  c_mode0_0 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(0),
      Q => NlwRenamedSig_OI_c_mode0_0_Q
    );
  c_mode0_2 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(2),
      Q => NlwRenamedSig_OI_c_mode0_2_Q
    );
  c_mode0_3 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(3),
      Q => NlwRenamedSig_OI_c_mode0_3_Q
    );
  c_mode0_12 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(12),
      Q => NlwRenamedSig_OI_c_mode0_12_Q
    );
  c_mode0_13 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => data_in(13),
      Q => NlwRenamedSig_OI_c_mode0_13_Q
    );
  rst_541 : FDR
    port map (
      C => clk,
      D => c_rst_norst,
      R => reset_inv,
      Q => rst
    );
  bx_irq_542 : FDR
    port map (
      C => clk,
      D => NlwRenamedSig_OI_c_mode0_2_Q,
      R => bx_irq_or0000_inv,
      Q => bx_irq
    );
  c_rst_inv1 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0_0_Q,
      O => c_rst_inv
    );
  c_mode0_not00011 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      I3 => N10,
      O => c_mode0_not0001
    );
  c_mask_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => cmd_adr(2),
      I2 => cmd_adr(1),
      I3 => N10,
      O => c_mask_not0001
    );
  c_inv_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => cmd_adr(2),
      I2 => cmd_adr(0),
      I3 => N10,
      O => c_inv_not0001
    );
  c_cnt0_not000121 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => cmd_adr(9),
      I2 => cmd_adr(8),
      I3 => cmd_cmd_data_we,
      O => N10
    );
  bx_irq_or0000_inv2 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => c_mask(0),
      I1 => c_inv(0),
      O => bx_irq_or0000_inv2_590
    );
  bx_irq_or0000_inv27 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(12),
      I1 => c_mask(13),
      I2 => c_mask(14),
      I3 => c_inv(13),
      I4 => c_inv(14),
      I5 => c_inv(12),
      O => bx_irq_or0000_inv27_591
    );
  bx_irq_or0000_inv63 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(2),
      I1 => c_mask(3),
      I2 => c_mask(11),
      I3 => c_inv(3),
      I4 => c_inv(11),
      I5 => c_inv(2),
      O => bx_irq_or0000_inv63_592
    );
  bx_irq_or0000_inv88 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(1),
      I1 => c_mask(10),
      I2 => c_mask(9),
      I3 => c_inv(10),
      I4 => c_inv(9),
      I5 => c_inv(1),
      O => bx_irq_or0000_inv88_593
    );
  bx_irq_or0000_inv130 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(7),
      I1 => c_mask(8),
      I2 => c_mask(15),
      I3 => c_inv(8),
      I4 => c_inv(15),
      I5 => c_inv(7),
      O => bx_irq_or0000_inv130_588
    );
  bx_irq_or0000_inv155 : LUT6
    generic map(
      INIT => X"01051155030F33FF"
    )
    port map (
      I0 => c_mask(4),
      I1 => c_mask(5),
      I2 => c_mask(6),
      I3 => c_inv(5),
      I4 => c_inv(6),
      I5 => c_inv(4),
      O => bx_irq_or0000_inv155_589
    );
  bx_irq_or0000_inv191 : LUT6
    generic map(
      INIT => X"8000000000000000"
    )
    port map (
      I0 => bx_irq_or0000_inv2_590,
      I1 => bx_irq_or0000_inv27_591,
      I2 => bx_irq_or0000_inv63_592,
      I3 => bx_irq_or0000_inv88_593,
      I4 => bx_irq_or0000_inv130_588,
      I5 => bx_irq_or0000_inv155_589,
      O => bx_irq_or0000_inv
    );
  bx_drq_req1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_mode0_13_Q,
      I1 => NlwRenamedSig_OI_c_mode0_3_Q,
      I2 => NlwRenamedSig_OI_c_mode0_12_Q,
      O => bx_drq_req
    );
  c_rst_norst1_INV_0 : INV
    port map (
      I => NlwRenamedSig_OI_c_mode0_0_Q,
      O => c_rst_norst
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity trd_test_ctrl_m1 is
  port (
    di_clk : out STD_LOGIC; 
    di_data_we : out STD_LOGIC; 
    do_start : in STD_LOGIC := 'X'; 
    do_fifo_rst : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    do_flag_rd_und : in STD_LOGIC := 'X'; 
    di_fifo_rst : in STD_LOGIC := 'X'; 
    do_flag_rd_pae : in STD_LOGIC := 'X'; 
    do_flag_rd_paf : in STD_LOGIC := 'X'; 
    bx_irq : out STD_LOGIC; 
    clk_check0 : in STD_LOGIC := 'X'; 
    clk_check1 : in STD_LOGIC := 'X'; 
    clk_check2 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    di_start : in STD_LOGIC := 'X'; 
    do_data_cs : out STD_LOGIC; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    do_clk : out STD_LOGIC; 
    di_flag_wr_ovr : in STD_LOGIC := 'X'; 
    do_flag_rd_ef : in STD_LOGIC := 'X'; 
    di_flag_wr_ef : in STD_LOGIC := 'X'; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    do_flag_rd_ff : in STD_LOGIC := 'X'; 
    di_flag_wr_ff : in STD_LOGIC := 'X'; 
    do_flag_rd_hf : in STD_LOGIC := 'X'; 
    di_flag_wr_hf : in STD_LOGIC := 'X'; 
    do_flag_rd_ovr : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    clk_sys : in STD_LOGIC := 'X'; 
    bx_drq_ack : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    di_flag_wr_und : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    di_flag_wr_pae : in STD_LOGIC := 'X'; 
    di_flag_wr_paf : in STD_LOGIC := 'X'; 
    cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    di_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    do_mode1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    di_mode1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    do_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end trd_test_ctrl_m1;

architecture STRUCTURE of trd_test_ctrl_m1 is
  component cl_chn_v3
    port (
      clk : in STD_LOGIC := 'X'; 
      fifo_flag_und : in STD_LOGIC := 'X'; 
      fifo_flag_pae : in STD_LOGIC := 'X'; 
      fifo_flag_paf : in STD_LOGIC := 'X'; 
      fdiv_we : out STD_LOGIC; 
      st10 : in STD_LOGIC := 'X'; 
      bx_irq : out STD_LOGIC; 
      st11 : in STD_LOGIC := 'X'; 
      st12 : in STD_LOGIC := 'X'; 
      st13 : in STD_LOGIC := 'X'; 
      st14 : in STD_LOGIC := 'X'; 
      st15 : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      rst : out STD_LOGIC; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      st9 : in STD_LOGIC := 'X'; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      fifo_rst : out STD_LOGIC; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      cmd_rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ovr : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      bx_drq_ack : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      rdy : in STD_LOGIC := 'X'; 
      fifo_flag_ef : in STD_LOGIC := 'X'; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      fifo_flag_ff : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      fifo_flag_hf : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      sflag : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      stmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fdiv : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      status : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fmode : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cnt2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component cl_test_generate
    port (
      di_clk : in STD_LOGIC := 'X'; 
      di_data_we : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      di_fifo_rst : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      di_start : in STD_LOGIC := 'X'; 
      di_flag_paf : in STD_LOGIC := 'X'; 
      di_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      test_gen_bl_wr : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test_gen_ctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_gen_size : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_gen_cnt1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_gen_cnt2 : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component cl_test_check
    port (
      clk : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      do_data_en : in STD_LOGIC := 'X'; 
      do_clk : in STD_LOGIC := 'X'; 
      test_check_error : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test_check_bl_ok : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test_check_bl_rd : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test_check_err_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_check_bl_err : out STD_LOGIC_VECTOR ( 31 downto 0 ); 
      test_check_ctrl : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_check_size : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test_check_err_adr : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      do_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component ctrl_freq
    port (
      clk_in : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      freq_en : out STD_LOGIC; 
      clk_sys : in STD_LOGIC := 'X'; 
      freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component ctrl_freq_INST_1
    port (
      clk_in : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      freq_en : out STD_LOGIC; 
      clk_sys : in STD_LOGIC := 'X'; 
      freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component ctrl_freq_INST_2
    port (
      clk_in : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      freq_en : out STD_LOGIC; 
      clk_sys : in STD_LOGIC := 'X'; 
      freq_adc : out STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal cmd_reg_i1_and0000 : STD_LOGIC; 
  signal di_gen_data_we : STD_LOGIC; 
  signal NlwRenamedSignal_do_clk : STD_LOGIC; 
  signal do_cs_rdy_5641 : STD_LOGIC; 
  signal do_cs_rdy_or0000 : STD_LOGIC; 
  signal do_data_cs_and0000 : STD_LOGIC; 
  signal do_data_cs_and0000_inv : STD_LOGIC; 
  signal do_data_en_5710 : STD_LOGIC; 
  signal flag_rdi_ef : STD_LOGIC; 
  signal mux10_5_f7_5826 : STD_LOGIC; 
  signal mux10_6_5827 : STD_LOGIC; 
  signal mux10_7_5828 : STD_LOGIC; 
  signal mux11_5_f7_5829 : STD_LOGIC; 
  signal mux11_6_5830 : STD_LOGIC; 
  signal mux11_7_5831 : STD_LOGIC; 
  signal mux12_5_f7_5832 : STD_LOGIC; 
  signal mux12_6_5833 : STD_LOGIC; 
  signal mux12_7_5834 : STD_LOGIC; 
  signal mux13_5_f7_5835 : STD_LOGIC; 
  signal mux13_6_5836 : STD_LOGIC; 
  signal mux13_7_5837 : STD_LOGIC; 
  signal mux14_5_f7_5838 : STD_LOGIC; 
  signal mux14_6_5839 : STD_LOGIC; 
  signal mux14_7_5840 : STD_LOGIC; 
  signal mux15_5_f7_5841 : STD_LOGIC; 
  signal mux15_6_5842 : STD_LOGIC; 
  signal mux15_7_5843 : STD_LOGIC; 
  signal mux1_5_f7_5844 : STD_LOGIC; 
  signal mux1_6_5845 : STD_LOGIC; 
  signal mux1_7_5846 : STD_LOGIC; 
  signal mux2_5_f7_5847 : STD_LOGIC; 
  signal mux2_6_5848 : STD_LOGIC; 
  signal mux2_7_5849 : STD_LOGIC; 
  signal mux3_5_f7_5850 : STD_LOGIC; 
  signal mux3_6_5851 : STD_LOGIC; 
  signal mux3_7_5852 : STD_LOGIC; 
  signal mux4_5_f7_5853 : STD_LOGIC; 
  signal mux4_6_5854 : STD_LOGIC; 
  signal mux4_7_5855 : STD_LOGIC; 
  signal mux5_5_f7_5856 : STD_LOGIC; 
  signal mux5_6_5857 : STD_LOGIC; 
  signal mux5_7_5858 : STD_LOGIC; 
  signal mux6_5_f7_5859 : STD_LOGIC; 
  signal mux6_6_5860 : STD_LOGIC; 
  signal mux6_7_5861 : STD_LOGIC; 
  signal mux7_5_f7_5862 : STD_LOGIC; 
  signal mux7_6_5863 : STD_LOGIC; 
  signal mux7_7_5864 : STD_LOGIC; 
  signal mux8_5_f7_5865 : STD_LOGIC; 
  signal mux8_6_5866 : STD_LOGIC; 
  signal mux8_7_5867 : STD_LOGIC; 
  signal mux9_5_f7_5868 : STD_LOGIC; 
  signal mux9_6_5869 : STD_LOGIC; 
  signal mux9_7_5870 : STD_LOGIC; 
  signal mux_5_f7_5871 : STD_LOGIC; 
  signal mux_6_5872 : STD_LOGIC; 
  signal mux_7_5873 : STD_LOGIC; 
  signal mux_ctrl_not0001_5876 : STD_LOGIC; 
  signal rst : STD_LOGIC; 
  signal rst_inv : STD_LOGIC; 
  signal test_check_ctrl_0_Q : STD_LOGIC; 
  signal test_check_ctrl_10_Q : STD_LOGIC; 
  signal test_check_ctrl_11_Q : STD_LOGIC; 
  signal test_check_ctrl_7_Q : STD_LOGIC; 
  signal test_check_ctrl_8_Q : STD_LOGIC; 
  signal test_check_ctrl_9_Q : STD_LOGIC; 
  signal test_check_ctrl_not0001 : STD_LOGIC; 
  signal test_check_err_adr_not0001_5999 : STD_LOGIC; 
  signal test_check_size_not0001 : STD_LOGIC; 
  signal test_gen_cnt1_not0001_6113 : STD_LOGIC; 
  signal test_gen_cnt2_not0001_6130 : STD_LOGIC; 
  signal test_gen_ctrl_0_Q : STD_LOGIC; 
  signal test_gen_ctrl_10_Q : STD_LOGIC; 
  signal test_gen_ctrl_11_Q : STD_LOGIC; 
  signal test_gen_ctrl_12_Q : STD_LOGIC; 
  signal test_gen_ctrl_5_Q : STD_LOGIC; 
  signal test_gen_ctrl_6_Q : STD_LOGIC; 
  signal test_gen_ctrl_7_Q : STD_LOGIC; 
  signal test_gen_ctrl_8_Q : STD_LOGIC; 
  signal test_gen_ctrl_9_Q : STD_LOGIC; 
  signal test_gen_ctrl_not0001 : STD_LOGIC; 
  signal test_gen_size_not0001 : STD_LOGIC; 
  signal NLW_fr0_freq_en_UNCONNECTED : STD_LOGIC; 
  signal NLW_fr1_freq_en_UNCONNECTED : STD_LOGIC; 
  signal NLW_fr2_freq_en_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_check_test_check_ctrl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_gen_test_gen_ctrl_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fifo_rst_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_sflag_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_stmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fdiv_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_status_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_fmode_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_chn_cnt2_0_UNCONNECTED : STD_LOGIC; 
  signal cmd_reg0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cmd_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cmd_reg_i0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal cmd_reg_i1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal di_gen_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal freq0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal freq1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal freq2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal mux_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal test_check_bl_err : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal test_check_bl_ok : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal test_check_bl_rd : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal test_check_err_adr : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test_check_err_data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test_check_error : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal test_check_size : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test_gen_bl_wr : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal test_gen_cnt1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test_gen_cnt2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal test_gen_size : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  di_clk <= NlwRenamedSignal_do_clk;
  NlwRenamedSignal_do_clk <= clk;
  do_clk <= NlwRenamedSignal_do_clk;
  XST_GND : GND
    port map (
      G => flag_rdi_ef
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  test_gen_cnt1_0 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(0),
      Q => test_gen_cnt1(0)
    );
  test_gen_cnt1_1 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(1),
      Q => test_gen_cnt1(1)
    );
  test_gen_cnt1_2 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(2),
      Q => test_gen_cnt1(2)
    );
  test_gen_cnt1_3 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(3),
      Q => test_gen_cnt1(3)
    );
  test_gen_cnt1_4 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(4),
      Q => test_gen_cnt1(4)
    );
  test_gen_cnt1_5 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(5),
      Q => test_gen_cnt1(5)
    );
  test_gen_cnt1_6 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(6),
      Q => test_gen_cnt1(6)
    );
  test_gen_cnt1_7 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(7),
      Q => test_gen_cnt1(7)
    );
  test_gen_cnt1_8 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(8),
      Q => test_gen_cnt1(8)
    );
  test_gen_cnt1_9 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(9),
      Q => test_gen_cnt1(9)
    );
  test_gen_cnt1_10 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(10),
      Q => test_gen_cnt1(10)
    );
  test_gen_cnt1_11 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(11),
      Q => test_gen_cnt1(11)
    );
  test_gen_cnt1_12 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(12),
      Q => test_gen_cnt1(12)
    );
  test_gen_cnt1_13 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(13),
      Q => test_gen_cnt1(13)
    );
  test_gen_cnt1_14 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(14),
      Q => test_gen_cnt1(14)
    );
  test_gen_cnt1_15 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt1_not0001_6113,
      D => cmd_data_in(15),
      Q => test_gen_cnt1(15)
    );
  test_check_err_adr_0 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(0),
      Q => test_check_err_adr(0)
    );
  test_check_err_adr_1 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(1),
      Q => test_check_err_adr(1)
    );
  test_check_err_adr_2 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(2),
      Q => test_check_err_adr(2)
    );
  test_check_err_adr_3 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(3),
      Q => test_check_err_adr(3)
    );
  test_check_err_adr_4 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(4),
      Q => test_check_err_adr(4)
    );
  test_check_err_adr_5 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(5),
      Q => test_check_err_adr(5)
    );
  test_check_err_adr_6 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(6),
      Q => test_check_err_adr(6)
    );
  test_check_err_adr_7 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(7),
      Q => test_check_err_adr(7)
    );
  test_check_err_adr_8 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(8),
      Q => test_check_err_adr(8)
    );
  test_check_err_adr_9 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(9),
      Q => test_check_err_adr(9)
    );
  test_check_err_adr_10 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(10),
      Q => test_check_err_adr(10)
    );
  test_check_err_adr_11 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(11),
      Q => test_check_err_adr(11)
    );
  test_check_err_adr_12 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(12),
      Q => test_check_err_adr(12)
    );
  test_check_err_adr_13 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(13),
      Q => test_check_err_adr(13)
    );
  test_check_err_adr_14 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(14),
      Q => test_check_err_adr(14)
    );
  test_check_err_adr_15 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_err_adr_not0001_5999,
      D => cmd_data_in(15),
      Q => test_check_err_adr(15)
    );
  test_gen_cnt2_0 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(0),
      Q => test_gen_cnt2(0)
    );
  test_gen_cnt2_1 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(1),
      Q => test_gen_cnt2(1)
    );
  test_gen_cnt2_2 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(2),
      Q => test_gen_cnt2(2)
    );
  test_gen_cnt2_3 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(3),
      Q => test_gen_cnt2(3)
    );
  test_gen_cnt2_4 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(4),
      Q => test_gen_cnt2(4)
    );
  test_gen_cnt2_5 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(5),
      Q => test_gen_cnt2(5)
    );
  test_gen_cnt2_6 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(6),
      Q => test_gen_cnt2(6)
    );
  test_gen_cnt2_7 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(7),
      Q => test_gen_cnt2(7)
    );
  test_gen_cnt2_8 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(8),
      Q => test_gen_cnt2(8)
    );
  test_gen_cnt2_9 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(9),
      Q => test_gen_cnt2(9)
    );
  test_gen_cnt2_10 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(10),
      Q => test_gen_cnt2(10)
    );
  test_gen_cnt2_11 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(11),
      Q => test_gen_cnt2(11)
    );
  test_gen_cnt2_12 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(12),
      Q => test_gen_cnt2(12)
    );
  test_gen_cnt2_13 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(13),
      Q => test_gen_cnt2(13)
    );
  test_gen_cnt2_14 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(14),
      Q => test_gen_cnt2(14)
    );
  test_gen_cnt2_15 : FDE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_cnt2_not0001_6130,
      D => cmd_data_in(15),
      Q => test_gen_cnt2(15)
    );
  do_data_cs_387 : FDR
    port map (
      C => NlwRenamedSignal_do_clk,
      D => N1,
      R => do_data_cs_and0000,
      Q => do_data_cs
    );
  do_cs_rdy : FDS
    port map (
      C => NlwRenamedSignal_do_clk,
      D => flag_rdi_ef,
      S => do_cs_rdy_or0000,
      Q => do_cs_rdy_5641
    );
  do_data_en : FDR
    port map (
      C => NlwRenamedSignal_do_clk,
      D => N1,
      R => do_data_cs_and0000_inv,
      Q => do_data_en_5710
    );
  cmd_reg1_0 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(0),
      Q => cmd_reg1(0)
    );
  cmd_reg1_1 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(1),
      Q => cmd_reg1(1)
    );
  cmd_reg1_2 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(2),
      Q => cmd_reg1(2)
    );
  cmd_reg1_3 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(3),
      Q => cmd_reg1(3)
    );
  cmd_reg1_4 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(4),
      Q => cmd_reg1(4)
    );
  cmd_reg1_5 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(5),
      Q => cmd_reg1(5)
    );
  cmd_reg1_6 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(6),
      Q => cmd_reg1(6)
    );
  cmd_reg1_7 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(7),
      Q => cmd_reg1(7)
    );
  cmd_reg1_8 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(8),
      Q => cmd_reg1(8)
    );
  cmd_reg1_9 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(9),
      Q => cmd_reg1(9)
    );
  cmd_reg1_10 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(10),
      Q => cmd_reg1(10)
    );
  cmd_reg1_11 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(11),
      Q => cmd_reg1(11)
    );
  cmd_reg1_12 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(12),
      Q => cmd_reg1(12)
    );
  cmd_reg1_13 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(13),
      Q => cmd_reg1(13)
    );
  cmd_reg1_14 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(14),
      Q => cmd_reg1(14)
    );
  cmd_reg1_15 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i1(15),
      Q => cmd_reg1(15)
    );
  test_gen_ctrl_0 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(0),
      R => rst_inv,
      Q => test_gen_ctrl_0_Q
    );
  test_gen_ctrl_5 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(5),
      R => rst_inv,
      Q => test_gen_ctrl_5_Q
    );
  test_gen_ctrl_6 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(6),
      R => rst_inv,
      Q => test_gen_ctrl_6_Q
    );
  test_gen_ctrl_7 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(7),
      R => rst_inv,
      Q => test_gen_ctrl_7_Q
    );
  test_gen_ctrl_8 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(8),
      R => rst_inv,
      Q => test_gen_ctrl_8_Q
    );
  test_gen_ctrl_9 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(9),
      R => rst_inv,
      Q => test_gen_ctrl_9_Q
    );
  test_gen_ctrl_10 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(10),
      R => rst_inv,
      Q => test_gen_ctrl_10_Q
    );
  test_gen_ctrl_11 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(11),
      R => rst_inv,
      Q => test_gen_ctrl_11_Q
    );
  test_gen_ctrl_12 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_ctrl_not0001,
      D => cmd_data_in(12),
      R => rst_inv,
      Q => test_gen_ctrl_12_Q
    );
  test_gen_size_0 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(0),
      R => rst_inv,
      Q => test_gen_size(0)
    );
  test_gen_size_1 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(1),
      R => rst_inv,
      Q => test_gen_size(1)
    );
  test_gen_size_2 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(2),
      R => rst_inv,
      Q => test_gen_size(2)
    );
  test_gen_size_3 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(3),
      R => rst_inv,
      Q => test_gen_size(3)
    );
  test_gen_size_4 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(4),
      R => rst_inv,
      Q => test_gen_size(4)
    );
  test_gen_size_5 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(5),
      R => rst_inv,
      Q => test_gen_size(5)
    );
  test_gen_size_6 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(6),
      R => rst_inv,
      Q => test_gen_size(6)
    );
  test_gen_size_7 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(7),
      R => rst_inv,
      Q => test_gen_size(7)
    );
  test_gen_size_8 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(8),
      R => rst_inv,
      Q => test_gen_size(8)
    );
  test_gen_size_9 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(9),
      R => rst_inv,
      Q => test_gen_size(9)
    );
  test_gen_size_10 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(10),
      R => rst_inv,
      Q => test_gen_size(10)
    );
  test_gen_size_11 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(11),
      R => rst_inv,
      Q => test_gen_size(11)
    );
  test_gen_size_12 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(12),
      R => rst_inv,
      Q => test_gen_size(12)
    );
  test_gen_size_13 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(13),
      R => rst_inv,
      Q => test_gen_size(13)
    );
  test_gen_size_14 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(14),
      R => rst_inv,
      Q => test_gen_size(14)
    );
  test_gen_size_15 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_gen_size_not0001,
      D => cmd_data_in(15),
      R => rst_inv,
      Q => test_gen_size(15)
    );
  mux_ctrl_0 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => mux_ctrl_not0001_5876,
      D => cmd_data_in(0),
      R => rst_inv,
      Q => mux_ctrl(0)
    );
  mux_ctrl_1 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => mux_ctrl_not0001_5876,
      D => cmd_data_in(1),
      R => rst_inv,
      Q => mux_ctrl(1)
    );
  test_check_ctrl_0 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(0),
      R => rst_inv,
      Q => test_check_ctrl_0_Q
    );
  test_check_ctrl_7 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(7),
      R => rst_inv,
      Q => test_check_ctrl_7_Q
    );
  test_check_ctrl_8 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(8),
      R => rst_inv,
      Q => test_check_ctrl_8_Q
    );
  test_check_ctrl_9 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(9),
      R => rst_inv,
      Q => test_check_ctrl_9_Q
    );
  test_check_ctrl_10 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(10),
      R => rst_inv,
      Q => test_check_ctrl_10_Q
    );
  test_check_ctrl_11 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_ctrl_not0001,
      D => cmd_data_in(11),
      R => rst_inv,
      Q => test_check_ctrl_11_Q
    );
  test_check_size_0 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(0),
      R => rst_inv,
      Q => test_check_size(0)
    );
  test_check_size_1 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(1),
      R => rst_inv,
      Q => test_check_size(1)
    );
  test_check_size_2 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(2),
      R => rst_inv,
      Q => test_check_size(2)
    );
  test_check_size_3 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(3),
      R => rst_inv,
      Q => test_check_size(3)
    );
  test_check_size_4 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(4),
      R => rst_inv,
      Q => test_check_size(4)
    );
  test_check_size_5 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(5),
      R => rst_inv,
      Q => test_check_size(5)
    );
  test_check_size_6 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(6),
      R => rst_inv,
      Q => test_check_size(6)
    );
  test_check_size_7 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(7),
      R => rst_inv,
      Q => test_check_size(7)
    );
  test_check_size_8 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(8),
      R => rst_inv,
      Q => test_check_size(8)
    );
  test_check_size_9 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(9),
      R => rst_inv,
      Q => test_check_size(9)
    );
  test_check_size_10 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(10),
      R => rst_inv,
      Q => test_check_size(10)
    );
  test_check_size_11 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(11),
      R => rst_inv,
      Q => test_check_size(11)
    );
  test_check_size_12 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(12),
      R => rst_inv,
      Q => test_check_size(12)
    );
  test_check_size_13 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(13),
      R => rst_inv,
      Q => test_check_size(13)
    );
  test_check_size_14 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(14),
      R => rst_inv,
      Q => test_check_size(14)
    );
  test_check_size_15 : FDRE
    port map (
      C => NlwRenamedSignal_do_clk,
      CE => test_check_size_not0001,
      D => cmd_data_in(15),
      R => rst_inv,
      Q => test_check_size(15)
    );
  cmd_reg0_0 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(0),
      Q => cmd_reg0(0)
    );
  cmd_reg0_1 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(1),
      Q => cmd_reg0(1)
    );
  cmd_reg0_2 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(2),
      Q => cmd_reg0(2)
    );
  cmd_reg0_3 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(3),
      Q => cmd_reg0(3)
    );
  cmd_reg0_4 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(4),
      Q => cmd_reg0(4)
    );
  cmd_reg0_5 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(5),
      Q => cmd_reg0(5)
    );
  cmd_reg0_6 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(6),
      Q => cmd_reg0(6)
    );
  cmd_reg0_7 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(7),
      Q => cmd_reg0(7)
    );
  cmd_reg0_8 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(8),
      Q => cmd_reg0(8)
    );
  cmd_reg0_9 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(9),
      Q => cmd_reg0(9)
    );
  cmd_reg0_10 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(10),
      Q => cmd_reg0(10)
    );
  cmd_reg0_11 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(11),
      Q => cmd_reg0(11)
    );
  cmd_reg0_12 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(12),
      Q => cmd_reg0(12)
    );
  cmd_reg0_13 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(13),
      Q => cmd_reg0(13)
    );
  cmd_reg0_14 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(14),
      Q => cmd_reg0(14)
    );
  cmd_reg0_15 : FD
    port map (
      C => NlwRenamedSignal_do_clk,
      D => cmd_reg_i0(15),
      Q => cmd_reg0(15)
    );
  mux1_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(26),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(10),
      I4 => test_check_bl_rd(10),
      I5 => test_check_bl_err(26),
      O => mux1_7_5846
    );
  mux1_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(26),
      I2 => cmd_adr(0),
      I3 => test_check_error(10),
      I4 => test_check_bl_ok(10),
      I5 => test_check_error(26),
      O => mux1_6_5845
    );
  mux_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(16),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(0),
      I4 => test_check_bl_rd(0),
      I5 => test_check_bl_err(16),
      O => mux_7_5873
    );
  mux_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(16),
      I2 => cmd_adr(0),
      I3 => test_check_error(0),
      I4 => test_check_bl_ok(0),
      I5 => test_check_error(16),
      O => mux_6_5872
    );
  mux4_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(29),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(13),
      I4 => test_check_bl_rd(13),
      I5 => test_check_bl_err(29),
      O => mux4_7_5855
    );
  mux4_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(29),
      I2 => cmd_adr(0),
      I3 => test_check_error(13),
      I4 => test_check_bl_ok(13),
      I5 => test_check_error(29),
      O => mux4_6_5854
    );
  mux2_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(27),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(11),
      I4 => test_check_bl_rd(11),
      I5 => test_check_bl_err(27),
      O => mux2_7_5849
    );
  mux2_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(27),
      I2 => cmd_adr(0),
      I3 => test_check_error(11),
      I4 => test_check_bl_ok(11),
      I5 => test_check_error(27),
      O => mux2_6_5848
    );
  mux3_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(28),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(12),
      I4 => test_check_bl_rd(12),
      I5 => test_check_bl_err(28),
      O => mux3_7_5852
    );
  mux3_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(28),
      I2 => cmd_adr(0),
      I3 => test_check_error(12),
      I4 => test_check_bl_ok(12),
      I5 => test_check_error(28),
      O => mux3_6_5851
    );
  mux7_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(17),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(1),
      I4 => test_check_bl_rd(1),
      I5 => test_check_bl_err(17),
      O => mux7_7_5864
    );
  mux7_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(17),
      I2 => cmd_adr(0),
      I3 => test_check_error(1),
      I4 => test_check_bl_ok(1),
      I5 => test_check_error(17),
      O => mux7_6_5863
    );
  mux5_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(30),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(14),
      I4 => test_check_bl_rd(14),
      I5 => test_check_bl_err(30),
      O => mux5_7_5858
    );
  mux5_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(30),
      I2 => cmd_adr(0),
      I3 => test_check_error(14),
      I4 => test_check_bl_ok(14),
      I5 => test_check_error(30),
      O => mux5_6_5857
    );
  mux6_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(31),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(15),
      I4 => test_check_bl_rd(15),
      I5 => test_check_bl_err(31),
      O => mux6_7_5861
    );
  mux6_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(31),
      I2 => cmd_adr(0),
      I3 => test_check_error(15),
      I4 => test_check_bl_ok(15),
      I5 => test_check_error(31),
      O => mux6_6_5860
    );
  mux10_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(20),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(4),
      I4 => test_check_bl_rd(4),
      I5 => test_check_bl_err(20),
      O => mux10_7_5828
    );
  mux10_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(20),
      I2 => cmd_adr(0),
      I3 => test_check_error(4),
      I4 => test_check_bl_ok(4),
      I5 => test_check_error(20),
      O => mux10_6_5827
    );
  mux8_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(18),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(2),
      I4 => test_check_bl_rd(2),
      I5 => test_check_bl_err(18),
      O => mux8_7_5867
    );
  mux8_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(18),
      I2 => cmd_adr(0),
      I3 => test_check_error(2),
      I4 => test_check_bl_ok(2),
      I5 => test_check_error(18),
      O => mux8_6_5866
    );
  mux9_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(19),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(3),
      I4 => test_check_bl_rd(3),
      I5 => test_check_bl_err(19),
      O => mux9_7_5870
    );
  mux9_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(19),
      I2 => cmd_adr(0),
      I3 => test_check_error(3),
      I4 => test_check_bl_ok(3),
      I5 => test_check_error(19),
      O => mux9_6_5869
    );
  mux13_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(23),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(7),
      I4 => test_check_bl_rd(7),
      I5 => test_check_bl_err(23),
      O => mux13_7_5837
    );
  mux13_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(23),
      I2 => cmd_adr(0),
      I3 => test_check_error(7),
      I4 => test_check_bl_ok(7),
      I5 => test_check_error(23),
      O => mux13_6_5836
    );
  mux11_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(21),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(5),
      I4 => test_check_bl_rd(5),
      I5 => test_check_bl_err(21),
      O => mux11_7_5831
    );
  mux11_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(21),
      I2 => cmd_adr(0),
      I3 => test_check_error(5),
      I4 => test_check_bl_ok(5),
      I5 => test_check_error(21),
      O => mux11_6_5830
    );
  mux12_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(22),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(6),
      I4 => test_check_bl_rd(6),
      I5 => test_check_bl_err(22),
      O => mux12_7_5834
    );
  mux12_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(22),
      I2 => cmd_adr(0),
      I3 => test_check_error(6),
      I4 => test_check_bl_ok(6),
      I5 => test_check_error(22),
      O => mux12_6_5833
    );
  mux14_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(24),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(8),
      I4 => test_check_bl_rd(8),
      I5 => test_check_bl_err(24),
      O => mux14_7_5840
    );
  mux14_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(24),
      I2 => cmd_adr(0),
      I3 => test_check_error(8),
      I4 => test_check_bl_ok(8),
      I5 => test_check_error(24),
      O => mux14_6_5839
    );
  mux15_7 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_rd(25),
      I2 => cmd_adr(0),
      I3 => test_check_bl_err(9),
      I4 => test_check_bl_rd(9),
      I5 => test_check_bl_err(25),
      O => mux15_7_5843
    );
  mux15_6 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => test_check_bl_ok(25),
      I2 => cmd_adr(0),
      I3 => test_check_error(9),
      I4 => test_check_bl_ok(9),
      I5 => test_check_error(25),
      O => mux15_6_5842
    );
  chn : cl_chn_v3
    port map (
      clk => NlwRenamedSignal_do_clk,
      fifo_flag_und => flag_rdi_ef,
      fifo_flag_pae => flag_rdi_ef,
      fifo_flag_paf => flag_rdi_ef,
      fdiv_we => NLW_chn_fdiv_we_UNCONNECTED,
      st10 => flag_rdi_ef,
      bx_irq => bx_irq,
      st11 => flag_rdi_ef,
      st12 => flag_rdi_ef,
      st13 => flag_rdi_ef,
      st14 => flag_rdi_ef,
      st15 => flag_rdi_ef,
      reset => reset,
      rst => rst,
      cmd_cmd_data_we => cmd_cmd_data_we,
      st9 => flag_rdi_ef,
      cmd_status_cs => cmd_status_cs,
      fifo_rst => NLW_chn_fifo_rst_UNCONNECTED,
      cmd_data_cs => cmd_data_cs,
      cmd_rdy => N1,
      fifo_flag_ovr => flag_rdi_ef,
      bx_drq_en => bx_drq_en,
      bx_drq_ack => bx_drq_ack,
      cmd_data_oe => cmd_data_oe,
      cmd_cmd_data_cs => cmd_cmd_data_cs,
      rdy => flag_rdi_ef,
      fifo_flag_ef => flag_rdi_ef,
      cmd_cmd_adr_we => cmd_cmd_adr_we,
      fifo_flag_ff => flag_rdi_ef,
      cmd_data_we => cmd_data_we,
      fifo_flag_hf => flag_rdi_ef,
      bx_drq_req => bx_drq_req,
      sflag(15) => NLW_chn_sflag_15_UNCONNECTED,
      sflag(14) => NLW_chn_sflag_14_UNCONNECTED,
      sflag(13) => NLW_chn_sflag_13_UNCONNECTED,
      sflag(12) => NLW_chn_sflag_12_UNCONNECTED,
      sflag(11) => NLW_chn_sflag_11_UNCONNECTED,
      sflag(10) => NLW_chn_sflag_10_UNCONNECTED,
      sflag(9) => NLW_chn_sflag_9_UNCONNECTED,
      sflag(8) => NLW_chn_sflag_8_UNCONNECTED,
      sflag(7) => NLW_chn_sflag_7_UNCONNECTED,
      sflag(6) => NLW_chn_sflag_6_UNCONNECTED,
      sflag(5) => NLW_chn_sflag_5_UNCONNECTED,
      sflag(4) => NLW_chn_sflag_4_UNCONNECTED,
      sflag(3) => NLW_chn_sflag_3_UNCONNECTED,
      sflag(2) => NLW_chn_sflag_2_UNCONNECTED,
      sflag(1) => NLW_chn_sflag_1_UNCONNECTED,
      sflag(0) => NLW_chn_sflag_0_UNCONNECTED,
      stmode(15) => NLW_chn_stmode_15_UNCONNECTED,
      stmode(14) => NLW_chn_stmode_14_UNCONNECTED,
      stmode(13) => NLW_chn_stmode_13_UNCONNECTED,
      stmode(12) => NLW_chn_stmode_12_UNCONNECTED,
      stmode(11) => NLW_chn_stmode_11_UNCONNECTED,
      stmode(10) => NLW_chn_stmode_10_UNCONNECTED,
      stmode(9) => NLW_chn_stmode_9_UNCONNECTED,
      stmode(8) => NLW_chn_stmode_8_UNCONNECTED,
      stmode(7) => NLW_chn_stmode_7_UNCONNECTED,
      stmode(6) => NLW_chn_stmode_6_UNCONNECTED,
      stmode(5) => NLW_chn_stmode_5_UNCONNECTED,
      stmode(4) => NLW_chn_stmode_4_UNCONNECTED,
      stmode(3) => NLW_chn_stmode_3_UNCONNECTED,
      stmode(2) => NLW_chn_stmode_2_UNCONNECTED,
      stmode(1) => NLW_chn_stmode_1_UNCONNECTED,
      stmode(0) => NLW_chn_stmode_0_UNCONNECTED,
      mode0(15) => mode0(15),
      mode0(14) => mode0(14),
      mode0(13) => mode0(13),
      mode0(12) => mode0(12),
      mode0(11) => mode0(11),
      mode0(10) => mode0(10),
      mode0(9) => mode0(9),
      mode0(8) => mode0(8),
      mode0(7) => mode0(7),
      mode0(6) => mode0(6),
      mode0(5) => mode0(5),
      mode0(4) => mode0(4),
      mode0(3) => mode0(3),
      mode0(2) => mode0(2),
      mode0(1) => mode0(1),
      mode0(0) => mode0(0),
      mode1(15) => mode1(15),
      mode1(14) => mode1(14),
      mode1(13) => mode1(13),
      mode1(12) => mode1(12),
      mode1(11) => mode1(11),
      mode1(10) => mode1(10),
      mode1(9) => mode1(9),
      mode1(8) => mode1(8),
      mode1(7) => mode1(7),
      mode1(6) => mode1(6),
      mode1(5) => mode1(5),
      mode1(4) => mode1(4),
      mode1(3) => mode1(3),
      mode1(2) => mode1(2),
      mode1(1) => mode1(1),
      mode1(0) => mode1(0),
      mode2(15) => mode2(15),
      mode2(14) => mode2(14),
      mode2(13) => mode2(13),
      mode2(12) => mode2(12),
      mode2(11) => mode2(11),
      mode2(10) => mode2(10),
      mode2(9) => mode2(9),
      mode2(8) => mode2(8),
      mode2(7) => mode2(7),
      mode2(6) => mode2(6),
      mode2(5) => mode2(5),
      mode2(4) => mode2(4),
      mode2(3) => mode2(3),
      mode2(2) => mode2(2),
      mode2(1) => mode2(1),
      mode2(0) => mode2(0),
      mode3(15) => mode3(15),
      mode3(14) => mode3(14),
      mode3(13) => mode3(13),
      mode3(12) => mode3(12),
      mode3(11) => mode3(11),
      mode3(10) => mode3(10),
      mode3(9) => mode3(9),
      mode3(8) => mode3(8),
      mode3(7) => mode3(7),
      mode3(6) => mode3(6),
      mode3(5) => mode3(5),
      mode3(4) => mode3(4),
      mode3(3) => mode3(3),
      mode3(2) => mode3(2),
      mode3(1) => mode3(1),
      mode3(0) => mode3(0),
      fdiv(15) => NLW_chn_fdiv_15_UNCONNECTED,
      fdiv(14) => NLW_chn_fdiv_14_UNCONNECTED,
      fdiv(13) => NLW_chn_fdiv_13_UNCONNECTED,
      fdiv(12) => NLW_chn_fdiv_12_UNCONNECTED,
      fdiv(11) => NLW_chn_fdiv_11_UNCONNECTED,
      fdiv(10) => NLW_chn_fdiv_10_UNCONNECTED,
      fdiv(9) => NLW_chn_fdiv_9_UNCONNECTED,
      fdiv(8) => NLW_chn_fdiv_8_UNCONNECTED,
      fdiv(7) => NLW_chn_fdiv_7_UNCONNECTED,
      fdiv(6) => NLW_chn_fdiv_6_UNCONNECTED,
      fdiv(5) => NLW_chn_fdiv_5_UNCONNECTED,
      fdiv(4) => NLW_chn_fdiv_4_UNCONNECTED,
      fdiv(3) => NLW_chn_fdiv_3_UNCONNECTED,
      fdiv(2) => NLW_chn_fdiv_2_UNCONNECTED,
      fdiv(1) => NLW_chn_fdiv_1_UNCONNECTED,
      fdiv(0) => NLW_chn_fdiv_0_UNCONNECTED,
      status(15) => NLW_chn_status_15_UNCONNECTED,
      status(14) => NLW_chn_status_14_UNCONNECTED,
      status(13) => NLW_chn_status_13_UNCONNECTED,
      status(12) => NLW_chn_status_12_UNCONNECTED,
      status(11) => NLW_chn_status_11_UNCONNECTED,
      status(10) => NLW_chn_status_10_UNCONNECTED,
      status(9) => NLW_chn_status_9_UNCONNECTED,
      status(8) => NLW_chn_status_8_UNCONNECTED,
      status(7) => NLW_chn_status_7_UNCONNECTED,
      status(6) => NLW_chn_status_6_UNCONNECTED,
      status(5) => NLW_chn_status_5_UNCONNECTED,
      status(4) => NLW_chn_status_4_UNCONNECTED,
      status(3) => NLW_chn_status_3_UNCONNECTED,
      status(2) => NLW_chn_status_2_UNCONNECTED,
      status(1) => NLW_chn_status_1_UNCONNECTED,
      status(0) => NLW_chn_status_0_UNCONNECTED,
      fmode(15) => NLW_chn_fmode_15_UNCONNECTED,
      fmode(14) => NLW_chn_fmode_14_UNCONNECTED,
      fmode(13) => NLW_chn_fmode_13_UNCONNECTED,
      fmode(12) => NLW_chn_fmode_12_UNCONNECTED,
      fmode(11) => NLW_chn_fmode_11_UNCONNECTED,
      fmode(10) => NLW_chn_fmode_10_UNCONNECTED,
      fmode(9) => NLW_chn_fmode_9_UNCONNECTED,
      fmode(8) => NLW_chn_fmode_8_UNCONNECTED,
      fmode(7) => NLW_chn_fmode_7_UNCONNECTED,
      fmode(6) => NLW_chn_fmode_6_UNCONNECTED,
      fmode(5) => NLW_chn_fmode_5_UNCONNECTED,
      fmode(4) => NLW_chn_fmode_4_UNCONNECTED,
      fmode(3) => NLW_chn_fmode_3_UNCONNECTED,
      fmode(2) => NLW_chn_fmode_2_UNCONNECTED,
      fmode(1) => NLW_chn_fmode_1_UNCONNECTED,
      fmode(0) => NLW_chn_fmode_0_UNCONNECTED,
      cnt0(15) => NLW_chn_cnt0_15_UNCONNECTED,
      cnt0(14) => NLW_chn_cnt0_14_UNCONNECTED,
      cnt0(13) => NLW_chn_cnt0_13_UNCONNECTED,
      cnt0(12) => NLW_chn_cnt0_12_UNCONNECTED,
      cnt0(11) => NLW_chn_cnt0_11_UNCONNECTED,
      cnt0(10) => NLW_chn_cnt0_10_UNCONNECTED,
      cnt0(9) => NLW_chn_cnt0_9_UNCONNECTED,
      cnt0(8) => NLW_chn_cnt0_8_UNCONNECTED,
      cnt0(7) => NLW_chn_cnt0_7_UNCONNECTED,
      cnt0(6) => NLW_chn_cnt0_6_UNCONNECTED,
      cnt0(5) => NLW_chn_cnt0_5_UNCONNECTED,
      cnt0(4) => NLW_chn_cnt0_4_UNCONNECTED,
      cnt0(3) => NLW_chn_cnt0_3_UNCONNECTED,
      cnt0(2) => NLW_chn_cnt0_2_UNCONNECTED,
      cnt0(1) => NLW_chn_cnt0_1_UNCONNECTED,
      cnt0(0) => NLW_chn_cnt0_0_UNCONNECTED,
      cnt1(15) => NLW_chn_cnt1_15_UNCONNECTED,
      cnt1(14) => NLW_chn_cnt1_14_UNCONNECTED,
      cnt1(13) => NLW_chn_cnt1_13_UNCONNECTED,
      cnt1(12) => NLW_chn_cnt1_12_UNCONNECTED,
      cnt1(11) => NLW_chn_cnt1_11_UNCONNECTED,
      cnt1(10) => NLW_chn_cnt1_10_UNCONNECTED,
      cnt1(9) => NLW_chn_cnt1_9_UNCONNECTED,
      cnt1(8) => NLW_chn_cnt1_8_UNCONNECTED,
      cnt1(7) => NLW_chn_cnt1_7_UNCONNECTED,
      cnt1(6) => NLW_chn_cnt1_6_UNCONNECTED,
      cnt1(5) => NLW_chn_cnt1_5_UNCONNECTED,
      cnt1(4) => NLW_chn_cnt1_4_UNCONNECTED,
      cnt1(3) => NLW_chn_cnt1_3_UNCONNECTED,
      cnt1(2) => NLW_chn_cnt1_2_UNCONNECTED,
      cnt1(1) => NLW_chn_cnt1_1_UNCONNECTED,
      cnt1(0) => NLW_chn_cnt1_0_UNCONNECTED,
      cnt2(15) => NLW_chn_cnt2_15_UNCONNECTED,
      cnt2(14) => NLW_chn_cnt2_14_UNCONNECTED,
      cnt2(13) => NLW_chn_cnt2_13_UNCONNECTED,
      cnt2(12) => NLW_chn_cnt2_12_UNCONNECTED,
      cnt2(11) => NLW_chn_cnt2_11_UNCONNECTED,
      cnt2(10) => NLW_chn_cnt2_10_UNCONNECTED,
      cnt2(9) => NLW_chn_cnt2_9_UNCONNECTED,
      cnt2(8) => NLW_chn_cnt2_8_UNCONNECTED,
      cnt2(7) => NLW_chn_cnt2_7_UNCONNECTED,
      cnt2(6) => NLW_chn_cnt2_6_UNCONNECTED,
      cnt2(5) => NLW_chn_cnt2_5_UNCONNECTED,
      cnt2(4) => NLW_chn_cnt2_4_UNCONNECTED,
      cnt2(3) => NLW_chn_cnt2_3_UNCONNECTED,
      cnt2(2) => NLW_chn_cnt2_2_UNCONNECTED,
      cnt2(1) => NLW_chn_cnt2_1_UNCONNECTED,
      cnt2(0) => NLW_chn_cnt2_0_UNCONNECTED,
      data_in(15) => cmd_data_in(15),
      data_in(14) => cmd_data_in(14),
      data_in(13) => cmd_data_in(13),
      data_in(12) => cmd_data_in(12),
      data_in(11) => cmd_data_in(11),
      data_in(10) => cmd_data_in(10),
      data_in(9) => cmd_data_in(9),
      data_in(8) => cmd_data_in(8),
      data_in(7) => cmd_data_in(7),
      data_in(6) => cmd_data_in(6),
      data_in(5) => cmd_data_in(5),
      data_in(4) => cmd_data_in(4),
      data_in(3) => cmd_data_in(3),
      data_in(2) => cmd_data_in(2),
      data_in(1) => cmd_data_in(1),
      data_in(0) => cmd_data_in(0),
      cmd_adr(9) => cmd_adr(9),
      cmd_adr(8) => cmd_adr(8),
      cmd_adr(7) => cmd_adr(7),
      cmd_adr(6) => cmd_adr(6),
      cmd_adr(5) => cmd_adr(5),
      cmd_adr(4) => cmd_adr(4),
      cmd_adr(3) => cmd_adr(3),
      cmd_adr(2) => cmd_adr(2),
      cmd_adr(1) => cmd_adr(1),
      cmd_adr(0) => cmd_adr(0)
    );
  test_gen : cl_test_generate
    port map (
      di_clk => NlwRenamedSignal_do_clk,
      di_data_we => di_gen_data_we,
      clk => NlwRenamedSignal_do_clk,
      di_fifo_rst => di_fifo_rst,
      reset => rst,
      di_start => di_start,
      di_flag_paf => di_flag_wr_paf,
      di_data(63) => di_gen_data(63),
      di_data(62) => di_gen_data(62),
      di_data(61) => di_gen_data(61),
      di_data(60) => di_gen_data(60),
      di_data(59) => di_gen_data(59),
      di_data(58) => di_gen_data(58),
      di_data(57) => di_gen_data(57),
      di_data(56) => di_gen_data(56),
      di_data(55) => di_gen_data(55),
      di_data(54) => di_gen_data(54),
      di_data(53) => di_gen_data(53),
      di_data(52) => di_gen_data(52),
      di_data(51) => di_gen_data(51),
      di_data(50) => di_gen_data(50),
      di_data(49) => di_gen_data(49),
      di_data(48) => di_gen_data(48),
      di_data(47) => di_gen_data(47),
      di_data(46) => di_gen_data(46),
      di_data(45) => di_gen_data(45),
      di_data(44) => di_gen_data(44),
      di_data(43) => di_gen_data(43),
      di_data(42) => di_gen_data(42),
      di_data(41) => di_gen_data(41),
      di_data(40) => di_gen_data(40),
      di_data(39) => di_gen_data(39),
      di_data(38) => di_gen_data(38),
      di_data(37) => di_gen_data(37),
      di_data(36) => di_gen_data(36),
      di_data(35) => di_gen_data(35),
      di_data(34) => di_gen_data(34),
      di_data(33) => di_gen_data(33),
      di_data(32) => di_gen_data(32),
      di_data(31) => di_gen_data(31),
      di_data(30) => di_gen_data(30),
      di_data(29) => di_gen_data(29),
      di_data(28) => di_gen_data(28),
      di_data(27) => di_gen_data(27),
      di_data(26) => di_gen_data(26),
      di_data(25) => di_gen_data(25),
      di_data(24) => di_gen_data(24),
      di_data(23) => di_gen_data(23),
      di_data(22) => di_gen_data(22),
      di_data(21) => di_gen_data(21),
      di_data(20) => di_gen_data(20),
      di_data(19) => di_gen_data(19),
      di_data(18) => di_gen_data(18),
      di_data(17) => di_gen_data(17),
      di_data(16) => di_gen_data(16),
      di_data(15) => di_gen_data(15),
      di_data(14) => di_gen_data(14),
      di_data(13) => di_gen_data(13),
      di_data(12) => di_gen_data(12),
      di_data(11) => di_gen_data(11),
      di_data(10) => di_gen_data(10),
      di_data(9) => di_gen_data(9),
      di_data(8) => di_gen_data(8),
      di_data(7) => di_gen_data(7),
      di_data(6) => di_gen_data(6),
      di_data(5) => di_gen_data(5),
      di_data(4) => di_gen_data(4),
      di_data(3) => di_gen_data(3),
      di_data(2) => di_gen_data(2),
      di_data(1) => di_gen_data(1),
      di_data(0) => di_gen_data(0),
      test_gen_bl_wr(31) => test_gen_bl_wr(31),
      test_gen_bl_wr(30) => test_gen_bl_wr(30),
      test_gen_bl_wr(29) => test_gen_bl_wr(29),
      test_gen_bl_wr(28) => test_gen_bl_wr(28),
      test_gen_bl_wr(27) => test_gen_bl_wr(27),
      test_gen_bl_wr(26) => test_gen_bl_wr(26),
      test_gen_bl_wr(25) => test_gen_bl_wr(25),
      test_gen_bl_wr(24) => test_gen_bl_wr(24),
      test_gen_bl_wr(23) => test_gen_bl_wr(23),
      test_gen_bl_wr(22) => test_gen_bl_wr(22),
      test_gen_bl_wr(21) => test_gen_bl_wr(21),
      test_gen_bl_wr(20) => test_gen_bl_wr(20),
      test_gen_bl_wr(19) => test_gen_bl_wr(19),
      test_gen_bl_wr(18) => test_gen_bl_wr(18),
      test_gen_bl_wr(17) => test_gen_bl_wr(17),
      test_gen_bl_wr(16) => test_gen_bl_wr(16),
      test_gen_bl_wr(15) => test_gen_bl_wr(15),
      test_gen_bl_wr(14) => test_gen_bl_wr(14),
      test_gen_bl_wr(13) => test_gen_bl_wr(13),
      test_gen_bl_wr(12) => test_gen_bl_wr(12),
      test_gen_bl_wr(11) => test_gen_bl_wr(11),
      test_gen_bl_wr(10) => test_gen_bl_wr(10),
      test_gen_bl_wr(9) => test_gen_bl_wr(9),
      test_gen_bl_wr(8) => test_gen_bl_wr(8),
      test_gen_bl_wr(7) => test_gen_bl_wr(7),
      test_gen_bl_wr(6) => test_gen_bl_wr(6),
      test_gen_bl_wr(5) => test_gen_bl_wr(5),
      test_gen_bl_wr(4) => test_gen_bl_wr(4),
      test_gen_bl_wr(3) => test_gen_bl_wr(3),
      test_gen_bl_wr(2) => test_gen_bl_wr(2),
      test_gen_bl_wr(1) => test_gen_bl_wr(1),
      test_gen_bl_wr(0) => test_gen_bl_wr(0),
      test_gen_ctrl(15) => NLW_test_gen_test_gen_ctrl_15_UNCONNECTED,
      test_gen_ctrl(14) => NLW_test_gen_test_gen_ctrl_14_UNCONNECTED,
      test_gen_ctrl(13) => NLW_test_gen_test_gen_ctrl_13_UNCONNECTED,
      test_gen_ctrl(12) => test_gen_ctrl_12_Q,
      test_gen_ctrl(11) => test_gen_ctrl_11_Q,
      test_gen_ctrl(10) => test_gen_ctrl_10_Q,
      test_gen_ctrl(9) => test_gen_ctrl_9_Q,
      test_gen_ctrl(8) => test_gen_ctrl_8_Q,
      test_gen_ctrl(7) => test_gen_ctrl_7_Q,
      test_gen_ctrl(6) => test_gen_ctrl_6_Q,
      test_gen_ctrl(5) => test_gen_ctrl_5_Q,
      test_gen_ctrl(4) => NLW_test_gen_test_gen_ctrl_4_UNCONNECTED,
      test_gen_ctrl(3) => NLW_test_gen_test_gen_ctrl_3_UNCONNECTED,
      test_gen_ctrl(2) => NLW_test_gen_test_gen_ctrl_2_UNCONNECTED,
      test_gen_ctrl(1) => NLW_test_gen_test_gen_ctrl_1_UNCONNECTED,
      test_gen_ctrl(0) => test_gen_ctrl_0_Q,
      test_gen_size(15) => test_gen_size(15),
      test_gen_size(14) => test_gen_size(14),
      test_gen_size(13) => test_gen_size(13),
      test_gen_size(12) => test_gen_size(12),
      test_gen_size(11) => test_gen_size(11),
      test_gen_size(10) => test_gen_size(10),
      test_gen_size(9) => test_gen_size(9),
      test_gen_size(8) => test_gen_size(8),
      test_gen_size(7) => test_gen_size(7),
      test_gen_size(6) => test_gen_size(6),
      test_gen_size(5) => test_gen_size(5),
      test_gen_size(4) => test_gen_size(4),
      test_gen_size(3) => test_gen_size(3),
      test_gen_size(2) => test_gen_size(2),
      test_gen_size(1) => test_gen_size(1),
      test_gen_size(0) => test_gen_size(0),
      test_gen_cnt1(15) => test_gen_cnt1(15),
      test_gen_cnt1(14) => test_gen_cnt1(14),
      test_gen_cnt1(13) => test_gen_cnt1(13),
      test_gen_cnt1(12) => test_gen_cnt1(12),
      test_gen_cnt1(11) => test_gen_cnt1(11),
      test_gen_cnt1(10) => test_gen_cnt1(10),
      test_gen_cnt1(9) => test_gen_cnt1(9),
      test_gen_cnt1(8) => test_gen_cnt1(8),
      test_gen_cnt1(7) => test_gen_cnt1(7),
      test_gen_cnt1(6) => test_gen_cnt1(6),
      test_gen_cnt1(5) => test_gen_cnt1(5),
      test_gen_cnt1(4) => test_gen_cnt1(4),
      test_gen_cnt1(3) => test_gen_cnt1(3),
      test_gen_cnt1(2) => test_gen_cnt1(2),
      test_gen_cnt1(1) => test_gen_cnt1(1),
      test_gen_cnt1(0) => test_gen_cnt1(0),
      test_gen_cnt2(15) => test_gen_cnt2(15),
      test_gen_cnt2(14) => test_gen_cnt2(14),
      test_gen_cnt2(13) => test_gen_cnt2(13),
      test_gen_cnt2(12) => test_gen_cnt2(12),
      test_gen_cnt2(11) => test_gen_cnt2(11),
      test_gen_cnt2(10) => test_gen_cnt2(10),
      test_gen_cnt2(9) => test_gen_cnt2(9),
      test_gen_cnt2(8) => test_gen_cnt2(8),
      test_gen_cnt2(7) => test_gen_cnt2(7),
      test_gen_cnt2(6) => test_gen_cnt2(6),
      test_gen_cnt2(5) => test_gen_cnt2(5),
      test_gen_cnt2(4) => test_gen_cnt2(4),
      test_gen_cnt2(3) => test_gen_cnt2(3),
      test_gen_cnt2(2) => test_gen_cnt2(2),
      test_gen_cnt2(1) => test_gen_cnt2(1),
      test_gen_cnt2(0) => test_gen_cnt2(0)
    );
  test_check : cl_test_check
    port map (
      clk => NlwRenamedSignal_do_clk,
      reset => rst,
      do_data_en => do_data_en_5710,
      do_clk => NlwRenamedSignal_do_clk,
      test_check_error(31) => test_check_error(31),
      test_check_error(30) => test_check_error(30),
      test_check_error(29) => test_check_error(29),
      test_check_error(28) => test_check_error(28),
      test_check_error(27) => test_check_error(27),
      test_check_error(26) => test_check_error(26),
      test_check_error(25) => test_check_error(25),
      test_check_error(24) => test_check_error(24),
      test_check_error(23) => test_check_error(23),
      test_check_error(22) => test_check_error(22),
      test_check_error(21) => test_check_error(21),
      test_check_error(20) => test_check_error(20),
      test_check_error(19) => test_check_error(19),
      test_check_error(18) => test_check_error(18),
      test_check_error(17) => test_check_error(17),
      test_check_error(16) => test_check_error(16),
      test_check_error(15) => test_check_error(15),
      test_check_error(14) => test_check_error(14),
      test_check_error(13) => test_check_error(13),
      test_check_error(12) => test_check_error(12),
      test_check_error(11) => test_check_error(11),
      test_check_error(10) => test_check_error(10),
      test_check_error(9) => test_check_error(9),
      test_check_error(8) => test_check_error(8),
      test_check_error(7) => test_check_error(7),
      test_check_error(6) => test_check_error(6),
      test_check_error(5) => test_check_error(5),
      test_check_error(4) => test_check_error(4),
      test_check_error(3) => test_check_error(3),
      test_check_error(2) => test_check_error(2),
      test_check_error(1) => test_check_error(1),
      test_check_error(0) => test_check_error(0),
      test_check_bl_ok(31) => test_check_bl_ok(31),
      test_check_bl_ok(30) => test_check_bl_ok(30),
      test_check_bl_ok(29) => test_check_bl_ok(29),
      test_check_bl_ok(28) => test_check_bl_ok(28),
      test_check_bl_ok(27) => test_check_bl_ok(27),
      test_check_bl_ok(26) => test_check_bl_ok(26),
      test_check_bl_ok(25) => test_check_bl_ok(25),
      test_check_bl_ok(24) => test_check_bl_ok(24),
      test_check_bl_ok(23) => test_check_bl_ok(23),
      test_check_bl_ok(22) => test_check_bl_ok(22),
      test_check_bl_ok(21) => test_check_bl_ok(21),
      test_check_bl_ok(20) => test_check_bl_ok(20),
      test_check_bl_ok(19) => test_check_bl_ok(19),
      test_check_bl_ok(18) => test_check_bl_ok(18),
      test_check_bl_ok(17) => test_check_bl_ok(17),
      test_check_bl_ok(16) => test_check_bl_ok(16),
      test_check_bl_ok(15) => test_check_bl_ok(15),
      test_check_bl_ok(14) => test_check_bl_ok(14),
      test_check_bl_ok(13) => test_check_bl_ok(13),
      test_check_bl_ok(12) => test_check_bl_ok(12),
      test_check_bl_ok(11) => test_check_bl_ok(11),
      test_check_bl_ok(10) => test_check_bl_ok(10),
      test_check_bl_ok(9) => test_check_bl_ok(9),
      test_check_bl_ok(8) => test_check_bl_ok(8),
      test_check_bl_ok(7) => test_check_bl_ok(7),
      test_check_bl_ok(6) => test_check_bl_ok(6),
      test_check_bl_ok(5) => test_check_bl_ok(5),
      test_check_bl_ok(4) => test_check_bl_ok(4),
      test_check_bl_ok(3) => test_check_bl_ok(3),
      test_check_bl_ok(2) => test_check_bl_ok(2),
      test_check_bl_ok(1) => test_check_bl_ok(1),
      test_check_bl_ok(0) => test_check_bl_ok(0),
      test_check_bl_rd(31) => test_check_bl_rd(31),
      test_check_bl_rd(30) => test_check_bl_rd(30),
      test_check_bl_rd(29) => test_check_bl_rd(29),
      test_check_bl_rd(28) => test_check_bl_rd(28),
      test_check_bl_rd(27) => test_check_bl_rd(27),
      test_check_bl_rd(26) => test_check_bl_rd(26),
      test_check_bl_rd(25) => test_check_bl_rd(25),
      test_check_bl_rd(24) => test_check_bl_rd(24),
      test_check_bl_rd(23) => test_check_bl_rd(23),
      test_check_bl_rd(22) => test_check_bl_rd(22),
      test_check_bl_rd(21) => test_check_bl_rd(21),
      test_check_bl_rd(20) => test_check_bl_rd(20),
      test_check_bl_rd(19) => test_check_bl_rd(19),
      test_check_bl_rd(18) => test_check_bl_rd(18),
      test_check_bl_rd(17) => test_check_bl_rd(17),
      test_check_bl_rd(16) => test_check_bl_rd(16),
      test_check_bl_rd(15) => test_check_bl_rd(15),
      test_check_bl_rd(14) => test_check_bl_rd(14),
      test_check_bl_rd(13) => test_check_bl_rd(13),
      test_check_bl_rd(12) => test_check_bl_rd(12),
      test_check_bl_rd(11) => test_check_bl_rd(11),
      test_check_bl_rd(10) => test_check_bl_rd(10),
      test_check_bl_rd(9) => test_check_bl_rd(9),
      test_check_bl_rd(8) => test_check_bl_rd(8),
      test_check_bl_rd(7) => test_check_bl_rd(7),
      test_check_bl_rd(6) => test_check_bl_rd(6),
      test_check_bl_rd(5) => test_check_bl_rd(5),
      test_check_bl_rd(4) => test_check_bl_rd(4),
      test_check_bl_rd(3) => test_check_bl_rd(3),
      test_check_bl_rd(2) => test_check_bl_rd(2),
      test_check_bl_rd(1) => test_check_bl_rd(1),
      test_check_bl_rd(0) => test_check_bl_rd(0),
      test_check_err_data(15) => test_check_err_data(15),
      test_check_err_data(14) => test_check_err_data(14),
      test_check_err_data(13) => test_check_err_data(13),
      test_check_err_data(12) => test_check_err_data(12),
      test_check_err_data(11) => test_check_err_data(11),
      test_check_err_data(10) => test_check_err_data(10),
      test_check_err_data(9) => test_check_err_data(9),
      test_check_err_data(8) => test_check_err_data(8),
      test_check_err_data(7) => test_check_err_data(7),
      test_check_err_data(6) => test_check_err_data(6),
      test_check_err_data(5) => test_check_err_data(5),
      test_check_err_data(4) => test_check_err_data(4),
      test_check_err_data(3) => test_check_err_data(3),
      test_check_err_data(2) => test_check_err_data(2),
      test_check_err_data(1) => test_check_err_data(1),
      test_check_err_data(0) => test_check_err_data(0),
      test_check_bl_err(31) => test_check_bl_err(31),
      test_check_bl_err(30) => test_check_bl_err(30),
      test_check_bl_err(29) => test_check_bl_err(29),
      test_check_bl_err(28) => test_check_bl_err(28),
      test_check_bl_err(27) => test_check_bl_err(27),
      test_check_bl_err(26) => test_check_bl_err(26),
      test_check_bl_err(25) => test_check_bl_err(25),
      test_check_bl_err(24) => test_check_bl_err(24),
      test_check_bl_err(23) => test_check_bl_err(23),
      test_check_bl_err(22) => test_check_bl_err(22),
      test_check_bl_err(21) => test_check_bl_err(21),
      test_check_bl_err(20) => test_check_bl_err(20),
      test_check_bl_err(19) => test_check_bl_err(19),
      test_check_bl_err(18) => test_check_bl_err(18),
      test_check_bl_err(17) => test_check_bl_err(17),
      test_check_bl_err(16) => test_check_bl_err(16),
      test_check_bl_err(15) => test_check_bl_err(15),
      test_check_bl_err(14) => test_check_bl_err(14),
      test_check_bl_err(13) => test_check_bl_err(13),
      test_check_bl_err(12) => test_check_bl_err(12),
      test_check_bl_err(11) => test_check_bl_err(11),
      test_check_bl_err(10) => test_check_bl_err(10),
      test_check_bl_err(9) => test_check_bl_err(9),
      test_check_bl_err(8) => test_check_bl_err(8),
      test_check_bl_err(7) => test_check_bl_err(7),
      test_check_bl_err(6) => test_check_bl_err(6),
      test_check_bl_err(5) => test_check_bl_err(5),
      test_check_bl_err(4) => test_check_bl_err(4),
      test_check_bl_err(3) => test_check_bl_err(3),
      test_check_bl_err(2) => test_check_bl_err(2),
      test_check_bl_err(1) => test_check_bl_err(1),
      test_check_bl_err(0) => test_check_bl_err(0),
      test_check_ctrl(15) => NLW_test_check_test_check_ctrl_15_UNCONNECTED,
      test_check_ctrl(14) => NLW_test_check_test_check_ctrl_14_UNCONNECTED,
      test_check_ctrl(13) => NLW_test_check_test_check_ctrl_13_UNCONNECTED,
      test_check_ctrl(12) => NLW_test_check_test_check_ctrl_12_UNCONNECTED,
      test_check_ctrl(11) => test_check_ctrl_11_Q,
      test_check_ctrl(10) => test_check_ctrl_10_Q,
      test_check_ctrl(9) => test_check_ctrl_9_Q,
      test_check_ctrl(8) => test_check_ctrl_8_Q,
      test_check_ctrl(7) => test_check_ctrl_7_Q,
      test_check_ctrl(6) => NLW_test_check_test_check_ctrl_6_UNCONNECTED,
      test_check_ctrl(5) => NLW_test_check_test_check_ctrl_5_UNCONNECTED,
      test_check_ctrl(4) => NLW_test_check_test_check_ctrl_4_UNCONNECTED,
      test_check_ctrl(3) => NLW_test_check_test_check_ctrl_3_UNCONNECTED,
      test_check_ctrl(2) => NLW_test_check_test_check_ctrl_2_UNCONNECTED,
      test_check_ctrl(1) => NLW_test_check_test_check_ctrl_1_UNCONNECTED,
      test_check_ctrl(0) => test_check_ctrl_0_Q,
      test_check_size(15) => test_check_size(15),
      test_check_size(14) => test_check_size(14),
      test_check_size(13) => test_check_size(13),
      test_check_size(12) => test_check_size(12),
      test_check_size(11) => test_check_size(11),
      test_check_size(10) => test_check_size(10),
      test_check_size(9) => test_check_size(9),
      test_check_size(8) => test_check_size(8),
      test_check_size(7) => test_check_size(7),
      test_check_size(6) => test_check_size(6),
      test_check_size(5) => test_check_size(5),
      test_check_size(4) => test_check_size(4),
      test_check_size(3) => test_check_size(3),
      test_check_size(2) => test_check_size(2),
      test_check_size(1) => test_check_size(1),
      test_check_size(0) => test_check_size(0),
      test_check_err_adr(15) => test_check_err_adr(15),
      test_check_err_adr(14) => test_check_err_adr(14),
      test_check_err_adr(13) => test_check_err_adr(13),
      test_check_err_adr(12) => test_check_err_adr(12),
      test_check_err_adr(11) => test_check_err_adr(11),
      test_check_err_adr(10) => test_check_err_adr(10),
      test_check_err_adr(9) => test_check_err_adr(9),
      test_check_err_adr(8) => test_check_err_adr(8),
      test_check_err_adr(7) => test_check_err_adr(7),
      test_check_err_adr(6) => test_check_err_adr(6),
      test_check_err_adr(5) => test_check_err_adr(5),
      test_check_err_adr(4) => test_check_err_adr(4),
      test_check_err_adr(3) => test_check_err_adr(3),
      test_check_err_adr(2) => test_check_err_adr(2),
      test_check_err_adr(1) => test_check_err_adr(1),
      test_check_err_adr(0) => test_check_err_adr(0),
      do_data(63) => do_data(63),
      do_data(62) => do_data(62),
      do_data(61) => do_data(61),
      do_data(60) => do_data(60),
      do_data(59) => do_data(59),
      do_data(58) => do_data(58),
      do_data(57) => do_data(57),
      do_data(56) => do_data(56),
      do_data(55) => do_data(55),
      do_data(54) => do_data(54),
      do_data(53) => do_data(53),
      do_data(52) => do_data(52),
      do_data(51) => do_data(51),
      do_data(50) => do_data(50),
      do_data(49) => do_data(49),
      do_data(48) => do_data(48),
      do_data(47) => do_data(47),
      do_data(46) => do_data(46),
      do_data(45) => do_data(45),
      do_data(44) => do_data(44),
      do_data(43) => do_data(43),
      do_data(42) => do_data(42),
      do_data(41) => do_data(41),
      do_data(40) => do_data(40),
      do_data(39) => do_data(39),
      do_data(38) => do_data(38),
      do_data(37) => do_data(37),
      do_data(36) => do_data(36),
      do_data(35) => do_data(35),
      do_data(34) => do_data(34),
      do_data(33) => do_data(33),
      do_data(32) => do_data(32),
      do_data(31) => do_data(31),
      do_data(30) => do_data(30),
      do_data(29) => do_data(29),
      do_data(28) => do_data(28),
      do_data(27) => do_data(27),
      do_data(26) => do_data(26),
      do_data(25) => do_data(25),
      do_data(24) => do_data(24),
      do_data(23) => do_data(23),
      do_data(22) => do_data(22),
      do_data(21) => do_data(21),
      do_data(20) => do_data(20),
      do_data(19) => do_data(19),
      do_data(18) => do_data(18),
      do_data(17) => do_data(17),
      do_data(16) => do_data(16),
      do_data(15) => do_data(15),
      do_data(14) => do_data(14),
      do_data(13) => do_data(13),
      do_data(12) => do_data(12),
      do_data(11) => do_data(11),
      do_data(10) => do_data(10),
      do_data(9) => do_data(9),
      do_data(8) => do_data(8),
      do_data(7) => do_data(7),
      do_data(6) => do_data(6),
      do_data(5) => do_data(5),
      do_data(4) => do_data(4),
      do_data(3) => do_data(3),
      do_data(2) => do_data(2),
      do_data(1) => do_data(1),
      do_data(0) => do_data(0)
    );
  fr2 : ctrl_freq
    port map (
      clk_in => flag_rdi_ef,
      reset => rst,
      freq_en => NLW_fr2_freq_en_UNCONNECTED,
      clk_sys => clk_sys,
      freq_adc(15) => freq2(15),
      freq_adc(14) => freq2(14),
      freq_adc(13) => freq2(13),
      freq_adc(12) => freq2(12),
      freq_adc(11) => freq2(11),
      freq_adc(10) => freq2(10),
      freq_adc(9) => freq2(9),
      freq_adc(8) => freq2(8),
      freq_adc(7) => freq2(7),
      freq_adc(6) => freq2(6),
      freq_adc(5) => freq2(5),
      freq_adc(4) => freq2(4),
      freq_adc(3) => freq2(3),
      freq_adc(2) => freq2(2),
      freq_adc(1) => freq2(1),
      freq_adc(0) => freq2(0)
    );
  fr1 : ctrl_freq_INST_1
    port map (
      clk_in => flag_rdi_ef,
      reset => rst,
      freq_en => NLW_fr1_freq_en_UNCONNECTED,
      clk_sys => clk_sys,
      freq_adc(15) => freq1(15),
      freq_adc(14) => freq1(14),
      freq_adc(13) => freq1(13),
      freq_adc(12) => freq1(12),
      freq_adc(11) => freq1(11),
      freq_adc(10) => freq1(10),
      freq_adc(9) => freq1(9),
      freq_adc(8) => freq1(8),
      freq_adc(7) => freq1(7),
      freq_adc(6) => freq1(6),
      freq_adc(5) => freq1(5),
      freq_adc(4) => freq1(4),
      freq_adc(3) => freq1(3),
      freq_adc(2) => freq1(2),
      freq_adc(1) => freq1(1),
      freq_adc(0) => freq1(0)
    );
  fr0 : ctrl_freq_INST_2
    port map (
      clk_in => clk_check0,
      reset => rst,
      freq_en => NLW_fr0_freq_en_UNCONNECTED,
      clk_sys => clk_sys,
      freq_adc(15) => freq0(15),
      freq_adc(14) => freq0(14),
      freq_adc(13) => freq0(13),
      freq_adc(12) => freq0(12),
      freq_adc(11) => freq0(11),
      freq_adc(10) => freq0(10),
      freq_adc(9) => freq0(9),
      freq_adc(8) => freq0(8),
      freq_adc(7) => freq0(7),
      freq_adc(6) => freq0(6),
      freq_adc(5) => freq0(5),
      freq_adc(4) => freq0(4),
      freq_adc(3) => freq0(3),
      freq_adc(2) => freq0(2),
      freq_adc(1) => freq0(1),
      freq_adc(0) => freq0(0)
    );
  cmd_data_int_9_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(9),
      I3 => cmd_reg1(9),
      O => cmd_data_out2(9)
    );
  cmd_data_int_8_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(8),
      I3 => cmd_reg1(8),
      O => cmd_data_out2(8)
    );
  cmd_data_int_7_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(7),
      I3 => cmd_reg1(7),
      O => cmd_data_out2(7)
    );
  cmd_data_int_6_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(6),
      I3 => cmd_reg1(6),
      O => cmd_data_out2(6)
    );
  cmd_data_int_5_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(5),
      I3 => cmd_reg1(5),
      O => cmd_data_out2(5)
    );
  cmd_data_int_4_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(4),
      I3 => cmd_reg1(4),
      O => cmd_data_out2(4)
    );
  cmd_data_int_3_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(3),
      I3 => cmd_reg1(3),
      O => cmd_data_out2(3)
    );
  cmd_data_int_2_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(2),
      I3 => cmd_reg1(2),
      O => cmd_data_out2(2)
    );
  cmd_data_int_1_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(1),
      I3 => cmd_reg1(1),
      O => cmd_data_out2(1)
    );
  cmd_data_int_15_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(15),
      I3 => cmd_reg1(15),
      O => cmd_data_out2(15)
    );
  cmd_data_int_14_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(14),
      I3 => cmd_reg1(14),
      O => cmd_data_out2(14)
    );
  cmd_data_int_13_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(13),
      I3 => cmd_reg1(13),
      O => cmd_data_out2(13)
    );
  cmd_data_int_12_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(12),
      I3 => cmd_reg1(12),
      O => cmd_data_out2(12)
    );
  cmd_data_int_11_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(11),
      I3 => cmd_reg1(11),
      O => cmd_data_out2(11)
    );
  cmd_data_int_10_1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(10),
      I3 => cmd_reg1(10),
      O => cmd_data_out2(10)
    );
  cmd_data_int_0_1 : LUT4
    generic map(
      INIT => X"FD75"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(5),
      I2 => cmd_reg0(0),
      I3 => cmd_reg1(0),
      O => cmd_data_out2(0)
    );
  di_data_9_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(9),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(9),
      O => di_data(9)
    );
  di_data_8_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(8),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(8),
      O => di_data(8)
    );
  di_data_7_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(7),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(7),
      O => di_data(7)
    );
  di_data_6_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(6),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(6),
      O => di_data(6)
    );
  di_data_63_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(63),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(63),
      O => di_data(63)
    );
  di_data_62_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(62),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(62),
      O => di_data(62)
    );
  di_data_61_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(61),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(61),
      O => di_data(61)
    );
  di_data_60_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(60),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(60),
      O => di_data(60)
    );
  di_data_5_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(5),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(5),
      O => di_data(5)
    );
  di_data_59_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(59),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(59),
      O => di_data(59)
    );
  di_data_58_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(58),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(58),
      O => di_data(58)
    );
  di_data_57_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(57),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(57),
      O => di_data(57)
    );
  di_data_56_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(56),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(56),
      O => di_data(56)
    );
  di_data_55_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(55),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(55),
      O => di_data(55)
    );
  di_data_54_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(54),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(54),
      O => di_data(54)
    );
  di_data_53_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(53),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(53),
      O => di_data(53)
    );
  di_data_52_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(52),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(52),
      O => di_data(52)
    );
  di_data_51_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(51),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(51),
      O => di_data(51)
    );
  di_data_50_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(50),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(50),
      O => di_data(50)
    );
  di_data_4_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(4),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(4),
      O => di_data(4)
    );
  di_data_49_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(49),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(49),
      O => di_data(49)
    );
  di_data_48_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(48),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(48),
      O => di_data(48)
    );
  di_data_47_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(47),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(47),
      O => di_data(47)
    );
  di_data_46_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(46),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(46),
      O => di_data(46)
    );
  di_data_45_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(45),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(45),
      O => di_data(45)
    );
  di_data_44_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(44),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(44),
      O => di_data(44)
    );
  di_data_43_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(43),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(43),
      O => di_data(43)
    );
  di_data_42_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(42),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(42),
      O => di_data(42)
    );
  di_data_41_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(41),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(41),
      O => di_data(41)
    );
  di_data_40_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(40),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(40),
      O => di_data(40)
    );
  di_data_3_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(3),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(3),
      O => di_data(3)
    );
  di_data_39_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(39),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(39),
      O => di_data(39)
    );
  di_data_38_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(38),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(38),
      O => di_data(38)
    );
  di_data_37_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(37),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(37),
      O => di_data(37)
    );
  di_data_36_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(36),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(36),
      O => di_data(36)
    );
  di_data_35_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(35),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(35),
      O => di_data(35)
    );
  di_data_34_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(34),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(34),
      O => di_data(34)
    );
  di_data_33_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(33),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(33),
      O => di_data(33)
    );
  di_data_32_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(32),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(32),
      O => di_data(32)
    );
  di_data_31_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(31),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(31),
      O => di_data(31)
    );
  di_data_30_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(30),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(30),
      O => di_data(30)
    );
  di_data_2_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(2),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(2),
      O => di_data(2)
    );
  di_data_29_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(29),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(29),
      O => di_data(29)
    );
  di_data_28_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(28),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(28),
      O => di_data(28)
    );
  di_data_27_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(27),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(27),
      O => di_data(27)
    );
  di_data_26_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(26),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(26),
      O => di_data(26)
    );
  di_data_25_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(25),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(25),
      O => di_data(25)
    );
  di_data_24_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(24),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(24),
      O => di_data(24)
    );
  di_data_23_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(23),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(23),
      O => di_data(23)
    );
  di_data_22_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(22),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(22),
      O => di_data(22)
    );
  di_data_21_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(21),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(21),
      O => di_data(21)
    );
  di_data_20_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(20),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(20),
      O => di_data(20)
    );
  di_data_1_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(1),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(1),
      O => di_data(1)
    );
  di_data_19_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(19),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(19),
      O => di_data(19)
    );
  di_data_18_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(18),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(18),
      O => di_data(18)
    );
  di_data_17_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(17),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(17),
      O => di_data(17)
    );
  di_data_16_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(16),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(16),
      O => di_data(16)
    );
  di_data_15_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(15),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(15),
      O => di_data(15)
    );
  di_data_14_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(14),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(14),
      O => di_data(14)
    );
  di_data_13_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(13),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(13),
      O => di_data(13)
    );
  di_data_12_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(12),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(12),
      O => di_data(12)
    );
  di_data_11_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(11),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(11),
      O => di_data(11)
    );
  di_data_10_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(10),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(10),
      O => di_data(10)
    );
  di_data_0_1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data(0),
      I2 => mux_ctrl(1),
      I3 => di_gen_data(0),
      O => di_data(0)
    );
  cmd_reg_i1_and00001 : LUT3
    generic map(
      INIT => X"01"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => cmd_adr(2),
      I2 => cmd_adr(1),
      O => cmd_reg_i1_and0000
    );
  cmd_reg_i1_9_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(9),
      I2 => cmd_adr(0),
      I3 => freq1(9),
      I4 => freq2(9),
      O => cmd_reg_i1(9)
    );
  cmd_reg_i1_8_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(8),
      I2 => cmd_adr(0),
      I3 => freq1(8),
      I4 => freq2(8),
      O => cmd_reg_i1(8)
    );
  cmd_reg_i1_7_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(7),
      I2 => cmd_adr(0),
      I3 => freq1(7),
      I4 => freq2(7),
      O => cmd_reg_i1(7)
    );
  cmd_reg_i1_6_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(6),
      I2 => cmd_adr(0),
      I3 => freq1(6),
      I4 => freq2(6),
      O => cmd_reg_i1(6)
    );
  cmd_reg_i1_5_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(5),
      I2 => cmd_adr(0),
      I3 => freq1(5),
      I4 => freq2(5),
      O => cmd_reg_i1(5)
    );
  cmd_reg_i1_4_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(4),
      I2 => cmd_adr(0),
      I3 => freq1(4),
      I4 => freq2(4),
      O => cmd_reg_i1(4)
    );
  cmd_reg_i1_3_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(3),
      I2 => cmd_adr(0),
      I3 => freq1(3),
      I4 => freq2(3),
      O => cmd_reg_i1(3)
    );
  cmd_reg_i1_2_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(2),
      I2 => cmd_adr(0),
      I3 => freq1(2),
      I4 => freq2(2),
      O => cmd_reg_i1(2)
    );
  cmd_reg_i1_1_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(1),
      I2 => cmd_adr(0),
      I3 => freq1(1),
      I4 => freq2(1),
      O => cmd_reg_i1(1)
    );
  cmd_reg_i1_15_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(15),
      I2 => cmd_adr(0),
      I3 => freq1(15),
      I4 => freq2(15),
      O => cmd_reg_i1(15)
    );
  cmd_reg_i1_14_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(14),
      I2 => cmd_adr(0),
      I3 => freq1(14),
      I4 => freq2(14),
      O => cmd_reg_i1(14)
    );
  cmd_reg_i1_13_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(13),
      I2 => cmd_adr(0),
      I3 => freq1(13),
      I4 => freq2(13),
      O => cmd_reg_i1(13)
    );
  cmd_reg_i1_12_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(12),
      I2 => cmd_adr(0),
      I3 => freq1(12),
      I4 => freq2(12),
      O => cmd_reg_i1(12)
    );
  cmd_reg_i1_11_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(11),
      I2 => cmd_adr(0),
      I3 => freq1(11),
      I4 => freq2(11),
      O => cmd_reg_i1(11)
    );
  cmd_reg_i1_10_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(10),
      I2 => cmd_adr(0),
      I3 => freq1(10),
      I4 => freq2(10),
      O => cmd_reg_i1(10)
    );
  cmd_reg_i1_0_1 : LUT5
    generic map(
      INIT => X"FD5DA808"
    )
    port map (
      I0 => cmd_reg_i1_and0000,
      I1 => freq0(0),
      I2 => cmd_adr(0),
      I3 => freq1(0),
      I4 => freq2(0),
      O => cmd_reg_i1(0)
    );
  di_data_we1 : LUT4
    generic map(
      INIT => X"0E04"
    )
    port map (
      I0 => mux_ctrl(0),
      I1 => do_data_en_5710,
      I2 => mux_ctrl(1),
      I3 => di_gen_data_we,
      O => di_data_we
    );
  do_cs_rdy_or00001 : LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      I0 => di_flag_wr_paf,
      I1 => di_start,
      I2 => mux_ctrl(1),
      I3 => mux_ctrl(0),
      O => do_cs_rdy_or0000
    );
  test_gen_size_not00011 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => N13,
      I1 => cmd_adr(0),
      I2 => cmd_adr(1),
      O => test_gen_size_not0001
    );
  test_gen_ctrl_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => N13,
      I2 => cmd_adr(0),
      O => test_gen_ctrl_not0001
    );
  test_check_size_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => N13,
      I1 => cmd_adr(0),
      I2 => cmd_adr(1),
      O => test_check_size_not0001
    );
  test_check_ctrl_not00012 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => N13,
      I1 => cmd_adr(0),
      I2 => cmd_adr(1),
      O => test_check_ctrl_not0001
    );
  test_check_ctrl_not000111 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => cmd_cmd_data_we,
      I1 => cmd_adr(4),
      I2 => cmd_adr(2),
      I3 => cmd_adr(3),
      I4 => cmd_adr(8),
      I5 => cmd_adr(9),
      O => N13
    );
  mux_ctrl_not0001_SW0 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      O => N0
    );
  mux_ctrl_not0001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => N0,
      I1 => cmd_adr(3),
      I2 => cmd_adr(9),
      I3 => cmd_cmd_data_we,
      I4 => cmd_adr(8),
      I5 => cmd_adr(4),
      O => mux_ctrl_not0001_5876
    );
  test_gen_cnt2_not0001_SW0 : LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      I3 => cmd_adr(2),
      O => N2
    );
  test_gen_cnt2_not0001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => rst,
      I1 => cmd_adr(4),
      I2 => cmd_adr(9),
      I3 => cmd_cmd_data_we,
      I4 => cmd_adr(8),
      I5 => N2,
      O => test_gen_cnt2_not0001_6130
    );
  test_gen_cnt1_not0001_SW0 : LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => cmd_adr(3),
      I2 => cmd_adr(1),
      I3 => cmd_adr(0),
      O => N4
    );
  test_gen_cnt1_not0001 : LUT6
    generic map(
      INIT => X"0000000000000800"
    )
    port map (
      I0 => rst,
      I1 => cmd_adr(4),
      I2 => cmd_adr(9),
      I3 => cmd_cmd_data_we,
      I4 => cmd_adr(8),
      I5 => N4,
      O => test_gen_cnt1_not0001_6113
    );
  test_check_err_adr_not0001_SW0 : LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => cmd_adr(2),
      I2 => cmd_adr(3),
      I3 => cmd_adr(0),
      O => N6
    );
  test_check_err_adr_not0001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => cmd_adr(4),
      I1 => cmd_cmd_data_we,
      I2 => cmd_adr(9),
      I3 => rst,
      I4 => cmd_adr(8),
      I5 => N6,
      O => test_check_err_adr_not0001_5999
    );
  do_data_cs_and00001 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => do_flag_rd_pae,
      I1 => do_start,
      I2 => do_cs_rdy_5641,
      I3 => rst,
      O => do_data_cs_and0000
    );
  cmd_adr_3_9_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(2),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(2),
      I4 => test_check_err_adr(2),
      I5 => test_gen_bl_wr(18),
      O => N8
    );
  cmd_adr_3_9 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux8_5_f7_5865,
      I2 => N8,
      O => cmd_reg_i0(2)
    );
  cmd_adr_3_8_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(4),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(4),
      I4 => test_check_err_adr(4),
      I5 => test_gen_bl_wr(20),
      O => N10
    );
  cmd_adr_3_8 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux10_5_f7_5826,
      I2 => N10,
      O => cmd_reg_i0(4)
    );
  cmd_adr_3_7_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(15),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(15),
      I4 => test_check_err_adr(15),
      I5 => test_gen_bl_wr(31),
      O => N12
    );
  cmd_adr_3_7 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux6_5_f7_5859,
      I2 => N12,
      O => cmd_reg_i0(15)
    );
  cmd_adr_3_6_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(14),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(14),
      I4 => test_check_err_adr(14),
      I5 => test_gen_bl_wr(30),
      O => N14
    );
  cmd_adr_3_6 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux5_5_f7_5856,
      I2 => N14,
      O => cmd_reg_i0(14)
    );
  cmd_adr_3_5_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(1),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(1),
      I4 => test_check_err_adr(1),
      I5 => test_gen_bl_wr(17),
      O => N16
    );
  cmd_adr_3_5 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux7_5_f7_5862,
      I2 => N16,
      O => cmd_reg_i0(1)
    );
  cmd_adr_3_4_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(12),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(12),
      I4 => test_check_err_adr(12),
      I5 => test_gen_bl_wr(28),
      O => N18
    );
  cmd_adr_3_4 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux3_5_f7_5850,
      I2 => N18,
      O => cmd_reg_i0(12)
    );
  cmd_adr_3_3_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(11),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(11),
      I4 => test_check_err_adr(11),
      I5 => test_gen_bl_wr(27),
      O => N20
    );
  cmd_adr_3_3 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux2_5_f7_5847,
      I2 => N20,
      O => cmd_reg_i0(11)
    );
  cmd_adr_3_2_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(13),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(13),
      I4 => test_check_err_adr(13),
      I5 => test_gen_bl_wr(29),
      O => N22
    );
  cmd_adr_3_2 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux4_5_f7_5853,
      I2 => N22,
      O => cmd_reg_i0(13)
    );
  cmd_adr_3_15_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(9),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(9),
      I4 => test_check_err_adr(9),
      I5 => test_gen_bl_wr(25),
      O => N24
    );
  cmd_adr_3_15 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux15_5_f7_5841,
      I2 => N24,
      O => cmd_reg_i0(9)
    );
  cmd_adr_3_14_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(8),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(8),
      I4 => test_check_err_adr(8),
      I5 => test_gen_bl_wr(24),
      O => N26
    );
  cmd_adr_3_14 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux14_5_f7_5838,
      I2 => N26,
      O => cmd_reg_i0(8)
    );
  cmd_adr_3_13_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(6),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(6),
      I4 => test_check_err_adr(6),
      I5 => test_gen_bl_wr(22),
      O => N28
    );
  cmd_adr_3_13 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux12_5_f7_5832,
      I2 => N28,
      O => cmd_reg_i0(6)
    );
  cmd_adr_3_12_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(5),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(5),
      I4 => test_check_err_adr(5),
      I5 => test_gen_bl_wr(21),
      O => N30
    );
  cmd_adr_3_12 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux11_5_f7_5829,
      I2 => N30,
      O => cmd_reg_i0(5)
    );
  cmd_adr_3_11_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(7),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(7),
      I4 => test_check_err_adr(7),
      I5 => test_gen_bl_wr(23),
      O => N32
    );
  cmd_adr_3_11 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux13_5_f7_5835,
      I2 => N32,
      O => cmd_reg_i0(7)
    );
  cmd_adr_3_10_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(3),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(3),
      I4 => test_check_err_adr(3),
      I5 => test_gen_bl_wr(19),
      O => N34
    );
  cmd_adr_3_10 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux9_5_f7_5868,
      I2 => N34,
      O => cmd_reg_i0(3)
    );
  cmd_adr_3_1_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(0),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(0),
      I4 => test_check_err_adr(0),
      I5 => test_gen_bl_wr(16),
      O => N36
    );
  cmd_adr_3_1 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux_5_f7_5871,
      I2 => N36,
      O => cmd_reg_i0(0)
    );
  cmd_adr_3_SW0 : LUT6
    generic map(
      INIT => X"EFE5EAE04F454A40"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => test_check_err_data(10),
      I2 => cmd_adr(0),
      I3 => test_gen_bl_wr(10),
      I4 => test_check_err_adr(10),
      I5 => test_gen_bl_wr(26),
      O => N38
    );
  cmd_adr_3_Q : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => mux1_5_f7_5844,
      I2 => N38,
      O => cmd_reg_i0(10)
    );
  mux1_5_f7 : MUXF7
    port map (
      I0 => mux1_7_5846,
      I1 => mux1_6_5845,
      S => cmd_adr(1),
      O => mux1_5_f7_5844
    );
  mux4_5_f7 : MUXF7
    port map (
      I0 => mux4_7_5855,
      I1 => mux4_6_5854,
      S => cmd_adr(1),
      O => mux4_5_f7_5853
    );
  mux2_5_f7 : MUXF7
    port map (
      I0 => mux2_7_5849,
      I1 => mux2_6_5848,
      S => cmd_adr(1),
      O => mux2_5_f7_5847
    );
  mux_5_f7 : MUXF7
    port map (
      I0 => mux_7_5873,
      I1 => mux_6_5872,
      S => cmd_adr(1),
      O => mux_5_f7_5871
    );
  mux7_5_f7 : MUXF7
    port map (
      I0 => mux7_7_5864,
      I1 => mux7_6_5863,
      S => cmd_adr(1),
      O => mux7_5_f7_5862
    );
  mux5_5_f7 : MUXF7
    port map (
      I0 => mux5_7_5858,
      I1 => mux5_6_5857,
      S => cmd_adr(1),
      O => mux5_5_f7_5856
    );
  mux3_5_f7 : MUXF7
    port map (
      I0 => mux3_7_5852,
      I1 => mux3_6_5851,
      S => cmd_adr(1),
      O => mux3_5_f7_5850
    );
  mux10_5_f7 : MUXF7
    port map (
      I0 => mux10_7_5828,
      I1 => mux10_6_5827,
      S => cmd_adr(1),
      O => mux10_5_f7_5826
    );
  mux8_5_f7 : MUXF7
    port map (
      I0 => mux8_7_5867,
      I1 => mux8_6_5866,
      S => cmd_adr(1),
      O => mux8_5_f7_5865
    );
  mux6_5_f7 : MUXF7
    port map (
      I0 => mux6_7_5861,
      I1 => mux6_6_5860,
      S => cmd_adr(1),
      O => mux6_5_f7_5859
    );
  mux13_5_f7 : MUXF7
    port map (
      I0 => mux13_7_5837,
      I1 => mux13_6_5836,
      S => cmd_adr(1),
      O => mux13_5_f7_5835
    );
  mux11_5_f7 : MUXF7
    port map (
      I0 => mux11_7_5831,
      I1 => mux11_6_5830,
      S => cmd_adr(1),
      O => mux11_5_f7_5829
    );
  mux9_5_f7 : MUXF7
    port map (
      I0 => mux9_7_5870,
      I1 => mux9_6_5869,
      S => cmd_adr(1),
      O => mux9_5_f7_5868
    );
  mux14_5_f7 : MUXF7
    port map (
      I0 => mux14_7_5840,
      I1 => mux14_6_5839,
      S => cmd_adr(1),
      O => mux14_5_f7_5838
    );
  mux15_5_f7 : MUXF7
    port map (
      I0 => mux15_7_5843,
      I1 => mux15_6_5842,
      S => cmd_adr(1),
      O => mux15_5_f7_5841
    );
  mux12_5_f7 : MUXF7
    port map (
      I0 => mux12_7_5834,
      I1 => mux12_6_5833,
      S => cmd_adr(1),
      O => mux12_5_f7_5832
    );
  do_data_cs_and0000_inv1 : LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      I0 => do_flag_rd_pae,
      I1 => do_start,
      I2 => do_cs_rdy_5641,
      I3 => rst,
      O => do_data_cs_and0000_inv
    );
  rst_inv1_INV_0 : INV
    port map (
      I => rst,
      O => rst_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ctrl_thdac is
  port (
    clk : in STD_LOGIC := 'X'; 
    start : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    thrs : out STD_LOGIC; 
    ld : out STD_LOGIC; 
    clkDAC_out : out STD_LOGIC; 
    sdo_dac : out STD_LOGIC; 
    ready : out STD_LOGIC; 
    data_dac : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end ctrl_thdac;

architecture STRUCTURE of ctrl_thdac is
  signal Mcount_counter2 : STD_LOGIC; 
  signal Mcount_counter21 : STD_LOGIC; 
  signal Mcount_counter22 : STD_LOGIC; 
  signal Mcount_counter23 : STD_LOGIC; 
  signal Mcount_counter24 : STD_LOGIC; 
  signal Mcount_counter25 : STD_LOGIC; 
  signal Mcount_counter26 : STD_LOGIC; 
  signal Mcount_counter27 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal counter_data_not0001 : STD_LOGIC; 
  signal l_ready_272 : STD_LOGIC; 
  signal l_ready2_273 : STD_LOGIC; 
  signal l_ready2_not0001_274 : STD_LOGIC; 
  signal l_ready_not0001_275 : STD_LOGIC; 
  signal ld_cmp_eq0000 : STD_LOGIC; 
  signal ld_not0001 : STD_LOGIC; 
  signal ready_not0001 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NlwRenamedSignal_thrs : STD_LOGIC; 
  signal Mcount_counter2_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Mcount_counter2_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal counter2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal counter : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal counter_data : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal counter_data_mux0000 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal counter_mux0002 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
begin
  NlwRenamedSignal_thrs <= reset;
  thrs <= NlwRenamedSignal_thrs;
  XST_GND : GND
    port map (
      G => N0
    );
  l_ready : FDCE
    port map (
      C => clk,
      CE => l_ready_not0001_275,
      CLR => reset_inv,
      D => start,
      Q => l_ready_272
    );
  ready_218 : FDP
    port map (
      C => clk,
      D => ready_not0001,
      PRE => reset_inv,
      Q => ready
    );
  counter_data_0 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(0),
      Q => counter_data(0)
    );
  counter_data_1 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(1),
      Q => counter_data(1)
    );
  counter_data_2 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(2),
      Q => counter_data(2)
    );
  counter_data_3 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(3),
      Q => counter_data(3)
    );
  counter_data_4 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(4),
      Q => counter_data(4)
    );
  counter_data_5 : FDCE
    port map (
      C => clk,
      CE => counter_data_not0001,
      CLR => reset_inv,
      D => counter_data_mux0000(5),
      Q => counter_data(5)
    );
  counter_0 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(5),
      Q => counter(0)
    );
  counter_1 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(4),
      Q => counter(1)
    );
  counter_2 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(3),
      Q => counter(2)
    );
  counter_3 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(2),
      Q => counter(3)
    );
  counter_4 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(1),
      Q => counter(4)
    );
  counter_5 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => counter_mux0002(0),
      Q => counter(5)
    );
  l_ready2 : FDCE
    port map (
      C => clk,
      CE => l_ready2_not0001_274,
      CLR => reset_inv,
      D => ld_cmp_eq0000,
      Q => l_ready2_273
    );
  Mcount_counter2_cy_0_Q : MUXCY
    port map (
      CI => l_ready2_273,
      DI => N0,
      S => Mcount_counter2_lut(0),
      O => Mcount_counter2_cy(0)
    );
  Mcount_counter2_xor_0_Q : XORCY
    port map (
      CI => l_ready2_273,
      LI => Mcount_counter2_lut(0),
      O => Mcount_counter2
    );
  Mcount_counter2_cy_1_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(0),
      DI => N0,
      S => Mcount_counter2_lut(1),
      O => Mcount_counter2_cy(1)
    );
  Mcount_counter2_xor_1_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(0),
      LI => Mcount_counter2_lut(1),
      O => Mcount_counter21
    );
  Mcount_counter2_cy_2_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(1),
      DI => N0,
      S => Mcount_counter2_lut(2),
      O => Mcount_counter2_cy(2)
    );
  Mcount_counter2_xor_2_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(1),
      LI => Mcount_counter2_lut(2),
      O => Mcount_counter22
    );
  Mcount_counter2_cy_3_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(2),
      DI => N0,
      S => Mcount_counter2_lut(3),
      O => Mcount_counter2_cy(3)
    );
  Mcount_counter2_xor_3_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(2),
      LI => Mcount_counter2_lut(3),
      O => Mcount_counter23
    );
  Mcount_counter2_cy_4_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(3),
      DI => N0,
      S => Mcount_counter2_lut(4),
      O => Mcount_counter2_cy(4)
    );
  Mcount_counter2_xor_4_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(3),
      LI => Mcount_counter2_lut(4),
      O => Mcount_counter24
    );
  Mcount_counter2_cy_5_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(4),
      DI => N0,
      S => Mcount_counter2_lut(5),
      O => Mcount_counter2_cy(5)
    );
  Mcount_counter2_xor_5_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(4),
      LI => Mcount_counter2_lut(5),
      O => Mcount_counter25
    );
  Mcount_counter2_cy_6_Q : MUXCY
    port map (
      CI => Mcount_counter2_cy(5),
      DI => N0,
      S => Mcount_counter2_lut(6),
      O => Mcount_counter2_cy(6)
    );
  Mcount_counter2_xor_6_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(5),
      LI => Mcount_counter2_lut(6),
      O => Mcount_counter26
    );
  Mcount_counter2_xor_7_Q : XORCY
    port map (
      CI => Mcount_counter2_cy(6),
      LI => Mcount_counter2_lut(7),
      O => Mcount_counter27
    );
  counter2_0 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter2,
      Q => counter2(0)
    );
  counter2_1 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter21,
      Q => counter2(1)
    );
  counter2_2 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter22,
      Q => counter2(2)
    );
  counter2_3 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter23,
      Q => counter2(3)
    );
  counter2_4 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter24,
      Q => counter2(4)
    );
  counter2_5 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter25,
      Q => counter2(5)
    );
  counter2_6 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter26,
      Q => counter2(6)
    );
  counter2_7 : FDC
    port map (
      C => clk,
      CLR => reset_inv,
      D => Mcount_counter27,
      Q => counter2(7)
    );
  ready_not00011 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => l_ready_272,
      I1 => l_ready2_273,
      O => ready_not0001
    );
  counter_data_mux0000_0_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => counter_data(0),
      I1 => l_ready_272,
      O => counter_data_mux0000(0)
    );
  counter_data_mux0000_1_1 : LUT3
    generic map(
      INIT => X"28"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter_data(0),
      I2 => counter_data(1),
      O => counter_data_mux0000(1)
    );
  counter_mux0002_3_1 : LUT4
    generic map(
      INIT => X"2888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(2),
      I2 => counter(0),
      I3 => counter(1),
      O => counter_mux0002(3)
    );
  counter_data_mux0000_2_1 : LUT4
    generic map(
      INIT => X"2888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter_data(2),
      I2 => counter_data(0),
      I3 => counter_data(1),
      O => counter_data_mux0000(2)
    );
  counter_data_mux0000_3_1 : LUT5
    generic map(
      INIT => X"28888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter_data(3),
      I2 => counter_data(0),
      I3 => counter_data(1),
      I4 => counter_data(2),
      O => counter_data_mux0000(3)
    );
  counter_mux0002_1_1 : LUT6
    generic map(
      INIT => X"2888888888888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(4),
      I2 => counter(0),
      I3 => counter(1),
      I4 => counter(2),
      I5 => counter(3),
      O => counter_mux0002(1)
    );
  counter_data_mux0000_4_1 : LUT6
    generic map(
      INIT => X"2888888888888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter_data(4),
      I2 => counter_data(0),
      I3 => counter_data(1),
      I4 => counter_data(2),
      I5 => counter_data(3),
      O => counter_data_mux0000(4)
    );
  ld_not00011 : LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
    port map (
      I0 => counter_data(3),
      I1 => counter_data(2),
      I2 => counter_data(0),
      I3 => counter_data(1),
      I4 => counter_data(4),
      I5 => counter_data(5),
      O => ld_not0001
    );
  counter_mux0002_5_1 : LUT6
    generic map(
      INIT => X"2222222220222222"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(0),
      I2 => counter(2),
      I3 => counter(1),
      I4 => counter(3),
      I5 => N22,
      O => counter_mux0002(5)
    );
  counter_mux0002_4_1 : LUT6
    generic map(
      INIT => X"2828280828282828"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(0),
      I2 => counter(1),
      I3 => counter(2),
      I4 => N22,
      I5 => counter(3),
      O => counter_mux0002(4)
    );
  counter_mux0002_2_1 : LUT6
    generic map(
      INIT => X"2888288088888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(3),
      I2 => counter(2),
      I3 => counter(0),
      I4 => N22,
      I5 => counter(1),
      O => counter_mux0002(2)
    );
  counter_mux0002_5_111 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => counter(4),
      I1 => counter(5),
      O => N22
    );
  counter_data_not00011 : LUT6
    generic map(
      INIT => X"5555555555555D55"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(1),
      I2 => counter(2),
      I3 => counter(3),
      I4 => N22,
      I5 => counter(0),
      O => counter_data_not0001
    );
  l_ready_not0001_SW0 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => counter_data(5),
      I1 => counter_data(0),
      O => N01
    );
  l_ready_not0001 : LUT6
    generic map(
      INIT => X"FFFFFFFF00020000"
    )
    port map (
      I0 => counter_data(3),
      I1 => counter_data(2),
      I2 => counter_data(1),
      I3 => N01,
      I4 => counter_data(4),
      I5 => start,
      O => l_ready_not0001_275
    );
  counter_mux0002_0_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => counter(1),
      I1 => counter(0),
      O => N2
    );
  counter_mux0002_0_Q : LUT6
    generic map(
      INIT => X"2888888888888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter(5),
      I2 => counter(4),
      I3 => counter(3),
      I4 => counter(2),
      I5 => N2,
      O => counter_mux0002(0)
    );
  counter_data_mux0000_5_SW0 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => counter_data(1),
      I1 => counter_data(0),
      O => N4
    );
  counter_data_mux0000_5_Q : LUT6
    generic map(
      INIT => X"2888888888888888"
    )
    port map (
      I0 => l_ready_272,
      I1 => counter_data(5),
      I2 => counter_data(4),
      I3 => counter_data(3),
      I4 => counter_data(2),
      I5 => N4,
      O => counter_data_mux0000(5)
    );
  l_ready2_not0001_SW0 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => counter2(0),
      I1 => counter2(3),
      I2 => counter2(6),
      I3 => counter2(7),
      O => N6
    );
  l_ready2_not0001 : LUT6
    generic map(
      INIT => X"20000000FFFFFFFF"
    )
    port map (
      I0 => counter2(4),
      I1 => N6,
      I2 => counter2(2),
      I3 => counter2(1),
      I4 => counter2(5),
      I5 => ld_not0001,
      O => l_ready2_not0001_274
    );
  Mcount_counter2_lut_0_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(0),
      O => Mcount_counter2_lut(0)
    );
  Mcount_counter2_lut_1_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(1),
      O => Mcount_counter2_lut(1)
    );
  Mcount_counter2_lut_2_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(2),
      O => Mcount_counter2_lut(2)
    );
  Mcount_counter2_lut_3_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(3),
      O => Mcount_counter2_lut(3)
    );
  Mcount_counter2_lut_4_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(4),
      O => Mcount_counter2_lut(4)
    );
  Mcount_counter2_lut_5_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(5),
      O => Mcount_counter2_lut(5)
    );
  Mcount_counter2_lut_6_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(6),
      O => Mcount_counter2_lut(6)
    );
  Mcount_counter2_lut_7_Q : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => l_ready2_273,
      I1 => counter2(7),
      O => Mcount_counter2_lut(7)
    );
  ld_cmp_eq00001 : LUT6
    generic map(
      INIT => X"0000000000008000"
    )
    port map (
      I0 => counter_data(4),
      I1 => counter_data(2),
      I2 => counter_data(0),
      I3 => counter_data(1),
      I4 => counter_data(3),
      I5 => counter_data(5),
      O => ld_cmp_eq0000
    );
  reset_inv1_INV_0 : INV
    port map (
      I => NlwRenamedSignal_thrs,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cl_test0_v4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    reg_test_mode : in STD_LOGIC := 'X'; 
    test_mode : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    data_cs : in STD_LOGIC := 'X'; 
    data_en : in STD_LOGIC := 'X'; 
    test_mode_init : in STD_LOGIC := 'X'; 
    reset_reg : in STD_LOGIC := 'X'; 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    adr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end cl_test0_v4;

architecture STRUCTURE of cl_test0_v4 is
  signal N01 : STD_LOGIC; 
  signal reg_0_mux0001_71 : STD_LOGIC; 
  signal reg_10_mux0000 : STD_LOGIC; 
  signal reg_11_mux0000 : STD_LOGIC; 
  signal reg_12_mux0000 : STD_LOGIC; 
  signal reg_13_mux0000 : STD_LOGIC; 
  signal reg_14_mux0000 : STD_LOGIC; 
  signal reg_15_mux0000 : STD_LOGIC; 
  signal reg_16_mux0000 : STD_LOGIC; 
  signal reg_17_mux0000 : STD_LOGIC; 
  signal reg_18_mux0000 : STD_LOGIC; 
  signal reg_19_mux0000 : STD_LOGIC; 
  signal reg_1_and0000 : STD_LOGIC; 
  signal reg_1_and0001 : STD_LOGIC; 
  signal reg_1_mux0000 : STD_LOGIC; 
  signal reg_1_not0001 : STD_LOGIC; 
  signal reg_1_or0000 : STD_LOGIC; 
  signal reg_20_mux0000 : STD_LOGIC; 
  signal reg_21_mux0000 : STD_LOGIC; 
  signal reg_22_mux0000 : STD_LOGIC; 
  signal reg_23_mux0000 : STD_LOGIC; 
  signal reg_24_mux0000 : STD_LOGIC; 
  signal reg_25_mux0000 : STD_LOGIC; 
  signal reg_26_mux0000 : STD_LOGIC; 
  signal reg_27_mux0000 : STD_LOGIC; 
  signal reg_28_mux0000 : STD_LOGIC; 
  signal reg_29_mux0000 : STD_LOGIC; 
  signal reg_2_mux0000 : STD_LOGIC; 
  signal reg_30_mux0000 : STD_LOGIC; 
  signal reg_31_mux0000 : STD_LOGIC; 
  signal reg_32_mux0000 : STD_LOGIC; 
  signal reg_33_mux0000 : STD_LOGIC; 
  signal reg_34_mux0000 : STD_LOGIC; 
  signal reg_35_mux0000 : STD_LOGIC; 
  signal reg_36_mux0000 : STD_LOGIC; 
  signal reg_37_mux0000 : STD_LOGIC; 
  signal reg_38_mux0000 : STD_LOGIC; 
  signal reg_39_mux0000 : STD_LOGIC; 
  signal reg_3_mux0000 : STD_LOGIC; 
  signal reg_40_mux0000 : STD_LOGIC; 
  signal reg_41_mux0000 : STD_LOGIC; 
  signal reg_42_mux0000 : STD_LOGIC; 
  signal reg_43_mux0000 : STD_LOGIC; 
  signal reg_44_mux0000 : STD_LOGIC; 
  signal reg_45_mux0000 : STD_LOGIC; 
  signal reg_46_mux0000 : STD_LOGIC; 
  signal reg_47_mux0000 : STD_LOGIC; 
  signal reg_48_mux0000 : STD_LOGIC; 
  signal reg_49_mux0000 : STD_LOGIC; 
  signal reg_4_mux0000 : STD_LOGIC; 
  signal reg_50_mux0000 : STD_LOGIC; 
  signal reg_51_mux0000 : STD_LOGIC; 
  signal reg_52_mux0000 : STD_LOGIC; 
  signal reg_53_mux0000 : STD_LOGIC; 
  signal reg_54_mux0000 : STD_LOGIC; 
  signal reg_55_mux0000 : STD_LOGIC; 
  signal reg_56_mux0000 : STD_LOGIC; 
  signal reg_57_mux0000 : STD_LOGIC; 
  signal reg_58_mux0000 : STD_LOGIC; 
  signal reg_59_mux0000 : STD_LOGIC; 
  signal reg_5_mux0000 : STD_LOGIC; 
  signal reg_60_mux0000 : STD_LOGIC; 
  signal reg_61_mux0000 : STD_LOGIC; 
  signal reg_62_mux0000 : STD_LOGIC; 
  signal reg_63_mux0000 : STD_LOGIC; 
  signal reg_6_mux0000 : STD_LOGIC; 
  signal reg_7_mux0000 : STD_LOGIC; 
  signal reg_8_mux0000 : STD_LOGIC; 
  signal reg_9_mux0000 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal NlwRenamedSig_OI_tmode : STD_LOGIC; 
  signal tmode1_207 : STD_LOGIC; 
  signal tmode_mux0000 : STD_LOGIC; 
  signal NlwRenamedSig_OI_reg : STD_LOGIC_VECTOR ( 63 downto 0 ); 
begin
  test_mode <= NlwRenamedSig_OI_tmode;
  data_out(63) <= NlwRenamedSig_OI_reg(63);
  data_out(62) <= NlwRenamedSig_OI_reg(62);
  data_out(61) <= NlwRenamedSig_OI_reg(61);
  data_out(60) <= NlwRenamedSig_OI_reg(60);
  data_out(59) <= NlwRenamedSig_OI_reg(59);
  data_out(58) <= NlwRenamedSig_OI_reg(58);
  data_out(57) <= NlwRenamedSig_OI_reg(57);
  data_out(56) <= NlwRenamedSig_OI_reg(56);
  data_out(55) <= NlwRenamedSig_OI_reg(55);
  data_out(54) <= NlwRenamedSig_OI_reg(54);
  data_out(53) <= NlwRenamedSig_OI_reg(53);
  data_out(52) <= NlwRenamedSig_OI_reg(52);
  data_out(51) <= NlwRenamedSig_OI_reg(51);
  data_out(50) <= NlwRenamedSig_OI_reg(50);
  data_out(49) <= NlwRenamedSig_OI_reg(49);
  data_out(48) <= NlwRenamedSig_OI_reg(48);
  data_out(47) <= NlwRenamedSig_OI_reg(47);
  data_out(46) <= NlwRenamedSig_OI_reg(46);
  data_out(45) <= NlwRenamedSig_OI_reg(45);
  data_out(44) <= NlwRenamedSig_OI_reg(44);
  data_out(43) <= NlwRenamedSig_OI_reg(43);
  data_out(42) <= NlwRenamedSig_OI_reg(42);
  data_out(41) <= NlwRenamedSig_OI_reg(41);
  data_out(40) <= NlwRenamedSig_OI_reg(40);
  data_out(39) <= NlwRenamedSig_OI_reg(39);
  data_out(38) <= NlwRenamedSig_OI_reg(38);
  data_out(37) <= NlwRenamedSig_OI_reg(37);
  data_out(36) <= NlwRenamedSig_OI_reg(36);
  data_out(35) <= NlwRenamedSig_OI_reg(35);
  data_out(34) <= NlwRenamedSig_OI_reg(34);
  data_out(33) <= NlwRenamedSig_OI_reg(33);
  data_out(32) <= NlwRenamedSig_OI_reg(32);
  data_out(31) <= NlwRenamedSig_OI_reg(31);
  data_out(30) <= NlwRenamedSig_OI_reg(30);
  data_out(29) <= NlwRenamedSig_OI_reg(29);
  data_out(28) <= NlwRenamedSig_OI_reg(28);
  data_out(27) <= NlwRenamedSig_OI_reg(27);
  data_out(26) <= NlwRenamedSig_OI_reg(26);
  data_out(25) <= NlwRenamedSig_OI_reg(25);
  data_out(24) <= NlwRenamedSig_OI_reg(24);
  data_out(23) <= NlwRenamedSig_OI_reg(23);
  data_out(22) <= NlwRenamedSig_OI_reg(22);
  data_out(21) <= NlwRenamedSig_OI_reg(21);
  data_out(20) <= NlwRenamedSig_OI_reg(20);
  data_out(19) <= NlwRenamedSig_OI_reg(19);
  data_out(18) <= NlwRenamedSig_OI_reg(18);
  data_out(17) <= NlwRenamedSig_OI_reg(17);
  data_out(16) <= NlwRenamedSig_OI_reg(16);
  data_out(15) <= NlwRenamedSig_OI_reg(15);
  data_out(14) <= NlwRenamedSig_OI_reg(14);
  data_out(13) <= NlwRenamedSig_OI_reg(13);
  data_out(12) <= NlwRenamedSig_OI_reg(12);
  data_out(11) <= NlwRenamedSig_OI_reg(11);
  data_out(10) <= NlwRenamedSig_OI_reg(10);
  data_out(9) <= NlwRenamedSig_OI_reg(9);
  data_out(8) <= NlwRenamedSig_OI_reg(8);
  data_out(7) <= NlwRenamedSig_OI_reg(7);
  data_out(6) <= NlwRenamedSig_OI_reg(6);
  data_out(5) <= NlwRenamedSig_OI_reg(5);
  data_out(4) <= NlwRenamedSig_OI_reg(4);
  data_out(3) <= NlwRenamedSig_OI_reg(3);
  data_out(2) <= NlwRenamedSig_OI_reg(2);
  data_out(1) <= NlwRenamedSig_OI_reg(1);
  data_out(0) <= NlwRenamedSig_OI_reg(0);
  reg_2 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_2_mux0000,
      Q => NlwRenamedSig_OI_reg(2)
    );
  reg_12 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_12_mux0000,
      Q => NlwRenamedSig_OI_reg(12)
    );
  reg_13 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_13_mux0000,
      Q => NlwRenamedSig_OI_reg(13)
    );
  reg_3 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_3_mux0000,
      Q => NlwRenamedSig_OI_reg(3)
    );
  reg_14 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_14_mux0000,
      Q => NlwRenamedSig_OI_reg(14)
    );
  reg_4 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_4_mux0000,
      Q => NlwRenamedSig_OI_reg(4)
    );
  reg_20 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_20_mux0000,
      Q => NlwRenamedSig_OI_reg(20)
    );
  reg_15 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_15_mux0000,
      Q => NlwRenamedSig_OI_reg(15)
    );
  reg_5 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_5_mux0000,
      Q => NlwRenamedSig_OI_reg(5)
    );
  reg_21 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_21_mux0000,
      Q => NlwRenamedSig_OI_reg(21)
    );
  reg_16 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_16_mux0000,
      Q => NlwRenamedSig_OI_reg(16)
    );
  reg_6 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_6_mux0000,
      Q => NlwRenamedSig_OI_reg(6)
    );
  reg_22 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_22_mux0000,
      Q => NlwRenamedSig_OI_reg(22)
    );
  reg_17 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_17_mux0000,
      Q => NlwRenamedSig_OI_reg(17)
    );
  reg_7 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_7_mux0000,
      Q => NlwRenamedSig_OI_reg(7)
    );
  reg_23 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_23_mux0000,
      Q => NlwRenamedSig_OI_reg(23)
    );
  reg_24 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_24_mux0000,
      Q => NlwRenamedSig_OI_reg(24)
    );
  reg_18 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_18_mux0000,
      Q => NlwRenamedSig_OI_reg(18)
    );
  reg_8 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_8_mux0000,
      Q => NlwRenamedSig_OI_reg(8)
    );
  reg_19 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_19_mux0000,
      Q => NlwRenamedSig_OI_reg(19)
    );
  reg_9 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_9_mux0000,
      Q => NlwRenamedSig_OI_reg(9)
    );
  reg_30 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_30_mux0000,
      Q => NlwRenamedSig_OI_reg(30)
    );
  reg_25 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_25_mux0000,
      Q => NlwRenamedSig_OI_reg(25)
    );
  reg_31 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_31_mux0000,
      Q => NlwRenamedSig_OI_reg(31)
    );
  reg_26 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_26_mux0000,
      Q => NlwRenamedSig_OI_reg(26)
    );
  reg_32 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_32_mux0000,
      Q => NlwRenamedSig_OI_reg(32)
    );
  reg_27 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_27_mux0000,
      Q => NlwRenamedSig_OI_reg(27)
    );
  reg_33 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_33_mux0000,
      Q => NlwRenamedSig_OI_reg(33)
    );
  reg_28 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_28_mux0000,
      Q => NlwRenamedSig_OI_reg(28)
    );
  reg_34 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_34_mux0000,
      Q => NlwRenamedSig_OI_reg(34)
    );
  reg_29 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_29_mux0000,
      Q => NlwRenamedSig_OI_reg(29)
    );
  reg_40 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_40_mux0000,
      Q => NlwRenamedSig_OI_reg(40)
    );
  reg_35 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_35_mux0000,
      Q => NlwRenamedSig_OI_reg(35)
    );
  reg_42 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_42_mux0000,
      Q => NlwRenamedSig_OI_reg(42)
    );
  reg_41 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_41_mux0000,
      Q => NlwRenamedSig_OI_reg(41)
    );
  reg_36 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_36_mux0000,
      Q => NlwRenamedSig_OI_reg(36)
    );
  reg_37 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_37_mux0000,
      Q => NlwRenamedSig_OI_reg(37)
    );
  reg_43 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_43_mux0000,
      Q => NlwRenamedSig_OI_reg(43)
    );
  reg_38 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_38_mux0000,
      Q => NlwRenamedSig_OI_reg(38)
    );
  reg_44 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_44_mux0000,
      Q => NlwRenamedSig_OI_reg(44)
    );
  reg_39 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_39_mux0000,
      Q => NlwRenamedSig_OI_reg(39)
    );
  reg_50 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_50_mux0000,
      Q => NlwRenamedSig_OI_reg(50)
    );
  reg_45 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_45_mux0000,
      Q => NlwRenamedSig_OI_reg(45)
    );
  reg_51 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_51_mux0000,
      Q => NlwRenamedSig_OI_reg(51)
    );
  reg_46 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_46_mux0000,
      Q => NlwRenamedSig_OI_reg(46)
    );
  reg_52 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_52_mux0000,
      Q => NlwRenamedSig_OI_reg(52)
    );
  reg_47 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_47_mux0000,
      Q => NlwRenamedSig_OI_reg(47)
    );
  reg_53 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_53_mux0000,
      Q => NlwRenamedSig_OI_reg(53)
    );
  reg_48 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_48_mux0000,
      Q => NlwRenamedSig_OI_reg(48)
    );
  reg_54 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_54_mux0000,
      Q => NlwRenamedSig_OI_reg(54)
    );
  reg_55 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_55_mux0000,
      Q => NlwRenamedSig_OI_reg(55)
    );
  reg_49 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_49_mux0000,
      Q => NlwRenamedSig_OI_reg(49)
    );
  reg_60 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_60_mux0000,
      Q => NlwRenamedSig_OI_reg(60)
    );
  reg_61 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_61_mux0000,
      Q => NlwRenamedSig_OI_reg(61)
    );
  reg_56 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_56_mux0000,
      Q => NlwRenamedSig_OI_reg(56)
    );
  reg_62 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_62_mux0000,
      Q => NlwRenamedSig_OI_reg(62)
    );
  reg_57 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_57_mux0000,
      Q => NlwRenamedSig_OI_reg(57)
    );
  reg_63 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_63_mux0000,
      Q => NlwRenamedSig_OI_reg(63)
    );
  reg_58 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_58_mux0000,
      Q => NlwRenamedSig_OI_reg(58)
    );
  reg_59 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_59_mux0000,
      Q => NlwRenamedSig_OI_reg(59)
    );
  tmode : FDPE
    port map (
      C => clk,
      CE => data_en,
      D => tmode_mux0000,
      PRE => reset_inv,
      Q => NlwRenamedSig_OI_tmode
    );
  reg_10 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_10_mux0000,
      Q => NlwRenamedSig_OI_reg(10)
    );
  reg_0 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_0_mux0001_71,
      Q => NlwRenamedSig_OI_reg(0)
    );
  reg_11 : FDCE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_or0000,
      D => reg_11_mux0000,
      Q => NlwRenamedSig_OI_reg(11)
    );
  tmode1 : FD
    port map (
      C => clk,
      D => NlwRenamedSig_OI_tmode,
      Q => tmode1_207
    );
  reg_1 : FDCPE
    port map (
      C => clk,
      CE => reg_1_not0001,
      CLR => reg_1_and0000,
      D => reg_1_mux0000,
      PRE => reg_1_and0001,
      Q => NlwRenamedSig_OI_reg(1)
    );
  tmode_mux00001 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => NlwRenamedSig_OI_tmode,
      I1 => data_in(1),
      I2 => data_in(0),
      O => tmode_mux0000
    );
  reg_9_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(8),
      I2 => data_in(9),
      O => reg_9_mux0000
    );
  reg_8_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(7),
      I2 => data_in(8),
      O => reg_8_mux0000
    );
  reg_7_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(6),
      I2 => data_in(7),
      O => reg_7_mux0000
    );
  reg_6_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(5),
      I2 => adr_in(6),
      O => reg_6_mux0000
    );
  reg_63_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(62),
      I2 => data_in(63),
      O => reg_63_mux0000
    );
  reg_62_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(61),
      I2 => data_in(62),
      O => reg_62_mux0000
    );
  reg_61_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(60),
      I2 => data_in(61),
      O => reg_61_mux0000
    );
  reg_60_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(59),
      I2 => data_in(60),
      O => reg_60_mux0000
    );
  reg_5_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(4),
      I2 => adr_in(5),
      O => reg_5_mux0000
    );
  reg_59_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(58),
      I2 => data_in(59),
      O => reg_59_mux0000
    );
  reg_58_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(57),
      I2 => data_in(58),
      O => reg_58_mux0000
    );
  reg_57_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(56),
      I2 => data_in(57),
      O => reg_57_mux0000
    );
  reg_56_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(55),
      I2 => data_in(56),
      O => reg_56_mux0000
    );
  reg_55_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(54),
      I2 => data_in(55),
      O => reg_55_mux0000
    );
  reg_54_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(53),
      I2 => data_in(54),
      O => reg_54_mux0000
    );
  reg_53_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(52),
      I2 => data_in(53),
      O => reg_53_mux0000
    );
  reg_52_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(51),
      I2 => data_in(52),
      O => reg_52_mux0000
    );
  reg_51_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(50),
      I2 => data_in(51),
      O => reg_51_mux0000
    );
  reg_50_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(49),
      I2 => data_in(50),
      O => reg_50_mux0000
    );
  reg_4_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(3),
      I2 => adr_in(4),
      O => reg_4_mux0000
    );
  reg_49_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(48),
      I2 => data_in(49),
      O => reg_49_mux0000
    );
  reg_48_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(47),
      I2 => data_in(48),
      O => reg_48_mux0000
    );
  reg_47_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(46),
      I2 => data_in(47),
      O => reg_47_mux0000
    );
  reg_46_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(45),
      I2 => data_in(46),
      O => reg_46_mux0000
    );
  reg_45_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(44),
      I2 => data_in(45),
      O => reg_45_mux0000
    );
  reg_44_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(43),
      I2 => data_in(44),
      O => reg_44_mux0000
    );
  reg_43_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(42),
      I2 => data_in(43),
      O => reg_43_mux0000
    );
  reg_42_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(41),
      I2 => data_in(42),
      O => reg_42_mux0000
    );
  reg_41_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(40),
      I2 => data_in(41),
      O => reg_41_mux0000
    );
  reg_40_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(39),
      I2 => data_in(40),
      O => reg_40_mux0000
    );
  reg_3_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(2),
      I2 => adr_in(3),
      O => reg_3_mux0000
    );
  reg_39_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(38),
      I2 => data_in(39),
      O => reg_39_mux0000
    );
  reg_38_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(37),
      I2 => data_in(38),
      O => reg_38_mux0000
    );
  reg_37_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(36),
      I2 => data_in(37),
      O => reg_37_mux0000
    );
  reg_36_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(35),
      I2 => data_in(36),
      O => reg_36_mux0000
    );
  reg_35_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(34),
      I2 => data_in(35),
      O => reg_35_mux0000
    );
  reg_34_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(33),
      I2 => data_in(34),
      O => reg_34_mux0000
    );
  reg_33_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(32),
      I2 => data_in(33),
      O => reg_33_mux0000
    );
  reg_32_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(31),
      I2 => data_in(32),
      O => reg_32_mux0000
    );
  reg_31_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(30),
      I2 => data_in(31),
      O => reg_31_mux0000
    );
  reg_30_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(29),
      I2 => data_in(30),
      O => reg_30_mux0000
    );
  reg_2_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(1),
      I2 => adr_in(2),
      O => reg_2_mux0000
    );
  reg_29_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(28),
      I2 => data_in(29),
      O => reg_29_mux0000
    );
  reg_28_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(27),
      I2 => data_in(28),
      O => reg_28_mux0000
    );
  reg_27_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(26),
      I2 => data_in(27),
      O => reg_27_mux0000
    );
  reg_26_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(25),
      I2 => data_in(26),
      O => reg_26_mux0000
    );
  reg_25_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(24),
      I2 => data_in(25),
      O => reg_25_mux0000
    );
  reg_24_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(23),
      I2 => data_in(24),
      O => reg_24_mux0000
    );
  reg_23_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(22),
      I2 => data_in(23),
      O => reg_23_mux0000
    );
  reg_22_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(21),
      I2 => data_in(22),
      O => reg_22_mux0000
    );
  reg_21_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(20),
      I2 => data_in(21),
      O => reg_21_mux0000
    );
  reg_20_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(19),
      I2 => data_in(20),
      O => reg_20_mux0000
    );
  reg_19_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(18),
      I2 => data_in(19),
      O => reg_19_mux0000
    );
  reg_18_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(17),
      I2 => data_in(18),
      O => reg_18_mux0000
    );
  reg_17_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(16),
      I2 => data_in(17),
      O => reg_17_mux0000
    );
  reg_16_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(15),
      I2 => data_in(16),
      O => reg_16_mux0000
    );
  reg_15_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(14),
      I2 => data_in(15),
      O => reg_15_mux0000
    );
  reg_14_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(13),
      I2 => data_in(14),
      O => reg_14_mux0000
    );
  reg_13_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(12),
      I2 => data_in(13),
      O => reg_13_mux0000
    );
  reg_12_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(11),
      I2 => data_in(12),
      O => reg_12_mux0000
    );
  reg_11_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(10),
      I2 => data_in(11),
      O => reg_11_mux0000
    );
  reg_10_mux00001 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => data_en,
      I1 => NlwRenamedSig_OI_reg(9),
      I2 => data_in(10),
      O => reg_10_mux0000
    );
  reg_0_mux0001_SW0 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg(60),
      I1 => NlwRenamedSig_OI_reg(59),
      O => N01
    );
  reg_0_mux0001 : LUT6
    generic map(
      INIT => X"FF95FF6500950065"
    )
    port map (
      I0 => NlwRenamedSig_OI_reg(63),
      I1 => N01,
      I2 => reg_test_mode,
      I3 => data_en,
      I4 => NlwRenamedSig_OI_reg(62),
      I5 => adr_in(0),
      O => reg_0_mux0001_71
    );
  reg_1_not00011 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => data_cs,
      I1 => data_en,
      O => reg_1_not0001
    );
  reg_1_or00001 : LUT4
    generic map(
      INIT => X"7DFF"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_tmode,
      I2 => tmode1_207,
      I3 => reset_reg,
      O => reg_1_or0000
    );
  reg_1_mux00001 : LUT5
    generic map(
      INIT => X"FDEC3120"
    )
    port map (
      I0 => data_en,
      I1 => reg_1_or0000,
      I2 => adr_in(1),
      I3 => NlwRenamedSig_OI_reg(0),
      I4 => reg_test_mode,
      O => reg_1_mux0000
    );
  reg_1_and00011 : LUT5
    generic map(
      INIT => X"60F0F0F0"
    )
    port map (
      I0 => tmode1_207,
      I1 => NlwRenamedSig_OI_tmode,
      I2 => reg_test_mode,
      I3 => reset,
      I4 => reset_reg,
      O => reg_1_and0001
    );
  reg_1_and00001 : LUT5
    generic map(
      INIT => X"14555555"
    )
    port map (
      I0 => reg_test_mode,
      I1 => tmode1_207,
      I2 => NlwRenamedSig_OI_tmode,
      I3 => reset,
      I4 => reset_reg,
      O => reg_1_and0000
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity trd_main_v8 is
  port (
    b4_drq_ack : in STD_LOGIC := 'X'; 
    cp0 : out STD_LOGIC; 
    cp1 : out STD_LOGIC; 
    clk : in STD_LOGIC := 'X'; 
    b3_drq_ack : in STD_LOGIC := 'X'; 
    b9_drq_en : in STD_LOGIC := 'X'; 
    b6_irq : in STD_LOGIC := 'X'; 
    bx_start : out STD_LOGIC; 
    thld : out STD_LOGIC; 
    drq1_ack : out STD_LOGIC; 
    b2_drq_ack : in STD_LOGIC := 'X'; 
    sn_rdy0_oe : out STD_LOGIC; 
    b4_drq_en : in STD_LOGIC := 'X'; 
    drq1_en : out STD_LOGIC; 
    bx_start_a : out STD_LOGIC; 
    b2_irq : in STD_LOGIC := 'X'; 
    drq0_req : out STD_LOGIC; 
    b12_irq : in STD_LOGIC := 'X'; 
    b9_drq_req : in STD_LOGIC := 'X'; 
    b1_drq_ack : in STD_LOGIC := 'X'; 
    b8_drq_req : in STD_LOGIC := 'X'; 
    b12_drq_en : in STD_LOGIC := 'X'; 
    b7_drq_req : in STD_LOGIC := 'X'; 
    test_mode : out STD_LOGIC; 
    sn_sync0_out : out STD_LOGIC; 
    bx_clk : out STD_LOGIC; 
    b15_drq_ack : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    cmd_cmd_data_we : in STD_LOGIC := 'X'; 
    b6_drq_req : in STD_LOGIC := 'X'; 
    b14_drq_ack : in STD_LOGIC := 'X'; 
    sn_rdy0_out : out STD_LOGIC; 
    b5_drq_req : in STD_LOGIC := 'X'; 
    b8_drq_en : in STD_LOGIC := 'X'; 
    goe0 : out STD_LOGIC; 
    goe1 : out STD_LOGIC; 
    b13_drq_ack : in STD_LOGIC := 'X'; 
    b4_drq_req : in STD_LOGIC := 'X'; 
    thrs : out STD_LOGIC; 
    b7_irq : in STD_LOGIC := 'X'; 
    sn_sync0 : in STD_LOGIC := 'X'; 
    drq2_ack : out STD_LOGIC; 
    b3_drq_en : in STD_LOGIC := 'X'; 
    b12_drq_ack : in STD_LOGIC := 'X'; 
    b3_drq_req : in STD_LOGIC := 'X'; 
    b3_irq : in STD_LOGIC := 'X'; 
    drq1_req : out STD_LOGIC; 
    b13_irq : in STD_LOGIC := 'X'; 
    b11_drq_ack : in STD_LOGIC := 'X'; 
    b11_drq_en : in STD_LOGIC := 'X'; 
    b2_drq_req : in STD_LOGIC := 'X'; 
    cmd_status_cs : in STD_LOGIC := 'X'; 
    sn_start_en : in STD_LOGIC := 'X'; 
    b10_drq_ack : in STD_LOGIC := 'X'; 
    drq3_en : out STD_LOGIC; 
    test_mode_init : in STD_LOGIC := 'X'; 
    b1_drq_req : in STD_LOGIC := 'X'; 
    bx_start_sync : out STD_LOGIC; 
    drq0_en : out STD_LOGIC; 
    b7_drq_en : in STD_LOGIC := 'X'; 
    sn_rdy1_out : out STD_LOGIC; 
    b15_drq_req : in STD_LOGIC := 'X'; 
    b2_drq_en : in STD_LOGIC := 'X'; 
    cmd_data_cs : in STD_LOGIC := 'X'; 
    b14_drq_req : in STD_LOGIC := 'X'; 
    b15_drq_en : in STD_LOGIC := 'X'; 
    b8_irq : in STD_LOGIC := 'X'; 
    drq3_ack : out STD_LOGIC; 
    b10_drq_en : in STD_LOGIC := 'X'; 
    b13_drq_req : in STD_LOGIC := 'X'; 
    fifo_rst_out : out STD_LOGIC; 
    drq2_req : out STD_LOGIC; 
    b4_irq : in STD_LOGIC := 'X'; 
    b14_irq : in STD_LOGIC := 'X'; 
    b12_drq_req : in STD_LOGIC := 'X'; 
    bx_drq_en : out STD_LOGIC; 
    b10_irq : in STD_LOGIC := 'X'; 
    sn_rdy0 : in STD_LOGIC := 'X'; 
    b11_drq_req : in STD_LOGIC := 'X'; 
    sn_rdy1 : in STD_LOGIC := 'X'; 
    b6_drq_en : in STD_LOGIC := 'X'; 
    b10_drq_req : in STD_LOGIC := 'X'; 
    thclk : out STD_LOGIC; 
    bx_drq_ack : out STD_LOGIC; 
    b1_drq_en : in STD_LOGIC := 'X'; 
    sn_rdy1_oe : out STD_LOGIC; 
    b14_drq_en : in STD_LOGIC := 'X'; 
    drq2_en : out STD_LOGIC; 
    cmd_data_oe : in STD_LOGIC := 'X'; 
    thdin : out STD_LOGIC; 
    cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
    b9_irq : in STD_LOGIC := 'X'; 
    b5_irq : in STD_LOGIC := 'X'; 
    drq3_req : out STD_LOGIC; 
    drq0_ack : out STD_LOGIC; 
    int1 : out STD_LOGIC; 
    b15_irq : in STD_LOGIC := 'X'; 
    int2 : out STD_LOGIC; 
    b9_drq_ack : in STD_LOGIC := 'X'; 
    int3 : out STD_LOGIC; 
    b8_drq_ack : in STD_LOGIC := 'X'; 
    b1_irq : in STD_LOGIC := 'X'; 
    sn_start_en_out : out STD_LOGIC; 
    b11_irq : in STD_LOGIC := 'X'; 
    sn_sync0_in : in STD_LOGIC := 'X'; 
    b5_drq_en : in STD_LOGIC := 'X'; 
    b7_drq_ack : in STD_LOGIC := 'X'; 
    cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
    b6_drq_ack : in STD_LOGIC := 'X'; 
    reset_out : out STD_LOGIC; 
    b13_drq_en : in STD_LOGIC := 'X'; 
    cmd_data_we : in STD_LOGIC := 'X'; 
    b5_drq_ack : in STD_LOGIC := 'X'; 
    bx_drq_req : out STD_LOGIC; 
    sn_master : out STD_LOGIC; 
    sel_drq0 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    sel_drq1 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    sel_drq2 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    sel_drq3 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    synx : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    b_clk : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
    adr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    b_start : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end trd_main_v8;

architecture STRUCTURE of trd_main_v8 is
  component cl_test0_v4
    port (
      clk : in STD_LOGIC := 'X'; 
      reg_test_mode : in STD_LOGIC := 'X'; 
      test_mode : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      data_cs : in STD_LOGIC := 'X'; 
      data_en : in STD_LOGIC := 'X'; 
      test_mode_init : in STD_LOGIC := 'X'; 
      reset_reg : in STD_LOGIC := 'X'; 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      adr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  component ctrl_thdac
    port (
      clk : in STD_LOGIC := 'X'; 
      start : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      thrs : out STD_LOGIC; 
      ld : out STD_LOGIC; 
      clkDAC_out : out STD_LOGIC; 
      sdo_dac : out STD_LOGIC; 
      ready : out STD_LOGIC; 
      data_dac : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
    );
  end component;
  signal Mmux_drq0i_en_3_283 : STD_LOGIC; 
  signal Mmux_drq0i_en_4_284 : STD_LOGIC; 
  signal Mmux_drq1i_en_3_285 : STD_LOGIC; 
  signal Mmux_drq1i_en_4_286 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N41 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal NlwRenamedSig_OI_bx_drq_ack : STD_LOGIC; 
  signal c_inv_not0001 : STD_LOGIC; 
  signal c_mask_not0001 : STD_LOGIC; 
  signal c_mode0_not0001 : STD_LOGIC; 
  signal c_sel0_not0001 : STD_LOGIC; 
  signal c_sel1_not0001 : STD_LOGIC; 
  signal c_sel6_not0001 : STD_LOGIC; 
  signal c_sel7_not0001 : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq0_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq0_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq0_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq0_4_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq1_0_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq1_1_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq1_2_Q : STD_LOGIC; 
  signal NlwRenamedSig_OI_c_sel_drq1_4_Q : STD_LOGIC; 
  signal c_synx_not0001 : STD_LOGIC; 
  signal c_test_mode_381 : STD_LOGIC; 
  signal c_test_mode_not0001 : STD_LOGIC; 
  signal c_thdac_not0001 : STD_LOGIC; 
  signal fifo_rst : STD_LOGIC; 
  signal fifo_rst_norst : STD_LOGIC; 
  signal fifo_rst_or0000 : STD_LOGIC; 
  signal int1110_555 : STD_LOGIC; 
  signal int1132_556 : STD_LOGIC; 
  signal int116_557 : STD_LOGIC; 
  signal int1168_558 : STD_LOGIC; 
  signal int1169_559 : STD_LOGIC; 
  signal int1181_560 : STD_LOGIC; 
  signal int122_561 : STD_LOGIC; 
  signal int143_562 : STD_LOGIC; 
  signal int175_563 : STD_LOGIC; 
  signal int185_564 : STD_LOGIC; 
  signal irq_en_1_mux0001 : STD_LOGIC; 
  signal irq_en_1_not0001 : STD_LOGIC; 
  signal irq_en_2_mux0001 : STD_LOGIC; 
  signal irq_en_3_mux0001 : STD_LOGIC; 
  signal reset_inv : STD_LOGIC; 
  signal rst : STD_LOGIC; 
  signal rst_inv : STD_LOGIC; 
  signal th_rdy : STD_LOGIC; 
  signal thdac_start_580 : STD_LOGIC; 
  signal NLW_thdac_data_dac_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_thdac_data_dac_0_UNCONNECTED : STD_LOGIC; 
  signal c_inv : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal c_mask : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal NlwRenamedSig_OI_c_mode0 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal c_sel0 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal c_sel1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal c_sel6 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal c_sel7 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_OI_c_synx : STD_LOGIC_VECTOR ( 15 downto 15 ); 
  signal NlwRenamedSignal_cmd_data_out : STD_LOGIC_VECTOR ( 5 downto 5 ); 
  signal irq_en : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  bx_drq_en <= NlwRenamedSig_OI_c_mode0(3);
  bx_drq_ack <= NlwRenamedSig_OI_bx_drq_ack;
  bx_drq_req <= NlwRenamedSig_OI_c_mode0(3);
  sel_drq0(4) <= NlwRenamedSig_OI_c_sel_drq0_4_Q;
  sel_drq0(2) <= NlwRenamedSig_OI_c_sel_drq0_2_Q;
  sel_drq0(1) <= NlwRenamedSig_OI_c_sel_drq0_1_Q;
  sel_drq0(0) <= NlwRenamedSig_OI_c_sel_drq0_0_Q;
  sel_drq1(4) <= NlwRenamedSig_OI_c_sel_drq1_4_Q;
  sel_drq1(2) <= NlwRenamedSig_OI_c_sel_drq1_2_Q;
  sel_drq1(1) <= NlwRenamedSig_OI_c_sel_drq1_1_Q;
  sel_drq1(0) <= NlwRenamedSig_OI_c_sel_drq1_0_Q;
  mode0(3) <= NlwRenamedSig_OI_c_mode0(3);
  mode0(2) <= NlwRenamedSig_OI_c_mode0(2);
  mode0(1) <= NlwRenamedSig_OI_c_mode0(1);
  mode0(0) <= NlwRenamedSig_OI_c_mode0(0);
  synx(15) <= NlwRenamedSig_OI_c_synx(15);
  cmd_data_out(6) <= NlwRenamedSignal_cmd_data_out(5);
  cmd_data_out(5) <= NlwRenamedSignal_cmd_data_out(5);
  XST_VCC : VCC
    port map (
      P => fifo_rst_norst
    );
  c_inv_0 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_inv(0)
    );
  c_inv_1 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_inv(1)
    );
  c_inv_2 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(2),
      Q => c_inv(2)
    );
  c_inv_3 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(3),
      Q => c_inv(3)
    );
  c_inv_4 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(4),
      Q => c_inv(4)
    );
  c_inv_5 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(5),
      Q => c_inv(5)
    );
  c_inv_6 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(6),
      Q => c_inv(6)
    );
  c_inv_7 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(7),
      Q => c_inv(7)
    );
  c_inv_8 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(8),
      Q => c_inv(8)
    );
  c_inv_9 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(9),
      Q => c_inv(9)
    );
  c_inv_10 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(10),
      Q => c_inv(10)
    );
  c_inv_11 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(11),
      Q => c_inv(11)
    );
  c_inv_12 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(12),
      Q => c_inv(12)
    );
  c_inv_13 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(13),
      Q => c_inv(13)
    );
  c_inv_14 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(14),
      Q => c_inv(14)
    );
  c_inv_15 : FDCE
    port map (
      C => clk,
      CE => c_inv_not0001,
      CLR => rst_inv,
      D => cmd_data_in(15),
      Q => c_inv(15)
    );
  c_test_mode : FDCE
    port map (
      C => clk,
      CE => c_test_mode_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_test_mode_381
    );
  c_sel0_0 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_sel0(0)
    );
  c_sel0_1 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_sel0(1)
    );
  c_sel1_0 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_sel1(0)
    );
  c_sel1_1 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_sel1(1)
    );
  c_synx_15 : FDCE
    port map (
      C => clk,
      CE => c_synx_not0001,
      CLR => rst_inv,
      D => cmd_data_in(15),
      Q => NlwRenamedSig_OI_c_synx(15)
    );
  c_sel7_0 : FDCE
    port map (
      C => clk,
      CE => c_sel7_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_sel7(0)
    );
  c_sel7_1 : FDCE
    port map (
      C => clk,
      CE => c_sel7_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_sel7(1)
    );
  c_sel6_0 : FDCE
    port map (
      C => clk,
      CE => c_sel6_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_sel6(0)
    );
  c_sel6_1 : FDCE
    port map (
      C => clk,
      CE => c_sel6_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_sel6(1)
    );
  c_mask_0 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(0),
      Q => c_mask(0)
    );
  c_mask_1 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(1),
      Q => c_mask(1)
    );
  c_mask_2 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(2),
      Q => c_mask(2)
    );
  c_mask_3 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(3),
      Q => c_mask(3)
    );
  c_mask_4 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(4),
      Q => c_mask(4)
    );
  c_mask_5 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(5),
      Q => c_mask(5)
    );
  c_mask_6 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(6),
      Q => c_mask(6)
    );
  c_mask_7 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(7),
      Q => c_mask(7)
    );
  c_mask_8 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(8),
      Q => c_mask(8)
    );
  c_mask_9 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(9),
      Q => c_mask(9)
    );
  c_mask_10 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(10),
      Q => c_mask(10)
    );
  c_mask_11 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(11),
      Q => c_mask(11)
    );
  c_mask_12 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(12),
      Q => c_mask(12)
    );
  c_mask_13 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(13),
      Q => c_mask(13)
    );
  c_mask_14 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(14),
      Q => c_mask(14)
    );
  c_mask_15 : FDCE
    port map (
      C => clk,
      CE => c_mask_not0001,
      CLR => rst_inv,
      D => cmd_data_in(15),
      Q => c_mask(15)
    );
  c_sel_drq1_0 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(8),
      Q => NlwRenamedSig_OI_c_sel_drq1_0_Q
    );
  c_sel_drq1_1 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(9),
      Q => NlwRenamedSig_OI_c_sel_drq1_1_Q
    );
  c_sel_drq1_2 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(10),
      Q => NlwRenamedSig_OI_c_sel_drq1_2_Q
    );
  c_sel_drq1_4 : FDCE
    port map (
      C => clk,
      CE => c_sel1_not0001,
      CLR => rst_inv,
      D => cmd_data_in(12),
      Q => NlwRenamedSig_OI_c_sel_drq1_4_Q
    );
  c_sel_drq0_0 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(8),
      Q => NlwRenamedSig_OI_c_sel_drq0_0_Q
    );
  c_sel_drq0_1 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(9),
      Q => NlwRenamedSig_OI_c_sel_drq0_1_Q
    );
  c_sel_drq0_2 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(10),
      Q => NlwRenamedSig_OI_c_sel_drq0_2_Q
    );
  c_sel_drq0_4 : FDCE
    port map (
      C => clk,
      CE => c_sel0_not0001,
      CLR => rst_inv,
      D => cmd_data_in(12),
      Q => NlwRenamedSig_OI_c_sel_drq0_4_Q
    );
  c_mode0_0 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => cmd_data_in(0),
      Q => NlwRenamedSig_OI_c_mode0(0)
    );
  c_mode0_1 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => cmd_data_in(1),
      Q => NlwRenamedSig_OI_c_mode0(1)
    );
  c_mode0_2 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => cmd_data_in(2),
      Q => NlwRenamedSig_OI_c_mode0(2)
    );
  c_mode0_3 : FDCE
    port map (
      C => clk,
      CE => c_mode0_not0001,
      CLR => reset_inv,
      D => cmd_data_in(3),
      Q => NlwRenamedSig_OI_c_mode0(3)
    );
  irq_en_1 : FDCE
    port map (
      C => clk,
      CE => irq_en_1_not0001,
      CLR => rst_inv,
      D => irq_en_1_mux0001,
      Q => irq_en(1)
    );
  irq_en_2 : FDCE
    port map (
      C => clk,
      CE => irq_en_1_not0001,
      CLR => rst_inv,
      D => irq_en_2_mux0001,
      Q => irq_en(2)
    );
  irq_en_3 : FDCE
    port map (
      C => clk,
      CE => irq_en_1_not0001,
      CLR => rst_inv,
      D => irq_en_3_mux0001,
      Q => irq_en(3)
    );
  thdac_start : FDE
    port map (
      C => clk,
      CE => rst,
      D => c_thdac_not0001,
      Q => thdac_start_580
    );
  fifo_rst_out_71 : FDR
    port map (
      C => clk,
      D => fifo_rst_norst,
      R => fifo_rst_or0000,
      Q => fifo_rst_out
    );
  reset_out_72 : FDR
    port map (
      C => clk,
      D => fifo_rst_norst,
      R => rst_inv,
      Q => reset_out
    );
  Mmux_drq1i_en_4 : LUT6
    generic map(
      INIT => X"AAF0CCFFAAF0CC00"
    )
    port map (
      I0 => b3_drq_en,
      I1 => b2_drq_en,
      I2 => b1_drq_en,
      I3 => NlwRenamedSig_OI_c_sel_drq1_1_Q,
      I4 => NlwRenamedSig_OI_c_sel_drq1_0_Q,
      I5 => NlwRenamedSig_OI_c_mode0(3),
      O => Mmux_drq1i_en_4_286
    );
  Mmux_drq1i_en_3 : LUT6
    generic map(
      INIT => X"F0CCF0CCFFAA00AA"
    )
    port map (
      I0 => b4_drq_en,
      I1 => b5_drq_en,
      I2 => b7_drq_en,
      I3 => NlwRenamedSig_OI_c_sel_drq1_1_Q,
      I4 => b6_drq_en,
      I5 => NlwRenamedSig_OI_c_sel_drq1_0_Q,
      O => Mmux_drq1i_en_3_285
    );
  Mmux_drq0i_en_4 : LUT6
    generic map(
      INIT => X"AAF0CCFFAAF0CC00"
    )
    port map (
      I0 => b3_drq_en,
      I1 => b2_drq_en,
      I2 => b1_drq_en,
      I3 => NlwRenamedSig_OI_c_sel_drq0_1_Q,
      I4 => NlwRenamedSig_OI_c_sel_drq0_0_Q,
      I5 => NlwRenamedSig_OI_c_mode0(3),
      O => Mmux_drq0i_en_4_284
    );
  Mmux_drq0i_en_3 : LUT6
    generic map(
      INIT => X"F0CCF0CCFFAA00AA"
    )
    port map (
      I0 => b4_drq_en,
      I1 => b5_drq_en,
      I2 => b7_drq_en,
      I3 => NlwRenamedSig_OI_c_sel_drq0_1_Q,
      I4 => b6_drq_en,
      I5 => NlwRenamedSig_OI_c_sel_drq0_0_Q,
      O => Mmux_drq0i_en_3_283
    );
  d_test0 : cl_test0_v4
    port map (
      clk => clk,
      reg_test_mode => c_test_mode_381,
      test_mode => test_mode,
      reset => reset,
      data_cs => NlwRenamedSig_OI_bx_drq_ack,
      data_en => cmd_data_we,
      test_mode_init => fifo_rst_norst,
      reset_reg => fifo_rst,
      data_out(63) => data_out(63),
      data_out(62) => data_out(62),
      data_out(61) => data_out(61),
      data_out(60) => data_out(60),
      data_out(59) => data_out(59),
      data_out(58) => data_out(58),
      data_out(57) => data_out(57),
      data_out(56) => data_out(56),
      data_out(55) => data_out(55),
      data_out(54) => data_out(54),
      data_out(53) => data_out(53),
      data_out(52) => data_out(52),
      data_out(51) => data_out(51),
      data_out(50) => data_out(50),
      data_out(49) => data_out(49),
      data_out(48) => data_out(48),
      data_out(47) => data_out(47),
      data_out(46) => data_out(46),
      data_out(45) => data_out(45),
      data_out(44) => data_out(44),
      data_out(43) => data_out(43),
      data_out(42) => data_out(42),
      data_out(41) => data_out(41),
      data_out(40) => data_out(40),
      data_out(39) => data_out(39),
      data_out(38) => data_out(38),
      data_out(37) => data_out(37),
      data_out(36) => data_out(36),
      data_out(35) => data_out(35),
      data_out(34) => data_out(34),
      data_out(33) => data_out(33),
      data_out(32) => data_out(32),
      data_out(31) => data_out(31),
      data_out(30) => data_out(30),
      data_out(29) => data_out(29),
      data_out(28) => data_out(28),
      data_out(27) => data_out(27),
      data_out(26) => data_out(26),
      data_out(25) => data_out(25),
      data_out(24) => data_out(24),
      data_out(23) => data_out(23),
      data_out(22) => data_out(22),
      data_out(21) => data_out(21),
      data_out(20) => data_out(20),
      data_out(19) => data_out(19),
      data_out(18) => data_out(18),
      data_out(17) => data_out(17),
      data_out(16) => data_out(16),
      data_out(15) => data_out(15),
      data_out(14) => data_out(14),
      data_out(13) => data_out(13),
      data_out(12) => data_out(12),
      data_out(11) => data_out(11),
      data_out(10) => data_out(10),
      data_out(9) => data_out(9),
      data_out(8) => data_out(8),
      data_out(7) => data_out(7),
      data_out(6) => data_out(6),
      data_out(5) => data_out(5),
      data_out(4) => data_out(4),
      data_out(3) => data_out(3),
      data_out(2) => data_out(2),
      data_out(1) => data_out(1),
      data_out(0) => data_out(0),
      data_in(63) => data_in(63),
      data_in(62) => data_in(62),
      data_in(61) => data_in(61),
      data_in(60) => data_in(60),
      data_in(59) => data_in(59),
      data_in(58) => data_in(58),
      data_in(57) => data_in(57),
      data_in(56) => data_in(56),
      data_in(55) => data_in(55),
      data_in(54) => data_in(54),
      data_in(53) => data_in(53),
      data_in(52) => data_in(52),
      data_in(51) => data_in(51),
      data_in(50) => data_in(50),
      data_in(49) => data_in(49),
      data_in(48) => data_in(48),
      data_in(47) => data_in(47),
      data_in(46) => data_in(46),
      data_in(45) => data_in(45),
      data_in(44) => data_in(44),
      data_in(43) => data_in(43),
      data_in(42) => data_in(42),
      data_in(41) => data_in(41),
      data_in(40) => data_in(40),
      data_in(39) => data_in(39),
      data_in(38) => data_in(38),
      data_in(37) => data_in(37),
      data_in(36) => data_in(36),
      data_in(35) => data_in(35),
      data_in(34) => data_in(34),
      data_in(33) => data_in(33),
      data_in(32) => data_in(32),
      data_in(31) => data_in(31),
      data_in(30) => data_in(30),
      data_in(29) => data_in(29),
      data_in(28) => data_in(28),
      data_in(27) => data_in(27),
      data_in(26) => data_in(26),
      data_in(25) => data_in(25),
      data_in(24) => data_in(24),
      data_in(23) => data_in(23),
      data_in(22) => data_in(22),
      data_in(21) => data_in(21),
      data_in(20) => data_in(20),
      data_in(19) => data_in(19),
      data_in(18) => data_in(18),
      data_in(17) => data_in(17),
      data_in(16) => data_in(16),
      data_in(15) => data_in(15),
      data_in(14) => data_in(14),
      data_in(13) => data_in(13),
      data_in(12) => data_in(12),
      data_in(11) => data_in(11),
      data_in(10) => data_in(10),
      data_in(9) => data_in(9),
      data_in(8) => data_in(8),
      data_in(7) => data_in(7),
      data_in(6) => data_in(6),
      data_in(5) => data_in(5),
      data_in(4) => data_in(4),
      data_in(3) => data_in(3),
      data_in(2) => data_in(2),
      data_in(1) => data_in(1),
      data_in(0) => data_in(0),
      adr_in(6) => adr_in(6),
      adr_in(5) => adr_in(5),
      adr_in(4) => adr_in(4),
      adr_in(3) => adr_in(3),
      adr_in(2) => adr_in(2),
      adr_in(1) => adr_in(1),
      adr_in(0) => adr_in(0)
    );
  thdac : ctrl_thdac
    port map (
      clk => clk,
      start => thdac_start_580,
      reset => rst,
      thrs => thrs,
      ld => thld,
      clkDAC_out => thclk,
      sdo_dac => thdin,
      ready => th_rdy,
      data_dac(11) => NLW_thdac_data_dac_11_UNCONNECTED,
      data_dac(10) => NLW_thdac_data_dac_10_UNCONNECTED,
      data_dac(9) => NLW_thdac_data_dac_9_UNCONNECTED,
      data_dac(8) => NLW_thdac_data_dac_8_UNCONNECTED,
      data_dac(7) => NLW_thdac_data_dac_7_UNCONNECTED,
      data_dac(6) => NLW_thdac_data_dac_6_UNCONNECTED,
      data_dac(5) => NLW_thdac_data_dac_5_UNCONNECTED,
      data_dac(4) => NLW_thdac_data_dac_4_UNCONNECTED,
      data_dac(3) => NLW_thdac_data_dac_3_UNCONNECTED,
      data_dac(2) => NLW_thdac_data_dac_2_UNCONNECTED,
      data_dac(1) => NLW_thdac_data_dac_1_UNCONNECTED,
      data_dac(0) => NLW_thdac_data_dac_0_UNCONNECTED
    );
  cmd_data_out_0_1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => th_rdy,
      O => cmd_data_out(0)
    );
  cmd_data_out_3_1 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => irq_en(3),
      I2 => cmd_adr(1),
      O => cmd_data_out(3)
    );
  cmd_data_out_2_1 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => irq_en(2),
      I2 => cmd_adr(1),
      O => cmd_data_out(2)
    );
  cmd_data_out_1_1 : LUT3
    generic map(
      INIT => X"5D"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => irq_en(1),
      I2 => cmd_adr(1),
      O => cmd_data_out(1)
    );
  cmd_data_out_15_1 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => cmd_status_cs,
      I1 => cmd_adr(1),
      I2 => NlwRenamedSig_OI_c_synx(15),
      O => cmd_data_out(15)
    );
  irq_en_3_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => cmd_data_in(3),
      I1 => irq_en(3),
      I2 => cmd_adr(0),
      O => irq_en_3_mux0001
    );
  irq_en_2_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => cmd_data_in(2),
      I1 => irq_en(2),
      I2 => cmd_adr(0),
      O => irq_en_2_mux0001
    );
  irq_en_1_mux00011 : LUT3
    generic map(
      INIT => X"4E"
    )
    port map (
      I0 => cmd_data_in(1),
      I1 => irq_en(1),
      I2 => cmd_adr(0),
      O => irq_en_1_mux0001
    );
  irq_en_1_not00011 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => cmd_cmd_data_we,
      I1 => cmd_adr(9),
      I2 => cmd_adr(8),
      O => irq_en_1_not0001
    );
  c_thdac_not00011 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => cmd_adr(1),
      I1 => cmd_adr(0),
      I2 => cmd_adr(2),
      I3 => N5,
      O => c_thdac_not0001
    );
  c_test_mode_not00011 : LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      I0 => cmd_adr(2),
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      I3 => N5,
      O => c_test_mode_not0001
    );
  c_synx_not00011 : LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => cmd_adr(1),
      I2 => cmd_adr(2),
      I3 => N5,
      O => c_synx_not0001
    );
  c_fdiv_not000111 : LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      I0 => cmd_adr(3),
      I1 => cmd_adr(8),
      I2 => cmd_adr(9),
      I3 => cmd_cmd_data_we,
      O => N4
    );
  c_sel7_not00011 : LUT5
    generic map(
      INIT => X"80000000"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => cmd_adr(2),
      I2 => cmd_adr(4),
      I3 => cmd_adr(1),
      I4 => N4,
      O => c_sel7_not0001
    );
  c_sel6_not00011 : LUT5
    generic map(
      INIT => X"08000000"
    )
    port map (
      I0 => cmd_adr(4),
      I1 => cmd_adr(2),
      I2 => cmd_adr(0),
      I3 => cmd_adr(1),
      I4 => N4,
      O => c_sel6_not0001
    );
  c_sel1_not00011 : LUT5
    generic map(
      INIT => X"00000080"
    )
    port map (
      I0 => cmd_adr(0),
      I1 => N4,
      I2 => cmd_adr(4),
      I3 => cmd_adr(2),
      I4 => cmd_adr(1),
      O => c_sel1_not0001
    );
  c_sel0_not00011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => N4,
      I1 => cmd_adr(4),
      I2 => cmd_adr(0),
      I3 => cmd_adr(2),
      I4 => cmd_adr(1),
      O => c_sel0_not0001
    );
  c_mux_not000111 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => cmd_cmd_data_we,
      I1 => cmd_adr(3),
      I2 => cmd_adr(4),
      I3 => cmd_adr(8),
      I4 => cmd_adr(9),
      O => N5
    );
  c_mode0_not00011 : LUT5
    generic map(
      INIT => X"00000002"
    )
    port map (
      I0 => N4,
      I1 => cmd_adr(4),
      I2 => cmd_adr(0),
      I3 => cmd_adr(2),
      I4 => cmd_adr(1),
      O => c_mode0_not0001
    );
  c_mask_not00011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => N4,
      I1 => cmd_adr(0),
      I2 => cmd_adr(4),
      I3 => cmd_adr(2),
      I4 => cmd_adr(1),
      O => c_mask_not0001
    );
  c_inv_not00011 : LUT5
    generic map(
      INIT => X"00000008"
    )
    port map (
      I0 => N4,
      I1 => cmd_adr(1),
      I2 => cmd_adr(0),
      I3 => cmd_adr(4),
      I4 => cmd_adr(2),
      O => c_inv_not0001
    );
  int116 : LUT6
    generic map(
      INIT => X"08080808FF080808"
    )
    port map (
      I0 => b6_irq,
      I1 => c_sel6(0),
      I2 => c_sel6(1),
      I3 => b7_irq,
      I4 => c_sel7(0),
      I5 => c_sel7(1),
      O => int116_557
    );
  int143 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => c_inv(11),
      I1 => c_mask(11),
      I2 => c_inv(12),
      I3 => c_mask(12),
      I4 => c_inv(10),
      I5 => c_mask(10),
      O => int143_562
    );
  int175 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => c_inv(5),
      I1 => c_mask(5),
      O => int175_563
    );
  int185 : LUT6
    generic map(
      INIT => X"FFFFFFFF2828FF28"
    )
    port map (
      I0 => c_mask(0),
      I1 => c_inv(0),
      I2 => th_rdy,
      I3 => c_mask(6),
      I4 => c_inv(6),
      I5 => int175_563,
      O => int185_564
    );
  int1110 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => c_inv(15),
      I1 => c_mask(15),
      I2 => c_inv(9),
      I3 => c_mask(9),
      I4 => c_inv(14),
      I5 => c_mask(14),
      O => int1110_555
    );
  int1132 : LUT6
    generic map(
      INIT => X"22F2FFFF22F222F2"
    )
    port map (
      I0 => c_mask(1),
      I1 => c_inv(1),
      I2 => c_mask(3),
      I3 => c_inv(3),
      I4 => c_inv(2),
      I5 => c_mask(2),
      O => int1132_556
    );
  int1168 : LUT6
    generic map(
      INIT => X"FFFFF888F888F888"
    )
    port map (
      I0 => c_inv(8),
      I1 => c_mask(8),
      I2 => c_inv(13),
      I3 => c_mask(13),
      I4 => c_inv(7),
      I5 => c_mask(7),
      O => int1168_558
    );
  int1169 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => c_inv(4),
      I1 => c_mask(4),
      O => int1169_559
    );
  int1181 : LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      I0 => int1169_559,
      I1 => int1168_558,
      I2 => int1132_556,
      I3 => int1110_555,
      I4 => int143_562,
      I5 => int185_564,
      O => int1181_560
    );
  rst_or00001 : LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0(0),
      O => rst_inv
    );
  drq1_en1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq1_4_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq1_2_Q,
      I2 => Mmux_drq1i_en_4_286,
      I3 => Mmux_drq1i_en_3_285,
      O => drq1_en
    );
  drq0_en1 : LUT4
    generic map(
      INIT => X"A820"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq0_4_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq0_2_Q,
      I2 => Mmux_drq0i_en_4_284,
      I3 => Mmux_drq0i_en_3_283,
      O => drq0_en
    );
  Mmux_drq0i_req_2_f7_SW0 : LUT6
    generic map(
      INIT => X"AFCFAFC0A0CFA0C0"
    )
    port map (
      I0 => b5_drq_req,
      I1 => b4_drq_req,
      I2 => NlwRenamedSig_OI_c_sel_drq0_2_Q,
      I3 => NlwRenamedSig_OI_c_sel_drq0_0_Q,
      I4 => NlwRenamedSig_OI_c_mode0(3),
      I5 => b1_drq_req,
      O => N0
    );
  Mmux_drq0i_req_2_f7_SW1 : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq0_0_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq0_2_Q,
      I2 => b3_drq_req,
      I3 => b2_drq_req,
      I4 => b7_drq_req,
      O => N1
    );
  Mmux_drq0i_req_2_f7_SW2 : LUT5
    generic map(
      INIT => X"FDEC7564"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq0_0_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq0_2_Q,
      I2 => b3_drq_req,
      I3 => b2_drq_req,
      I4 => b7_drq_req,
      O => N2
    );
  Mmux_drq0i_req_2_f7 : LUT5
    generic map(
      INIT => X"FA72D850"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq0_1_Q,
      I1 => b6_drq_req,
      I2 => N0,
      I3 => N2,
      I4 => N1,
      O => drq0_req
    );
  Mmux_drq1i_req_2_f7_SW0 : LUT6
    generic map(
      INIT => X"AFCFAFC0A0CFA0C0"
    )
    port map (
      I0 => b5_drq_req,
      I1 => b4_drq_req,
      I2 => NlwRenamedSig_OI_c_sel_drq1_2_Q,
      I3 => NlwRenamedSig_OI_c_sel_drq1_0_Q,
      I4 => NlwRenamedSig_OI_c_mode0(3),
      I5 => b1_drq_req,
      O => N41
    );
  Mmux_drq1i_req_2_f7_SW1 : LUT5
    generic map(
      INIT => X"B9A83120"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq1_0_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq1_2_Q,
      I2 => b3_drq_req,
      I3 => b2_drq_req,
      I4 => b7_drq_req,
      O => N51
    );
  Mmux_drq1i_req_2_f7_SW2 : LUT5
    generic map(
      INIT => X"FDEC7564"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq1_0_Q,
      I1 => NlwRenamedSig_OI_c_sel_drq1_2_Q,
      I2 => b3_drq_req,
      I3 => b2_drq_req,
      I4 => b7_drq_req,
      O => N6
    );
  Mmux_drq1i_req_2_f7 : LUT5
    generic map(
      INIT => X"FA72D850"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_sel_drq1_1_Q,
      I1 => b6_drq_req,
      I2 => N41,
      I3 => N6,
      I4 => N51,
      O => drq1_req
    );
  int122 : LUT4
    generic map(
      INIT => X"FF08"
    )
    port map (
      I0 => b1_irq,
      I1 => c_sel1(0),
      I2 => c_sel1(1),
      I3 => int116_557,
      O => int122_561
    );
  int1217 : LUT6
    generic map(
      INIT => X"FF004000FF000000"
    )
    port map (
      I0 => c_sel0(1),
      I1 => NlwRenamedSig_OI_c_mode0(2),
      I2 => c_sel0(0),
      I3 => irq_en(1),
      I4 => int122_561,
      I5 => int1181_560,
      O => int1
    );
  rst1 : LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_mode0(0),
      I1 => reset,
      O => rst
    );
  fifo_rst1 : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => reset,
      I1 => NlwRenamedSig_OI_c_mode0(0),
      I2 => NlwRenamedSig_OI_c_mode0(1),
      O => fifo_rst
    );
  fifo_rst_or00001 : LUT3
    generic map(
      INIT => X"FB"
    )
    port map (
      I0 => NlwRenamedSig_OI_c_mode0(0),
      I1 => reset,
      I2 => NlwRenamedSig_OI_c_mode0(1),
      O => fifo_rst_or0000
    );
  reset_inv1_INV_0 : INV
    port map (
      I => reset,
      O => reset_inv
    );
  cmd_data_out_6_1_INV_0 : INV
    port map (
      I => cmd_status_cs,
      O => NlwRenamedSignal_cmd_data_out(5)
    );
  data_csp1_INV_0 : INV
    port map (
      I => cmd_data_cs,
      O => NlwRenamedSig_OI_bx_drq_ack
    );

end STRUCTURE;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ambpex5_v20_sx50t_core is
  port (
    bperst : in STD_LOGIC := 'X'; 
    mgt251_n : in STD_LOGIC := 'X'; 
    mgt251_p : in STD_LOGIC := 'X'; 
    bled1 : out STD_LOGIC; 
    bled2 : out STD_LOGIC; 
    bled3 : out STD_LOGIC; 
    bled4 : out STD_LOGIC; 
    btp : out STD_LOGIC_VECTOR ( 3 downto 1 ); 
    txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end ambpex5_v20_sx50t_core;

architecture STRUCTURE of ambpex5_v20_sx50t_core is
  component trd_main_v8
    port (
      b4_drq_ack : in STD_LOGIC := 'X'; 
      cp0 : out STD_LOGIC; 
      cp1 : out STD_LOGIC; 
      clk : in STD_LOGIC := 'X'; 
      b3_drq_ack : in STD_LOGIC := 'X'; 
      b9_drq_en : in STD_LOGIC := 'X'; 
      b6_irq : in STD_LOGIC := 'X'; 
      bx_start : out STD_LOGIC; 
      thld : out STD_LOGIC; 
      drq1_ack : out STD_LOGIC; 
      b2_drq_ack : in STD_LOGIC := 'X'; 
      sn_rdy0_oe : out STD_LOGIC; 
      b4_drq_en : in STD_LOGIC := 'X'; 
      drq1_en : out STD_LOGIC; 
      bx_start_a : out STD_LOGIC; 
      b2_irq : in STD_LOGIC := 'X'; 
      drq0_req : out STD_LOGIC; 
      b12_irq : in STD_LOGIC := 'X'; 
      b9_drq_req : in STD_LOGIC := 'X'; 
      b1_drq_ack : in STD_LOGIC := 'X'; 
      b8_drq_req : in STD_LOGIC := 'X'; 
      b12_drq_en : in STD_LOGIC := 'X'; 
      b7_drq_req : in STD_LOGIC := 'X'; 
      test_mode : out STD_LOGIC; 
      sn_sync0_out : out STD_LOGIC; 
      bx_clk : out STD_LOGIC; 
      b15_drq_ack : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      b6_drq_req : in STD_LOGIC := 'X'; 
      b14_drq_ack : in STD_LOGIC := 'X'; 
      sn_rdy0_out : out STD_LOGIC; 
      b5_drq_req : in STD_LOGIC := 'X'; 
      b8_drq_en : in STD_LOGIC := 'X'; 
      goe0 : out STD_LOGIC; 
      goe1 : out STD_LOGIC; 
      b13_drq_ack : in STD_LOGIC := 'X'; 
      b4_drq_req : in STD_LOGIC := 'X'; 
      thrs : out STD_LOGIC; 
      b7_irq : in STD_LOGIC := 'X'; 
      sn_sync0 : in STD_LOGIC := 'X'; 
      drq2_ack : out STD_LOGIC; 
      b3_drq_en : in STD_LOGIC := 'X'; 
      b12_drq_ack : in STD_LOGIC := 'X'; 
      b3_drq_req : in STD_LOGIC := 'X'; 
      b3_irq : in STD_LOGIC := 'X'; 
      drq1_req : out STD_LOGIC; 
      b13_irq : in STD_LOGIC := 'X'; 
      b11_drq_ack : in STD_LOGIC := 'X'; 
      b11_drq_en : in STD_LOGIC := 'X'; 
      b2_drq_req : in STD_LOGIC := 'X'; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      sn_start_en : in STD_LOGIC := 'X'; 
      b10_drq_ack : in STD_LOGIC := 'X'; 
      drq3_en : out STD_LOGIC; 
      test_mode_init : in STD_LOGIC := 'X'; 
      b1_drq_req : in STD_LOGIC := 'X'; 
      bx_start_sync : out STD_LOGIC; 
      drq0_en : out STD_LOGIC; 
      b7_drq_en : in STD_LOGIC := 'X'; 
      sn_rdy1_out : out STD_LOGIC; 
      b15_drq_req : in STD_LOGIC := 'X'; 
      b2_drq_en : in STD_LOGIC := 'X'; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      b14_drq_req : in STD_LOGIC := 'X'; 
      b15_drq_en : in STD_LOGIC := 'X'; 
      b8_irq : in STD_LOGIC := 'X'; 
      drq3_ack : out STD_LOGIC; 
      b10_drq_en : in STD_LOGIC := 'X'; 
      b13_drq_req : in STD_LOGIC := 'X'; 
      fifo_rst_out : out STD_LOGIC; 
      drq2_req : out STD_LOGIC; 
      b4_irq : in STD_LOGIC := 'X'; 
      b14_irq : in STD_LOGIC := 'X'; 
      b12_drq_req : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      b10_irq : in STD_LOGIC := 'X'; 
      sn_rdy0 : in STD_LOGIC := 'X'; 
      b11_drq_req : in STD_LOGIC := 'X'; 
      sn_rdy1 : in STD_LOGIC := 'X'; 
      b6_drq_en : in STD_LOGIC := 'X'; 
      b10_drq_req : in STD_LOGIC := 'X'; 
      thclk : out STD_LOGIC; 
      bx_drq_ack : out STD_LOGIC; 
      b1_drq_en : in STD_LOGIC := 'X'; 
      sn_rdy1_oe : out STD_LOGIC; 
      b14_drq_en : in STD_LOGIC := 'X'; 
      drq2_en : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      thdin : out STD_LOGIC; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      b9_irq : in STD_LOGIC := 'X'; 
      b5_irq : in STD_LOGIC := 'X'; 
      drq3_req : out STD_LOGIC; 
      drq0_ack : out STD_LOGIC; 
      int1 : out STD_LOGIC; 
      b15_irq : in STD_LOGIC := 'X'; 
      int2 : out STD_LOGIC; 
      b9_drq_ack : in STD_LOGIC := 'X'; 
      int3 : out STD_LOGIC; 
      b8_drq_ack : in STD_LOGIC := 'X'; 
      b1_irq : in STD_LOGIC := 'X'; 
      sn_start_en_out : out STD_LOGIC; 
      b11_irq : in STD_LOGIC := 'X'; 
      sn_sync0_in : in STD_LOGIC := 'X'; 
      b5_drq_en : in STD_LOGIC := 'X'; 
      b7_drq_ack : in STD_LOGIC := 'X'; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      b6_drq_ack : in STD_LOGIC := 'X'; 
      reset_out : out STD_LOGIC; 
      b13_drq_en : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      b5_drq_ack : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      sn_master : out STD_LOGIC; 
      sel_drq0 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      sel_drq1 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      sel_drq2 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      sel_drq3 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      synx : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      b_clk : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      adr_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      b_start : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  component trd_test_ctrl_m1
    port (
      di_clk : out STD_LOGIC; 
      di_data_we : out STD_LOGIC; 
      do_start : in STD_LOGIC := 'X'; 
      do_fifo_rst : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      do_flag_rd_und : in STD_LOGIC := 'X'; 
      di_fifo_rst : in STD_LOGIC := 'X'; 
      do_flag_rd_pae : in STD_LOGIC := 'X'; 
      do_flag_rd_paf : in STD_LOGIC := 'X'; 
      bx_irq : out STD_LOGIC; 
      clk_check0 : in STD_LOGIC := 'X'; 
      clk_check1 : in STD_LOGIC := 'X'; 
      clk_check2 : in STD_LOGIC := 'X'; 
      reset : in STD_LOGIC := 'X'; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      di_start : in STD_LOGIC := 'X'; 
      do_data_cs : out STD_LOGIC; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      do_clk : out STD_LOGIC; 
      di_flag_wr_ovr : in STD_LOGIC := 'X'; 
      do_flag_rd_ef : in STD_LOGIC := 'X'; 
      di_flag_wr_ef : in STD_LOGIC := 'X'; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      do_flag_rd_ff : in STD_LOGIC := 'X'; 
      di_flag_wr_ff : in STD_LOGIC := 'X'; 
      do_flag_rd_hf : in STD_LOGIC := 'X'; 
      di_flag_wr_hf : in STD_LOGIC := 'X'; 
      do_flag_rd_ovr : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      clk_sys : in STD_LOGIC := 'X'; 
      bx_drq_ack : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      di_flag_wr_und : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      di_flag_wr_pae : in STD_LOGIC := 'X'; 
      di_flag_wr_paf : in STD_LOGIC := 'X'; 
      cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      di_data : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      do_mode1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      di_mode1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
      do_data : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  component trd_admdio64_in_v6
    port (
      clk : in STD_LOGIC := 'X'; 
      flag_rd_ef : out STD_LOGIC; 
      flag_rd_ff : out STD_LOGIC; 
      flag_rd_hf : out STD_LOGIC; 
      flag_wr_und : out STD_LOGIC; 
      bx_irq : out STD_LOGIC; 
      flag_wr_pae : out STD_LOGIC; 
      flag_wr_paf : out STD_LOGIC; 
      start : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      flag_wr_ef : out STD_LOGIC; 
      flag_wr_ff : out STD_LOGIC; 
      flag_rd_ovr : out STD_LOGIC; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      flag_wr_hf : out STD_LOGIC; 
      fifo_rst : out STD_LOGIC; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      clk_wr : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      flag_wr_ovr : out STD_LOGIC; 
      bx_drq_ack : out STD_LOGIC; 
      data_wr : in STD_LOGIC := 'X'; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      flag_rd_und : out STD_LOGIC; 
      flag_rd_pae : out STD_LOGIC; 
      flag_rd_paf : out STD_LOGIC; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      fifo_rst_in : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      fifo_cnt_rd : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      fifo_cnt_wr : out STD_LOGIC_VECTOR ( 9 downto 0 ); 
      data_out2 : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component trd_admdio64_out_v4
    port (
      clk : in STD_LOGIC := 'X'; 
      flag_rd_ef : out STD_LOGIC; 
      flag_rd_ff : out STD_LOGIC; 
      flag_rd_hf : out STD_LOGIC; 
      bx_irq : out STD_LOGIC; 
      start : out STD_LOGIC; 
      reset : in STD_LOGIC := 'X'; 
      cmd_cmd_data_we : in STD_LOGIC := 'X'; 
      data_cs : in STD_LOGIC := 'X'; 
      clk_rd : in STD_LOGIC := 'X'; 
      flag_rd_ovr : out STD_LOGIC; 
      cmd_status_cs : in STD_LOGIC := 'X'; 
      fifo_rst : out STD_LOGIC; 
      cmd_data_cs : in STD_LOGIC := 'X'; 
      bx_drq_en : out STD_LOGIC; 
      bx_drq_ack : out STD_LOGIC; 
      cmd_data_oe : in STD_LOGIC := 'X'; 
      cmd_cmd_data_cs : in STD_LOGIC := 'X'; 
      flag_rd_und : out STD_LOGIC; 
      flag_rd_pae : out STD_LOGIC; 
      flag_rd_paf : out STD_LOGIC; 
      cmd_cmd_adr_we : in STD_LOGIC := 'X'; 
      cmd_data_we : in STD_LOGIC := 'X'; 
      bx_drq_req : out STD_LOGIC; 
      data_out : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cmd_data_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      mode3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      fifo_cnt : out STD_LOGIC_VECTOR ( 12 downto 0 ); 
      cmd_data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      test : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      data_in : in STD_LOGIC_VECTOR ( 63 downto 0 ); 
      cmd_data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      cmd_adr : in STD_LOGIC_VECTOR ( 9 downto 0 ) 
    );
  end component;
  component cl_ambpex5_m5
    port (
      trd_host_cmd_11_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_13_data_oe : out STD_LOGIC; 
      trd_host_cmd_6_cmd_data_cs : out STD_LOGIC; 
      trd_drq_14_req : in STD_LOGIC := 'X'; 
      trd_drq_14_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_2_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_9_data_cs : out STD_LOGIC; 
      trd_host_cmd_12_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_15_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_2_data_we : out STD_LOGIC; 
      trd_drq_15_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_cs : out STD_LOGIC; 
      trd_host_cmd_1_data_oe : out STD_LOGIC; 
      trd_main_drq_0_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_3_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_2_status_cs : out STD_LOGIC; 
      trd_host_cmd_13_data_we : out STD_LOGIC; 
      trd_host_cmd_11_data_cs : out STD_LOGIC; 
      trd_main_drq_1_ack : in STD_LOGIC := 'X'; 
      trd_drq_3_en : in STD_LOGIC := 'X'; 
      trd_drq_0_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_data_oe : out STD_LOGIC; 
      trd_host_cmd_9_cmd_data_we : out STD_LOGIC; 
      trd_main_drq_8_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_8_status_cs : out STD_LOGIC; 
      trd_host_cmd_11_status_cs : out STD_LOGIC; 
      trd_main_drq_2_ack : in STD_LOGIC := 'X'; 
      trd_drq_8_en : in STD_LOGIC := 'X'; 
      trd_drq_1_ack : in STD_LOGIC := 'X'; 
      clk_out : out STD_LOGIC; 
      trd_host_cmd_8_data_cs : out STD_LOGIC; 
      trd_host_cmd_9_data_oe : out STD_LOGIC; 
      trd_host_cmd_4_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_1_data_we : out STD_LOGIC; 
      clk5_pll : out STD_LOGIC; 
      trd_main_drq_3_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_11_en : in STD_LOGIC := 'X'; 
      trd_drq_2_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_oe : out STD_LOGIC; 
      trd_host_cmd_15_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_14_cmd_adr_we : out STD_LOGIC; 
      trd_main_drq_4_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_0_req : in STD_LOGIC := 'X'; 
      trd_drq_3_ack : in STD_LOGIC := 'X'; 
      trd_drq_11_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_12_data_we : out STD_LOGIC; 
      trd_host_cmd_10_data_cs : out STD_LOGIC; 
      trd_host_cmd_11_data_oe : out STD_LOGIC; 
      trd_host_cmd_6_cmd_data_we : out STD_LOGIC; 
      reset_out : out STD_LOGIC; 
      trd_main_drq_1_req : in STD_LOGIC := 'X'; 
      trd_main_drq_5_ack : in STD_LOGIC := 'X'; 
      trd_drq_4_ack : in STD_LOGIC := 'X'; 
      trd_drq_0_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_data_we : out STD_LOGIC; 
      trd_host_cmd_3_status_cs : out STD_LOGIC; 
      trd_main_drq_0_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_7_data_cs : out STD_LOGIC; 
      clk_lock_out : out STD_LOGIC; 
      trd_host_cmd_12_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_8_data_oe : out STD_LOGIC; 
      trd_main_drq_2_req : in STD_LOGIC := 'X'; 
      trd_main_drq_6_ack : in STD_LOGIC := 'X'; 
      trd_drq_5_ack : in STD_LOGIC := 'X'; 
      trd_drq_1_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_data_we : out STD_LOGIC; 
      trd_host_cmd_7_cmd_data_cs : out STD_LOGIC; 
      trd_drq_0_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_status_cs : out STD_LOGIC; 
      trd_main_drq_5_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_cmd_adr_we : out STD_LOGIC; 
      trd_main_drq_3_req : in STD_LOGIC := 'X'; 
      trd_main_drq_7_ack : in STD_LOGIC := 'X'; 
      trd_drq_6_ack : in STD_LOGIC := 'X'; 
      trd_drq_2_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_status_cs : out STD_LOGIC; 
      trd_host_cmd_3_cmd_data_we : out STD_LOGIC; 
      trd_drq_5_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_11_data_we : out STD_LOGIC; 
      trd_host_cmd_13_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_10_data_oe : out STD_LOGIC; 
      trd_main_drq_8_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_4_req : in STD_LOGIC := 'X'; 
      trd_drq_7_ack : in STD_LOGIC := 'X'; 
      trd_drq_3_req : in STD_LOGIC := 'X'; 
      clk2_pll : out STD_LOGIC; 
      trd_host_cmd_13_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_9_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_5_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_8_data_we : out STD_LOGIC; 
      trd_drq_4_req : in STD_LOGIC := 'X'; 
      trd_drq_8_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_6_data_cs : out STD_LOGIC; 
      trd_host_cmd_7_data_oe : out STD_LOGIC; 
      trd_main_drq_13_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_4_cmd_data_cs : out STD_LOGIC; 
      led_h1 : out STD_LOGIC; 
      led_h2 : out STD_LOGIC; 
      trd_main_drq_6_req : in STD_LOGIC := 'X'; 
      led_h3 : out STD_LOGIC; 
      trd_drq_5_req : in STD_LOGIC := 'X'; 
      trd_drq_9_ack : in STD_LOGIC := 'X'; 
      led_h4 : out STD_LOGIC; 
      trd_drq_13_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_4_status_cs : out STD_LOGIC; 
      trd_host_cmd_10_data_we : out STD_LOGIC; 
      trd_main_drq_7_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_cmd_adr_we : out STD_LOGIC; 
      trd_drq_6_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_2_cmd_adr_we : out STD_LOGIC; 
      bperst : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_10_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_8_req : in STD_LOGIC := 'X'; 
      trd_drq_7_req : in STD_LOGIC := 'X'; 
      trd_main_drq_2_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_13_status_cs : out STD_LOGIC; 
      trd_host_cmd_7_data_we : out STD_LOGIC; 
      trd_host_cmd_5_data_cs : out STD_LOGIC; 
      trd_host_cmd_6_data_oe : out STD_LOGIC; 
      trd_drq_2_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_7_cmd_data_we : out STD_LOGIC; 
      trd_main_drq_9_req : in STD_LOGIC := 'X'; 
      trd_drq_8_req : in STD_LOGIC := 'X'; 
      trd_main_drq_7_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_cmd_data_cs : out STD_LOGIC; 
      clk30k : out STD_LOGIC; 
      trd_drq_7_en : in STD_LOGIC := 'X'; 
      trd_drq_9_req : in STD_LOGIC := 'X'; 
      clk200_out : out STD_LOGIC; 
      clk4_pll : out STD_LOGIC; 
      trd_main_drq_10_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_13_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_8_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_1_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_8_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_15_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_6_data_we : out STD_LOGIC; 
      trd_drq_10_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_4_data_cs : out STD_LOGIC; 
      trd_host_cmd_5_status_cs : out STD_LOGIC; 
      trd_host_cmd_5_data_oe : out STD_LOGIC; 
      trd_host_cmd_4_cmd_data_we : out STD_LOGIC; 
      trd_drq_15_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_11_cmd_adr_we : out STD_LOGIC; 
      trd_main_drq_10_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_data_cs : out STD_LOGIC; 
      trd_host_cmd_14_status_cs : out STD_LOGIC; 
      trd_host_cmd_14_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_11_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_10_cmd_data_we : out STD_LOGIC; 
      trd_main_drq_4_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_12_ack : in STD_LOGIC := 'X'; 
      trd_drq_4_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_data_we : out STD_LOGIC; 
      trd_host_cmd_7_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_3_data_cs : out STD_LOGIC; 
      trd_host_cmd_0_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_4_data_oe : out STD_LOGIC; 
      trd_main_drq_9_en : in STD_LOGIC := 'X'; 
      test_mode : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_cmd_data_we : out STD_LOGIC; 
      trd_main_drq_13_ack : in STD_LOGIC := 'X'; 
      trd_drq_9_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_0_status_cs : out STD_LOGIC; 
      trd_drq_10_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_14_data_cs : out STD_LOGIC; 
      trd_host_cmd_15_data_oe : out STD_LOGIC; 
      trd_host_cmd_11_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_10_req : in STD_LOGIC := 'X'; 
      trd_main_drq_14_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_12_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_10_cmd_adr_we : out STD_LOGIC; 
      trd_host_cmd_6_status_cs : out STD_LOGIC; 
      trd_drq_11_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_8_cmd_data_we : out STD_LOGIC; 
      trd_main_drq_11_req : in STD_LOGIC := 'X'; 
      trd_main_drq_15_ack : in STD_LOGIC := 'X'; 
      trd_drq_12_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_2_cmd_data_cs : out STD_LOGIC; 
      trd_drq_12_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_status_cs : out STD_LOGIC; 
      trd_host_cmd_4_data_we : out STD_LOGIC; 
      trd_host_cmd_2_data_cs : out STD_LOGIC; 
      trd_host_cmd_3_data_oe : out STD_LOGIC; 
      trd_main_drq_12_req : in STD_LOGIC := 'X'; 
      trd_drq_13_ack : in STD_LOGIC := 'X'; 
      trd_main_drq_1_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_15_data_we : out STD_LOGIC; 
      trd_main_drq_13_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_13_data_cs : out STD_LOGIC; 
      trd_host_cmd_14_cmd_data_we : out STD_LOGIC; 
      trd_host_cmd_14_data_oe : out STD_LOGIC; 
      trd_host_cmd_6_cmd_adr_we : out STD_LOGIC; 
      trd_drq_10_req : in STD_LOGIC := 'X'; 
      trd_drq_14_ack : in STD_LOGIC := 'X'; 
      trd_drq_1_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_9_cmd_data_cs : out STD_LOGIC; 
      trd_main_drq_6_en : in STD_LOGIC := 'X'; 
      trd_main_drq_14_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_status_cs : out STD_LOGIC; 
      trd_drq_11_req : in STD_LOGIC := 'X'; 
      trd_drq_15_ack : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_cmd_data_we : out STD_LOGIC; 
      trd_drq_6_en : in STD_LOGIC := 'X'; 
      mgt251_n : in STD_LOGIC := 'X'; 
      mgt251_p : in STD_LOGIC := 'X'; 
      trd_host_cmd_3_data_we : out STD_LOGIC; 
      trd_main_drq_15_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_1_data_cs : out STD_LOGIC; 
      trd_host_cmd_2_data_oe : out STD_LOGIC; 
      trd_host_cmd_7_status_cs : out STD_LOGIC; 
      trd_drq_12_req : in STD_LOGIC := 'X'; 
      clk3_pll : out STD_LOGIC; 
      trd_host_cmd_15_cmd_data_cs : out STD_LOGIC; 
      trd_host_cmd_10_status_cs : out STD_LOGIC; 
      trd_host_cmd_14_data_we : out STD_LOGIC; 
      trd_drq_13_req : in STD_LOGIC := 'X'; 
      trd_host_cmd_12_data_cs : out STD_LOGIC; 
      trd_main_drq_14_en : in STD_LOGIC := 'X'; 
      trd_host_cmd_5_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_5_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_6_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_7_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_8_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_9_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_10_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_11_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_12_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_13_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_14_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_15_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_0_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_1_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_2_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_3_adr_0_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_9_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_8_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_7_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_6_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_5_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_4_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_3_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_2_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_1_Q : out STD_LOGIC; 
      trd_host_cmd_4_adr_0_Q : out STD_LOGIC; 
      trd_host_adr : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
      p : out STD_LOGIC_VECTOR ( 3 downto 1 ); 
      trd_host_data : out STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
      txn : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      txp : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trd_host_cmd_data : out STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
      trd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 63 downto 0 ); 
      trd_cmd_data : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 15 downto 0 ); 
      rxn : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      rxp : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      trd_main_sel_drq : in STD_LOGIC_VECTOR2 ( 15 downto 0 , 6 downto 0 ); 
      trd_main_irq : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
      trd_reset_fifo : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
    );
  end component;
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal clk : STD_LOGIC; 
  signal clk200 : STD_LOGIC; 
  signal clk30k : STD_LOGIC; 
  signal di_clk : STD_LOGIC; 
  signal di_data_we : STD_LOGIC; 
  signal di_fifo_rst : STD_LOGIC; 
  signal di_flag_wr_ef : STD_LOGIC; 
  signal di_flag_wr_ff : STD_LOGIC; 
  signal di_flag_wr_hf : STD_LOGIC; 
  signal di_flag_wr_ovr : STD_LOGIC; 
  signal di_flag_wr_pae : STD_LOGIC; 
  signal di_flag_wr_paf : STD_LOGIC; 
  signal di_flag_wr_und : STD_LOGIC; 
  signal di_start : STD_LOGIC; 
  signal do_clk : STD_LOGIC; 
  signal do_data_cs : STD_LOGIC; 
  signal do_fifo_rst : STD_LOGIC; 
  signal do_flag_rd_ef : STD_LOGIC; 
  signal do_flag_rd_ff : STD_LOGIC; 
  signal do_flag_rd_hf : STD_LOGIC; 
  signal do_flag_rd_ovr : STD_LOGIC; 
  signal do_flag_rd_pae : STD_LOGIC; 
  signal do_flag_rd_paf : STD_LOGIC; 
  signal do_flag_rd_und : STD_LOGIC; 
  signal do_start : STD_LOGIC; 
  signal led_h1 : STD_LOGIC; 
  signal led_h2 : STD_LOGIC; 
  signal led_h3 : STD_LOGIC; 
  signal led_h4 : STD_LOGIC; 
  signal reset : STD_LOGIC; 
  signal reset_main : STD_LOGIC; 
  signal rxn_0_IBUF_36497 : STD_LOGIC; 
  signal rxn_1_IBUF_36498 : STD_LOGIC; 
  signal rxn_2_IBUF_36499 : STD_LOGIC; 
  signal rxn_3_IBUF_36500 : STD_LOGIC; 
  signal rxn_4_IBUF_36501 : STD_LOGIC; 
  signal rxn_5_IBUF_36502 : STD_LOGIC; 
  signal rxn_6_IBUF_36503 : STD_LOGIC; 
  signal rxn_7_IBUF_36504 : STD_LOGIC; 
  signal rxp_0_IBUF_36513 : STD_LOGIC; 
  signal rxp_1_IBUF_36514 : STD_LOGIC; 
  signal rxp_2_IBUF_36515 : STD_LOGIC; 
  signal rxp_3_IBUF_36516 : STD_LOGIC; 
  signal rxp_4_IBUF_36517 : STD_LOGIC; 
  signal rxp_5_IBUF_36518 : STD_LOGIC; 
  signal rxp_6_IBUF_36519 : STD_LOGIC; 
  signal rxp_7_IBUF_36520 : STD_LOGIC; 
  signal test_mode : STD_LOGIC; 
  signal tp1_36522 : STD_LOGIC; 
  signal trd_cmd_data_0_0_Q : STD_LOGIC; 
  signal trd_cmd_data_0_10_Q : STD_LOGIC; 
  signal trd_cmd_data_0_11_Q : STD_LOGIC; 
  signal trd_cmd_data_0_12_Q : STD_LOGIC; 
  signal trd_cmd_data_0_13_Q : STD_LOGIC; 
  signal trd_cmd_data_0_14_Q : STD_LOGIC; 
  signal trd_cmd_data_0_15_Q : STD_LOGIC; 
  signal trd_cmd_data_0_1_Q : STD_LOGIC; 
  signal trd_cmd_data_0_2_Q : STD_LOGIC; 
  signal trd_cmd_data_0_3_Q : STD_LOGIC; 
  signal trd_cmd_data_0_4_Q : STD_LOGIC; 
  signal trd_cmd_data_0_5_Q : STD_LOGIC; 
  signal trd_cmd_data_0_6_Q : STD_LOGIC; 
  signal trd_cmd_data_0_7_Q : STD_LOGIC; 
  signal trd_cmd_data_0_8_Q : STD_LOGIC; 
  signal trd_cmd_data_0_9_Q : STD_LOGIC; 
  signal trd_cmd_data_1_0_Q : STD_LOGIC; 
  signal trd_cmd_data_1_10_Q : STD_LOGIC; 
  signal trd_cmd_data_1_11_Q : STD_LOGIC; 
  signal trd_cmd_data_1_12_Q : STD_LOGIC; 
  signal trd_cmd_data_1_13_Q : STD_LOGIC; 
  signal trd_cmd_data_1_14_Q : STD_LOGIC; 
  signal trd_cmd_data_1_15_Q : STD_LOGIC; 
  signal trd_cmd_data_1_1_Q : STD_LOGIC; 
  signal trd_cmd_data_1_2_Q : STD_LOGIC; 
  signal trd_cmd_data_1_3_Q : STD_LOGIC; 
  signal trd_cmd_data_1_4_Q : STD_LOGIC; 
  signal trd_cmd_data_1_5_Q : STD_LOGIC; 
  signal trd_cmd_data_1_6_Q : STD_LOGIC; 
  signal trd_cmd_data_1_7_Q : STD_LOGIC; 
  signal trd_cmd_data_1_8_Q : STD_LOGIC; 
  signal trd_cmd_data_1_9_Q : STD_LOGIC; 
  signal trd_cmd_data_6_0_Q : STD_LOGIC; 
  signal trd_cmd_data_6_10_Q : STD_LOGIC; 
  signal trd_cmd_data_6_11_Q : STD_LOGIC; 
  signal trd_cmd_data_6_12_Q : STD_LOGIC; 
  signal trd_cmd_data_6_13_Q : STD_LOGIC; 
  signal trd_cmd_data_6_14_Q : STD_LOGIC; 
  signal trd_cmd_data_6_15_Q : STD_LOGIC; 
  signal trd_cmd_data_6_1_Q : STD_LOGIC; 
  signal trd_cmd_data_6_2_Q : STD_LOGIC; 
  signal trd_cmd_data_6_3_Q : STD_LOGIC; 
  signal trd_cmd_data_6_4_Q : STD_LOGIC; 
  signal trd_cmd_data_6_5_Q : STD_LOGIC; 
  signal trd_cmd_data_6_6_Q : STD_LOGIC; 
  signal trd_cmd_data_6_7_Q : STD_LOGIC; 
  signal trd_cmd_data_6_8_Q : STD_LOGIC; 
  signal trd_cmd_data_6_9_Q : STD_LOGIC; 
  signal trd_cmd_data_7_0_Q : STD_LOGIC; 
  signal trd_cmd_data_7_10_Q : STD_LOGIC; 
  signal trd_cmd_data_7_11_Q : STD_LOGIC; 
  signal trd_cmd_data_7_12_Q : STD_LOGIC; 
  signal trd_cmd_data_7_13_Q : STD_LOGIC; 
  signal trd_cmd_data_7_14_Q : STD_LOGIC; 
  signal trd_cmd_data_7_15_Q : STD_LOGIC; 
  signal trd_cmd_data_7_1_Q : STD_LOGIC; 
  signal trd_cmd_data_7_2_Q : STD_LOGIC; 
  signal trd_cmd_data_7_3_Q : STD_LOGIC; 
  signal trd_cmd_data_7_4_Q : STD_LOGIC; 
  signal trd_cmd_data_7_5_Q : STD_LOGIC; 
  signal trd_cmd_data_7_6_Q : STD_LOGIC; 
  signal trd_cmd_data_7_7_Q : STD_LOGIC; 
  signal trd_cmd_data_7_8_Q : STD_LOGIC; 
  signal trd_cmd_data_7_9_Q : STD_LOGIC; 
  signal trd_data_0_0_Q : STD_LOGIC; 
  signal trd_data_0_10_Q : STD_LOGIC; 
  signal trd_data_0_11_Q : STD_LOGIC; 
  signal trd_data_0_12_Q : STD_LOGIC; 
  signal trd_data_0_13_Q : STD_LOGIC; 
  signal trd_data_0_14_Q : STD_LOGIC; 
  signal trd_data_0_15_Q : STD_LOGIC; 
  signal trd_data_0_16_Q : STD_LOGIC; 
  signal trd_data_0_17_Q : STD_LOGIC; 
  signal trd_data_0_18_Q : STD_LOGIC; 
  signal trd_data_0_19_Q : STD_LOGIC; 
  signal trd_data_0_1_Q : STD_LOGIC; 
  signal trd_data_0_20_Q : STD_LOGIC; 
  signal trd_data_0_21_Q : STD_LOGIC; 
  signal trd_data_0_22_Q : STD_LOGIC; 
  signal trd_data_0_23_Q : STD_LOGIC; 
  signal trd_data_0_24_Q : STD_LOGIC; 
  signal trd_data_0_25_Q : STD_LOGIC; 
  signal trd_data_0_26_Q : STD_LOGIC; 
  signal trd_data_0_27_Q : STD_LOGIC; 
  signal trd_data_0_28_Q : STD_LOGIC; 
  signal trd_data_0_29_Q : STD_LOGIC; 
  signal trd_data_0_2_Q : STD_LOGIC; 
  signal trd_data_0_30_Q : STD_LOGIC; 
  signal trd_data_0_31_Q : STD_LOGIC; 
  signal trd_data_0_32_Q : STD_LOGIC; 
  signal trd_data_0_33_Q : STD_LOGIC; 
  signal trd_data_0_34_Q : STD_LOGIC; 
  signal trd_data_0_35_Q : STD_LOGIC; 
  signal trd_data_0_36_Q : STD_LOGIC; 
  signal trd_data_0_37_Q : STD_LOGIC; 
  signal trd_data_0_38_Q : STD_LOGIC; 
  signal trd_data_0_39_Q : STD_LOGIC; 
  signal trd_data_0_3_Q : STD_LOGIC; 
  signal trd_data_0_40_Q : STD_LOGIC; 
  signal trd_data_0_41_Q : STD_LOGIC; 
  signal trd_data_0_42_Q : STD_LOGIC; 
  signal trd_data_0_43_Q : STD_LOGIC; 
  signal trd_data_0_44_Q : STD_LOGIC; 
  signal trd_data_0_45_Q : STD_LOGIC; 
  signal trd_data_0_46_Q : STD_LOGIC; 
  signal trd_data_0_47_Q : STD_LOGIC; 
  signal trd_data_0_48_Q : STD_LOGIC; 
  signal trd_data_0_49_Q : STD_LOGIC; 
  signal trd_data_0_4_Q : STD_LOGIC; 
  signal trd_data_0_50_Q : STD_LOGIC; 
  signal trd_data_0_51_Q : STD_LOGIC; 
  signal trd_data_0_52_Q : STD_LOGIC; 
  signal trd_data_0_53_Q : STD_LOGIC; 
  signal trd_data_0_54_Q : STD_LOGIC; 
  signal trd_data_0_55_Q : STD_LOGIC; 
  signal trd_data_0_56_Q : STD_LOGIC; 
  signal trd_data_0_57_Q : STD_LOGIC; 
  signal trd_data_0_58_Q : STD_LOGIC; 
  signal trd_data_0_59_Q : STD_LOGIC; 
  signal trd_data_0_5_Q : STD_LOGIC; 
  signal trd_data_0_60_Q : STD_LOGIC; 
  signal trd_data_0_61_Q : STD_LOGIC; 
  signal trd_data_0_62_Q : STD_LOGIC; 
  signal trd_data_0_63_Q : STD_LOGIC; 
  signal trd_data_0_6_Q : STD_LOGIC; 
  signal trd_data_0_7_Q : STD_LOGIC; 
  signal trd_data_0_8_Q : STD_LOGIC; 
  signal trd_data_0_9_Q : STD_LOGIC; 
  signal trd_data_6_0_Q : STD_LOGIC; 
  signal trd_data_6_10_Q : STD_LOGIC; 
  signal trd_data_6_11_Q : STD_LOGIC; 
  signal trd_data_6_12_Q : STD_LOGIC; 
  signal trd_data_6_13_Q : STD_LOGIC; 
  signal trd_data_6_14_Q : STD_LOGIC; 
  signal trd_data_6_15_Q : STD_LOGIC; 
  signal trd_data_6_16_Q : STD_LOGIC; 
  signal trd_data_6_17_Q : STD_LOGIC; 
  signal trd_data_6_18_Q : STD_LOGIC; 
  signal trd_data_6_19_Q : STD_LOGIC; 
  signal trd_data_6_1_Q : STD_LOGIC; 
  signal trd_data_6_20_Q : STD_LOGIC; 
  signal trd_data_6_21_Q : STD_LOGIC; 
  signal trd_data_6_22_Q : STD_LOGIC; 
  signal trd_data_6_23_Q : STD_LOGIC; 
  signal trd_data_6_24_Q : STD_LOGIC; 
  signal trd_data_6_25_Q : STD_LOGIC; 
  signal trd_data_6_26_Q : STD_LOGIC; 
  signal trd_data_6_27_Q : STD_LOGIC; 
  signal trd_data_6_28_Q : STD_LOGIC; 
  signal trd_data_6_29_Q : STD_LOGIC; 
  signal trd_data_6_2_Q : STD_LOGIC; 
  signal trd_data_6_30_Q : STD_LOGIC; 
  signal trd_data_6_31_Q : STD_LOGIC; 
  signal trd_data_6_32_Q : STD_LOGIC; 
  signal trd_data_6_33_Q : STD_LOGIC; 
  signal trd_data_6_34_Q : STD_LOGIC; 
  signal trd_data_6_35_Q : STD_LOGIC; 
  signal trd_data_6_36_Q : STD_LOGIC; 
  signal trd_data_6_37_Q : STD_LOGIC; 
  signal trd_data_6_38_Q : STD_LOGIC; 
  signal trd_data_6_39_Q : STD_LOGIC; 
  signal trd_data_6_3_Q : STD_LOGIC; 
  signal trd_data_6_40_Q : STD_LOGIC; 
  signal trd_data_6_41_Q : STD_LOGIC; 
  signal trd_data_6_42_Q : STD_LOGIC; 
  signal trd_data_6_43_Q : STD_LOGIC; 
  signal trd_data_6_44_Q : STD_LOGIC; 
  signal trd_data_6_45_Q : STD_LOGIC; 
  signal trd_data_6_46_Q : STD_LOGIC; 
  signal trd_data_6_47_Q : STD_LOGIC; 
  signal trd_data_6_48_Q : STD_LOGIC; 
  signal trd_data_6_49_Q : STD_LOGIC; 
  signal trd_data_6_4_Q : STD_LOGIC; 
  signal trd_data_6_50_Q : STD_LOGIC; 
  signal trd_data_6_51_Q : STD_LOGIC; 
  signal trd_data_6_52_Q : STD_LOGIC; 
  signal trd_data_6_53_Q : STD_LOGIC; 
  signal trd_data_6_54_Q : STD_LOGIC; 
  signal trd_data_6_55_Q : STD_LOGIC; 
  signal trd_data_6_56_Q : STD_LOGIC; 
  signal trd_data_6_57_Q : STD_LOGIC; 
  signal trd_data_6_58_Q : STD_LOGIC; 
  signal trd_data_6_59_Q : STD_LOGIC; 
  signal trd_data_6_5_Q : STD_LOGIC; 
  signal trd_data_6_60_Q : STD_LOGIC; 
  signal trd_data_6_61_Q : STD_LOGIC; 
  signal trd_data_6_62_Q : STD_LOGIC; 
  signal trd_data_6_63_Q : STD_LOGIC; 
  signal trd_data_6_6_Q : STD_LOGIC; 
  signal trd_data_6_7_Q : STD_LOGIC; 
  signal trd_data_6_8_Q : STD_LOGIC; 
  signal trd_data_6_9_Q : STD_LOGIC; 
  signal trd_drq_0_ack : STD_LOGIC; 
  signal trd_drq_0_en : STD_LOGIC; 
  signal trd_drq_0_req : STD_LOGIC; 
  signal trd_drq_1_ack : STD_LOGIC; 
  signal trd_drq_1_en : STD_LOGIC; 
  signal trd_drq_1_req : STD_LOGIC; 
  signal trd_drq_6_ack : STD_LOGIC; 
  signal trd_drq_6_en : STD_LOGIC; 
  signal trd_drq_6_req : STD_LOGIC; 
  signal trd_drq_7_ack : STD_LOGIC; 
  signal trd_drq_7_en : STD_LOGIC; 
  signal trd_drq_7_req : STD_LOGIC; 
  signal trd_host_cmd_0_adr_0_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_1_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_2_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_3_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_4_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_5_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_6_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_7_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_8_Q : STD_LOGIC; 
  signal trd_host_cmd_0_adr_9_Q : STD_LOGIC; 
  signal trd_host_cmd_0_cmd_adr_we : STD_LOGIC; 
  signal trd_host_cmd_0_cmd_data_cs : STD_LOGIC; 
  signal trd_host_cmd_0_cmd_data_we : STD_LOGIC; 
  signal trd_host_cmd_0_data_cs : STD_LOGIC; 
  signal trd_host_cmd_0_data_oe : STD_LOGIC; 
  signal trd_host_cmd_0_data_we : STD_LOGIC; 
  signal trd_host_cmd_0_status_cs : STD_LOGIC; 
  signal trd_host_cmd_1_adr_0_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_1_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_2_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_3_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_4_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_5_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_6_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_7_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_8_Q : STD_LOGIC; 
  signal trd_host_cmd_1_adr_9_Q : STD_LOGIC; 
  signal trd_host_cmd_1_cmd_adr_we : STD_LOGIC; 
  signal trd_host_cmd_1_cmd_data_cs : STD_LOGIC; 
  signal trd_host_cmd_1_cmd_data_we : STD_LOGIC; 
  signal trd_host_cmd_1_data_cs : STD_LOGIC; 
  signal trd_host_cmd_1_data_oe : STD_LOGIC; 
  signal trd_host_cmd_1_data_we : STD_LOGIC; 
  signal trd_host_cmd_1_status_cs : STD_LOGIC; 
  signal trd_host_cmd_6_adr_0_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_1_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_2_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_3_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_4_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_5_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_6_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_7_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_8_Q : STD_LOGIC; 
  signal trd_host_cmd_6_adr_9_Q : STD_LOGIC; 
  signal trd_host_cmd_6_cmd_adr_we : STD_LOGIC; 
  signal trd_host_cmd_6_cmd_data_cs : STD_LOGIC; 
  signal trd_host_cmd_6_cmd_data_we : STD_LOGIC; 
  signal trd_host_cmd_6_data_cs : STD_LOGIC; 
  signal trd_host_cmd_6_data_oe : STD_LOGIC; 
  signal trd_host_cmd_6_data_we : STD_LOGIC; 
  signal trd_host_cmd_6_status_cs : STD_LOGIC; 
  signal trd_host_cmd_7_adr_0_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_1_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_2_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_3_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_4_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_5_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_6_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_7_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_8_Q : STD_LOGIC; 
  signal trd_host_cmd_7_adr_9_Q : STD_LOGIC; 
  signal trd_host_cmd_7_cmd_adr_we : STD_LOGIC; 
  signal trd_host_cmd_7_cmd_data_cs : STD_LOGIC; 
  signal trd_host_cmd_7_cmd_data_we : STD_LOGIC; 
  signal trd_host_cmd_7_data_cs : STD_LOGIC; 
  signal trd_host_cmd_7_data_oe : STD_LOGIC; 
  signal trd_host_cmd_7_data_we : STD_LOGIC; 
  signal trd_host_cmd_7_status_cs : STD_LOGIC; 
  signal trd_host_cmd_data_0_0_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_10_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_11_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_12_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_13_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_14_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_15_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_1_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_2_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_3_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_4_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_5_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_6_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_7_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_8_Q : STD_LOGIC; 
  signal trd_host_cmd_data_0_9_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_0_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_10_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_11_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_12_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_13_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_14_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_15_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_1_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_2_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_3_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_4_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_5_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_6_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_7_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_8_Q : STD_LOGIC; 
  signal trd_host_cmd_data_1_9_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_0_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_10_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_11_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_12_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_13_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_14_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_15_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_1_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_2_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_3_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_4_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_5_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_6_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_7_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_8_Q : STD_LOGIC; 
  signal trd_host_cmd_data_6_9_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_0_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_10_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_11_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_12_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_13_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_14_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_15_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_1_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_2_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_3_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_4_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_5_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_6_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_7_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_8_Q : STD_LOGIC; 
  signal trd_host_cmd_data_7_9_Q : STD_LOGIC; 
  signal trd_host_data_0_0_Q : STD_LOGIC; 
  signal trd_host_data_0_10_Q : STD_LOGIC; 
  signal trd_host_data_0_11_Q : STD_LOGIC; 
  signal trd_host_data_0_12_Q : STD_LOGIC; 
  signal trd_host_data_0_13_Q : STD_LOGIC; 
  signal trd_host_data_0_14_Q : STD_LOGIC; 
  signal trd_host_data_0_15_Q : STD_LOGIC; 
  signal trd_host_data_0_16_Q : STD_LOGIC; 
  signal trd_host_data_0_17_Q : STD_LOGIC; 
  signal trd_host_data_0_18_Q : STD_LOGIC; 
  signal trd_host_data_0_19_Q : STD_LOGIC; 
  signal trd_host_data_0_1_Q : STD_LOGIC; 
  signal trd_host_data_0_20_Q : STD_LOGIC; 
  signal trd_host_data_0_21_Q : STD_LOGIC; 
  signal trd_host_data_0_22_Q : STD_LOGIC; 
  signal trd_host_data_0_23_Q : STD_LOGIC; 
  signal trd_host_data_0_24_Q : STD_LOGIC; 
  signal trd_host_data_0_25_Q : STD_LOGIC; 
  signal trd_host_data_0_26_Q : STD_LOGIC; 
  signal trd_host_data_0_27_Q : STD_LOGIC; 
  signal trd_host_data_0_28_Q : STD_LOGIC; 
  signal trd_host_data_0_29_Q : STD_LOGIC; 
  signal trd_host_data_0_2_Q : STD_LOGIC; 
  signal trd_host_data_0_30_Q : STD_LOGIC; 
  signal trd_host_data_0_31_Q : STD_LOGIC; 
  signal trd_host_data_0_32_Q : STD_LOGIC; 
  signal trd_host_data_0_33_Q : STD_LOGIC; 
  signal trd_host_data_0_34_Q : STD_LOGIC; 
  signal trd_host_data_0_35_Q : STD_LOGIC; 
  signal trd_host_data_0_36_Q : STD_LOGIC; 
  signal trd_host_data_0_37_Q : STD_LOGIC; 
  signal trd_host_data_0_38_Q : STD_LOGIC; 
  signal trd_host_data_0_39_Q : STD_LOGIC; 
  signal trd_host_data_0_3_Q : STD_LOGIC; 
  signal trd_host_data_0_40_Q : STD_LOGIC; 
  signal trd_host_data_0_41_Q : STD_LOGIC; 
  signal trd_host_data_0_42_Q : STD_LOGIC; 
  signal trd_host_data_0_43_Q : STD_LOGIC; 
  signal trd_host_data_0_44_Q : STD_LOGIC; 
  signal trd_host_data_0_45_Q : STD_LOGIC; 
  signal trd_host_data_0_46_Q : STD_LOGIC; 
  signal trd_host_data_0_47_Q : STD_LOGIC; 
  signal trd_host_data_0_48_Q : STD_LOGIC; 
  signal trd_host_data_0_49_Q : STD_LOGIC; 
  signal trd_host_data_0_4_Q : STD_LOGIC; 
  signal trd_host_data_0_50_Q : STD_LOGIC; 
  signal trd_host_data_0_51_Q : STD_LOGIC; 
  signal trd_host_data_0_52_Q : STD_LOGIC; 
  signal trd_host_data_0_53_Q : STD_LOGIC; 
  signal trd_host_data_0_54_Q : STD_LOGIC; 
  signal trd_host_data_0_55_Q : STD_LOGIC; 
  signal trd_host_data_0_56_Q : STD_LOGIC; 
  signal trd_host_data_0_57_Q : STD_LOGIC; 
  signal trd_host_data_0_58_Q : STD_LOGIC; 
  signal trd_host_data_0_59_Q : STD_LOGIC; 
  signal trd_host_data_0_5_Q : STD_LOGIC; 
  signal trd_host_data_0_60_Q : STD_LOGIC; 
  signal trd_host_data_0_61_Q : STD_LOGIC; 
  signal trd_host_data_0_62_Q : STD_LOGIC; 
  signal trd_host_data_0_63_Q : STD_LOGIC; 
  signal trd_host_data_0_6_Q : STD_LOGIC; 
  signal trd_host_data_0_7_Q : STD_LOGIC; 
  signal trd_host_data_0_8_Q : STD_LOGIC; 
  signal trd_host_data_0_9_Q : STD_LOGIC; 
  signal trd_host_data_7_0_Q : STD_LOGIC; 
  signal trd_host_data_7_10_Q : STD_LOGIC; 
  signal trd_host_data_7_11_Q : STD_LOGIC; 
  signal trd_host_data_7_12_Q : STD_LOGIC; 
  signal trd_host_data_7_13_Q : STD_LOGIC; 
  signal trd_host_data_7_14_Q : STD_LOGIC; 
  signal trd_host_data_7_15_Q : STD_LOGIC; 
  signal trd_host_data_7_16_Q : STD_LOGIC; 
  signal trd_host_data_7_17_Q : STD_LOGIC; 
  signal trd_host_data_7_18_Q : STD_LOGIC; 
  signal trd_host_data_7_19_Q : STD_LOGIC; 
  signal trd_host_data_7_1_Q : STD_LOGIC; 
  signal trd_host_data_7_20_Q : STD_LOGIC; 
  signal trd_host_data_7_21_Q : STD_LOGIC; 
  signal trd_host_data_7_22_Q : STD_LOGIC; 
  signal trd_host_data_7_23_Q : STD_LOGIC; 
  signal trd_host_data_7_24_Q : STD_LOGIC; 
  signal trd_host_data_7_25_Q : STD_LOGIC; 
  signal trd_host_data_7_26_Q : STD_LOGIC; 
  signal trd_host_data_7_27_Q : STD_LOGIC; 
  signal trd_host_data_7_28_Q : STD_LOGIC; 
  signal trd_host_data_7_29_Q : STD_LOGIC; 
  signal trd_host_data_7_2_Q : STD_LOGIC; 
  signal trd_host_data_7_30_Q : STD_LOGIC; 
  signal trd_host_data_7_31_Q : STD_LOGIC; 
  signal trd_host_data_7_32_Q : STD_LOGIC; 
  signal trd_host_data_7_33_Q : STD_LOGIC; 
  signal trd_host_data_7_34_Q : STD_LOGIC; 
  signal trd_host_data_7_35_Q : STD_LOGIC; 
  signal trd_host_data_7_36_Q : STD_LOGIC; 
  signal trd_host_data_7_37_Q : STD_LOGIC; 
  signal trd_host_data_7_38_Q : STD_LOGIC; 
  signal trd_host_data_7_39_Q : STD_LOGIC; 
  signal trd_host_data_7_3_Q : STD_LOGIC; 
  signal trd_host_data_7_40_Q : STD_LOGIC; 
  signal trd_host_data_7_41_Q : STD_LOGIC; 
  signal trd_host_data_7_42_Q : STD_LOGIC; 
  signal trd_host_data_7_43_Q : STD_LOGIC; 
  signal trd_host_data_7_44_Q : STD_LOGIC; 
  signal trd_host_data_7_45_Q : STD_LOGIC; 
  signal trd_host_data_7_46_Q : STD_LOGIC; 
  signal trd_host_data_7_47_Q : STD_LOGIC; 
  signal trd_host_data_7_48_Q : STD_LOGIC; 
  signal trd_host_data_7_49_Q : STD_LOGIC; 
  signal trd_host_data_7_4_Q : STD_LOGIC; 
  signal trd_host_data_7_50_Q : STD_LOGIC; 
  signal trd_host_data_7_51_Q : STD_LOGIC; 
  signal trd_host_data_7_52_Q : STD_LOGIC; 
  signal trd_host_data_7_53_Q : STD_LOGIC; 
  signal trd_host_data_7_54_Q : STD_LOGIC; 
  signal trd_host_data_7_55_Q : STD_LOGIC; 
  signal trd_host_data_7_56_Q : STD_LOGIC; 
  signal trd_host_data_7_57_Q : STD_LOGIC; 
  signal trd_host_data_7_58_Q : STD_LOGIC; 
  signal trd_host_data_7_59_Q : STD_LOGIC; 
  signal trd_host_data_7_5_Q : STD_LOGIC; 
  signal trd_host_data_7_60_Q : STD_LOGIC; 
  signal trd_host_data_7_61_Q : STD_LOGIC; 
  signal trd_host_data_7_62_Q : STD_LOGIC; 
  signal trd_host_data_7_63_Q : STD_LOGIC; 
  signal trd_host_data_7_6_Q : STD_LOGIC; 
  signal trd_host_data_7_7_Q : STD_LOGIC; 
  signal trd_host_data_7_8_Q : STD_LOGIC; 
  signal trd_host_data_7_9_Q : STD_LOGIC; 
  signal trd_irq_1_Q : STD_LOGIC; 
  signal trd_irq_6_Q : STD_LOGIC; 
  signal trd_irq_7_Q : STD_LOGIC; 
  signal trd_main_drq_0_ack : STD_LOGIC; 
  signal trd_main_drq_0_en : STD_LOGIC; 
  signal trd_main_drq_0_req : STD_LOGIC; 
  signal trd_main_drq_1_ack : STD_LOGIC; 
  signal trd_main_drq_1_en : STD_LOGIC; 
  signal trd_main_drq_1_req : STD_LOGIC; 
  signal trd_main_drq_2_ack : STD_LOGIC; 
  signal trd_main_drq_2_en : STD_LOGIC; 
  signal trd_main_drq_2_req : STD_LOGIC; 
  signal trd_main_drq_3_ack : STD_LOGIC; 
  signal trd_main_drq_3_en : STD_LOGIC; 
  signal trd_main_drq_3_req : STD_LOGIC; 
  signal txn_0_OBUF_37019 : STD_LOGIC; 
  signal txn_1_OBUF_37020 : STD_LOGIC; 
  signal txn_2_OBUF_37021 : STD_LOGIC; 
  signal txn_3_OBUF_37022 : STD_LOGIC; 
  signal txn_4_OBUF_37023 : STD_LOGIC; 
  signal txn_5_OBUF_37024 : STD_LOGIC; 
  signal txn_6_OBUF_37025 : STD_LOGIC; 
  signal txn_7_OBUF_37026 : STD_LOGIC; 
  signal txp_0_OBUF_37035 : STD_LOGIC; 
  signal txp_1_OBUF_37036 : STD_LOGIC; 
  signal txp_2_OBUF_37037 : STD_LOGIC; 
  signal txp_3_OBUF_37038 : STD_LOGIC; 
  signal txp_4_OBUF_37039 : STD_LOGIC; 
  signal txp_5_OBUF_37040 : STD_LOGIC; 
  signal txp_6_OBUF_37041 : STD_LOGIC; 
  signal txp_7_OBUF_37042 : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_clk5_pll_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_clk_lock_out_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_clk2_pll_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_clk4_pll_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_cmd_adr_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_cmd_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_data_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_clk3_pll_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_cmd_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_status_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_data_we_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_data_cs_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_5_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_8_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_9_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_p_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_p_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_10_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_11_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_12_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_13_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_14_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_15_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_14_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_13_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_12_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_11_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_10_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_9_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_8_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_6_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_5_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_4_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_data_1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_15_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_15_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_14_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_13_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_12_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_11_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_10_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_9_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_8_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_5_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_4_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_data_2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_2_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_3_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_amb_trd_host_cmd_4_adr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_mode3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_fifo_cnt_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_cmd_data_out_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_out_test_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_ef_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_ff_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_hf_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_ovr_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_und_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_pae_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_flag_rd_paf_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_rd_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_63_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_62_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_61_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_60_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_59_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_58_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_57_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_56_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_55_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_54_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_53_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_52_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_51_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_50_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_49_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_48_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_47_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_46_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_45_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_44_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_43_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_42_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_41_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_40_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_39_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_38_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_37_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_36_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_35_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_34_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_33_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_32_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_31_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_30_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_29_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_28_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_27_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_26_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_25_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_24_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_23_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_22_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_21_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_20_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_19_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_18_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_17_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_16_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_data_out_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_fifo_cnt_wr_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_mode3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_dio_in_cmd_data_out_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_mode3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_test_ctrl_cmd_data_out_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_cp0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_cp1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_bx_start_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_thld_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_rdy0_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_bx_start_a_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_sync0_out_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_bx_clk_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_rdy0_out_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_goe0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_goe1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_thrs_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_bx_start_sync_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_rdy1_out_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_thclk_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_rdy1_oe_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_thdin_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_int2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_int3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_start_en_out_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sn_master_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq2_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_sel_drq3_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode0_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_mode1_0_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_15_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_14_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_13_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_12_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_11_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_10_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_9_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_8_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_7_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_6_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_5_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_4_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_3_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_main_synx_0_UNCONNECTED : STD_LOGIC; 
  signal di_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal di_mode1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal do_data : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal do_mode1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal px : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal trd_host_adr : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal trd_main_irq : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal trd_reset_fifo : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  XST_GND : GND
    port map (
      G => N0
    );
  XST_VCC : VCC
    port map (
      P => N1
    );
  tp1 : FDR
    port map (
      C => clk,
      D => N1,
      R => tp1_36522,
      Q => tp1_36522
    );
  xled1 : OBUF_S_16
    port map (
      I => led_h1,
      O => bled1
    );
  xled2 : OBUF_S_16
    port map (
      I => led_h2,
      O => bled2
    );
  xled3 : OBUF_S_16
    port map (
      I => led_h3,
      O => bled3
    );
  xled4 : OBUF_S_16
    port map (
      I => led_h4,
      O => bled4
    );
  btp1 : OBUF_F_16
    port map (
      I => tp1_36522,
      O => btp(1)
    );
  btp2 : OBUF_F_16
    port map (
      I => px(2),
      O => btp(2)
    );
  btp3 : OBUF_F_16
    port map (
      I => clk30k,
      O => btp(3)
    );
  main : trd_main_v8
    port map (
      b4_drq_ack => N0,
      cp0 => NLW_main_cp0_UNCONNECTED,
      cp1 => NLW_main_cp1_UNCONNECTED,
      clk => clk,
      b3_drq_ack => N0,
      b9_drq_en => N0,
      b6_irq => trd_irq_6_Q,
      bx_start => NLW_main_bx_start_UNCONNECTED,
      thld => NLW_main_thld_UNCONNECTED,
      drq1_ack => trd_main_drq_1_ack,
      b2_drq_ack => N0,
      sn_rdy0_oe => NLW_main_sn_rdy0_oe_UNCONNECTED,
      b4_drq_en => N0,
      drq1_en => trd_main_drq_1_en,
      bx_start_a => NLW_main_bx_start_a_UNCONNECTED,
      b2_irq => N0,
      drq0_req => trd_main_drq_0_req,
      b12_irq => N0,
      b9_drq_req => N0,
      b1_drq_ack => trd_drq_1_ack,
      b8_drq_req => N0,
      b12_drq_en => N0,
      b7_drq_req => trd_drq_7_req,
      test_mode => test_mode,
      sn_sync0_out => NLW_main_sn_sync0_out_UNCONNECTED,
      bx_clk => NLW_main_bx_clk_UNCONNECTED,
      b15_drq_ack => N0,
      reset => reset_main,
      cmd_cmd_data_we => trd_host_cmd_0_cmd_data_we,
      b6_drq_req => trd_drq_6_req,
      b14_drq_ack => N0,
      sn_rdy0_out => NLW_main_sn_rdy0_out_UNCONNECTED,
      b5_drq_req => N0,
      b8_drq_en => N0,
      goe0 => NLW_main_goe0_UNCONNECTED,
      goe1 => NLW_main_goe1_UNCONNECTED,
      b13_drq_ack => N0,
      b4_drq_req => N0,
      thrs => NLW_main_thrs_UNCONNECTED,
      b7_irq => trd_irq_7_Q,
      sn_sync0 => N0,
      drq2_ack => trd_main_drq_2_ack,
      b3_drq_en => N0,
      b12_drq_ack => N0,
      b3_drq_req => N0,
      b3_irq => N0,
      drq1_req => trd_main_drq_1_req,
      b13_irq => N0,
      b11_drq_ack => N0,
      b11_drq_en => N0,
      b2_drq_req => N0,
      cmd_status_cs => trd_host_cmd_0_status_cs,
      sn_start_en => N0,
      b10_drq_ack => N0,
      drq3_en => trd_main_drq_3_en,
      test_mode_init => N1,
      b1_drq_req => trd_drq_1_req,
      bx_start_sync => NLW_main_bx_start_sync_UNCONNECTED,
      drq0_en => trd_main_drq_0_en,
      b7_drq_en => trd_drq_7_en,
      sn_rdy1_out => NLW_main_sn_rdy1_out_UNCONNECTED,
      b15_drq_req => N0,
      b2_drq_en => N0,
      cmd_data_cs => trd_host_cmd_0_data_cs,
      b14_drq_req => N0,
      b15_drq_en => N0,
      b8_irq => N0,
      drq3_ack => trd_main_drq_3_ack,
      b10_drq_en => N0,
      b13_drq_req => N0,
      fifo_rst_out => trd_reset_fifo(0),
      drq2_req => trd_main_drq_2_req,
      b4_irq => N0,
      b14_irq => N0,
      b12_drq_req => N0,
      bx_drq_en => trd_drq_0_en,
      b10_irq => N0,
      sn_rdy0 => N0,
      b11_drq_req => N0,
      sn_rdy1 => N0,
      b6_drq_en => trd_drq_6_en,
      b10_drq_req => N0,
      thclk => NLW_main_thclk_UNCONNECTED,
      bx_drq_ack => trd_drq_0_ack,
      b1_drq_en => trd_drq_1_en,
      sn_rdy1_oe => NLW_main_sn_rdy1_oe_UNCONNECTED,
      b14_drq_en => N0,
      drq2_en => trd_main_drq_2_en,
      cmd_data_oe => trd_host_cmd_0_data_oe,
      thdin => NLW_main_thdin_UNCONNECTED,
      cmd_cmd_data_cs => trd_host_cmd_0_cmd_data_cs,
      b9_irq => N0,
      b5_irq => N0,
      drq3_req => trd_main_drq_3_req,
      drq0_ack => trd_main_drq_0_ack,
      int1 => trd_main_irq(1),
      b15_irq => N0,
      int2 => NLW_main_int2_UNCONNECTED,
      b9_drq_ack => N0,
      int3 => NLW_main_int3_UNCONNECTED,
      b8_drq_ack => N0,
      b1_irq => trd_irq_1_Q,
      sn_start_en_out => NLW_main_sn_start_en_out_UNCONNECTED,
      b11_irq => N0,
      sn_sync0_in => N0,
      b5_drq_en => N0,
      b7_drq_ack => trd_drq_7_ack,
      cmd_cmd_adr_we => trd_host_cmd_0_cmd_adr_we,
      b6_drq_ack => trd_drq_6_ack,
      reset_out => reset,
      b13_drq_en => N0,
      cmd_data_we => trd_host_cmd_0_data_we,
      b5_drq_ack => N0,
      bx_drq_req => trd_drq_0_req,
      sn_master => NLW_main_sn_master_UNCONNECTED,
      sel_drq0(6) => NLW_main_sel_drq0_6_UNCONNECTED,
      sel_drq0(5) => NLW_main_sel_drq0_5_UNCONNECTED,
      sel_drq0(4) => NLW_main_sel_drq0_4_UNCONNECTED,
      sel_drq0(3) => NLW_main_sel_drq0_3_UNCONNECTED,
      sel_drq0(2) => NLW_main_sel_drq0_2_UNCONNECTED,
      sel_drq0(1) => NLW_main_sel_drq0_1_UNCONNECTED,
      sel_drq0(0) => NLW_main_sel_drq0_0_UNCONNECTED,
      sel_drq1(6) => NLW_main_sel_drq1_6_UNCONNECTED,
      sel_drq1(5) => NLW_main_sel_drq1_5_UNCONNECTED,
      sel_drq1(4) => NLW_main_sel_drq1_4_UNCONNECTED,
      sel_drq1(3) => NLW_main_sel_drq1_3_UNCONNECTED,
      sel_drq1(2) => NLW_main_sel_drq1_2_UNCONNECTED,
      sel_drq1(1) => NLW_main_sel_drq1_1_UNCONNECTED,
      sel_drq1(0) => NLW_main_sel_drq1_0_UNCONNECTED,
      sel_drq2(6) => NLW_main_sel_drq2_6_UNCONNECTED,
      sel_drq2(5) => NLW_main_sel_drq2_5_UNCONNECTED,
      sel_drq2(4) => NLW_main_sel_drq2_4_UNCONNECTED,
      sel_drq2(3) => NLW_main_sel_drq2_3_UNCONNECTED,
      sel_drq2(2) => NLW_main_sel_drq2_2_UNCONNECTED,
      sel_drq2(1) => NLW_main_sel_drq2_1_UNCONNECTED,
      sel_drq2(0) => NLW_main_sel_drq2_0_UNCONNECTED,
      sel_drq3(6) => NLW_main_sel_drq3_6_UNCONNECTED,
      sel_drq3(5) => NLW_main_sel_drq3_5_UNCONNECTED,
      sel_drq3(4) => NLW_main_sel_drq3_4_UNCONNECTED,
      sel_drq3(3) => NLW_main_sel_drq3_3_UNCONNECTED,
      sel_drq3(2) => NLW_main_sel_drq3_2_UNCONNECTED,
      sel_drq3(1) => NLW_main_sel_drq3_1_UNCONNECTED,
      sel_drq3(0) => NLW_main_sel_drq3_0_UNCONNECTED,
      data_out(63) => trd_data_0_63_Q,
      data_out(62) => trd_data_0_62_Q,
      data_out(61) => trd_data_0_61_Q,
      data_out(60) => trd_data_0_60_Q,
      data_out(59) => trd_data_0_59_Q,
      data_out(58) => trd_data_0_58_Q,
      data_out(57) => trd_data_0_57_Q,
      data_out(56) => trd_data_0_56_Q,
      data_out(55) => trd_data_0_55_Q,
      data_out(54) => trd_data_0_54_Q,
      data_out(53) => trd_data_0_53_Q,
      data_out(52) => trd_data_0_52_Q,
      data_out(51) => trd_data_0_51_Q,
      data_out(50) => trd_data_0_50_Q,
      data_out(49) => trd_data_0_49_Q,
      data_out(48) => trd_data_0_48_Q,
      data_out(47) => trd_data_0_47_Q,
      data_out(46) => trd_data_0_46_Q,
      data_out(45) => trd_data_0_45_Q,
      data_out(44) => trd_data_0_44_Q,
      data_out(43) => trd_data_0_43_Q,
      data_out(42) => trd_data_0_42_Q,
      data_out(41) => trd_data_0_41_Q,
      data_out(40) => trd_data_0_40_Q,
      data_out(39) => trd_data_0_39_Q,
      data_out(38) => trd_data_0_38_Q,
      data_out(37) => trd_data_0_37_Q,
      data_out(36) => trd_data_0_36_Q,
      data_out(35) => trd_data_0_35_Q,
      data_out(34) => trd_data_0_34_Q,
      data_out(33) => trd_data_0_33_Q,
      data_out(32) => trd_data_0_32_Q,
      data_out(31) => trd_data_0_31_Q,
      data_out(30) => trd_data_0_30_Q,
      data_out(29) => trd_data_0_29_Q,
      data_out(28) => trd_data_0_28_Q,
      data_out(27) => trd_data_0_27_Q,
      data_out(26) => trd_data_0_26_Q,
      data_out(25) => trd_data_0_25_Q,
      data_out(24) => trd_data_0_24_Q,
      data_out(23) => trd_data_0_23_Q,
      data_out(22) => trd_data_0_22_Q,
      data_out(21) => trd_data_0_21_Q,
      data_out(20) => trd_data_0_20_Q,
      data_out(19) => trd_data_0_19_Q,
      data_out(18) => trd_data_0_18_Q,
      data_out(17) => trd_data_0_17_Q,
      data_out(16) => trd_data_0_16_Q,
      data_out(15) => trd_data_0_15_Q,
      data_out(14) => trd_data_0_14_Q,
      data_out(13) => trd_data_0_13_Q,
      data_out(12) => trd_data_0_12_Q,
      data_out(11) => trd_data_0_11_Q,
      data_out(10) => trd_data_0_10_Q,
      data_out(9) => trd_data_0_9_Q,
      data_out(8) => trd_data_0_8_Q,
      data_out(7) => trd_data_0_7_Q,
      data_out(6) => trd_data_0_6_Q,
      data_out(5) => trd_data_0_5_Q,
      data_out(4) => trd_data_0_4_Q,
      data_out(3) => trd_data_0_3_Q,
      data_out(2) => trd_data_0_2_Q,
      data_out(1) => trd_data_0_1_Q,
      data_out(0) => trd_data_0_0_Q,
      mode0(15) => NLW_main_mode0_15_UNCONNECTED,
      mode0(14) => NLW_main_mode0_14_UNCONNECTED,
      mode0(13) => NLW_main_mode0_13_UNCONNECTED,
      mode0(12) => NLW_main_mode0_12_UNCONNECTED,
      mode0(11) => NLW_main_mode0_11_UNCONNECTED,
      mode0(10) => NLW_main_mode0_10_UNCONNECTED,
      mode0(9) => NLW_main_mode0_9_UNCONNECTED,
      mode0(8) => NLW_main_mode0_8_UNCONNECTED,
      mode0(7) => NLW_main_mode0_7_UNCONNECTED,
      mode0(6) => NLW_main_mode0_6_UNCONNECTED,
      mode0(5) => NLW_main_mode0_5_UNCONNECTED,
      mode0(4) => NLW_main_mode0_4_UNCONNECTED,
      mode0(3) => NLW_main_mode0_3_UNCONNECTED,
      mode0(2) => NLW_main_mode0_2_UNCONNECTED,
      mode0(1) => NLW_main_mode0_1_UNCONNECTED,
      mode0(0) => NLW_main_mode0_0_UNCONNECTED,
      mode1(15) => NLW_main_mode1_15_UNCONNECTED,
      mode1(14) => NLW_main_mode1_14_UNCONNECTED,
      mode1(13) => NLW_main_mode1_13_UNCONNECTED,
      mode1(12) => NLW_main_mode1_12_UNCONNECTED,
      mode1(11) => NLW_main_mode1_11_UNCONNECTED,
      mode1(10) => NLW_main_mode1_10_UNCONNECTED,
      mode1(9) => NLW_main_mode1_9_UNCONNECTED,
      mode1(8) => NLW_main_mode1_8_UNCONNECTED,
      mode1(7) => NLW_main_mode1_7_UNCONNECTED,
      mode1(6) => NLW_main_mode1_6_UNCONNECTED,
      mode1(5) => NLW_main_mode1_5_UNCONNECTED,
      mode1(4) => NLW_main_mode1_4_UNCONNECTED,
      mode1(3) => NLW_main_mode1_3_UNCONNECTED,
      mode1(2) => NLW_main_mode1_2_UNCONNECTED,
      mode1(1) => NLW_main_mode1_1_UNCONNECTED,
      mode1(0) => NLW_main_mode1_0_UNCONNECTED,
      synx(15) => NLW_main_synx_15_UNCONNECTED,
      synx(14) => NLW_main_synx_14_UNCONNECTED,
      synx(13) => NLW_main_synx_13_UNCONNECTED,
      synx(12) => NLW_main_synx_12_UNCONNECTED,
      synx(11) => NLW_main_synx_11_UNCONNECTED,
      synx(10) => NLW_main_synx_10_UNCONNECTED,
      synx(9) => NLW_main_synx_9_UNCONNECTED,
      synx(8) => NLW_main_synx_8_UNCONNECTED,
      synx(7) => NLW_main_synx_7_UNCONNECTED,
      synx(6) => NLW_main_synx_6_UNCONNECTED,
      synx(5) => NLW_main_synx_5_UNCONNECTED,
      synx(4) => NLW_main_synx_4_UNCONNECTED,
      synx(3) => NLW_main_synx_3_UNCONNECTED,
      synx(2) => NLW_main_synx_2_UNCONNECTED,
      synx(1) => NLW_main_synx_1_UNCONNECTED,
      synx(0) => NLW_main_synx_0_UNCONNECTED,
      cmd_data_out(15) => trd_cmd_data_0_15_Q,
      cmd_data_out(14) => trd_cmd_data_0_14_Q,
      cmd_data_out(13) => trd_cmd_data_0_13_Q,
      cmd_data_out(12) => trd_cmd_data_0_12_Q,
      cmd_data_out(11) => trd_cmd_data_0_11_Q,
      cmd_data_out(10) => trd_cmd_data_0_10_Q,
      cmd_data_out(9) => trd_cmd_data_0_9_Q,
      cmd_data_out(8) => trd_cmd_data_0_8_Q,
      cmd_data_out(7) => trd_cmd_data_0_7_Q,
      cmd_data_out(6) => trd_cmd_data_0_6_Q,
      cmd_data_out(5) => trd_cmd_data_0_5_Q,
      cmd_data_out(4) => trd_cmd_data_0_4_Q,
      cmd_data_out(3) => trd_cmd_data_0_3_Q,
      cmd_data_out(2) => trd_cmd_data_0_2_Q,
      cmd_data_out(1) => trd_cmd_data_0_1_Q,
      cmd_data_out(0) => trd_cmd_data_0_0_Q,
      b_clk(15) => N0,
      b_clk(14) => N0,
      b_clk(13) => N0,
      b_clk(12) => N0,
      b_clk(11) => N0,
      b_clk(10) => N0,
      b_clk(9) => N0,
      b_clk(8) => N0,
      b_clk(7) => N0,
      b_clk(6) => N0,
      b_clk(5) => N0,
      b_clk(4) => N0,
      b_clk(3) => N0,
      b_clk(2) => N0,
      b_clk(1) => N0,
      b_clk(0) => N0,
      data_in(63) => trd_host_data_0_63_Q,
      data_in(62) => trd_host_data_0_62_Q,
      data_in(61) => trd_host_data_0_61_Q,
      data_in(60) => trd_host_data_0_60_Q,
      data_in(59) => trd_host_data_0_59_Q,
      data_in(58) => trd_host_data_0_58_Q,
      data_in(57) => trd_host_data_0_57_Q,
      data_in(56) => trd_host_data_0_56_Q,
      data_in(55) => trd_host_data_0_55_Q,
      data_in(54) => trd_host_data_0_54_Q,
      data_in(53) => trd_host_data_0_53_Q,
      data_in(52) => trd_host_data_0_52_Q,
      data_in(51) => trd_host_data_0_51_Q,
      data_in(50) => trd_host_data_0_50_Q,
      data_in(49) => trd_host_data_0_49_Q,
      data_in(48) => trd_host_data_0_48_Q,
      data_in(47) => trd_host_data_0_47_Q,
      data_in(46) => trd_host_data_0_46_Q,
      data_in(45) => trd_host_data_0_45_Q,
      data_in(44) => trd_host_data_0_44_Q,
      data_in(43) => trd_host_data_0_43_Q,
      data_in(42) => trd_host_data_0_42_Q,
      data_in(41) => trd_host_data_0_41_Q,
      data_in(40) => trd_host_data_0_40_Q,
      data_in(39) => trd_host_data_0_39_Q,
      data_in(38) => trd_host_data_0_38_Q,
      data_in(37) => trd_host_data_0_37_Q,
      data_in(36) => trd_host_data_0_36_Q,
      data_in(35) => trd_host_data_0_35_Q,
      data_in(34) => trd_host_data_0_34_Q,
      data_in(33) => trd_host_data_0_33_Q,
      data_in(32) => trd_host_data_0_32_Q,
      data_in(31) => trd_host_data_0_31_Q,
      data_in(30) => trd_host_data_0_30_Q,
      data_in(29) => trd_host_data_0_29_Q,
      data_in(28) => trd_host_data_0_28_Q,
      data_in(27) => trd_host_data_0_27_Q,
      data_in(26) => trd_host_data_0_26_Q,
      data_in(25) => trd_host_data_0_25_Q,
      data_in(24) => trd_host_data_0_24_Q,
      data_in(23) => trd_host_data_0_23_Q,
      data_in(22) => trd_host_data_0_22_Q,
      data_in(21) => trd_host_data_0_21_Q,
      data_in(20) => trd_host_data_0_20_Q,
      data_in(19) => trd_host_data_0_19_Q,
      data_in(18) => trd_host_data_0_18_Q,
      data_in(17) => trd_host_data_0_17_Q,
      data_in(16) => trd_host_data_0_16_Q,
      data_in(15) => trd_host_data_0_15_Q,
      data_in(14) => trd_host_data_0_14_Q,
      data_in(13) => trd_host_data_0_13_Q,
      data_in(12) => trd_host_data_0_12_Q,
      data_in(11) => trd_host_data_0_11_Q,
      data_in(10) => trd_host_data_0_10_Q,
      data_in(9) => trd_host_data_0_9_Q,
      data_in(8) => trd_host_data_0_8_Q,
      data_in(7) => trd_host_data_0_7_Q,
      data_in(6) => trd_host_data_0_6_Q,
      data_in(5) => trd_host_data_0_5_Q,
      data_in(4) => trd_host_data_0_4_Q,
      data_in(3) => trd_host_data_0_3_Q,
      data_in(2) => trd_host_data_0_2_Q,
      data_in(1) => trd_host_data_0_1_Q,
      data_in(0) => trd_host_data_0_0_Q,
      adr_in(6) => trd_host_adr(6),
      adr_in(5) => trd_host_adr(5),
      adr_in(4) => trd_host_adr(4),
      adr_in(3) => trd_host_adr(3),
      adr_in(2) => trd_host_adr(2),
      adr_in(1) => trd_host_adr(1),
      adr_in(0) => trd_host_adr(0),
      cmd_data_in(15) => trd_host_cmd_data_0_15_Q,
      cmd_data_in(14) => trd_host_cmd_data_0_14_Q,
      cmd_data_in(13) => trd_host_cmd_data_0_13_Q,
      cmd_data_in(12) => trd_host_cmd_data_0_12_Q,
      cmd_data_in(11) => trd_host_cmd_data_0_11_Q,
      cmd_data_in(10) => trd_host_cmd_data_0_10_Q,
      cmd_data_in(9) => trd_host_cmd_data_0_9_Q,
      cmd_data_in(8) => trd_host_cmd_data_0_8_Q,
      cmd_data_in(7) => trd_host_cmd_data_0_7_Q,
      cmd_data_in(6) => trd_host_cmd_data_0_6_Q,
      cmd_data_in(5) => trd_host_cmd_data_0_5_Q,
      cmd_data_in(4) => trd_host_cmd_data_0_4_Q,
      cmd_data_in(3) => trd_host_cmd_data_0_3_Q,
      cmd_data_in(2) => trd_host_cmd_data_0_2_Q,
      cmd_data_in(1) => trd_host_cmd_data_0_1_Q,
      cmd_data_in(0) => trd_host_cmd_data_0_0_Q,
      cmd_adr(9) => trd_host_cmd_0_adr_9_Q,
      cmd_adr(8) => trd_host_cmd_0_adr_8_Q,
      cmd_adr(7) => trd_host_cmd_0_adr_7_Q,
      cmd_adr(6) => trd_host_cmd_0_adr_6_Q,
      cmd_adr(5) => trd_host_cmd_0_adr_5_Q,
      cmd_adr(4) => trd_host_cmd_0_adr_4_Q,
      cmd_adr(3) => trd_host_cmd_0_adr_3_Q,
      cmd_adr(2) => trd_host_cmd_0_adr_2_Q,
      cmd_adr(1) => trd_host_cmd_0_adr_1_Q,
      cmd_adr(0) => trd_host_cmd_0_adr_0_Q,
      b_start(15) => N0,
      b_start(14) => N0,
      b_start(13) => N0,
      b_start(12) => N0,
      b_start(11) => N0,
      b_start(10) => N0,
      b_start(9) => N0,
      b_start(8) => N0,
      b_start(7) => N0,
      b_start(6) => N0,
      b_start(5) => N0,
      b_start(4) => N0,
      b_start(3) => N0,
      b_start(2) => N0,
      b_start(1) => N0,
      b_start(0) => N0
    );
  test_ctrl : trd_test_ctrl_m1
    port map (
      di_clk => di_clk,
      di_data_we => di_data_we,
      do_start => do_start,
      do_fifo_rst => do_fifo_rst,
      clk => clk,
      do_flag_rd_und => do_flag_rd_und,
      di_fifo_rst => di_fifo_rst,
      do_flag_rd_pae => do_flag_rd_pae,
      do_flag_rd_paf => do_flag_rd_paf,
      bx_irq => trd_irq_1_Q,
      clk_check0 => clk,
      clk_check1 => N0,
      clk_check2 => N0,
      reset => reset,
      cmd_cmd_data_we => trd_host_cmd_1_cmd_data_we,
      di_start => di_start,
      do_data_cs => do_data_cs,
      cmd_status_cs => trd_host_cmd_1_status_cs,
      do_clk => do_clk,
      di_flag_wr_ovr => di_flag_wr_ovr,
      do_flag_rd_ef => do_flag_rd_ef,
      di_flag_wr_ef => di_flag_wr_ef,
      cmd_data_cs => trd_host_cmd_1_data_cs,
      do_flag_rd_ff => do_flag_rd_ff,
      di_flag_wr_ff => di_flag_wr_ff,
      do_flag_rd_hf => do_flag_rd_hf,
      di_flag_wr_hf => di_flag_wr_hf,
      do_flag_rd_ovr => do_flag_rd_ovr,
      bx_drq_en => trd_drq_1_en,
      clk_sys => clk200,
      bx_drq_ack => trd_drq_1_ack,
      cmd_data_oe => trd_host_cmd_1_data_oe,
      cmd_cmd_data_cs => trd_host_cmd_1_cmd_data_cs,
      cmd_cmd_adr_we => trd_host_cmd_1_cmd_adr_we,
      di_flag_wr_und => di_flag_wr_und,
      cmd_data_we => trd_host_cmd_1_data_we,
      bx_drq_req => trd_drq_1_req,
      di_flag_wr_pae => di_flag_wr_pae,
      di_flag_wr_paf => di_flag_wr_paf,
      cmd_data_out2(15) => trd_cmd_data_1_15_Q,
      cmd_data_out2(14) => trd_cmd_data_1_14_Q,
      cmd_data_out2(13) => trd_cmd_data_1_13_Q,
      cmd_data_out2(12) => trd_cmd_data_1_12_Q,
      cmd_data_out2(11) => trd_cmd_data_1_11_Q,
      cmd_data_out2(10) => trd_cmd_data_1_10_Q,
      cmd_data_out2(9) => trd_cmd_data_1_9_Q,
      cmd_data_out2(8) => trd_cmd_data_1_8_Q,
      cmd_data_out2(7) => trd_cmd_data_1_7_Q,
      cmd_data_out2(6) => trd_cmd_data_1_6_Q,
      cmd_data_out2(5) => trd_cmd_data_1_5_Q,
      cmd_data_out2(4) => trd_cmd_data_1_4_Q,
      cmd_data_out2(3) => trd_cmd_data_1_3_Q,
      cmd_data_out2(2) => trd_cmd_data_1_2_Q,
      cmd_data_out2(1) => trd_cmd_data_1_1_Q,
      cmd_data_out2(0) => trd_cmd_data_1_0_Q,
      mode0(15) => NLW_test_ctrl_mode0_15_UNCONNECTED,
      mode0(14) => NLW_test_ctrl_mode0_14_UNCONNECTED,
      mode0(13) => NLW_test_ctrl_mode0_13_UNCONNECTED,
      mode0(12) => NLW_test_ctrl_mode0_12_UNCONNECTED,
      mode0(11) => NLW_test_ctrl_mode0_11_UNCONNECTED,
      mode0(10) => NLW_test_ctrl_mode0_10_UNCONNECTED,
      mode0(9) => NLW_test_ctrl_mode0_9_UNCONNECTED,
      mode0(8) => NLW_test_ctrl_mode0_8_UNCONNECTED,
      mode0(7) => NLW_test_ctrl_mode0_7_UNCONNECTED,
      mode0(6) => NLW_test_ctrl_mode0_6_UNCONNECTED,
      mode0(5) => NLW_test_ctrl_mode0_5_UNCONNECTED,
      mode0(4) => NLW_test_ctrl_mode0_4_UNCONNECTED,
      mode0(3) => NLW_test_ctrl_mode0_3_UNCONNECTED,
      mode0(2) => NLW_test_ctrl_mode0_2_UNCONNECTED,
      mode0(1) => NLW_test_ctrl_mode0_1_UNCONNECTED,
      mode0(0) => NLW_test_ctrl_mode0_0_UNCONNECTED,
      mode1(15) => NLW_test_ctrl_mode1_15_UNCONNECTED,
      mode1(14) => NLW_test_ctrl_mode1_14_UNCONNECTED,
      mode1(13) => NLW_test_ctrl_mode1_13_UNCONNECTED,
      mode1(12) => NLW_test_ctrl_mode1_12_UNCONNECTED,
      mode1(11) => NLW_test_ctrl_mode1_11_UNCONNECTED,
      mode1(10) => NLW_test_ctrl_mode1_10_UNCONNECTED,
      mode1(9) => NLW_test_ctrl_mode1_9_UNCONNECTED,
      mode1(8) => NLW_test_ctrl_mode1_8_UNCONNECTED,
      mode1(7) => NLW_test_ctrl_mode1_7_UNCONNECTED,
      mode1(6) => NLW_test_ctrl_mode1_6_UNCONNECTED,
      mode1(5) => NLW_test_ctrl_mode1_5_UNCONNECTED,
      mode1(4) => NLW_test_ctrl_mode1_4_UNCONNECTED,
      mode1(3) => NLW_test_ctrl_mode1_3_UNCONNECTED,
      mode1(2) => NLW_test_ctrl_mode1_2_UNCONNECTED,
      mode1(1) => NLW_test_ctrl_mode1_1_UNCONNECTED,
      mode1(0) => NLW_test_ctrl_mode1_0_UNCONNECTED,
      mode2(15) => NLW_test_ctrl_mode2_15_UNCONNECTED,
      mode2(14) => NLW_test_ctrl_mode2_14_UNCONNECTED,
      mode2(13) => NLW_test_ctrl_mode2_13_UNCONNECTED,
      mode2(12) => NLW_test_ctrl_mode2_12_UNCONNECTED,
      mode2(11) => NLW_test_ctrl_mode2_11_UNCONNECTED,
      mode2(10) => NLW_test_ctrl_mode2_10_UNCONNECTED,
      mode2(9) => NLW_test_ctrl_mode2_9_UNCONNECTED,
      mode2(8) => NLW_test_ctrl_mode2_8_UNCONNECTED,
      mode2(7) => NLW_test_ctrl_mode2_7_UNCONNECTED,
      mode2(6) => NLW_test_ctrl_mode2_6_UNCONNECTED,
      mode2(5) => NLW_test_ctrl_mode2_5_UNCONNECTED,
      mode2(4) => NLW_test_ctrl_mode2_4_UNCONNECTED,
      mode2(3) => NLW_test_ctrl_mode2_3_UNCONNECTED,
      mode2(2) => NLW_test_ctrl_mode2_2_UNCONNECTED,
      mode2(1) => NLW_test_ctrl_mode2_1_UNCONNECTED,
      mode2(0) => NLW_test_ctrl_mode2_0_UNCONNECTED,
      mode3(15) => NLW_test_ctrl_mode3_15_UNCONNECTED,
      mode3(14) => NLW_test_ctrl_mode3_14_UNCONNECTED,
      mode3(13) => NLW_test_ctrl_mode3_13_UNCONNECTED,
      mode3(12) => NLW_test_ctrl_mode3_12_UNCONNECTED,
      mode3(11) => NLW_test_ctrl_mode3_11_UNCONNECTED,
      mode3(10) => NLW_test_ctrl_mode3_10_UNCONNECTED,
      mode3(9) => NLW_test_ctrl_mode3_9_UNCONNECTED,
      mode3(8) => NLW_test_ctrl_mode3_8_UNCONNECTED,
      mode3(7) => NLW_test_ctrl_mode3_7_UNCONNECTED,
      mode3(6) => NLW_test_ctrl_mode3_6_UNCONNECTED,
      mode3(5) => NLW_test_ctrl_mode3_5_UNCONNECTED,
      mode3(4) => NLW_test_ctrl_mode3_4_UNCONNECTED,
      mode3(3) => NLW_test_ctrl_mode3_3_UNCONNECTED,
      mode3(2) => NLW_test_ctrl_mode3_2_UNCONNECTED,
      mode3(1) => NLW_test_ctrl_mode3_1_UNCONNECTED,
      mode3(0) => NLW_test_ctrl_mode3_0_UNCONNECTED,
      di_data(63) => di_data(63),
      di_data(62) => di_data(62),
      di_data(61) => di_data(61),
      di_data(60) => di_data(60),
      di_data(59) => di_data(59),
      di_data(58) => di_data(58),
      di_data(57) => di_data(57),
      di_data(56) => di_data(56),
      di_data(55) => di_data(55),
      di_data(54) => di_data(54),
      di_data(53) => di_data(53),
      di_data(52) => di_data(52),
      di_data(51) => di_data(51),
      di_data(50) => di_data(50),
      di_data(49) => di_data(49),
      di_data(48) => di_data(48),
      di_data(47) => di_data(47),
      di_data(46) => di_data(46),
      di_data(45) => di_data(45),
      di_data(44) => di_data(44),
      di_data(43) => di_data(43),
      di_data(42) => di_data(42),
      di_data(41) => di_data(41),
      di_data(40) => di_data(40),
      di_data(39) => di_data(39),
      di_data(38) => di_data(38),
      di_data(37) => di_data(37),
      di_data(36) => di_data(36),
      di_data(35) => di_data(35),
      di_data(34) => di_data(34),
      di_data(33) => di_data(33),
      di_data(32) => di_data(32),
      di_data(31) => di_data(31),
      di_data(30) => di_data(30),
      di_data(29) => di_data(29),
      di_data(28) => di_data(28),
      di_data(27) => di_data(27),
      di_data(26) => di_data(26),
      di_data(25) => di_data(25),
      di_data(24) => di_data(24),
      di_data(23) => di_data(23),
      di_data(22) => di_data(22),
      di_data(21) => di_data(21),
      di_data(20) => di_data(20),
      di_data(19) => di_data(19),
      di_data(18) => di_data(18),
      di_data(17) => di_data(17),
      di_data(16) => di_data(16),
      di_data(15) => di_data(15),
      di_data(14) => di_data(14),
      di_data(13) => di_data(13),
      di_data(12) => di_data(12),
      di_data(11) => di_data(11),
      di_data(10) => di_data(10),
      di_data(9) => di_data(9),
      di_data(8) => di_data(8),
      di_data(7) => di_data(7),
      di_data(6) => di_data(6),
      di_data(5) => di_data(5),
      di_data(4) => di_data(4),
      di_data(3) => di_data(3),
      di_data(2) => di_data(2),
      di_data(1) => di_data(1),
      di_data(0) => di_data(0),
      cmd_data_out(15) => NLW_test_ctrl_cmd_data_out_15_UNCONNECTED,
      cmd_data_out(14) => NLW_test_ctrl_cmd_data_out_14_UNCONNECTED,
      cmd_data_out(13) => NLW_test_ctrl_cmd_data_out_13_UNCONNECTED,
      cmd_data_out(12) => NLW_test_ctrl_cmd_data_out_12_UNCONNECTED,
      cmd_data_out(11) => NLW_test_ctrl_cmd_data_out_11_UNCONNECTED,
      cmd_data_out(10) => NLW_test_ctrl_cmd_data_out_10_UNCONNECTED,
      cmd_data_out(9) => NLW_test_ctrl_cmd_data_out_9_UNCONNECTED,
      cmd_data_out(8) => NLW_test_ctrl_cmd_data_out_8_UNCONNECTED,
      cmd_data_out(7) => NLW_test_ctrl_cmd_data_out_7_UNCONNECTED,
      cmd_data_out(6) => NLW_test_ctrl_cmd_data_out_6_UNCONNECTED,
      cmd_data_out(5) => NLW_test_ctrl_cmd_data_out_5_UNCONNECTED,
      cmd_data_out(4) => NLW_test_ctrl_cmd_data_out_4_UNCONNECTED,
      cmd_data_out(3) => NLW_test_ctrl_cmd_data_out_3_UNCONNECTED,
      cmd_data_out(2) => NLW_test_ctrl_cmd_data_out_2_UNCONNECTED,
      cmd_data_out(1) => NLW_test_ctrl_cmd_data_out_1_UNCONNECTED,
      cmd_data_out(0) => NLW_test_ctrl_cmd_data_out_0_UNCONNECTED,
      do_mode1(15) => do_mode1(15),
      do_mode1(14) => do_mode1(14),
      do_mode1(13) => do_mode1(13),
      do_mode1(12) => do_mode1(12),
      do_mode1(11) => do_mode1(11),
      do_mode1(10) => do_mode1(10),
      do_mode1(9) => do_mode1(9),
      do_mode1(8) => do_mode1(8),
      do_mode1(7) => do_mode1(7),
      do_mode1(6) => do_mode1(6),
      do_mode1(5) => do_mode1(5),
      do_mode1(4) => do_mode1(4),
      do_mode1(3) => do_mode1(3),
      do_mode1(2) => do_mode1(2),
      do_mode1(1) => do_mode1(1),
      do_mode1(0) => do_mode1(0),
      di_mode1(15) => di_mode1(15),
      di_mode1(14) => di_mode1(14),
      di_mode1(13) => di_mode1(13),
      di_mode1(12) => di_mode1(12),
      di_mode1(11) => di_mode1(11),
      di_mode1(10) => di_mode1(10),
      di_mode1(9) => di_mode1(9),
      di_mode1(8) => di_mode1(8),
      di_mode1(7) => di_mode1(7),
      di_mode1(6) => di_mode1(6),
      di_mode1(5) => di_mode1(5),
      di_mode1(4) => di_mode1(4),
      di_mode1(3) => di_mode1(3),
      di_mode1(2) => di_mode1(2),
      di_mode1(1) => di_mode1(1),
      di_mode1(0) => di_mode1(0),
      cmd_data_in(15) => trd_host_cmd_data_1_15_Q,
      cmd_data_in(14) => trd_host_cmd_data_1_14_Q,
      cmd_data_in(13) => trd_host_cmd_data_1_13_Q,
      cmd_data_in(12) => trd_host_cmd_data_1_12_Q,
      cmd_data_in(11) => trd_host_cmd_data_1_11_Q,
      cmd_data_in(10) => trd_host_cmd_data_1_10_Q,
      cmd_data_in(9) => trd_host_cmd_data_1_9_Q,
      cmd_data_in(8) => trd_host_cmd_data_1_8_Q,
      cmd_data_in(7) => trd_host_cmd_data_1_7_Q,
      cmd_data_in(6) => trd_host_cmd_data_1_6_Q,
      cmd_data_in(5) => trd_host_cmd_data_1_5_Q,
      cmd_data_in(4) => trd_host_cmd_data_1_4_Q,
      cmd_data_in(3) => trd_host_cmd_data_1_3_Q,
      cmd_data_in(2) => trd_host_cmd_data_1_2_Q,
      cmd_data_in(1) => trd_host_cmd_data_1_1_Q,
      cmd_data_in(0) => trd_host_cmd_data_1_0_Q,
      cmd_adr(9) => trd_host_cmd_1_adr_9_Q,
      cmd_adr(8) => trd_host_cmd_1_adr_8_Q,
      cmd_adr(7) => trd_host_cmd_1_adr_7_Q,
      cmd_adr(6) => trd_host_cmd_1_adr_6_Q,
      cmd_adr(5) => trd_host_cmd_1_adr_5_Q,
      cmd_adr(4) => trd_host_cmd_1_adr_4_Q,
      cmd_adr(3) => trd_host_cmd_1_adr_3_Q,
      cmd_adr(2) => trd_host_cmd_1_adr_2_Q,
      cmd_adr(1) => trd_host_cmd_1_adr_1_Q,
      cmd_adr(0) => trd_host_cmd_1_adr_0_Q,
      do_data(63) => do_data(63),
      do_data(62) => do_data(62),
      do_data(61) => do_data(61),
      do_data(60) => do_data(60),
      do_data(59) => do_data(59),
      do_data(58) => do_data(58),
      do_data(57) => do_data(57),
      do_data(56) => do_data(56),
      do_data(55) => do_data(55),
      do_data(54) => do_data(54),
      do_data(53) => do_data(53),
      do_data(52) => do_data(52),
      do_data(51) => do_data(51),
      do_data(50) => do_data(50),
      do_data(49) => do_data(49),
      do_data(48) => do_data(48),
      do_data(47) => do_data(47),
      do_data(46) => do_data(46),
      do_data(45) => do_data(45),
      do_data(44) => do_data(44),
      do_data(43) => do_data(43),
      do_data(42) => do_data(42),
      do_data(41) => do_data(41),
      do_data(40) => do_data(40),
      do_data(39) => do_data(39),
      do_data(38) => do_data(38),
      do_data(37) => do_data(37),
      do_data(36) => do_data(36),
      do_data(35) => do_data(35),
      do_data(34) => do_data(34),
      do_data(33) => do_data(33),
      do_data(32) => do_data(32),
      do_data(31) => do_data(31),
      do_data(30) => do_data(30),
      do_data(29) => do_data(29),
      do_data(28) => do_data(28),
      do_data(27) => do_data(27),
      do_data(26) => do_data(26),
      do_data(25) => do_data(25),
      do_data(24) => do_data(24),
      do_data(23) => do_data(23),
      do_data(22) => do_data(22),
      do_data(21) => do_data(21),
      do_data(20) => do_data(20),
      do_data(19) => do_data(19),
      do_data(18) => do_data(18),
      do_data(17) => do_data(17),
      do_data(16) => do_data(16),
      do_data(15) => do_data(15),
      do_data(14) => do_data(14),
      do_data(13) => do_data(13),
      do_data(12) => do_data(12),
      do_data(11) => do_data(11),
      do_data(10) => do_data(10),
      do_data(9) => do_data(9),
      do_data(8) => do_data(8),
      do_data(7) => do_data(7),
      do_data(6) => do_data(6),
      do_data(5) => do_data(5),
      do_data(4) => do_data(4),
      do_data(3) => do_data(3),
      do_data(2) => do_data(2),
      do_data(1) => do_data(1),
      do_data(0) => do_data(0)
    );
  dio_in : trd_admdio64_in_v6
    port map (
      clk => clk,
      flag_rd_ef => NLW_dio_in_flag_rd_ef_UNCONNECTED,
      flag_rd_ff => NLW_dio_in_flag_rd_ff_UNCONNECTED,
      flag_rd_hf => NLW_dio_in_flag_rd_hf_UNCONNECTED,
      flag_wr_und => di_flag_wr_und,
      bx_irq => trd_irq_6_Q,
      flag_wr_pae => di_flag_wr_pae,
      flag_wr_paf => di_flag_wr_paf,
      start => di_start,
      reset => reset,
      cmd_cmd_data_we => trd_host_cmd_6_cmd_data_we,
      flag_wr_ef => di_flag_wr_ef,
      flag_wr_ff => di_flag_wr_ff,
      flag_rd_ovr => NLW_dio_in_flag_rd_ovr_UNCONNECTED,
      cmd_status_cs => trd_host_cmd_6_status_cs,
      flag_wr_hf => di_flag_wr_hf,
      fifo_rst => di_fifo_rst,
      cmd_data_cs => trd_host_cmd_6_data_cs,
      clk_wr => di_clk,
      bx_drq_en => trd_drq_6_en,
      flag_wr_ovr => di_flag_wr_ovr,
      bx_drq_ack => trd_drq_6_ack,
      data_wr => di_data_we,
      cmd_data_oe => trd_host_cmd_6_data_oe,
      cmd_cmd_data_cs => trd_host_cmd_6_cmd_data_cs,
      flag_rd_und => NLW_dio_in_flag_rd_und_UNCONNECTED,
      flag_rd_pae => NLW_dio_in_flag_rd_pae_UNCONNECTED,
      flag_rd_paf => NLW_dio_in_flag_rd_paf_UNCONNECTED,
      cmd_cmd_adr_we => trd_host_cmd_6_cmd_adr_we,
      fifo_rst_in => N1,
      cmd_data_we => trd_host_cmd_6_data_we,
      bx_drq_req => trd_drq_6_req,
      fifo_cnt_rd(9) => NLW_dio_in_fifo_cnt_rd_9_UNCONNECTED,
      fifo_cnt_rd(8) => NLW_dio_in_fifo_cnt_rd_8_UNCONNECTED,
      fifo_cnt_rd(7) => NLW_dio_in_fifo_cnt_rd_7_UNCONNECTED,
      fifo_cnt_rd(6) => NLW_dio_in_fifo_cnt_rd_6_UNCONNECTED,
      fifo_cnt_rd(5) => NLW_dio_in_fifo_cnt_rd_5_UNCONNECTED,
      fifo_cnt_rd(4) => NLW_dio_in_fifo_cnt_rd_4_UNCONNECTED,
      fifo_cnt_rd(3) => NLW_dio_in_fifo_cnt_rd_3_UNCONNECTED,
      fifo_cnt_rd(2) => NLW_dio_in_fifo_cnt_rd_2_UNCONNECTED,
      fifo_cnt_rd(1) => NLW_dio_in_fifo_cnt_rd_1_UNCONNECTED,
      fifo_cnt_rd(0) => NLW_dio_in_fifo_cnt_rd_0_UNCONNECTED,
      data_out(63) => NLW_dio_in_data_out_63_UNCONNECTED,
      data_out(62) => NLW_dio_in_data_out_62_UNCONNECTED,
      data_out(61) => NLW_dio_in_data_out_61_UNCONNECTED,
      data_out(60) => NLW_dio_in_data_out_60_UNCONNECTED,
      data_out(59) => NLW_dio_in_data_out_59_UNCONNECTED,
      data_out(58) => NLW_dio_in_data_out_58_UNCONNECTED,
      data_out(57) => NLW_dio_in_data_out_57_UNCONNECTED,
      data_out(56) => NLW_dio_in_data_out_56_UNCONNECTED,
      data_out(55) => NLW_dio_in_data_out_55_UNCONNECTED,
      data_out(54) => NLW_dio_in_data_out_54_UNCONNECTED,
      data_out(53) => NLW_dio_in_data_out_53_UNCONNECTED,
      data_out(52) => NLW_dio_in_data_out_52_UNCONNECTED,
      data_out(51) => NLW_dio_in_data_out_51_UNCONNECTED,
      data_out(50) => NLW_dio_in_data_out_50_UNCONNECTED,
      data_out(49) => NLW_dio_in_data_out_49_UNCONNECTED,
      data_out(48) => NLW_dio_in_data_out_48_UNCONNECTED,
      data_out(47) => NLW_dio_in_data_out_47_UNCONNECTED,
      data_out(46) => NLW_dio_in_data_out_46_UNCONNECTED,
      data_out(45) => NLW_dio_in_data_out_45_UNCONNECTED,
      data_out(44) => NLW_dio_in_data_out_44_UNCONNECTED,
      data_out(43) => NLW_dio_in_data_out_43_UNCONNECTED,
      data_out(42) => NLW_dio_in_data_out_42_UNCONNECTED,
      data_out(41) => NLW_dio_in_data_out_41_UNCONNECTED,
      data_out(40) => NLW_dio_in_data_out_40_UNCONNECTED,
      data_out(39) => NLW_dio_in_data_out_39_UNCONNECTED,
      data_out(38) => NLW_dio_in_data_out_38_UNCONNECTED,
      data_out(37) => NLW_dio_in_data_out_37_UNCONNECTED,
      data_out(36) => NLW_dio_in_data_out_36_UNCONNECTED,
      data_out(35) => NLW_dio_in_data_out_35_UNCONNECTED,
      data_out(34) => NLW_dio_in_data_out_34_UNCONNECTED,
      data_out(33) => NLW_dio_in_data_out_33_UNCONNECTED,
      data_out(32) => NLW_dio_in_data_out_32_UNCONNECTED,
      data_out(31) => NLW_dio_in_data_out_31_UNCONNECTED,
      data_out(30) => NLW_dio_in_data_out_30_UNCONNECTED,
      data_out(29) => NLW_dio_in_data_out_29_UNCONNECTED,
      data_out(28) => NLW_dio_in_data_out_28_UNCONNECTED,
      data_out(27) => NLW_dio_in_data_out_27_UNCONNECTED,
      data_out(26) => NLW_dio_in_data_out_26_UNCONNECTED,
      data_out(25) => NLW_dio_in_data_out_25_UNCONNECTED,
      data_out(24) => NLW_dio_in_data_out_24_UNCONNECTED,
      data_out(23) => NLW_dio_in_data_out_23_UNCONNECTED,
      data_out(22) => NLW_dio_in_data_out_22_UNCONNECTED,
      data_out(21) => NLW_dio_in_data_out_21_UNCONNECTED,
      data_out(20) => NLW_dio_in_data_out_20_UNCONNECTED,
      data_out(19) => NLW_dio_in_data_out_19_UNCONNECTED,
      data_out(18) => NLW_dio_in_data_out_18_UNCONNECTED,
      data_out(17) => NLW_dio_in_data_out_17_UNCONNECTED,
      data_out(16) => NLW_dio_in_data_out_16_UNCONNECTED,
      data_out(15) => NLW_dio_in_data_out_15_UNCONNECTED,
      data_out(14) => NLW_dio_in_data_out_14_UNCONNECTED,
      data_out(13) => NLW_dio_in_data_out_13_UNCONNECTED,
      data_out(12) => NLW_dio_in_data_out_12_UNCONNECTED,
      data_out(11) => NLW_dio_in_data_out_11_UNCONNECTED,
      data_out(10) => NLW_dio_in_data_out_10_UNCONNECTED,
      data_out(9) => NLW_dio_in_data_out_9_UNCONNECTED,
      data_out(8) => NLW_dio_in_data_out_8_UNCONNECTED,
      data_out(7) => NLW_dio_in_data_out_7_UNCONNECTED,
      data_out(6) => NLW_dio_in_data_out_6_UNCONNECTED,
      data_out(5) => NLW_dio_in_data_out_5_UNCONNECTED,
      data_out(4) => NLW_dio_in_data_out_4_UNCONNECTED,
      data_out(3) => NLW_dio_in_data_out_3_UNCONNECTED,
      data_out(2) => NLW_dio_in_data_out_2_UNCONNECTED,
      data_out(1) => NLW_dio_in_data_out_1_UNCONNECTED,
      data_out(0) => NLW_dio_in_data_out_0_UNCONNECTED,
      fifo_cnt_wr(9) => NLW_dio_in_fifo_cnt_wr_9_UNCONNECTED,
      fifo_cnt_wr(8) => NLW_dio_in_fifo_cnt_wr_8_UNCONNECTED,
      fifo_cnt_wr(7) => NLW_dio_in_fifo_cnt_wr_7_UNCONNECTED,
      fifo_cnt_wr(6) => NLW_dio_in_fifo_cnt_wr_6_UNCONNECTED,
      fifo_cnt_wr(5) => NLW_dio_in_fifo_cnt_wr_5_UNCONNECTED,
      fifo_cnt_wr(4) => NLW_dio_in_fifo_cnt_wr_4_UNCONNECTED,
      fifo_cnt_wr(3) => NLW_dio_in_fifo_cnt_wr_3_UNCONNECTED,
      fifo_cnt_wr(2) => NLW_dio_in_fifo_cnt_wr_2_UNCONNECTED,
      fifo_cnt_wr(1) => NLW_dio_in_fifo_cnt_wr_1_UNCONNECTED,
      fifo_cnt_wr(0) => NLW_dio_in_fifo_cnt_wr_0_UNCONNECTED,
      data_out2(63) => trd_data_6_63_Q,
      data_out2(62) => trd_data_6_62_Q,
      data_out2(61) => trd_data_6_61_Q,
      data_out2(60) => trd_data_6_60_Q,
      data_out2(59) => trd_data_6_59_Q,
      data_out2(58) => trd_data_6_58_Q,
      data_out2(57) => trd_data_6_57_Q,
      data_out2(56) => trd_data_6_56_Q,
      data_out2(55) => trd_data_6_55_Q,
      data_out2(54) => trd_data_6_54_Q,
      data_out2(53) => trd_data_6_53_Q,
      data_out2(52) => trd_data_6_52_Q,
      data_out2(51) => trd_data_6_51_Q,
      data_out2(50) => trd_data_6_50_Q,
      data_out2(49) => trd_data_6_49_Q,
      data_out2(48) => trd_data_6_48_Q,
      data_out2(47) => trd_data_6_47_Q,
      data_out2(46) => trd_data_6_46_Q,
      data_out2(45) => trd_data_6_45_Q,
      data_out2(44) => trd_data_6_44_Q,
      data_out2(43) => trd_data_6_43_Q,
      data_out2(42) => trd_data_6_42_Q,
      data_out2(41) => trd_data_6_41_Q,
      data_out2(40) => trd_data_6_40_Q,
      data_out2(39) => trd_data_6_39_Q,
      data_out2(38) => trd_data_6_38_Q,
      data_out2(37) => trd_data_6_37_Q,
      data_out2(36) => trd_data_6_36_Q,
      data_out2(35) => trd_data_6_35_Q,
      data_out2(34) => trd_data_6_34_Q,
      data_out2(33) => trd_data_6_33_Q,
      data_out2(32) => trd_data_6_32_Q,
      data_out2(31) => trd_data_6_31_Q,
      data_out2(30) => trd_data_6_30_Q,
      data_out2(29) => trd_data_6_29_Q,
      data_out2(28) => trd_data_6_28_Q,
      data_out2(27) => trd_data_6_27_Q,
      data_out2(26) => trd_data_6_26_Q,
      data_out2(25) => trd_data_6_25_Q,
      data_out2(24) => trd_data_6_24_Q,
      data_out2(23) => trd_data_6_23_Q,
      data_out2(22) => trd_data_6_22_Q,
      data_out2(21) => trd_data_6_21_Q,
      data_out2(20) => trd_data_6_20_Q,
      data_out2(19) => trd_data_6_19_Q,
      data_out2(18) => trd_data_6_18_Q,
      data_out2(17) => trd_data_6_17_Q,
      data_out2(16) => trd_data_6_16_Q,
      data_out2(15) => trd_data_6_15_Q,
      data_out2(14) => trd_data_6_14_Q,
      data_out2(13) => trd_data_6_13_Q,
      data_out2(12) => trd_data_6_12_Q,
      data_out2(11) => trd_data_6_11_Q,
      data_out2(10) => trd_data_6_10_Q,
      data_out2(9) => trd_data_6_9_Q,
      data_out2(8) => trd_data_6_8_Q,
      data_out2(7) => trd_data_6_7_Q,
      data_out2(6) => trd_data_6_6_Q,
      data_out2(5) => trd_data_6_5_Q,
      data_out2(4) => trd_data_6_4_Q,
      data_out2(3) => trd_data_6_3_Q,
      data_out2(2) => trd_data_6_2_Q,
      data_out2(1) => trd_data_6_1_Q,
      data_out2(0) => trd_data_6_0_Q,
      cmd_data_out2(15) => trd_cmd_data_6_15_Q,
      cmd_data_out2(14) => trd_cmd_data_6_14_Q,
      cmd_data_out2(13) => trd_cmd_data_6_13_Q,
      cmd_data_out2(12) => trd_cmd_data_6_12_Q,
      cmd_data_out2(11) => trd_cmd_data_6_11_Q,
      cmd_data_out2(10) => trd_cmd_data_6_10_Q,
      cmd_data_out2(9) => trd_cmd_data_6_9_Q,
      cmd_data_out2(8) => trd_cmd_data_6_8_Q,
      cmd_data_out2(7) => trd_cmd_data_6_7_Q,
      cmd_data_out2(6) => trd_cmd_data_6_6_Q,
      cmd_data_out2(5) => trd_cmd_data_6_5_Q,
      cmd_data_out2(4) => trd_cmd_data_6_4_Q,
      cmd_data_out2(3) => trd_cmd_data_6_3_Q,
      cmd_data_out2(2) => trd_cmd_data_6_2_Q,
      cmd_data_out2(1) => trd_cmd_data_6_1_Q,
      cmd_data_out2(0) => trd_cmd_data_6_0_Q,
      mode0(15) => NLW_dio_in_mode0_15_UNCONNECTED,
      mode0(14) => NLW_dio_in_mode0_14_UNCONNECTED,
      mode0(13) => NLW_dio_in_mode0_13_UNCONNECTED,
      mode0(12) => NLW_dio_in_mode0_12_UNCONNECTED,
      mode0(11) => NLW_dio_in_mode0_11_UNCONNECTED,
      mode0(10) => NLW_dio_in_mode0_10_UNCONNECTED,
      mode0(9) => NLW_dio_in_mode0_9_UNCONNECTED,
      mode0(8) => NLW_dio_in_mode0_8_UNCONNECTED,
      mode0(7) => NLW_dio_in_mode0_7_UNCONNECTED,
      mode0(6) => NLW_dio_in_mode0_6_UNCONNECTED,
      mode0(5) => NLW_dio_in_mode0_5_UNCONNECTED,
      mode0(4) => NLW_dio_in_mode0_4_UNCONNECTED,
      mode0(3) => NLW_dio_in_mode0_3_UNCONNECTED,
      mode0(2) => NLW_dio_in_mode0_2_UNCONNECTED,
      mode0(1) => NLW_dio_in_mode0_1_UNCONNECTED,
      mode0(0) => NLW_dio_in_mode0_0_UNCONNECTED,
      mode1(15) => di_mode1(15),
      mode1(14) => di_mode1(14),
      mode1(13) => di_mode1(13),
      mode1(12) => di_mode1(12),
      mode1(11) => di_mode1(11),
      mode1(10) => di_mode1(10),
      mode1(9) => di_mode1(9),
      mode1(8) => di_mode1(8),
      mode1(7) => di_mode1(7),
      mode1(6) => di_mode1(6),
      mode1(5) => di_mode1(5),
      mode1(4) => di_mode1(4),
      mode1(3) => di_mode1(3),
      mode1(2) => di_mode1(2),
      mode1(1) => di_mode1(1),
      mode1(0) => di_mode1(0),
      mode2(15) => NLW_dio_in_mode2_15_UNCONNECTED,
      mode2(14) => NLW_dio_in_mode2_14_UNCONNECTED,
      mode2(13) => NLW_dio_in_mode2_13_UNCONNECTED,
      mode2(12) => NLW_dio_in_mode2_12_UNCONNECTED,
      mode2(11) => NLW_dio_in_mode2_11_UNCONNECTED,
      mode2(10) => NLW_dio_in_mode2_10_UNCONNECTED,
      mode2(9) => NLW_dio_in_mode2_9_UNCONNECTED,
      mode2(8) => NLW_dio_in_mode2_8_UNCONNECTED,
      mode2(7) => NLW_dio_in_mode2_7_UNCONNECTED,
      mode2(6) => NLW_dio_in_mode2_6_UNCONNECTED,
      mode2(5) => NLW_dio_in_mode2_5_UNCONNECTED,
      mode2(4) => NLW_dio_in_mode2_4_UNCONNECTED,
      mode2(3) => NLW_dio_in_mode2_3_UNCONNECTED,
      mode2(2) => NLW_dio_in_mode2_2_UNCONNECTED,
      mode2(1) => NLW_dio_in_mode2_1_UNCONNECTED,
      mode2(0) => NLW_dio_in_mode2_0_UNCONNECTED,
      mode3(15) => NLW_dio_in_mode3_15_UNCONNECTED,
      mode3(14) => NLW_dio_in_mode3_14_UNCONNECTED,
      mode3(13) => NLW_dio_in_mode3_13_UNCONNECTED,
      mode3(12) => NLW_dio_in_mode3_12_UNCONNECTED,
      mode3(11) => NLW_dio_in_mode3_11_UNCONNECTED,
      mode3(10) => NLW_dio_in_mode3_10_UNCONNECTED,
      mode3(9) => NLW_dio_in_mode3_9_UNCONNECTED,
      mode3(8) => NLW_dio_in_mode3_8_UNCONNECTED,
      mode3(7) => NLW_dio_in_mode3_7_UNCONNECTED,
      mode3(6) => NLW_dio_in_mode3_6_UNCONNECTED,
      mode3(5) => NLW_dio_in_mode3_5_UNCONNECTED,
      mode3(4) => NLW_dio_in_mode3_4_UNCONNECTED,
      mode3(3) => NLW_dio_in_mode3_3_UNCONNECTED,
      mode3(2) => NLW_dio_in_mode3_2_UNCONNECTED,
      mode3(1) => NLW_dio_in_mode3_1_UNCONNECTED,
      mode3(0) => NLW_dio_in_mode3_0_UNCONNECTED,
      cmd_data_out(15) => NLW_dio_in_cmd_data_out_15_UNCONNECTED,
      cmd_data_out(14) => NLW_dio_in_cmd_data_out_14_UNCONNECTED,
      cmd_data_out(13) => NLW_dio_in_cmd_data_out_13_UNCONNECTED,
      cmd_data_out(12) => NLW_dio_in_cmd_data_out_12_UNCONNECTED,
      cmd_data_out(11) => NLW_dio_in_cmd_data_out_11_UNCONNECTED,
      cmd_data_out(10) => NLW_dio_in_cmd_data_out_10_UNCONNECTED,
      cmd_data_out(9) => NLW_dio_in_cmd_data_out_9_UNCONNECTED,
      cmd_data_out(8) => NLW_dio_in_cmd_data_out_8_UNCONNECTED,
      cmd_data_out(7) => NLW_dio_in_cmd_data_out_7_UNCONNECTED,
      cmd_data_out(6) => NLW_dio_in_cmd_data_out_6_UNCONNECTED,
      cmd_data_out(5) => NLW_dio_in_cmd_data_out_5_UNCONNECTED,
      cmd_data_out(4) => NLW_dio_in_cmd_data_out_4_UNCONNECTED,
      cmd_data_out(3) => NLW_dio_in_cmd_data_out_3_UNCONNECTED,
      cmd_data_out(2) => NLW_dio_in_cmd_data_out_2_UNCONNECTED,
      cmd_data_out(1) => NLW_dio_in_cmd_data_out_1_UNCONNECTED,
      cmd_data_out(0) => NLW_dio_in_cmd_data_out_0_UNCONNECTED,
      data_in(63) => di_data(63),
      data_in(62) => di_data(62),
      data_in(61) => di_data(61),
      data_in(60) => di_data(60),
      data_in(59) => di_data(59),
      data_in(58) => di_data(58),
      data_in(57) => di_data(57),
      data_in(56) => di_data(56),
      data_in(55) => di_data(55),
      data_in(54) => di_data(54),
      data_in(53) => di_data(53),
      data_in(52) => di_data(52),
      data_in(51) => di_data(51),
      data_in(50) => di_data(50),
      data_in(49) => di_data(49),
      data_in(48) => di_data(48),
      data_in(47) => di_data(47),
      data_in(46) => di_data(46),
      data_in(45) => di_data(45),
      data_in(44) => di_data(44),
      data_in(43) => di_data(43),
      data_in(42) => di_data(42),
      data_in(41) => di_data(41),
      data_in(40) => di_data(40),
      data_in(39) => di_data(39),
      data_in(38) => di_data(38),
      data_in(37) => di_data(37),
      data_in(36) => di_data(36),
      data_in(35) => di_data(35),
      data_in(34) => di_data(34),
      data_in(33) => di_data(33),
      data_in(32) => di_data(32),
      data_in(31) => di_data(31),
      data_in(30) => di_data(30),
      data_in(29) => di_data(29),
      data_in(28) => di_data(28),
      data_in(27) => di_data(27),
      data_in(26) => di_data(26),
      data_in(25) => di_data(25),
      data_in(24) => di_data(24),
      data_in(23) => di_data(23),
      data_in(22) => di_data(22),
      data_in(21) => di_data(21),
      data_in(20) => di_data(20),
      data_in(19) => di_data(19),
      data_in(18) => di_data(18),
      data_in(17) => di_data(17),
      data_in(16) => di_data(16),
      data_in(15) => di_data(15),
      data_in(14) => di_data(14),
      data_in(13) => di_data(13),
      data_in(12) => di_data(12),
      data_in(11) => di_data(11),
      data_in(10) => di_data(10),
      data_in(9) => di_data(9),
      data_in(8) => di_data(8),
      data_in(7) => di_data(7),
      data_in(6) => di_data(6),
      data_in(5) => di_data(5),
      data_in(4) => di_data(4),
      data_in(3) => di_data(3),
      data_in(2) => di_data(2),
      data_in(1) => di_data(1),
      data_in(0) => di_data(0),
      cmd_data_in(15) => trd_host_cmd_data_6_15_Q,
      cmd_data_in(14) => trd_host_cmd_data_6_14_Q,
      cmd_data_in(13) => trd_host_cmd_data_6_13_Q,
      cmd_data_in(12) => trd_host_cmd_data_6_12_Q,
      cmd_data_in(11) => trd_host_cmd_data_6_11_Q,
      cmd_data_in(10) => trd_host_cmd_data_6_10_Q,
      cmd_data_in(9) => trd_host_cmd_data_6_9_Q,
      cmd_data_in(8) => trd_host_cmd_data_6_8_Q,
      cmd_data_in(7) => trd_host_cmd_data_6_7_Q,
      cmd_data_in(6) => trd_host_cmd_data_6_6_Q,
      cmd_data_in(5) => trd_host_cmd_data_6_5_Q,
      cmd_data_in(4) => trd_host_cmd_data_6_4_Q,
      cmd_data_in(3) => trd_host_cmd_data_6_3_Q,
      cmd_data_in(2) => trd_host_cmd_data_6_2_Q,
      cmd_data_in(1) => trd_host_cmd_data_6_1_Q,
      cmd_data_in(0) => trd_host_cmd_data_6_0_Q,
      cmd_adr(9) => trd_host_cmd_6_adr_9_Q,
      cmd_adr(8) => trd_host_cmd_6_adr_8_Q,
      cmd_adr(7) => trd_host_cmd_6_adr_7_Q,
      cmd_adr(6) => trd_host_cmd_6_adr_6_Q,
      cmd_adr(5) => trd_host_cmd_6_adr_5_Q,
      cmd_adr(4) => trd_host_cmd_6_adr_4_Q,
      cmd_adr(3) => trd_host_cmd_6_adr_3_Q,
      cmd_adr(2) => trd_host_cmd_6_adr_2_Q,
      cmd_adr(1) => trd_host_cmd_6_adr_1_Q,
      cmd_adr(0) => trd_host_cmd_6_adr_0_Q
    );
  dio_out : trd_admdio64_out_v4
    port map (
      clk => clk,
      flag_rd_ef => do_flag_rd_ef,
      flag_rd_ff => do_flag_rd_ff,
      flag_rd_hf => do_flag_rd_hf,
      bx_irq => trd_irq_7_Q,
      start => do_start,
      reset => reset,
      cmd_cmd_data_we => trd_host_cmd_7_cmd_data_we,
      data_cs => do_data_cs,
      clk_rd => do_clk,
      flag_rd_ovr => do_flag_rd_ovr,
      cmd_status_cs => trd_host_cmd_7_status_cs,
      fifo_rst => do_fifo_rst,
      cmd_data_cs => trd_host_cmd_7_data_cs,
      bx_drq_en => trd_drq_7_en,
      bx_drq_ack => trd_drq_7_ack,
      cmd_data_oe => trd_host_cmd_7_data_oe,
      cmd_cmd_data_cs => trd_host_cmd_7_cmd_data_cs,
      flag_rd_und => do_flag_rd_und,
      flag_rd_pae => do_flag_rd_pae,
      flag_rd_paf => do_flag_rd_paf,
      cmd_cmd_adr_we => trd_host_cmd_7_cmd_adr_we,
      cmd_data_we => trd_host_cmd_7_data_we,
      bx_drq_req => trd_drq_7_req,
      data_out(63) => do_data(63),
      data_out(62) => do_data(62),
      data_out(61) => do_data(61),
      data_out(60) => do_data(60),
      data_out(59) => do_data(59),
      data_out(58) => do_data(58),
      data_out(57) => do_data(57),
      data_out(56) => do_data(56),
      data_out(55) => do_data(55),
      data_out(54) => do_data(54),
      data_out(53) => do_data(53),
      data_out(52) => do_data(52),
      data_out(51) => do_data(51),
      data_out(50) => do_data(50),
      data_out(49) => do_data(49),
      data_out(48) => do_data(48),
      data_out(47) => do_data(47),
      data_out(46) => do_data(46),
      data_out(45) => do_data(45),
      data_out(44) => do_data(44),
      data_out(43) => do_data(43),
      data_out(42) => do_data(42),
      data_out(41) => do_data(41),
      data_out(40) => do_data(40),
      data_out(39) => do_data(39),
      data_out(38) => do_data(38),
      data_out(37) => do_data(37),
      data_out(36) => do_data(36),
      data_out(35) => do_data(35),
      data_out(34) => do_data(34),
      data_out(33) => do_data(33),
      data_out(32) => do_data(32),
      data_out(31) => do_data(31),
      data_out(30) => do_data(30),
      data_out(29) => do_data(29),
      data_out(28) => do_data(28),
      data_out(27) => do_data(27),
      data_out(26) => do_data(26),
      data_out(25) => do_data(25),
      data_out(24) => do_data(24),
      data_out(23) => do_data(23),
      data_out(22) => do_data(22),
      data_out(21) => do_data(21),
      data_out(20) => do_data(20),
      data_out(19) => do_data(19),
      data_out(18) => do_data(18),
      data_out(17) => do_data(17),
      data_out(16) => do_data(16),
      data_out(15) => do_data(15),
      data_out(14) => do_data(14),
      data_out(13) => do_data(13),
      data_out(12) => do_data(12),
      data_out(11) => do_data(11),
      data_out(10) => do_data(10),
      data_out(9) => do_data(9),
      data_out(8) => do_data(8),
      data_out(7) => do_data(7),
      data_out(6) => do_data(6),
      data_out(5) => do_data(5),
      data_out(4) => do_data(4),
      data_out(3) => do_data(3),
      data_out(2) => do_data(2),
      data_out(1) => do_data(1),
      data_out(0) => do_data(0),
      cmd_data_out2(15) => trd_cmd_data_7_15_Q,
      cmd_data_out2(14) => trd_cmd_data_7_14_Q,
      cmd_data_out2(13) => trd_cmd_data_7_13_Q,
      cmd_data_out2(12) => trd_cmd_data_7_12_Q,
      cmd_data_out2(11) => trd_cmd_data_7_11_Q,
      cmd_data_out2(10) => trd_cmd_data_7_10_Q,
      cmd_data_out2(9) => trd_cmd_data_7_9_Q,
      cmd_data_out2(8) => trd_cmd_data_7_8_Q,
      cmd_data_out2(7) => trd_cmd_data_7_7_Q,
      cmd_data_out2(6) => trd_cmd_data_7_6_Q,
      cmd_data_out2(5) => trd_cmd_data_7_5_Q,
      cmd_data_out2(4) => trd_cmd_data_7_4_Q,
      cmd_data_out2(3) => trd_cmd_data_7_3_Q,
      cmd_data_out2(2) => trd_cmd_data_7_2_Q,
      cmd_data_out2(1) => trd_cmd_data_7_1_Q,
      cmd_data_out2(0) => trd_cmd_data_7_0_Q,
      mode0(15) => NLW_dio_out_mode0_15_UNCONNECTED,
      mode0(14) => NLW_dio_out_mode0_14_UNCONNECTED,
      mode0(13) => NLW_dio_out_mode0_13_UNCONNECTED,
      mode0(12) => NLW_dio_out_mode0_12_UNCONNECTED,
      mode0(11) => NLW_dio_out_mode0_11_UNCONNECTED,
      mode0(10) => NLW_dio_out_mode0_10_UNCONNECTED,
      mode0(9) => NLW_dio_out_mode0_9_UNCONNECTED,
      mode0(8) => NLW_dio_out_mode0_8_UNCONNECTED,
      mode0(7) => NLW_dio_out_mode0_7_UNCONNECTED,
      mode0(6) => NLW_dio_out_mode0_6_UNCONNECTED,
      mode0(5) => NLW_dio_out_mode0_5_UNCONNECTED,
      mode0(4) => NLW_dio_out_mode0_4_UNCONNECTED,
      mode0(3) => NLW_dio_out_mode0_3_UNCONNECTED,
      mode0(2) => NLW_dio_out_mode0_2_UNCONNECTED,
      mode0(1) => NLW_dio_out_mode0_1_UNCONNECTED,
      mode0(0) => NLW_dio_out_mode0_0_UNCONNECTED,
      mode1(15) => do_mode1(15),
      mode1(14) => do_mode1(14),
      mode1(13) => do_mode1(13),
      mode1(12) => do_mode1(12),
      mode1(11) => do_mode1(11),
      mode1(10) => do_mode1(10),
      mode1(9) => do_mode1(9),
      mode1(8) => do_mode1(8),
      mode1(7) => do_mode1(7),
      mode1(6) => do_mode1(6),
      mode1(5) => do_mode1(5),
      mode1(4) => do_mode1(4),
      mode1(3) => do_mode1(3),
      mode1(2) => do_mode1(2),
      mode1(1) => do_mode1(1),
      mode1(0) => do_mode1(0),
      mode2(15) => NLW_dio_out_mode2_15_UNCONNECTED,
      mode2(14) => NLW_dio_out_mode2_14_UNCONNECTED,
      mode2(13) => NLW_dio_out_mode2_13_UNCONNECTED,
      mode2(12) => NLW_dio_out_mode2_12_UNCONNECTED,
      mode2(11) => NLW_dio_out_mode2_11_UNCONNECTED,
      mode2(10) => NLW_dio_out_mode2_10_UNCONNECTED,
      mode2(9) => NLW_dio_out_mode2_9_UNCONNECTED,
      mode2(8) => NLW_dio_out_mode2_8_UNCONNECTED,
      mode2(7) => NLW_dio_out_mode2_7_UNCONNECTED,
      mode2(6) => NLW_dio_out_mode2_6_UNCONNECTED,
      mode2(5) => NLW_dio_out_mode2_5_UNCONNECTED,
      mode2(4) => NLW_dio_out_mode2_4_UNCONNECTED,
      mode2(3) => NLW_dio_out_mode2_3_UNCONNECTED,
      mode2(2) => NLW_dio_out_mode2_2_UNCONNECTED,
      mode2(1) => NLW_dio_out_mode2_1_UNCONNECTED,
      mode2(0) => NLW_dio_out_mode2_0_UNCONNECTED,
      mode3(15) => NLW_dio_out_mode3_15_UNCONNECTED,
      mode3(14) => NLW_dio_out_mode3_14_UNCONNECTED,
      mode3(13) => NLW_dio_out_mode3_13_UNCONNECTED,
      mode3(12) => NLW_dio_out_mode3_12_UNCONNECTED,
      mode3(11) => NLW_dio_out_mode3_11_UNCONNECTED,
      mode3(10) => NLW_dio_out_mode3_10_UNCONNECTED,
      mode3(9) => NLW_dio_out_mode3_9_UNCONNECTED,
      mode3(8) => NLW_dio_out_mode3_8_UNCONNECTED,
      mode3(7) => NLW_dio_out_mode3_7_UNCONNECTED,
      mode3(6) => NLW_dio_out_mode3_6_UNCONNECTED,
      mode3(5) => NLW_dio_out_mode3_5_UNCONNECTED,
      mode3(4) => NLW_dio_out_mode3_4_UNCONNECTED,
      mode3(3) => NLW_dio_out_mode3_3_UNCONNECTED,
      mode3(2) => NLW_dio_out_mode3_2_UNCONNECTED,
      mode3(1) => NLW_dio_out_mode3_1_UNCONNECTED,
      mode3(0) => NLW_dio_out_mode3_0_UNCONNECTED,
      fifo_cnt(12) => NLW_dio_out_fifo_cnt_12_UNCONNECTED,
      fifo_cnt(11) => NLW_dio_out_fifo_cnt_11_UNCONNECTED,
      fifo_cnt(10) => NLW_dio_out_fifo_cnt_10_UNCONNECTED,
      fifo_cnt(9) => NLW_dio_out_fifo_cnt_9_UNCONNECTED,
      fifo_cnt(8) => NLW_dio_out_fifo_cnt_8_UNCONNECTED,
      fifo_cnt(7) => NLW_dio_out_fifo_cnt_7_UNCONNECTED,
      fifo_cnt(6) => NLW_dio_out_fifo_cnt_6_UNCONNECTED,
      fifo_cnt(5) => NLW_dio_out_fifo_cnt_5_UNCONNECTED,
      fifo_cnt(4) => NLW_dio_out_fifo_cnt_4_UNCONNECTED,
      fifo_cnt(3) => NLW_dio_out_fifo_cnt_3_UNCONNECTED,
      fifo_cnt(2) => NLW_dio_out_fifo_cnt_2_UNCONNECTED,
      fifo_cnt(1) => NLW_dio_out_fifo_cnt_1_UNCONNECTED,
      fifo_cnt(0) => NLW_dio_out_fifo_cnt_0_UNCONNECTED,
      cmd_data_out(15) => NLW_dio_out_cmd_data_out_15_UNCONNECTED,
      cmd_data_out(14) => NLW_dio_out_cmd_data_out_14_UNCONNECTED,
      cmd_data_out(13) => NLW_dio_out_cmd_data_out_13_UNCONNECTED,
      cmd_data_out(12) => NLW_dio_out_cmd_data_out_12_UNCONNECTED,
      cmd_data_out(11) => NLW_dio_out_cmd_data_out_11_UNCONNECTED,
      cmd_data_out(10) => NLW_dio_out_cmd_data_out_10_UNCONNECTED,
      cmd_data_out(9) => NLW_dio_out_cmd_data_out_9_UNCONNECTED,
      cmd_data_out(8) => NLW_dio_out_cmd_data_out_8_UNCONNECTED,
      cmd_data_out(7) => NLW_dio_out_cmd_data_out_7_UNCONNECTED,
      cmd_data_out(6) => NLW_dio_out_cmd_data_out_6_UNCONNECTED,
      cmd_data_out(5) => NLW_dio_out_cmd_data_out_5_UNCONNECTED,
      cmd_data_out(4) => NLW_dio_out_cmd_data_out_4_UNCONNECTED,
      cmd_data_out(3) => NLW_dio_out_cmd_data_out_3_UNCONNECTED,
      cmd_data_out(2) => NLW_dio_out_cmd_data_out_2_UNCONNECTED,
      cmd_data_out(1) => NLW_dio_out_cmd_data_out_1_UNCONNECTED,
      cmd_data_out(0) => NLW_dio_out_cmd_data_out_0_UNCONNECTED,
      test(7) => NLW_dio_out_test_7_UNCONNECTED,
      test(6) => NLW_dio_out_test_6_UNCONNECTED,
      test(5) => NLW_dio_out_test_5_UNCONNECTED,
      test(4) => NLW_dio_out_test_4_UNCONNECTED,
      test(3) => NLW_dio_out_test_3_UNCONNECTED,
      test(2) => NLW_dio_out_test_2_UNCONNECTED,
      test(1) => NLW_dio_out_test_1_UNCONNECTED,
      test(0) => NLW_dio_out_test_0_UNCONNECTED,
      data_in(63) => trd_host_data_7_63_Q,
      data_in(62) => trd_host_data_7_62_Q,
      data_in(61) => trd_host_data_7_61_Q,
      data_in(60) => trd_host_data_7_60_Q,
      data_in(59) => trd_host_data_7_59_Q,
      data_in(58) => trd_host_data_7_58_Q,
      data_in(57) => trd_host_data_7_57_Q,
      data_in(56) => trd_host_data_7_56_Q,
      data_in(55) => trd_host_data_7_55_Q,
      data_in(54) => trd_host_data_7_54_Q,
      data_in(53) => trd_host_data_7_53_Q,
      data_in(52) => trd_host_data_7_52_Q,
      data_in(51) => trd_host_data_7_51_Q,
      data_in(50) => trd_host_data_7_50_Q,
      data_in(49) => trd_host_data_7_49_Q,
      data_in(48) => trd_host_data_7_48_Q,
      data_in(47) => trd_host_data_7_47_Q,
      data_in(46) => trd_host_data_7_46_Q,
      data_in(45) => trd_host_data_7_45_Q,
      data_in(44) => trd_host_data_7_44_Q,
      data_in(43) => trd_host_data_7_43_Q,
      data_in(42) => trd_host_data_7_42_Q,
      data_in(41) => trd_host_data_7_41_Q,
      data_in(40) => trd_host_data_7_40_Q,
      data_in(39) => trd_host_data_7_39_Q,
      data_in(38) => trd_host_data_7_38_Q,
      data_in(37) => trd_host_data_7_37_Q,
      data_in(36) => trd_host_data_7_36_Q,
      data_in(35) => trd_host_data_7_35_Q,
      data_in(34) => trd_host_data_7_34_Q,
      data_in(33) => trd_host_data_7_33_Q,
      data_in(32) => trd_host_data_7_32_Q,
      data_in(31) => trd_host_data_7_31_Q,
      data_in(30) => trd_host_data_7_30_Q,
      data_in(29) => trd_host_data_7_29_Q,
      data_in(28) => trd_host_data_7_28_Q,
      data_in(27) => trd_host_data_7_27_Q,
      data_in(26) => trd_host_data_7_26_Q,
      data_in(25) => trd_host_data_7_25_Q,
      data_in(24) => trd_host_data_7_24_Q,
      data_in(23) => trd_host_data_7_23_Q,
      data_in(22) => trd_host_data_7_22_Q,
      data_in(21) => trd_host_data_7_21_Q,
      data_in(20) => trd_host_data_7_20_Q,
      data_in(19) => trd_host_data_7_19_Q,
      data_in(18) => trd_host_data_7_18_Q,
      data_in(17) => trd_host_data_7_17_Q,
      data_in(16) => trd_host_data_7_16_Q,
      data_in(15) => trd_host_data_7_15_Q,
      data_in(14) => trd_host_data_7_14_Q,
      data_in(13) => trd_host_data_7_13_Q,
      data_in(12) => trd_host_data_7_12_Q,
      data_in(11) => trd_host_data_7_11_Q,
      data_in(10) => trd_host_data_7_10_Q,
      data_in(9) => trd_host_data_7_9_Q,
      data_in(8) => trd_host_data_7_8_Q,
      data_in(7) => trd_host_data_7_7_Q,
      data_in(6) => trd_host_data_7_6_Q,
      data_in(5) => trd_host_data_7_5_Q,
      data_in(4) => trd_host_data_7_4_Q,
      data_in(3) => trd_host_data_7_3_Q,
      data_in(2) => trd_host_data_7_2_Q,
      data_in(1) => trd_host_data_7_1_Q,
      data_in(0) => trd_host_data_7_0_Q,
      cmd_data_in(15) => trd_host_cmd_data_7_15_Q,
      cmd_data_in(14) => trd_host_cmd_data_7_14_Q,
      cmd_data_in(13) => trd_host_cmd_data_7_13_Q,
      cmd_data_in(12) => trd_host_cmd_data_7_12_Q,
      cmd_data_in(11) => trd_host_cmd_data_7_11_Q,
      cmd_data_in(10) => trd_host_cmd_data_7_10_Q,
      cmd_data_in(9) => trd_host_cmd_data_7_9_Q,
      cmd_data_in(8) => trd_host_cmd_data_7_8_Q,
      cmd_data_in(7) => trd_host_cmd_data_7_7_Q,
      cmd_data_in(6) => trd_host_cmd_data_7_6_Q,
      cmd_data_in(5) => trd_host_cmd_data_7_5_Q,
      cmd_data_in(4) => trd_host_cmd_data_7_4_Q,
      cmd_data_in(3) => trd_host_cmd_data_7_3_Q,
      cmd_data_in(2) => trd_host_cmd_data_7_2_Q,
      cmd_data_in(1) => trd_host_cmd_data_7_1_Q,
      cmd_data_in(0) => trd_host_cmd_data_7_0_Q,
      cmd_adr(9) => trd_host_cmd_7_adr_9_Q,
      cmd_adr(8) => trd_host_cmd_7_adr_8_Q,
      cmd_adr(7) => trd_host_cmd_7_adr_7_Q,
      cmd_adr(6) => trd_host_cmd_7_adr_6_Q,
      cmd_adr(5) => trd_host_cmd_7_adr_5_Q,
      cmd_adr(4) => trd_host_cmd_7_adr_4_Q,
      cmd_adr(3) => trd_host_cmd_7_adr_3_Q,
      cmd_adr(2) => trd_host_cmd_7_adr_2_Q,
      cmd_adr(1) => trd_host_cmd_7_adr_1_Q,
      cmd_adr(0) => trd_host_cmd_7_adr_0_Q
    );
  amb : cl_ambpex5_m5
    port map (
      trd_host_cmd_11_cmd_data_we => NLW_amb_trd_host_cmd_11_cmd_data_we_UNCONNECTED,
      trd_host_cmd_13_data_oe => NLW_amb_trd_host_cmd_13_data_oe_UNCONNECTED,
      trd_host_cmd_6_cmd_data_cs => trd_host_cmd_6_cmd_data_cs,
      trd_drq_14_req => N0,
      trd_drq_14_en => N0,
      trd_host_cmd_5_cmd_adr_we => NLW_amb_trd_host_cmd_5_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_2_cmd_data_we => NLW_amb_trd_host_cmd_2_cmd_data_we_UNCONNECTED,
      trd_host_cmd_9_data_cs => NLW_amb_trd_host_cmd_9_data_cs_UNCONNECTED,
      trd_host_cmd_12_cmd_data_cs => NLW_amb_trd_host_cmd_12_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_15_cmd_adr_we => NLW_amb_trd_host_cmd_15_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_2_data_we => NLW_amb_trd_host_cmd_2_data_we_UNCONNECTED,
      trd_drq_15_req => N0,
      trd_host_cmd_0_data_cs => trd_host_cmd_0_data_cs,
      trd_host_cmd_1_data_oe => trd_host_cmd_1_data_oe,
      trd_main_drq_0_ack => trd_main_drq_0_ack,
      trd_main_drq_3_en => trd_main_drq_3_en,
      trd_host_cmd_3_cmd_data_cs => NLW_amb_trd_host_cmd_3_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_2_status_cs => NLW_amb_trd_host_cmd_2_status_cs_UNCONNECTED,
      trd_host_cmd_13_data_we => NLW_amb_trd_host_cmd_13_data_we_UNCONNECTED,
      trd_host_cmd_11_data_cs => NLW_amb_trd_host_cmd_11_data_cs_UNCONNECTED,
      trd_main_drq_1_ack => trd_main_drq_1_ack,
      trd_drq_3_en => N0,
      trd_drq_0_ack => trd_drq_0_ack,
      trd_host_cmd_12_data_oe => NLW_amb_trd_host_cmd_12_data_oe_UNCONNECTED,
      trd_host_cmd_9_cmd_data_we => NLW_amb_trd_host_cmd_9_cmd_data_we_UNCONNECTED,
      trd_main_drq_8_en => N0,
      trd_host_cmd_8_status_cs => NLW_amb_trd_host_cmd_8_status_cs_UNCONNECTED,
      trd_host_cmd_11_status_cs => NLW_amb_trd_host_cmd_11_status_cs_UNCONNECTED,
      trd_main_drq_2_ack => trd_main_drq_2_ack,
      trd_drq_8_en => N0,
      trd_drq_1_ack => trd_drq_1_ack,
      clk_out => clk,
      trd_host_cmd_8_data_cs => NLW_amb_trd_host_cmd_8_data_cs_UNCONNECTED,
      trd_host_cmd_9_data_oe => NLW_amb_trd_host_cmd_9_data_oe_UNCONNECTED,
      trd_host_cmd_4_cmd_adr_we => NLW_amb_trd_host_cmd_4_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_1_data_we => trd_host_cmd_1_data_we,
      clk5_pll => NLW_amb_clk5_pll_UNCONNECTED,
      trd_main_drq_3_ack => trd_main_drq_3_ack,
      trd_main_drq_11_en => N0,
      trd_drq_2_ack => N0,
      trd_host_cmd_0_data_oe => trd_host_cmd_0_data_oe,
      trd_host_cmd_15_cmd_data_we => NLW_amb_trd_host_cmd_15_cmd_data_we_UNCONNECTED,
      trd_host_cmd_14_cmd_adr_we => NLW_amb_trd_host_cmd_14_cmd_adr_we_UNCONNECTED,
      trd_main_drq_4_ack => N0,
      trd_main_drq_0_req => trd_main_drq_0_req,
      trd_drq_3_ack => N0,
      trd_drq_11_en => N0,
      trd_host_cmd_0_cmd_data_cs => trd_host_cmd_0_cmd_data_cs,
      trd_host_cmd_12_data_we => NLW_amb_trd_host_cmd_12_data_we_UNCONNECTED,
      trd_host_cmd_10_data_cs => NLW_amb_trd_host_cmd_10_data_cs_UNCONNECTED,
      trd_host_cmd_11_data_oe => NLW_amb_trd_host_cmd_11_data_oe_UNCONNECTED,
      trd_host_cmd_6_cmd_data_we => trd_host_cmd_6_cmd_data_we,
      reset_out => reset_main,
      trd_main_drq_1_req => trd_main_drq_1_req,
      trd_main_drq_5_ack => N0,
      trd_drq_4_ack => N0,
      trd_drq_0_req => trd_drq_0_req,
      trd_host_cmd_9_data_we => NLW_amb_trd_host_cmd_9_data_we_UNCONNECTED,
      trd_host_cmd_3_status_cs => NLW_amb_trd_host_cmd_3_status_cs_UNCONNECTED,
      trd_main_drq_0_en => trd_main_drq_0_en,
      trd_host_cmd_7_data_cs => trd_host_cmd_7_data_cs,
      clk_lock_out => NLW_amb_clk_lock_out_UNCONNECTED,
      trd_host_cmd_12_cmd_data_we => NLW_amb_trd_host_cmd_12_cmd_data_we_UNCONNECTED,
      trd_host_cmd_8_data_oe => NLW_amb_trd_host_cmd_8_data_oe_UNCONNECTED,
      trd_main_drq_2_req => trd_main_drq_2_req,
      trd_main_drq_6_ack => N0,
      trd_drq_5_ack => N0,
      trd_drq_1_req => trd_drq_1_req,
      trd_host_cmd_0_data_we => trd_host_cmd_0_data_we,
      trd_host_cmd_7_cmd_data_cs => trd_host_cmd_7_cmd_data_cs,
      trd_drq_0_en => trd_drq_0_en,
      trd_host_cmd_9_status_cs => NLW_amb_trd_host_cmd_9_status_cs_UNCONNECTED,
      trd_main_drq_5_en => N0,
      trd_host_cmd_3_cmd_adr_we => NLW_amb_trd_host_cmd_3_cmd_adr_we_UNCONNECTED,
      trd_main_drq_3_req => trd_main_drq_3_req,
      trd_main_drq_7_ack => N0,
      trd_drq_6_ack => trd_drq_6_ack,
      trd_drq_2_req => N0,
      trd_host_cmd_12_status_cs => NLW_amb_trd_host_cmd_12_status_cs_UNCONNECTED,
      trd_host_cmd_3_cmd_data_we => NLW_amb_trd_host_cmd_3_cmd_data_we_UNCONNECTED,
      trd_drq_5_en => N0,
      trd_host_cmd_11_data_we => NLW_amb_trd_host_cmd_11_data_we_UNCONNECTED,
      trd_host_cmd_13_cmd_adr_we => NLW_amb_trd_host_cmd_13_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_10_data_oe => NLW_amb_trd_host_cmd_10_data_oe_UNCONNECTED,
      trd_main_drq_8_ack => N0,
      trd_main_drq_4_req => N0,
      trd_drq_7_ack => trd_drq_7_ack,
      trd_drq_3_req => N0,
      clk2_pll => NLW_amb_clk2_pll_UNCONNECTED,
      trd_host_cmd_13_cmd_data_cs => NLW_amb_trd_host_cmd_13_cmd_data_cs_UNCONNECTED,
      trd_main_drq_9_ack => N0,
      trd_main_drq_5_req => N0,
      trd_host_cmd_8_data_we => NLW_amb_trd_host_cmd_8_data_we_UNCONNECTED,
      trd_drq_4_req => N0,
      trd_drq_8_ack => N0,
      trd_host_cmd_6_data_cs => trd_host_cmd_6_data_cs,
      trd_host_cmd_7_data_oe => trd_host_cmd_7_data_oe,
      trd_main_drq_13_en => N0,
      trd_host_cmd_4_cmd_data_cs => NLW_amb_trd_host_cmd_4_cmd_data_cs_UNCONNECTED,
      led_h1 => led_h1,
      led_h2 => led_h2,
      trd_main_drq_6_req => N0,
      led_h3 => led_h3,
      trd_drq_5_req => N0,
      trd_drq_9_ack => N0,
      led_h4 => led_h4,
      trd_drq_13_en => N0,
      trd_host_cmd_0_cmd_data_we => trd_host_cmd_0_cmd_data_we,
      trd_host_cmd_4_status_cs => NLW_amb_trd_host_cmd_4_status_cs_UNCONNECTED,
      trd_host_cmd_10_data_we => NLW_amb_trd_host_cmd_10_data_we_UNCONNECTED,
      trd_main_drq_7_req => N0,
      trd_host_cmd_9_cmd_adr_we => NLW_amb_trd_host_cmd_9_cmd_adr_we_UNCONNECTED,
      trd_drq_6_req => trd_drq_6_req,
      trd_host_cmd_2_cmd_adr_we => NLW_amb_trd_host_cmd_2_cmd_adr_we_UNCONNECTED,
      bperst => bperst,
      trd_host_cmd_12_cmd_adr_we => NLW_amb_trd_host_cmd_12_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_10_cmd_data_cs => NLW_amb_trd_host_cmd_10_cmd_data_cs_UNCONNECTED,
      trd_main_drq_8_req => N0,
      trd_drq_7_req => trd_drq_7_req,
      trd_main_drq_2_en => trd_main_drq_2_en,
      trd_host_cmd_13_status_cs => NLW_amb_trd_host_cmd_13_status_cs_UNCONNECTED,
      trd_host_cmd_7_data_we => trd_host_cmd_7_data_we,
      trd_host_cmd_5_data_cs => NLW_amb_trd_host_cmd_5_data_cs_UNCONNECTED,
      trd_host_cmd_6_data_oe => trd_host_cmd_6_data_oe,
      trd_drq_2_en => N0,
      trd_host_cmd_7_cmd_data_we => trd_host_cmd_7_cmd_data_we,
      trd_main_drq_9_req => N0,
      trd_drq_8_req => N0,
      trd_main_drq_7_en => N0,
      trd_host_cmd_1_cmd_data_cs => trd_host_cmd_1_cmd_data_cs,
      clk30k => clk30k,
      trd_drq_7_en => trd_drq_7_en,
      trd_drq_9_req => N0,
      clk200_out => clk200,
      clk4_pll => NLW_amb_clk4_pll_UNCONNECTED,
      trd_main_drq_10_en => N0,
      trd_host_cmd_13_cmd_data_we => NLW_amb_trd_host_cmd_13_cmd_data_we_UNCONNECTED,
      trd_host_cmd_8_cmd_adr_we => NLW_amb_trd_host_cmd_8_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_1_cmd_adr_we => trd_host_cmd_1_cmd_adr_we,
      trd_host_cmd_8_cmd_data_cs => NLW_amb_trd_host_cmd_8_cmd_data_cs_UNCONNECTED,
      trd_main_drq_15_en => N0,
      trd_host_cmd_6_data_we => trd_host_cmd_6_data_we,
      trd_drq_10_en => N0,
      trd_host_cmd_4_data_cs => NLW_amb_trd_host_cmd_4_data_cs_UNCONNECTED,
      trd_host_cmd_5_status_cs => NLW_amb_trd_host_cmd_5_status_cs_UNCONNECTED,
      trd_host_cmd_5_data_oe => NLW_amb_trd_host_cmd_5_data_oe_UNCONNECTED,
      trd_host_cmd_4_cmd_data_we => NLW_amb_trd_host_cmd_4_cmd_data_we_UNCONNECTED,
      trd_drq_15_en => N0,
      trd_host_cmd_11_cmd_adr_we => NLW_amb_trd_host_cmd_11_cmd_adr_we_UNCONNECTED,
      trd_main_drq_10_ack => N0,
      trd_host_cmd_15_data_cs => NLW_amb_trd_host_cmd_15_data_cs_UNCONNECTED,
      trd_host_cmd_14_status_cs => NLW_amb_trd_host_cmd_14_status_cs_UNCONNECTED,
      trd_host_cmd_14_cmd_data_cs => NLW_amb_trd_host_cmd_14_cmd_data_cs_UNCONNECTED,
      trd_main_drq_11_ack => N0,
      trd_host_cmd_10_cmd_data_we => NLW_amb_trd_host_cmd_10_cmd_data_we_UNCONNECTED,
      trd_main_drq_4_en => N0,
      trd_host_cmd_5_cmd_data_cs => NLW_amb_trd_host_cmd_5_cmd_data_cs_UNCONNECTED,
      trd_main_drq_12_ack => N0,
      trd_drq_4_en => N0,
      trd_host_cmd_5_data_we => NLW_amb_trd_host_cmd_5_data_we_UNCONNECTED,
      trd_host_cmd_7_cmd_adr_we => trd_host_cmd_7_cmd_adr_we,
      trd_host_cmd_3_data_cs => NLW_amb_trd_host_cmd_3_data_cs_UNCONNECTED,
      trd_host_cmd_0_cmd_adr_we => trd_host_cmd_0_cmd_adr_we,
      trd_host_cmd_4_data_oe => NLW_amb_trd_host_cmd_4_data_oe_UNCONNECTED,
      trd_main_drq_9_en => N0,
      test_mode => test_mode,
      trd_host_cmd_1_cmd_data_we => trd_host_cmd_1_cmd_data_we,
      trd_main_drq_13_ack => N0,
      trd_drq_9_en => N0,
      trd_host_cmd_0_status_cs => trd_host_cmd_0_status_cs,
      trd_drq_10_ack => N0,
      trd_host_cmd_14_data_cs => NLW_amb_trd_host_cmd_14_data_cs_UNCONNECTED,
      trd_host_cmd_15_data_oe => NLW_amb_trd_host_cmd_15_data_oe_UNCONNECTED,
      trd_host_cmd_11_cmd_data_cs => NLW_amb_trd_host_cmd_11_cmd_data_cs_UNCONNECTED,
      trd_main_drq_10_req => N0,
      trd_main_drq_14_ack => N0,
      trd_main_drq_12_en => N0,
      trd_host_cmd_10_cmd_adr_we => NLW_amb_trd_host_cmd_10_cmd_adr_we_UNCONNECTED,
      trd_host_cmd_6_status_cs => trd_host_cmd_6_status_cs,
      trd_drq_11_ack => N0,
      trd_host_cmd_8_cmd_data_we => NLW_amb_trd_host_cmd_8_cmd_data_we_UNCONNECTED,
      trd_main_drq_11_req => N0,
      trd_main_drq_15_ack => N0,
      trd_drq_12_en => N0,
      trd_host_cmd_2_cmd_data_cs => NLW_amb_trd_host_cmd_2_cmd_data_cs_UNCONNECTED,
      trd_drq_12_ack => N0,
      trd_host_cmd_15_status_cs => NLW_amb_trd_host_cmd_15_status_cs_UNCONNECTED,
      trd_host_cmd_4_data_we => NLW_amb_trd_host_cmd_4_data_we_UNCONNECTED,
      trd_host_cmd_2_data_cs => NLW_amb_trd_host_cmd_2_data_cs_UNCONNECTED,
      trd_host_cmd_3_data_oe => NLW_amb_trd_host_cmd_3_data_oe_UNCONNECTED,
      trd_main_drq_12_req => N0,
      trd_drq_13_ack => N0,
      trd_main_drq_1_en => trd_main_drq_1_en,
      trd_host_cmd_15_data_we => NLW_amb_trd_host_cmd_15_data_we_UNCONNECTED,
      trd_main_drq_13_req => N0,
      trd_host_cmd_13_data_cs => NLW_amb_trd_host_cmd_13_data_cs_UNCONNECTED,
      trd_host_cmd_14_cmd_data_we => NLW_amb_trd_host_cmd_14_cmd_data_we_UNCONNECTED,
      trd_host_cmd_14_data_oe => NLW_amb_trd_host_cmd_14_data_oe_UNCONNECTED,
      trd_host_cmd_6_cmd_adr_we => trd_host_cmd_6_cmd_adr_we,
      trd_drq_10_req => N0,
      trd_drq_14_ack => N0,
      trd_drq_1_en => trd_drq_1_en,
      trd_host_cmd_9_cmd_data_cs => NLW_amb_trd_host_cmd_9_cmd_data_cs_UNCONNECTED,
      trd_main_drq_6_en => N0,
      trd_main_drq_14_req => N0,
      trd_host_cmd_1_status_cs => trd_host_cmd_1_status_cs,
      trd_drq_11_req => N0,
      trd_drq_15_ack => N0,
      trd_host_cmd_5_cmd_data_we => NLW_amb_trd_host_cmd_5_cmd_data_we_UNCONNECTED,
      trd_drq_6_en => trd_drq_6_en,
      mgt251_n => mgt251_n,
      mgt251_p => mgt251_p,
      trd_host_cmd_3_data_we => NLW_amb_trd_host_cmd_3_data_we_UNCONNECTED,
      trd_main_drq_15_req => N0,
      trd_host_cmd_1_data_cs => trd_host_cmd_1_data_cs,
      trd_host_cmd_2_data_oe => NLW_amb_trd_host_cmd_2_data_oe_UNCONNECTED,
      trd_host_cmd_7_status_cs => trd_host_cmd_7_status_cs,
      trd_drq_12_req => N0,
      clk3_pll => NLW_amb_clk3_pll_UNCONNECTED,
      trd_host_cmd_15_cmd_data_cs => NLW_amb_trd_host_cmd_15_cmd_data_cs_UNCONNECTED,
      trd_host_cmd_10_status_cs => NLW_amb_trd_host_cmd_10_status_cs_UNCONNECTED,
      trd_host_cmd_14_data_we => NLW_amb_trd_host_cmd_14_data_we_UNCONNECTED,
      trd_drq_13_req => N0,
      trd_host_cmd_12_data_cs => NLW_amb_trd_host_cmd_12_data_cs_UNCONNECTED,
      trd_main_drq_14_en => N0,
      trd_host_cmd_5_adr_9_Q => NLW_amb_trd_host_cmd_5_adr_9_UNCONNECTED,
      trd_host_cmd_5_adr_8_Q => NLW_amb_trd_host_cmd_5_adr_8_UNCONNECTED,
      trd_host_cmd_5_adr_7_Q => NLW_amb_trd_host_cmd_5_adr_7_UNCONNECTED,
      trd_host_cmd_5_adr_6_Q => NLW_amb_trd_host_cmd_5_adr_6_UNCONNECTED,
      trd_host_cmd_5_adr_5_Q => NLW_amb_trd_host_cmd_5_adr_5_UNCONNECTED,
      trd_host_cmd_5_adr_4_Q => NLW_amb_trd_host_cmd_5_adr_4_UNCONNECTED,
      trd_host_cmd_5_adr_3_Q => NLW_amb_trd_host_cmd_5_adr_3_UNCONNECTED,
      trd_host_cmd_5_adr_2_Q => NLW_amb_trd_host_cmd_5_adr_2_UNCONNECTED,
      trd_host_cmd_5_adr_1_Q => NLW_amb_trd_host_cmd_5_adr_1_UNCONNECTED,
      trd_host_cmd_5_adr_0_Q => NLW_amb_trd_host_cmd_5_adr_0_UNCONNECTED,
      trd_host_cmd_6_adr_9_Q => trd_host_cmd_6_adr_9_Q,
      trd_host_cmd_6_adr_8_Q => trd_host_cmd_6_adr_8_Q,
      trd_host_cmd_6_adr_7_Q => trd_host_cmd_6_adr_7_Q,
      trd_host_cmd_6_adr_6_Q => trd_host_cmd_6_adr_6_Q,
      trd_host_cmd_6_adr_5_Q => trd_host_cmd_6_adr_5_Q,
      trd_host_cmd_6_adr_4_Q => trd_host_cmd_6_adr_4_Q,
      trd_host_cmd_6_adr_3_Q => trd_host_cmd_6_adr_3_Q,
      trd_host_cmd_6_adr_2_Q => trd_host_cmd_6_adr_2_Q,
      trd_host_cmd_6_adr_1_Q => trd_host_cmd_6_adr_1_Q,
      trd_host_cmd_6_adr_0_Q => trd_host_cmd_6_adr_0_Q,
      trd_host_cmd_7_adr_9_Q => trd_host_cmd_7_adr_9_Q,
      trd_host_cmd_7_adr_8_Q => trd_host_cmd_7_adr_8_Q,
      trd_host_cmd_7_adr_7_Q => trd_host_cmd_7_adr_7_Q,
      trd_host_cmd_7_adr_6_Q => trd_host_cmd_7_adr_6_Q,
      trd_host_cmd_7_adr_5_Q => trd_host_cmd_7_adr_5_Q,
      trd_host_cmd_7_adr_4_Q => trd_host_cmd_7_adr_4_Q,
      trd_host_cmd_7_adr_3_Q => trd_host_cmd_7_adr_3_Q,
      trd_host_cmd_7_adr_2_Q => trd_host_cmd_7_adr_2_Q,
      trd_host_cmd_7_adr_1_Q => trd_host_cmd_7_adr_1_Q,
      trd_host_cmd_7_adr_0_Q => trd_host_cmd_7_adr_0_Q,
      trd_host_cmd_8_adr_9_Q => NLW_amb_trd_host_cmd_8_adr_9_UNCONNECTED,
      trd_host_cmd_8_adr_8_Q => NLW_amb_trd_host_cmd_8_adr_8_UNCONNECTED,
      trd_host_cmd_8_adr_7_Q => NLW_amb_trd_host_cmd_8_adr_7_UNCONNECTED,
      trd_host_cmd_8_adr_6_Q => NLW_amb_trd_host_cmd_8_adr_6_UNCONNECTED,
      trd_host_cmd_8_adr_5_Q => NLW_amb_trd_host_cmd_8_adr_5_UNCONNECTED,
      trd_host_cmd_8_adr_4_Q => NLW_amb_trd_host_cmd_8_adr_4_UNCONNECTED,
      trd_host_cmd_8_adr_3_Q => NLW_amb_trd_host_cmd_8_adr_3_UNCONNECTED,
      trd_host_cmd_8_adr_2_Q => NLW_amb_trd_host_cmd_8_adr_2_UNCONNECTED,
      trd_host_cmd_8_adr_1_Q => NLW_amb_trd_host_cmd_8_adr_1_UNCONNECTED,
      trd_host_cmd_8_adr_0_Q => NLW_amb_trd_host_cmd_8_adr_0_UNCONNECTED,
      trd_host_cmd_9_adr_9_Q => NLW_amb_trd_host_cmd_9_adr_9_UNCONNECTED,
      trd_host_cmd_9_adr_8_Q => NLW_amb_trd_host_cmd_9_adr_8_UNCONNECTED,
      trd_host_cmd_9_adr_7_Q => NLW_amb_trd_host_cmd_9_adr_7_UNCONNECTED,
      trd_host_cmd_9_adr_6_Q => NLW_amb_trd_host_cmd_9_adr_6_UNCONNECTED,
      trd_host_cmd_9_adr_5_Q => NLW_amb_trd_host_cmd_9_adr_5_UNCONNECTED,
      trd_host_cmd_9_adr_4_Q => NLW_amb_trd_host_cmd_9_adr_4_UNCONNECTED,
      trd_host_cmd_9_adr_3_Q => NLW_amb_trd_host_cmd_9_adr_3_UNCONNECTED,
      trd_host_cmd_9_adr_2_Q => NLW_amb_trd_host_cmd_9_adr_2_UNCONNECTED,
      trd_host_cmd_9_adr_1_Q => NLW_amb_trd_host_cmd_9_adr_1_UNCONNECTED,
      trd_host_cmd_9_adr_0_Q => NLW_amb_trd_host_cmd_9_adr_0_UNCONNECTED,
      trd_host_cmd_10_adr_9_Q => NLW_amb_trd_host_cmd_10_adr_9_UNCONNECTED,
      trd_host_cmd_10_adr_8_Q => NLW_amb_trd_host_cmd_10_adr_8_UNCONNECTED,
      trd_host_cmd_10_adr_7_Q => NLW_amb_trd_host_cmd_10_adr_7_UNCONNECTED,
      trd_host_cmd_10_adr_6_Q => NLW_amb_trd_host_cmd_10_adr_6_UNCONNECTED,
      trd_host_cmd_10_adr_5_Q => NLW_amb_trd_host_cmd_10_adr_5_UNCONNECTED,
      trd_host_cmd_10_adr_4_Q => NLW_amb_trd_host_cmd_10_adr_4_UNCONNECTED,
      trd_host_cmd_10_adr_3_Q => NLW_amb_trd_host_cmd_10_adr_3_UNCONNECTED,
      trd_host_cmd_10_adr_2_Q => NLW_amb_trd_host_cmd_10_adr_2_UNCONNECTED,
      trd_host_cmd_10_adr_1_Q => NLW_amb_trd_host_cmd_10_adr_1_UNCONNECTED,
      trd_host_cmd_10_adr_0_Q => NLW_amb_trd_host_cmd_10_adr_0_UNCONNECTED,
      trd_host_cmd_11_adr_9_Q => NLW_amb_trd_host_cmd_11_adr_9_UNCONNECTED,
      trd_host_cmd_11_adr_8_Q => NLW_amb_trd_host_cmd_11_adr_8_UNCONNECTED,
      trd_host_cmd_11_adr_7_Q => NLW_amb_trd_host_cmd_11_adr_7_UNCONNECTED,
      trd_host_cmd_11_adr_6_Q => NLW_amb_trd_host_cmd_11_adr_6_UNCONNECTED,
      trd_host_cmd_11_adr_5_Q => NLW_amb_trd_host_cmd_11_adr_5_UNCONNECTED,
      trd_host_cmd_11_adr_4_Q => NLW_amb_trd_host_cmd_11_adr_4_UNCONNECTED,
      trd_host_cmd_11_adr_3_Q => NLW_amb_trd_host_cmd_11_adr_3_UNCONNECTED,
      trd_host_cmd_11_adr_2_Q => NLW_amb_trd_host_cmd_11_adr_2_UNCONNECTED,
      trd_host_cmd_11_adr_1_Q => NLW_amb_trd_host_cmd_11_adr_1_UNCONNECTED,
      trd_host_cmd_11_adr_0_Q => NLW_amb_trd_host_cmd_11_adr_0_UNCONNECTED,
      trd_host_cmd_12_adr_9_Q => NLW_amb_trd_host_cmd_12_adr_9_UNCONNECTED,
      trd_host_cmd_12_adr_8_Q => NLW_amb_trd_host_cmd_12_adr_8_UNCONNECTED,
      trd_host_cmd_12_adr_7_Q => NLW_amb_trd_host_cmd_12_adr_7_UNCONNECTED,
      trd_host_cmd_12_adr_6_Q => NLW_amb_trd_host_cmd_12_adr_6_UNCONNECTED,
      trd_host_cmd_12_adr_5_Q => NLW_amb_trd_host_cmd_12_adr_5_UNCONNECTED,
      trd_host_cmd_12_adr_4_Q => NLW_amb_trd_host_cmd_12_adr_4_UNCONNECTED,
      trd_host_cmd_12_adr_3_Q => NLW_amb_trd_host_cmd_12_adr_3_UNCONNECTED,
      trd_host_cmd_12_adr_2_Q => NLW_amb_trd_host_cmd_12_adr_2_UNCONNECTED,
      trd_host_cmd_12_adr_1_Q => NLW_amb_trd_host_cmd_12_adr_1_UNCONNECTED,
      trd_host_cmd_12_adr_0_Q => NLW_amb_trd_host_cmd_12_adr_0_UNCONNECTED,
      trd_host_cmd_13_adr_9_Q => NLW_amb_trd_host_cmd_13_adr_9_UNCONNECTED,
      trd_host_cmd_13_adr_8_Q => NLW_amb_trd_host_cmd_13_adr_8_UNCONNECTED,
      trd_host_cmd_13_adr_7_Q => NLW_amb_trd_host_cmd_13_adr_7_UNCONNECTED,
      trd_host_cmd_13_adr_6_Q => NLW_amb_trd_host_cmd_13_adr_6_UNCONNECTED,
      trd_host_cmd_13_adr_5_Q => NLW_amb_trd_host_cmd_13_adr_5_UNCONNECTED,
      trd_host_cmd_13_adr_4_Q => NLW_amb_trd_host_cmd_13_adr_4_UNCONNECTED,
      trd_host_cmd_13_adr_3_Q => NLW_amb_trd_host_cmd_13_adr_3_UNCONNECTED,
      trd_host_cmd_13_adr_2_Q => NLW_amb_trd_host_cmd_13_adr_2_UNCONNECTED,
      trd_host_cmd_13_adr_1_Q => NLW_amb_trd_host_cmd_13_adr_1_UNCONNECTED,
      trd_host_cmd_13_adr_0_Q => NLW_amb_trd_host_cmd_13_adr_0_UNCONNECTED,
      trd_host_cmd_14_adr_9_Q => NLW_amb_trd_host_cmd_14_adr_9_UNCONNECTED,
      trd_host_cmd_14_adr_8_Q => NLW_amb_trd_host_cmd_14_adr_8_UNCONNECTED,
      trd_host_cmd_14_adr_7_Q => NLW_amb_trd_host_cmd_14_adr_7_UNCONNECTED,
      trd_host_cmd_14_adr_6_Q => NLW_amb_trd_host_cmd_14_adr_6_UNCONNECTED,
      trd_host_cmd_14_adr_5_Q => NLW_amb_trd_host_cmd_14_adr_5_UNCONNECTED,
      trd_host_cmd_14_adr_4_Q => NLW_amb_trd_host_cmd_14_adr_4_UNCONNECTED,
      trd_host_cmd_14_adr_3_Q => NLW_amb_trd_host_cmd_14_adr_3_UNCONNECTED,
      trd_host_cmd_14_adr_2_Q => NLW_amb_trd_host_cmd_14_adr_2_UNCONNECTED,
      trd_host_cmd_14_adr_1_Q => NLW_amb_trd_host_cmd_14_adr_1_UNCONNECTED,
      trd_host_cmd_14_adr_0_Q => NLW_amb_trd_host_cmd_14_adr_0_UNCONNECTED,
      trd_host_cmd_15_adr_9_Q => NLW_amb_trd_host_cmd_15_adr_9_UNCONNECTED,
      trd_host_cmd_15_adr_8_Q => NLW_amb_trd_host_cmd_15_adr_8_UNCONNECTED,
      trd_host_cmd_15_adr_7_Q => NLW_amb_trd_host_cmd_15_adr_7_UNCONNECTED,
      trd_host_cmd_15_adr_6_Q => NLW_amb_trd_host_cmd_15_adr_6_UNCONNECTED,
      trd_host_cmd_15_adr_5_Q => NLW_amb_trd_host_cmd_15_adr_5_UNCONNECTED,
      trd_host_cmd_15_adr_4_Q => NLW_amb_trd_host_cmd_15_adr_4_UNCONNECTED,
      trd_host_cmd_15_adr_3_Q => NLW_amb_trd_host_cmd_15_adr_3_UNCONNECTED,
      trd_host_cmd_15_adr_2_Q => NLW_amb_trd_host_cmd_15_adr_2_UNCONNECTED,
      trd_host_cmd_15_adr_1_Q => NLW_amb_trd_host_cmd_15_adr_1_UNCONNECTED,
      trd_host_cmd_15_adr_0_Q => NLW_amb_trd_host_cmd_15_adr_0_UNCONNECTED,
      trd_host_cmd_0_adr_9_Q => trd_host_cmd_0_adr_9_Q,
      trd_host_cmd_0_adr_8_Q => trd_host_cmd_0_adr_8_Q,
      trd_host_cmd_0_adr_7_Q => trd_host_cmd_0_adr_7_Q,
      trd_host_cmd_0_adr_6_Q => trd_host_cmd_0_adr_6_Q,
      trd_host_cmd_0_adr_5_Q => trd_host_cmd_0_adr_5_Q,
      trd_host_cmd_0_adr_4_Q => trd_host_cmd_0_adr_4_Q,
      trd_host_cmd_0_adr_3_Q => trd_host_cmd_0_adr_3_Q,
      trd_host_cmd_0_adr_2_Q => trd_host_cmd_0_adr_2_Q,
      trd_host_cmd_0_adr_1_Q => trd_host_cmd_0_adr_1_Q,
      trd_host_cmd_0_adr_0_Q => trd_host_cmd_0_adr_0_Q,
      trd_host_cmd_1_adr_9_Q => trd_host_cmd_1_adr_9_Q,
      trd_host_cmd_1_adr_8_Q => trd_host_cmd_1_adr_8_Q,
      trd_host_cmd_1_adr_7_Q => trd_host_cmd_1_adr_7_Q,
      trd_host_cmd_1_adr_6_Q => trd_host_cmd_1_adr_6_Q,
      trd_host_cmd_1_adr_5_Q => trd_host_cmd_1_adr_5_Q,
      trd_host_cmd_1_adr_4_Q => trd_host_cmd_1_adr_4_Q,
      trd_host_cmd_1_adr_3_Q => trd_host_cmd_1_adr_3_Q,
      trd_host_cmd_1_adr_2_Q => trd_host_cmd_1_adr_2_Q,
      trd_host_cmd_1_adr_1_Q => trd_host_cmd_1_adr_1_Q,
      trd_host_cmd_1_adr_0_Q => trd_host_cmd_1_adr_0_Q,
      trd_host_cmd_2_adr_9_Q => NLW_amb_trd_host_cmd_2_adr_9_UNCONNECTED,
      trd_host_cmd_2_adr_8_Q => NLW_amb_trd_host_cmd_2_adr_8_UNCONNECTED,
      trd_host_cmd_2_adr_7_Q => NLW_amb_trd_host_cmd_2_adr_7_UNCONNECTED,
      trd_host_cmd_2_adr_6_Q => NLW_amb_trd_host_cmd_2_adr_6_UNCONNECTED,
      trd_host_cmd_2_adr_5_Q => NLW_amb_trd_host_cmd_2_adr_5_UNCONNECTED,
      trd_host_cmd_2_adr_4_Q => NLW_amb_trd_host_cmd_2_adr_4_UNCONNECTED,
      trd_host_cmd_2_adr_3_Q => NLW_amb_trd_host_cmd_2_adr_3_UNCONNECTED,
      trd_host_cmd_2_adr_2_Q => NLW_amb_trd_host_cmd_2_adr_2_UNCONNECTED,
      trd_host_cmd_2_adr_1_Q => NLW_amb_trd_host_cmd_2_adr_1_UNCONNECTED,
      trd_host_cmd_2_adr_0_Q => NLW_amb_trd_host_cmd_2_adr_0_UNCONNECTED,
      trd_host_cmd_3_adr_9_Q => NLW_amb_trd_host_cmd_3_adr_9_UNCONNECTED,
      trd_host_cmd_3_adr_8_Q => NLW_amb_trd_host_cmd_3_adr_8_UNCONNECTED,
      trd_host_cmd_3_adr_7_Q => NLW_amb_trd_host_cmd_3_adr_7_UNCONNECTED,
      trd_host_cmd_3_adr_6_Q => NLW_amb_trd_host_cmd_3_adr_6_UNCONNECTED,
      trd_host_cmd_3_adr_5_Q => NLW_amb_trd_host_cmd_3_adr_5_UNCONNECTED,
      trd_host_cmd_3_adr_4_Q => NLW_amb_trd_host_cmd_3_adr_4_UNCONNECTED,
      trd_host_cmd_3_adr_3_Q => NLW_amb_trd_host_cmd_3_adr_3_UNCONNECTED,
      trd_host_cmd_3_adr_2_Q => NLW_amb_trd_host_cmd_3_adr_2_UNCONNECTED,
      trd_host_cmd_3_adr_1_Q => NLW_amb_trd_host_cmd_3_adr_1_UNCONNECTED,
      trd_host_cmd_3_adr_0_Q => NLW_amb_trd_host_cmd_3_adr_0_UNCONNECTED,
      trd_host_cmd_4_adr_9_Q => NLW_amb_trd_host_cmd_4_adr_9_UNCONNECTED,
      trd_host_cmd_4_adr_8_Q => NLW_amb_trd_host_cmd_4_adr_8_UNCONNECTED,
      trd_host_cmd_4_adr_7_Q => NLW_amb_trd_host_cmd_4_adr_7_UNCONNECTED,
      trd_host_cmd_4_adr_6_Q => NLW_amb_trd_host_cmd_4_adr_6_UNCONNECTED,
      trd_host_cmd_4_adr_5_Q => NLW_amb_trd_host_cmd_4_adr_5_UNCONNECTED,
      trd_host_cmd_4_adr_4_Q => NLW_amb_trd_host_cmd_4_adr_4_UNCONNECTED,
      trd_host_cmd_4_adr_3_Q => NLW_amb_trd_host_cmd_4_adr_3_UNCONNECTED,
      trd_host_cmd_4_adr_2_Q => NLW_amb_trd_host_cmd_4_adr_2_UNCONNECTED,
      trd_host_cmd_4_adr_1_Q => NLW_amb_trd_host_cmd_4_adr_1_UNCONNECTED,
      trd_host_cmd_4_adr_0_Q => NLW_amb_trd_host_cmd_4_adr_0_UNCONNECTED,
      trd_host_adr(15) => NLW_amb_trd_host_adr_15_UNCONNECTED,
      trd_host_adr(14) => NLW_amb_trd_host_adr_14_UNCONNECTED,
      trd_host_adr(13) => NLW_amb_trd_host_adr_13_UNCONNECTED,
      trd_host_adr(12) => NLW_amb_trd_host_adr_12_UNCONNECTED,
      trd_host_adr(11) => NLW_amb_trd_host_adr_11_UNCONNECTED,
      trd_host_adr(10) => NLW_amb_trd_host_adr_10_UNCONNECTED,
      trd_host_adr(9) => NLW_amb_trd_host_adr_9_UNCONNECTED,
      trd_host_adr(8) => NLW_amb_trd_host_adr_8_UNCONNECTED,
      trd_host_adr(7) => NLW_amb_trd_host_adr_7_UNCONNECTED,
      trd_host_adr(6) => trd_host_adr(6),
      trd_host_adr(5) => trd_host_adr(5),
      trd_host_adr(4) => trd_host_adr(4),
      trd_host_adr(3) => trd_host_adr(3),
      trd_host_adr(2) => trd_host_adr(2),
      trd_host_adr(1) => trd_host_adr(1),
      trd_host_adr(0) => trd_host_adr(0),
      p(3) => NLW_amb_p_3_UNCONNECTED,
      p(2) => px(2),
      p(1) => NLW_amb_p_1_UNCONNECTED,
      trd_host_data(15, 63) => NLW_amb_trd_host_data_15_63_UNCONNECTED,
      trd_host_data(15, 62) => NLW_amb_trd_host_data_15_62_UNCONNECTED,
      trd_host_data(15, 61) => NLW_amb_trd_host_data_15_61_UNCONNECTED,
      trd_host_data(15, 60) => NLW_amb_trd_host_data_15_60_UNCONNECTED,
      trd_host_data(15, 59) => NLW_amb_trd_host_data_15_59_UNCONNECTED,
      trd_host_data(15, 58) => NLW_amb_trd_host_data_15_58_UNCONNECTED,
      trd_host_data(15, 57) => NLW_amb_trd_host_data_15_57_UNCONNECTED,
      trd_host_data(15, 56) => NLW_amb_trd_host_data_15_56_UNCONNECTED,
      trd_host_data(15, 55) => NLW_amb_trd_host_data_15_55_UNCONNECTED,
      trd_host_data(15, 54) => NLW_amb_trd_host_data_15_54_UNCONNECTED,
      trd_host_data(15, 53) => NLW_amb_trd_host_data_15_53_UNCONNECTED,
      trd_host_data(15, 52) => NLW_amb_trd_host_data_15_52_UNCONNECTED,
      trd_host_data(15, 51) => NLW_amb_trd_host_data_15_51_UNCONNECTED,
      trd_host_data(15, 50) => NLW_amb_trd_host_data_15_50_UNCONNECTED,
      trd_host_data(15, 49) => NLW_amb_trd_host_data_15_49_UNCONNECTED,
      trd_host_data(15, 48) => NLW_amb_trd_host_data_15_48_UNCONNECTED,
      trd_host_data(15, 47) => NLW_amb_trd_host_data_15_47_UNCONNECTED,
      trd_host_data(15, 46) => NLW_amb_trd_host_data_15_46_UNCONNECTED,
      trd_host_data(15, 45) => NLW_amb_trd_host_data_15_45_UNCONNECTED,
      trd_host_data(15, 44) => NLW_amb_trd_host_data_15_44_UNCONNECTED,
      trd_host_data(15, 43) => NLW_amb_trd_host_data_15_43_UNCONNECTED,
      trd_host_data(15, 42) => NLW_amb_trd_host_data_15_42_UNCONNECTED,
      trd_host_data(15, 41) => NLW_amb_trd_host_data_15_41_UNCONNECTED,
      trd_host_data(15, 40) => NLW_amb_trd_host_data_15_40_UNCONNECTED,
      trd_host_data(15, 39) => NLW_amb_trd_host_data_15_39_UNCONNECTED,
      trd_host_data(15, 38) => NLW_amb_trd_host_data_15_38_UNCONNECTED,
      trd_host_data(15, 37) => NLW_amb_trd_host_data_15_37_UNCONNECTED,
      trd_host_data(15, 36) => NLW_amb_trd_host_data_15_36_UNCONNECTED,
      trd_host_data(15, 35) => NLW_amb_trd_host_data_15_35_UNCONNECTED,
      trd_host_data(15, 34) => NLW_amb_trd_host_data_15_34_UNCONNECTED,
      trd_host_data(15, 33) => NLW_amb_trd_host_data_15_33_UNCONNECTED,
      trd_host_data(15, 32) => NLW_amb_trd_host_data_15_32_UNCONNECTED,
      trd_host_data(15, 31) => NLW_amb_trd_host_data_15_31_UNCONNECTED,
      trd_host_data(15, 30) => NLW_amb_trd_host_data_15_30_UNCONNECTED,
      trd_host_data(15, 29) => NLW_amb_trd_host_data_15_29_UNCONNECTED,
      trd_host_data(15, 28) => NLW_amb_trd_host_data_15_28_UNCONNECTED,
      trd_host_data(15, 27) => NLW_amb_trd_host_data_15_27_UNCONNECTED,
      trd_host_data(15, 26) => NLW_amb_trd_host_data_15_26_UNCONNECTED,
      trd_host_data(15, 25) => NLW_amb_trd_host_data_15_25_UNCONNECTED,
      trd_host_data(15, 24) => NLW_amb_trd_host_data_15_24_UNCONNECTED,
      trd_host_data(15, 23) => NLW_amb_trd_host_data_15_23_UNCONNECTED,
      trd_host_data(15, 22) => NLW_amb_trd_host_data_15_22_UNCONNECTED,
      trd_host_data(15, 21) => NLW_amb_trd_host_data_15_21_UNCONNECTED,
      trd_host_data(15, 20) => NLW_amb_trd_host_data_15_20_UNCONNECTED,
      trd_host_data(15, 19) => NLW_amb_trd_host_data_15_19_UNCONNECTED,
      trd_host_data(15, 18) => NLW_amb_trd_host_data_15_18_UNCONNECTED,
      trd_host_data(15, 17) => NLW_amb_trd_host_data_15_17_UNCONNECTED,
      trd_host_data(15, 16) => NLW_amb_trd_host_data_15_16_UNCONNECTED,
      trd_host_data(15, 15) => NLW_amb_trd_host_data_15_15_UNCONNECTED,
      trd_host_data(15, 14) => NLW_amb_trd_host_data_15_14_UNCONNECTED,
      trd_host_data(15, 13) => NLW_amb_trd_host_data_15_13_UNCONNECTED,
      trd_host_data(15, 12) => NLW_amb_trd_host_data_15_12_UNCONNECTED,
      trd_host_data(15, 11) => NLW_amb_trd_host_data_15_11_UNCONNECTED,
      trd_host_data(15, 10) => NLW_amb_trd_host_data_15_10_UNCONNECTED,
      trd_host_data(15, 9) => NLW_amb_trd_host_data_15_9_UNCONNECTED,
      trd_host_data(15, 8) => NLW_amb_trd_host_data_15_8_UNCONNECTED,
      trd_host_data(15, 7) => NLW_amb_trd_host_data_15_7_UNCONNECTED,
      trd_host_data(15, 6) => NLW_amb_trd_host_data_15_6_UNCONNECTED,
      trd_host_data(15, 5) => NLW_amb_trd_host_data_15_5_UNCONNECTED,
      trd_host_data(15, 4) => NLW_amb_trd_host_data_15_4_UNCONNECTED,
      trd_host_data(15, 3) => NLW_amb_trd_host_data_15_3_UNCONNECTED,
      trd_host_data(15, 2) => NLW_amb_trd_host_data_15_2_UNCONNECTED,
      trd_host_data(15, 1) => NLW_amb_trd_host_data_15_1_UNCONNECTED,
      trd_host_data(15, 0) => NLW_amb_trd_host_data_15_0_UNCONNECTED,
      trd_host_data(14, 63) => NLW_amb_trd_host_data_14_63_UNCONNECTED,
      trd_host_data(14, 62) => NLW_amb_trd_host_data_14_62_UNCONNECTED,
      trd_host_data(14, 61) => NLW_amb_trd_host_data_14_61_UNCONNECTED,
      trd_host_data(14, 60) => NLW_amb_trd_host_data_14_60_UNCONNECTED,
      trd_host_data(14, 59) => NLW_amb_trd_host_data_14_59_UNCONNECTED,
      trd_host_data(14, 58) => NLW_amb_trd_host_data_14_58_UNCONNECTED,
      trd_host_data(14, 57) => NLW_amb_trd_host_data_14_57_UNCONNECTED,
      trd_host_data(14, 56) => NLW_amb_trd_host_data_14_56_UNCONNECTED,
      trd_host_data(14, 55) => NLW_amb_trd_host_data_14_55_UNCONNECTED,
      trd_host_data(14, 54) => NLW_amb_trd_host_data_14_54_UNCONNECTED,
      trd_host_data(14, 53) => NLW_amb_trd_host_data_14_53_UNCONNECTED,
      trd_host_data(14, 52) => NLW_amb_trd_host_data_14_52_UNCONNECTED,
      trd_host_data(14, 51) => NLW_amb_trd_host_data_14_51_UNCONNECTED,
      trd_host_data(14, 50) => NLW_amb_trd_host_data_14_50_UNCONNECTED,
      trd_host_data(14, 49) => NLW_amb_trd_host_data_14_49_UNCONNECTED,
      trd_host_data(14, 48) => NLW_amb_trd_host_data_14_48_UNCONNECTED,
      trd_host_data(14, 47) => NLW_amb_trd_host_data_14_47_UNCONNECTED,
      trd_host_data(14, 46) => NLW_amb_trd_host_data_14_46_UNCONNECTED,
      trd_host_data(14, 45) => NLW_amb_trd_host_data_14_45_UNCONNECTED,
      trd_host_data(14, 44) => NLW_amb_trd_host_data_14_44_UNCONNECTED,
      trd_host_data(14, 43) => NLW_amb_trd_host_data_14_43_UNCONNECTED,
      trd_host_data(14, 42) => NLW_amb_trd_host_data_14_42_UNCONNECTED,
      trd_host_data(14, 41) => NLW_amb_trd_host_data_14_41_UNCONNECTED,
      trd_host_data(14, 40) => NLW_amb_trd_host_data_14_40_UNCONNECTED,
      trd_host_data(14, 39) => NLW_amb_trd_host_data_14_39_UNCONNECTED,
      trd_host_data(14, 38) => NLW_amb_trd_host_data_14_38_UNCONNECTED,
      trd_host_data(14, 37) => NLW_amb_trd_host_data_14_37_UNCONNECTED,
      trd_host_data(14, 36) => NLW_amb_trd_host_data_14_36_UNCONNECTED,
      trd_host_data(14, 35) => NLW_amb_trd_host_data_14_35_UNCONNECTED,
      trd_host_data(14, 34) => NLW_amb_trd_host_data_14_34_UNCONNECTED,
      trd_host_data(14, 33) => NLW_amb_trd_host_data_14_33_UNCONNECTED,
      trd_host_data(14, 32) => NLW_amb_trd_host_data_14_32_UNCONNECTED,
      trd_host_data(14, 31) => NLW_amb_trd_host_data_14_31_UNCONNECTED,
      trd_host_data(14, 30) => NLW_amb_trd_host_data_14_30_UNCONNECTED,
      trd_host_data(14, 29) => NLW_amb_trd_host_data_14_29_UNCONNECTED,
      trd_host_data(14, 28) => NLW_amb_trd_host_data_14_28_UNCONNECTED,
      trd_host_data(14, 27) => NLW_amb_trd_host_data_14_27_UNCONNECTED,
      trd_host_data(14, 26) => NLW_amb_trd_host_data_14_26_UNCONNECTED,
      trd_host_data(14, 25) => NLW_amb_trd_host_data_14_25_UNCONNECTED,
      trd_host_data(14, 24) => NLW_amb_trd_host_data_14_24_UNCONNECTED,
      trd_host_data(14, 23) => NLW_amb_trd_host_data_14_23_UNCONNECTED,
      trd_host_data(14, 22) => NLW_amb_trd_host_data_14_22_UNCONNECTED,
      trd_host_data(14, 21) => NLW_amb_trd_host_data_14_21_UNCONNECTED,
      trd_host_data(14, 20) => NLW_amb_trd_host_data_14_20_UNCONNECTED,
      trd_host_data(14, 19) => NLW_amb_trd_host_data_14_19_UNCONNECTED,
      trd_host_data(14, 18) => NLW_amb_trd_host_data_14_18_UNCONNECTED,
      trd_host_data(14, 17) => NLW_amb_trd_host_data_14_17_UNCONNECTED,
      trd_host_data(14, 16) => NLW_amb_trd_host_data_14_16_UNCONNECTED,
      trd_host_data(14, 15) => NLW_amb_trd_host_data_14_15_UNCONNECTED,
      trd_host_data(14, 14) => NLW_amb_trd_host_data_14_14_UNCONNECTED,
      trd_host_data(14, 13) => NLW_amb_trd_host_data_14_13_UNCONNECTED,
      trd_host_data(14, 12) => NLW_amb_trd_host_data_14_12_UNCONNECTED,
      trd_host_data(14, 11) => NLW_amb_trd_host_data_14_11_UNCONNECTED,
      trd_host_data(14, 10) => NLW_amb_trd_host_data_14_10_UNCONNECTED,
      trd_host_data(14, 9) => NLW_amb_trd_host_data_14_9_UNCONNECTED,
      trd_host_data(14, 8) => NLW_amb_trd_host_data_14_8_UNCONNECTED,
      trd_host_data(14, 7) => NLW_amb_trd_host_data_14_7_UNCONNECTED,
      trd_host_data(14, 6) => NLW_amb_trd_host_data_14_6_UNCONNECTED,
      trd_host_data(14, 5) => NLW_amb_trd_host_data_14_5_UNCONNECTED,
      trd_host_data(14, 4) => NLW_amb_trd_host_data_14_4_UNCONNECTED,
      trd_host_data(14, 3) => NLW_amb_trd_host_data_14_3_UNCONNECTED,
      trd_host_data(14, 2) => NLW_amb_trd_host_data_14_2_UNCONNECTED,
      trd_host_data(14, 1) => NLW_amb_trd_host_data_14_1_UNCONNECTED,
      trd_host_data(14, 0) => NLW_amb_trd_host_data_14_0_UNCONNECTED,
      trd_host_data(13, 63) => NLW_amb_trd_host_data_13_63_UNCONNECTED,
      trd_host_data(13, 62) => NLW_amb_trd_host_data_13_62_UNCONNECTED,
      trd_host_data(13, 61) => NLW_amb_trd_host_data_13_61_UNCONNECTED,
      trd_host_data(13, 60) => NLW_amb_trd_host_data_13_60_UNCONNECTED,
      trd_host_data(13, 59) => NLW_amb_trd_host_data_13_59_UNCONNECTED,
      trd_host_data(13, 58) => NLW_amb_trd_host_data_13_58_UNCONNECTED,
      trd_host_data(13, 57) => NLW_amb_trd_host_data_13_57_UNCONNECTED,
      trd_host_data(13, 56) => NLW_amb_trd_host_data_13_56_UNCONNECTED,
      trd_host_data(13, 55) => NLW_amb_trd_host_data_13_55_UNCONNECTED,
      trd_host_data(13, 54) => NLW_amb_trd_host_data_13_54_UNCONNECTED,
      trd_host_data(13, 53) => NLW_amb_trd_host_data_13_53_UNCONNECTED,
      trd_host_data(13, 52) => NLW_amb_trd_host_data_13_52_UNCONNECTED,
      trd_host_data(13, 51) => NLW_amb_trd_host_data_13_51_UNCONNECTED,
      trd_host_data(13, 50) => NLW_amb_trd_host_data_13_50_UNCONNECTED,
      trd_host_data(13, 49) => NLW_amb_trd_host_data_13_49_UNCONNECTED,
      trd_host_data(13, 48) => NLW_amb_trd_host_data_13_48_UNCONNECTED,
      trd_host_data(13, 47) => NLW_amb_trd_host_data_13_47_UNCONNECTED,
      trd_host_data(13, 46) => NLW_amb_trd_host_data_13_46_UNCONNECTED,
      trd_host_data(13, 45) => NLW_amb_trd_host_data_13_45_UNCONNECTED,
      trd_host_data(13, 44) => NLW_amb_trd_host_data_13_44_UNCONNECTED,
      trd_host_data(13, 43) => NLW_amb_trd_host_data_13_43_UNCONNECTED,
      trd_host_data(13, 42) => NLW_amb_trd_host_data_13_42_UNCONNECTED,
      trd_host_data(13, 41) => NLW_amb_trd_host_data_13_41_UNCONNECTED,
      trd_host_data(13, 40) => NLW_amb_trd_host_data_13_40_UNCONNECTED,
      trd_host_data(13, 39) => NLW_amb_trd_host_data_13_39_UNCONNECTED,
      trd_host_data(13, 38) => NLW_amb_trd_host_data_13_38_UNCONNECTED,
      trd_host_data(13, 37) => NLW_amb_trd_host_data_13_37_UNCONNECTED,
      trd_host_data(13, 36) => NLW_amb_trd_host_data_13_36_UNCONNECTED,
      trd_host_data(13, 35) => NLW_amb_trd_host_data_13_35_UNCONNECTED,
      trd_host_data(13, 34) => NLW_amb_trd_host_data_13_34_UNCONNECTED,
      trd_host_data(13, 33) => NLW_amb_trd_host_data_13_33_UNCONNECTED,
      trd_host_data(13, 32) => NLW_amb_trd_host_data_13_32_UNCONNECTED,
      trd_host_data(13, 31) => NLW_amb_trd_host_data_13_31_UNCONNECTED,
      trd_host_data(13, 30) => NLW_amb_trd_host_data_13_30_UNCONNECTED,
      trd_host_data(13, 29) => NLW_amb_trd_host_data_13_29_UNCONNECTED,
      trd_host_data(13, 28) => NLW_amb_trd_host_data_13_28_UNCONNECTED,
      trd_host_data(13, 27) => NLW_amb_trd_host_data_13_27_UNCONNECTED,
      trd_host_data(13, 26) => NLW_amb_trd_host_data_13_26_UNCONNECTED,
      trd_host_data(13, 25) => NLW_amb_trd_host_data_13_25_UNCONNECTED,
      trd_host_data(13, 24) => NLW_amb_trd_host_data_13_24_UNCONNECTED,
      trd_host_data(13, 23) => NLW_amb_trd_host_data_13_23_UNCONNECTED,
      trd_host_data(13, 22) => NLW_amb_trd_host_data_13_22_UNCONNECTED,
      trd_host_data(13, 21) => NLW_amb_trd_host_data_13_21_UNCONNECTED,
      trd_host_data(13, 20) => NLW_amb_trd_host_data_13_20_UNCONNECTED,
      trd_host_data(13, 19) => NLW_amb_trd_host_data_13_19_UNCONNECTED,
      trd_host_data(13, 18) => NLW_amb_trd_host_data_13_18_UNCONNECTED,
      trd_host_data(13, 17) => NLW_amb_trd_host_data_13_17_UNCONNECTED,
      trd_host_data(13, 16) => NLW_amb_trd_host_data_13_16_UNCONNECTED,
      trd_host_data(13, 15) => NLW_amb_trd_host_data_13_15_UNCONNECTED,
      trd_host_data(13, 14) => NLW_amb_trd_host_data_13_14_UNCONNECTED,
      trd_host_data(13, 13) => NLW_amb_trd_host_data_13_13_UNCONNECTED,
      trd_host_data(13, 12) => NLW_amb_trd_host_data_13_12_UNCONNECTED,
      trd_host_data(13, 11) => NLW_amb_trd_host_data_13_11_UNCONNECTED,
      trd_host_data(13, 10) => NLW_amb_trd_host_data_13_10_UNCONNECTED,
      trd_host_data(13, 9) => NLW_amb_trd_host_data_13_9_UNCONNECTED,
      trd_host_data(13, 8) => NLW_amb_trd_host_data_13_8_UNCONNECTED,
      trd_host_data(13, 7) => NLW_amb_trd_host_data_13_7_UNCONNECTED,
      trd_host_data(13, 6) => NLW_amb_trd_host_data_13_6_UNCONNECTED,
      trd_host_data(13, 5) => NLW_amb_trd_host_data_13_5_UNCONNECTED,
      trd_host_data(13, 4) => NLW_amb_trd_host_data_13_4_UNCONNECTED,
      trd_host_data(13, 3) => NLW_amb_trd_host_data_13_3_UNCONNECTED,
      trd_host_data(13, 2) => NLW_amb_trd_host_data_13_2_UNCONNECTED,
      trd_host_data(13, 1) => NLW_amb_trd_host_data_13_1_UNCONNECTED,
      trd_host_data(13, 0) => NLW_amb_trd_host_data_13_0_UNCONNECTED,
      trd_host_data(12, 63) => NLW_amb_trd_host_data_12_63_UNCONNECTED,
      trd_host_data(12, 62) => NLW_amb_trd_host_data_12_62_UNCONNECTED,
      trd_host_data(12, 61) => NLW_amb_trd_host_data_12_61_UNCONNECTED,
      trd_host_data(12, 60) => NLW_amb_trd_host_data_12_60_UNCONNECTED,
      trd_host_data(12, 59) => NLW_amb_trd_host_data_12_59_UNCONNECTED,
      trd_host_data(12, 58) => NLW_amb_trd_host_data_12_58_UNCONNECTED,
      trd_host_data(12, 57) => NLW_amb_trd_host_data_12_57_UNCONNECTED,
      trd_host_data(12, 56) => NLW_amb_trd_host_data_12_56_UNCONNECTED,
      trd_host_data(12, 55) => NLW_amb_trd_host_data_12_55_UNCONNECTED,
      trd_host_data(12, 54) => NLW_amb_trd_host_data_12_54_UNCONNECTED,
      trd_host_data(12, 53) => NLW_amb_trd_host_data_12_53_UNCONNECTED,
      trd_host_data(12, 52) => NLW_amb_trd_host_data_12_52_UNCONNECTED,
      trd_host_data(12, 51) => NLW_amb_trd_host_data_12_51_UNCONNECTED,
      trd_host_data(12, 50) => NLW_amb_trd_host_data_12_50_UNCONNECTED,
      trd_host_data(12, 49) => NLW_amb_trd_host_data_12_49_UNCONNECTED,
      trd_host_data(12, 48) => NLW_amb_trd_host_data_12_48_UNCONNECTED,
      trd_host_data(12, 47) => NLW_amb_trd_host_data_12_47_UNCONNECTED,
      trd_host_data(12, 46) => NLW_amb_trd_host_data_12_46_UNCONNECTED,
      trd_host_data(12, 45) => NLW_amb_trd_host_data_12_45_UNCONNECTED,
      trd_host_data(12, 44) => NLW_amb_trd_host_data_12_44_UNCONNECTED,
      trd_host_data(12, 43) => NLW_amb_trd_host_data_12_43_UNCONNECTED,
      trd_host_data(12, 42) => NLW_amb_trd_host_data_12_42_UNCONNECTED,
      trd_host_data(12, 41) => NLW_amb_trd_host_data_12_41_UNCONNECTED,
      trd_host_data(12, 40) => NLW_amb_trd_host_data_12_40_UNCONNECTED,
      trd_host_data(12, 39) => NLW_amb_trd_host_data_12_39_UNCONNECTED,
      trd_host_data(12, 38) => NLW_amb_trd_host_data_12_38_UNCONNECTED,
      trd_host_data(12, 37) => NLW_amb_trd_host_data_12_37_UNCONNECTED,
      trd_host_data(12, 36) => NLW_amb_trd_host_data_12_36_UNCONNECTED,
      trd_host_data(12, 35) => NLW_amb_trd_host_data_12_35_UNCONNECTED,
      trd_host_data(12, 34) => NLW_amb_trd_host_data_12_34_UNCONNECTED,
      trd_host_data(12, 33) => NLW_amb_trd_host_data_12_33_UNCONNECTED,
      trd_host_data(12, 32) => NLW_amb_trd_host_data_12_32_UNCONNECTED,
      trd_host_data(12, 31) => NLW_amb_trd_host_data_12_31_UNCONNECTED,
      trd_host_data(12, 30) => NLW_amb_trd_host_data_12_30_UNCONNECTED,
      trd_host_data(12, 29) => NLW_amb_trd_host_data_12_29_UNCONNECTED,
      trd_host_data(12, 28) => NLW_amb_trd_host_data_12_28_UNCONNECTED,
      trd_host_data(12, 27) => NLW_amb_trd_host_data_12_27_UNCONNECTED,
      trd_host_data(12, 26) => NLW_amb_trd_host_data_12_26_UNCONNECTED,
      trd_host_data(12, 25) => NLW_amb_trd_host_data_12_25_UNCONNECTED,
      trd_host_data(12, 24) => NLW_amb_trd_host_data_12_24_UNCONNECTED,
      trd_host_data(12, 23) => NLW_amb_trd_host_data_12_23_UNCONNECTED,
      trd_host_data(12, 22) => NLW_amb_trd_host_data_12_22_UNCONNECTED,
      trd_host_data(12, 21) => NLW_amb_trd_host_data_12_21_UNCONNECTED,
      trd_host_data(12, 20) => NLW_amb_trd_host_data_12_20_UNCONNECTED,
      trd_host_data(12, 19) => NLW_amb_trd_host_data_12_19_UNCONNECTED,
      trd_host_data(12, 18) => NLW_amb_trd_host_data_12_18_UNCONNECTED,
      trd_host_data(12, 17) => NLW_amb_trd_host_data_12_17_UNCONNECTED,
      trd_host_data(12, 16) => NLW_amb_trd_host_data_12_16_UNCONNECTED,
      trd_host_data(12, 15) => NLW_amb_trd_host_data_12_15_UNCONNECTED,
      trd_host_data(12, 14) => NLW_amb_trd_host_data_12_14_UNCONNECTED,
      trd_host_data(12, 13) => NLW_amb_trd_host_data_12_13_UNCONNECTED,
      trd_host_data(12, 12) => NLW_amb_trd_host_data_12_12_UNCONNECTED,
      trd_host_data(12, 11) => NLW_amb_trd_host_data_12_11_UNCONNECTED,
      trd_host_data(12, 10) => NLW_amb_trd_host_data_12_10_UNCONNECTED,
      trd_host_data(12, 9) => NLW_amb_trd_host_data_12_9_UNCONNECTED,
      trd_host_data(12, 8) => NLW_amb_trd_host_data_12_8_UNCONNECTED,
      trd_host_data(12, 7) => NLW_amb_trd_host_data_12_7_UNCONNECTED,
      trd_host_data(12, 6) => NLW_amb_trd_host_data_12_6_UNCONNECTED,
      trd_host_data(12, 5) => NLW_amb_trd_host_data_12_5_UNCONNECTED,
      trd_host_data(12, 4) => NLW_amb_trd_host_data_12_4_UNCONNECTED,
      trd_host_data(12, 3) => NLW_amb_trd_host_data_12_3_UNCONNECTED,
      trd_host_data(12, 2) => NLW_amb_trd_host_data_12_2_UNCONNECTED,
      trd_host_data(12, 1) => NLW_amb_trd_host_data_12_1_UNCONNECTED,
      trd_host_data(12, 0) => NLW_amb_trd_host_data_12_0_UNCONNECTED,
      trd_host_data(11, 63) => NLW_amb_trd_host_data_11_63_UNCONNECTED,
      trd_host_data(11, 62) => NLW_amb_trd_host_data_11_62_UNCONNECTED,
      trd_host_data(11, 61) => NLW_amb_trd_host_data_11_61_UNCONNECTED,
      trd_host_data(11, 60) => NLW_amb_trd_host_data_11_60_UNCONNECTED,
      trd_host_data(11, 59) => NLW_amb_trd_host_data_11_59_UNCONNECTED,
      trd_host_data(11, 58) => NLW_amb_trd_host_data_11_58_UNCONNECTED,
      trd_host_data(11, 57) => NLW_amb_trd_host_data_11_57_UNCONNECTED,
      trd_host_data(11, 56) => NLW_amb_trd_host_data_11_56_UNCONNECTED,
      trd_host_data(11, 55) => NLW_amb_trd_host_data_11_55_UNCONNECTED,
      trd_host_data(11, 54) => NLW_amb_trd_host_data_11_54_UNCONNECTED,
      trd_host_data(11, 53) => NLW_amb_trd_host_data_11_53_UNCONNECTED,
      trd_host_data(11, 52) => NLW_amb_trd_host_data_11_52_UNCONNECTED,
      trd_host_data(11, 51) => NLW_amb_trd_host_data_11_51_UNCONNECTED,
      trd_host_data(11, 50) => NLW_amb_trd_host_data_11_50_UNCONNECTED,
      trd_host_data(11, 49) => NLW_amb_trd_host_data_11_49_UNCONNECTED,
      trd_host_data(11, 48) => NLW_amb_trd_host_data_11_48_UNCONNECTED,
      trd_host_data(11, 47) => NLW_amb_trd_host_data_11_47_UNCONNECTED,
      trd_host_data(11, 46) => NLW_amb_trd_host_data_11_46_UNCONNECTED,
      trd_host_data(11, 45) => NLW_amb_trd_host_data_11_45_UNCONNECTED,
      trd_host_data(11, 44) => NLW_amb_trd_host_data_11_44_UNCONNECTED,
      trd_host_data(11, 43) => NLW_amb_trd_host_data_11_43_UNCONNECTED,
      trd_host_data(11, 42) => NLW_amb_trd_host_data_11_42_UNCONNECTED,
      trd_host_data(11, 41) => NLW_amb_trd_host_data_11_41_UNCONNECTED,
      trd_host_data(11, 40) => NLW_amb_trd_host_data_11_40_UNCONNECTED,
      trd_host_data(11, 39) => NLW_amb_trd_host_data_11_39_UNCONNECTED,
      trd_host_data(11, 38) => NLW_amb_trd_host_data_11_38_UNCONNECTED,
      trd_host_data(11, 37) => NLW_amb_trd_host_data_11_37_UNCONNECTED,
      trd_host_data(11, 36) => NLW_amb_trd_host_data_11_36_UNCONNECTED,
      trd_host_data(11, 35) => NLW_amb_trd_host_data_11_35_UNCONNECTED,
      trd_host_data(11, 34) => NLW_amb_trd_host_data_11_34_UNCONNECTED,
      trd_host_data(11, 33) => NLW_amb_trd_host_data_11_33_UNCONNECTED,
      trd_host_data(11, 32) => NLW_amb_trd_host_data_11_32_UNCONNECTED,
      trd_host_data(11, 31) => NLW_amb_trd_host_data_11_31_UNCONNECTED,
      trd_host_data(11, 30) => NLW_amb_trd_host_data_11_30_UNCONNECTED,
      trd_host_data(11, 29) => NLW_amb_trd_host_data_11_29_UNCONNECTED,
      trd_host_data(11, 28) => NLW_amb_trd_host_data_11_28_UNCONNECTED,
      trd_host_data(11, 27) => NLW_amb_trd_host_data_11_27_UNCONNECTED,
      trd_host_data(11, 26) => NLW_amb_trd_host_data_11_26_UNCONNECTED,
      trd_host_data(11, 25) => NLW_amb_trd_host_data_11_25_UNCONNECTED,
      trd_host_data(11, 24) => NLW_amb_trd_host_data_11_24_UNCONNECTED,
      trd_host_data(11, 23) => NLW_amb_trd_host_data_11_23_UNCONNECTED,
      trd_host_data(11, 22) => NLW_amb_trd_host_data_11_22_UNCONNECTED,
      trd_host_data(11, 21) => NLW_amb_trd_host_data_11_21_UNCONNECTED,
      trd_host_data(11, 20) => NLW_amb_trd_host_data_11_20_UNCONNECTED,
      trd_host_data(11, 19) => NLW_amb_trd_host_data_11_19_UNCONNECTED,
      trd_host_data(11, 18) => NLW_amb_trd_host_data_11_18_UNCONNECTED,
      trd_host_data(11, 17) => NLW_amb_trd_host_data_11_17_UNCONNECTED,
      trd_host_data(11, 16) => NLW_amb_trd_host_data_11_16_UNCONNECTED,
      trd_host_data(11, 15) => NLW_amb_trd_host_data_11_15_UNCONNECTED,
      trd_host_data(11, 14) => NLW_amb_trd_host_data_11_14_UNCONNECTED,
      trd_host_data(11, 13) => NLW_amb_trd_host_data_11_13_UNCONNECTED,
      trd_host_data(11, 12) => NLW_amb_trd_host_data_11_12_UNCONNECTED,
      trd_host_data(11, 11) => NLW_amb_trd_host_data_11_11_UNCONNECTED,
      trd_host_data(11, 10) => NLW_amb_trd_host_data_11_10_UNCONNECTED,
      trd_host_data(11, 9) => NLW_amb_trd_host_data_11_9_UNCONNECTED,
      trd_host_data(11, 8) => NLW_amb_trd_host_data_11_8_UNCONNECTED,
      trd_host_data(11, 7) => NLW_amb_trd_host_data_11_7_UNCONNECTED,
      trd_host_data(11, 6) => NLW_amb_trd_host_data_11_6_UNCONNECTED,
      trd_host_data(11, 5) => NLW_amb_trd_host_data_11_5_UNCONNECTED,
      trd_host_data(11, 4) => NLW_amb_trd_host_data_11_4_UNCONNECTED,
      trd_host_data(11, 3) => NLW_amb_trd_host_data_11_3_UNCONNECTED,
      trd_host_data(11, 2) => NLW_amb_trd_host_data_11_2_UNCONNECTED,
      trd_host_data(11, 1) => NLW_amb_trd_host_data_11_1_UNCONNECTED,
      trd_host_data(11, 0) => NLW_amb_trd_host_data_11_0_UNCONNECTED,
      trd_host_data(10, 63) => NLW_amb_trd_host_data_10_63_UNCONNECTED,
      trd_host_data(10, 62) => NLW_amb_trd_host_data_10_62_UNCONNECTED,
      trd_host_data(10, 61) => NLW_amb_trd_host_data_10_61_UNCONNECTED,
      trd_host_data(10, 60) => NLW_amb_trd_host_data_10_60_UNCONNECTED,
      trd_host_data(10, 59) => NLW_amb_trd_host_data_10_59_UNCONNECTED,
      trd_host_data(10, 58) => NLW_amb_trd_host_data_10_58_UNCONNECTED,
      trd_host_data(10, 57) => NLW_amb_trd_host_data_10_57_UNCONNECTED,
      trd_host_data(10, 56) => NLW_amb_trd_host_data_10_56_UNCONNECTED,
      trd_host_data(10, 55) => NLW_amb_trd_host_data_10_55_UNCONNECTED,
      trd_host_data(10, 54) => NLW_amb_trd_host_data_10_54_UNCONNECTED,
      trd_host_data(10, 53) => NLW_amb_trd_host_data_10_53_UNCONNECTED,
      trd_host_data(10, 52) => NLW_amb_trd_host_data_10_52_UNCONNECTED,
      trd_host_data(10, 51) => NLW_amb_trd_host_data_10_51_UNCONNECTED,
      trd_host_data(10, 50) => NLW_amb_trd_host_data_10_50_UNCONNECTED,
      trd_host_data(10, 49) => NLW_amb_trd_host_data_10_49_UNCONNECTED,
      trd_host_data(10, 48) => NLW_amb_trd_host_data_10_48_UNCONNECTED,
      trd_host_data(10, 47) => NLW_amb_trd_host_data_10_47_UNCONNECTED,
      trd_host_data(10, 46) => NLW_amb_trd_host_data_10_46_UNCONNECTED,
      trd_host_data(10, 45) => NLW_amb_trd_host_data_10_45_UNCONNECTED,
      trd_host_data(10, 44) => NLW_amb_trd_host_data_10_44_UNCONNECTED,
      trd_host_data(10, 43) => NLW_amb_trd_host_data_10_43_UNCONNECTED,
      trd_host_data(10, 42) => NLW_amb_trd_host_data_10_42_UNCONNECTED,
      trd_host_data(10, 41) => NLW_amb_trd_host_data_10_41_UNCONNECTED,
      trd_host_data(10, 40) => NLW_amb_trd_host_data_10_40_UNCONNECTED,
      trd_host_data(10, 39) => NLW_amb_trd_host_data_10_39_UNCONNECTED,
      trd_host_data(10, 38) => NLW_amb_trd_host_data_10_38_UNCONNECTED,
      trd_host_data(10, 37) => NLW_amb_trd_host_data_10_37_UNCONNECTED,
      trd_host_data(10, 36) => NLW_amb_trd_host_data_10_36_UNCONNECTED,
      trd_host_data(10, 35) => NLW_amb_trd_host_data_10_35_UNCONNECTED,
      trd_host_data(10, 34) => NLW_amb_trd_host_data_10_34_UNCONNECTED,
      trd_host_data(10, 33) => NLW_amb_trd_host_data_10_33_UNCONNECTED,
      trd_host_data(10, 32) => NLW_amb_trd_host_data_10_32_UNCONNECTED,
      trd_host_data(10, 31) => NLW_amb_trd_host_data_10_31_UNCONNECTED,
      trd_host_data(10, 30) => NLW_amb_trd_host_data_10_30_UNCONNECTED,
      trd_host_data(10, 29) => NLW_amb_trd_host_data_10_29_UNCONNECTED,
      trd_host_data(10, 28) => NLW_amb_trd_host_data_10_28_UNCONNECTED,
      trd_host_data(10, 27) => NLW_amb_trd_host_data_10_27_UNCONNECTED,
      trd_host_data(10, 26) => NLW_amb_trd_host_data_10_26_UNCONNECTED,
      trd_host_data(10, 25) => NLW_amb_trd_host_data_10_25_UNCONNECTED,
      trd_host_data(10, 24) => NLW_amb_trd_host_data_10_24_UNCONNECTED,
      trd_host_data(10, 23) => NLW_amb_trd_host_data_10_23_UNCONNECTED,
      trd_host_data(10, 22) => NLW_amb_trd_host_data_10_22_UNCONNECTED,
      trd_host_data(10, 21) => NLW_amb_trd_host_data_10_21_UNCONNECTED,
      trd_host_data(10, 20) => NLW_amb_trd_host_data_10_20_UNCONNECTED,
      trd_host_data(10, 19) => NLW_amb_trd_host_data_10_19_UNCONNECTED,
      trd_host_data(10, 18) => NLW_amb_trd_host_data_10_18_UNCONNECTED,
      trd_host_data(10, 17) => NLW_amb_trd_host_data_10_17_UNCONNECTED,
      trd_host_data(10, 16) => NLW_amb_trd_host_data_10_16_UNCONNECTED,
      trd_host_data(10, 15) => NLW_amb_trd_host_data_10_15_UNCONNECTED,
      trd_host_data(10, 14) => NLW_amb_trd_host_data_10_14_UNCONNECTED,
      trd_host_data(10, 13) => NLW_amb_trd_host_data_10_13_UNCONNECTED,
      trd_host_data(10, 12) => NLW_amb_trd_host_data_10_12_UNCONNECTED,
      trd_host_data(10, 11) => NLW_amb_trd_host_data_10_11_UNCONNECTED,
      trd_host_data(10, 10) => NLW_amb_trd_host_data_10_10_UNCONNECTED,
      trd_host_data(10, 9) => NLW_amb_trd_host_data_10_9_UNCONNECTED,
      trd_host_data(10, 8) => NLW_amb_trd_host_data_10_8_UNCONNECTED,
      trd_host_data(10, 7) => NLW_amb_trd_host_data_10_7_UNCONNECTED,
      trd_host_data(10, 6) => NLW_amb_trd_host_data_10_6_UNCONNECTED,
      trd_host_data(10, 5) => NLW_amb_trd_host_data_10_5_UNCONNECTED,
      trd_host_data(10, 4) => NLW_amb_trd_host_data_10_4_UNCONNECTED,
      trd_host_data(10, 3) => NLW_amb_trd_host_data_10_3_UNCONNECTED,
      trd_host_data(10, 2) => NLW_amb_trd_host_data_10_2_UNCONNECTED,
      trd_host_data(10, 1) => NLW_amb_trd_host_data_10_1_UNCONNECTED,
      trd_host_data(10, 0) => NLW_amb_trd_host_data_10_0_UNCONNECTED,
      trd_host_data(9, 63) => NLW_amb_trd_host_data_9_63_UNCONNECTED,
      trd_host_data(9, 62) => NLW_amb_trd_host_data_9_62_UNCONNECTED,
      trd_host_data(9, 61) => NLW_amb_trd_host_data_9_61_UNCONNECTED,
      trd_host_data(9, 60) => NLW_amb_trd_host_data_9_60_UNCONNECTED,
      trd_host_data(9, 59) => NLW_amb_trd_host_data_9_59_UNCONNECTED,
      trd_host_data(9, 58) => NLW_amb_trd_host_data_9_58_UNCONNECTED,
      trd_host_data(9, 57) => NLW_amb_trd_host_data_9_57_UNCONNECTED,
      trd_host_data(9, 56) => NLW_amb_trd_host_data_9_56_UNCONNECTED,
      trd_host_data(9, 55) => NLW_amb_trd_host_data_9_55_UNCONNECTED,
      trd_host_data(9, 54) => NLW_amb_trd_host_data_9_54_UNCONNECTED,
      trd_host_data(9, 53) => NLW_amb_trd_host_data_9_53_UNCONNECTED,
      trd_host_data(9, 52) => NLW_amb_trd_host_data_9_52_UNCONNECTED,
      trd_host_data(9, 51) => NLW_amb_trd_host_data_9_51_UNCONNECTED,
      trd_host_data(9, 50) => NLW_amb_trd_host_data_9_50_UNCONNECTED,
      trd_host_data(9, 49) => NLW_amb_trd_host_data_9_49_UNCONNECTED,
      trd_host_data(9, 48) => NLW_amb_trd_host_data_9_48_UNCONNECTED,
      trd_host_data(9, 47) => NLW_amb_trd_host_data_9_47_UNCONNECTED,
      trd_host_data(9, 46) => NLW_amb_trd_host_data_9_46_UNCONNECTED,
      trd_host_data(9, 45) => NLW_amb_trd_host_data_9_45_UNCONNECTED,
      trd_host_data(9, 44) => NLW_amb_trd_host_data_9_44_UNCONNECTED,
      trd_host_data(9, 43) => NLW_amb_trd_host_data_9_43_UNCONNECTED,
      trd_host_data(9, 42) => NLW_amb_trd_host_data_9_42_UNCONNECTED,
      trd_host_data(9, 41) => NLW_amb_trd_host_data_9_41_UNCONNECTED,
      trd_host_data(9, 40) => NLW_amb_trd_host_data_9_40_UNCONNECTED,
      trd_host_data(9, 39) => NLW_amb_trd_host_data_9_39_UNCONNECTED,
      trd_host_data(9, 38) => NLW_amb_trd_host_data_9_38_UNCONNECTED,
      trd_host_data(9, 37) => NLW_amb_trd_host_data_9_37_UNCONNECTED,
      trd_host_data(9, 36) => NLW_amb_trd_host_data_9_36_UNCONNECTED,
      trd_host_data(9, 35) => NLW_amb_trd_host_data_9_35_UNCONNECTED,
      trd_host_data(9, 34) => NLW_amb_trd_host_data_9_34_UNCONNECTED,
      trd_host_data(9, 33) => NLW_amb_trd_host_data_9_33_UNCONNECTED,
      trd_host_data(9, 32) => NLW_amb_trd_host_data_9_32_UNCONNECTED,
      trd_host_data(9, 31) => NLW_amb_trd_host_data_9_31_UNCONNECTED,
      trd_host_data(9, 30) => NLW_amb_trd_host_data_9_30_UNCONNECTED,
      trd_host_data(9, 29) => NLW_amb_trd_host_data_9_29_UNCONNECTED,
      trd_host_data(9, 28) => NLW_amb_trd_host_data_9_28_UNCONNECTED,
      trd_host_data(9, 27) => NLW_amb_trd_host_data_9_27_UNCONNECTED,
      trd_host_data(9, 26) => NLW_amb_trd_host_data_9_26_UNCONNECTED,
      trd_host_data(9, 25) => NLW_amb_trd_host_data_9_25_UNCONNECTED,
      trd_host_data(9, 24) => NLW_amb_trd_host_data_9_24_UNCONNECTED,
      trd_host_data(9, 23) => NLW_amb_trd_host_data_9_23_UNCONNECTED,
      trd_host_data(9, 22) => NLW_amb_trd_host_data_9_22_UNCONNECTED,
      trd_host_data(9, 21) => NLW_amb_trd_host_data_9_21_UNCONNECTED,
      trd_host_data(9, 20) => NLW_amb_trd_host_data_9_20_UNCONNECTED,
      trd_host_data(9, 19) => NLW_amb_trd_host_data_9_19_UNCONNECTED,
      trd_host_data(9, 18) => NLW_amb_trd_host_data_9_18_UNCONNECTED,
      trd_host_data(9, 17) => NLW_amb_trd_host_data_9_17_UNCONNECTED,
      trd_host_data(9, 16) => NLW_amb_trd_host_data_9_16_UNCONNECTED,
      trd_host_data(9, 15) => NLW_amb_trd_host_data_9_15_UNCONNECTED,
      trd_host_data(9, 14) => NLW_amb_trd_host_data_9_14_UNCONNECTED,
      trd_host_data(9, 13) => NLW_amb_trd_host_data_9_13_UNCONNECTED,
      trd_host_data(9, 12) => NLW_amb_trd_host_data_9_12_UNCONNECTED,
      trd_host_data(9, 11) => NLW_amb_trd_host_data_9_11_UNCONNECTED,
      trd_host_data(9, 10) => NLW_amb_trd_host_data_9_10_UNCONNECTED,
      trd_host_data(9, 9) => NLW_amb_trd_host_data_9_9_UNCONNECTED,
      trd_host_data(9, 8) => NLW_amb_trd_host_data_9_8_UNCONNECTED,
      trd_host_data(9, 7) => NLW_amb_trd_host_data_9_7_UNCONNECTED,
      trd_host_data(9, 6) => NLW_amb_trd_host_data_9_6_UNCONNECTED,
      trd_host_data(9, 5) => NLW_amb_trd_host_data_9_5_UNCONNECTED,
      trd_host_data(9, 4) => NLW_amb_trd_host_data_9_4_UNCONNECTED,
      trd_host_data(9, 3) => NLW_amb_trd_host_data_9_3_UNCONNECTED,
      trd_host_data(9, 2) => NLW_amb_trd_host_data_9_2_UNCONNECTED,
      trd_host_data(9, 1) => NLW_amb_trd_host_data_9_1_UNCONNECTED,
      trd_host_data(9, 0) => NLW_amb_trd_host_data_9_0_UNCONNECTED,
      trd_host_data(8, 63) => NLW_amb_trd_host_data_8_63_UNCONNECTED,
      trd_host_data(8, 62) => NLW_amb_trd_host_data_8_62_UNCONNECTED,
      trd_host_data(8, 61) => NLW_amb_trd_host_data_8_61_UNCONNECTED,
      trd_host_data(8, 60) => NLW_amb_trd_host_data_8_60_UNCONNECTED,
      trd_host_data(8, 59) => NLW_amb_trd_host_data_8_59_UNCONNECTED,
      trd_host_data(8, 58) => NLW_amb_trd_host_data_8_58_UNCONNECTED,
      trd_host_data(8, 57) => NLW_amb_trd_host_data_8_57_UNCONNECTED,
      trd_host_data(8, 56) => NLW_amb_trd_host_data_8_56_UNCONNECTED,
      trd_host_data(8, 55) => NLW_amb_trd_host_data_8_55_UNCONNECTED,
      trd_host_data(8, 54) => NLW_amb_trd_host_data_8_54_UNCONNECTED,
      trd_host_data(8, 53) => NLW_amb_trd_host_data_8_53_UNCONNECTED,
      trd_host_data(8, 52) => NLW_amb_trd_host_data_8_52_UNCONNECTED,
      trd_host_data(8, 51) => NLW_amb_trd_host_data_8_51_UNCONNECTED,
      trd_host_data(8, 50) => NLW_amb_trd_host_data_8_50_UNCONNECTED,
      trd_host_data(8, 49) => NLW_amb_trd_host_data_8_49_UNCONNECTED,
      trd_host_data(8, 48) => NLW_amb_trd_host_data_8_48_UNCONNECTED,
      trd_host_data(8, 47) => NLW_amb_trd_host_data_8_47_UNCONNECTED,
      trd_host_data(8, 46) => NLW_amb_trd_host_data_8_46_UNCONNECTED,
      trd_host_data(8, 45) => NLW_amb_trd_host_data_8_45_UNCONNECTED,
      trd_host_data(8, 44) => NLW_amb_trd_host_data_8_44_UNCONNECTED,
      trd_host_data(8, 43) => NLW_amb_trd_host_data_8_43_UNCONNECTED,
      trd_host_data(8, 42) => NLW_amb_trd_host_data_8_42_UNCONNECTED,
      trd_host_data(8, 41) => NLW_amb_trd_host_data_8_41_UNCONNECTED,
      trd_host_data(8, 40) => NLW_amb_trd_host_data_8_40_UNCONNECTED,
      trd_host_data(8, 39) => NLW_amb_trd_host_data_8_39_UNCONNECTED,
      trd_host_data(8, 38) => NLW_amb_trd_host_data_8_38_UNCONNECTED,
      trd_host_data(8, 37) => NLW_amb_trd_host_data_8_37_UNCONNECTED,
      trd_host_data(8, 36) => NLW_amb_trd_host_data_8_36_UNCONNECTED,
      trd_host_data(8, 35) => NLW_amb_trd_host_data_8_35_UNCONNECTED,
      trd_host_data(8, 34) => NLW_amb_trd_host_data_8_34_UNCONNECTED,
      trd_host_data(8, 33) => NLW_amb_trd_host_data_8_33_UNCONNECTED,
      trd_host_data(8, 32) => NLW_amb_trd_host_data_8_32_UNCONNECTED,
      trd_host_data(8, 31) => NLW_amb_trd_host_data_8_31_UNCONNECTED,
      trd_host_data(8, 30) => NLW_amb_trd_host_data_8_30_UNCONNECTED,
      trd_host_data(8, 29) => NLW_amb_trd_host_data_8_29_UNCONNECTED,
      trd_host_data(8, 28) => NLW_amb_trd_host_data_8_28_UNCONNECTED,
      trd_host_data(8, 27) => NLW_amb_trd_host_data_8_27_UNCONNECTED,
      trd_host_data(8, 26) => NLW_amb_trd_host_data_8_26_UNCONNECTED,
      trd_host_data(8, 25) => NLW_amb_trd_host_data_8_25_UNCONNECTED,
      trd_host_data(8, 24) => NLW_amb_trd_host_data_8_24_UNCONNECTED,
      trd_host_data(8, 23) => NLW_amb_trd_host_data_8_23_UNCONNECTED,
      trd_host_data(8, 22) => NLW_amb_trd_host_data_8_22_UNCONNECTED,
      trd_host_data(8, 21) => NLW_amb_trd_host_data_8_21_UNCONNECTED,
      trd_host_data(8, 20) => NLW_amb_trd_host_data_8_20_UNCONNECTED,
      trd_host_data(8, 19) => NLW_amb_trd_host_data_8_19_UNCONNECTED,
      trd_host_data(8, 18) => NLW_amb_trd_host_data_8_18_UNCONNECTED,
      trd_host_data(8, 17) => NLW_amb_trd_host_data_8_17_UNCONNECTED,
      trd_host_data(8, 16) => NLW_amb_trd_host_data_8_16_UNCONNECTED,
      trd_host_data(8, 15) => NLW_amb_trd_host_data_8_15_UNCONNECTED,
      trd_host_data(8, 14) => NLW_amb_trd_host_data_8_14_UNCONNECTED,
      trd_host_data(8, 13) => NLW_amb_trd_host_data_8_13_UNCONNECTED,
      trd_host_data(8, 12) => NLW_amb_trd_host_data_8_12_UNCONNECTED,
      trd_host_data(8, 11) => NLW_amb_trd_host_data_8_11_UNCONNECTED,
      trd_host_data(8, 10) => NLW_amb_trd_host_data_8_10_UNCONNECTED,
      trd_host_data(8, 9) => NLW_amb_trd_host_data_8_9_UNCONNECTED,
      trd_host_data(8, 8) => NLW_amb_trd_host_data_8_8_UNCONNECTED,
      trd_host_data(8, 7) => NLW_amb_trd_host_data_8_7_UNCONNECTED,
      trd_host_data(8, 6) => NLW_amb_trd_host_data_8_6_UNCONNECTED,
      trd_host_data(8, 5) => NLW_amb_trd_host_data_8_5_UNCONNECTED,
      trd_host_data(8, 4) => NLW_amb_trd_host_data_8_4_UNCONNECTED,
      trd_host_data(8, 3) => NLW_amb_trd_host_data_8_3_UNCONNECTED,
      trd_host_data(8, 2) => NLW_amb_trd_host_data_8_2_UNCONNECTED,
      trd_host_data(8, 1) => NLW_amb_trd_host_data_8_1_UNCONNECTED,
      trd_host_data(8, 0) => NLW_amb_trd_host_data_8_0_UNCONNECTED,
      trd_host_data(7, 63) => trd_host_data_7_63_Q,
      trd_host_data(7, 62) => trd_host_data_7_62_Q,
      trd_host_data(7, 61) => trd_host_data_7_61_Q,
      trd_host_data(7, 60) => trd_host_data_7_60_Q,
      trd_host_data(7, 59) => trd_host_data_7_59_Q,
      trd_host_data(7, 58) => trd_host_data_7_58_Q,
      trd_host_data(7, 57) => trd_host_data_7_57_Q,
      trd_host_data(7, 56) => trd_host_data_7_56_Q,
      trd_host_data(7, 55) => trd_host_data_7_55_Q,
      trd_host_data(7, 54) => trd_host_data_7_54_Q,
      trd_host_data(7, 53) => trd_host_data_7_53_Q,
      trd_host_data(7, 52) => trd_host_data_7_52_Q,
      trd_host_data(7, 51) => trd_host_data_7_51_Q,
      trd_host_data(7, 50) => trd_host_data_7_50_Q,
      trd_host_data(7, 49) => trd_host_data_7_49_Q,
      trd_host_data(7, 48) => trd_host_data_7_48_Q,
      trd_host_data(7, 47) => trd_host_data_7_47_Q,
      trd_host_data(7, 46) => trd_host_data_7_46_Q,
      trd_host_data(7, 45) => trd_host_data_7_45_Q,
      trd_host_data(7, 44) => trd_host_data_7_44_Q,
      trd_host_data(7, 43) => trd_host_data_7_43_Q,
      trd_host_data(7, 42) => trd_host_data_7_42_Q,
      trd_host_data(7, 41) => trd_host_data_7_41_Q,
      trd_host_data(7, 40) => trd_host_data_7_40_Q,
      trd_host_data(7, 39) => trd_host_data_7_39_Q,
      trd_host_data(7, 38) => trd_host_data_7_38_Q,
      trd_host_data(7, 37) => trd_host_data_7_37_Q,
      trd_host_data(7, 36) => trd_host_data_7_36_Q,
      trd_host_data(7, 35) => trd_host_data_7_35_Q,
      trd_host_data(7, 34) => trd_host_data_7_34_Q,
      trd_host_data(7, 33) => trd_host_data_7_33_Q,
      trd_host_data(7, 32) => trd_host_data_7_32_Q,
      trd_host_data(7, 31) => trd_host_data_7_31_Q,
      trd_host_data(7, 30) => trd_host_data_7_30_Q,
      trd_host_data(7, 29) => trd_host_data_7_29_Q,
      trd_host_data(7, 28) => trd_host_data_7_28_Q,
      trd_host_data(7, 27) => trd_host_data_7_27_Q,
      trd_host_data(7, 26) => trd_host_data_7_26_Q,
      trd_host_data(7, 25) => trd_host_data_7_25_Q,
      trd_host_data(7, 24) => trd_host_data_7_24_Q,
      trd_host_data(7, 23) => trd_host_data_7_23_Q,
      trd_host_data(7, 22) => trd_host_data_7_22_Q,
      trd_host_data(7, 21) => trd_host_data_7_21_Q,
      trd_host_data(7, 20) => trd_host_data_7_20_Q,
      trd_host_data(7, 19) => trd_host_data_7_19_Q,
      trd_host_data(7, 18) => trd_host_data_7_18_Q,
      trd_host_data(7, 17) => trd_host_data_7_17_Q,
      trd_host_data(7, 16) => trd_host_data_7_16_Q,
      trd_host_data(7, 15) => trd_host_data_7_15_Q,
      trd_host_data(7, 14) => trd_host_data_7_14_Q,
      trd_host_data(7, 13) => trd_host_data_7_13_Q,
      trd_host_data(7, 12) => trd_host_data_7_12_Q,
      trd_host_data(7, 11) => trd_host_data_7_11_Q,
      trd_host_data(7, 10) => trd_host_data_7_10_Q,
      trd_host_data(7, 9) => trd_host_data_7_9_Q,
      trd_host_data(7, 8) => trd_host_data_7_8_Q,
      trd_host_data(7, 7) => trd_host_data_7_7_Q,
      trd_host_data(7, 6) => trd_host_data_7_6_Q,
      trd_host_data(7, 5) => trd_host_data_7_5_Q,
      trd_host_data(7, 4) => trd_host_data_7_4_Q,
      trd_host_data(7, 3) => trd_host_data_7_3_Q,
      trd_host_data(7, 2) => trd_host_data_7_2_Q,
      trd_host_data(7, 1) => trd_host_data_7_1_Q,
      trd_host_data(7, 0) => trd_host_data_7_0_Q,
      trd_host_data(6, 63) => NLW_amb_trd_host_data_6_63_UNCONNECTED,
      trd_host_data(6, 62) => NLW_amb_trd_host_data_6_62_UNCONNECTED,
      trd_host_data(6, 61) => NLW_amb_trd_host_data_6_61_UNCONNECTED,
      trd_host_data(6, 60) => NLW_amb_trd_host_data_6_60_UNCONNECTED,
      trd_host_data(6, 59) => NLW_amb_trd_host_data_6_59_UNCONNECTED,
      trd_host_data(6, 58) => NLW_amb_trd_host_data_6_58_UNCONNECTED,
      trd_host_data(6, 57) => NLW_amb_trd_host_data_6_57_UNCONNECTED,
      trd_host_data(6, 56) => NLW_amb_trd_host_data_6_56_UNCONNECTED,
      trd_host_data(6, 55) => NLW_amb_trd_host_data_6_55_UNCONNECTED,
      trd_host_data(6, 54) => NLW_amb_trd_host_data_6_54_UNCONNECTED,
      trd_host_data(6, 53) => NLW_amb_trd_host_data_6_53_UNCONNECTED,
      trd_host_data(6, 52) => NLW_amb_trd_host_data_6_52_UNCONNECTED,
      trd_host_data(6, 51) => NLW_amb_trd_host_data_6_51_UNCONNECTED,
      trd_host_data(6, 50) => NLW_amb_trd_host_data_6_50_UNCONNECTED,
      trd_host_data(6, 49) => NLW_amb_trd_host_data_6_49_UNCONNECTED,
      trd_host_data(6, 48) => NLW_amb_trd_host_data_6_48_UNCONNECTED,
      trd_host_data(6, 47) => NLW_amb_trd_host_data_6_47_UNCONNECTED,
      trd_host_data(6, 46) => NLW_amb_trd_host_data_6_46_UNCONNECTED,
      trd_host_data(6, 45) => NLW_amb_trd_host_data_6_45_UNCONNECTED,
      trd_host_data(6, 44) => NLW_amb_trd_host_data_6_44_UNCONNECTED,
      trd_host_data(6, 43) => NLW_amb_trd_host_data_6_43_UNCONNECTED,
      trd_host_data(6, 42) => NLW_amb_trd_host_data_6_42_UNCONNECTED,
      trd_host_data(6, 41) => NLW_amb_trd_host_data_6_41_UNCONNECTED,
      trd_host_data(6, 40) => NLW_amb_trd_host_data_6_40_UNCONNECTED,
      trd_host_data(6, 39) => NLW_amb_trd_host_data_6_39_UNCONNECTED,
      trd_host_data(6, 38) => NLW_amb_trd_host_data_6_38_UNCONNECTED,
      trd_host_data(6, 37) => NLW_amb_trd_host_data_6_37_UNCONNECTED,
      trd_host_data(6, 36) => NLW_amb_trd_host_data_6_36_UNCONNECTED,
      trd_host_data(6, 35) => NLW_amb_trd_host_data_6_35_UNCONNECTED,
      trd_host_data(6, 34) => NLW_amb_trd_host_data_6_34_UNCONNECTED,
      trd_host_data(6, 33) => NLW_amb_trd_host_data_6_33_UNCONNECTED,
      trd_host_data(6, 32) => NLW_amb_trd_host_data_6_32_UNCONNECTED,
      trd_host_data(6, 31) => NLW_amb_trd_host_data_6_31_UNCONNECTED,
      trd_host_data(6, 30) => NLW_amb_trd_host_data_6_30_UNCONNECTED,
      trd_host_data(6, 29) => NLW_amb_trd_host_data_6_29_UNCONNECTED,
      trd_host_data(6, 28) => NLW_amb_trd_host_data_6_28_UNCONNECTED,
      trd_host_data(6, 27) => NLW_amb_trd_host_data_6_27_UNCONNECTED,
      trd_host_data(6, 26) => NLW_amb_trd_host_data_6_26_UNCONNECTED,
      trd_host_data(6, 25) => NLW_amb_trd_host_data_6_25_UNCONNECTED,
      trd_host_data(6, 24) => NLW_amb_trd_host_data_6_24_UNCONNECTED,
      trd_host_data(6, 23) => NLW_amb_trd_host_data_6_23_UNCONNECTED,
      trd_host_data(6, 22) => NLW_amb_trd_host_data_6_22_UNCONNECTED,
      trd_host_data(6, 21) => NLW_amb_trd_host_data_6_21_UNCONNECTED,
      trd_host_data(6, 20) => NLW_amb_trd_host_data_6_20_UNCONNECTED,
      trd_host_data(6, 19) => NLW_amb_trd_host_data_6_19_UNCONNECTED,
      trd_host_data(6, 18) => NLW_amb_trd_host_data_6_18_UNCONNECTED,
      trd_host_data(6, 17) => NLW_amb_trd_host_data_6_17_UNCONNECTED,
      trd_host_data(6, 16) => NLW_amb_trd_host_data_6_16_UNCONNECTED,
      trd_host_data(6, 15) => NLW_amb_trd_host_data_6_15_UNCONNECTED,
      trd_host_data(6, 14) => NLW_amb_trd_host_data_6_14_UNCONNECTED,
      trd_host_data(6, 13) => NLW_amb_trd_host_data_6_13_UNCONNECTED,
      trd_host_data(6, 12) => NLW_amb_trd_host_data_6_12_UNCONNECTED,
      trd_host_data(6, 11) => NLW_amb_trd_host_data_6_11_UNCONNECTED,
      trd_host_data(6, 10) => NLW_amb_trd_host_data_6_10_UNCONNECTED,
      trd_host_data(6, 9) => NLW_amb_trd_host_data_6_9_UNCONNECTED,
      trd_host_data(6, 8) => NLW_amb_trd_host_data_6_8_UNCONNECTED,
      trd_host_data(6, 7) => NLW_amb_trd_host_data_6_7_UNCONNECTED,
      trd_host_data(6, 6) => NLW_amb_trd_host_data_6_6_UNCONNECTED,
      trd_host_data(6, 5) => NLW_amb_trd_host_data_6_5_UNCONNECTED,
      trd_host_data(6, 4) => NLW_amb_trd_host_data_6_4_UNCONNECTED,
      trd_host_data(6, 3) => NLW_amb_trd_host_data_6_3_UNCONNECTED,
      trd_host_data(6, 2) => NLW_amb_trd_host_data_6_2_UNCONNECTED,
      trd_host_data(6, 1) => NLW_amb_trd_host_data_6_1_UNCONNECTED,
      trd_host_data(6, 0) => NLW_amb_trd_host_data_6_0_UNCONNECTED,
      trd_host_data(5, 63) => NLW_amb_trd_host_data_5_63_UNCONNECTED,
      trd_host_data(5, 62) => NLW_amb_trd_host_data_5_62_UNCONNECTED,
      trd_host_data(5, 61) => NLW_amb_trd_host_data_5_61_UNCONNECTED,
      trd_host_data(5, 60) => NLW_amb_trd_host_data_5_60_UNCONNECTED,
      trd_host_data(5, 59) => NLW_amb_trd_host_data_5_59_UNCONNECTED,
      trd_host_data(5, 58) => NLW_amb_trd_host_data_5_58_UNCONNECTED,
      trd_host_data(5, 57) => NLW_amb_trd_host_data_5_57_UNCONNECTED,
      trd_host_data(5, 56) => NLW_amb_trd_host_data_5_56_UNCONNECTED,
      trd_host_data(5, 55) => NLW_amb_trd_host_data_5_55_UNCONNECTED,
      trd_host_data(5, 54) => NLW_amb_trd_host_data_5_54_UNCONNECTED,
      trd_host_data(5, 53) => NLW_amb_trd_host_data_5_53_UNCONNECTED,
      trd_host_data(5, 52) => NLW_amb_trd_host_data_5_52_UNCONNECTED,
      trd_host_data(5, 51) => NLW_amb_trd_host_data_5_51_UNCONNECTED,
      trd_host_data(5, 50) => NLW_amb_trd_host_data_5_50_UNCONNECTED,
      trd_host_data(5, 49) => NLW_amb_trd_host_data_5_49_UNCONNECTED,
      trd_host_data(5, 48) => NLW_amb_trd_host_data_5_48_UNCONNECTED,
      trd_host_data(5, 47) => NLW_amb_trd_host_data_5_47_UNCONNECTED,
      trd_host_data(5, 46) => NLW_amb_trd_host_data_5_46_UNCONNECTED,
      trd_host_data(5, 45) => NLW_amb_trd_host_data_5_45_UNCONNECTED,
      trd_host_data(5, 44) => NLW_amb_trd_host_data_5_44_UNCONNECTED,
      trd_host_data(5, 43) => NLW_amb_trd_host_data_5_43_UNCONNECTED,
      trd_host_data(5, 42) => NLW_amb_trd_host_data_5_42_UNCONNECTED,
      trd_host_data(5, 41) => NLW_amb_trd_host_data_5_41_UNCONNECTED,
      trd_host_data(5, 40) => NLW_amb_trd_host_data_5_40_UNCONNECTED,
      trd_host_data(5, 39) => NLW_amb_trd_host_data_5_39_UNCONNECTED,
      trd_host_data(5, 38) => NLW_amb_trd_host_data_5_38_UNCONNECTED,
      trd_host_data(5, 37) => NLW_amb_trd_host_data_5_37_UNCONNECTED,
      trd_host_data(5, 36) => NLW_amb_trd_host_data_5_36_UNCONNECTED,
      trd_host_data(5, 35) => NLW_amb_trd_host_data_5_35_UNCONNECTED,
      trd_host_data(5, 34) => NLW_amb_trd_host_data_5_34_UNCONNECTED,
      trd_host_data(5, 33) => NLW_amb_trd_host_data_5_33_UNCONNECTED,
      trd_host_data(5, 32) => NLW_amb_trd_host_data_5_32_UNCONNECTED,
      trd_host_data(5, 31) => NLW_amb_trd_host_data_5_31_UNCONNECTED,
      trd_host_data(5, 30) => NLW_amb_trd_host_data_5_30_UNCONNECTED,
      trd_host_data(5, 29) => NLW_amb_trd_host_data_5_29_UNCONNECTED,
      trd_host_data(5, 28) => NLW_amb_trd_host_data_5_28_UNCONNECTED,
      trd_host_data(5, 27) => NLW_amb_trd_host_data_5_27_UNCONNECTED,
      trd_host_data(5, 26) => NLW_amb_trd_host_data_5_26_UNCONNECTED,
      trd_host_data(5, 25) => NLW_amb_trd_host_data_5_25_UNCONNECTED,
      trd_host_data(5, 24) => NLW_amb_trd_host_data_5_24_UNCONNECTED,
      trd_host_data(5, 23) => NLW_amb_trd_host_data_5_23_UNCONNECTED,
      trd_host_data(5, 22) => NLW_amb_trd_host_data_5_22_UNCONNECTED,
      trd_host_data(5, 21) => NLW_amb_trd_host_data_5_21_UNCONNECTED,
      trd_host_data(5, 20) => NLW_amb_trd_host_data_5_20_UNCONNECTED,
      trd_host_data(5, 19) => NLW_amb_trd_host_data_5_19_UNCONNECTED,
      trd_host_data(5, 18) => NLW_amb_trd_host_data_5_18_UNCONNECTED,
      trd_host_data(5, 17) => NLW_amb_trd_host_data_5_17_UNCONNECTED,
      trd_host_data(5, 16) => NLW_amb_trd_host_data_5_16_UNCONNECTED,
      trd_host_data(5, 15) => NLW_amb_trd_host_data_5_15_UNCONNECTED,
      trd_host_data(5, 14) => NLW_amb_trd_host_data_5_14_UNCONNECTED,
      trd_host_data(5, 13) => NLW_amb_trd_host_data_5_13_UNCONNECTED,
      trd_host_data(5, 12) => NLW_amb_trd_host_data_5_12_UNCONNECTED,
      trd_host_data(5, 11) => NLW_amb_trd_host_data_5_11_UNCONNECTED,
      trd_host_data(5, 10) => NLW_amb_trd_host_data_5_10_UNCONNECTED,
      trd_host_data(5, 9) => NLW_amb_trd_host_data_5_9_UNCONNECTED,
      trd_host_data(5, 8) => NLW_amb_trd_host_data_5_8_UNCONNECTED,
      trd_host_data(5, 7) => NLW_amb_trd_host_data_5_7_UNCONNECTED,
      trd_host_data(5, 6) => NLW_amb_trd_host_data_5_6_UNCONNECTED,
      trd_host_data(5, 5) => NLW_amb_trd_host_data_5_5_UNCONNECTED,
      trd_host_data(5, 4) => NLW_amb_trd_host_data_5_4_UNCONNECTED,
      trd_host_data(5, 3) => NLW_amb_trd_host_data_5_3_UNCONNECTED,
      trd_host_data(5, 2) => NLW_amb_trd_host_data_5_2_UNCONNECTED,
      trd_host_data(5, 1) => NLW_amb_trd_host_data_5_1_UNCONNECTED,
      trd_host_data(5, 0) => NLW_amb_trd_host_data_5_0_UNCONNECTED,
      trd_host_data(4, 63) => NLW_amb_trd_host_data_4_63_UNCONNECTED,
      trd_host_data(4, 62) => NLW_amb_trd_host_data_4_62_UNCONNECTED,
      trd_host_data(4, 61) => NLW_amb_trd_host_data_4_61_UNCONNECTED,
      trd_host_data(4, 60) => NLW_amb_trd_host_data_4_60_UNCONNECTED,
      trd_host_data(4, 59) => NLW_amb_trd_host_data_4_59_UNCONNECTED,
      trd_host_data(4, 58) => NLW_amb_trd_host_data_4_58_UNCONNECTED,
      trd_host_data(4, 57) => NLW_amb_trd_host_data_4_57_UNCONNECTED,
      trd_host_data(4, 56) => NLW_amb_trd_host_data_4_56_UNCONNECTED,
      trd_host_data(4, 55) => NLW_amb_trd_host_data_4_55_UNCONNECTED,
      trd_host_data(4, 54) => NLW_amb_trd_host_data_4_54_UNCONNECTED,
      trd_host_data(4, 53) => NLW_amb_trd_host_data_4_53_UNCONNECTED,
      trd_host_data(4, 52) => NLW_amb_trd_host_data_4_52_UNCONNECTED,
      trd_host_data(4, 51) => NLW_amb_trd_host_data_4_51_UNCONNECTED,
      trd_host_data(4, 50) => NLW_amb_trd_host_data_4_50_UNCONNECTED,
      trd_host_data(4, 49) => NLW_amb_trd_host_data_4_49_UNCONNECTED,
      trd_host_data(4, 48) => NLW_amb_trd_host_data_4_48_UNCONNECTED,
      trd_host_data(4, 47) => NLW_amb_trd_host_data_4_47_UNCONNECTED,
      trd_host_data(4, 46) => NLW_amb_trd_host_data_4_46_UNCONNECTED,
      trd_host_data(4, 45) => NLW_amb_trd_host_data_4_45_UNCONNECTED,
      trd_host_data(4, 44) => NLW_amb_trd_host_data_4_44_UNCONNECTED,
      trd_host_data(4, 43) => NLW_amb_trd_host_data_4_43_UNCONNECTED,
      trd_host_data(4, 42) => NLW_amb_trd_host_data_4_42_UNCONNECTED,
      trd_host_data(4, 41) => NLW_amb_trd_host_data_4_41_UNCONNECTED,
      trd_host_data(4, 40) => NLW_amb_trd_host_data_4_40_UNCONNECTED,
      trd_host_data(4, 39) => NLW_amb_trd_host_data_4_39_UNCONNECTED,
      trd_host_data(4, 38) => NLW_amb_trd_host_data_4_38_UNCONNECTED,
      trd_host_data(4, 37) => NLW_amb_trd_host_data_4_37_UNCONNECTED,
      trd_host_data(4, 36) => NLW_amb_trd_host_data_4_36_UNCONNECTED,
      trd_host_data(4, 35) => NLW_amb_trd_host_data_4_35_UNCONNECTED,
      trd_host_data(4, 34) => NLW_amb_trd_host_data_4_34_UNCONNECTED,
      trd_host_data(4, 33) => NLW_amb_trd_host_data_4_33_UNCONNECTED,
      trd_host_data(4, 32) => NLW_amb_trd_host_data_4_32_UNCONNECTED,
      trd_host_data(4, 31) => NLW_amb_trd_host_data_4_31_UNCONNECTED,
      trd_host_data(4, 30) => NLW_amb_trd_host_data_4_30_UNCONNECTED,
      trd_host_data(4, 29) => NLW_amb_trd_host_data_4_29_UNCONNECTED,
      trd_host_data(4, 28) => NLW_amb_trd_host_data_4_28_UNCONNECTED,
      trd_host_data(4, 27) => NLW_amb_trd_host_data_4_27_UNCONNECTED,
      trd_host_data(4, 26) => NLW_amb_trd_host_data_4_26_UNCONNECTED,
      trd_host_data(4, 25) => NLW_amb_trd_host_data_4_25_UNCONNECTED,
      trd_host_data(4, 24) => NLW_amb_trd_host_data_4_24_UNCONNECTED,
      trd_host_data(4, 23) => NLW_amb_trd_host_data_4_23_UNCONNECTED,
      trd_host_data(4, 22) => NLW_amb_trd_host_data_4_22_UNCONNECTED,
      trd_host_data(4, 21) => NLW_amb_trd_host_data_4_21_UNCONNECTED,
      trd_host_data(4, 20) => NLW_amb_trd_host_data_4_20_UNCONNECTED,
      trd_host_data(4, 19) => NLW_amb_trd_host_data_4_19_UNCONNECTED,
      trd_host_data(4, 18) => NLW_amb_trd_host_data_4_18_UNCONNECTED,
      trd_host_data(4, 17) => NLW_amb_trd_host_data_4_17_UNCONNECTED,
      trd_host_data(4, 16) => NLW_amb_trd_host_data_4_16_UNCONNECTED,
      trd_host_data(4, 15) => NLW_amb_trd_host_data_4_15_UNCONNECTED,
      trd_host_data(4, 14) => NLW_amb_trd_host_data_4_14_UNCONNECTED,
      trd_host_data(4, 13) => NLW_amb_trd_host_data_4_13_UNCONNECTED,
      trd_host_data(4, 12) => NLW_amb_trd_host_data_4_12_UNCONNECTED,
      trd_host_data(4, 11) => NLW_amb_trd_host_data_4_11_UNCONNECTED,
      trd_host_data(4, 10) => NLW_amb_trd_host_data_4_10_UNCONNECTED,
      trd_host_data(4, 9) => NLW_amb_trd_host_data_4_9_UNCONNECTED,
      trd_host_data(4, 8) => NLW_amb_trd_host_data_4_8_UNCONNECTED,
      trd_host_data(4, 7) => NLW_amb_trd_host_data_4_7_UNCONNECTED,
      trd_host_data(4, 6) => NLW_amb_trd_host_data_4_6_UNCONNECTED,
      trd_host_data(4, 5) => NLW_amb_trd_host_data_4_5_UNCONNECTED,
      trd_host_data(4, 4) => NLW_amb_trd_host_data_4_4_UNCONNECTED,
      trd_host_data(4, 3) => NLW_amb_trd_host_data_4_3_UNCONNECTED,
      trd_host_data(4, 2) => NLW_amb_trd_host_data_4_2_UNCONNECTED,
      trd_host_data(4, 1) => NLW_amb_trd_host_data_4_1_UNCONNECTED,
      trd_host_data(4, 0) => NLW_amb_trd_host_data_4_0_UNCONNECTED,
      trd_host_data(3, 63) => NLW_amb_trd_host_data_3_63_UNCONNECTED,
      trd_host_data(3, 62) => NLW_amb_trd_host_data_3_62_UNCONNECTED,
      trd_host_data(3, 61) => NLW_amb_trd_host_data_3_61_UNCONNECTED,
      trd_host_data(3, 60) => NLW_amb_trd_host_data_3_60_UNCONNECTED,
      trd_host_data(3, 59) => NLW_amb_trd_host_data_3_59_UNCONNECTED,
      trd_host_data(3, 58) => NLW_amb_trd_host_data_3_58_UNCONNECTED,
      trd_host_data(3, 57) => NLW_amb_trd_host_data_3_57_UNCONNECTED,
      trd_host_data(3, 56) => NLW_amb_trd_host_data_3_56_UNCONNECTED,
      trd_host_data(3, 55) => NLW_amb_trd_host_data_3_55_UNCONNECTED,
      trd_host_data(3, 54) => NLW_amb_trd_host_data_3_54_UNCONNECTED,
      trd_host_data(3, 53) => NLW_amb_trd_host_data_3_53_UNCONNECTED,
      trd_host_data(3, 52) => NLW_amb_trd_host_data_3_52_UNCONNECTED,
      trd_host_data(3, 51) => NLW_amb_trd_host_data_3_51_UNCONNECTED,
      trd_host_data(3, 50) => NLW_amb_trd_host_data_3_50_UNCONNECTED,
      trd_host_data(3, 49) => NLW_amb_trd_host_data_3_49_UNCONNECTED,
      trd_host_data(3, 48) => NLW_amb_trd_host_data_3_48_UNCONNECTED,
      trd_host_data(3, 47) => NLW_amb_trd_host_data_3_47_UNCONNECTED,
      trd_host_data(3, 46) => NLW_amb_trd_host_data_3_46_UNCONNECTED,
      trd_host_data(3, 45) => NLW_amb_trd_host_data_3_45_UNCONNECTED,
      trd_host_data(3, 44) => NLW_amb_trd_host_data_3_44_UNCONNECTED,
      trd_host_data(3, 43) => NLW_amb_trd_host_data_3_43_UNCONNECTED,
      trd_host_data(3, 42) => NLW_amb_trd_host_data_3_42_UNCONNECTED,
      trd_host_data(3, 41) => NLW_amb_trd_host_data_3_41_UNCONNECTED,
      trd_host_data(3, 40) => NLW_amb_trd_host_data_3_40_UNCONNECTED,
      trd_host_data(3, 39) => NLW_amb_trd_host_data_3_39_UNCONNECTED,
      trd_host_data(3, 38) => NLW_amb_trd_host_data_3_38_UNCONNECTED,
      trd_host_data(3, 37) => NLW_amb_trd_host_data_3_37_UNCONNECTED,
      trd_host_data(3, 36) => NLW_amb_trd_host_data_3_36_UNCONNECTED,
      trd_host_data(3, 35) => NLW_amb_trd_host_data_3_35_UNCONNECTED,
      trd_host_data(3, 34) => NLW_amb_trd_host_data_3_34_UNCONNECTED,
      trd_host_data(3, 33) => NLW_amb_trd_host_data_3_33_UNCONNECTED,
      trd_host_data(3, 32) => NLW_amb_trd_host_data_3_32_UNCONNECTED,
      trd_host_data(3, 31) => NLW_amb_trd_host_data_3_31_UNCONNECTED,
      trd_host_data(3, 30) => NLW_amb_trd_host_data_3_30_UNCONNECTED,
      trd_host_data(3, 29) => NLW_amb_trd_host_data_3_29_UNCONNECTED,
      trd_host_data(3, 28) => NLW_amb_trd_host_data_3_28_UNCONNECTED,
      trd_host_data(3, 27) => NLW_amb_trd_host_data_3_27_UNCONNECTED,
      trd_host_data(3, 26) => NLW_amb_trd_host_data_3_26_UNCONNECTED,
      trd_host_data(3, 25) => NLW_amb_trd_host_data_3_25_UNCONNECTED,
      trd_host_data(3, 24) => NLW_amb_trd_host_data_3_24_UNCONNECTED,
      trd_host_data(3, 23) => NLW_amb_trd_host_data_3_23_UNCONNECTED,
      trd_host_data(3, 22) => NLW_amb_trd_host_data_3_22_UNCONNECTED,
      trd_host_data(3, 21) => NLW_amb_trd_host_data_3_21_UNCONNECTED,
      trd_host_data(3, 20) => NLW_amb_trd_host_data_3_20_UNCONNECTED,
      trd_host_data(3, 19) => NLW_amb_trd_host_data_3_19_UNCONNECTED,
      trd_host_data(3, 18) => NLW_amb_trd_host_data_3_18_UNCONNECTED,
      trd_host_data(3, 17) => NLW_amb_trd_host_data_3_17_UNCONNECTED,
      trd_host_data(3, 16) => NLW_amb_trd_host_data_3_16_UNCONNECTED,
      trd_host_data(3, 15) => NLW_amb_trd_host_data_3_15_UNCONNECTED,
      trd_host_data(3, 14) => NLW_amb_trd_host_data_3_14_UNCONNECTED,
      trd_host_data(3, 13) => NLW_amb_trd_host_data_3_13_UNCONNECTED,
      trd_host_data(3, 12) => NLW_amb_trd_host_data_3_12_UNCONNECTED,
      trd_host_data(3, 11) => NLW_amb_trd_host_data_3_11_UNCONNECTED,
      trd_host_data(3, 10) => NLW_amb_trd_host_data_3_10_UNCONNECTED,
      trd_host_data(3, 9) => NLW_amb_trd_host_data_3_9_UNCONNECTED,
      trd_host_data(3, 8) => NLW_amb_trd_host_data_3_8_UNCONNECTED,
      trd_host_data(3, 7) => NLW_amb_trd_host_data_3_7_UNCONNECTED,
      trd_host_data(3, 6) => NLW_amb_trd_host_data_3_6_UNCONNECTED,
      trd_host_data(3, 5) => NLW_amb_trd_host_data_3_5_UNCONNECTED,
      trd_host_data(3, 4) => NLW_amb_trd_host_data_3_4_UNCONNECTED,
      trd_host_data(3, 3) => NLW_amb_trd_host_data_3_3_UNCONNECTED,
      trd_host_data(3, 2) => NLW_amb_trd_host_data_3_2_UNCONNECTED,
      trd_host_data(3, 1) => NLW_amb_trd_host_data_3_1_UNCONNECTED,
      trd_host_data(3, 0) => NLW_amb_trd_host_data_3_0_UNCONNECTED,
      trd_host_data(2, 63) => NLW_amb_trd_host_data_2_63_UNCONNECTED,
      trd_host_data(2, 62) => NLW_amb_trd_host_data_2_62_UNCONNECTED,
      trd_host_data(2, 61) => NLW_amb_trd_host_data_2_61_UNCONNECTED,
      trd_host_data(2, 60) => NLW_amb_trd_host_data_2_60_UNCONNECTED,
      trd_host_data(2, 59) => NLW_amb_trd_host_data_2_59_UNCONNECTED,
      trd_host_data(2, 58) => NLW_amb_trd_host_data_2_58_UNCONNECTED,
      trd_host_data(2, 57) => NLW_amb_trd_host_data_2_57_UNCONNECTED,
      trd_host_data(2, 56) => NLW_amb_trd_host_data_2_56_UNCONNECTED,
      trd_host_data(2, 55) => NLW_amb_trd_host_data_2_55_UNCONNECTED,
      trd_host_data(2, 54) => NLW_amb_trd_host_data_2_54_UNCONNECTED,
      trd_host_data(2, 53) => NLW_amb_trd_host_data_2_53_UNCONNECTED,
      trd_host_data(2, 52) => NLW_amb_trd_host_data_2_52_UNCONNECTED,
      trd_host_data(2, 51) => NLW_amb_trd_host_data_2_51_UNCONNECTED,
      trd_host_data(2, 50) => NLW_amb_trd_host_data_2_50_UNCONNECTED,
      trd_host_data(2, 49) => NLW_amb_trd_host_data_2_49_UNCONNECTED,
      trd_host_data(2, 48) => NLW_amb_trd_host_data_2_48_UNCONNECTED,
      trd_host_data(2, 47) => NLW_amb_trd_host_data_2_47_UNCONNECTED,
      trd_host_data(2, 46) => NLW_amb_trd_host_data_2_46_UNCONNECTED,
      trd_host_data(2, 45) => NLW_amb_trd_host_data_2_45_UNCONNECTED,
      trd_host_data(2, 44) => NLW_amb_trd_host_data_2_44_UNCONNECTED,
      trd_host_data(2, 43) => NLW_amb_trd_host_data_2_43_UNCONNECTED,
      trd_host_data(2, 42) => NLW_amb_trd_host_data_2_42_UNCONNECTED,
      trd_host_data(2, 41) => NLW_amb_trd_host_data_2_41_UNCONNECTED,
      trd_host_data(2, 40) => NLW_amb_trd_host_data_2_40_UNCONNECTED,
      trd_host_data(2, 39) => NLW_amb_trd_host_data_2_39_UNCONNECTED,
      trd_host_data(2, 38) => NLW_amb_trd_host_data_2_38_UNCONNECTED,
      trd_host_data(2, 37) => NLW_amb_trd_host_data_2_37_UNCONNECTED,
      trd_host_data(2, 36) => NLW_amb_trd_host_data_2_36_UNCONNECTED,
      trd_host_data(2, 35) => NLW_amb_trd_host_data_2_35_UNCONNECTED,
      trd_host_data(2, 34) => NLW_amb_trd_host_data_2_34_UNCONNECTED,
      trd_host_data(2, 33) => NLW_amb_trd_host_data_2_33_UNCONNECTED,
      trd_host_data(2, 32) => NLW_amb_trd_host_data_2_32_UNCONNECTED,
      trd_host_data(2, 31) => NLW_amb_trd_host_data_2_31_UNCONNECTED,
      trd_host_data(2, 30) => NLW_amb_trd_host_data_2_30_UNCONNECTED,
      trd_host_data(2, 29) => NLW_amb_trd_host_data_2_29_UNCONNECTED,
      trd_host_data(2, 28) => NLW_amb_trd_host_data_2_28_UNCONNECTED,
      trd_host_data(2, 27) => NLW_amb_trd_host_data_2_27_UNCONNECTED,
      trd_host_data(2, 26) => NLW_amb_trd_host_data_2_26_UNCONNECTED,
      trd_host_data(2, 25) => NLW_amb_trd_host_data_2_25_UNCONNECTED,
      trd_host_data(2, 24) => NLW_amb_trd_host_data_2_24_UNCONNECTED,
      trd_host_data(2, 23) => NLW_amb_trd_host_data_2_23_UNCONNECTED,
      trd_host_data(2, 22) => NLW_amb_trd_host_data_2_22_UNCONNECTED,
      trd_host_data(2, 21) => NLW_amb_trd_host_data_2_21_UNCONNECTED,
      trd_host_data(2, 20) => NLW_amb_trd_host_data_2_20_UNCONNECTED,
      trd_host_data(2, 19) => NLW_amb_trd_host_data_2_19_UNCONNECTED,
      trd_host_data(2, 18) => NLW_amb_trd_host_data_2_18_UNCONNECTED,
      trd_host_data(2, 17) => NLW_amb_trd_host_data_2_17_UNCONNECTED,
      trd_host_data(2, 16) => NLW_amb_trd_host_data_2_16_UNCONNECTED,
      trd_host_data(2, 15) => NLW_amb_trd_host_data_2_15_UNCONNECTED,
      trd_host_data(2, 14) => NLW_amb_trd_host_data_2_14_UNCONNECTED,
      trd_host_data(2, 13) => NLW_amb_trd_host_data_2_13_UNCONNECTED,
      trd_host_data(2, 12) => NLW_amb_trd_host_data_2_12_UNCONNECTED,
      trd_host_data(2, 11) => NLW_amb_trd_host_data_2_11_UNCONNECTED,
      trd_host_data(2, 10) => NLW_amb_trd_host_data_2_10_UNCONNECTED,
      trd_host_data(2, 9) => NLW_amb_trd_host_data_2_9_UNCONNECTED,
      trd_host_data(2, 8) => NLW_amb_trd_host_data_2_8_UNCONNECTED,
      trd_host_data(2, 7) => NLW_amb_trd_host_data_2_7_UNCONNECTED,
      trd_host_data(2, 6) => NLW_amb_trd_host_data_2_6_UNCONNECTED,
      trd_host_data(2, 5) => NLW_amb_trd_host_data_2_5_UNCONNECTED,
      trd_host_data(2, 4) => NLW_amb_trd_host_data_2_4_UNCONNECTED,
      trd_host_data(2, 3) => NLW_amb_trd_host_data_2_3_UNCONNECTED,
      trd_host_data(2, 2) => NLW_amb_trd_host_data_2_2_UNCONNECTED,
      trd_host_data(2, 1) => NLW_amb_trd_host_data_2_1_UNCONNECTED,
      trd_host_data(2, 0) => NLW_amb_trd_host_data_2_0_UNCONNECTED,
      trd_host_data(1, 63) => NLW_amb_trd_host_data_1_63_UNCONNECTED,
      trd_host_data(1, 62) => NLW_amb_trd_host_data_1_62_UNCONNECTED,
      trd_host_data(1, 61) => NLW_amb_trd_host_data_1_61_UNCONNECTED,
      trd_host_data(1, 60) => NLW_amb_trd_host_data_1_60_UNCONNECTED,
      trd_host_data(1, 59) => NLW_amb_trd_host_data_1_59_UNCONNECTED,
      trd_host_data(1, 58) => NLW_amb_trd_host_data_1_58_UNCONNECTED,
      trd_host_data(1, 57) => NLW_amb_trd_host_data_1_57_UNCONNECTED,
      trd_host_data(1, 56) => NLW_amb_trd_host_data_1_56_UNCONNECTED,
      trd_host_data(1, 55) => NLW_amb_trd_host_data_1_55_UNCONNECTED,
      trd_host_data(1, 54) => NLW_amb_trd_host_data_1_54_UNCONNECTED,
      trd_host_data(1, 53) => NLW_amb_trd_host_data_1_53_UNCONNECTED,
      trd_host_data(1, 52) => NLW_amb_trd_host_data_1_52_UNCONNECTED,
      trd_host_data(1, 51) => NLW_amb_trd_host_data_1_51_UNCONNECTED,
      trd_host_data(1, 50) => NLW_amb_trd_host_data_1_50_UNCONNECTED,
      trd_host_data(1, 49) => NLW_amb_trd_host_data_1_49_UNCONNECTED,
      trd_host_data(1, 48) => NLW_amb_trd_host_data_1_48_UNCONNECTED,
      trd_host_data(1, 47) => NLW_amb_trd_host_data_1_47_UNCONNECTED,
      trd_host_data(1, 46) => NLW_amb_trd_host_data_1_46_UNCONNECTED,
      trd_host_data(1, 45) => NLW_amb_trd_host_data_1_45_UNCONNECTED,
      trd_host_data(1, 44) => NLW_amb_trd_host_data_1_44_UNCONNECTED,
      trd_host_data(1, 43) => NLW_amb_trd_host_data_1_43_UNCONNECTED,
      trd_host_data(1, 42) => NLW_amb_trd_host_data_1_42_UNCONNECTED,
      trd_host_data(1, 41) => NLW_amb_trd_host_data_1_41_UNCONNECTED,
      trd_host_data(1, 40) => NLW_amb_trd_host_data_1_40_UNCONNECTED,
      trd_host_data(1, 39) => NLW_amb_trd_host_data_1_39_UNCONNECTED,
      trd_host_data(1, 38) => NLW_amb_trd_host_data_1_38_UNCONNECTED,
      trd_host_data(1, 37) => NLW_amb_trd_host_data_1_37_UNCONNECTED,
      trd_host_data(1, 36) => NLW_amb_trd_host_data_1_36_UNCONNECTED,
      trd_host_data(1, 35) => NLW_amb_trd_host_data_1_35_UNCONNECTED,
      trd_host_data(1, 34) => NLW_amb_trd_host_data_1_34_UNCONNECTED,
      trd_host_data(1, 33) => NLW_amb_trd_host_data_1_33_UNCONNECTED,
      trd_host_data(1, 32) => NLW_amb_trd_host_data_1_32_UNCONNECTED,
      trd_host_data(1, 31) => NLW_amb_trd_host_data_1_31_UNCONNECTED,
      trd_host_data(1, 30) => NLW_amb_trd_host_data_1_30_UNCONNECTED,
      trd_host_data(1, 29) => NLW_amb_trd_host_data_1_29_UNCONNECTED,
      trd_host_data(1, 28) => NLW_amb_trd_host_data_1_28_UNCONNECTED,
      trd_host_data(1, 27) => NLW_amb_trd_host_data_1_27_UNCONNECTED,
      trd_host_data(1, 26) => NLW_amb_trd_host_data_1_26_UNCONNECTED,
      trd_host_data(1, 25) => NLW_amb_trd_host_data_1_25_UNCONNECTED,
      trd_host_data(1, 24) => NLW_amb_trd_host_data_1_24_UNCONNECTED,
      trd_host_data(1, 23) => NLW_amb_trd_host_data_1_23_UNCONNECTED,
      trd_host_data(1, 22) => NLW_amb_trd_host_data_1_22_UNCONNECTED,
      trd_host_data(1, 21) => NLW_amb_trd_host_data_1_21_UNCONNECTED,
      trd_host_data(1, 20) => NLW_amb_trd_host_data_1_20_UNCONNECTED,
      trd_host_data(1, 19) => NLW_amb_trd_host_data_1_19_UNCONNECTED,
      trd_host_data(1, 18) => NLW_amb_trd_host_data_1_18_UNCONNECTED,
      trd_host_data(1, 17) => NLW_amb_trd_host_data_1_17_UNCONNECTED,
      trd_host_data(1, 16) => NLW_amb_trd_host_data_1_16_UNCONNECTED,
      trd_host_data(1, 15) => NLW_amb_trd_host_data_1_15_UNCONNECTED,
      trd_host_data(1, 14) => NLW_amb_trd_host_data_1_14_UNCONNECTED,
      trd_host_data(1, 13) => NLW_amb_trd_host_data_1_13_UNCONNECTED,
      trd_host_data(1, 12) => NLW_amb_trd_host_data_1_12_UNCONNECTED,
      trd_host_data(1, 11) => NLW_amb_trd_host_data_1_11_UNCONNECTED,
      trd_host_data(1, 10) => NLW_amb_trd_host_data_1_10_UNCONNECTED,
      trd_host_data(1, 9) => NLW_amb_trd_host_data_1_9_UNCONNECTED,
      trd_host_data(1, 8) => NLW_amb_trd_host_data_1_8_UNCONNECTED,
      trd_host_data(1, 7) => NLW_amb_trd_host_data_1_7_UNCONNECTED,
      trd_host_data(1, 6) => NLW_amb_trd_host_data_1_6_UNCONNECTED,
      trd_host_data(1, 5) => NLW_amb_trd_host_data_1_5_UNCONNECTED,
      trd_host_data(1, 4) => NLW_amb_trd_host_data_1_4_UNCONNECTED,
      trd_host_data(1, 3) => NLW_amb_trd_host_data_1_3_UNCONNECTED,
      trd_host_data(1, 2) => NLW_amb_trd_host_data_1_2_UNCONNECTED,
      trd_host_data(1, 1) => NLW_amb_trd_host_data_1_1_UNCONNECTED,
      trd_host_data(1, 0) => NLW_amb_trd_host_data_1_0_UNCONNECTED,
      trd_host_data(0, 63) => trd_host_data_0_63_Q,
      trd_host_data(0, 62) => trd_host_data_0_62_Q,
      trd_host_data(0, 61) => trd_host_data_0_61_Q,
      trd_host_data(0, 60) => trd_host_data_0_60_Q,
      trd_host_data(0, 59) => trd_host_data_0_59_Q,
      trd_host_data(0, 58) => trd_host_data_0_58_Q,
      trd_host_data(0, 57) => trd_host_data_0_57_Q,
      trd_host_data(0, 56) => trd_host_data_0_56_Q,
      trd_host_data(0, 55) => trd_host_data_0_55_Q,
      trd_host_data(0, 54) => trd_host_data_0_54_Q,
      trd_host_data(0, 53) => trd_host_data_0_53_Q,
      trd_host_data(0, 52) => trd_host_data_0_52_Q,
      trd_host_data(0, 51) => trd_host_data_0_51_Q,
      trd_host_data(0, 50) => trd_host_data_0_50_Q,
      trd_host_data(0, 49) => trd_host_data_0_49_Q,
      trd_host_data(0, 48) => trd_host_data_0_48_Q,
      trd_host_data(0, 47) => trd_host_data_0_47_Q,
      trd_host_data(0, 46) => trd_host_data_0_46_Q,
      trd_host_data(0, 45) => trd_host_data_0_45_Q,
      trd_host_data(0, 44) => trd_host_data_0_44_Q,
      trd_host_data(0, 43) => trd_host_data_0_43_Q,
      trd_host_data(0, 42) => trd_host_data_0_42_Q,
      trd_host_data(0, 41) => trd_host_data_0_41_Q,
      trd_host_data(0, 40) => trd_host_data_0_40_Q,
      trd_host_data(0, 39) => trd_host_data_0_39_Q,
      trd_host_data(0, 38) => trd_host_data_0_38_Q,
      trd_host_data(0, 37) => trd_host_data_0_37_Q,
      trd_host_data(0, 36) => trd_host_data_0_36_Q,
      trd_host_data(0, 35) => trd_host_data_0_35_Q,
      trd_host_data(0, 34) => trd_host_data_0_34_Q,
      trd_host_data(0, 33) => trd_host_data_0_33_Q,
      trd_host_data(0, 32) => trd_host_data_0_32_Q,
      trd_host_data(0, 31) => trd_host_data_0_31_Q,
      trd_host_data(0, 30) => trd_host_data_0_30_Q,
      trd_host_data(0, 29) => trd_host_data_0_29_Q,
      trd_host_data(0, 28) => trd_host_data_0_28_Q,
      trd_host_data(0, 27) => trd_host_data_0_27_Q,
      trd_host_data(0, 26) => trd_host_data_0_26_Q,
      trd_host_data(0, 25) => trd_host_data_0_25_Q,
      trd_host_data(0, 24) => trd_host_data_0_24_Q,
      trd_host_data(0, 23) => trd_host_data_0_23_Q,
      trd_host_data(0, 22) => trd_host_data_0_22_Q,
      trd_host_data(0, 21) => trd_host_data_0_21_Q,
      trd_host_data(0, 20) => trd_host_data_0_20_Q,
      trd_host_data(0, 19) => trd_host_data_0_19_Q,
      trd_host_data(0, 18) => trd_host_data_0_18_Q,
      trd_host_data(0, 17) => trd_host_data_0_17_Q,
      trd_host_data(0, 16) => trd_host_data_0_16_Q,
      trd_host_data(0, 15) => trd_host_data_0_15_Q,
      trd_host_data(0, 14) => trd_host_data_0_14_Q,
      trd_host_data(0, 13) => trd_host_data_0_13_Q,
      trd_host_data(0, 12) => trd_host_data_0_12_Q,
      trd_host_data(0, 11) => trd_host_data_0_11_Q,
      trd_host_data(0, 10) => trd_host_data_0_10_Q,
      trd_host_data(0, 9) => trd_host_data_0_9_Q,
      trd_host_data(0, 8) => trd_host_data_0_8_Q,
      trd_host_data(0, 7) => trd_host_data_0_7_Q,
      trd_host_data(0, 6) => trd_host_data_0_6_Q,
      trd_host_data(0, 5) => trd_host_data_0_5_Q,
      trd_host_data(0, 4) => trd_host_data_0_4_Q,
      trd_host_data(0, 3) => trd_host_data_0_3_Q,
      trd_host_data(0, 2) => trd_host_data_0_2_Q,
      trd_host_data(0, 1) => trd_host_data_0_1_Q,
      trd_host_data(0, 0) => trd_host_data_0_0_Q,
      txn(7) => txn_7_OBUF_37026,
      txn(6) => txn_6_OBUF_37025,
      txn(5) => txn_5_OBUF_37024,
      txn(4) => txn_4_OBUF_37023,
      txn(3) => txn_3_OBUF_37022,
      txn(2) => txn_2_OBUF_37021,
      txn(1) => txn_1_OBUF_37020,
      txn(0) => txn_0_OBUF_37019,
      txp(7) => txp_7_OBUF_37042,
      txp(6) => txp_6_OBUF_37041,
      txp(5) => txp_5_OBUF_37040,
      txp(4) => txp_4_OBUF_37039,
      txp(3) => txp_3_OBUF_37038,
      txp(2) => txp_2_OBUF_37037,
      txp(1) => txp_1_OBUF_37036,
      txp(0) => txp_0_OBUF_37035,
      trd_host_cmd_data(15, 15) => NLW_amb_trd_host_cmd_data_15_15_UNCONNECTED,
      trd_host_cmd_data(15, 14) => NLW_amb_trd_host_cmd_data_15_14_UNCONNECTED,
      trd_host_cmd_data(15, 13) => NLW_amb_trd_host_cmd_data_15_13_UNCONNECTED,
      trd_host_cmd_data(15, 12) => NLW_amb_trd_host_cmd_data_15_12_UNCONNECTED,
      trd_host_cmd_data(15, 11) => NLW_amb_trd_host_cmd_data_15_11_UNCONNECTED,
      trd_host_cmd_data(15, 10) => NLW_amb_trd_host_cmd_data_15_10_UNCONNECTED,
      trd_host_cmd_data(15, 9) => NLW_amb_trd_host_cmd_data_15_9_UNCONNECTED,
      trd_host_cmd_data(15, 8) => NLW_amb_trd_host_cmd_data_15_8_UNCONNECTED,
      trd_host_cmd_data(15, 7) => NLW_amb_trd_host_cmd_data_15_7_UNCONNECTED,
      trd_host_cmd_data(15, 6) => NLW_amb_trd_host_cmd_data_15_6_UNCONNECTED,
      trd_host_cmd_data(15, 5) => NLW_amb_trd_host_cmd_data_15_5_UNCONNECTED,
      trd_host_cmd_data(15, 4) => NLW_amb_trd_host_cmd_data_15_4_UNCONNECTED,
      trd_host_cmd_data(15, 3) => NLW_amb_trd_host_cmd_data_15_3_UNCONNECTED,
      trd_host_cmd_data(15, 2) => NLW_amb_trd_host_cmd_data_15_2_UNCONNECTED,
      trd_host_cmd_data(15, 1) => NLW_amb_trd_host_cmd_data_15_1_UNCONNECTED,
      trd_host_cmd_data(15, 0) => NLW_amb_trd_host_cmd_data_15_0_UNCONNECTED,
      trd_host_cmd_data(14, 15) => NLW_amb_trd_host_cmd_data_14_15_UNCONNECTED,
      trd_host_cmd_data(14, 14) => NLW_amb_trd_host_cmd_data_14_14_UNCONNECTED,
      trd_host_cmd_data(14, 13) => NLW_amb_trd_host_cmd_data_14_13_UNCONNECTED,
      trd_host_cmd_data(14, 12) => NLW_amb_trd_host_cmd_data_14_12_UNCONNECTED,
      trd_host_cmd_data(14, 11) => NLW_amb_trd_host_cmd_data_14_11_UNCONNECTED,
      trd_host_cmd_data(14, 10) => NLW_amb_trd_host_cmd_data_14_10_UNCONNECTED,
      trd_host_cmd_data(14, 9) => NLW_amb_trd_host_cmd_data_14_9_UNCONNECTED,
      trd_host_cmd_data(14, 8) => NLW_amb_trd_host_cmd_data_14_8_UNCONNECTED,
      trd_host_cmd_data(14, 7) => NLW_amb_trd_host_cmd_data_14_7_UNCONNECTED,
      trd_host_cmd_data(14, 6) => NLW_amb_trd_host_cmd_data_14_6_UNCONNECTED,
      trd_host_cmd_data(14, 5) => NLW_amb_trd_host_cmd_data_14_5_UNCONNECTED,
      trd_host_cmd_data(14, 4) => NLW_amb_trd_host_cmd_data_14_4_UNCONNECTED,
      trd_host_cmd_data(14, 3) => NLW_amb_trd_host_cmd_data_14_3_UNCONNECTED,
      trd_host_cmd_data(14, 2) => NLW_amb_trd_host_cmd_data_14_2_UNCONNECTED,
      trd_host_cmd_data(14, 1) => NLW_amb_trd_host_cmd_data_14_1_UNCONNECTED,
      trd_host_cmd_data(14, 0) => NLW_amb_trd_host_cmd_data_14_0_UNCONNECTED,
      trd_host_cmd_data(13, 15) => NLW_amb_trd_host_cmd_data_13_15_UNCONNECTED,
      trd_host_cmd_data(13, 14) => NLW_amb_trd_host_cmd_data_13_14_UNCONNECTED,
      trd_host_cmd_data(13, 13) => NLW_amb_trd_host_cmd_data_13_13_UNCONNECTED,
      trd_host_cmd_data(13, 12) => NLW_amb_trd_host_cmd_data_13_12_UNCONNECTED,
      trd_host_cmd_data(13, 11) => NLW_amb_trd_host_cmd_data_13_11_UNCONNECTED,
      trd_host_cmd_data(13, 10) => NLW_amb_trd_host_cmd_data_13_10_UNCONNECTED,
      trd_host_cmd_data(13, 9) => NLW_amb_trd_host_cmd_data_13_9_UNCONNECTED,
      trd_host_cmd_data(13, 8) => NLW_amb_trd_host_cmd_data_13_8_UNCONNECTED,
      trd_host_cmd_data(13, 7) => NLW_amb_trd_host_cmd_data_13_7_UNCONNECTED,
      trd_host_cmd_data(13, 6) => NLW_amb_trd_host_cmd_data_13_6_UNCONNECTED,
      trd_host_cmd_data(13, 5) => NLW_amb_trd_host_cmd_data_13_5_UNCONNECTED,
      trd_host_cmd_data(13, 4) => NLW_amb_trd_host_cmd_data_13_4_UNCONNECTED,
      trd_host_cmd_data(13, 3) => NLW_amb_trd_host_cmd_data_13_3_UNCONNECTED,
      trd_host_cmd_data(13, 2) => NLW_amb_trd_host_cmd_data_13_2_UNCONNECTED,
      trd_host_cmd_data(13, 1) => NLW_amb_trd_host_cmd_data_13_1_UNCONNECTED,
      trd_host_cmd_data(13, 0) => NLW_amb_trd_host_cmd_data_13_0_UNCONNECTED,
      trd_host_cmd_data(12, 15) => NLW_amb_trd_host_cmd_data_12_15_UNCONNECTED,
      trd_host_cmd_data(12, 14) => NLW_amb_trd_host_cmd_data_12_14_UNCONNECTED,
      trd_host_cmd_data(12, 13) => NLW_amb_trd_host_cmd_data_12_13_UNCONNECTED,
      trd_host_cmd_data(12, 12) => NLW_amb_trd_host_cmd_data_12_12_UNCONNECTED,
      trd_host_cmd_data(12, 11) => NLW_amb_trd_host_cmd_data_12_11_UNCONNECTED,
      trd_host_cmd_data(12, 10) => NLW_amb_trd_host_cmd_data_12_10_UNCONNECTED,
      trd_host_cmd_data(12, 9) => NLW_amb_trd_host_cmd_data_12_9_UNCONNECTED,
      trd_host_cmd_data(12, 8) => NLW_amb_trd_host_cmd_data_12_8_UNCONNECTED,
      trd_host_cmd_data(12, 7) => NLW_amb_trd_host_cmd_data_12_7_UNCONNECTED,
      trd_host_cmd_data(12, 6) => NLW_amb_trd_host_cmd_data_12_6_UNCONNECTED,
      trd_host_cmd_data(12, 5) => NLW_amb_trd_host_cmd_data_12_5_UNCONNECTED,
      trd_host_cmd_data(12, 4) => NLW_amb_trd_host_cmd_data_12_4_UNCONNECTED,
      trd_host_cmd_data(12, 3) => NLW_amb_trd_host_cmd_data_12_3_UNCONNECTED,
      trd_host_cmd_data(12, 2) => NLW_amb_trd_host_cmd_data_12_2_UNCONNECTED,
      trd_host_cmd_data(12, 1) => NLW_amb_trd_host_cmd_data_12_1_UNCONNECTED,
      trd_host_cmd_data(12, 0) => NLW_amb_trd_host_cmd_data_12_0_UNCONNECTED,
      trd_host_cmd_data(11, 15) => NLW_amb_trd_host_cmd_data_11_15_UNCONNECTED,
      trd_host_cmd_data(11, 14) => NLW_amb_trd_host_cmd_data_11_14_UNCONNECTED,
      trd_host_cmd_data(11, 13) => NLW_amb_trd_host_cmd_data_11_13_UNCONNECTED,
      trd_host_cmd_data(11, 12) => NLW_amb_trd_host_cmd_data_11_12_UNCONNECTED,
      trd_host_cmd_data(11, 11) => NLW_amb_trd_host_cmd_data_11_11_UNCONNECTED,
      trd_host_cmd_data(11, 10) => NLW_amb_trd_host_cmd_data_11_10_UNCONNECTED,
      trd_host_cmd_data(11, 9) => NLW_amb_trd_host_cmd_data_11_9_UNCONNECTED,
      trd_host_cmd_data(11, 8) => NLW_amb_trd_host_cmd_data_11_8_UNCONNECTED,
      trd_host_cmd_data(11, 7) => NLW_amb_trd_host_cmd_data_11_7_UNCONNECTED,
      trd_host_cmd_data(11, 6) => NLW_amb_trd_host_cmd_data_11_6_UNCONNECTED,
      trd_host_cmd_data(11, 5) => NLW_amb_trd_host_cmd_data_11_5_UNCONNECTED,
      trd_host_cmd_data(11, 4) => NLW_amb_trd_host_cmd_data_11_4_UNCONNECTED,
      trd_host_cmd_data(11, 3) => NLW_amb_trd_host_cmd_data_11_3_UNCONNECTED,
      trd_host_cmd_data(11, 2) => NLW_amb_trd_host_cmd_data_11_2_UNCONNECTED,
      trd_host_cmd_data(11, 1) => NLW_amb_trd_host_cmd_data_11_1_UNCONNECTED,
      trd_host_cmd_data(11, 0) => NLW_amb_trd_host_cmd_data_11_0_UNCONNECTED,
      trd_host_cmd_data(10, 15) => NLW_amb_trd_host_cmd_data_10_15_UNCONNECTED,
      trd_host_cmd_data(10, 14) => NLW_amb_trd_host_cmd_data_10_14_UNCONNECTED,
      trd_host_cmd_data(10, 13) => NLW_amb_trd_host_cmd_data_10_13_UNCONNECTED,
      trd_host_cmd_data(10, 12) => NLW_amb_trd_host_cmd_data_10_12_UNCONNECTED,
      trd_host_cmd_data(10, 11) => NLW_amb_trd_host_cmd_data_10_11_UNCONNECTED,
      trd_host_cmd_data(10, 10) => NLW_amb_trd_host_cmd_data_10_10_UNCONNECTED,
      trd_host_cmd_data(10, 9) => NLW_amb_trd_host_cmd_data_10_9_UNCONNECTED,
      trd_host_cmd_data(10, 8) => NLW_amb_trd_host_cmd_data_10_8_UNCONNECTED,
      trd_host_cmd_data(10, 7) => NLW_amb_trd_host_cmd_data_10_7_UNCONNECTED,
      trd_host_cmd_data(10, 6) => NLW_amb_trd_host_cmd_data_10_6_UNCONNECTED,
      trd_host_cmd_data(10, 5) => NLW_amb_trd_host_cmd_data_10_5_UNCONNECTED,
      trd_host_cmd_data(10, 4) => NLW_amb_trd_host_cmd_data_10_4_UNCONNECTED,
      trd_host_cmd_data(10, 3) => NLW_amb_trd_host_cmd_data_10_3_UNCONNECTED,
      trd_host_cmd_data(10, 2) => NLW_amb_trd_host_cmd_data_10_2_UNCONNECTED,
      trd_host_cmd_data(10, 1) => NLW_amb_trd_host_cmd_data_10_1_UNCONNECTED,
      trd_host_cmd_data(10, 0) => NLW_amb_trd_host_cmd_data_10_0_UNCONNECTED,
      trd_host_cmd_data(9, 15) => NLW_amb_trd_host_cmd_data_9_15_UNCONNECTED,
      trd_host_cmd_data(9, 14) => NLW_amb_trd_host_cmd_data_9_14_UNCONNECTED,
      trd_host_cmd_data(9, 13) => NLW_amb_trd_host_cmd_data_9_13_UNCONNECTED,
      trd_host_cmd_data(9, 12) => NLW_amb_trd_host_cmd_data_9_12_UNCONNECTED,
      trd_host_cmd_data(9, 11) => NLW_amb_trd_host_cmd_data_9_11_UNCONNECTED,
      trd_host_cmd_data(9, 10) => NLW_amb_trd_host_cmd_data_9_10_UNCONNECTED,
      trd_host_cmd_data(9, 9) => NLW_amb_trd_host_cmd_data_9_9_UNCONNECTED,
      trd_host_cmd_data(9, 8) => NLW_amb_trd_host_cmd_data_9_8_UNCONNECTED,
      trd_host_cmd_data(9, 7) => NLW_amb_trd_host_cmd_data_9_7_UNCONNECTED,
      trd_host_cmd_data(9, 6) => NLW_amb_trd_host_cmd_data_9_6_UNCONNECTED,
      trd_host_cmd_data(9, 5) => NLW_amb_trd_host_cmd_data_9_5_UNCONNECTED,
      trd_host_cmd_data(9, 4) => NLW_amb_trd_host_cmd_data_9_4_UNCONNECTED,
      trd_host_cmd_data(9, 3) => NLW_amb_trd_host_cmd_data_9_3_UNCONNECTED,
      trd_host_cmd_data(9, 2) => NLW_amb_trd_host_cmd_data_9_2_UNCONNECTED,
      trd_host_cmd_data(9, 1) => NLW_amb_trd_host_cmd_data_9_1_UNCONNECTED,
      trd_host_cmd_data(9, 0) => NLW_amb_trd_host_cmd_data_9_0_UNCONNECTED,
      trd_host_cmd_data(8, 15) => NLW_amb_trd_host_cmd_data_8_15_UNCONNECTED,
      trd_host_cmd_data(8, 14) => NLW_amb_trd_host_cmd_data_8_14_UNCONNECTED,
      trd_host_cmd_data(8, 13) => NLW_amb_trd_host_cmd_data_8_13_UNCONNECTED,
      trd_host_cmd_data(8, 12) => NLW_amb_trd_host_cmd_data_8_12_UNCONNECTED,
      trd_host_cmd_data(8, 11) => NLW_amb_trd_host_cmd_data_8_11_UNCONNECTED,
      trd_host_cmd_data(8, 10) => NLW_amb_trd_host_cmd_data_8_10_UNCONNECTED,
      trd_host_cmd_data(8, 9) => NLW_amb_trd_host_cmd_data_8_9_UNCONNECTED,
      trd_host_cmd_data(8, 8) => NLW_amb_trd_host_cmd_data_8_8_UNCONNECTED,
      trd_host_cmd_data(8, 7) => NLW_amb_trd_host_cmd_data_8_7_UNCONNECTED,
      trd_host_cmd_data(8, 6) => NLW_amb_trd_host_cmd_data_8_6_UNCONNECTED,
      trd_host_cmd_data(8, 5) => NLW_amb_trd_host_cmd_data_8_5_UNCONNECTED,
      trd_host_cmd_data(8, 4) => NLW_amb_trd_host_cmd_data_8_4_UNCONNECTED,
      trd_host_cmd_data(8, 3) => NLW_amb_trd_host_cmd_data_8_3_UNCONNECTED,
      trd_host_cmd_data(8, 2) => NLW_amb_trd_host_cmd_data_8_2_UNCONNECTED,
      trd_host_cmd_data(8, 1) => NLW_amb_trd_host_cmd_data_8_1_UNCONNECTED,
      trd_host_cmd_data(8, 0) => NLW_amb_trd_host_cmd_data_8_0_UNCONNECTED,
      trd_host_cmd_data(7, 15) => trd_host_cmd_data_7_15_Q,
      trd_host_cmd_data(7, 14) => trd_host_cmd_data_7_14_Q,
      trd_host_cmd_data(7, 13) => trd_host_cmd_data_7_13_Q,
      trd_host_cmd_data(7, 12) => trd_host_cmd_data_7_12_Q,
      trd_host_cmd_data(7, 11) => trd_host_cmd_data_7_11_Q,
      trd_host_cmd_data(7, 10) => trd_host_cmd_data_7_10_Q,
      trd_host_cmd_data(7, 9) => trd_host_cmd_data_7_9_Q,
      trd_host_cmd_data(7, 8) => trd_host_cmd_data_7_8_Q,
      trd_host_cmd_data(7, 7) => trd_host_cmd_data_7_7_Q,
      trd_host_cmd_data(7, 6) => trd_host_cmd_data_7_6_Q,
      trd_host_cmd_data(7, 5) => trd_host_cmd_data_7_5_Q,
      trd_host_cmd_data(7, 4) => trd_host_cmd_data_7_4_Q,
      trd_host_cmd_data(7, 3) => trd_host_cmd_data_7_3_Q,
      trd_host_cmd_data(7, 2) => trd_host_cmd_data_7_2_Q,
      trd_host_cmd_data(7, 1) => trd_host_cmd_data_7_1_Q,
      trd_host_cmd_data(7, 0) => trd_host_cmd_data_7_0_Q,
      trd_host_cmd_data(6, 15) => trd_host_cmd_data_6_15_Q,
      trd_host_cmd_data(6, 14) => trd_host_cmd_data_6_14_Q,
      trd_host_cmd_data(6, 13) => trd_host_cmd_data_6_13_Q,
      trd_host_cmd_data(6, 12) => trd_host_cmd_data_6_12_Q,
      trd_host_cmd_data(6, 11) => trd_host_cmd_data_6_11_Q,
      trd_host_cmd_data(6, 10) => trd_host_cmd_data_6_10_Q,
      trd_host_cmd_data(6, 9) => trd_host_cmd_data_6_9_Q,
      trd_host_cmd_data(6, 8) => trd_host_cmd_data_6_8_Q,
      trd_host_cmd_data(6, 7) => trd_host_cmd_data_6_7_Q,
      trd_host_cmd_data(6, 6) => trd_host_cmd_data_6_6_Q,
      trd_host_cmd_data(6, 5) => trd_host_cmd_data_6_5_Q,
      trd_host_cmd_data(6, 4) => trd_host_cmd_data_6_4_Q,
      trd_host_cmd_data(6, 3) => trd_host_cmd_data_6_3_Q,
      trd_host_cmd_data(6, 2) => trd_host_cmd_data_6_2_Q,
      trd_host_cmd_data(6, 1) => trd_host_cmd_data_6_1_Q,
      trd_host_cmd_data(6, 0) => trd_host_cmd_data_6_0_Q,
      trd_host_cmd_data(5, 15) => NLW_amb_trd_host_cmd_data_5_15_UNCONNECTED,
      trd_host_cmd_data(5, 14) => NLW_amb_trd_host_cmd_data_5_14_UNCONNECTED,
      trd_host_cmd_data(5, 13) => NLW_amb_trd_host_cmd_data_5_13_UNCONNECTED,
      trd_host_cmd_data(5, 12) => NLW_amb_trd_host_cmd_data_5_12_UNCONNECTED,
      trd_host_cmd_data(5, 11) => NLW_amb_trd_host_cmd_data_5_11_UNCONNECTED,
      trd_host_cmd_data(5, 10) => NLW_amb_trd_host_cmd_data_5_10_UNCONNECTED,
      trd_host_cmd_data(5, 9) => NLW_amb_trd_host_cmd_data_5_9_UNCONNECTED,
      trd_host_cmd_data(5, 8) => NLW_amb_trd_host_cmd_data_5_8_UNCONNECTED,
      trd_host_cmd_data(5, 7) => NLW_amb_trd_host_cmd_data_5_7_UNCONNECTED,
      trd_host_cmd_data(5, 6) => NLW_amb_trd_host_cmd_data_5_6_UNCONNECTED,
      trd_host_cmd_data(5, 5) => NLW_amb_trd_host_cmd_data_5_5_UNCONNECTED,
      trd_host_cmd_data(5, 4) => NLW_amb_trd_host_cmd_data_5_4_UNCONNECTED,
      trd_host_cmd_data(5, 3) => NLW_amb_trd_host_cmd_data_5_3_UNCONNECTED,
      trd_host_cmd_data(5, 2) => NLW_amb_trd_host_cmd_data_5_2_UNCONNECTED,
      trd_host_cmd_data(5, 1) => NLW_amb_trd_host_cmd_data_5_1_UNCONNECTED,
      trd_host_cmd_data(5, 0) => NLW_amb_trd_host_cmd_data_5_0_UNCONNECTED,
      trd_host_cmd_data(4, 15) => NLW_amb_trd_host_cmd_data_4_15_UNCONNECTED,
      trd_host_cmd_data(4, 14) => NLW_amb_trd_host_cmd_data_4_14_UNCONNECTED,
      trd_host_cmd_data(4, 13) => NLW_amb_trd_host_cmd_data_4_13_UNCONNECTED,
      trd_host_cmd_data(4, 12) => NLW_amb_trd_host_cmd_data_4_12_UNCONNECTED,
      trd_host_cmd_data(4, 11) => NLW_amb_trd_host_cmd_data_4_11_UNCONNECTED,
      trd_host_cmd_data(4, 10) => NLW_amb_trd_host_cmd_data_4_10_UNCONNECTED,
      trd_host_cmd_data(4, 9) => NLW_amb_trd_host_cmd_data_4_9_UNCONNECTED,
      trd_host_cmd_data(4, 8) => NLW_amb_trd_host_cmd_data_4_8_UNCONNECTED,
      trd_host_cmd_data(4, 7) => NLW_amb_trd_host_cmd_data_4_7_UNCONNECTED,
      trd_host_cmd_data(4, 6) => NLW_amb_trd_host_cmd_data_4_6_UNCONNECTED,
      trd_host_cmd_data(4, 5) => NLW_amb_trd_host_cmd_data_4_5_UNCONNECTED,
      trd_host_cmd_data(4, 4) => NLW_amb_trd_host_cmd_data_4_4_UNCONNECTED,
      trd_host_cmd_data(4, 3) => NLW_amb_trd_host_cmd_data_4_3_UNCONNECTED,
      trd_host_cmd_data(4, 2) => NLW_amb_trd_host_cmd_data_4_2_UNCONNECTED,
      trd_host_cmd_data(4, 1) => NLW_amb_trd_host_cmd_data_4_1_UNCONNECTED,
      trd_host_cmd_data(4, 0) => NLW_amb_trd_host_cmd_data_4_0_UNCONNECTED,
      trd_host_cmd_data(3, 15) => NLW_amb_trd_host_cmd_data_3_15_UNCONNECTED,
      trd_host_cmd_data(3, 14) => NLW_amb_trd_host_cmd_data_3_14_UNCONNECTED,
      trd_host_cmd_data(3, 13) => NLW_amb_trd_host_cmd_data_3_13_UNCONNECTED,
      trd_host_cmd_data(3, 12) => NLW_amb_trd_host_cmd_data_3_12_UNCONNECTED,
      trd_host_cmd_data(3, 11) => NLW_amb_trd_host_cmd_data_3_11_UNCONNECTED,
      trd_host_cmd_data(3, 10) => NLW_amb_trd_host_cmd_data_3_10_UNCONNECTED,
      trd_host_cmd_data(3, 9) => NLW_amb_trd_host_cmd_data_3_9_UNCONNECTED,
      trd_host_cmd_data(3, 8) => NLW_amb_trd_host_cmd_data_3_8_UNCONNECTED,
      trd_host_cmd_data(3, 7) => NLW_amb_trd_host_cmd_data_3_7_UNCONNECTED,
      trd_host_cmd_data(3, 6) => NLW_amb_trd_host_cmd_data_3_6_UNCONNECTED,
      trd_host_cmd_data(3, 5) => NLW_amb_trd_host_cmd_data_3_5_UNCONNECTED,
      trd_host_cmd_data(3, 4) => NLW_amb_trd_host_cmd_data_3_4_UNCONNECTED,
      trd_host_cmd_data(3, 3) => NLW_amb_trd_host_cmd_data_3_3_UNCONNECTED,
      trd_host_cmd_data(3, 2) => NLW_amb_trd_host_cmd_data_3_2_UNCONNECTED,
      trd_host_cmd_data(3, 1) => NLW_amb_trd_host_cmd_data_3_1_UNCONNECTED,
      trd_host_cmd_data(3, 0) => NLW_amb_trd_host_cmd_data_3_0_UNCONNECTED,
      trd_host_cmd_data(2, 15) => NLW_amb_trd_host_cmd_data_2_15_UNCONNECTED,
      trd_host_cmd_data(2, 14) => NLW_amb_trd_host_cmd_data_2_14_UNCONNECTED,
      trd_host_cmd_data(2, 13) => NLW_amb_trd_host_cmd_data_2_13_UNCONNECTED,
      trd_host_cmd_data(2, 12) => NLW_amb_trd_host_cmd_data_2_12_UNCONNECTED,
      trd_host_cmd_data(2, 11) => NLW_amb_trd_host_cmd_data_2_11_UNCONNECTED,
      trd_host_cmd_data(2, 10) => NLW_amb_trd_host_cmd_data_2_10_UNCONNECTED,
      trd_host_cmd_data(2, 9) => NLW_amb_trd_host_cmd_data_2_9_UNCONNECTED,
      trd_host_cmd_data(2, 8) => NLW_amb_trd_host_cmd_data_2_8_UNCONNECTED,
      trd_host_cmd_data(2, 7) => NLW_amb_trd_host_cmd_data_2_7_UNCONNECTED,
      trd_host_cmd_data(2, 6) => NLW_amb_trd_host_cmd_data_2_6_UNCONNECTED,
      trd_host_cmd_data(2, 5) => NLW_amb_trd_host_cmd_data_2_5_UNCONNECTED,
      trd_host_cmd_data(2, 4) => NLW_amb_trd_host_cmd_data_2_4_UNCONNECTED,
      trd_host_cmd_data(2, 3) => NLW_amb_trd_host_cmd_data_2_3_UNCONNECTED,
      trd_host_cmd_data(2, 2) => NLW_amb_trd_host_cmd_data_2_2_UNCONNECTED,
      trd_host_cmd_data(2, 1) => NLW_amb_trd_host_cmd_data_2_1_UNCONNECTED,
      trd_host_cmd_data(2, 0) => NLW_amb_trd_host_cmd_data_2_0_UNCONNECTED,
      trd_host_cmd_data(1, 15) => trd_host_cmd_data_1_15_Q,
      trd_host_cmd_data(1, 14) => trd_host_cmd_data_1_14_Q,
      trd_host_cmd_data(1, 13) => trd_host_cmd_data_1_13_Q,
      trd_host_cmd_data(1, 12) => trd_host_cmd_data_1_12_Q,
      trd_host_cmd_data(1, 11) => trd_host_cmd_data_1_11_Q,
      trd_host_cmd_data(1, 10) => trd_host_cmd_data_1_10_Q,
      trd_host_cmd_data(1, 9) => trd_host_cmd_data_1_9_Q,
      trd_host_cmd_data(1, 8) => trd_host_cmd_data_1_8_Q,
      trd_host_cmd_data(1, 7) => trd_host_cmd_data_1_7_Q,
      trd_host_cmd_data(1, 6) => trd_host_cmd_data_1_6_Q,
      trd_host_cmd_data(1, 5) => trd_host_cmd_data_1_5_Q,
      trd_host_cmd_data(1, 4) => trd_host_cmd_data_1_4_Q,
      trd_host_cmd_data(1, 3) => trd_host_cmd_data_1_3_Q,
      trd_host_cmd_data(1, 2) => trd_host_cmd_data_1_2_Q,
      trd_host_cmd_data(1, 1) => trd_host_cmd_data_1_1_Q,
      trd_host_cmd_data(1, 0) => trd_host_cmd_data_1_0_Q,
      trd_host_cmd_data(0, 15) => trd_host_cmd_data_0_15_Q,
      trd_host_cmd_data(0, 14) => trd_host_cmd_data_0_14_Q,
      trd_host_cmd_data(0, 13) => trd_host_cmd_data_0_13_Q,
      trd_host_cmd_data(0, 12) => trd_host_cmd_data_0_12_Q,
      trd_host_cmd_data(0, 11) => trd_host_cmd_data_0_11_Q,
      trd_host_cmd_data(0, 10) => trd_host_cmd_data_0_10_Q,
      trd_host_cmd_data(0, 9) => trd_host_cmd_data_0_9_Q,
      trd_host_cmd_data(0, 8) => trd_host_cmd_data_0_8_Q,
      trd_host_cmd_data(0, 7) => trd_host_cmd_data_0_7_Q,
      trd_host_cmd_data(0, 6) => trd_host_cmd_data_0_6_Q,
      trd_host_cmd_data(0, 5) => trd_host_cmd_data_0_5_Q,
      trd_host_cmd_data(0, 4) => trd_host_cmd_data_0_4_Q,
      trd_host_cmd_data(0, 3) => trd_host_cmd_data_0_3_Q,
      trd_host_cmd_data(0, 2) => trd_host_cmd_data_0_2_Q,
      trd_host_cmd_data(0, 1) => trd_host_cmd_data_0_1_Q,
      trd_host_cmd_data(0, 0) => trd_host_cmd_data_0_0_Q,
      trd_data(15, 63) => N0,
      trd_data(15, 62) => N0,
      trd_data(15, 61) => N0,
      trd_data(15, 60) => N0,
      trd_data(15, 59) => N0,
      trd_data(15, 58) => N0,
      trd_data(15, 57) => N0,
      trd_data(15, 56) => N0,
      trd_data(15, 55) => N0,
      trd_data(15, 54) => N0,
      trd_data(15, 53) => N0,
      trd_data(15, 52) => N0,
      trd_data(15, 51) => N0,
      trd_data(15, 50) => N0,
      trd_data(15, 49) => N0,
      trd_data(15, 48) => N0,
      trd_data(15, 47) => N0,
      trd_data(15, 46) => N0,
      trd_data(15, 45) => N0,
      trd_data(15, 44) => N0,
      trd_data(15, 43) => N0,
      trd_data(15, 42) => N0,
      trd_data(15, 41) => N0,
      trd_data(15, 40) => N0,
      trd_data(15, 39) => N0,
      trd_data(15, 38) => N0,
      trd_data(15, 37) => N0,
      trd_data(15, 36) => N0,
      trd_data(15, 35) => N0,
      trd_data(15, 34) => N0,
      trd_data(15, 33) => N0,
      trd_data(15, 32) => N0,
      trd_data(15, 31) => N0,
      trd_data(15, 30) => N0,
      trd_data(15, 29) => N0,
      trd_data(15, 28) => N0,
      trd_data(15, 27) => N0,
      trd_data(15, 26) => N0,
      trd_data(15, 25) => N0,
      trd_data(15, 24) => N0,
      trd_data(15, 23) => N0,
      trd_data(15, 22) => N0,
      trd_data(15, 21) => N0,
      trd_data(15, 20) => N0,
      trd_data(15, 19) => N0,
      trd_data(15, 18) => N0,
      trd_data(15, 17) => N0,
      trd_data(15, 16) => N0,
      trd_data(15, 15) => N0,
      trd_data(15, 14) => N0,
      trd_data(15, 13) => N0,
      trd_data(15, 12) => N0,
      trd_data(15, 11) => N0,
      trd_data(15, 10) => N0,
      trd_data(15, 9) => N0,
      trd_data(15, 8) => N0,
      trd_data(15, 7) => N0,
      trd_data(15, 6) => N0,
      trd_data(15, 5) => N0,
      trd_data(15, 4) => N0,
      trd_data(15, 3) => N0,
      trd_data(15, 2) => N0,
      trd_data(15, 1) => N0,
      trd_data(15, 0) => N0,
      trd_data(14, 63) => N0,
      trd_data(14, 62) => N0,
      trd_data(14, 61) => N0,
      trd_data(14, 60) => N0,
      trd_data(14, 59) => N0,
      trd_data(14, 58) => N0,
      trd_data(14, 57) => N0,
      trd_data(14, 56) => N0,
      trd_data(14, 55) => N0,
      trd_data(14, 54) => N0,
      trd_data(14, 53) => N0,
      trd_data(14, 52) => N0,
      trd_data(14, 51) => N0,
      trd_data(14, 50) => N0,
      trd_data(14, 49) => N0,
      trd_data(14, 48) => N0,
      trd_data(14, 47) => N0,
      trd_data(14, 46) => N0,
      trd_data(14, 45) => N0,
      trd_data(14, 44) => N0,
      trd_data(14, 43) => N0,
      trd_data(14, 42) => N0,
      trd_data(14, 41) => N0,
      trd_data(14, 40) => N0,
      trd_data(14, 39) => N0,
      trd_data(14, 38) => N0,
      trd_data(14, 37) => N0,
      trd_data(14, 36) => N0,
      trd_data(14, 35) => N0,
      trd_data(14, 34) => N0,
      trd_data(14, 33) => N0,
      trd_data(14, 32) => N0,
      trd_data(14, 31) => N0,
      trd_data(14, 30) => N0,
      trd_data(14, 29) => N0,
      trd_data(14, 28) => N0,
      trd_data(14, 27) => N0,
      trd_data(14, 26) => N0,
      trd_data(14, 25) => N0,
      trd_data(14, 24) => N0,
      trd_data(14, 23) => N0,
      trd_data(14, 22) => N0,
      trd_data(14, 21) => N0,
      trd_data(14, 20) => N0,
      trd_data(14, 19) => N0,
      trd_data(14, 18) => N0,
      trd_data(14, 17) => N0,
      trd_data(14, 16) => N0,
      trd_data(14, 15) => N0,
      trd_data(14, 14) => N0,
      trd_data(14, 13) => N0,
      trd_data(14, 12) => N0,
      trd_data(14, 11) => N0,
      trd_data(14, 10) => N0,
      trd_data(14, 9) => N0,
      trd_data(14, 8) => N0,
      trd_data(14, 7) => N0,
      trd_data(14, 6) => N0,
      trd_data(14, 5) => N0,
      trd_data(14, 4) => N0,
      trd_data(14, 3) => N0,
      trd_data(14, 2) => N0,
      trd_data(14, 1) => N0,
      trd_data(14, 0) => N0,
      trd_data(13, 63) => N0,
      trd_data(13, 62) => N0,
      trd_data(13, 61) => N0,
      trd_data(13, 60) => N0,
      trd_data(13, 59) => N0,
      trd_data(13, 58) => N0,
      trd_data(13, 57) => N0,
      trd_data(13, 56) => N0,
      trd_data(13, 55) => N0,
      trd_data(13, 54) => N0,
      trd_data(13, 53) => N0,
      trd_data(13, 52) => N0,
      trd_data(13, 51) => N0,
      trd_data(13, 50) => N0,
      trd_data(13, 49) => N0,
      trd_data(13, 48) => N0,
      trd_data(13, 47) => N0,
      trd_data(13, 46) => N0,
      trd_data(13, 45) => N0,
      trd_data(13, 44) => N0,
      trd_data(13, 43) => N0,
      trd_data(13, 42) => N0,
      trd_data(13, 41) => N0,
      trd_data(13, 40) => N0,
      trd_data(13, 39) => N0,
      trd_data(13, 38) => N0,
      trd_data(13, 37) => N0,
      trd_data(13, 36) => N0,
      trd_data(13, 35) => N0,
      trd_data(13, 34) => N0,
      trd_data(13, 33) => N0,
      trd_data(13, 32) => N0,
      trd_data(13, 31) => N0,
      trd_data(13, 30) => N0,
      trd_data(13, 29) => N0,
      trd_data(13, 28) => N0,
      trd_data(13, 27) => N0,
      trd_data(13, 26) => N0,
      trd_data(13, 25) => N0,
      trd_data(13, 24) => N0,
      trd_data(13, 23) => N0,
      trd_data(13, 22) => N0,
      trd_data(13, 21) => N0,
      trd_data(13, 20) => N0,
      trd_data(13, 19) => N0,
      trd_data(13, 18) => N0,
      trd_data(13, 17) => N0,
      trd_data(13, 16) => N0,
      trd_data(13, 15) => N0,
      trd_data(13, 14) => N0,
      trd_data(13, 13) => N0,
      trd_data(13, 12) => N0,
      trd_data(13, 11) => N0,
      trd_data(13, 10) => N0,
      trd_data(13, 9) => N0,
      trd_data(13, 8) => N0,
      trd_data(13, 7) => N0,
      trd_data(13, 6) => N0,
      trd_data(13, 5) => N0,
      trd_data(13, 4) => N0,
      trd_data(13, 3) => N0,
      trd_data(13, 2) => N0,
      trd_data(13, 1) => N0,
      trd_data(13, 0) => N0,
      trd_data(12, 63) => N0,
      trd_data(12, 62) => N0,
      trd_data(12, 61) => N0,
      trd_data(12, 60) => N0,
      trd_data(12, 59) => N0,
      trd_data(12, 58) => N0,
      trd_data(12, 57) => N0,
      trd_data(12, 56) => N0,
      trd_data(12, 55) => N0,
      trd_data(12, 54) => N0,
      trd_data(12, 53) => N0,
      trd_data(12, 52) => N0,
      trd_data(12, 51) => N0,
      trd_data(12, 50) => N0,
      trd_data(12, 49) => N0,
      trd_data(12, 48) => N0,
      trd_data(12, 47) => N0,
      trd_data(12, 46) => N0,
      trd_data(12, 45) => N0,
      trd_data(12, 44) => N0,
      trd_data(12, 43) => N0,
      trd_data(12, 42) => N0,
      trd_data(12, 41) => N0,
      trd_data(12, 40) => N0,
      trd_data(12, 39) => N0,
      trd_data(12, 38) => N0,
      trd_data(12, 37) => N0,
      trd_data(12, 36) => N0,
      trd_data(12, 35) => N0,
      trd_data(12, 34) => N0,
      trd_data(12, 33) => N0,
      trd_data(12, 32) => N0,
      trd_data(12, 31) => N0,
      trd_data(12, 30) => N0,
      trd_data(12, 29) => N0,
      trd_data(12, 28) => N0,
      trd_data(12, 27) => N0,
      trd_data(12, 26) => N0,
      trd_data(12, 25) => N0,
      trd_data(12, 24) => N0,
      trd_data(12, 23) => N0,
      trd_data(12, 22) => N0,
      trd_data(12, 21) => N0,
      trd_data(12, 20) => N0,
      trd_data(12, 19) => N0,
      trd_data(12, 18) => N0,
      trd_data(12, 17) => N0,
      trd_data(12, 16) => N0,
      trd_data(12, 15) => N0,
      trd_data(12, 14) => N0,
      trd_data(12, 13) => N0,
      trd_data(12, 12) => N0,
      trd_data(12, 11) => N0,
      trd_data(12, 10) => N0,
      trd_data(12, 9) => N0,
      trd_data(12, 8) => N0,
      trd_data(12, 7) => N0,
      trd_data(12, 6) => N0,
      trd_data(12, 5) => N0,
      trd_data(12, 4) => N0,
      trd_data(12, 3) => N0,
      trd_data(12, 2) => N0,
      trd_data(12, 1) => N0,
      trd_data(12, 0) => N0,
      trd_data(11, 63) => N0,
      trd_data(11, 62) => N0,
      trd_data(11, 61) => N0,
      trd_data(11, 60) => N0,
      trd_data(11, 59) => N0,
      trd_data(11, 58) => N0,
      trd_data(11, 57) => N0,
      trd_data(11, 56) => N0,
      trd_data(11, 55) => N0,
      trd_data(11, 54) => N0,
      trd_data(11, 53) => N0,
      trd_data(11, 52) => N0,
      trd_data(11, 51) => N0,
      trd_data(11, 50) => N0,
      trd_data(11, 49) => N0,
      trd_data(11, 48) => N0,
      trd_data(11, 47) => N0,
      trd_data(11, 46) => N0,
      trd_data(11, 45) => N0,
      trd_data(11, 44) => N0,
      trd_data(11, 43) => N0,
      trd_data(11, 42) => N0,
      trd_data(11, 41) => N0,
      trd_data(11, 40) => N0,
      trd_data(11, 39) => N0,
      trd_data(11, 38) => N0,
      trd_data(11, 37) => N0,
      trd_data(11, 36) => N0,
      trd_data(11, 35) => N0,
      trd_data(11, 34) => N0,
      trd_data(11, 33) => N0,
      trd_data(11, 32) => N0,
      trd_data(11, 31) => N0,
      trd_data(11, 30) => N0,
      trd_data(11, 29) => N0,
      trd_data(11, 28) => N0,
      trd_data(11, 27) => N0,
      trd_data(11, 26) => N0,
      trd_data(11, 25) => N0,
      trd_data(11, 24) => N0,
      trd_data(11, 23) => N0,
      trd_data(11, 22) => N0,
      trd_data(11, 21) => N0,
      trd_data(11, 20) => N0,
      trd_data(11, 19) => N0,
      trd_data(11, 18) => N0,
      trd_data(11, 17) => N0,
      trd_data(11, 16) => N0,
      trd_data(11, 15) => N0,
      trd_data(11, 14) => N0,
      trd_data(11, 13) => N0,
      trd_data(11, 12) => N0,
      trd_data(11, 11) => N0,
      trd_data(11, 10) => N0,
      trd_data(11, 9) => N0,
      trd_data(11, 8) => N0,
      trd_data(11, 7) => N0,
      trd_data(11, 6) => N0,
      trd_data(11, 5) => N0,
      trd_data(11, 4) => N0,
      trd_data(11, 3) => N0,
      trd_data(11, 2) => N0,
      trd_data(11, 1) => N0,
      trd_data(11, 0) => N0,
      trd_data(10, 63) => N0,
      trd_data(10, 62) => N0,
      trd_data(10, 61) => N0,
      trd_data(10, 60) => N0,
      trd_data(10, 59) => N0,
      trd_data(10, 58) => N0,
      trd_data(10, 57) => N0,
      trd_data(10, 56) => N0,
      trd_data(10, 55) => N0,
      trd_data(10, 54) => N0,
      trd_data(10, 53) => N0,
      trd_data(10, 52) => N0,
      trd_data(10, 51) => N0,
      trd_data(10, 50) => N0,
      trd_data(10, 49) => N0,
      trd_data(10, 48) => N0,
      trd_data(10, 47) => N0,
      trd_data(10, 46) => N0,
      trd_data(10, 45) => N0,
      trd_data(10, 44) => N0,
      trd_data(10, 43) => N0,
      trd_data(10, 42) => N0,
      trd_data(10, 41) => N0,
      trd_data(10, 40) => N0,
      trd_data(10, 39) => N0,
      trd_data(10, 38) => N0,
      trd_data(10, 37) => N0,
      trd_data(10, 36) => N0,
      trd_data(10, 35) => N0,
      trd_data(10, 34) => N0,
      trd_data(10, 33) => N0,
      trd_data(10, 32) => N0,
      trd_data(10, 31) => N0,
      trd_data(10, 30) => N0,
      trd_data(10, 29) => N0,
      trd_data(10, 28) => N0,
      trd_data(10, 27) => N0,
      trd_data(10, 26) => N0,
      trd_data(10, 25) => N0,
      trd_data(10, 24) => N0,
      trd_data(10, 23) => N0,
      trd_data(10, 22) => N0,
      trd_data(10, 21) => N0,
      trd_data(10, 20) => N0,
      trd_data(10, 19) => N0,
      trd_data(10, 18) => N0,
      trd_data(10, 17) => N0,
      trd_data(10, 16) => N0,
      trd_data(10, 15) => N0,
      trd_data(10, 14) => N0,
      trd_data(10, 13) => N0,
      trd_data(10, 12) => N0,
      trd_data(10, 11) => N0,
      trd_data(10, 10) => N0,
      trd_data(10, 9) => N0,
      trd_data(10, 8) => N0,
      trd_data(10, 7) => N0,
      trd_data(10, 6) => N0,
      trd_data(10, 5) => N0,
      trd_data(10, 4) => N0,
      trd_data(10, 3) => N0,
      trd_data(10, 2) => N0,
      trd_data(10, 1) => N0,
      trd_data(10, 0) => N0,
      trd_data(9, 63) => N0,
      trd_data(9, 62) => N0,
      trd_data(9, 61) => N0,
      trd_data(9, 60) => N0,
      trd_data(9, 59) => N0,
      trd_data(9, 58) => N0,
      trd_data(9, 57) => N0,
      trd_data(9, 56) => N0,
      trd_data(9, 55) => N0,
      trd_data(9, 54) => N0,
      trd_data(9, 53) => N0,
      trd_data(9, 52) => N0,
      trd_data(9, 51) => N0,
      trd_data(9, 50) => N0,
      trd_data(9, 49) => N0,
      trd_data(9, 48) => N0,
      trd_data(9, 47) => N0,
      trd_data(9, 46) => N0,
      trd_data(9, 45) => N0,
      trd_data(9, 44) => N0,
      trd_data(9, 43) => N0,
      trd_data(9, 42) => N0,
      trd_data(9, 41) => N0,
      trd_data(9, 40) => N0,
      trd_data(9, 39) => N0,
      trd_data(9, 38) => N0,
      trd_data(9, 37) => N0,
      trd_data(9, 36) => N0,
      trd_data(9, 35) => N0,
      trd_data(9, 34) => N0,
      trd_data(9, 33) => N0,
      trd_data(9, 32) => N0,
      trd_data(9, 31) => N0,
      trd_data(9, 30) => N0,
      trd_data(9, 29) => N0,
      trd_data(9, 28) => N0,
      trd_data(9, 27) => N0,
      trd_data(9, 26) => N0,
      trd_data(9, 25) => N0,
      trd_data(9, 24) => N0,
      trd_data(9, 23) => N0,
      trd_data(9, 22) => N0,
      trd_data(9, 21) => N0,
      trd_data(9, 20) => N0,
      trd_data(9, 19) => N0,
      trd_data(9, 18) => N0,
      trd_data(9, 17) => N0,
      trd_data(9, 16) => N0,
      trd_data(9, 15) => N0,
      trd_data(9, 14) => N0,
      trd_data(9, 13) => N0,
      trd_data(9, 12) => N0,
      trd_data(9, 11) => N0,
      trd_data(9, 10) => N0,
      trd_data(9, 9) => N0,
      trd_data(9, 8) => N0,
      trd_data(9, 7) => N0,
      trd_data(9, 6) => N0,
      trd_data(9, 5) => N0,
      trd_data(9, 4) => N0,
      trd_data(9, 3) => N0,
      trd_data(9, 2) => N0,
      trd_data(9, 1) => N0,
      trd_data(9, 0) => N0,
      trd_data(8, 63) => N0,
      trd_data(8, 62) => N0,
      trd_data(8, 61) => N0,
      trd_data(8, 60) => N0,
      trd_data(8, 59) => N0,
      trd_data(8, 58) => N0,
      trd_data(8, 57) => N0,
      trd_data(8, 56) => N0,
      trd_data(8, 55) => N0,
      trd_data(8, 54) => N0,
      trd_data(8, 53) => N0,
      trd_data(8, 52) => N0,
      trd_data(8, 51) => N0,
      trd_data(8, 50) => N0,
      trd_data(8, 49) => N0,
      trd_data(8, 48) => N0,
      trd_data(8, 47) => N0,
      trd_data(8, 46) => N0,
      trd_data(8, 45) => N0,
      trd_data(8, 44) => N0,
      trd_data(8, 43) => N0,
      trd_data(8, 42) => N0,
      trd_data(8, 41) => N0,
      trd_data(8, 40) => N0,
      trd_data(8, 39) => N0,
      trd_data(8, 38) => N0,
      trd_data(8, 37) => N0,
      trd_data(8, 36) => N0,
      trd_data(8, 35) => N0,
      trd_data(8, 34) => N0,
      trd_data(8, 33) => N0,
      trd_data(8, 32) => N0,
      trd_data(8, 31) => N0,
      trd_data(8, 30) => N0,
      trd_data(8, 29) => N0,
      trd_data(8, 28) => N0,
      trd_data(8, 27) => N0,
      trd_data(8, 26) => N0,
      trd_data(8, 25) => N0,
      trd_data(8, 24) => N0,
      trd_data(8, 23) => N0,
      trd_data(8, 22) => N0,
      trd_data(8, 21) => N0,
      trd_data(8, 20) => N0,
      trd_data(8, 19) => N0,
      trd_data(8, 18) => N0,
      trd_data(8, 17) => N0,
      trd_data(8, 16) => N0,
      trd_data(8, 15) => N0,
      trd_data(8, 14) => N0,
      trd_data(8, 13) => N0,
      trd_data(8, 12) => N0,
      trd_data(8, 11) => N0,
      trd_data(8, 10) => N0,
      trd_data(8, 9) => N0,
      trd_data(8, 8) => N0,
      trd_data(8, 7) => N0,
      trd_data(8, 6) => N0,
      trd_data(8, 5) => N0,
      trd_data(8, 4) => N0,
      trd_data(8, 3) => N0,
      trd_data(8, 2) => N0,
      trd_data(8, 1) => N0,
      trd_data(8, 0) => N0,
      trd_data(7, 63) => N0,
      trd_data(7, 62) => N0,
      trd_data(7, 61) => N0,
      trd_data(7, 60) => N0,
      trd_data(7, 59) => N0,
      trd_data(7, 58) => N0,
      trd_data(7, 57) => N0,
      trd_data(7, 56) => N0,
      trd_data(7, 55) => N0,
      trd_data(7, 54) => N0,
      trd_data(7, 53) => N0,
      trd_data(7, 52) => N0,
      trd_data(7, 51) => N0,
      trd_data(7, 50) => N0,
      trd_data(7, 49) => N0,
      trd_data(7, 48) => N0,
      trd_data(7, 47) => N0,
      trd_data(7, 46) => N0,
      trd_data(7, 45) => N0,
      trd_data(7, 44) => N0,
      trd_data(7, 43) => N0,
      trd_data(7, 42) => N0,
      trd_data(7, 41) => N0,
      trd_data(7, 40) => N0,
      trd_data(7, 39) => N0,
      trd_data(7, 38) => N0,
      trd_data(7, 37) => N0,
      trd_data(7, 36) => N0,
      trd_data(7, 35) => N0,
      trd_data(7, 34) => N0,
      trd_data(7, 33) => N0,
      trd_data(7, 32) => N0,
      trd_data(7, 31) => N0,
      trd_data(7, 30) => N0,
      trd_data(7, 29) => N0,
      trd_data(7, 28) => N0,
      trd_data(7, 27) => N0,
      trd_data(7, 26) => N0,
      trd_data(7, 25) => N0,
      trd_data(7, 24) => N0,
      trd_data(7, 23) => N0,
      trd_data(7, 22) => N0,
      trd_data(7, 21) => N0,
      trd_data(7, 20) => N0,
      trd_data(7, 19) => N0,
      trd_data(7, 18) => N0,
      trd_data(7, 17) => N0,
      trd_data(7, 16) => N0,
      trd_data(7, 15) => N0,
      trd_data(7, 14) => N0,
      trd_data(7, 13) => N0,
      trd_data(7, 12) => N0,
      trd_data(7, 11) => N0,
      trd_data(7, 10) => N0,
      trd_data(7, 9) => N0,
      trd_data(7, 8) => N0,
      trd_data(7, 7) => N0,
      trd_data(7, 6) => N0,
      trd_data(7, 5) => N0,
      trd_data(7, 4) => N0,
      trd_data(7, 3) => N0,
      trd_data(7, 2) => N0,
      trd_data(7, 1) => N0,
      trd_data(7, 0) => N0,
      trd_data(6, 63) => trd_data_6_63_Q,
      trd_data(6, 62) => trd_data_6_62_Q,
      trd_data(6, 61) => trd_data_6_61_Q,
      trd_data(6, 60) => trd_data_6_60_Q,
      trd_data(6, 59) => trd_data_6_59_Q,
      trd_data(6, 58) => trd_data_6_58_Q,
      trd_data(6, 57) => trd_data_6_57_Q,
      trd_data(6, 56) => trd_data_6_56_Q,
      trd_data(6, 55) => trd_data_6_55_Q,
      trd_data(6, 54) => trd_data_6_54_Q,
      trd_data(6, 53) => trd_data_6_53_Q,
      trd_data(6, 52) => trd_data_6_52_Q,
      trd_data(6, 51) => trd_data_6_51_Q,
      trd_data(6, 50) => trd_data_6_50_Q,
      trd_data(6, 49) => trd_data_6_49_Q,
      trd_data(6, 48) => trd_data_6_48_Q,
      trd_data(6, 47) => trd_data_6_47_Q,
      trd_data(6, 46) => trd_data_6_46_Q,
      trd_data(6, 45) => trd_data_6_45_Q,
      trd_data(6, 44) => trd_data_6_44_Q,
      trd_data(6, 43) => trd_data_6_43_Q,
      trd_data(6, 42) => trd_data_6_42_Q,
      trd_data(6, 41) => trd_data_6_41_Q,
      trd_data(6, 40) => trd_data_6_40_Q,
      trd_data(6, 39) => trd_data_6_39_Q,
      trd_data(6, 38) => trd_data_6_38_Q,
      trd_data(6, 37) => trd_data_6_37_Q,
      trd_data(6, 36) => trd_data_6_36_Q,
      trd_data(6, 35) => trd_data_6_35_Q,
      trd_data(6, 34) => trd_data_6_34_Q,
      trd_data(6, 33) => trd_data_6_33_Q,
      trd_data(6, 32) => trd_data_6_32_Q,
      trd_data(6, 31) => trd_data_6_31_Q,
      trd_data(6, 30) => trd_data_6_30_Q,
      trd_data(6, 29) => trd_data_6_29_Q,
      trd_data(6, 28) => trd_data_6_28_Q,
      trd_data(6, 27) => trd_data_6_27_Q,
      trd_data(6, 26) => trd_data_6_26_Q,
      trd_data(6, 25) => trd_data_6_25_Q,
      trd_data(6, 24) => trd_data_6_24_Q,
      trd_data(6, 23) => trd_data_6_23_Q,
      trd_data(6, 22) => trd_data_6_22_Q,
      trd_data(6, 21) => trd_data_6_21_Q,
      trd_data(6, 20) => trd_data_6_20_Q,
      trd_data(6, 19) => trd_data_6_19_Q,
      trd_data(6, 18) => trd_data_6_18_Q,
      trd_data(6, 17) => trd_data_6_17_Q,
      trd_data(6, 16) => trd_data_6_16_Q,
      trd_data(6, 15) => trd_data_6_15_Q,
      trd_data(6, 14) => trd_data_6_14_Q,
      trd_data(6, 13) => trd_data_6_13_Q,
      trd_data(6, 12) => trd_data_6_12_Q,
      trd_data(6, 11) => trd_data_6_11_Q,
      trd_data(6, 10) => trd_data_6_10_Q,
      trd_data(6, 9) => trd_data_6_9_Q,
      trd_data(6, 8) => trd_data_6_8_Q,
      trd_data(6, 7) => trd_data_6_7_Q,
      trd_data(6, 6) => trd_data_6_6_Q,
      trd_data(6, 5) => trd_data_6_5_Q,
      trd_data(6, 4) => trd_data_6_4_Q,
      trd_data(6, 3) => trd_data_6_3_Q,
      trd_data(6, 2) => trd_data_6_2_Q,
      trd_data(6, 1) => trd_data_6_1_Q,
      trd_data(6, 0) => trd_data_6_0_Q,
      trd_data(5, 63) => N0,
      trd_data(5, 62) => N0,
      trd_data(5, 61) => N0,
      trd_data(5, 60) => N0,
      trd_data(5, 59) => N0,
      trd_data(5, 58) => N0,
      trd_data(5, 57) => N0,
      trd_data(5, 56) => N0,
      trd_data(5, 55) => N0,
      trd_data(5, 54) => N0,
      trd_data(5, 53) => N0,
      trd_data(5, 52) => N0,
      trd_data(5, 51) => N0,
      trd_data(5, 50) => N0,
      trd_data(5, 49) => N0,
      trd_data(5, 48) => N0,
      trd_data(5, 47) => N0,
      trd_data(5, 46) => N0,
      trd_data(5, 45) => N0,
      trd_data(5, 44) => N0,
      trd_data(5, 43) => N0,
      trd_data(5, 42) => N0,
      trd_data(5, 41) => N0,
      trd_data(5, 40) => N0,
      trd_data(5, 39) => N0,
      trd_data(5, 38) => N0,
      trd_data(5, 37) => N0,
      trd_data(5, 36) => N0,
      trd_data(5, 35) => N0,
      trd_data(5, 34) => N0,
      trd_data(5, 33) => N0,
      trd_data(5, 32) => N0,
      trd_data(5, 31) => N0,
      trd_data(5, 30) => N0,
      trd_data(5, 29) => N0,
      trd_data(5, 28) => N0,
      trd_data(5, 27) => N0,
      trd_data(5, 26) => N0,
      trd_data(5, 25) => N0,
      trd_data(5, 24) => N0,
      trd_data(5, 23) => N0,
      trd_data(5, 22) => N0,
      trd_data(5, 21) => N0,
      trd_data(5, 20) => N0,
      trd_data(5, 19) => N0,
      trd_data(5, 18) => N0,
      trd_data(5, 17) => N0,
      trd_data(5, 16) => N0,
      trd_data(5, 15) => N0,
      trd_data(5, 14) => N0,
      trd_data(5, 13) => N0,
      trd_data(5, 12) => N0,
      trd_data(5, 11) => N0,
      trd_data(5, 10) => N0,
      trd_data(5, 9) => N0,
      trd_data(5, 8) => N0,
      trd_data(5, 7) => N0,
      trd_data(5, 6) => N0,
      trd_data(5, 5) => N0,
      trd_data(5, 4) => N0,
      trd_data(5, 3) => N0,
      trd_data(5, 2) => N0,
      trd_data(5, 1) => N0,
      trd_data(5, 0) => N0,
      trd_data(4, 63) => N0,
      trd_data(4, 62) => N0,
      trd_data(4, 61) => N0,
      trd_data(4, 60) => N0,
      trd_data(4, 59) => N0,
      trd_data(4, 58) => N0,
      trd_data(4, 57) => N0,
      trd_data(4, 56) => N0,
      trd_data(4, 55) => N0,
      trd_data(4, 54) => N0,
      trd_data(4, 53) => N0,
      trd_data(4, 52) => N0,
      trd_data(4, 51) => N0,
      trd_data(4, 50) => N0,
      trd_data(4, 49) => N0,
      trd_data(4, 48) => N0,
      trd_data(4, 47) => N0,
      trd_data(4, 46) => N0,
      trd_data(4, 45) => N0,
      trd_data(4, 44) => N0,
      trd_data(4, 43) => N0,
      trd_data(4, 42) => N0,
      trd_data(4, 41) => N0,
      trd_data(4, 40) => N0,
      trd_data(4, 39) => N0,
      trd_data(4, 38) => N0,
      trd_data(4, 37) => N0,
      trd_data(4, 36) => N0,
      trd_data(4, 35) => N0,
      trd_data(4, 34) => N0,
      trd_data(4, 33) => N0,
      trd_data(4, 32) => N0,
      trd_data(4, 31) => N0,
      trd_data(4, 30) => N0,
      trd_data(4, 29) => N0,
      trd_data(4, 28) => N0,
      trd_data(4, 27) => N0,
      trd_data(4, 26) => N0,
      trd_data(4, 25) => N0,
      trd_data(4, 24) => N0,
      trd_data(4, 23) => N0,
      trd_data(4, 22) => N0,
      trd_data(4, 21) => N0,
      trd_data(4, 20) => N0,
      trd_data(4, 19) => N0,
      trd_data(4, 18) => N0,
      trd_data(4, 17) => N0,
      trd_data(4, 16) => N0,
      trd_data(4, 15) => N0,
      trd_data(4, 14) => N0,
      trd_data(4, 13) => N0,
      trd_data(4, 12) => N0,
      trd_data(4, 11) => N0,
      trd_data(4, 10) => N0,
      trd_data(4, 9) => N0,
      trd_data(4, 8) => N0,
      trd_data(4, 7) => N0,
      trd_data(4, 6) => N0,
      trd_data(4, 5) => N0,
      trd_data(4, 4) => N0,
      trd_data(4, 3) => N0,
      trd_data(4, 2) => N0,
      trd_data(4, 1) => N0,
      trd_data(4, 0) => N0,
      trd_data(3, 63) => N0,
      trd_data(3, 62) => N0,
      trd_data(3, 61) => N0,
      trd_data(3, 60) => N0,
      trd_data(3, 59) => N0,
      trd_data(3, 58) => N0,
      trd_data(3, 57) => N0,
      trd_data(3, 56) => N0,
      trd_data(3, 55) => N0,
      trd_data(3, 54) => N0,
      trd_data(3, 53) => N0,
      trd_data(3, 52) => N0,
      trd_data(3, 51) => N0,
      trd_data(3, 50) => N0,
      trd_data(3, 49) => N0,
      trd_data(3, 48) => N0,
      trd_data(3, 47) => N0,
      trd_data(3, 46) => N0,
      trd_data(3, 45) => N0,
      trd_data(3, 44) => N0,
      trd_data(3, 43) => N0,
      trd_data(3, 42) => N0,
      trd_data(3, 41) => N0,
      trd_data(3, 40) => N0,
      trd_data(3, 39) => N0,
      trd_data(3, 38) => N0,
      trd_data(3, 37) => N0,
      trd_data(3, 36) => N0,
      trd_data(3, 35) => N0,
      trd_data(3, 34) => N0,
      trd_data(3, 33) => N0,
      trd_data(3, 32) => N0,
      trd_data(3, 31) => N0,
      trd_data(3, 30) => N0,
      trd_data(3, 29) => N0,
      trd_data(3, 28) => N0,
      trd_data(3, 27) => N0,
      trd_data(3, 26) => N0,
      trd_data(3, 25) => N0,
      trd_data(3, 24) => N0,
      trd_data(3, 23) => N0,
      trd_data(3, 22) => N0,
      trd_data(3, 21) => N0,
      trd_data(3, 20) => N0,
      trd_data(3, 19) => N0,
      trd_data(3, 18) => N0,
      trd_data(3, 17) => N0,
      trd_data(3, 16) => N0,
      trd_data(3, 15) => N0,
      trd_data(3, 14) => N0,
      trd_data(3, 13) => N0,
      trd_data(3, 12) => N0,
      trd_data(3, 11) => N0,
      trd_data(3, 10) => N0,
      trd_data(3, 9) => N0,
      trd_data(3, 8) => N0,
      trd_data(3, 7) => N0,
      trd_data(3, 6) => N0,
      trd_data(3, 5) => N0,
      trd_data(3, 4) => N0,
      trd_data(3, 3) => N0,
      trd_data(3, 2) => N0,
      trd_data(3, 1) => N0,
      trd_data(3, 0) => N0,
      trd_data(2, 63) => N0,
      trd_data(2, 62) => N0,
      trd_data(2, 61) => N0,
      trd_data(2, 60) => N0,
      trd_data(2, 59) => N0,
      trd_data(2, 58) => N0,
      trd_data(2, 57) => N0,
      trd_data(2, 56) => N0,
      trd_data(2, 55) => N0,
      trd_data(2, 54) => N0,
      trd_data(2, 53) => N0,
      trd_data(2, 52) => N0,
      trd_data(2, 51) => N0,
      trd_data(2, 50) => N0,
      trd_data(2, 49) => N0,
      trd_data(2, 48) => N0,
      trd_data(2, 47) => N0,
      trd_data(2, 46) => N0,
      trd_data(2, 45) => N0,
      trd_data(2, 44) => N0,
      trd_data(2, 43) => N0,
      trd_data(2, 42) => N0,
      trd_data(2, 41) => N0,
      trd_data(2, 40) => N0,
      trd_data(2, 39) => N0,
      trd_data(2, 38) => N0,
      trd_data(2, 37) => N0,
      trd_data(2, 36) => N0,
      trd_data(2, 35) => N0,
      trd_data(2, 34) => N0,
      trd_data(2, 33) => N0,
      trd_data(2, 32) => N0,
      trd_data(2, 31) => N0,
      trd_data(2, 30) => N0,
      trd_data(2, 29) => N0,
      trd_data(2, 28) => N0,
      trd_data(2, 27) => N0,
      trd_data(2, 26) => N0,
      trd_data(2, 25) => N0,
      trd_data(2, 24) => N0,
      trd_data(2, 23) => N0,
      trd_data(2, 22) => N0,
      trd_data(2, 21) => N0,
      trd_data(2, 20) => N0,
      trd_data(2, 19) => N0,
      trd_data(2, 18) => N0,
      trd_data(2, 17) => N0,
      trd_data(2, 16) => N0,
      trd_data(2, 15) => N0,
      trd_data(2, 14) => N0,
      trd_data(2, 13) => N0,
      trd_data(2, 12) => N0,
      trd_data(2, 11) => N0,
      trd_data(2, 10) => N0,
      trd_data(2, 9) => N0,
      trd_data(2, 8) => N0,
      trd_data(2, 7) => N0,
      trd_data(2, 6) => N0,
      trd_data(2, 5) => N0,
      trd_data(2, 4) => N0,
      trd_data(2, 3) => N0,
      trd_data(2, 2) => N0,
      trd_data(2, 1) => N0,
      trd_data(2, 0) => N0,
      trd_data(1, 63) => N0,
      trd_data(1, 62) => N0,
      trd_data(1, 61) => N0,
      trd_data(1, 60) => N0,
      trd_data(1, 59) => N0,
      trd_data(1, 58) => N0,
      trd_data(1, 57) => N0,
      trd_data(1, 56) => N0,
      trd_data(1, 55) => N0,
      trd_data(1, 54) => N0,
      trd_data(1, 53) => N0,
      trd_data(1, 52) => N0,
      trd_data(1, 51) => N0,
      trd_data(1, 50) => N0,
      trd_data(1, 49) => N0,
      trd_data(1, 48) => N0,
      trd_data(1, 47) => N0,
      trd_data(1, 46) => N0,
      trd_data(1, 45) => N0,
      trd_data(1, 44) => N0,
      trd_data(1, 43) => N0,
      trd_data(1, 42) => N0,
      trd_data(1, 41) => N0,
      trd_data(1, 40) => N0,
      trd_data(1, 39) => N0,
      trd_data(1, 38) => N0,
      trd_data(1, 37) => N0,
      trd_data(1, 36) => N0,
      trd_data(1, 35) => N0,
      trd_data(1, 34) => N0,
      trd_data(1, 33) => N0,
      trd_data(1, 32) => N0,
      trd_data(1, 31) => N0,
      trd_data(1, 30) => N0,
      trd_data(1, 29) => N0,
      trd_data(1, 28) => N0,
      trd_data(1, 27) => N0,
      trd_data(1, 26) => N0,
      trd_data(1, 25) => N0,
      trd_data(1, 24) => N0,
      trd_data(1, 23) => N0,
      trd_data(1, 22) => N0,
      trd_data(1, 21) => N0,
      trd_data(1, 20) => N0,
      trd_data(1, 19) => N0,
      trd_data(1, 18) => N0,
      trd_data(1, 17) => N0,
      trd_data(1, 16) => N0,
      trd_data(1, 15) => N0,
      trd_data(1, 14) => N0,
      trd_data(1, 13) => N0,
      trd_data(1, 12) => N0,
      trd_data(1, 11) => N0,
      trd_data(1, 10) => N0,
      trd_data(1, 9) => N0,
      trd_data(1, 8) => N0,
      trd_data(1, 7) => N0,
      trd_data(1, 6) => N0,
      trd_data(1, 5) => N0,
      trd_data(1, 4) => N0,
      trd_data(1, 3) => N0,
      trd_data(1, 2) => N0,
      trd_data(1, 1) => N0,
      trd_data(1, 0) => N0,
      trd_data(0, 63) => trd_data_0_63_Q,
      trd_data(0, 62) => trd_data_0_62_Q,
      trd_data(0, 61) => trd_data_0_61_Q,
      trd_data(0, 60) => trd_data_0_60_Q,
      trd_data(0, 59) => trd_data_0_59_Q,
      trd_data(0, 58) => trd_data_0_58_Q,
      trd_data(0, 57) => trd_data_0_57_Q,
      trd_data(0, 56) => trd_data_0_56_Q,
      trd_data(0, 55) => trd_data_0_55_Q,
      trd_data(0, 54) => trd_data_0_54_Q,
      trd_data(0, 53) => trd_data_0_53_Q,
      trd_data(0, 52) => trd_data_0_52_Q,
      trd_data(0, 51) => trd_data_0_51_Q,
      trd_data(0, 50) => trd_data_0_50_Q,
      trd_data(0, 49) => trd_data_0_49_Q,
      trd_data(0, 48) => trd_data_0_48_Q,
      trd_data(0, 47) => trd_data_0_47_Q,
      trd_data(0, 46) => trd_data_0_46_Q,
      trd_data(0, 45) => trd_data_0_45_Q,
      trd_data(0, 44) => trd_data_0_44_Q,
      trd_data(0, 43) => trd_data_0_43_Q,
      trd_data(0, 42) => trd_data_0_42_Q,
      trd_data(0, 41) => trd_data_0_41_Q,
      trd_data(0, 40) => trd_data_0_40_Q,
      trd_data(0, 39) => trd_data_0_39_Q,
      trd_data(0, 38) => trd_data_0_38_Q,
      trd_data(0, 37) => trd_data_0_37_Q,
      trd_data(0, 36) => trd_data_0_36_Q,
      trd_data(0, 35) => trd_data_0_35_Q,
      trd_data(0, 34) => trd_data_0_34_Q,
      trd_data(0, 33) => trd_data_0_33_Q,
      trd_data(0, 32) => trd_data_0_32_Q,
      trd_data(0, 31) => trd_data_0_31_Q,
      trd_data(0, 30) => trd_data_0_30_Q,
      trd_data(0, 29) => trd_data_0_29_Q,
      trd_data(0, 28) => trd_data_0_28_Q,
      trd_data(0, 27) => trd_data_0_27_Q,
      trd_data(0, 26) => trd_data_0_26_Q,
      trd_data(0, 25) => trd_data_0_25_Q,
      trd_data(0, 24) => trd_data_0_24_Q,
      trd_data(0, 23) => trd_data_0_23_Q,
      trd_data(0, 22) => trd_data_0_22_Q,
      trd_data(0, 21) => trd_data_0_21_Q,
      trd_data(0, 20) => trd_data_0_20_Q,
      trd_data(0, 19) => trd_data_0_19_Q,
      trd_data(0, 18) => trd_data_0_18_Q,
      trd_data(0, 17) => trd_data_0_17_Q,
      trd_data(0, 16) => trd_data_0_16_Q,
      trd_data(0, 15) => trd_data_0_15_Q,
      trd_data(0, 14) => trd_data_0_14_Q,
      trd_data(0, 13) => trd_data_0_13_Q,
      trd_data(0, 12) => trd_data_0_12_Q,
      trd_data(0, 11) => trd_data_0_11_Q,
      trd_data(0, 10) => trd_data_0_10_Q,
      trd_data(0, 9) => trd_data_0_9_Q,
      trd_data(0, 8) => trd_data_0_8_Q,
      trd_data(0, 7) => trd_data_0_7_Q,
      trd_data(0, 6) => trd_data_0_6_Q,
      trd_data(0, 5) => trd_data_0_5_Q,
      trd_data(0, 4) => trd_data_0_4_Q,
      trd_data(0, 3) => trd_data_0_3_Q,
      trd_data(0, 2) => trd_data_0_2_Q,
      trd_data(0, 1) => trd_data_0_1_Q,
      trd_data(0, 0) => trd_data_0_0_Q,
      trd_cmd_data(15, 15) => N1,
      trd_cmd_data(15, 14) => N1,
      trd_cmd_data(15, 13) => N1,
      trd_cmd_data(15, 12) => N1,
      trd_cmd_data(15, 11) => N1,
      trd_cmd_data(15, 10) => N1,
      trd_cmd_data(15, 9) => N1,
      trd_cmd_data(15, 8) => N1,
      trd_cmd_data(15, 7) => N1,
      trd_cmd_data(15, 6) => N1,
      trd_cmd_data(15, 5) => N1,
      trd_cmd_data(15, 4) => N1,
      trd_cmd_data(15, 3) => N1,
      trd_cmd_data(15, 2) => N1,
      trd_cmd_data(15, 1) => N1,
      trd_cmd_data(15, 0) => N1,
      trd_cmd_data(14, 15) => N1,
      trd_cmd_data(14, 14) => N1,
      trd_cmd_data(14, 13) => N1,
      trd_cmd_data(14, 12) => N1,
      trd_cmd_data(14, 11) => N1,
      trd_cmd_data(14, 10) => N1,
      trd_cmd_data(14, 9) => N1,
      trd_cmd_data(14, 8) => N1,
      trd_cmd_data(14, 7) => N1,
      trd_cmd_data(14, 6) => N1,
      trd_cmd_data(14, 5) => N1,
      trd_cmd_data(14, 4) => N1,
      trd_cmd_data(14, 3) => N1,
      trd_cmd_data(14, 2) => N1,
      trd_cmd_data(14, 1) => N1,
      trd_cmd_data(14, 0) => N1,
      trd_cmd_data(13, 15) => N1,
      trd_cmd_data(13, 14) => N1,
      trd_cmd_data(13, 13) => N1,
      trd_cmd_data(13, 12) => N1,
      trd_cmd_data(13, 11) => N1,
      trd_cmd_data(13, 10) => N1,
      trd_cmd_data(13, 9) => N1,
      trd_cmd_data(13, 8) => N1,
      trd_cmd_data(13, 7) => N1,
      trd_cmd_data(13, 6) => N1,
      trd_cmd_data(13, 5) => N1,
      trd_cmd_data(13, 4) => N1,
      trd_cmd_data(13, 3) => N1,
      trd_cmd_data(13, 2) => N1,
      trd_cmd_data(13, 1) => N1,
      trd_cmd_data(13, 0) => N1,
      trd_cmd_data(12, 15) => N1,
      trd_cmd_data(12, 14) => N1,
      trd_cmd_data(12, 13) => N1,
      trd_cmd_data(12, 12) => N1,
      trd_cmd_data(12, 11) => N1,
      trd_cmd_data(12, 10) => N1,
      trd_cmd_data(12, 9) => N1,
      trd_cmd_data(12, 8) => N1,
      trd_cmd_data(12, 7) => N1,
      trd_cmd_data(12, 6) => N1,
      trd_cmd_data(12, 5) => N1,
      trd_cmd_data(12, 4) => N1,
      trd_cmd_data(12, 3) => N1,
      trd_cmd_data(12, 2) => N1,
      trd_cmd_data(12, 1) => N1,
      trd_cmd_data(12, 0) => N1,
      trd_cmd_data(11, 15) => N1,
      trd_cmd_data(11, 14) => N1,
      trd_cmd_data(11, 13) => N1,
      trd_cmd_data(11, 12) => N1,
      trd_cmd_data(11, 11) => N1,
      trd_cmd_data(11, 10) => N1,
      trd_cmd_data(11, 9) => N1,
      trd_cmd_data(11, 8) => N1,
      trd_cmd_data(11, 7) => N1,
      trd_cmd_data(11, 6) => N1,
      trd_cmd_data(11, 5) => N1,
      trd_cmd_data(11, 4) => N1,
      trd_cmd_data(11, 3) => N1,
      trd_cmd_data(11, 2) => N1,
      trd_cmd_data(11, 1) => N1,
      trd_cmd_data(11, 0) => N1,
      trd_cmd_data(10, 15) => N1,
      trd_cmd_data(10, 14) => N1,
      trd_cmd_data(10, 13) => N1,
      trd_cmd_data(10, 12) => N1,
      trd_cmd_data(10, 11) => N1,
      trd_cmd_data(10, 10) => N1,
      trd_cmd_data(10, 9) => N1,
      trd_cmd_data(10, 8) => N1,
      trd_cmd_data(10, 7) => N1,
      trd_cmd_data(10, 6) => N1,
      trd_cmd_data(10, 5) => N1,
      trd_cmd_data(10, 4) => N1,
      trd_cmd_data(10, 3) => N1,
      trd_cmd_data(10, 2) => N1,
      trd_cmd_data(10, 1) => N1,
      trd_cmd_data(10, 0) => N1,
      trd_cmd_data(9, 15) => N1,
      trd_cmd_data(9, 14) => N1,
      trd_cmd_data(9, 13) => N1,
      trd_cmd_data(9, 12) => N1,
      trd_cmd_data(9, 11) => N1,
      trd_cmd_data(9, 10) => N1,
      trd_cmd_data(9, 9) => N1,
      trd_cmd_data(9, 8) => N1,
      trd_cmd_data(9, 7) => N1,
      trd_cmd_data(9, 6) => N1,
      trd_cmd_data(9, 5) => N1,
      trd_cmd_data(9, 4) => N1,
      trd_cmd_data(9, 3) => N1,
      trd_cmd_data(9, 2) => N1,
      trd_cmd_data(9, 1) => N1,
      trd_cmd_data(9, 0) => N1,
      trd_cmd_data(8, 15) => N1,
      trd_cmd_data(8, 14) => N1,
      trd_cmd_data(8, 13) => N1,
      trd_cmd_data(8, 12) => N1,
      trd_cmd_data(8, 11) => N1,
      trd_cmd_data(8, 10) => N1,
      trd_cmd_data(8, 9) => N1,
      trd_cmd_data(8, 8) => N1,
      trd_cmd_data(8, 7) => N1,
      trd_cmd_data(8, 6) => N1,
      trd_cmd_data(8, 5) => N1,
      trd_cmd_data(8, 4) => N1,
      trd_cmd_data(8, 3) => N1,
      trd_cmd_data(8, 2) => N1,
      trd_cmd_data(8, 1) => N1,
      trd_cmd_data(8, 0) => N1,
      trd_cmd_data(7, 15) => trd_cmd_data_7_15_Q,
      trd_cmd_data(7, 14) => trd_cmd_data_7_14_Q,
      trd_cmd_data(7, 13) => trd_cmd_data_7_13_Q,
      trd_cmd_data(7, 12) => trd_cmd_data_7_12_Q,
      trd_cmd_data(7, 11) => trd_cmd_data_7_11_Q,
      trd_cmd_data(7, 10) => trd_cmd_data_7_10_Q,
      trd_cmd_data(7, 9) => trd_cmd_data_7_9_Q,
      trd_cmd_data(7, 8) => trd_cmd_data_7_8_Q,
      trd_cmd_data(7, 7) => trd_cmd_data_7_7_Q,
      trd_cmd_data(7, 6) => trd_cmd_data_7_6_Q,
      trd_cmd_data(7, 5) => trd_cmd_data_7_5_Q,
      trd_cmd_data(7, 4) => trd_cmd_data_7_4_Q,
      trd_cmd_data(7, 3) => trd_cmd_data_7_3_Q,
      trd_cmd_data(7, 2) => trd_cmd_data_7_2_Q,
      trd_cmd_data(7, 1) => trd_cmd_data_7_1_Q,
      trd_cmd_data(7, 0) => trd_cmd_data_7_0_Q,
      trd_cmd_data(6, 15) => trd_cmd_data_6_15_Q,
      trd_cmd_data(6, 14) => trd_cmd_data_6_14_Q,
      trd_cmd_data(6, 13) => trd_cmd_data_6_13_Q,
      trd_cmd_data(6, 12) => trd_cmd_data_6_12_Q,
      trd_cmd_data(6, 11) => trd_cmd_data_6_11_Q,
      trd_cmd_data(6, 10) => trd_cmd_data_6_10_Q,
      trd_cmd_data(6, 9) => trd_cmd_data_6_9_Q,
      trd_cmd_data(6, 8) => trd_cmd_data_6_8_Q,
      trd_cmd_data(6, 7) => trd_cmd_data_6_7_Q,
      trd_cmd_data(6, 6) => trd_cmd_data_6_6_Q,
      trd_cmd_data(6, 5) => trd_cmd_data_6_5_Q,
      trd_cmd_data(6, 4) => trd_cmd_data_6_4_Q,
      trd_cmd_data(6, 3) => trd_cmd_data_6_3_Q,
      trd_cmd_data(6, 2) => trd_cmd_data_6_2_Q,
      trd_cmd_data(6, 1) => trd_cmd_data_6_1_Q,
      trd_cmd_data(6, 0) => trd_cmd_data_6_0_Q,
      trd_cmd_data(5, 15) => N1,
      trd_cmd_data(5, 14) => N1,
      trd_cmd_data(5, 13) => N1,
      trd_cmd_data(5, 12) => N1,
      trd_cmd_data(5, 11) => N1,
      trd_cmd_data(5, 10) => N1,
      trd_cmd_data(5, 9) => N1,
      trd_cmd_data(5, 8) => N1,
      trd_cmd_data(5, 7) => N1,
      trd_cmd_data(5, 6) => N1,
      trd_cmd_data(5, 5) => N1,
      trd_cmd_data(5, 4) => N1,
      trd_cmd_data(5, 3) => N1,
      trd_cmd_data(5, 2) => N1,
      trd_cmd_data(5, 1) => N1,
      trd_cmd_data(5, 0) => N1,
      trd_cmd_data(4, 15) => N1,
      trd_cmd_data(4, 14) => N1,
      trd_cmd_data(4, 13) => N1,
      trd_cmd_data(4, 12) => N1,
      trd_cmd_data(4, 11) => N1,
      trd_cmd_data(4, 10) => N1,
      trd_cmd_data(4, 9) => N1,
      trd_cmd_data(4, 8) => N1,
      trd_cmd_data(4, 7) => N1,
      trd_cmd_data(4, 6) => N1,
      trd_cmd_data(4, 5) => N1,
      trd_cmd_data(4, 4) => N1,
      trd_cmd_data(4, 3) => N1,
      trd_cmd_data(4, 2) => N1,
      trd_cmd_data(4, 1) => N1,
      trd_cmd_data(4, 0) => N1,
      trd_cmd_data(3, 15) => N1,
      trd_cmd_data(3, 14) => N1,
      trd_cmd_data(3, 13) => N1,
      trd_cmd_data(3, 12) => N1,
      trd_cmd_data(3, 11) => N1,
      trd_cmd_data(3, 10) => N1,
      trd_cmd_data(3, 9) => N1,
      trd_cmd_data(3, 8) => N1,
      trd_cmd_data(3, 7) => N1,
      trd_cmd_data(3, 6) => N1,
      trd_cmd_data(3, 5) => N1,
      trd_cmd_data(3, 4) => N1,
      trd_cmd_data(3, 3) => N1,
      trd_cmd_data(3, 2) => N1,
      trd_cmd_data(3, 1) => N1,
      trd_cmd_data(3, 0) => N1,
      trd_cmd_data(2, 15) => N1,
      trd_cmd_data(2, 14) => N1,
      trd_cmd_data(2, 13) => N1,
      trd_cmd_data(2, 12) => N1,
      trd_cmd_data(2, 11) => N1,
      trd_cmd_data(2, 10) => N1,
      trd_cmd_data(2, 9) => N1,
      trd_cmd_data(2, 8) => N1,
      trd_cmd_data(2, 7) => N1,
      trd_cmd_data(2, 6) => N1,
      trd_cmd_data(2, 5) => N1,
      trd_cmd_data(2, 4) => N1,
      trd_cmd_data(2, 3) => N1,
      trd_cmd_data(2, 2) => N1,
      trd_cmd_data(2, 1) => N1,
      trd_cmd_data(2, 0) => N1,
      trd_cmd_data(1, 15) => trd_cmd_data_1_15_Q,
      trd_cmd_data(1, 14) => trd_cmd_data_1_14_Q,
      trd_cmd_data(1, 13) => trd_cmd_data_1_13_Q,
      trd_cmd_data(1, 12) => trd_cmd_data_1_12_Q,
      trd_cmd_data(1, 11) => trd_cmd_data_1_11_Q,
      trd_cmd_data(1, 10) => trd_cmd_data_1_10_Q,
      trd_cmd_data(1, 9) => trd_cmd_data_1_9_Q,
      trd_cmd_data(1, 8) => trd_cmd_data_1_8_Q,
      trd_cmd_data(1, 7) => trd_cmd_data_1_7_Q,
      trd_cmd_data(1, 6) => trd_cmd_data_1_6_Q,
      trd_cmd_data(1, 5) => trd_cmd_data_1_5_Q,
      trd_cmd_data(1, 4) => trd_cmd_data_1_4_Q,
      trd_cmd_data(1, 3) => trd_cmd_data_1_3_Q,
      trd_cmd_data(1, 2) => trd_cmd_data_1_2_Q,
      trd_cmd_data(1, 1) => trd_cmd_data_1_1_Q,
      trd_cmd_data(1, 0) => trd_cmd_data_1_0_Q,
      trd_cmd_data(0, 15) => trd_cmd_data_0_15_Q,
      trd_cmd_data(0, 14) => trd_cmd_data_0_14_Q,
      trd_cmd_data(0, 13) => trd_cmd_data_0_13_Q,
      trd_cmd_data(0, 12) => trd_cmd_data_0_12_Q,
      trd_cmd_data(0, 11) => trd_cmd_data_0_11_Q,
      trd_cmd_data(0, 10) => trd_cmd_data_0_10_Q,
      trd_cmd_data(0, 9) => trd_cmd_data_0_9_Q,
      trd_cmd_data(0, 8) => trd_cmd_data_0_8_Q,
      trd_cmd_data(0, 7) => trd_cmd_data_0_7_Q,
      trd_cmd_data(0, 6) => trd_cmd_data_0_6_Q,
      trd_cmd_data(0, 5) => trd_cmd_data_0_5_Q,
      trd_cmd_data(0, 4) => trd_cmd_data_0_4_Q,
      trd_cmd_data(0, 3) => trd_cmd_data_0_3_Q,
      trd_cmd_data(0, 2) => trd_cmd_data_0_2_Q,
      trd_cmd_data(0, 1) => trd_cmd_data_0_1_Q,
      trd_cmd_data(0, 0) => trd_cmd_data_0_0_Q,
      rxn(7) => rxn_7_IBUF_36504,
      rxn(6) => rxn_6_IBUF_36503,
      rxn(5) => rxn_5_IBUF_36502,
      rxn(4) => rxn_4_IBUF_36501,
      rxn(3) => rxn_3_IBUF_36500,
      rxn(2) => rxn_2_IBUF_36499,
      rxn(1) => rxn_1_IBUF_36498,
      rxn(0) => rxn_0_IBUF_36497,
      rxp(7) => rxp_7_IBUF_36520,
      rxp(6) => rxp_6_IBUF_36519,
      rxp(5) => rxp_5_IBUF_36518,
      rxp(4) => rxp_4_IBUF_36517,
      rxp(3) => rxp_3_IBUF_36516,
      rxp(2) => rxp_2_IBUF_36515,
      rxp(1) => rxp_1_IBUF_36514,
      rxp(0) => rxp_0_IBUF_36513,
      trd_main_sel_drq(15, 6) => N0,
      trd_main_sel_drq(15, 5) => N0,
      trd_main_sel_drq(15, 4) => N0,
      trd_main_sel_drq(15, 3) => N0,
      trd_main_sel_drq(15, 2) => N0,
      trd_main_sel_drq(15, 1) => N0,
      trd_main_sel_drq(15, 0) => N0,
      trd_main_sel_drq(14, 6) => N0,
      trd_main_sel_drq(14, 5) => N0,
      trd_main_sel_drq(14, 4) => N0,
      trd_main_sel_drq(14, 3) => N0,
      trd_main_sel_drq(14, 2) => N0,
      trd_main_sel_drq(14, 1) => N0,
      trd_main_sel_drq(14, 0) => N0,
      trd_main_sel_drq(13, 6) => N0,
      trd_main_sel_drq(13, 5) => N0,
      trd_main_sel_drq(13, 4) => N0,
      trd_main_sel_drq(13, 3) => N0,
      trd_main_sel_drq(13, 2) => N0,
      trd_main_sel_drq(13, 1) => N0,
      trd_main_sel_drq(13, 0) => N0,
      trd_main_sel_drq(12, 6) => N0,
      trd_main_sel_drq(12, 5) => N0,
      trd_main_sel_drq(12, 4) => N0,
      trd_main_sel_drq(12, 3) => N0,
      trd_main_sel_drq(12, 2) => N0,
      trd_main_sel_drq(12, 1) => N0,
      trd_main_sel_drq(12, 0) => N0,
      trd_main_sel_drq(11, 6) => N0,
      trd_main_sel_drq(11, 5) => N0,
      trd_main_sel_drq(11, 4) => N0,
      trd_main_sel_drq(11, 3) => N0,
      trd_main_sel_drq(11, 2) => N0,
      trd_main_sel_drq(11, 1) => N0,
      trd_main_sel_drq(11, 0) => N0,
      trd_main_sel_drq(10, 6) => N0,
      trd_main_sel_drq(10, 5) => N0,
      trd_main_sel_drq(10, 4) => N0,
      trd_main_sel_drq(10, 3) => N0,
      trd_main_sel_drq(10, 2) => N0,
      trd_main_sel_drq(10, 1) => N0,
      trd_main_sel_drq(10, 0) => N0,
      trd_main_sel_drq(9, 6) => N0,
      trd_main_sel_drq(9, 5) => N0,
      trd_main_sel_drq(9, 4) => N0,
      trd_main_sel_drq(9, 3) => N0,
      trd_main_sel_drq(9, 2) => N0,
      trd_main_sel_drq(9, 1) => N0,
      trd_main_sel_drq(9, 0) => N0,
      trd_main_sel_drq(8, 6) => N0,
      trd_main_sel_drq(8, 5) => N0,
      trd_main_sel_drq(8, 4) => N0,
      trd_main_sel_drq(8, 3) => N0,
      trd_main_sel_drq(8, 2) => N0,
      trd_main_sel_drq(8, 1) => N0,
      trd_main_sel_drq(8, 0) => N0,
      trd_main_sel_drq(7, 6) => N0,
      trd_main_sel_drq(7, 5) => N0,
      trd_main_sel_drq(7, 4) => N0,
      trd_main_sel_drq(7, 3) => N0,
      trd_main_sel_drq(7, 2) => N0,
      trd_main_sel_drq(7, 1) => N0,
      trd_main_sel_drq(7, 0) => N0,
      trd_main_sel_drq(6, 6) => N0,
      trd_main_sel_drq(6, 5) => N0,
      trd_main_sel_drq(6, 4) => N0,
      trd_main_sel_drq(6, 3) => N0,
      trd_main_sel_drq(6, 2) => N0,
      trd_main_sel_drq(6, 1) => N0,
      trd_main_sel_drq(6, 0) => N0,
      trd_main_sel_drq(5, 6) => N0,
      trd_main_sel_drq(5, 5) => N0,
      trd_main_sel_drq(5, 4) => N0,
      trd_main_sel_drq(5, 3) => N0,
      trd_main_sel_drq(5, 2) => N0,
      trd_main_sel_drq(5, 1) => N0,
      trd_main_sel_drq(5, 0) => N0,
      trd_main_sel_drq(4, 6) => N0,
      trd_main_sel_drq(4, 5) => N0,
      trd_main_sel_drq(4, 4) => N0,
      trd_main_sel_drq(4, 3) => N0,
      trd_main_sel_drq(4, 2) => N0,
      trd_main_sel_drq(4, 1) => N0,
      trd_main_sel_drq(4, 0) => N0,
      trd_main_sel_drq(3, 6) => N0,
      trd_main_sel_drq(3, 5) => N0,
      trd_main_sel_drq(3, 4) => N0,
      trd_main_sel_drq(3, 3) => N0,
      trd_main_sel_drq(3, 2) => N0,
      trd_main_sel_drq(3, 1) => N0,
      trd_main_sel_drq(3, 0) => N0,
      trd_main_sel_drq(2, 6) => N0,
      trd_main_sel_drq(2, 5) => N0,
      trd_main_sel_drq(2, 4) => N0,
      trd_main_sel_drq(2, 3) => N0,
      trd_main_sel_drq(2, 2) => N0,
      trd_main_sel_drq(2, 1) => N0,
      trd_main_sel_drq(2, 0) => N0,
      trd_main_sel_drq(1, 6) => N0,
      trd_main_sel_drq(1, 5) => N0,
      trd_main_sel_drq(1, 4) => N0,
      trd_main_sel_drq(1, 3) => N0,
      trd_main_sel_drq(1, 2) => N0,
      trd_main_sel_drq(1, 1) => N0,
      trd_main_sel_drq(1, 0) => N0,
      trd_main_sel_drq(0, 6) => N0,
      trd_main_sel_drq(0, 5) => N0,
      trd_main_sel_drq(0, 4) => N0,
      trd_main_sel_drq(0, 3) => N0,
      trd_main_sel_drq(0, 2) => N0,
      trd_main_sel_drq(0, 1) => N0,
      trd_main_sel_drq(0, 0) => N0,
      trd_main_irq(15) => N0,
      trd_main_irq(14) => N0,
      trd_main_irq(13) => N0,
      trd_main_irq(12) => N0,
      trd_main_irq(11) => N0,
      trd_main_irq(10) => N0,
      trd_main_irq(9) => N0,
      trd_main_irq(8) => N0,
      trd_main_irq(7) => N0,
      trd_main_irq(6) => N0,
      trd_main_irq(5) => N0,
      trd_main_irq(4) => N0,
      trd_main_irq(3) => N0,
      trd_main_irq(2) => N0,
      trd_main_irq(1) => trd_main_irq(1),
      trd_main_irq(0) => N0,
      trd_reset_fifo(15) => N0,
      trd_reset_fifo(14) => N0,
      trd_reset_fifo(13) => N0,
      trd_reset_fifo(12) => N0,
      trd_reset_fifo(11) => N0,
      trd_reset_fifo(10) => N0,
      trd_reset_fifo(9) => N0,
      trd_reset_fifo(8) => N0,
      trd_reset_fifo(7) => do_fifo_rst,
      trd_reset_fifo(6) => di_fifo_rst,
      trd_reset_fifo(5) => N0,
      trd_reset_fifo(4) => N0,
      trd_reset_fifo(3) => N0,
      trd_reset_fifo(2) => N0,
      trd_reset_fifo(1) => N0,
      trd_reset_fifo(0) => trd_reset_fifo(0)
    );
  rxn_7_IBUF : IBUF
    port map (
      I => rxn(7),
      O => rxn_7_IBUF_36504
    );
  rxn_6_IBUF : IBUF
    port map (
      I => rxn(6),
      O => rxn_6_IBUF_36503
    );
  rxn_5_IBUF : IBUF
    port map (
      I => rxn(5),
      O => rxn_5_IBUF_36502
    );
  rxn_4_IBUF : IBUF
    port map (
      I => rxn(4),
      O => rxn_4_IBUF_36501
    );
  rxn_3_IBUF : IBUF
    port map (
      I => rxn(3),
      O => rxn_3_IBUF_36500
    );
  rxn_2_IBUF : IBUF
    port map (
      I => rxn(2),
      O => rxn_2_IBUF_36499
    );
  rxn_1_IBUF : IBUF
    port map (
      I => rxn(1),
      O => rxn_1_IBUF_36498
    );
  rxn_0_IBUF : IBUF
    port map (
      I => rxn(0),
      O => rxn_0_IBUF_36497
    );
  rxp_7_IBUF : IBUF
    port map (
      I => rxp(7),
      O => rxp_7_IBUF_36520
    );
  rxp_6_IBUF : IBUF
    port map (
      I => rxp(6),
      O => rxp_6_IBUF_36519
    );
  rxp_5_IBUF : IBUF
    port map (
      I => rxp(5),
      O => rxp_5_IBUF_36518
    );
  rxp_4_IBUF : IBUF
    port map (
      I => rxp(4),
      O => rxp_4_IBUF_36517
    );
  rxp_3_IBUF : IBUF
    port map (
      I => rxp(3),
      O => rxp_3_IBUF_36516
    );
  rxp_2_IBUF : IBUF
    port map (
      I => rxp(2),
      O => rxp_2_IBUF_36515
    );
  rxp_1_IBUF : IBUF
    port map (
      I => rxp(1),
      O => rxp_1_IBUF_36514
    );
  rxp_0_IBUF : IBUF
    port map (
      I => rxp(0),
      O => rxp_0_IBUF_36513
    );
  txn_7_OBUF : OBUF
    port map (
      I => txn_7_OBUF_37026,
      O => txn(7)
    );
  txn_6_OBUF : OBUF
    port map (
      I => txn_6_OBUF_37025,
      O => txn(6)
    );
  txn_5_OBUF : OBUF
    port map (
      I => txn_5_OBUF_37024,
      O => txn(5)
    );
  txn_4_OBUF : OBUF
    port map (
      I => txn_4_OBUF_37023,
      O => txn(4)
    );
  txn_3_OBUF : OBUF
    port map (
      I => txn_3_OBUF_37022,
      O => txn(3)
    );
  txn_2_OBUF : OBUF
    port map (
      I => txn_2_OBUF_37021,
      O => txn(2)
    );
  txn_1_OBUF : OBUF
    port map (
      I => txn_1_OBUF_37020,
      O => txn(1)
    );
  txn_0_OBUF : OBUF
    port map (
      I => txn_0_OBUF_37019,
      O => txn(0)
    );
  txp_7_OBUF : OBUF
    port map (
      I => txp_7_OBUF_37042,
      O => txp(7)
    );
  txp_6_OBUF : OBUF
    port map (
      I => txp_6_OBUF_37041,
      O => txp(6)
    );
  txp_5_OBUF : OBUF
    port map (
      I => txp_5_OBUF_37040,
      O => txp(5)
    );
  txp_4_OBUF : OBUF
    port map (
      I => txp_4_OBUF_37039,
      O => txp(4)
    );
  txp_3_OBUF : OBUF
    port map (
      I => txp_3_OBUF_37038,
      O => txp(3)
    );
  txp_2_OBUF : OBUF
    port map (
      I => txp_2_OBUF_37037,
      O => txp(2)
    );
  txp_1_OBUF : OBUF
    port map (
      I => txp_1_OBUF_37036,
      O => txp(1)
    );
  txp_0_OBUF : OBUF
    port map (
      I => txp_0_OBUF_37035,
      O => txp(0)
    );

end STRUCTURE;

