## Implement Log

Created on 8:30:34 22.09.2011

InputFile = e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/implement/xie10.ini
Release 13.1 ChipScope Core Inserter 13100.11.34.704
Copyright (c) 1999-2011 Xilinx, Inc. All Rights Reserved.
Command Line: inserter -intstyle silent -mode setup -ise_project_dir e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis -proj e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/synthesis/ambpex5_v20_sx50t_core.cdc -p XC5VSX50TFF1136-1 -quiet e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_merge.ngc e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_merge_chipscope.ngc
ngcbuild.exe -p XC5VSX50TFF1136-1 -i e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_merge.ngc e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_merge_chipscope.ngc
Release 13.1 - ngcbuild O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: ngcbuild.exe -p XC5VSX50TFF1136-1 -i
e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_m
erge.ngc
e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core_m
erge_chipscope.ngc
Reading NGO file
"e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/synthesis/ambpex5_v20_sx50t_core_
merge.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file
"e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/synthesis/ambpex5_v20_sx50t_core_
merge_chipscope.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file
"e:/prog/ds_dma_project/ambpex5_v20_sx50t_core/synthesis/ambpex5_v20_sx50t_core_
merge_chipscope.blc"...
NGCBUILD done.
Loading CDC project e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core.cdc
Successfully read project e:\prog\ds_dma_project\ambpex5_v20_sx50t_core\synthesis\ambpex5_v20_sx50t_core.cdc
Executing "C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\par.exe" -w -ol high -p -mt off map.ncd "ambpex5_v20_sx50t_core_merge_chipscope.ncd" "ambpex5_v20_sx50t_core_merge_chipscope.pcf"
Release 13.1 - par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Constraints file: ambpex5_v20_sx50t_core_merge_chipscope.pcf.
Loading device for application Rf_Device from file '5vsx50t.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
"ambpex5_v20_sx50t_core" is an NCD, version 3.2, device xc5vsx50t, package ff1136, speed -1
Par:381 - One or more of the following switches -p and -r is not supported for this architecture. PAR will
ignore the switch and processing will continue
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.72 2011-02-03".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFDSs 1 out of 6 16%
Number of BUFGs 4 out of 32 12%
Number of DSP48Es 4 out of 288 1%
Number of GTP_DUALs 4 out of 6 66%
Number of External IOBs 8 out of 480 1%
Number of LOCed IOBs 8 out of 8 100%
Number of External IPADs 18 out of 518 3%
Number of LOCed IPADs 18 out of 18 100%
Number of External OPADs 16 out of 24 66%
Number of LOCed OPADs 16 out of 16 100%
Number of PCIEs 1 out of 1 100%
Number of PLL_ADVs 1 out of 6 16%
Number of RAMB18X2s 10 out of 132 7%
Number of RAMB36SDP_EXPs 2 out of 132 1%
Number of RAMB36_EXPs 8 out of 132 6%
Number of Slices 3014 out of 8160 36%
Number of Slice Registers 7809 out of 32640 23%
Number used as Flip Flops 7799
Number used as Latches 9
Number used as LatchThrus 1
Number of Slice LUTS 6481 out of 32640 19%
Number of Slice LUT-Flip Flop pairs 9963 out of 32640 30%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 16 secs
Finished initial Timing Analysis. REAL time: 16 secs
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/trn_rerrfwd_n has no load. PAR will not attempt to route
this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/trn_rrem_n<0> has no load. PAR will not attempt to route
this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<336> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<335> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<334> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<259> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<258> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<257> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<183> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<182> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<181> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<104> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<103> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<102> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<91> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<90> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<89> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<12> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<11> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/DEBUG<10> has no load. PAR will not attempt to
route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/l0_mac_negotiated_link_width<2> has no load.
PAR will not attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/l0_mac_negotiated_link_width<1> has no load.
PAR will not attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/l0_mac_negotiated_link_width<0> has no load.
PAR will not attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l7 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l6 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l5 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l4 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l3 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l2 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l1 has no load. PAR will not
attempt to route this signal.
Par:288 - The signal amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l0 has no load. PAR will not
attempt to route this signal.
Starting Router
Phase 1 : 45292 unrouted; REAL time: 18 secs
Phase 2 : 37339 unrouted; REAL time: 21 secs
Phase 3 : 9318 unrouted; REAL time: 57 secs
Phase 4 : 9321 unrouted; (Setup:1105304, Hold:110526, Component Switching Limit:0) REAL time: 1 mins 5 secs
Updating file: ambpex5_v20_sx50t_core_merge_chipscope.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:1174366, Hold:104829, Component Switching Limit:0) REAL time: 1 mins 21 secs
Phase 6 : 0 unrouted; (Setup:1173685, Hold:104829, Component Switching Limit:0) REAL time: 1 mins 26 secs
Updating file: ambpex5_v20_sx50t_core_merge_chipscope.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:1173685, Hold:104829, Component Switching Limit:0) REAL time: 1 mins 48 secs
Phase 8 : 0 unrouted; (Setup:1156055, Hold:104829, Component Switching Limit:0) REAL time: 1 mins 56 secs
Phase 9 : 0 unrouted; (Setup:1156055, Hold:0, Component Switching Limit:0) REAL time: 1 mins 57 secs
Phase 10 : 0 unrouted; (Setup:1044412, Hold:0, Component Switching Limit:0) REAL time: 1 mins 59 secs
Total REAL time to Router completion: 1 mins 59 secs
Total CPU time to Router completion: 2 mins 5 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGCTRL_X0Y0| No | 2801 | 0.464 | 1.982 |
+---------------------+--------------+------+------+------------+-------------+
| clk200 |BUFGCTRL_X0Y30| No | 49 | 0.095 | 1.764 |
+---------------------+--------------+------+------+------------+-------------+
| icon_control0<0> | BUFGCTRL_X0Y1| No | 73 | 0.221 | 1.982 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
| lk/REFCLKOUT_bufg |BUFGCTRL_X0Y31| No | 6 | 0.005 | 1.709 |
+---------------------+--------------+------+------+------------+-------------+
| clk30k | Local| | 3 | 0.000 | 0.471 |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/U0/iUPDAT | | | | | |
| E_OUT | Local| | 1 | 0.000 | 1.251 |
+---------------------+--------------+------+------+------------+-------------+
| icon_control0<13> | Local| | 5 | 0.000 | 1.120 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<0> | Local| | 2 | 0.000 | 0.465 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<12> | Local| | 3 | 0.000 | 0.604 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<9> | Local| | 2 | 0.000 | 0.456 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<10> | Local| | 2 | 0.000 | 0.458 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<11> | Local| | 2 | 0.000 | 0.463 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<1> | Local| | 2 | 0.000 | 0.489 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<2> | Local| | 2 | 0.000 | 0.634 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<3> | Local| | 2 | 0.000 | 0.638 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<4> | Local| | 2 | 0.000 | 0.475 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<5> | Local| | 2 | 0.000 | 0.512 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<6> | Local| | 2 | 0.000 | 0.457 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<7> | Local| | 2 | 0.000 | 0.452 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.blink/cn | | | | | |
| t30k<8> | Local| | 2 | 0.000 | 0.465 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1901_13526 | Local| | 2 | 0.000 | 1.557 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1905_13528 | Local| | 2 | 0.000 | 2.041 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1897_13524 | Local| | 2 | 0.000 | 1.642 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1893_13522 | Local| | 2 | 0.000 | 1.496 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1889_13520 | Local| | 2 | 0.000 | 1.200 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1885_13518 | Local| | 2 | 0.000 | 1.085 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1881_13516 | Local| | 2 | 0.000 | 0.632 |
+---------------------+--------------+------+------+------------+-------------+
|amb/gen_syn.pcie/cor | | | | | |
|e/ep/pcie_ep0/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/lut1877_13514 | Local| | 2 | 0.000 | 0.513 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 1044412 (Setup: 1044412, Hold: 0, Component Switching Limit: 0)
Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 250 M | SETUP | -1.445ns| 5.445ns| 2405| 1044412
Hz HIGH 50% | HOLD | 0.163ns| | 0| 0
| MINPERIOD | 0.000ns| 4.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 14.127ns| 0.873ns| 0| 0
TO TIMEGRP "U_CLK" 15 ns | HOLD | 0.550ns| | 0| 0
----------------------------------------------------------------------------------------------------------
1 constraint not met.
Generating Pad Report.
All signals are completely routed.
Par:283 - There are 31 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 5 secs
Total CPU time to PAR completion: 2 mins 10 secs
Peak Memory Usage: 462 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 2405 errors found.
Number of error messages: 0
Number of warning messages: 35
Number of info messages: 0
Writing design to file ambpex5_v20_sx50t_core_merge_chipscope.ncd
PAR done!
Executing "C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\trce.exe" -e 32 -s 1 -n 3 -fastpaths "ambpex5_v20_sx50t_core_merge_chipscope.ncd" "ambpex5_v20_sx50t_core_merge_chipscope.pcf" -o "ambpex5_v20_sx50t_core_merge_chipscope_postpar.twr"
Release 13.1 - Trace (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '5vsx50t.nph' in environment
C:\Xilinx\13.1\ISE_DS\ISE\.
"ambpex5_v20_sx50t_core" is an NCD, version 3.2, device xc5vsx50t, package
ff1136, speed -1
--------------------------------------------------------------------------------
Release 13.1 Trace (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -e 32 -s 1 -n 3 -fastpaths
ambpex5_v20_sx50t_core_merge_chipscope.ncd
ambpex5_v20_sx50t_core_merge_chipscope.pcf -o
ambpex5_v20_sx50t_core_merge_chipscope_postpar.twr
Design file: ambpex5_v20_sx50t_core_merge_chipscope.ncd
Physical constraint file: ambpex5_v20_sx50t_core_merge_chipscope.pcf
Device,speed: xc5vsx50t,-1 (PRODUCTION 1.72 2011-02-03, STEPPING
level 0)
Report level: error report, limited to 32 items per constraint
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
50 Ohm transmission line loading model. For the details of this model, and
for more information on accounting for different loading conditions, please
see the device datasheet.
Timing summary:
---------------
Timing errors: 2405 Score: 1044412 (Setup/Max: 1044412, Hold: 0)
Constraints cover 157714 paths, 0 nets, and 36166 connections
Design statistics:
Minimum period: 5.445ns (Maximum frequency: 183.655MHz)
Maximum path delay from/to any node: 0.873ns
Analysis completed Thu Sep 22 08:29:29 2011
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 2
Total time: 19 secs
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most
commonly, bitgen has determined and will use a specific value instead of the
generic command-line value of "Auto". Alternately, this message appears if
the same option is specified multiple times on the command-line. In this
case, the option listed last will be used.
PhysDesignRules:1841 - One or more GTPs are being used in this design.
Evaluate the SelectIO-To-GTP Crosstalk section of the Virtex-5 RocketIO GTP
Transceiver User Guide to ensure that the design SelectIO usage meets the
guidelines to minimize the impact on GTP performance.
PhysDesignRules:372 - Gated clock. Clock net clk30k is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1901_135
26 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1905_135
28 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1897_135
24 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1893_135
22 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1889_135
20 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1885_135
18 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1881_135
16 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:372 - Gated clock. Clock net
amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/lut1877_135
14 is sourced by a combinatorial pin. This is not good design practice. Use
the CE pin to control the loading of data into the flip-flop.
PhysDesignRules:367 - The signal <amb/trd_cmd_data<0><5>> is incomplete.
The signal does not drive any load pins in the design.
INFO:PhysDesignRules:1505 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/ram_data/cmd/gen_dsp48.dsp>:<DSP48E_DSP48E>
. When the DSP48E AREG attribute is set to 1 the CEA1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1509 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/ram_data/cmd/gen_dsp48.dsp>:<DSP48E_DSP48E>
. When the DSP48E BREG attribute is set to 1 the CEB1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1511 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/ram_data/cmd/gen_dsp48.dsp>:<DSP48E_DSP48E>
. When the DSP48E USE_MULT attribute is set to NONE the CEM input pin should
be tied GND to save power.
INFO:PhysDesignRules:1505 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/cmd/dma_adr/gen_dsp48.dsp0>:<DSP48E_DSP48E>
. When the DSP48E AREG attribute is set to 1 the CEA1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1509 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/cmd/dma_adr/gen_dsp48.dsp0>:<DSP48E_DSP48E>
. When the DSP48E BREG attribute is set to 1 the CEB1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1505 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/cmd/dma_adr/gen_dsp48.dsp1>:<DSP48E_DSP48E>
. When the DSP48E AREG attribute is set to 1 the CEA1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1509 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/cmd/dma_adr/gen_dsp48.dsp1>:<DSP48E_DSP48E>
. When the DSP48E BREG attribute is set to 1 the CEB1 input pin should be
tied GND to save power.
INFO:PhysDesignRules:1505 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/dsc/gen_dsp48.dsp>:<DSP48E_DSP48E>. When
the DSP48E AREG attribute is set to 1 the CEA1 input pin should be tied GND
to save power.
INFO:PhysDesignRules:1509 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/dsc/gen_dsp48.dsp>:<DSP48E_DSP48E>. When
the DSP48E BREG attribute is set to 1 the CEB1 input pin should be tied GND
to save power.
INFO:PhysDesignRules:1515 - Issue with pin connections and/or configuration on
block:<amb/gen_syn.pcie/core/fifo/dsc/gen_dsp48.dsp>:<DSP48E_DSP48E>. To
save power with this DSP48E OPMODE input pin programming the USE_MODE
attribute should be set to NONE.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l7> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l6> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l5> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l4> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l3> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l2> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l1> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/pipe_deskew_lanes_l0> is
incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk/use_reset_logic.reset_i/USERCLK>
is incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/GLOBAL_LOG
IC0> is incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk_if/cf_bridge/cfg_arb/cfg_rd_hdr<2
0>> is incomplete. The signal does not drive any load pins in the design.
PhysDesignRules:367 - The signal
<amb/gen_syn.pcie/core/ep/pcie_ep0/pcie_blk_if/cf_bridge/cfg_arb/cfg_rd_hdr<0
>> is incomplete. The signal does not drive any load pins in the design.
E:\prog\ds_dma_project\ambpex5_v20_sx50t_core\implement\ver1\rev1>promgen -u 0 "ambpex5_v20_sx50t_core_merge_chipscope" -w
Release 13.1 - Promgen O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
0x146d74 (1338740) bytes loaded up from 0x0
Using generated prom size of 2048K
Writing file "ambpex5_v20_sx50t_core_merge_chipscope.mcs".
Writing file "ambpex5_v20_sx50t_core_merge_chipscope.prm".
Writing file "ambpex5_v20_sx50t_core_merge_chipscope.cfi".
Implementation ver1->rev1: 0 error(s), 58 warning(s)
Implementation ended with warning(s).